diff --git a/[refs] b/[refs] index b60568900431..ab7075bd7207 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e0aa8afd97536a9d94f82a07b4c4b3f05aef6f82 +refs/heads/master: 40a085c41dc3d5991fdf90ed2557cc06cce0590a diff --git a/trunk/CREDITS b/trunk/CREDITS index d97e62524ddc..3b7a1548aaf9 100644 --- a/trunk/CREDITS +++ b/trunk/CREDITS @@ -1624,10 +1624,10 @@ E: ajoshi@shell.unixbox.com D: fbdev hacking N: Jesper Juhl -E: jesper.juhl@gmail.com -D: Various fixes, cleanups and minor features. +E: juhl-lkml@dif.dk +D: Various small janitor fixes, cleanups etc. S: Lemnosvej 1, 3.tv -S: 2300 Copenhagen S. +S: 2300 Copenhagen S S: Denmark N: Jozsef Kadlecsik diff --git a/trunk/Documentation/Changes b/trunk/Documentation/Changes index 5eaab0441d76..dfec7569d450 100644 --- a/trunk/Documentation/Changes +++ b/trunk/Documentation/Changes @@ -65,7 +65,6 @@ o isdn4k-utils 3.1pre1 # isdnctrl 2>&1|grep version o nfs-utils 1.0.5 # showmount --version o procps 3.2.0 # ps --version o oprofile 0.9 # oprofiled --version -o udev 058 # udevinfo -V Kernel compilation ================== diff --git a/trunk/Documentation/infiniband/core_locking.txt b/trunk/Documentation/infiniband/core_locking.txt deleted file mode 100644 index e1678542279a..000000000000 --- a/trunk/Documentation/infiniband/core_locking.txt +++ /dev/null @@ -1,114 +0,0 @@ -INFINIBAND MIDLAYER LOCKING - - This guide is an attempt to make explicit the locking assumptions - made by the InfiniBand midlayer. It describes the requirements on - both low-level drivers that sit below the midlayer and upper level - protocols that use the midlayer. - -Sleeping and interrupt context - - With the following exceptions, a low-level driver implementation of - all of the methods in struct ib_device may sleep. The exceptions - are any methods from the list: - - create_ah - modify_ah - query_ah - destroy_ah - bind_mw - post_send - post_recv - poll_cq - req_notify_cq - map_phys_fmr - - which may not sleep and must be callable from any context. - - The corresponding functions exported to upper level protocol - consumers: - - ib_create_ah - ib_modify_ah - ib_query_ah - ib_destroy_ah - ib_bind_mw - ib_post_send - ib_post_recv - ib_req_notify_cq - ib_map_phys_fmr - - are therefore safe to call from any context. - - In addition, the function - - ib_dispatch_event - - used by low-level drivers to dispatch asynchronous events through - the midlayer is also safe to call from any context. - -Reentrancy - - All of the methods in struct ib_device exported by a low-level - driver must be fully reentrant. The low-level driver is required to - perform all synchronization necessary to maintain consistency, even - if multiple function calls using the same object are run - simultaneously. - - The IB midlayer does not perform any serialization of function calls. - - Because low-level drivers are reentrant, upper level protocol - consumers are not required to perform any serialization. However, - some serialization may be required to get sensible results. For - example, a consumer may safely call ib_poll_cq() on multiple CPUs - simultaneously. However, the ordering of the work completion - information between different calls of ib_poll_cq() is not defined. - -Callbacks - - A low-level driver must not perform a callback directly from the - same callchain as an ib_device method call. For example, it is not - allowed for a low-level driver to call a consumer's completion event - handler directly from its post_send method. Instead, the low-level - driver should defer this callback by, for example, scheduling a - tasklet to perform the callback. - - The low-level driver is responsible for ensuring that multiple - completion event handlers for the same CQ are not called - simultaneously. The driver must guarantee that only one CQ event - handler for a given CQ is running at a time. In other words, the - following situation is not allowed: - - CPU1 CPU2 - - low-level driver -> - consumer CQ event callback: - /* ... */ - ib_req_notify_cq(cq, ...); - low-level driver -> - /* ... */ consumer CQ event callback: - /* ... */ - return from CQ event handler - - The context in which completion event and asynchronous event - callbacks run is not defined. Depending on the low-level driver, it - may be process context, softirq context, or interrupt context. - Upper level protocol consumers may not sleep in a callback. - -Hot-plug - - A low-level driver announces that a device is ready for use by - consumers when it calls ib_register_device(), all initialization - must be complete before this call. The device must remain usable - until the driver's call to ib_unregister_device() has returned. - - A low-level driver must call ib_register_device() and - ib_unregister_device() from process context. It must not hold any - semaphores that could cause deadlock if a consumer calls back into - the driver across these calls. - - An upper level protocol consumer may begin using an IB device as - soon as the add method of its struct ib_client is called for that - device. A consumer must finish all cleanup and free all resources - relating to a device before returning from the remove method. - - A consumer is permitted to sleep in its add and remove methods. diff --git a/trunk/Documentation/infiniband/user_mad.txt b/trunk/Documentation/infiniband/user_mad.txt index 750fe5e80ebc..cae0c83f1ee9 100644 --- a/trunk/Documentation/infiniband/user_mad.txt +++ b/trunk/Documentation/infiniband/user_mad.txt @@ -28,37 +28,13 @@ Creating MAD agents Receiving MADs - MADs are received using read(). The receive side now supports - RMPP. The buffer passed to read() must be at least one - struct ib_user_mad + 256 bytes. For example: - - If the buffer passed is not large enough to hold the received - MAD (RMPP), the errno is set to ENOSPC and the length of the - buffer needed is set in mad.length. - - Example for normal MAD (non RMPP) reads: - struct ib_user_mad *mad; - mad = malloc(sizeof *mad + 256); - ret = read(fd, mad, sizeof *mad + 256); - if (ret != sizeof mad + 256) { - perror("read"); - free(mad); - } - - Example for RMPP reads: - struct ib_user_mad *mad; - mad = malloc(sizeof *mad + 256); - ret = read(fd, mad, sizeof *mad + 256); - if (ret == -ENOSPC)) { - length = mad.length; - free(mad); - mad = malloc(sizeof *mad + length); - ret = read(fd, mad, sizeof *mad + length); - } - if (ret < 0) { + MADs are received using read(). The buffer passed to read() must be + large enough to hold at least one struct ib_user_mad. For example: + + struct ib_user_mad mad; + ret = read(fd, &mad, sizeof mad); + if (ret != sizeof mad) perror("read"); - free(mad); - } In addition to the actual MAD contents, the other struct ib_user_mad fields will be filled in with information on the received MAD. For @@ -74,21 +50,18 @@ Sending MADs MADs are sent using write(). The agent ID for sending should be filled into the id field of the MAD, the destination LID should be - filled into the lid field, and so on. The send side does support - RMPP so arbitrary length MAD can be sent. For example: - - struct ib_user_mad *mad; + filled into the lid field, and so on. For example: - mad = malloc(sizeof *mad + mad_length); + struct ib_user_mad mad; - /* fill in mad->data */ + /* fill in mad.data */ - mad->hdr.id = my_agent; /* req.id from agent registration */ - mad->hdr.lid = my_dest; /* in network byte order... */ + mad.id = my_agent; /* req.id from agent registration */ + mad.lid = my_dest; /* in network byte order... */ /* etc. */ - ret = write(fd, &mad, sizeof *mad + mad_length); - if (ret != sizeof *mad + mad_length) + ret = write(fd, &mad, sizeof mad); + if (ret != sizeof mad) perror("write"); Setting IsSM Capability Bit diff --git a/trunk/README b/trunk/README index 76dd780d88ed..0df20f07227b 100644 --- a/trunk/README +++ b/trunk/README @@ -87,16 +87,6 @@ INSTALLING the kernel: kernel source. Patches are applied from the current directory, but an alternative directory can be specified as the second argument. - - If you are upgrading between releases using the stable series patches - (for example, patch-2.6.xx.y), note that these "dot-releases" are - not incremental and must be applied to the 2.6.xx base tree. For - example, if your base kernel is 2.6.12 and you want to apply the - 2.6.12.3 patch, you do not and indeed must not first apply the - 2.6.12.1 and 2.6.12.2 patches. Similarly, if you are running kernel - version 2.6.12.2 and want to jump to 2.6.12.3, you must first - reverse the 2.6.12.2 patch (that is, patch -R) _before_ applying - the 2.6.12.3 patch. - - Make sure you have no stale .o files and dependencies lying around: cd linux diff --git a/trunk/arch/arm/lib/bitops.h b/trunk/arch/arm/lib/bitops.h index 5382a3023602..6976e60e47cb 100644 --- a/trunk/arch/arm/lib/bitops.h +++ b/trunk/arch/arm/lib/bitops.h @@ -19,9 +19,9 @@ mov r3, r2, lsl r3 @ create mask 1: ldrexb r2, [r1] ands r0, r2, r3 @ save old value of bit - \instr r2, r2, r3 @ toggle bit - strexb ip, r2, [r1] - cmp ip, #0 + \instr ip, r2, r3 @ toggle bit + strexb r2, ip, [r1] + cmp r2, #0 bne 1b cmp r0, #0 movne r0, #1 diff --git a/trunk/arch/cris/Kconfig.debug b/trunk/arch/cris/Kconfig.debug index cd72324935c4..f42918bf22a9 100644 --- a/trunk/arch/cris/Kconfig.debug +++ b/trunk/arch/cris/Kconfig.debug @@ -38,9 +38,4 @@ config FRAME_POINTER If you don't debug the kernel, you can say N, but we may not be able to solve problems without frame pointers. -config DEBUG_NMI_OOPS - bool "NMI causes oops printout" - help - If the system locks up without any debug information you can say Y - here to make it possible to dump an OOPS with an external NMI. endmenu diff --git a/trunk/arch/cris/Makefile b/trunk/arch/cris/Makefile index 90ca8730b120..9d28fa8563cc 100644 --- a/trunk/arch/cris/Makefile +++ b/trunk/arch/cris/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile,v 1.28 2005/03/17 10:44:37 larsv Exp $ +# $Id: Makefile,v 1.23 2004/10/19 13:07:34 starvik Exp $ # cris/Makefile # # This file is included by the global makefile so that you can add your own @@ -15,7 +15,6 @@ arch-y := v10 arch-$(CONFIG_ETRAX_ARCH_V10) := v10 -arch-$(CONFIG_ETRAX_ARCH_V32) := v32 # No config avaiable for make clean etc ifneq ($(arch-y),) @@ -47,21 +46,6 @@ core-y += arch/$(ARCH)/$(SARCH)/kernel/ arch/$(ARCH)/$(SARCH)/mm/ drivers-y += arch/$(ARCH)/$(SARCH)/drivers/ libs-y += arch/$(ARCH)/$(SARCH)/lib/ $(LIBGCC) -# cris source path -SRC_ARCH = $(srctree)/arch/$(ARCH) -# cris object files path -OBJ_ARCH = $(objtree)/arch/$(ARCH) - -target_boot_arch_dir = $(OBJ_ARCH)/$(SARCH)/boot -target_boot_dir = $(OBJ_ARCH)/boot -src_boot_dir = $(SRC_ARCH)/boot -target_compressed_dir = $(OBJ_ARCH)/boot/compressed -src_compressed_dir = $(SRC_ARCH)/boot/compressed -target_rescue_dir = $(OBJ_ARCH)/boot/rescue -src_rescue_dir = $(SRC_ARCH)/boot/rescue - -export target_boot_arch_dir target_boot_dir src_boot_dir target_compressed_dir src_compressed_dir target_rescue_dir src_rescue_dir - vmlinux.bin: vmlinux $(OBJCOPY) $(OBJCOPYFLAGS) vmlinux vmlinux.bin @@ -81,52 +65,44 @@ cramfs: clinux: vmlinux.bin decompress.bin rescue.bin -decompress.bin: $(target_boot_dir) - @$(MAKE) -f $(src_compressed_dir)/Makefile $(target_compressed_dir)/decompress.bin +decompress.bin: FORCE + @make -C arch/$(ARCH)/boot/compressed decompress.bin -$(target_rescue_dir)/rescue.bin: $(target_boot_dir) - @$(MAKE) -f $(src_rescue_dir)/Makefile $(target_rescue_dir)/rescue.bin +rescue.bin: FORCE + @make -C arch/$(ARCH)/boot/rescue rescue.bin -zImage: $(target_boot_dir) vmlinux.bin $(target_rescue_dir)/rescue.bin +zImage: vmlinux.bin rescue.bin ## zImage - Compressed kernel (gzip) - @$(MAKE) -f $(src_boot_dir)/Makefile zImage - -$(target_boot_dir): $(target_boot_arch_dir) - ln -sfn $< $@ - -$(target_boot_arch_dir): - mkdir -p $@ + @make -C arch/$(ARCH)/boot/ zImage compressed: zImage archmrproper: archclean: - @if [ -d arch/$(ARCH)/boot ]; then \ - $(MAKE) $(clean)=arch/$(ARCH)/boot ; \ - fi + $(Q)$(MAKE) $(clean)=arch/$(ARCH)/boot rm -f timage vmlinux.bin decompress.bin rescue.bin cramfs.img rm -rf $(LD_SCRIPT).tmp -prepare: $(SRC_ARCH)/.links $(srctree)/include/asm-$(ARCH)/.arch \ +prepare: arch/$(ARCH)/.links include/asm-$(ARCH)/.arch \ include/asm-$(ARCH)/$(SARCH)/offset.h # Create some links to make all tools happy -$(SRC_ARCH)/.links: - @rm -rf $(SRC_ARCH)/drivers - @ln -sfn $(SRC_ARCH)/$(SARCH)/drivers $(SRC_ARCH)/drivers - @rm -rf $(SRC_ARCH)/boot - @ln -sfn $(SRC_ARCH)/$(SARCH)/boot $(SRC_ARCH)/boot - @rm -rf $(SRC_ARCH)/lib - @ln -sfn $(SRC_ARCH)/$(SARCH)/lib $(SRC_ARCH)/lib - @ln -sfn $(SRC_ARCH)/$(SARCH) $(SRC_ARCH)/arch - @ln -sfn $(SRC_ARCH)/$(SARCH)/vmlinux.lds.S $(SRC_ARCH)/kernel/vmlinux.lds.S +arch/$(ARCH)/.links: + @rm -rf arch/$(ARCH)/drivers + @ln -sfn $(SARCH)/drivers arch/$(ARCH)/drivers + @rm -rf arch/$(ARCH)/boot + @ln -sfn $(SARCH)/boot arch/$(ARCH)/boot + @rm -rf arch/$(ARCH)/lib + @ln -sfn $(SARCH)/lib arch/$(ARCH)/lib + @ln -sfn $(SARCH) arch/$(ARCH)/arch + @ln -sfn ../$(SARCH)/vmlinux.lds.S arch/$(ARCH)/kernel/vmlinux.lds.S @touch $@ # Create link to sub arch includes -$(srctree)/include/asm-$(ARCH)/.arch: $(wildcard include/config/arch/*.h) - @echo ' Making $(srctree)/include/asm-$(ARCH)/arch -> $(srctree)/include/asm-$(ARCH)/$(SARCH) symlink' +include/asm-$(ARCH)/.arch: $(wildcard include/config/arch/*.h) + @echo ' Making asm-$(ARCH)/arch -> asm-$(ARCH)/$(SARCH) symlink' @rm -f include/asm-$(ARCH)/arch - @ln -sf $(srctree)/include/asm-$(ARCH)/$(SARCH) $(srctree)/include/asm-$(ARCH)/arch + @ln -sf $(SARCH) include/asm-$(ARCH)/arch @touch $@ arch/$(ARCH)/$(SARCH)/kernel/asm-offsets.s: include/asm include/linux/version.h \ diff --git a/trunk/arch/cris/arch-v10/Kconfig b/trunk/arch/cris/arch-v10/Kconfig index 44eb1b9accb3..2ca64cc40c63 100644 --- a/trunk/arch/cris/arch-v10/Kconfig +++ b/trunk/arch/cris/arch-v10/Kconfig @@ -259,37 +259,6 @@ config ETRAX_DEBUG_PORT_NULL endchoice -choice - prompt "Kernel GDB port" - depends on ETRAX_KGDB - default ETRAX_KGDB_PORT0 - help - Choose a serial port for kernel debugging. NOTE: This port should - not be enabled under Drivers for built-in interfaces (as it has its - own initialization code) and should not be the same as the debug port. - -config ETRAX_KGDB_PORT0 - bool "Serial-0" - help - Use serial port 0 for kernel debugging. - -config ETRAX_KGDB_PORT1 - bool "Serial-1" - help - Use serial port 1 for kernel debugging. - -config ETRAX_KGDB_PORT2 - bool "Serial-2" - help - Use serial port 2 for kernel debugging. - -config ETRAX_KGDB_PORT3 - bool "Serial-3" - help - Use serial port 3 for kernel debugging. - -endchoice - choice prompt "Product rescue-port" depends on ETRAX_ARCH_V10 diff --git a/trunk/arch/cris/arch-v10/boot/Makefile b/trunk/arch/cris/arch-v10/boot/Makefile index e5b105851108..fe6650368e6a 100644 --- a/trunk/arch/cris/arch-v10/boot/Makefile +++ b/trunk/arch/cris/arch-v10/boot/Makefile @@ -1,13 +1,12 @@ # # arch/cris/boot/Makefile # -target = $(target_boot_dir) -src = $(src_boot_dir) zImage: compressed/vmlinuz -compressed/vmlinuz: - @$(MAKE) -f $(src)/compressed/Makefile $(target_compressed_dir)/vmlinuz +compressed/vmlinuz: $(TOPDIR)/vmlinux + @$(MAKE) -C compressed vmlinuz clean: - @$(MAKE) -f $(src)/compressed/Makefile clean + rm -f zImage tools/build compressed/vmlinux.out + @$(MAKE) -C compressed clean diff --git a/trunk/arch/cris/arch-v10/boot/compressed/Makefile b/trunk/arch/cris/arch-v10/boot/compressed/Makefile index 6584a44820f4..5f71c2c819e6 100644 --- a/trunk/arch/cris/arch-v10/boot/compressed/Makefile +++ b/trunk/arch/cris/arch-v10/boot/compressed/Makefile @@ -1,45 +1,40 @@ # -# create a compressed vmlinuz image from the binary vmlinux.bin file +# linux/arch/etrax100/boot/compressed/Makefile +# +# create a compressed vmlinux image from the original vmlinux files and romfs # -target = $(target_compressed_dir) -src = $(src_compressed_dir) -CC = gcc-cris -melf $(LINUXINCLUDE) +CC = gcc-cris -melf -I $(TOPDIR)/include CFLAGS = -O2 LD = ld-cris OBJCOPY = objcopy-cris OBJCOPYFLAGS = -O binary --remove-section=.bss -OBJECTS = $(target)/head.o $(target)/misc.o +OBJECTS = head.o misc.o # files to compress -SYSTEM = $(objtree)/vmlinux.bin +SYSTEM = $(TOPDIR)/vmlinux.bin -all: $(target_compressed_dir)/vmlinuz +all: vmlinuz -$(target)/decompress.bin: $(OBJECTS) - $(LD) -T $(src)/decompress.ld -o $(target)/decompress.o $(OBJECTS) - $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/decompress.o $(target)/decompress.bin +decompress.bin: $(OBJECTS) + $(LD) -T decompress.ld -o decompress.o $(OBJECTS) + $(OBJCOPY) $(OBJCOPYFLAGS) decompress.o decompress.bin +# save it for mkprod in the topdir. + cp decompress.bin $(TOPDIR) -# Create vmlinuz image in top-level build directory -$(target_compressed_dir)/vmlinuz: $(target) piggy.img $(target)/decompress.bin - @echo " COMPR vmlinux.bin --> vmlinuz" - @cat $(target)/decompress.bin piggy.img > $(target_compressed_dir)/vmlinuz - @rm -f piggy.img -$(target)/head.o: $(src)/head.S - $(CC) -D__ASSEMBLY__ -traditional -c $< -o $@ +vmlinuz: piggy.img decompress.bin + cat decompress.bin piggy.img > vmlinuz + rm -f piggy.img -$(target)/misc.o: $(src)/misc.c - $(CC) -D__KERNEL__ -c $< -o $@ +head.o: head.S + $(CC) -D__ASSEMBLY__ -traditional -c head.S -o head.o # gzip the kernel image piggy.img: $(SYSTEM) - @cat $(SYSTEM) | gzip -f -9 > piggy.img - -$(target): - mkdir -p $(target) + cat $(SYSTEM) | gzip -f -9 > piggy.img clean: - rm -f piggy.img $(objtree)/vmlinuz + rm -f piggy.img vmlinuz vmlinuz.o diff --git a/trunk/arch/cris/arch-v10/boot/compressed/head.S b/trunk/arch/cris/arch-v10/boot/compressed/head.S index e73f44c998d9..4cbdd4b1d9d6 100644 --- a/trunk/arch/cris/arch-v10/boot/compressed/head.S +++ b/trunk/arch/cris/arch-v10/boot/compressed/head.S @@ -13,8 +13,7 @@ #include #define RAM_INIT_MAGIC 0x56902387 -#define COMMAND_LINE_MAGIC 0x87109563 - + ;; Exported symbols .globl _input_data @@ -89,12 +88,6 @@ basse: move.d pc, r5 cmp.d r2, r1 bcs 1b nop - - ;; Save command line magic and address. - move.d _cmd_line_magic, $r12 - move.d $r10, [$r12] - move.d _cmd_line_addr, $r12 - move.d $r11, [$r12] ;; Do the decompression and save compressed size in _inptr @@ -105,13 +98,7 @@ basse: move.d pc, r5 move.d [_input_data], r9 ; flash address of compressed kernel add.d [_inptr], r9 ; size of compressed kernel - - ;; Restore command line magic and address. - move.d _cmd_line_magic, $r10 - move.d [$r10], $r10 - move.d _cmd_line_addr, $r11 - move.d [$r11], $r11 - + ;; Enter the decompressed kernel move.d RAM_INIT_MAGIC, r8 ; Tell kernel that DRAM is initialized jump 0x40004000 ; kernel is linked to this address @@ -120,8 +107,5 @@ basse: move.d pc, r5 _input_data: .dword 0 ; used by the decompressor -_cmd_line_magic: - .dword 0 -_cmd_line_addr: - .dword 0 + #include "../../lib/hw_settings.S" diff --git a/trunk/arch/cris/arch-v10/boot/rescue/Makefile b/trunk/arch/cris/arch-v10/boot/rescue/Makefile index 8be9b3130312..e9f2ba2ad02c 100644 --- a/trunk/arch/cris/arch-v10/boot/rescue/Makefile +++ b/trunk/arch/cris/arch-v10/boot/rescue/Makefile @@ -1,53 +1,52 @@ # # Makefile for rescue code # -target = $(target_rescue_dir) -src = $(src_rescue_dir) - -CC = gcc-cris -mlinux $(LINUXINCLUDE) +ifndef TOPDIR +TOPDIR = ../../../.. +endif +CC = gcc-cris -mlinux -I $(TOPDIR)/include CFLAGS = -O2 LD = gcc-cris -mlinux -nostdlib OBJCOPY = objcopy-cris OBJCOPYFLAGS = -O binary --remove-section=.bss -all: $(target)/rescue.bin $(target)/testrescue.bin $(target)/kimagerescue.bin +all: rescue.bin testrescue.bin kimagerescue.bin + +rescue: rescue.bin + # do nothing -$(target)/rescue.bin: $(target) $(target)/head.o - $(LD) -T $(src)/rescue.ld -o $(target)/rescue.o $(target)/head.o - $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/rescue.o $(target)/rescue.bin -# Place a copy in top-level build directory - cp -p $(target)/rescue.bin $(objtree) +rescue.bin: head.o + $(LD) -T rescue.ld -o rescue.o head.o + $(OBJCOPY) $(OBJCOPYFLAGS) rescue.o rescue.bin + cp rescue.bin $(TOPDIR) -$(target)/testrescue.bin: $(target) $(target)/testrescue.o - $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/testrescue.o tr.bin +testrescue.bin: testrescue.o + $(OBJCOPY) $(OBJCOPYFLAGS) testrescue.o tr.bin # Pad it to 784 bytes dd if=/dev/zero of=tmp2423 bs=1 count=784 cat tr.bin tmp2423 >testrescue_tmp.bin - dd if=testrescue_tmp.bin of=$(target)/testrescue.bin bs=1 count=784 + dd if=testrescue_tmp.bin of=testrescue.bin bs=1 count=784 rm tr.bin tmp2423 testrescue_tmp.bin -$(target)/kimagerescue.bin: $(target) $(target)/kimagerescue.o - $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/kimagerescue.o ktr.bin +kimagerescue.bin: kimagerescue.o + $(OBJCOPY) $(OBJCOPYFLAGS) kimagerescue.o ktr.bin # Pad it to 784 bytes, that's what the rescue loader expects dd if=/dev/zero of=tmp2423 bs=1 count=784 cat ktr.bin tmp2423 >kimagerescue_tmp.bin - dd if=kimagerescue_tmp.bin of=$(target)/kimagerescue.bin bs=1 count=784 + dd if=kimagerescue_tmp.bin of=kimagerescue.bin bs=1 count=784 rm ktr.bin tmp2423 kimagerescue_tmp.bin -$(target): - mkdir -p $(target) - -$(target)/head.o: $(src)/head.S +head.o: head.S $(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o -$(target)/testrescue.o: $(src)/testrescue.S +testrescue.o: testrescue.S $(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o -$(target)/kimagerescue.o: $(src)/kimagerescue.S +kimagerescue.o: kimagerescue.S $(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o clean: - rm -f $(target)/*.o $(target)/*.bin + rm -f *.o *.bin fastdep: diff --git a/trunk/arch/cris/arch-v10/boot/rescue/head.S b/trunk/arch/cris/arch-v10/boot/rescue/head.S index addb2194de0f..8689ea972c46 100644 --- a/trunk/arch/cris/arch-v10/boot/rescue/head.S +++ b/trunk/arch/cris/arch-v10/boot/rescue/head.S @@ -1,4 +1,4 @@ -/* $Id: head.S,v 1.7 2005/03/07 12:11:06 starvik Exp $ +/* $Id: head.S,v 1.6 2003/04/09 08:12:43 pkj Exp $ * * Rescue code, made to reside at the beginning of the * flash-memory. when it starts, it checks a partition @@ -121,13 +121,12 @@ ;; 0x80000000 if loaded in flash (as it should be) ;; since etrax actually starts at address 2 when booting from flash, we ;; put a nop (2 bytes) here first so we dont accidentally skip the di - + nop di jump in_cache ; enter cached area instead -in_cache: - +in_cache: ;; first put a jump test to give a possibility of upgrading the rescue code ;; without erasing/reflashing the sector. we put a longword of -1 here and if @@ -326,29 +325,9 @@ flash_ok: ;; result will be in r0 checksum: moveq 0, $r0 - moveq CONFIG_ETRAX_FLASH1_SIZE, $r6 - - ;; If the first physical flash memory is exceeded wrap to the second one. - btstq 26, $r1 ; Are we addressing first flash? - bpl 1f - nop - clear.d $r6 - -1: test.d $r6 ; 0 = no wrapping - beq 2f - nop - lslq 20, $r6 ; Convert MB to bytes - sub.d $r1, $r6 - -2: addu.b [$r1+], $r0 - subq 1, $r6 ; Flash memory left - beq 3f - subq 1, $r2 ; Length left - bne 2b +1: addu.b [$r1+], $r0 + subq 1, $r2 + bne 1b nop ret nop - -3: move.d MEM_CSE1_START, $r1 ; wrap to second flash - ba 2b - nop diff --git a/trunk/arch/cris/arch-v10/drivers/Kconfig b/trunk/arch/cris/arch-v10/drivers/Kconfig index 8b50e8402954..748374f25b87 100644 --- a/trunk/arch/cris/arch-v10/drivers/Kconfig +++ b/trunk/arch/cris/arch-v10/drivers/Kconfig @@ -1,11 +1,17 @@ config ETRAX_ETHERNET bool "Ethernet support" depends on ETRAX_ARCH_V10 - select NET_ETHERNET help This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet controller. +# this is just so that the user does not have to go into the +# normal ethernet driver section just to enable ethernetworking +config NET_ETHERNET + bool + depends on ETRAX_ETHERNET + default y + choice prompt "Network LED behavior" depends on ETRAX_ETHERNET @@ -14,26 +20,26 @@ choice config ETRAX_NETWORK_LED_ON_WHEN_LINK bool "LED_on_when_link" help - Selecting LED_on_when_link will light the LED when there is a - connection and will flash off when there is activity. + Selecting LED_on_when_link will light the LED when there is a + connection and will flash off when there is activity. - Selecting LED_on_when_activity will light the LED only when + Selecting LED_on_when_activity will light the LED only when there is activity. - This setting will also affect the behaviour of other activity LEDs - e.g. Bluetooth. + This setting will also affect the behaviour of other activity LEDs + e.g. Bluetooth. config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY bool "LED_on_when_activity" help - Selecting LED_on_when_link will light the LED when there is a - connection and will flash off when there is activity. + Selecting LED_on_when_link will light the LED when there is a + connection and will flash off when there is activity. - Selecting LED_on_when_activity will light the LED only when + Selecting LED_on_when_activity will light the LED only when there is activity. - This setting will also affect the behaviour of other activity LEDs - e.g. Bluetooth. + This setting will also affect the behaviour of other activity LEDs + e.g. Bluetooth. endchoice @@ -85,11 +91,11 @@ choice depends on ETRAX_SERIAL_PORT0 default ETRAX_SERIAL_PORT0_DMA6_OUT -config ETRAX_SERIAL_PORT0_NO_DMA_OUT - bool "No DMA out" +config CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_OUT + bool "No DMA out" -config ETRAX_SERIAL_PORT0_DMA6_OUT - bool "DMA 6" +config CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT + bool "DMA 6" endchoice @@ -98,11 +104,11 @@ choice depends on ETRAX_SERIAL_PORT0 default ETRAX_SERIAL_PORT0_DMA7_IN -config ETRAX_SERIAL_PORT0_NO_DMA_IN - bool "No DMA in" +config CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_IN + bool "No DMA in" -config ETRAX_SERIAL_PORT0_DMA7_IN - bool "DMA 7" +config CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN + bool "DMA 7" endchoice @@ -199,11 +205,11 @@ choice depends on ETRAX_SERIAL_PORT1 default ETRAX_SERIAL_PORT1_DMA8_OUT -config ETRAX_SERIAL_PORT1_NO_DMA_OUT - bool "No DMA out" +config CONFIG_ETRAX_SERIAL_PORT1_NO_DMA_OUT + bool "No DMA out" -config ETRAX_SERIAL_PORT1_DMA8_OUT - bool "DMA 8" +config CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT + bool "DMA 8" endchoice @@ -212,11 +218,11 @@ choice depends on ETRAX_SERIAL_PORT1 default ETRAX_SERIAL_PORT1_DMA9_IN -config ETRAX_SERIAL_PORT1_NO_DMA_IN - bool "No DMA in" +config CONFIG_ETRAX_SERIAL_PORT1_NO_DMA_IN + bool "No DMA in" -config ETRAX_SERIAL_PORT1_DMA9_IN - bool "DMA 9" +config CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN + bool "DMA 9" endchoice @@ -302,7 +308,7 @@ config ETRAX_SER1_CD_ON_PB_BIT Specify the pin of the PB port to carry the CD signal for serial port 1. -comment "Make sure you do not have the same PB bits more than once!" +comment "Make sure you dont have the same PB bits more than once!" depends on ETRAX_SERIAL && ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && ETRAX_SER1_DTR_RI_DSR_CD_ON_PB config ETRAX_SERIAL_PORT2 @@ -316,11 +322,11 @@ choice depends on ETRAX_SERIAL_PORT2 default ETRAX_SERIAL_PORT2_DMA2_OUT -config ETRAX_SERIAL_PORT2_NO_DMA_OUT - bool "No DMA out" +config CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_OUT + bool "No DMA out" -config ETRAX_SERIAL_PORT2_DMA2_OUT - bool "DMA 2" +config CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT + bool "DMA 2" endchoice @@ -329,11 +335,11 @@ choice depends on ETRAX_SERIAL_PORT2 default ETRAX_SERIAL_PORT2_DMA3_IN -config ETRAX_SERIAL_PORT2_NO_DMA_IN - bool "No DMA in" +config CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_IN + bool "No DMA in" -config ETRAX_SERIAL_PORT2_DMA3_IN - bool "DMA 3" +config CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN + bool "DMA 3" endchoice @@ -430,11 +436,11 @@ choice depends on ETRAX_SERIAL_PORT3 default ETRAX_SERIAL_PORT3_DMA4_OUT -config ETRAX_SERIAL_PORT3_NO_DMA_OUT - bool "No DMA out" +config CONFIG_ETRAX_SERIAL_PORT3_NO_DMA_OUT + bool "No DMA out" -config ETRAX_SERIAL_PORT3_DMA4_OUT - bool "DMA 4" +config CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT + bool "DMA 4" endchoice @@ -443,11 +449,11 @@ choice depends on ETRAX_SERIAL_PORT3 default ETRAX_SERIAL_PORT3_DMA5_IN -config ETRAX_SERIAL_PORT3_NO_DMA_IN - bool "No DMA in" +config CONFIG_ETRAX_SERIAL_PORT3_NO_DMA_IN + bool "No DMA in" -config ETRAX_SERIAL_PORT3_DMA5_IN - bool "DMA 5" +config CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN + bool "DMA 5" endchoice @@ -548,6 +554,7 @@ config ETRAX_IDE select BLK_DEV_IDEDISK select BLK_DEV_IDECD select BLK_DEV_IDEDMA + select DMA_NONPCI help Enable this to get support for ATA/IDE. You can't use paralell ports or SCSI ports @@ -572,7 +579,7 @@ config ETRAX_IDE_PB7_RESET IDE reset on pin 7 on port B config ETRAX_IDE_G27_RESET - bool "Port_G_Bit_27" + bool "Port_G_Bit_27" help IDE reset on pin 27 on port G @@ -581,36 +588,30 @@ endchoice config ETRAX_USB_HOST bool "USB host" - select USB help This option enables the host functionality of the ETRAX 100LX built-in USB controller. In host mode the controller is designed for CTRL and BULK traffic only, INTR traffic may work as well however (depending on the requirements of timeliness). +config USB + tristate + depends on ETRAX_USB_HOST + default y + config ETRAX_USB_HOST_PORT1 - bool "USB port 1 enabled" - depends on ETRAX_USB_HOST - default n + bool " USB port 1 enabled" + depends on ETRAX_USB_HOST + default n config ETRAX_USB_HOST_PORT2 - bool "USB port 2 enabled" - depends on ETRAX_USB_HOST - default n + bool " USB port 2 enabled" + depends on ETRAX_USB_HOST + default n config ETRAX_AXISFLASHMAP bool "Axis flash-map support" depends on ETRAX_ARCH_V10 - select MTD - select MTD_CFI - select MTD_CFI_AMDSTD - select MTD_OBSOLETE_CHIPS - select MTD_AMDSTD - select MTD_CHAR - select MTD_BLOCK - select MTD_PARTITIONS - select MTD_CONCAT - select MTD_COMPLEX_MAPPINGS help This option enables MTD mapping of flash devices. Needed to use flash memories. If unsure, say Y. @@ -626,6 +627,119 @@ config ETRAX_PTABLE_SECTOR for changing this is when the flash block size is bigger than 64kB (e.g. when using two parallel 16 bit flashes). +# here we define the CONFIG_'s necessary to enable MTD support +# for the flash +config MTD + tristate + depends on ETRAX_AXISFLASHMAP + default y + help + Memory Technology Devices are flash, RAM and similar chips, often + used for solid state file systems on embedded devices. This option + will provide the generic support for MTD drivers to register + themselves with the kernel and for potential users of MTD devices + to enumerate the devices which are present and obtain a handle on + them. It will also allow you to select individual drivers for + particular hardware and users of MTD devices. If unsure, say N. + +config MTD_CFI + tristate + depends on ETRAX_AXISFLASHMAP + default y + help + The Common Flash Interface specification was developed by Intel, + AMD and other flash manufactures that provides a universal method + for probing the capabilities of flash devices. If you wish to + support any device that is CFI-compliant, you need to enable this + option. Visit + for more information on CFI. + +config MTD_CFI_AMDSTD + tristate + depends on ETRAX_AXISFLASHMAP + default y + help + The Common Flash Interface defines a number of different command + sets which a CFI-compliant chip may claim to implement. This code + provides support for one of those command sets, used on chips + chips including the AMD Am29LV320. + +config MTD_OBSOLETE_CHIPS + bool + depends on ETRAX_AXISFLASHMAP + default y + help + This option does not enable any code directly, but will allow you to + select some other chip drivers which are now considered obsolete, + because the generic CONFIG_JEDEC_PROBE code above should now detect + the chips which are supported by these drivers, and allow the generic + CFI-compatible drivers to drive the chips. Say 'N' here unless you have + already tried the CONFIG_JEDEC_PROBE method and reported its failure + to the MTD mailing list at + +config MTD_AMDSTD + tristate + depends on ETRAX_AXISFLASHMAP + default y + help + This option enables support for flash chips using AMD-compatible + commands, including some which are not CFI-compatible and hence + cannot be used with the CONFIG_MTD_CFI_AMDSTD option. + + It also works on AMD compatible chips that do conform to CFI. + +config MTD_CHAR + tristate + depends on ETRAX_AXISFLASHMAP + default y + help + This provides a character device for each MTD device present in + the system, allowing the user to read and write directly to the + memory chips, and also use ioctl() to obtain information about + the device, or to erase parts of it. + +config MTD_BLOCK + tristate + depends on ETRAX_AXISFLASHMAP + default y + ---help--- + Although most flash chips have an erase size too large to be useful + as block devices, it is possible to use MTD devices which are based + on RAM chips in this manner. This block device is a user of MTD + devices performing that function. + + At the moment, it is also required for the Journalling Flash File + System(s) to obtain a handle on the MTD device when it's mounted + (although JFFS and JFFS2 don't actually use any of the functionality + of the mtdblock device). + + Later, it may be extended to perform read/erase/modify/write cycles + on flash chips to emulate a smaller block size. Needless to say, + this is very unsafe, but could be useful for file systems which are + almost never written to. + + You do not need this option for use with the DiskOnChip devices. For + those, enable NFTL support (CONFIG_NFTL) instead. + +config MTD_PARTITIONS + tristate + depends on ETRAX_AXISFLASHMAP + default y + help + If you have a device which needs to divide its flash chip(s) up + into multiple 'partitions', each of which appears to the user as + a separate MTD device, you require this option to be enabled. If + unsure, say 'Y'. + + Note, however, that you don't need this option for the DiskOnChip + devices. Partitioning on NFTL 'devices' is a different - that's the + 'normal' form of partitioning used on a block device. + +config MTD_CONCAT + tristate + depends on ETRAX_AXISFLASHMAP + default y + config ETRAX_I2C bool "I2C support" depends on ETRAX_ARCH_V10 @@ -638,7 +752,7 @@ config ETRAX_I2C val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); # this is true for most products since PB-I2C seems to be somewhat -# flawed.. +# flawed.. config ETRAX_I2C_USES_PB_NOT_PB_I2C bool "I2C uses PB not PB-I2C" depends on ETRAX_I2C @@ -772,7 +886,7 @@ config ETRAX_RTC bool "Real Time Clock support" depends on ETRAX_ARCH_V10 help - Enables drivers for the Real-Time Clock battery-backed chips on + Enables drivers for the Real-Time Clock battery-backed chips on some products. The kernel reads the time when booting, and the date can be set using ioctl(fd, RTC_SET_TIME, &rt) with rt a rtc_time struct (see ) on the /dev/rtc @@ -789,13 +903,13 @@ config ETRAX_DS1302 bool "DS1302" help Enables the driver for the DS1302 Real-Time Clock battery-backed - chip on some products. + chip on some products. config ETRAX_PCF8563 bool "PCF8563" help Enables the driver for the PCF8563 Real-Time Clock battery-backed - chip on some products. + chip on some products. endchoice @@ -840,8 +954,10 @@ config ETRAX_DS1302_TRICKLE_CHARGE help This controls the initial value of the trickle charge register. 0 = disabled (use this if you are unsure or have a non rechargable battery) - Otherwise the following values can be OR:ed together to control the + Otherwise the following values can be OR:ed together to control the charge current: 1 = 2kohm, 2 = 4kohm, 3 = 4kohm 4 = 1 diode, 8 = 2 diodes Allowed values are (increasing current): 0, 11, 10, 9, 7, 6, 5 + + diff --git a/trunk/arch/cris/arch-v10/drivers/axisflashmap.c b/trunk/arch/cris/arch-v10/drivers/axisflashmap.c index 11ab3836aac6..fb7d4855ea62 100644 --- a/trunk/arch/cris/arch-v10/drivers/axisflashmap.c +++ b/trunk/arch/cris/arch-v10/drivers/axisflashmap.c @@ -11,9 +11,6 @@ * partition split defined below. * * $Log: axisflashmap.c,v $ - * Revision 1.11 2004/11/15 10:27:14 starvik - * Corrected typo (Thanks to Milton Miller ). - * * Revision 1.10 2004/08/16 12:37:22 starvik * Merge of Linux 2.6.8 * @@ -164,7 +161,7 @@ #elif CONFIG_ETRAX_FLASH_BUSWIDTH==2 #define flash_data __u16 #elif CONFIG_ETRAX_FLASH_BUSWIDTH==4 -#define flash_data __u32 +#define flash_data __u16 #endif /* From head.S */ diff --git a/trunk/arch/cris/arch-v10/drivers/ds1302.c b/trunk/arch/cris/arch-v10/drivers/ds1302.c index 10795f67f687..fba530fcfaeb 100644 --- a/trunk/arch/cris/arch-v10/drivers/ds1302.c +++ b/trunk/arch/cris/arch-v10/drivers/ds1302.c @@ -7,15 +7,6 @@ *! Functions exported: ds1302_readreg, ds1302_writereg, ds1302_init *! *! $Log: ds1302.c,v $ -*! Revision 1.18 2005/01/24 09:11:26 mikaelam -*! Minor changes to get DS1302 RTC chip driver to work -*! -*! Revision 1.17 2005/01/05 06:11:22 starvik -*! No need to do local_irq_disable after local_irq_save. -*! -*! Revision 1.16 2004/12/13 12:21:52 starvik -*! Added I/O and DMA allocators from Linux 2.4 -*! *! Revision 1.14 2004/08/24 06:48:43 starvik *! Whitespace cleanup *! @@ -133,9 +124,9 @@ *! *! --------------------------------------------------------------------------- *! -*! (C) Copyright 1999, 2000, 2001, 2002, 2003, 2004 Axis Communications AB, LUND, SWEDEN +*! (C) Copyright 1999, 2000, 2001 Axis Communications AB, LUND, SWEDEN *! -*! $Id: ds1302.c,v 1.18 2005/01/24 09:11:26 mikaelam Exp $ +*! $Id: ds1302.c,v 1.14 2004/08/24 06:48:43 starvik Exp $ *! *!***************************************************************************/ @@ -154,7 +145,6 @@ #include #include #include -#include #define RTC_MAJOR_NR 121 /* local major, change later */ @@ -330,6 +320,7 @@ get_rtc_time(struct rtc_time *rtc_tm) unsigned long flags; local_irq_save(flags); + local_irq_disable(); rtc_tm->tm_sec = CMOS_READ(RTC_SECONDS); rtc_tm->tm_min = CMOS_READ(RTC_MINUTES); @@ -367,7 +358,7 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) { - unsigned long flags; + unsigned long flags; switch(cmd) { case RTC_RD_TIME: /* read the time/date from RTC */ @@ -391,7 +382,7 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, return -EPERM; if (copy_from_user(&rtc_tm, (struct rtc_time*)arg, sizeof(struct rtc_time))) - return -EFAULT; + return -EFAULT; yrs = rtc_tm.tm_year + 1900; mon = rtc_tm.tm_mon + 1; /* tm_mon starts at zero */ @@ -428,6 +419,7 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, BIN_TO_BCD(yrs); local_irq_save(flags); + local_irq_disable(); CMOS_WRITE(yrs, RTC_YEAR); CMOS_WRITE(mon, RTC_MONTH); CMOS_WRITE(day, RTC_DAY_OF_MONTH); @@ -446,7 +438,7 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, case RTC_SET_CHARGE: /* set the RTC TRICKLE CHARGE register */ { - int tcs_val; + int tcs_val; if (!capable(CAP_SYS_TIME)) return -EPERM; @@ -500,8 +492,8 @@ print_rtc_status(void) /* The various file operations we support. */ static struct file_operations rtc_fops = { - .owner = THIS_MODULE, - .ioctl = rtc_ioctl, + .owner = THIS_MODULE, + .ioctl = rtc_ioctl, }; /* Probe for the chip by writing something to its RAM and try reading it back. */ @@ -540,7 +532,7 @@ ds1302_probe(void) "PB", #endif CONFIG_ETRAX_DS1302_RSTBIT); - print_rtc_status(); + print_rtc_status(); retval = 1; } else { stop(); @@ -556,9 +548,7 @@ ds1302_probe(void) int __init ds1302_init(void) { -#ifdef CONFIG_ETRAX_I2C i2c_init(); -#endif if (!ds1302_probe()) { #ifdef CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT @@ -568,42 +558,25 @@ ds1302_init(void) * * Make sure that R_GEN_CONFIG is setup correct. */ - /* Allocating the ATA interface will grab almost all - * pins in I/O groups a, b, c and d. A consequence of - * allocating the ATA interface is that the fixed - * interfaces shared RAM, parallel port 0, parallel - * port 1, parallel port W, SCSI-8 port 0, SCSI-8 port - * 1, SCSI-W, serial port 2, serial port 3, - * synchronous serial port 3 and USB port 2 and almost - * all GPIO pins on port g cannot be used. - */ - if (cris_request_io_interface(if_ata, "ds1302/ATA")) { - printk(KERN_WARNING "ds1302: Failed to get IO interface\n"); - return -1; - } - + genconfig_shadow = ((genconfig_shadow & + ~IO_MASK(R_GEN_CONFIG, ata)) | + (IO_STATE(R_GEN_CONFIG, ata, select))); + *R_GEN_CONFIG = genconfig_shadow; #elif CONFIG_ETRAX_DS1302_RSTBIT == 0 - if (cris_io_interface_allocate_pins(if_gpio_grp_a, - 'g', - CONFIG_ETRAX_DS1302_RSTBIT, - CONFIG_ETRAX_DS1302_RSTBIT)) { - printk(KERN_WARNING "ds1302: Failed to get IO interface\n"); - return -1; - } - - /* Set the direction of this bit to out. */ - genconfig_shadow = ((genconfig_shadow & - ~IO_MASK(R_GEN_CONFIG, g0dir)) | - (IO_STATE(R_GEN_CONFIG, g0dir, out))); - *R_GEN_CONFIG = genconfig_shadow; + + /* Set the direction of this bit to out. */ + genconfig_shadow = ((genconfig_shadow & + ~IO_MASK(R_GEN_CONFIG, g0dir)) | + (IO_STATE(R_GEN_CONFIG, g0dir, out))); + *R_GEN_CONFIG = genconfig_shadow; #endif if (!ds1302_probe()) { printk(KERN_WARNING "%s: RTC not found.\n", ds1302_name); - return -1; + return -1; } #else printk(KERN_WARNING "%s: RTC not found.\n", ds1302_name); - return -1; + return -1; #endif } /* Initialise trickle charger */ diff --git a/trunk/arch/cris/arch-v10/drivers/eeprom.c b/trunk/arch/cris/arch-v10/drivers/eeprom.c index 512f16dec060..316ca15d6802 100644 --- a/trunk/arch/cris/arch-v10/drivers/eeprom.c +++ b/trunk/arch/cris/arch-v10/drivers/eeprom.c @@ -20,12 +20,6 @@ *! in the spin-lock. *! *! $Log: eeprom.c,v $ -*! Revision 1.12 2005/06/19 17:06:46 starvik -*! Merge of Linux 2.6.12. -*! -*! Revision 1.11 2005/01/26 07:14:46 starvik -*! Applied diff from kernel janitors (Nish Aravamudan). -*! *! Revision 1.10 2003/09/11 07:29:48 starvik *! Merge of Linux 2.6.0-test5 *! @@ -100,7 +94,6 @@ #include #include #include -#include #include #include "i2c.h" @@ -533,10 +526,15 @@ static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t return -EFAULT; } - wait_event_interruptible(eeprom.wait_q, !eeprom.busy); - if (signal_pending(current)) - return -EINTR; + while(eeprom.busy) + { + interruptible_sleep_on(&eeprom.wait_q); + /* bail out if we get interrupted */ + if (signal_pending(current)) + return -EINTR; + + } eeprom.busy++; page = (unsigned char) (p >> 8); @@ -606,10 +604,13 @@ static ssize_t eeprom_write(struct file * file, const char * buf, size_t count, return -EFAULT; } - wait_event_interruptible(eeprom.wait_q, !eeprom.busy); - /* bail out if we get interrupted */ - if (signal_pending(current)) - return -EINTR; + while(eeprom.busy) + { + interruptible_sleep_on(&eeprom.wait_q); + /* bail out if we get interrupted */ + if (signal_pending(current)) + return -EINTR; + } eeprom.busy++; for(i = 0; (i < EEPROM_RETRIES) && (restart > 0); i++) { diff --git a/trunk/arch/cris/arch-v10/drivers/gpio.c b/trunk/arch/cris/arch-v10/drivers/gpio.c index 09963fe299a7..c095de82a0da 100644 --- a/trunk/arch/cris/arch-v10/drivers/gpio.c +++ b/trunk/arch/cris/arch-v10/drivers/gpio.c @@ -1,4 +1,4 @@ -/* $Id: gpio.c,v 1.17 2005/06/19 17:06:46 starvik Exp $ +/* $Id: gpio.c,v 1.12 2004/08/24 07:19:59 starvik Exp $ * * Etrax general port I/O device * @@ -9,18 +9,6 @@ * Johan Adolfsson (read/set directions, write, port G) * * $Log: gpio.c,v $ - * Revision 1.17 2005/06/19 17:06:46 starvik - * Merge of Linux 2.6.12. - * - * Revision 1.16 2005/03/07 13:02:29 starvik - * Protect driver global states with spinlock - * - * Revision 1.15 2005/01/05 06:08:55 starvik - * No need to do local_irq_disable after local_irq_save. - * - * Revision 1.14 2004/12/13 12:21:52 starvik - * Added I/O and DMA allocators from Linux 2.4 - * * Revision 1.12 2004/08/24 07:19:59 starvik * Whitespace cleanup * @@ -154,7 +142,6 @@ #include #include #include -#include #define GPIO_MAJOR 120 /* experimental MAJOR number */ @@ -207,8 +194,6 @@ static struct gpio_private *alarmlist = 0; static int gpio_some_alarms = 0; /* Set if someone uses alarm */ static unsigned long gpio_pa_irq_enabled_mask = 0; -static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */ - /* Port A and B use 8 bit access, but Port G is 32 bit */ #define NUM_PORTS (GPIO_MINOR_B+1) @@ -256,9 +241,6 @@ static volatile unsigned char *dir_shadow[NUM_PORTS] = { &port_pb_dir_shadow }; -/* All bits in port g that can change dir. */ -static const unsigned long int changeable_dir_g_mask = 0x01FFFF01; - /* Port G is 32 bit, handle it special, some bits are both inputs and outputs at the same time, only some of the bits can change direction and some of them in groups of 8 bit. */ @@ -278,7 +260,6 @@ gpio_poll(struct file *file, unsigned int mask = 0; struct gpio_private *priv = (struct gpio_private *)file->private_data; unsigned long data; - spin_lock(&gpio_lock); poll_wait(file, &priv->alarm_wq, wait); if (priv->minor == GPIO_MINOR_A) { unsigned long flags; @@ -289,10 +270,10 @@ gpio_poll(struct file *file, */ tmp = ~data & priv->highalarm & 0xFF; tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR); - local_irq_save(flags); + save_flags(flags); cli(); gpio_pa_irq_enabled_mask |= tmp; *R_IRQ_MASK1_SET = tmp; - local_irq_restore(flags); + restore_flags(flags); } else if (priv->minor == GPIO_MINOR_B) data = *R_PORT_PB_DATA; @@ -305,11 +286,8 @@ gpio_poll(struct file *file, (~data & priv->lowalarm)) { mask = POLLIN|POLLRDNORM; } - - spin_unlock(&gpio_lock); DP(printk("gpio_poll ready: mask 0x%08X\n", mask)); - return mask; } @@ -318,7 +296,6 @@ int etrax_gpio_wake_up_check(void) struct gpio_private *priv = alarmlist; unsigned long data = 0; int ret = 0; - spin_lock(&gpio_lock); while (priv) { if (USE_PORTS(priv)) { data = *priv->port; @@ -333,7 +310,6 @@ int etrax_gpio_wake_up_check(void) } priv = priv->next; } - spin_unlock(&gpio_lock); return ret; } @@ -351,7 +327,6 @@ static irqreturn_t gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs) { unsigned long tmp; - spin_lock(&gpio_lock); /* Find what PA interrupts are active */ tmp = (*R_IRQ_READ1); @@ -362,8 +337,6 @@ gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs) *R_IRQ_MASK1_CLR = tmp; gpio_pa_irq_enabled_mask &= ~tmp; - spin_unlock(&gpio_lock); - if (gpio_some_alarms) { return IRQ_RETVAL(etrax_gpio_wake_up_check()); } @@ -377,9 +350,6 @@ static ssize_t gpio_write(struct file * file, const char * buf, size_t count, struct gpio_private *priv = (struct gpio_private *)file->private_data; unsigned char data, clk_mask, data_mask, write_msb; unsigned long flags; - - spin_lock(&gpio_lock); - ssize_t retval = count; if (priv->minor !=GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) { return -EFAULT; @@ -402,7 +372,7 @@ static ssize_t gpio_write(struct file * file, const char * buf, size_t count, data = *buf++; if (priv->write_msb) { for (i = 7; i >= 0;i--) { - local_irq_save(flags); + local_irq_save(flags); local_irq_disable(); *priv->port = *priv->shadow &= ~clk_mask; if (data & 1<port = *priv->shadow |= data_mask; @@ -414,7 +384,7 @@ static ssize_t gpio_write(struct file * file, const char * buf, size_t count, } } else { for (i = 0; i <= 7;i++) { - local_irq_save(flags); + local_irq_save(flags); local_irq_disable(); *priv->port = *priv->shadow &= ~clk_mask; if (data & 1<port = *priv->shadow |= data_mask; @@ -426,7 +396,6 @@ static ssize_t gpio_write(struct file * file, const char * buf, size_t count, } } } - spin_unlock(&gpio_lock); return retval; } @@ -483,14 +452,9 @@ gpio_open(struct inode *inode, struct file *filp) static int gpio_release(struct inode *inode, struct file *filp) { - struct gpio_private *p; - struct gpio_private *todel; - - spin_lock(&gpio_lock); - - p = alarmlist; - todel = (struct gpio_private *)filp->private_data; - + struct gpio_private *p = alarmlist; + struct gpio_private *todel = (struct gpio_private *)filp->private_data; + /* unlink from alarmlist and free the private structure */ if (p == todel) { @@ -512,7 +476,7 @@ gpio_release(struct inode *inode, struct file *filp) p = p->next; } gpio_some_alarms = 0; - spin_unlock(&gpio_lock); + return 0; } @@ -527,14 +491,14 @@ unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg) */ unsigned long flags; if (USE_PORTS(priv)) { - local_irq_save(flags); + local_irq_save(flags); local_irq_disable(); *priv->dir = *priv->dir_shadow &= ~((unsigned char)arg & priv->changeable_dir); local_irq_restore(flags); return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */ } else if (priv->minor == GPIO_MINOR_G) { /* We must fiddle with R_GEN_CONFIG to change dir */ - local_irq_save(flags); + save_flags(flags); cli(); if (((arg & dir_g_in_bits) != arg) && (arg & changeable_dir_g)) { arg &= changeable_dir_g; @@ -569,7 +533,7 @@ unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg) /* Must be a >120 ns delay before writing this again */ } - local_irq_restore(flags); + restore_flags(flags); return dir_g_in_bits; } return 0; @@ -579,14 +543,14 @@ unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg) { unsigned long flags; if (USE_PORTS(priv)) { - local_irq_save(flags); + local_irq_save(flags); local_irq_disable(); *priv->dir = *priv->dir_shadow |= ((unsigned char)arg & priv->changeable_dir); local_irq_restore(flags); return *priv->dir_shadow; } else if (priv->minor == GPIO_MINOR_G) { /* We must fiddle with R_GEN_CONFIG to change dir */ - local_irq_save(flags); + save_flags(flags); cli(); if (((arg & dir_g_out_bits) != arg) && (arg & changeable_dir_g)) { /* Set bits in genconfig to set to output */ @@ -619,7 +583,7 @@ unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg) *R_GEN_CONFIG = genconfig_shadow; /* Must be a >120 ns delay before writing this again */ } - local_irq_restore(flags); + restore_flags(flags); return dir_g_out_bits & 0x7FFFFFFF; } return 0; @@ -634,26 +598,22 @@ gpio_ioctl(struct inode *inode, struct file *file, { unsigned long flags; unsigned long val; - int ret = 0; - struct gpio_private *priv = (struct gpio_private *)file->private_data; if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) { return -EINVAL; } - spin_lock(&gpio_lock); - switch (_IOC_NR(cmd)) { case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */ // read the port if (USE_PORTS(priv)) { - ret = *priv->port; + return *priv->port; } else if (priv->minor == GPIO_MINOR_G) { - ret = (*R_PORT_G_DATA) & 0x7FFFFFFF; + return (*R_PORT_G_DATA) & 0x7FFFFFFF; } break; case IO_SETBITS: - local_irq_save(flags); + local_irq_save(flags); local_irq_disable(); // set changeable bits with a 1 in arg if (USE_PORTS(priv)) { *priv->port = *priv->shadow |= @@ -664,7 +624,7 @@ gpio_ioctl(struct inode *inode, struct file *file, local_irq_restore(flags); break; case IO_CLRBITS: - local_irq_save(flags); + local_irq_save(flags); local_irq_disable(); // clear changeable bits with a 1 in arg if (USE_PORTS(priv)) { *priv->port = *priv->shadow &= @@ -706,34 +666,33 @@ gpio_ioctl(struct inode *inode, struct file *file, case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */ /* Read direction 0=input 1=output */ if (USE_PORTS(priv)) { - ret = *priv->dir_shadow; + return *priv->dir_shadow; } else if (priv->minor == GPIO_MINOR_G) { /* Note: Some bits are both in and out, * Those that are dual is set here as well. */ - ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF; + return (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF; } - break; case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */ /* Set direction 0=unchanged 1=input, * return mask with 1=input */ - ret = setget_input(priv, arg) & 0x7FFFFFFF; + return setget_input(priv, arg) & 0x7FFFFFFF; break; case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */ /* Set direction 0=unchanged 1=output, * return mask with 1=output */ - ret = setget_output(priv, arg) & 0x7FFFFFFF; - break; + return setget_output(priv, arg) & 0x7FFFFFFF; + case IO_SHUTDOWN: SOFT_SHUTDOWN(); break; case IO_GET_PWR_BT: #if defined (CONFIG_ETRAX_SOFT_SHUTDOWN) - ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT)); + return (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT)); #else - ret = 0; + return 0; #endif break; case IO_CFG_WRITE_MODE: @@ -750,7 +709,7 @@ gpio_ioctl(struct inode *inode, struct file *file, { priv->clk_mask = 0; priv->data_mask = 0; - ret = -EPERM; + return -EPERM; } break; case IO_READ_INBITS: @@ -761,7 +720,8 @@ gpio_ioctl(struct inode *inode, struct file *file, val = *R_PORT_G_DATA; } if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) - ret = -EFAULT; + return -EFAULT; + return 0; break; case IO_READ_OUTBITS: /* *arg is result of reading the output shadow */ @@ -771,43 +731,36 @@ gpio_ioctl(struct inode *inode, struct file *file, val = port_g_data_shadow; } if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) - ret = -EFAULT; + return -EFAULT; break; case IO_SETGET_INPUT: /* bits set in *arg is set to input, * *arg updated with current input pins. */ if (copy_from_user(&val, (unsigned long*)arg, sizeof(val))) - { - ret = -EFAULT; - break; - } + return -EFAULT; val = setget_input(priv, val); if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) - ret = -EFAULT; + return -EFAULT; break; case IO_SETGET_OUTPUT: /* bits set in *arg is set to output, * *arg updated with current output pins. */ if (copy_from_user(&val, (unsigned long*)arg, sizeof(val))) - { - ret = -EFAULT; - break; - } + return -EFAULT; val = setget_output(priv, val); if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) - ret = -EFAULT; + return -EFAULT; break; default: if (priv->minor == GPIO_MINOR_LEDS) - ret = gpio_leds_ioctl(cmd, arg); + return gpio_leds_ioctl(cmd, arg); else - ret = -EINVAL; + return -EINVAL; } /* switch */ - - spin_unlock(&gpio_lock); - return ret; + + return 0; } static int @@ -849,20 +802,60 @@ struct file_operations gpio_fops = { }; -void ioif_watcher(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available) +static void __init gpio_init_port_g(void) { - unsigned long int flags; - D(printk("gpio.c: ioif_watcher called\n")); - D(printk("gpio.c: G in: 0x%08x G out: 0x%08x PA: 0x%02x PB: 0x%02x\n", - gpio_in_available, gpio_out_available, pa_available, pb_available)); +#define GROUPA (0x0000FF3F) +#define GROUPB (1<<6 | 1<<7) +#define GROUPC (1<<30 | 1<<31) +#define GROUPD (0x3FFF0000) +#define GROUPD_LOW (0x00FF0000) + unsigned long used_in_bits = 0; + unsigned long used_out_bits = 0; + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi0, select)){ + used_in_bits |= GROUPA | GROUPB | 0 | 0; + used_out_bits |= GROUPA | GROUPB | 0 | 0; + } + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ata, select)) { + used_in_bits |= GROUPA | GROUPB | GROUPC | (GROUPD & ~(1<<25|1<<26)); + used_out_bits |= GROUPA | GROUPB | GROUPC | GROUPD; + } - spin_lock_irqsave(&gpio_lock, flags); + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, par0, select)) { + used_in_bits |= (GROUPA & ~(1<<0)) | 0 | 0 | 0; + used_out_bits |= (GROUPA & ~(1<<0)) | 0 | 0 | 0; + } + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ser2, select)) { + used_in_bits |= 0 | GROUPB | 0 | 0; + used_out_bits |= 0 | GROUPB | 0 | 0; + } + /* mio same as shared RAM ? */ + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, mio, select)) { + used_in_bits |= (GROUPA & ~(1<<0)) | 0 |0 |GROUPD_LOW; + used_out_bits |= (GROUPA & ~(1<<0|1<<1|1<<2)) | 0 |0 |GROUPD_LOW; + } + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi1, select)) { + used_in_bits |= 0 | 0 | GROUPC | GROUPD; + used_out_bits |= 0 | 0 | GROUPC | GROUPD; + } + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi0w, select)) { + used_in_bits |= GROUPA | GROUPB | 0 | (GROUPD_LOW | 1<<24); + used_out_bits |= GROUPA | GROUPB | 0 | (GROUPD_LOW | 1<<24 | 1<<25|1<<26); + } - dir_g_in_bits = gpio_in_available; - dir_g_out_bits = gpio_out_available; + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, par1, select)) { + used_in_bits |= 0 | 0 | 0 | (GROUPD & ~(1<<24)); + used_out_bits |= 0 | 0 | 0 | (GROUPD & ~(1<<24)); + } + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ser3, select)) { + used_in_bits |= 0 | 0 | GROUPC | 0; + used_out_bits |= 0 | 0 | GROUPC | 0; + } + /* mio same as shared RAM-W? */ + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, mio_w, select)) { + used_in_bits |= (GROUPA & ~(1<<0)) | 0 | 0 |GROUPD_LOW; + used_out_bits |= (GROUPA & ~(1<<0|1<<1|1<<2)) | 0 | 0 |GROUPD_LOW; + } + /* TODO: USB p2, parw, sync ser3? */ /* Initialise the dir_g_shadow etc. depending on genconfig */ /* 0=input 1=output */ @@ -875,7 +868,10 @@ void ioif_watcher(const unsigned int gpio_in_available, if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out)) dir_g_shadow |= (1 << 24); - changeable_dir_g = changeable_dir_g_mask; + dir_g_in_bits = ~used_in_bits; + dir_g_out_bits = ~used_out_bits; + + changeable_dir_g = 0x01FFFF01; /* all that can change dir */ changeable_dir_g &= dir_g_out_bits; changeable_dir_g &= dir_g_in_bits; /* Correct the bits that can change direction */ @@ -884,7 +880,6 @@ void ioif_watcher(const unsigned int gpio_in_available, dir_g_in_bits &= ~changeable_dir_g; dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g); - spin_unlock_irqrestore(&gpio_lock, flags); printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX val: %08lX\n", dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA); @@ -901,7 +896,6 @@ gpio_init(void) #if defined (CONFIG_ETRAX_CSP0_LEDS) int i; #endif - printk("gpio init\n"); /* do the formalities */ @@ -925,13 +919,8 @@ gpio_init(void) #endif #endif - /* The I/O interface allocation watcher will be called when - * registering it. */ - if (cris_io_interface_register_watcher(ioif_watcher)){ - printk(KERN_WARNING "gpio_init: Failed to install IO if allocator watcher\n"); - } - - printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001, 2002, 2003, 2004 Axis Communications AB\n"); + gpio_init_port_g(); + printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001, 2002 Axis Communications AB\n"); /* We call etrax_gpio_wake_up_check() from timer interrupt and * from cpu_idle() in kernel/process.c * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms diff --git a/trunk/arch/cris/arch-v10/drivers/i2c.c b/trunk/arch/cris/arch-v10/drivers/i2c.c index b38267d60d30..8bbe233ba7b1 100644 --- a/trunk/arch/cris/arch-v10/drivers/i2c.c +++ b/trunk/arch/cris/arch-v10/drivers/i2c.c @@ -12,15 +12,6 @@ *! don't use PB_I2C if DS1302 uses same bits, *! use PB. *! $Log: i2c.c,v $ -*! Revision 1.13 2005/03/07 13:13:07 starvik -*! Added spinlocks to protect states etc -*! -*! Revision 1.12 2005/01/05 06:11:22 starvik -*! No need to do local_irq_disable after local_irq_save. -*! -*! Revision 1.11 2004/12/13 12:21:52 starvik -*! Added I/O and DMA allocators from Linux 2.4 -*! *! Revision 1.9 2004/08/24 06:49:14 starvik *! Whitespace cleanup *! @@ -84,7 +75,7 @@ *! (C) Copyright 1999-2002 Axis Communications AB, LUND, SWEDEN *! *!***************************************************************************/ -/* $Id: i2c.c,v 1.13 2005/03/07 13:13:07 starvik Exp $ */ +/* $Id: i2c.c,v 1.9 2004/08/24 06:49:14 starvik Exp $ */ /****************** INCLUDE FILES SECTION ***********************************/ @@ -104,7 +95,6 @@ #include #include #include -#include #include "i2c.h" @@ -194,7 +184,6 @@ static const char i2c_name[] = "i2c"; #define i2c_delay(usecs) udelay(usecs) -static DEFINE_SPINLOCK(i2c_lock); /* Protect directions etc */ /****************** FUNCTION DEFINITION SECTION *************************/ @@ -499,14 +488,13 @@ i2c_writereg(unsigned char theSlave, unsigned char theReg, int error, cntr = 3; unsigned long flags; - spin_lock(&i2c_lock); - do { error = 0; /* * we don't like to be interrupted */ local_irq_save(flags); + local_irq_disable(); i2c_start(); /* @@ -550,8 +538,6 @@ i2c_writereg(unsigned char theSlave, unsigned char theReg, i2c_delay(CLOCK_LOW_TIME); - spin_unlock(&i2c_lock); - return -error; } @@ -569,14 +555,13 @@ i2c_readreg(unsigned char theSlave, unsigned char theReg) int error, cntr = 3; unsigned long flags; - spin_lock(&i2c_lock); - do { error = 0; /* * we don't like to be interrupted */ local_irq_save(flags); + local_irq_disable(); /* * generate start condition */ @@ -635,8 +620,6 @@ i2c_readreg(unsigned char theSlave, unsigned char theReg) } while(error && cntr--); - spin_unlock(&i2c_lock); - return b; } @@ -703,26 +686,15 @@ static struct file_operations i2c_fops = { int __init i2c_init(void) { - static int res = 0; - static int first = 1; - - if (!first) { - return res; - } - /* Setup and enable the Port B I2C interface */ #ifndef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C - if ((res = cris_request_io_interface(if_i2c, "I2C"))) { - printk(KERN_CRIT "i2c_init: Failed to get IO interface\n"); - return res; - } - *R_PORT_PB_I2C = port_pb_i2c_shadow |= IO_STATE(R_PORT_PB_I2C, i2c_en, on) | IO_FIELD(R_PORT_PB_I2C, i2c_d, 1) | IO_FIELD(R_PORT_PB_I2C, i2c_clk, 1) | IO_STATE(R_PORT_PB_I2C, i2c_oe_, enable); +#endif port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir0); port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir1); @@ -730,26 +702,8 @@ i2c_init(void) *R_PORT_PB_DIR = (port_pb_dir_shadow |= IO_STATE(R_PORT_PB_DIR, dir0, input) | IO_STATE(R_PORT_PB_DIR, dir1, output)); -#else - if ((res = cris_io_interface_allocate_pins(if_i2c, - 'b', - CONFIG_ETRAX_I2C_DATA_PORT, - CONFIG_ETRAX_I2C_DATA_PORT))) { - printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C data port\n"); - return res; - } else if ((res = cris_io_interface_allocate_pins(if_i2c, - 'b', - CONFIG_ETRAX_I2C_CLK_PORT, - CONFIG_ETRAX_I2C_CLK_PORT))) { - cris_io_interface_free_pins(if_i2c, - 'b', - CONFIG_ETRAX_I2C_DATA_PORT, - CONFIG_ETRAX_I2C_DATA_PORT); - printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C clk port\n"); - } -#endif - return res; + return 0; } static int __init @@ -757,16 +711,14 @@ i2c_register(void) { int res; - res = i2c_init(); - if (res < 0) - return res; + i2c_init(); res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops); if(res < 0) { printk(KERN_ERR "i2c: couldn't get a major number.\n"); return res; } - printk(KERN_INFO "I2C driver v2.2, (c) 1999-2004 Axis Communications AB\n"); + printk(KERN_INFO "I2C driver v2.2, (c) 1999-2001 Axis Communications AB\n"); return 0; } diff --git a/trunk/arch/cris/arch-v10/drivers/pcf8563.c b/trunk/arch/cris/arch-v10/drivers/pcf8563.c index 201f4c90d961..b3dfdf7b8fc5 100644 --- a/trunk/arch/cris/arch-v10/drivers/pcf8563.c +++ b/trunk/arch/cris/arch-v10/drivers/pcf8563.c @@ -15,7 +15,7 @@ * * Author: Tobias Anderberg . * - * $Id: pcf8563.c,v 1.11 2005/03/07 13:13:07 starvik Exp $ + * $Id: pcf8563.c,v 1.8 2004/08/24 06:42:51 starvik Exp $ */ #include @@ -40,7 +40,7 @@ #define PCF8563_MAJOR 121 /* Local major number. */ #define DEVICE_NAME "rtc" /* Name which is registered in /proc/devices. */ #define PCF8563_NAME "PCF8563" -#define DRIVER_VERSION "$Revision: 1.11 $" +#define DRIVER_VERSION "$Revision: 1.8 $" /* I2C bus slave registers. */ #define RTC_I2C_READ 0xa3 @@ -49,8 +49,6 @@ /* Two simple wrapper macros, saves a few keystrokes. */ #define rtc_read(x) i2c_readreg(RTC_I2C_READ, x) #define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y) - -static DEFINE_SPINLOCK(rtc_lock); /* Protect state etc */ static const unsigned char days_in_month[] = { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; @@ -127,12 +125,9 @@ get_rtc_time(struct rtc_time *tm) int __init pcf8563_init(void) { - int ret; + unsigned char ret; - if ((ret = i2c_init())) { - printk(KERN_CRIT "pcf8563_init: failed to init i2c\n"); - return ret; - } + i2c_init(); /* * First of all we need to reset the chip. This is done by @@ -205,15 +200,12 @@ pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned { struct rtc_time tm; - spin_lock(&rtc_lock); get_rtc_time(&tm); if (copy_to_user((struct rtc_time *) arg, &tm, sizeof(struct rtc_time))) { - spin_unlock(&rtc_lock); return -EFAULT; } - spin_unlock(&rtc_lock); return 0; } break; @@ -258,8 +250,6 @@ pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned BIN_TO_BCD(tm.tm_min); BIN_TO_BCD(tm.tm_sec); tm.tm_mon |= century; - - spin_lock(&rtc_lock); rtc_write(RTC_YEAR, tm.tm_year); rtc_write(RTC_MONTH, tm.tm_mon); @@ -268,8 +258,6 @@ pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned rtc_write(RTC_MINUTES, tm.tm_min); rtc_write(RTC_SECONDS, tm.tm_sec); - spin_unlock(&rtc_lock); - return 0; #endif /* !CONFIG_ETRAX_RTC_READONLY */ } diff --git a/trunk/arch/cris/arch-v10/kernel/Makefile b/trunk/arch/cris/arch-v10/kernel/Makefile index dcfec41d3533..52761603b6a5 100644 --- a/trunk/arch/cris/arch-v10/kernel/Makefile +++ b/trunk/arch/cris/arch-v10/kernel/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile,v 1.6 2004/12/13 12:21:51 starvik Exp $ +# $Id: Makefile,v 1.5 2004/06/02 08:24:38 starvik Exp $ # # Makefile for the linux kernel. # @@ -7,8 +7,7 @@ extra-y := head.o obj-y := entry.o traps.o shadows.o debugport.o irq.o \ - process.o setup.o signal.o traps.o time.o ptrace.o \ - dma.o io_interface_mux.o + process.o setup.o signal.o traps.o time.o ptrace.o obj-$(CONFIG_ETRAX_KGDB) += kgdb.o obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o diff --git a/trunk/arch/cris/arch-v10/kernel/debugport.c b/trunk/arch/cris/arch-v10/kernel/debugport.c index f3a85b77c17e..6cf069e5e7b6 100644 --- a/trunk/arch/cris/arch-v10/kernel/debugport.c +++ b/trunk/arch/cris/arch-v10/kernel/debugport.c @@ -12,31 +12,6 @@ * init_etrax_debug() * * $Log: debugport.c,v $ - * Revision 1.27 2005/06/10 10:34:14 starvik - * Real console support - * - * Revision 1.26 2005/06/07 07:06:07 starvik - * Added LF->CR translation to make ETRAX customers happy. - * - * Revision 1.25 2005/03/08 08:56:47 mikaelam - * Do only set index as port->index if port is defined, otherwise use the index from the command line - * - * Revision 1.24 2005/01/19 10:26:33 mikaelam - * Return the cris serial driver in console device driver callback function - * - * Revision 1.23 2005/01/14 10:12:17 starvik - * KGDB on separate port. - * Console fixes from 2.4. - * - * Revision 1.22 2005/01/11 16:06:13 starvik - * typo - * - * Revision 1.21 2005/01/11 13:49:14 starvik - * Added raw_printk to be used where we don't trust the console. - * - * Revision 1.20 2004/12/27 11:18:32 starvik - * Merge of Linux 2.6.10 (not functional yet). - * * Revision 1.19 2004/10/21 07:26:16 starvik * Made it possible to specify console settings on kernel command line. * @@ -139,11 +114,7 @@ struct dbg_port ports[]= R_SERIAL0_BAUD, R_SERIAL0_TR_CTRL, R_SERIAL0_REC_CTRL, - IO_STATE(R_IRQ_MASK1_SET, ser0_data, set), - 0, - 115200, - 'N', - 8 + IO_STATE(R_IRQ_MASK1_SET, ser0_data, set) }, { 1, @@ -153,11 +124,7 @@ struct dbg_port ports[]= R_SERIAL1_BAUD, R_SERIAL1_TR_CTRL, R_SERIAL1_REC_CTRL, - IO_STATE(R_IRQ_MASK1_SET, ser1_data, set), - 0, - 115200, - 'N', - 8 + IO_STATE(R_IRQ_MASK1_SET, ser1_data, set) }, { 2, @@ -167,11 +134,7 @@ struct dbg_port ports[]= R_SERIAL2_BAUD, R_SERIAL2_TR_CTRL, R_SERIAL2_REC_CTRL, - IO_STATE(R_IRQ_MASK1_SET, ser2_data, set), - 0, - 115200, - 'N', - 8 + IO_STATE(R_IRQ_MASK1_SET, ser2_data, set) }, { 3, @@ -181,15 +144,11 @@ struct dbg_port ports[]= R_SERIAL3_BAUD, R_SERIAL3_TR_CTRL, R_SERIAL3_REC_CTRL, - IO_STATE(R_IRQ_MASK1_SET, ser3_data, set), - 0, - 115200, - 'N', - 8 + IO_STATE(R_IRQ_MASK1_SET, ser3_data, set) } }; -extern struct tty_driver *serial_driver; +static struct tty_driver *serial_driver; struct dbg_port* port = #if defined(CONFIG_ETRAX_DEBUG_PORT0) @@ -203,44 +162,37 @@ struct dbg_port* port = #else NULL; #endif +/* Used by serial.c to register a debug_write_function so that the normal + * serial driver is used for kernel debug output + */ +typedef int (*debugport_write_function)(int i, const char *buf, unsigned int len); -static struct dbg_port* kgdb_port = -#if defined(CONFIG_ETRAX_KGDB_PORT0) - &ports[0]; -#elif defined(CONFIG_ETRAX_KGDB_PORT1) - &ports[1]; -#elif defined(CONFIG_ETRAX_KGDB_PORT2) - &ports[2]; -#elif defined(CONFIG_ETRAX_KGDB_PORT3) - &ports[3]; -#else - NULL; -#endif +debugport_write_function debug_write_function = NULL; static void -start_port(struct dbg_port* p) +start_port(void) { unsigned long rec_ctrl = 0; unsigned long tr_ctrl = 0; - if (!p) + if (!port) return; - if (p->started) + if (port->started) return; - p->started = 1; + port->started = 1; - if (p->index == 0) + if (port->index == 0) { genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6); genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused); } - else if (p->index == 1) + else if (port->index == 1) { genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8); genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb); } - else if (p->index == 2) + else if (port->index == 2) { genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2); genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0); @@ -259,69 +211,69 @@ start_port(struct dbg_port* p) *R_GEN_CONFIG = genconfig_shadow; - *p->xoff = + *port->xoff = IO_STATE(R_SERIAL0_XOFF, tx_stop, enable) | IO_STATE(R_SERIAL0_XOFF, auto_xoff, disable) | IO_FIELD(R_SERIAL0_XOFF, xoff_char, 0); - switch (p->baudrate) + switch (port->baudrate) { case 0: case 115200: - *p->baud = + *port->baud = IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); break; case 1200: - *p->baud = + *port->baud = IO_STATE(R_SERIAL0_BAUD, tr_baud, c1200Hz) | IO_STATE(R_SERIAL0_BAUD, rec_baud, c1200Hz); break; case 2400: - *p->baud = + *port->baud = IO_STATE(R_SERIAL0_BAUD, tr_baud, c2400Hz) | IO_STATE(R_SERIAL0_BAUD, rec_baud, c2400Hz); break; case 4800: - *p->baud = + *port->baud = IO_STATE(R_SERIAL0_BAUD, tr_baud, c4800Hz) | IO_STATE(R_SERIAL0_BAUD, rec_baud, c4800Hz); break; case 9600: - *p->baud = + *port->baud = IO_STATE(R_SERIAL0_BAUD, tr_baud, c9600Hz) | IO_STATE(R_SERIAL0_BAUD, rec_baud, c9600Hz); break; case 19200: - *p->baud = + *port->baud = IO_STATE(R_SERIAL0_BAUD, tr_baud, c19k2Hz) | IO_STATE(R_SERIAL0_BAUD, rec_baud, c19k2Hz); break; case 38400: - *p->baud = + *port->baud = IO_STATE(R_SERIAL0_BAUD, tr_baud, c38k4Hz) | IO_STATE(R_SERIAL0_BAUD, rec_baud, c38k4Hz); break; case 57600: - *p->baud = + *port->baud = IO_STATE(R_SERIAL0_BAUD, tr_baud, c57k6Hz) | IO_STATE(R_SERIAL0_BAUD, rec_baud, c57k6Hz); break; default: - *p->baud = + *port->baud = IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); break; } - if (p->parity == 'E') { + if (port->parity == 'E') { rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) | IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); tr_ctrl = IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); - } else if (p->parity == 'O') { + } else if (port->parity == 'O') { rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd) | IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); @@ -336,7 +288,8 @@ start_port(struct dbg_port* p) IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, disable); } - if (p->bits == 7) + + if (port->bits == 7) { rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit); tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit); @@ -347,7 +300,7 @@ start_port(struct dbg_port* p) tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit); } - *p->rec_ctrl = + *port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, dma_err, stop) | IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable) | IO_STATE(R_SERIAL0_REC_CTRL, rts_, active) | @@ -355,7 +308,7 @@ start_port(struct dbg_port* p) IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, normal) | rec_ctrl; - *p->tr_ctrl = + *port->tr_ctrl = IO_FIELD(R_SERIAL0_TR_CTRL, txd, 0) | IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable) | IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, disabled) | @@ -370,18 +323,8 @@ console_write_direct(struct console *co, const char *buf, unsigned int len) int i; unsigned long flags; local_irq_save(flags); - - if (!port) - return; - /* Send data */ for (i = 0; i < len; i++) { - /* LF -> CRLF */ - if (buf[i] == '\n') { - while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) - ; - *port->write = '\r'; - } /* Wait until transmitter is ready and send.*/ while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) ; @@ -390,25 +333,6 @@ console_write_direct(struct console *co, const char *buf, unsigned int len) local_irq_restore(flags); } -int raw_printk(const char *fmt, ...) -{ - static char buf[1024]; - int printed_len; - static int first = 1; - if (first) { - /* Force reinitialization of the port to get manual mode. */ - port->started = 0; - start_port(port); - first = 0; - } - va_list args; - va_start(args, fmt); - printed_len = vsnprintf(buf, sizeof(buf), fmt, args); - va_end(args); - console_write_direct(NULL, buf, strlen(buf)); - return printed_len; -} - static void console_write(struct console *co, const char *buf, unsigned int len) { @@ -421,7 +345,18 @@ console_write(struct console *co, const char *buf, unsigned int len) return; #endif - console_write_direct(co, buf, len); + start_port(); + +#ifdef CONFIG_ETRAX_KGDB + /* kgdb needs to output debug info using the gdb protocol */ + putDebugString(buf, len); + return; +#endif + + if (debug_write_function) + debug_write_function(co->index, buf, len); + else + console_write_direct(co, buf, len); } /* legacy function */ @@ -439,11 +374,8 @@ getDebugChar(void) { unsigned long readval; - if (!kgdb_port) - return 0; - do { - readval = *kgdb_port->read; + readval = *port->read; } while (!(readval & IO_MASK(R_SERIAL0_READ, data_avail))); return (readval & IO_MASK(R_SERIAL0_READ, data_in)); @@ -454,12 +386,9 @@ getDebugChar(void) void putDebugChar(int val) { - if (!kgdb_port) - return; - - while (!(*kgdb_port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) + while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) ; - *kgdb_port->write = val; + *port->write = val; } /* Enable irq for receiving chars on the debug port, used by kgdb */ @@ -467,16 +396,19 @@ putDebugChar(int val) void enableDebugIRQ(void) { - if (!kgdb_port) - return; - - *R_IRQ_MASK1_SET = kgdb_port->irq; + *R_IRQ_MASK1_SET = port->irq; /* use R_VECT_MASK directly, since we really bypass Linux normal * IRQ handling in kgdb anyway, we don't need to use enable_irq */ *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set); - *kgdb_port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable); + *port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable); +} + +static struct tty_driver* +etrax_console_device(struct console* co, int *index) +{ + return serial_driver; } static int __init @@ -496,69 +428,11 @@ console_setup(struct console *co, char *options) if (*s) port->parity = *s++; if (*s) port->bits = *s++ - '0'; port->started = 0; - start_port(0); + start_port(); } return 0; } -/* This is a dummy serial device that throws away anything written to it. - * This is used when no debug output is wanted. - */ -static struct tty_driver dummy_driver; - -static int dummy_open(struct tty_struct *tty, struct file * filp) -{ - return 0; -} - -static void dummy_close(struct tty_struct *tty, struct file * filp) -{ -} - -static int dummy_write(struct tty_struct * tty, - const unsigned char *buf, int count) -{ - return count; -} - -static int -dummy_write_room(struct tty_struct *tty) -{ - return 8192; -} - -void __init -init_dummy_console(void) -{ - memset(&dummy_driver, 0, sizeof(struct tty_driver)); - dummy_driver.driver_name = "serial"; - dummy_driver.name = "ttyS"; - dummy_driver.major = TTY_MAJOR; - dummy_driver.minor_start = 68; - dummy_driver.num = 1; /* etrax100 has 4 serial ports */ - dummy_driver.type = TTY_DRIVER_TYPE_SERIAL; - dummy_driver.subtype = SERIAL_TYPE_NORMAL; - dummy_driver.init_termios = tty_std_termios; - dummy_driver.init_termios.c_cflag = - B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */ - dummy_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS; - - dummy_driver.open = dummy_open; - dummy_driver.close = dummy_close; - dummy_driver.write = dummy_write; - dummy_driver.write_room = dummy_write_room; - if (tty_register_driver(&dummy_driver)) - panic("Couldn't register dummy serial driver\n"); -} - -static struct tty_driver* -etrax_console_device(struct console* co, int *index) -{ - if (port) - *index = port->index; - return port ? serial_driver : &dummy_driver; -} - static struct console sercons = { name : "ttyS", write: console_write, @@ -630,21 +504,28 @@ init_etrax_debug(void) static int first = 1; if (!first) { - unregister_console(&sercons); - register_console(&sercons0); - register_console(&sercons1); - register_console(&sercons2); - register_console(&sercons3); - init_dummy_console(); + if (!port) { + register_console(&sercons0); + register_console(&sercons1); + register_console(&sercons2); + register_console(&sercons3); + unregister_console(&sercons); + } return 0; } - first = 0; - register_console(&sercons); - start_port(port); -#ifdef CONFIG_ETRAX_KGDB - start_port(kgdb_port); -#endif + if (port) + register_console(&sercons); + return 0; +} + +int __init +init_console(void) +{ + serial_driver = alloc_tty_driver(1); + if (!serial_driver) + return -ENOMEM; return 0; } + __initcall(init_etrax_debug); diff --git a/trunk/arch/cris/arch-v10/kernel/dma.c b/trunk/arch/cris/arch-v10/kernel/dma.c deleted file mode 100644 index e9a0311b141d..000000000000 --- a/trunk/arch/cris/arch-v10/kernel/dma.c +++ /dev/null @@ -1,287 +0,0 @@ -/* Wrapper for DMA channel allocator that updates DMA client muxing. - * Copyright 2004, Axis Communications AB - * $Id: dma.c,v 1.1 2004/12/13 12:21:51 starvik Exp $ - */ - -#include -#include -#include - -#include -#include - -/* Macro to access ETRAX 100 registers */ -#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \ - IO_STATE_(reg##_, field##_, _##val) - - -static char used_dma_channels[MAX_DMA_CHANNELS]; -static const char * used_dma_channels_users[MAX_DMA_CHANNELS]; - -int cris_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, enum dma_owner owner) -{ - unsigned long flags; - unsigned long int gens; - int fail = -EINVAL; - - if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) { - printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr); - return -EINVAL; - } - - local_irq_save(flags); - if (used_dma_channels[dmanr]) { - local_irq_restore(flags); - if (options & DMA_VERBOSE_ON_ERROR) { - printk(KERN_CRIT "Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]); - } - if (options & DMA_PANIC_ON_ERROR) { - panic("request_dma error!"); - } - return -EBUSY; - } - - gens = genconfig_shadow; - - switch(owner) - { - case dma_eth: - if ((dmanr != NETWORK_TX_DMA_NBR) && - (dmanr != NETWORK_RX_DMA_NBR)) { - printk(KERN_CRIT "Invalid DMA channel for eth\n"); - goto bail; - } - break; - case dma_ser0: - if (dmanr == SER0_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma6, serial0); - } else if (dmanr == SER0_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma7, serial0); - } else { - printk(KERN_CRIT "Invalid DMA channel for ser0\n"); - goto bail; - } - break; - case dma_ser1: - if (dmanr == SER1_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma8, serial1); - } else if (dmanr == SER1_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma9, serial1); - } else { - printk(KERN_CRIT "Invalid DMA channel for ser1\n"); - goto bail; - } - break; - case dma_ser2: - if (dmanr == SER2_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma2, serial2); - } else if (dmanr == SER2_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma3, serial2); - } else { - printk(KERN_CRIT "Invalid DMA channel for ser2\n"); - goto bail; - } - break; - case dma_ser3: - if (dmanr == SER3_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma4, serial3); - } else if (dmanr == SER3_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma5, serial3); - } else { - printk(KERN_CRIT "Invalid DMA channel for ser3\n"); - goto bail; - } - break; - case dma_ata: - if (dmanr == ATA_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma2, ata); - } else if (dmanr == ATA_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma3, ata); - } else { - printk(KERN_CRIT "Invalid DMA channel for ata\n"); - goto bail; - } - break; - case dma_ext0: - if (dmanr == EXTDMA0_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma4, extdma0); - } else if (dmanr == EXTDMA0_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma5, extdma0); - } else { - printk(KERN_CRIT "Invalid DMA channel for ext0\n"); - goto bail; - } - break; - case dma_ext1: - if (dmanr == EXTDMA1_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma6, extdma1); - } else if (dmanr == EXTDMA1_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma7, extdma1); - } else { - printk(KERN_CRIT "Invalid DMA channel for ext1\n"); - goto bail; - } - break; - case dma_int6: - if (dmanr == MEM2MEM_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma7, intdma6); - } else { - printk(KERN_CRIT "Invalid DMA channel for int6\n"); - goto bail; - } - break; - case dma_int7: - if (dmanr == MEM2MEM_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma6, intdma7); - } else { - printk(KERN_CRIT "Invalid DMA channel for int7\n"); - goto bail; - } - break; - case dma_usb: - if (dmanr == USB_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma8, usb); - } else if (dmanr == USB_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma9, usb); - } else { - printk(KERN_CRIT "Invalid DMA channel for usb\n"); - goto bail; - } - break; - case dma_scsi0: - if (dmanr == SCSI0_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma2, scsi0); - } else if (dmanr == SCSI0_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma3, scsi0); - } else { - printk(KERN_CRIT "Invalid DMA channel for scsi0\n"); - goto bail; - } - break; - case dma_scsi1: - if (dmanr == SCSI1_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma4, scsi1); - } else if (dmanr == SCSI1_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma5, scsi1); - } else { - printk(KERN_CRIT "Invalid DMA channel for scsi1\n"); - goto bail; - } - break; - case dma_par0: - if (dmanr == PAR0_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma2, par0); - } else if (dmanr == PAR0_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma3, par0); - } else { - printk(KERN_CRIT "Invalid DMA channel for par0\n"); - goto bail; - } - break; - case dma_par1: - if (dmanr == PAR1_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma4, par1); - } else if (dmanr == PAR1_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma5, par1); - } else { - printk(KERN_CRIT "Invalid DMA channel for par1\n"); - goto bail; - } - break; - default: - printk(KERN_CRIT "Invalid DMA owner.\n"); - goto bail; - } - - used_dma_channels[dmanr] = 1; - used_dma_channels_users[dmanr] = device_id; - - { - volatile int i; - genconfig_shadow = gens; - *R_GEN_CONFIG = genconfig_shadow; - /* Wait 12 cycles before doing any DMA command */ - for(i = 6; i > 0; i--) - nop(); - } - fail = 0; - bail: - local_irq_restore(flags); - return fail; -} - -void cris_free_dma(unsigned int dmanr, const char * device_id) -{ - unsigned long flags; - if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) { - printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr); - return; - } - - local_irq_save(flags); - if (!used_dma_channels[dmanr]) { - printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated\n", dmanr); - } else if (device_id != used_dma_channels_users[dmanr]) { - printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated by device\n", dmanr); - } else { - switch(dmanr) - { - case 0: - *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH0_CMD, cmd, *R_DMA_CH0_CMD) == - IO_STATE_VALUE(R_DMA_CH0_CMD, cmd, reset)); - break; - case 1: - *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH1_CMD, cmd, *R_DMA_CH1_CMD) == - IO_STATE_VALUE(R_DMA_CH1_CMD, cmd, reset)); - break; - case 2: - *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH2_CMD, cmd, *R_DMA_CH2_CMD) == - IO_STATE_VALUE(R_DMA_CH2_CMD, cmd, reset)); - break; - case 3: - *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH3_CMD, cmd, *R_DMA_CH3_CMD) == - IO_STATE_VALUE(R_DMA_CH3_CMD, cmd, reset)); - break; - case 4: - *R_DMA_CH4_CMD = IO_STATE(R_DMA_CH4_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH4_CMD, cmd, *R_DMA_CH4_CMD) == - IO_STATE_VALUE(R_DMA_CH4_CMD, cmd, reset)); - break; - case 5: - *R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH5_CMD, cmd, *R_DMA_CH5_CMD) == - IO_STATE_VALUE(R_DMA_CH5_CMD, cmd, reset)); - break; - case 6: - *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *R_DMA_CH6_CMD) == - IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); - break; - case 7: - *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH7_CMD, cmd, *R_DMA_CH7_CMD) == - IO_STATE_VALUE(R_DMA_CH7_CMD, cmd, reset)); - break; - case 8: - *R_DMA_CH8_CMD = IO_STATE(R_DMA_CH8_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH8_CMD, cmd, *R_DMA_CH8_CMD) == - IO_STATE_VALUE(R_DMA_CH8_CMD, cmd, reset)); - break; - case 9: - *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH9_CMD, cmd, *R_DMA_CH9_CMD) == - IO_STATE_VALUE(R_DMA_CH9_CMD, cmd, reset)); - break; - } - used_dma_channels[dmanr] = 0; - } - local_irq_restore(flags); -} - -EXPORT_SYMBOL(cris_request_dma); -EXPORT_SYMBOL(cris_free_dma); diff --git a/trunk/arch/cris/arch-v10/kernel/entry.S b/trunk/arch/cris/arch-v10/kernel/entry.S index c0163bf94a50..1bc44f481c34 100644 --- a/trunk/arch/cris/arch-v10/kernel/entry.S +++ b/trunk/arch/cris/arch-v10/kernel/entry.S @@ -1,4 +1,4 @@ -/* $Id: entry.S,v 1.28 2005/06/20 05:06:30 starvik Exp $ +/* $Id: entry.S,v 1.23 2004/10/19 13:07:37 starvik Exp $ * * linux/arch/cris/entry.S * @@ -7,22 +7,6 @@ * Authors: Bjorn Wesen (bjornw@axis.com) * * $Log: entry.S,v $ - * Revision 1.28 2005/06/20 05:06:30 starvik - * Remove unnecessary diff to kernel.org tree - * - * Revision 1.27 2005/03/04 08:16:16 starvik - * Merge of Linux 2.6.11. - * - * Revision 1.26 2005/01/11 13:49:47 starvik - * Added NMI handler. - * - * Revision 1.25 2004/12/27 11:18:32 starvik - * Merge of Linux 2.6.10 (not functional yet). - * - * Revision 1.24 2004/12/22 10:41:23 starvik - * Updates to make v10 compile with the latest SMP aware generic code (even - * though v10 will never have SMP). - * * Revision 1.23 2004/10/19 13:07:37 starvik * Merge of Linux 2.6.9 * @@ -295,7 +279,6 @@ #ifdef CONFIG_PREEMPT ; Check if preemptive kernel scheduling should be done _resume_kernel: - di ; Load current task struct movs.w -8192, $r0 ; THREAD_SIZE = 8192 and.d $sp, $r0 @@ -308,7 +291,12 @@ _need_resched: bpl _Rexit nop ; Ok, lets's do some preemptive kernel scheduling - jsr preempt_schedule_irq + move.d PREEMPT_ACTIVE, $r10 + move.d $r10, [$r0+TI_preempt_count] ; Mark as active + ei + jsr schedule + clear.d [$r0+TI_preempt_count] ; Mark as inactive + di ; Load new task struct movs.w -8192, $r0 ; THREAD_SIZE = 8192 and.d $sp, $r0 @@ -602,15 +590,15 @@ mmu_bus_fault: move.d $r0, [$sp+16] 1: btstq 12, $r1 ; Refill? bpl 2f - lsrq 24, $r1 ; Get PGD index (bit 24-31) - move.d [per_cpu__current_pgd], $r0 ; PGD for the current process + lsrq PMD_SHIFT, $r1 ; Get PMD index into PGD (bit 24-31) + move.d [current_pgd], $r0 ; PGD for the current process move.d [$r0+$r1.d], $r0 ; Get PMD beq 2f nop and.w PAGE_MASK, $r0 ; Remove PMD flags move.d [R_MMU_CAUSE], $r1 lsrq PAGE_SHIFT, $r1 - and.d 0x7ff, $r1 ; Get PTE index into PGD (bit 13-23) + and.d 0x7ff, $r1 ; Get PTE index into PMD (bit 13-24) move.d [$r0+$r1.d], $r1 ; Get PTE beq 2f nop @@ -668,6 +656,11 @@ hwbreakpoint: nop IRQ1_interrupt: + +#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) +;; If we receive a watchdog interrupt while it is not expected, then set +;; up a canonical frame and dump register contents before dying. + ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!! move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame push $srp @@ -679,16 +672,9 @@ IRQ1_interrupt: push $r10 ; push orig_r10 clear.d [$sp=$sp-4] ; frametype == 0, normal frame - move.d [R_IRQ_MASK0_RD], $r1 ; External NMI or watchdog? - and.d 0x80000000, $r1 - beq wdog - move.d $sp, $r10 - jsr handle_nmi - setf m ; Enable NMI again - retb ; Return from NMI - nop -wdog: -#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) +;; We don't check that we actually were bit by the watchdog as opposed to +;; an external NMI, since there is currently no handler for external NMI. + ;; Check if we're waiting for reset to happen, as signalled by ;; hard_reset_now setting cause_of_death to a magic value. If so, just ;; get stuck until reset happens. @@ -1132,10 +1118,6 @@ sys_call_table: .long sys_mq_getsetattr .long sys_ni_syscall /* reserved for kexec */ .long sys_waitid - .long sys_ni_syscall /* 285 */ /* available */ - .long sys_add_key - .long sys_request_key - .long sys_keyctl /* * NOTE!! This doesn't have to be exact - we just have diff --git a/trunk/arch/cris/arch-v10/kernel/fasttimer.c b/trunk/arch/cris/arch-v10/kernel/fasttimer.c index 094ff45ae85b..4717f7ae8e51 100644 --- a/trunk/arch/cris/arch-v10/kernel/fasttimer.c +++ b/trunk/arch/cris/arch-v10/kernel/fasttimer.c @@ -1,20 +1,10 @@ -/* $Id: fasttimer.c,v 1.9 2005/03/04 08:16:16 starvik Exp $ +/* $Id: fasttimer.c,v 1.6 2004/05/14 10:18:39 starvik Exp $ * linux/arch/cris/kernel/fasttimer.c * * Fast timers for ETRAX100/ETRAX100LX * This may be useful in other OS than Linux so use 2 space indentation... * * $Log: fasttimer.c,v $ - * Revision 1.9 2005/03/04 08:16:16 starvik - * Merge of Linux 2.6.11. - * - * Revision 1.8 2005/01/05 06:09:29 starvik - * cli()/sti() will be obsolete in 2.6.11. - * - * Revision 1.7 2005/01/03 13:35:46 starvik - * Removed obsolete stuff. - * Mark fast timer IRQ as not shared. - * * Revision 1.6 2004/05/14 10:18:39 starvik * Export fast_timer_list * @@ -158,7 +148,8 @@ static int debug_log_cnt_wrapped = 0; #define DEBUG_LOG(string, value) \ { \ unsigned long log_flags; \ - local_irq_save(log_flags); \ + save_flags(log_flags); \ + cli(); \ debug_log_string[debug_log_cnt] = (string); \ debug_log_value[debug_log_cnt] = (unsigned long)(value); \ if (++debug_log_cnt >= DEBUG_LOG_MAX) \ @@ -166,7 +157,7 @@ static int debug_log_cnt_wrapped = 0; debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \ debug_log_cnt_wrapped = 1; \ } \ - local_irq_restore(log_flags); \ + restore_flags(log_flags); \ } #else #define DEBUG_LOG(string, value) @@ -329,7 +320,8 @@ void start_one_shot_timer(struct fast_timer *t, D1(printk("sft %s %d us\n", name, delay_us)); - local_irq_save(flags); + save_flags(flags); + cli(); do_gettimeofday_fast(&t->tv_set); tmp = fast_timer_list; @@ -403,7 +395,7 @@ void start_one_shot_timer(struct fast_timer *t, D2(printk("start_one_shot_timer: %d us done\n", delay_us)); - local_irq_restore(flags); + restore_flags(flags); } /* start_one_shot_timer */ static inline int fast_timer_pending (const struct fast_timer * t) @@ -433,10 +425,11 @@ int del_fast_timer(struct fast_timer * t) unsigned long flags; int ret; - local_irq_save(flags); + save_flags(flags); + cli(); ret = detach_fast_timer(t); t->next = t->prev = NULL; - local_irq_restore(flags); + restore_flags(flags); return ret; } /* del_fast_timer */ @@ -451,7 +444,8 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs) struct fast_timer *t; unsigned long flags; - local_irq_save(flags); + save_flags(flags); + cli(); /* Clear timer1 irq */ *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr); @@ -468,7 +462,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs) fast_timer_running = 0; fast_timer_ints++; - local_irq_restore(flags); + restore_flags(flags); t = fast_timer_list; while (t) @@ -488,7 +482,8 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs) fast_timers_expired++; /* Remove this timer before call, since it may reuse the timer */ - local_irq_save(flags); + save_flags(flags); + cli(); if (t->prev) { t->prev->next = t->next; @@ -503,7 +498,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs) } t->prev = NULL; t->next = NULL; - local_irq_restore(flags); + restore_flags(flags); if (t->function != NULL) { @@ -520,7 +515,8 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs) D1(printk(".\n")); } - local_irq_save(flags); + save_flags(flags); + cli(); if ((t = fast_timer_list) != NULL) { /* Start next timer.. */ @@ -539,7 +535,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs) #endif start_timer1(us); } - local_irq_restore(flags); + restore_flags(flags); break; } else @@ -550,7 +546,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs) D1(printk("e! %d\n", us)); } } - local_irq_restore(flags); + restore_flags(flags); } if (!t) @@ -752,12 +748,13 @@ static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len #endif used += sprintf(bigbuf + used, "Active timers:\n"); - local_irq_save(flags); + save_flags(flags); + cli(); t = fast_timer_list; while (t != NULL && (used+100 < BIG_BUF_SIZE)) { nextt = t->next; - local_irq_restore(flags); + restore_flags(flags); used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu " "d: %6li us data: 0x%08lX" /* " func: 0x%08lX" */ @@ -771,14 +768,14 @@ static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len t->data /* , t->function */ ); - local_irq_disable(); + cli(); if (t->next != nextt) { printk(KERN_WARNING "timer removed!\n"); } t = nextt; } - local_irq_restore(flags); + restore_flags(flags); } if (used - offset < len) @@ -966,7 +963,7 @@ void fast_timer_init(void) if ((fasttimer_proc_entry = create_proc_entry( "fasttimer", 0, 0 ))) fasttimer_proc_entry->read_proc = proc_fasttimer_read; #endif /* PROC_FS */ - if(request_irq(TIMER1_IRQ_NBR, timer1_handler, 0, + if(request_irq(TIMER1_IRQ_NBR, timer1_handler, SA_SHIRQ, "fast timer int", NULL)) { printk("err: timer1 irq\n"); diff --git a/trunk/arch/cris/arch-v10/kernel/head.S b/trunk/arch/cris/arch-v10/kernel/head.S index f00c145b43f1..2c1dd1184a8f 100644 --- a/trunk/arch/cris/arch-v10/kernel/head.S +++ b/trunk/arch/cris/arch-v10/kernel/head.S @@ -1,4 +1,4 @@ -/* $Id: head.S,v 1.10 2005/06/20 05:12:54 starvik Exp $ +/* $Id: head.S,v 1.7 2004/05/14 07:58:01 starvik Exp $ * * Head of the kernel - alter with care * @@ -7,16 +7,6 @@ * Authors: Bjorn Wesen (bjornw@axis.com) * * $Log: head.S,v $ - * Revision 1.10 2005/06/20 05:12:54 starvik - * Remove unnecessary diff to kernel.org tree - * - * Revision 1.9 2004/12/13 12:21:51 starvik - * Added I/O and DMA allocators from Linux 2.4 - * - * Revision 1.8 2004/11/22 11:41:14 starvik - * Kernel command line may be supplied to kernel. Not used by Axis but may - * be used by customers. - * * Revision 1.7 2004/05/14 07:58:01 starvik * Merge of changes from 2.4 * @@ -191,7 +181,6 @@ #define CRAMFS_MAGIC 0x28cd3d45 #define RAM_INIT_MAGIC 0x56902387 -#define COMMAND_LINE_MAGIC 0x87109563 #define START_ETHERNET_CLOCK IO_STATE(R_NETWORK_GEN_CONFIG, enable, on) |\ IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk) @@ -501,23 +490,6 @@ _no_romfs_in_flash: _start_it: - ;; Check if kernel command line is supplied - cmp.d COMMAND_LINE_MAGIC, $r10 - bne no_command_line - nop - - move.d 256, $r13 - move.d cris_command_line, $r10 - or.d 0x80000000, $r11 ; Make it virtual -1: - move.b [$r11+], $r12 - move.b $r12, [$r10+] - subq 1, $r13 - bne 1b - nop - -no_command_line: - ;; the kernel stack is overlayed with the task structure for each ;; task. thus the initial kernel stack is in the same page as the ;; init_task (but starts in the top of the page, size 8192) @@ -595,32 +567,76 @@ no_command_line: ;; Etrax product HW genconfig setup moveq 0,$r0 - - ;; Init interfaces (disable them). - or.d IO_STATE (R_GEN_CONFIG, scsi0, disable) \ - | IO_STATE (R_GEN_CONFIG, ata, disable) \ - | IO_STATE (R_GEN_CONFIG, par0, disable) \ - | IO_STATE (R_GEN_CONFIG, ser2, disable) \ - | IO_STATE (R_GEN_CONFIG, mio, disable) \ - | IO_STATE (R_GEN_CONFIG, scsi1, disable) \ - | IO_STATE (R_GEN_CONFIG, scsi0w, disable) \ - | IO_STATE (R_GEN_CONFIG, par1, disable) \ - | IO_STATE (R_GEN_CONFIG, ser3, disable) \ - | IO_STATE (R_GEN_CONFIG, mio_w, disable) \ - | IO_STATE (R_GEN_CONFIG, usb1, disable) \ - | IO_STATE (R_GEN_CONFIG, usb2, disable) \ - | IO_STATE (R_GEN_CONFIG, par_w, disable),$r0 - - ;; Init DMA channel muxing (set to unused clients). - or.d IO_STATE (R_GEN_CONFIG, dma2, ata) \ - | IO_STATE (R_GEN_CONFIG, dma3, ata) \ - | IO_STATE (R_GEN_CONFIG, dma4, scsi1) \ - | IO_STATE (R_GEN_CONFIG, dma5, scsi1) \ - | IO_STATE (R_GEN_CONFIG, dma6, unused) \ - | IO_STATE (R_GEN_CONFIG, dma7, unused) \ - | IO_STATE (R_GEN_CONFIG, dma8, usb) \ - | IO_STATE (R_GEN_CONFIG, dma9, usb),$r0 - +#if (!defined(CONFIG_ETRAX_KGDB) || !defined(CONFIG_ETRAX_DEBUG_PORT0)) \ + && !defined(CONFIG_DMA_MEMCPY) + ; DMA channels 6 and 7 to ser0, kgdb doesnt want DMA + or.d IO_STATE (R_GEN_CONFIG, dma7, serial0) \ + | IO_STATE (R_GEN_CONFIG, dma6, serial0),$r0 +#endif +#if !defined(CONFIG_ETRAX_KGDB) || !defined(CONFIG_ETRAX_DEBUG_PORT1) + ; DMA channels 8 and 9 to ser1, kgdb doesnt want DMA + or.d IO_STATE (R_GEN_CONFIG, dma9, serial1) \ + | IO_STATE (R_GEN_CONFIG, dma8, serial1),$r0 +#endif +#ifdef CONFIG_DMA_MEMCPY + ; 6/7 memory-memory DMA + or.d IO_STATE (R_GEN_CONFIG, dma7, intdma6) \ + | IO_STATE (R_GEN_CONFIG, dma6, intdma7),$r0 +#endif +#ifdef CONFIG_ETRAX_SERIAL_PORT2 + ; Enable serial port 2 + or.w IO_STATE (R_GEN_CONFIG, ser2, select),$r0 +#if !defined(CONFIG_ETRAX_KGDB) || !defined(CONFIG_ETRAX_DEBUG_PORT2) + ; DMA channels 2 and 3 to ser2, kgdb doesnt want DMA + or.d IO_STATE (R_GEN_CONFIG, dma3, serial2) \ + | IO_STATE (R_GEN_CONFIG, dma2, serial2),$r0 +#endif +#endif +#if defined(CONFIG_ETRAX_SERIAL_PORT3) || defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) + ; Enable serial port 3 + or.w IO_STATE (R_GEN_CONFIG, ser3, select),$r0 +#if !defined(CONFIG_ETRAX_KGDB) || !defined(CONFIG_ETRAX_DEBUG_PORT3) + ; DMA channels 4 and 5 to ser3, kgdb doesnt want DMA + or.d IO_STATE (R_GEN_CONFIG, dma5, serial3) \ + | IO_STATE (R_GEN_CONFIG, dma4, serial3),$r0 +#endif +#endif +#if defined(CONFIG_ETRAX_PARALLEL_PORT0) || defined(CONFIG_ETRAX_ETHERNET_LPSLAVE) + ; parport 0 enabled using DMA 2/3 + or.w IO_STATE (R_GEN_CONFIG, par0, select),$r0 +#endif +#if defined(CONFIG_ETRAX_PARALLEL_PORT1) || defined(CONFIG_ETRAX_ETHERNET_LPSLAVE) + ; parport 1 enabled using DMA 4/5 + or.w IO_STATE (R_GEN_CONFIG, par1, select),$r0 +#endif +#ifdef CONFIG_ETRAX_IDE + ; DMA channels 2 and 3 to ATA, ATA enabled + or.d IO_STATE (R_GEN_CONFIG, dma3, ata) \ + | IO_STATE (R_GEN_CONFIG, dma2, ata) \ + | IO_STATE (R_GEN_CONFIG, ata, select),$r0 +#endif + +#ifdef CONFIG_ETRAX_USB_HOST_PORT1 + ; Set the USB port 1 enable bit + or.d IO_STATE (R_GEN_CONFIG, usb1, select),$r0 +#endif +#ifdef CONFIG_ETRAX_USB_HOST_PORT2 + ; Set the USB port 2 enable bit + or.d IO_STATE (R_GEN_CONFIG, usb2, select),$r0 +#endif +#ifdef CONFIG_ETRAX_USB_HOST + ; Connect DMA channels 8 and 9 to USB + and.d (~(IO_MASK (R_GEN_CONFIG, dma9) \ + | IO_MASK (R_GEN_CONFIG, dma8))) \ + | IO_STATE (R_GEN_CONFIG, dma9, usb) \ + | IO_STATE (R_GEN_CONFIG, dma8, usb),$r0 +#endif + +#ifdef CONFIG_JULIETTE + ; DMA channels 4 and 5 to EXTDMA0, for Juliette + or.d IO_STATE (R_GEN_CONFIG, dma5, extdma0) \ + | IO_STATE (R_GEN_CONFIG, dma4, extdma0),$r0 +#endif #if defined(CONFIG_ETRAX_DEF_R_PORT_G0_DIR_OUT) or.d IO_STATE (R_GEN_CONFIG, g0dir, out),$r0 diff --git a/trunk/arch/cris/arch-v10/kernel/io_interface_mux.c b/trunk/arch/cris/arch-v10/kernel/io_interface_mux.c deleted file mode 100644 index 29d48ad00df9..000000000000 --- a/trunk/arch/cris/arch-v10/kernel/io_interface_mux.c +++ /dev/null @@ -1,879 +0,0 @@ -/* IO interface mux allocator for ETRAX100LX. - * Copyright 2004, Axis Communications AB - * $Id: io_interface_mux.c,v 1.2 2004/12/21 12:08:38 starvik Exp $ - */ - - -/* C.f. ETRAX100LX Designer's Reference 20.9 */ - -#include -#include -#include -#include -#include - -#include -#include -#include - - -#define DBG(s) - -/* Macro to access ETRAX 100 registers */ -#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \ - IO_STATE_(reg##_, field##_, _##val) - -enum io_if_group { - group_a = (1<<0), - group_b = (1<<1), - group_c = (1<<2), - group_d = (1<<3), - group_e = (1<<4), - group_f = (1<<5) -}; - -struct watcher -{ - void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available); - struct watcher *next; -}; - - -struct if_group -{ - enum io_if_group group; - unsigned char used; - enum cris_io_interface owner; -}; - - -struct interface -{ - enum cris_io_interface ioif; - unsigned char groups; - unsigned char used; - char *owner; - unsigned int gpio_g_in; - unsigned int gpio_g_out; - unsigned char gpio_b; -}; - -static struct if_group if_groups[6] = { - { - .group = group_a, - .used = 0, - }, - { - .group = group_b, - .used = 0, - }, - { - .group = group_c, - .used = 0, - }, - { - .group = group_d, - .used = 0, - }, - { - .group = group_e, - .used = 0, - }, - { - .group = group_f, - .used = 0, - } -}; - -/* The order in the array must match the order of enum - * cris_io_interface in io_interface_mux.h */ -static struct interface interfaces[] = { - /* Begin Non-multiplexed interfaces */ - { - .ioif = if_eth, - .groups = 0, - .gpio_g_in = 0, - .gpio_g_out = 0, - .gpio_b = 0 - }, - { - .ioif = if_serial_0, - .groups = 0, - .gpio_g_in = 0, - .gpio_g_out = 0, - .gpio_b = 0 - }, - /* End Non-multiplexed interfaces */ - { - .ioif = if_serial_1, - .groups = group_e, - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x00 - }, - { - .ioif = if_serial_2, - .groups = group_b, - .gpio_g_in = 0x000000c0, - .gpio_g_out = 0x000000c0, - .gpio_b = 0x00 - }, - { - .ioif = if_serial_3, - .groups = group_c, - .gpio_g_in = 0xc0000000, - .gpio_g_out = 0xc0000000, - .gpio_b = 0x00 - }, - { - .ioif = if_sync_serial_1, - .groups = group_e | group_f, /* if_sync_serial_1 and if_sync_serial_3 - can be used simultaneously */ - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x10 - }, - { - .ioif = if_sync_serial_3, - .groups = group_c | group_f, - .gpio_g_in = 0xc0000000, - .gpio_g_out = 0xc0000000, - .gpio_b = 0x80 - }, - { - .ioif = if_shared_ram, - .groups = group_a, - .gpio_g_in = 0x0000ff3e, - .gpio_g_out = 0x0000ff38, - .gpio_b = 0x00 - }, - { - .ioif = if_shared_ram_w, - .groups = group_a | group_d, - .gpio_g_in = 0x00ffff3e, - .gpio_g_out = 0x00ffff38, - .gpio_b = 0x00 - }, - { - .ioif = if_par_0, - .groups = group_a, - .gpio_g_in = 0x0000ff3e, - .gpio_g_out = 0x0000ff3e, - .gpio_b = 0x00 - }, - { - .ioif = if_par_1, - .groups = group_d, - .gpio_g_in = 0x3eff0000, - .gpio_g_out = 0x3eff0000, - .gpio_b = 0x00 - }, - { - .ioif = if_par_w, - .groups = group_a | group_d, - .gpio_g_in = 0x00ffff3e, - .gpio_g_out = 0x00ffff3e, - .gpio_b = 0x00 - }, - { - .ioif = if_scsi8_0, - .groups = group_a | group_b | group_f, /* if_scsi8_0 and if_scsi8_1 - can be used simultaneously */ - .gpio_g_in = 0x0000ffff, - .gpio_g_out = 0x0000ffff, - .gpio_b = 0x10 - }, - { - .ioif = if_scsi8_1, - .groups = group_c | group_d | group_f, /* if_scsi8_0 and if_scsi8_1 - can be used simultaneously */ - .gpio_g_in = 0xffff0000, - .gpio_g_out = 0xffff0000, - .gpio_b = 0x80 - }, - { - .ioif = if_scsi_w, - .groups = group_a | group_b | group_d | group_f, - .gpio_g_in = 0x01ffffff, - .gpio_g_out = 0x07ffffff, - .gpio_b = 0x80 - }, - { - .ioif = if_ata, - .groups = group_a | group_b | group_c | group_d, - .gpio_g_in = 0xf9ffffff, - .gpio_g_out = 0xffffffff, - .gpio_b = 0x80 - }, - { - .ioif = if_csp, - .groups = group_f, /* if_csp and if_i2c can be used simultaneously */ - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0xfc - }, - { - .ioif = if_i2c, - .groups = group_f, /* if_csp and if_i2c can be used simultaneously */ - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x03 - }, - { - .ioif = if_usb_1, - .groups = group_e | group_f, - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x2c - }, - { - .ioif = if_usb_2, - .groups = group_d, - .gpio_g_in = 0x0e000000, - .gpio_g_out = 0x3c000000, - .gpio_b = 0x00 - }, - /* GPIO pins */ - { - .ioif = if_gpio_grp_a, - .groups = group_a, - .gpio_g_in = 0x0000ff3f, - .gpio_g_out = 0x0000ff3f, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_b, - .groups = group_b, - .gpio_g_in = 0x000000c0, - .gpio_g_out = 0x000000c0, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_c, - .groups = group_c, - .gpio_g_in = 0xc0000000, - .gpio_g_out = 0xc0000000, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_d, - .groups = group_d, - .gpio_g_in = 0x3fff0000, - .gpio_g_out = 0x3fff0000, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_e, - .groups = group_e, - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_f, - .groups = group_f, - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0xff - } - /* Array end */ -}; - -static struct watcher *watchers = NULL; - -static unsigned int gpio_in_pins = 0xffffffff; -static unsigned int gpio_out_pins = 0xffffffff; -static unsigned char gpio_pb_pins = 0xff; -static unsigned char gpio_pa_pins = 0xff; - -static enum cris_io_interface gpio_pa_owners[8]; -static enum cris_io_interface gpio_pb_owners[8]; -static enum cris_io_interface gpio_pg_owners[32]; - -static int cris_io_interface_init(void); - -static unsigned char clear_group_from_set(const unsigned char groups, struct if_group *group) -{ - return (groups & ~group->group); -} - - -static struct if_group *get_group(const unsigned char groups) -{ - int i; - for (i = 0; i < sizeof(if_groups)/sizeof(struct if_group); i++) { - if (groups & if_groups[i].group) { - return &if_groups[i]; - } - } - return NULL; -} - - -static void notify_watchers(void) -{ - struct watcher *w = watchers; - - DBG(printk("io_interface_mux: notifying watchers\n")); - - while (NULL != w) { - w->notify((const unsigned int)gpio_in_pins, - (const unsigned int)gpio_out_pins, - (const unsigned char)gpio_pa_pins, - (const unsigned char)gpio_pb_pins); - w = w->next; - } -} - - -int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id) -{ - int set_gen_config = 0; - int set_gen_config_ii = 0; - unsigned long int gens; - unsigned long int gens_ii; - struct if_group *grp; - unsigned char group_set; - unsigned long flags; - - (void)cris_io_interface_init(); - - DBG(printk("cris_request_io_interface(%d, \"%s\")\n", ioif, device_id)); - - if ((ioif >= if_max_interfaces) || (ioif < 0)) { - printk(KERN_CRIT "cris_request_io_interface: Bad interface %u submitted for %s\n", - ioif, - device_id); - return -EINVAL; - } - - local_irq_save(flags); - - if (interfaces[ioif].used) { - local_irq_restore(flags); - printk(KERN_CRIT "cris_io_interface: Cannot allocate interface for %s, in use by %s\n", - device_id, - interfaces[ioif].owner); - return -EBUSY; - } - - /* Check that all required groups are free before allocating, */ - group_set = interfaces[ioif].groups; - while (NULL != (grp = get_group(group_set))) { - if (grp->used) { - if (grp->group == group_f) { - if ((if_sync_serial_1 == ioif) || - (if_sync_serial_3 == ioif)) { - if ((grp->owner != if_sync_serial_1) && - (grp->owner != if_sync_serial_3)) { - local_irq_restore(flags); - return -EBUSY; - } - } else if ((if_scsi8_0 == ioif) || - (if_scsi8_1 == ioif)) { - if ((grp->owner != if_scsi8_0) && - (grp->owner != if_scsi8_1)) { - local_irq_restore(flags); - return -EBUSY; - } - } - } else { - local_irq_restore(flags); - return -EBUSY; - } - } - group_set = clear_group_from_set(group_set, grp); - } - - /* Are the required GPIO pins available too? */ - if (((interfaces[ioif].gpio_g_in & gpio_in_pins) != interfaces[ioif].gpio_g_in) || - ((interfaces[ioif].gpio_g_out & gpio_out_pins) != interfaces[ioif].gpio_g_out) || - ((interfaces[ioif].gpio_b & gpio_pb_pins) != interfaces[ioif].gpio_b)) { - printk(KERN_CRIT "cris_request_io_interface: Could not get required pins for interface %u\n", - ioif); - return -EBUSY; - } - - /* All needed I/O pins and pin groups are free, allocate. */ - group_set = interfaces[ioif].groups; - while (NULL != (grp = get_group(group_set))) { - grp->used = 1; - grp->owner = ioif; - group_set = clear_group_from_set(group_set, grp); - } - - gens = genconfig_shadow; - gens_ii = gen_config_ii_shadow; - - set_gen_config = 1; - switch (ioif) - { - /* Begin Non-multiplexed interfaces */ - case if_eth: - /* fall through */ - case if_serial_0: - set_gen_config = 0; - break; - /* End Non-multiplexed interfaces */ - case if_serial_1: - set_gen_config_ii = 1; - SETS(gens_ii, R_GEN_CONFIG_II, sermode1, async); - break; - case if_serial_2: - SETS(gens, R_GEN_CONFIG, ser2, select); - break; - case if_serial_3: - SETS(gens, R_GEN_CONFIG, ser3, select); - set_gen_config_ii = 1; - SETS(gens_ii, R_GEN_CONFIG_II, sermode3, async); - break; - case if_sync_serial_1: - set_gen_config_ii = 1; - SETS(gens_ii, R_GEN_CONFIG_II, sermode1, sync); - break; - case if_sync_serial_3: - SETS(gens, R_GEN_CONFIG, ser3, select); - set_gen_config_ii = 1; - SETS(gens_ii, R_GEN_CONFIG_II, sermode3, sync); - break; - case if_shared_ram: - SETS(gens, R_GEN_CONFIG, mio, select); - break; - case if_shared_ram_w: - SETS(gens, R_GEN_CONFIG, mio_w, select); - break; - case if_par_0: - SETS(gens, R_GEN_CONFIG, par0, select); - break; - case if_par_1: - SETS(gens, R_GEN_CONFIG, par1, select); - break; - case if_par_w: - SETS(gens, R_GEN_CONFIG, par0, select); - SETS(gens, R_GEN_CONFIG, par_w, select); - break; - case if_scsi8_0: - SETS(gens, R_GEN_CONFIG, scsi0, select); - break; - case if_scsi8_1: - SETS(gens, R_GEN_CONFIG, scsi1, select); - break; - case if_scsi_w: - SETS(gens, R_GEN_CONFIG, scsi0, select); - SETS(gens, R_GEN_CONFIG, scsi0w, select); - break; - case if_ata: - SETS(gens, R_GEN_CONFIG, ata, select); - break; - case if_csp: - /* fall through */ - case if_i2c: - set_gen_config = 0; - break; - case if_usb_1: - SETS(gens, R_GEN_CONFIG, usb1, select); - break; - case if_usb_2: - SETS(gens, R_GEN_CONFIG, usb2, select); - break; - case if_gpio_grp_a: - /* GPIO groups are only accounted, don't do configuration changes. */ - /* fall through */ - case if_gpio_grp_b: - /* fall through */ - case if_gpio_grp_c: - /* fall through */ - case if_gpio_grp_d: - /* fall through */ - case if_gpio_grp_e: - /* fall through */ - case if_gpio_grp_f: - set_gen_config = 0; - break; - default: - panic("cris_request_io_interface: Bad interface %u submitted for %s\n", - ioif, - device_id); - } - - interfaces[ioif].used = 1; - interfaces[ioif].owner = (char*)device_id; - - if (set_gen_config) { - volatile int i; - genconfig_shadow = gens; - *R_GEN_CONFIG = genconfig_shadow; - /* Wait 12 cycles before doing any DMA command */ - for(i = 6; i > 0; i--) - nop(); - } - if (set_gen_config_ii) { - gen_config_ii_shadow = gens_ii; - *R_GEN_CONFIG_II = gen_config_ii_shadow; - } - - DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - gpio_in_pins, gpio_out_pins, gpio_pb_pins)); - DBG(printk("grabbing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - interfaces[ioif].gpio_g_in, - interfaces[ioif].gpio_g_out, - interfaces[ioif].gpio_b)); - - gpio_in_pins &= ~interfaces[ioif].gpio_g_in; - gpio_out_pins &= ~interfaces[ioif].gpio_g_out; - gpio_pb_pins &= ~interfaces[ioif].gpio_b; - - DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - gpio_in_pins, gpio_out_pins, gpio_pb_pins)); - - local_irq_restore(flags); - - notify_watchers(); - - return 0; -} - - -void cris_free_io_interface(enum cris_io_interface ioif) -{ - struct if_group *grp; - unsigned char group_set; - unsigned long flags; - - (void)cris_io_interface_init(); - - if ((ioif >= if_max_interfaces) || (ioif < 0)) { - printk(KERN_CRIT "cris_free_io_interface: Bad interface %u\n", - ioif); - return; - } - local_irq_save(flags); - if (!interfaces[ioif].used) { - printk(KERN_CRIT "cris_free_io_interface: Freeing free interface %u\n", - ioif); - local_irq_restore(flags); - return; - } - group_set = interfaces[ioif].groups; - while (NULL != (grp = get_group(group_set))) { - if (grp->group == group_f) { - switch (ioif) - { - case if_sync_serial_1: - if ((grp->owner == if_sync_serial_1) && - interfaces[if_sync_serial_3].used) { - grp->owner = if_sync_serial_3; - } else - grp->used = 0; - break; - case if_sync_serial_3: - if ((grp->owner == if_sync_serial_3) && - interfaces[if_sync_serial_1].used) { - grp->owner = if_sync_serial_1; - } else - grp->used = 0; - break; - case if_scsi8_0: - if ((grp->owner == if_scsi8_0) && - interfaces[if_scsi8_1].used) { - grp->owner = if_scsi8_1; - } else - grp->used = 0; - break; - case if_scsi8_1: - if ((grp->owner == if_scsi8_1) && - interfaces[if_scsi8_0].used) { - grp->owner = if_scsi8_0; - } else - grp->used = 0; - break; - default: - grp->used = 0; - } - } else { - grp->used = 0; - } - group_set = clear_group_from_set(group_set, grp); - } - interfaces[ioif].used = 0; - interfaces[ioif].owner = NULL; - - DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - gpio_in_pins, gpio_out_pins, gpio_pb_pins)); - DBG(printk("freeing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - interfaces[ioif].gpio_g_in, - interfaces[ioif].gpio_g_out, - interfaces[ioif].gpio_b)); - - gpio_in_pins |= interfaces[ioif].gpio_g_in; - gpio_out_pins |= interfaces[ioif].gpio_g_out; - gpio_pb_pins |= interfaces[ioif].gpio_b; - - DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - gpio_in_pins, gpio_out_pins, gpio_pb_pins)); - - local_irq_restore(flags); - - notify_watchers(); -} - -/* Create a bitmask from bit 0 (inclusive) to bit stop_bit - (non-inclusive). stop_bit == 0 returns 0x0 */ -static inline unsigned int create_mask(const unsigned stop_bit) -{ - /* Avoid overflow */ - if (stop_bit >= 32) { - return 0xffffffff; - } - return (1<notify = notify; - w->next = watchers; - watchers = w; - - w->notify((const unsigned int)gpio_in_pins, - (const unsigned int)gpio_out_pins, - (const unsigned char)gpio_pa_pins, - (const unsigned char)gpio_pb_pins); - - return 0; -} - -void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)) -{ - struct watcher *w = watchers, *prev = NULL; - - (void)cris_io_interface_init(); - - while ((NULL != w) && (w->notify != notify)){ - prev = w; - w = w->next; - } - if (NULL != w) { - if (NULL != prev) { - prev->next = w->next; - } else { - watchers = w->next; - } - kfree(w); - return; - } - printk(KERN_WARNING "cris_io_interface_delete_watcher: Deleting unknown watcher 0x%p\n", notify); -} - - -static int cris_io_interface_init(void) -{ - static int first = 1; - int i; - - if (!first) { - return 0; - } - first = 0; - - for (i = 0; i<8; i++) { - gpio_pa_owners[i] = if_unclaimed; - gpio_pb_owners[i] = if_unclaimed; - gpio_pg_owners[i] = if_unclaimed; - } - for (; i<32; i++) { - gpio_pg_owners[i] = if_unclaimed; - } - return 0; -} - - -module_init(cris_io_interface_init); - - -EXPORT_SYMBOL(cris_request_io_interface); -EXPORT_SYMBOL(cris_free_io_interface); -EXPORT_SYMBOL(cris_io_interface_allocate_pins); -EXPORT_SYMBOL(cris_io_interface_free_pins); -EXPORT_SYMBOL(cris_io_interface_register_watcher); -EXPORT_SYMBOL(cris_io_interface_delete_watcher); diff --git a/trunk/arch/cris/arch-v10/kernel/irq.c b/trunk/arch/cris/arch-v10/kernel/irq.c index 4b368a122015..b2f16d6fc871 100644 --- a/trunk/arch/cris/arch-v10/kernel/irq.c +++ b/trunk/arch/cris/arch-v10/kernel/irq.c @@ -1,4 +1,4 @@ -/* $Id: irq.c,v 1.4 2005/01/04 12:22:28 starvik Exp $ +/* $Id: irq.c,v 1.2 2004/06/09 05:30:27 starvik Exp $ * * linux/arch/cris/kernel/irq.c * @@ -12,13 +12,11 @@ */ #include -#include #include #include #include -#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr)); -#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr)); +irqvectptr irq_shortcuts[NR_IRQS]; /* vector of shortcut jumps after the irq prologue */ /* don't use set_int_vector, it bypasses the linux interrupt handlers. it is * global just so that the kernel gdb can use it. @@ -104,52 +102,41 @@ static void (*interrupt[NR_IRQS])(void) = { IRQ31_interrupt }; -static void enable_crisv10_irq(unsigned int irq); - -static unsigned int startup_crisv10_irq(unsigned int irq) -{ - enable_crisv10_irq(irq); - return 0; -} - -#define shutdown_crisv10_irq disable_crisv10_irq - -static void enable_crisv10_irq(unsigned int irq) -{ - unmask_irq(irq); -} - -static void disable_crisv10_irq(unsigned int irq) -{ - mask_irq(irq); -} +static void (*bad_interrupt[NR_IRQS])(void) = { + NULL, NULL, + NULL, bad_IRQ3_interrupt, + bad_IRQ4_interrupt, bad_IRQ5_interrupt, + bad_IRQ6_interrupt, bad_IRQ7_interrupt, + bad_IRQ8_interrupt, bad_IRQ9_interrupt, + bad_IRQ10_interrupt, bad_IRQ11_interrupt, + bad_IRQ12_interrupt, bad_IRQ13_interrupt, + NULL, NULL, + bad_IRQ16_interrupt, bad_IRQ17_interrupt, + bad_IRQ18_interrupt, bad_IRQ19_interrupt, + bad_IRQ20_interrupt, bad_IRQ21_interrupt, + bad_IRQ22_interrupt, bad_IRQ23_interrupt, + bad_IRQ24_interrupt, bad_IRQ25_interrupt, + NULL, NULL, NULL, NULL, NULL, + bad_IRQ31_interrupt +}; -static void ack_crisv10_irq(unsigned int irq) +void arch_setup_irq(int irq) { + set_int_vector(irq, interrupt[irq]); } -static void end_crisv10_irq(unsigned int irq) +void arch_free_irq(int irq) { + set_int_vector(irq, bad_interrupt[irq]); } -static struct hw_interrupt_type crisv10_irq_type = { - .typename = "CRISv10", - .startup = startup_crisv10_irq, - .shutdown = shutdown_crisv10_irq, - .enable = enable_crisv10_irq, - .disable = disable_crisv10_irq, - .ack = ack_crisv10_irq, - .end = end_crisv10_irq, - .set_affinity = NULL -}; - void weird_irq(void); void system_call(void); /* from entry.S */ void do_sigtrap(void); /* from entry.S */ void gdb_handle_breakpoint(void); /* from entry.S */ /* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and - setting the irq vector table. + setting the irq vector table to point to bad_interrupt ptrs. */ void __init @@ -167,15 +154,14 @@ init_IRQ(void) *R_VECT_MASK_CLR = 0xffffffff; + /* clear the shortcut entry points */ + + for(i = 0; i < NR_IRQS; i++) + irq_shortcuts[i] = NULL; + for (i = 0; i < 256; i++) etrax_irv->v[i] = weird_irq; - /* Initialize IRQ handler descriptiors. */ - for(i = 2; i < NR_IRQS; i++) { - irq_desc[i].handler = &crisv10_irq_type; - set_int_vector(i, interrupt[i]); - } - /* the entries in the break vector contain actual code to be executed by the associated break handler, rather than just a jump address. therefore we need to setup a default breakpoint handler @@ -184,6 +170,10 @@ init_IRQ(void) for (i = 0; i < 16; i++) set_break_vector(i, do_sigtrap); + /* set all etrax irq's to the bad handlers */ + for (i = 2; i < NR_IRQS; i++) + set_int_vector(i, bad_interrupt[i]); + /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */ set_int_vector(15, multiple_interrupt); diff --git a/trunk/arch/cris/arch-v10/kernel/kgdb.c b/trunk/arch/cris/arch-v10/kernel/kgdb.c index b72e6a91a639..7d368c877ee9 100644 --- a/trunk/arch/cris/arch-v10/kernel/kgdb.c +++ b/trunk/arch/cris/arch-v10/kernel/kgdb.c @@ -18,10 +18,6 @@ *! Jul 21 1999 Bjorn Wesen eLinux port *! *! $Log: kgdb.c,v $ -*! Revision 1.6 2005/01/14 10:12:17 starvik -*! KGDB on separate port. -*! Console fixes from 2.4. -*! *! Revision 1.5 2004/10/07 13:59:08 starvik *! Corrected call to set_int_vector *! @@ -75,7 +71,7 @@ *! *!--------------------------------------------------------------------------- *! -*! $Id: kgdb.c,v 1.6 2005/01/14 10:12:17 starvik Exp $ +*! $Id: kgdb.c,v 1.5 2004/10/07 13:59:08 starvik Exp $ *! *! (C) Copyright 1999, Axis Communications AB, LUND, SWEDEN *! @@ -229,7 +225,6 @@ #include #include #include -#include #include #include @@ -1349,11 +1344,12 @@ handle_exception (int sigval) } } -/* Performs a complete re-start from scratch. */ +/* The jump is to the address 0x00000002. Performs a complete re-start + from scratch. */ static void kill_restart () { - machine_restart(""); + __asm__ volatile ("jump 2"); } /********************************** Breakpoint *******************************/ @@ -1510,11 +1506,6 @@ asm (" bne goback nop - move.d [reg+0x5E], $r10 ; Get DCCR - btstq 8, $r10 ; Test the U-flag. - bmi goback - nop - ;; ;; Handle the communication ;; diff --git a/trunk/arch/cris/arch-v10/kernel/process.c b/trunk/arch/cris/arch-v10/kernel/process.c index 69e28b4057e8..87ff37790827 100644 --- a/trunk/arch/cris/arch-v10/kernel/process.c +++ b/trunk/arch/cris/arch-v10/kernel/process.c @@ -1,4 +1,4 @@ -/* $Id: process.c,v 1.12 2004/12/27 11:18:32 starvik Exp $ +/* $Id: process.c,v 1.9 2004/10/19 13:07:37 starvik Exp $ * * linux/arch/cris/kernel/process.c * @@ -101,7 +101,6 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) regs.r11 = (unsigned long)fn; regs.r12 = (unsigned long)arg; regs.irp = (unsigned long)kernel_thread_helper; - regs.dccr = 1 << I_DCCR_BITNR; /* Ok, create the new process.. */ return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); diff --git a/trunk/arch/cris/arch-v10/kernel/ptrace.c b/trunk/arch/cris/arch-v10/kernel/ptrace.c index 130dd214e41d..581ecabaae53 100644 --- a/trunk/arch/cris/arch-v10/kernel/ptrace.c +++ b/trunk/arch/cris/arch-v10/kernel/ptrace.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include @@ -87,13 +86,9 @@ sys_ptrace(long request, long pid, long addr, long data) ret = -EPERM; if (request == PTRACE_TRACEME) { - /* are we already being traced? */ if (current->ptrace & PT_PTRACED) goto out; - ret = security_ptrace(current->parent, current); - if (ret) - goto out; - /* set the ptrace bit in the process flags. */ + current->ptrace |= PT_PTRACED; ret = 0; goto out; @@ -212,7 +207,7 @@ sys_ptrace(long request, long pid, long addr, long data) case PTRACE_KILL: ret = 0; - if (child->exit_state == EXIT_ZOMBIE) + if (child->state == TASK_ZOMBIE) break; child->exit_code = SIGKILL; diff --git a/trunk/arch/cris/arch-v10/kernel/shadows.c b/trunk/arch/cris/arch-v10/kernel/shadows.c index 38fd44dfbc5b..561a890a8e4c 100644 --- a/trunk/arch/cris/arch-v10/kernel/shadows.c +++ b/trunk/arch/cris/arch-v10/kernel/shadows.c @@ -1,4 +1,4 @@ -/* $Id: shadows.c,v 1.2 2004/12/13 12:21:51 starvik Exp $ +/* $Id: shadows.c,v 1.1 2001/12/17 13:59:27 bjornw Exp $ * * Various shadow registers. Defines for these are in include/asm-etrax100/io.h */ @@ -6,7 +6,6 @@ /* Shadows for internal Etrax-registers */ unsigned long genconfig_shadow; -unsigned long gen_config_ii_shadow; unsigned long port_g_data_shadow; unsigned char port_pa_dir_shadow; unsigned char port_pa_data_shadow; diff --git a/trunk/arch/cris/arch-v10/kernel/traps.c b/trunk/arch/cris/arch-v10/kernel/traps.c index 34a27ea2052d..da491f438a6e 100644 --- a/trunk/arch/cris/arch-v10/kernel/traps.c +++ b/trunk/arch/cris/arch-v10/kernel/traps.c @@ -1,4 +1,4 @@ -/* $Id: traps.c,v 1.4 2005/04/24 18:47:55 starvik Exp $ +/* $Id: traps.c,v 1.2 2003/07/04 08:27:41 starvik Exp $ * * linux/arch/cris/arch-v10/traps.c * @@ -16,8 +16,6 @@ #include #include -extern int raw_printk(const char *fmt, ...); - void show_registers(struct pt_regs * regs) { @@ -28,18 +26,18 @@ show_registers(struct pt_regs * regs) register. */ unsigned long usp = rdusp(); - raw_printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n", + printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n", regs->irp, regs->srp, regs->dccr, usp, regs->mof ); - raw_printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", + printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", regs->r0, regs->r1, regs->r2, regs->r3); - raw_printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", + printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", regs->r4, regs->r5, regs->r6, regs->r7); - raw_printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", + printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", regs->r8, regs->r9, regs->r10, regs->r11); - raw_printk("r12: %08lx r13: %08lx oR10: %08lx sp: %08lx\n", - regs->r12, regs->r13, regs->orig_r10, regs); - raw_printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE); - raw_printk("Process %s (pid: %d, stackpage=%08lx)\n", + printk("r12: %08lx r13: %08lx oR10: %08lx\n", + regs->r12, regs->r13, regs->orig_r10); + printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE); + printk("Process %s (pid: %d, stackpage=%08lx)\n", current->comm, current->pid, (unsigned long)current); /* @@ -55,7 +53,7 @@ show_registers(struct pt_regs * regs) if (usp != 0) show_stack (NULL, NULL); - raw_printk("\nCode: "); + printk("\nCode: "); if(regs->irp < PAGE_OFFSET) goto bad; @@ -72,16 +70,16 @@ show_registers(struct pt_regs * regs) unsigned char c; if(__get_user(c, &((unsigned char*)regs->irp)[i])) { bad: - raw_printk(" Bad IP value."); + printk(" Bad IP value."); break; } if (i == 0) - raw_printk("(%02x) ", c); + printk("(%02x) ", c); else - raw_printk("%02x ", c); + printk("%02x ", c); } - raw_printk("\n"); + printk("\n"); } } @@ -123,7 +121,7 @@ die_if_kernel(const char * str, struct pt_regs * regs, long err) stop_watchdog(); #endif - raw_printk("%s: %04lx\n", str, err & 0xffff); + printk("%s: %04lx\n", str, err & 0xffff); show_registers(regs); @@ -132,8 +130,3 @@ die_if_kernel(const char * str, struct pt_regs * regs, long err) #endif do_exit(SIGSEGV); } - -void arch_enable_nmi(void) -{ - asm volatile("setf m"); -} diff --git a/trunk/arch/cris/arch-v10/mm/fault.c b/trunk/arch/cris/arch-v10/mm/fault.c index fe2615022b97..6805cdb25a53 100644 --- a/trunk/arch/cris/arch-v10/mm/fault.c +++ b/trunk/arch/cris/arch-v10/mm/fault.c @@ -14,7 +14,6 @@ #include #include #include -#include /* debug of low-level TLB reload */ #undef DEBUG @@ -25,6 +24,8 @@ #define D(x) #endif +extern volatile pgd_t *current_pgd; + extern const struct exception_table_entry *search_exception_tables(unsigned long addr); @@ -45,7 +46,7 @@ handle_mmu_bus_fault(struct pt_regs *regs) int page_id; int acc, inv; #endif - pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id()); + pgd_t* pgd = (pgd_t*)current_pgd; pmd_t *pmd; pte_t pte; int miss, we, writeac; @@ -93,3 +94,24 @@ handle_mmu_bus_fault(struct pt_regs *regs) *R_TLB_LO = pte_val(pte); local_irq_restore(flags); } + +/* Called from arch/cris/mm/fault.c to find fixup code. */ +int +find_fixup_code(struct pt_regs *regs) +{ + const struct exception_table_entry *fixup; + + if ((fixup = search_exception_tables(regs->irp)) != 0) { + /* Adjust the instruction pointer in the stackframe. */ + regs->irp = fixup->fixup; + + /* + * Don't return by restoring the CPU state, so switch + * frame-type. + */ + regs->frametype = CRIS_FRAME_NORMAL; + return 1; + } + + return 0; +} diff --git a/trunk/arch/cris/arch-v10/mm/init.c b/trunk/arch/cris/arch-v10/mm/init.c index ff3481e76dd4..a9f975a9cfb5 100644 --- a/trunk/arch/cris/arch-v10/mm/init.c +++ b/trunk/arch/cris/arch-v10/mm/init.c @@ -42,7 +42,7 @@ paging_init(void) * switch_mm) */ - per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd; + current_pgd = init_mm.pgd; /* initialise the TLB (tlb.c) */ diff --git a/trunk/arch/cris/arch-v10/mm/tlb.c b/trunk/arch/cris/arch-v10/mm/tlb.c index 70a5523eff78..9d06125ff5a2 100644 --- a/trunk/arch/cris/arch-v10/mm/tlb.c +++ b/trunk/arch/cris/arch-v10/mm/tlb.c @@ -139,6 +139,53 @@ flush_tlb_page(struct vm_area_struct *vma, local_irq_restore(flags); } +/* invalidate a page range */ + +void +flush_tlb_range(struct vm_area_struct *vma, + unsigned long start, + unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + int page_id = mm->context.page_id; + int i; + unsigned long flags; + + D(printk("tlb: flush range %p<->%p in context %d (%p)\n", + start, end, page_id, mm)); + + if(page_id == NO_CONTEXT) + return; + + start &= PAGE_MASK; /* probably not necessary */ + end &= PAGE_MASK; /* dito */ + + /* invalidate those TLB entries that match both the mm context + * and the virtual address range + */ + + local_save_flags(flags); + local_irq_disable(); + for(i = 0; i < NUM_TLB_ENTRIES; i++) { + unsigned long tlb_hi, vpn; + *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i); + tlb_hi = *R_TLB_HI; + vpn = tlb_hi & PAGE_MASK; + if (IO_EXTRACT(R_TLB_HI, page_id, tlb_hi) == page_id && + vpn >= start && vpn < end) { + *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) | + IO_FIELD(R_TLB_HI, vpn, i & 0xf ) ); + + *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | + IO_STATE(R_TLB_LO, valid, no ) | + IO_STATE(R_TLB_LO, kernel,no ) | + IO_STATE(R_TLB_LO, we, no ) | + IO_FIELD(R_TLB_LO, pfn, 0 ) ); + } + } + local_irq_restore(flags); +} + /* dump the entire TLB for debug purposes */ #if 0 @@ -190,7 +237,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, * the pgd. */ - per_cpu(current_pgd, smp_processor_id()) = next->pgd; + current_pgd = next->pgd; /* switch context in the MMU */ diff --git a/trunk/arch/cris/arch-v32/Kconfig b/trunk/arch/cris/arch-v32/Kconfig deleted file mode 100644 index 22f0ddc04c50..000000000000 --- a/trunk/arch/cris/arch-v32/Kconfig +++ /dev/null @@ -1,296 +0,0 @@ -config ETRAX_DRAM_VIRTUAL_BASE - hex - depends on ETRAX_ARCH_V32 - default "c0000000" - -config ETRAX_LED1G - string "First green LED bit" - depends on ETRAX_ARCH_V32 - default "PA3" - help - Bit to use for the first green LED (network LED). - Most Axis products use bit A3 here. - -config ETRAX_LED1R - string "First red LED bit" - depends on ETRAX_ARCH_V32 - default "PA4" - help - Bit to use for the first red LED (network LED). - Most Axis products use bit A4 here. - -config ETRAX_LED2G - string "Second green LED bit" - depends on ETRAX_ARCH_V32 - default "PA5" - help - Bit to use for the first green LED (status LED). - Most Axis products use bit A5 here. - -config ETRAX_LED2R - string "Second red LED bit" - depends on ETRAX_ARCH_V32 - default "PA6" - help - Bit to use for the first red LED (network LED). - Most Axis products use bit A6 here. - -config ETRAX_LED3G - string "Third green LED bit" - depends on ETRAX_ARCH_V32 - default "PA7" - help - Bit to use for the first green LED (drive/power LED). - Most Axis products use bit A7 here. - -config ETRAX_LED3R - string "Third red LED bit" - depends on ETRAX_ARCH_V32 - default "PA7" - help - Bit to use for the first red LED (drive/power LED). - Most Axis products use bit A7 here. - -choice - prompt "Product debug-port" - depends on ETRAX_ARCH_V32 - default ETRAX_DEBUG_PORT0 - -config ETRAX_DEBUG_PORT0 - bool "Serial-0" - help - Choose a serial port for the ETRAX debug console. Default to - port 0. - -config ETRAX_DEBUG_PORT1 - bool "Serial-1" - help - Use serial port 1 for the console. - -config ETRAX_DEBUG_PORT2 - bool "Serial-2" - help - Use serial port 2 for the console. - -config ETRAX_DEBUG_PORT3 - bool "Serial-3" - help - Use serial port 3 for the console. - -config ETRAX_DEBUG_PORT_NULL - bool "disabled" - help - Disable serial-port debugging. - -endchoice - -choice - prompt "Kernel GDB port" - depends on ETRAX_KGDB - default ETRAX_KGDB_PORT0 - help - Choose a serial port for kernel debugging. NOTE: This port should - not be enabled under Drivers for built-in interfaces (as it has its - own initialization code) and should not be the same as the debug port. - -config ETRAX_KGDB_PORT0 - bool "Serial-0" - help - Use serial port 0 for kernel debugging. - -config ETRAX_KGDB_PORT1 - bool "Serial-1" - help - Use serial port 1 for kernel debugging. - -config ETRAX_KGDB_PORT2 - bool "Serial-2" - help - Use serial port 2 for kernel debugging. - -config ETRAX_KGDB_PORT3 - bool "Serial-3" - help - Use serial port 3 for kernel debugging. - -endchoice - -config ETRAX_MEM_GRP1_CONFIG - hex "MEM_GRP1_CONFIG" - depends on ETRAX_ARCH_V32 - default "4044a" - help - Waitstates for flash. The default value is suitable for the - standard flashes used in axis products (120 ns). - -config ETRAX_MEM_GRP2_CONFIG - hex "MEM_GRP2_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - Waitstates for SRAM. 0 is a good choice for most Axis products. - -config ETRAX_MEM_GRP3_CONFIG - hex "MEM_GRP3_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - Waitstates for CSP0-3. 0 is a good choice for most Axis products. - It may need to be changed if external devices such as extra - register-mapped LEDs are used. - -config ETRAX_MEM_GRP4_CONFIG - hex "MEM_GRP4_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - Waitstates for CSP4-6. 0 is a good choice for most Axis products. - -config ETRAX_SDRAM_GRP0_CONFIG - hex "SDRAM_GRP0_CONFIG" - depends on ETRAX_ARCH_V32 - default "336" - help - SDRAM configuration for group 0. The value depends on the - hardware configuration. The default value is suitable - for 32 MB organized as two 16 bits chips (e.g. Axis - part number 18550) connected as one 32 bit device (i.e. in - the same group). - -config ETRAX_SDRAM_GRP1_CONFIG - hex "SDRAM_GRP1_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - SDRAM configuration for group 1. The defult value is 0 - because group 1 is not used in the default configuration, - described in the help for SDRAM_GRP0_CONFIG. - -config ETRAX_SDRAM_TIMING - hex "SDRAM_TIMING" - depends on ETRAX_ARCH_V32 - default "104a" - help - SDRAM timing parameters. The default value is ok for - most hardwares but large SDRAMs may require a faster - refresh (a.k.a 8K refresh). The default value implies - 100MHz clock and SDR mode. - -config ETRAX_SDRAM_COMMAND - hex "SDRAM_COMMAND" - depends on ETRAX_ARCH_V32 - default "0" - help - SDRAM command. Should be 0 unless you really know what - you are doing (may be != 0 for unusual address line - mappings such as in a MCM).. - -config ETRAX_DEF_GIO_PA_OE - hex "GIO_PA_OE" - depends on ETRAX_ARCH_V32 - default "1c" - help - Configures the direction of general port A bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PA_OUT - hex "GIO_PA_OUT" - depends on ETRAX_ARCH_V32 - default "00" - help - Configures the initial data for the general port A bits. Most - products should use 00 here. - -config ETRAX_DEF_GIO_PB_OE - hex "GIO_PB_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port B bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PB_OUT - hex "GIO_PB_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port B bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PC_OE - hex "GIO_PC_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port C bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PC_OUT - hex "GIO_PC_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port C bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PD_OE - hex "GIO_PD_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port D bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PD_OUT - hex "GIO_PD_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port D bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PE_OE - hex "GIO_PE_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port E bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PE_OUT - hex "GIO_PE_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port E bits. Most - products should use 00000 here. diff --git a/trunk/arch/cris/arch-v32/boot/Makefile b/trunk/arch/cris/arch-v32/boot/Makefile deleted file mode 100644 index 26f293ab9617..000000000000 --- a/trunk/arch/cris/arch-v32/boot/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# arch/cris/arch-v32/boot/Makefile -# -target = $(target_boot_dir) -src = $(src_boot_dir) - -zImage: compressed/vmlinuz - -compressed/vmlinuz: $(objtree)/vmlinux - @$(MAKE) -f $(src)/compressed/Makefile $(objtree)/vmlinuz - -clean: - rm -f zImage tools/build compressed/vmlinux.out - @$(MAKE) -f $(src)/compressed/Makefile clean diff --git a/trunk/arch/cris/arch-v32/boot/compressed/Makefile b/trunk/arch/cris/arch-v32/boot/compressed/Makefile deleted file mode 100644 index 9f77eda914ba..000000000000 --- a/trunk/arch/cris/arch-v32/boot/compressed/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# lx25/arch/cris/arch-v32/boot/compressed/Makefile -# -# create a compressed vmlinux image from the original vmlinux files and romfs -# - -target = $(target_compressed_dir) -src = $(src_compressed_dir) - -CC = gcc-cris -mlinux -march=v32 -I $(TOPDIR)/include -CFLAGS = -O2 -LD = gcc-cris -mlinux -march=v32 -nostdlib -OBJCOPY = objcopy-cris -OBJCOPYFLAGS = -O binary --remove-section=.bss -OBJECTS = $(target)/head.o $(target)/misc.o - -# files to compress -SYSTEM = $(objtree)/vmlinux.bin - -all: vmlinuz - -$(target)/decompress.bin: $(OBJECTS) - $(LD) -T $(src)/decompress.ld -o $(target)/decompress.o $(OBJECTS) - $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/decompress.o $(target)/decompress.bin - -$(objtree)/vmlinuz: $(target) piggy.img $(target)/decompress.bin - cat $(target)/decompress.bin piggy.img > $(objtree)/vmlinuz - rm -f piggy.img - cp $(objtree)/vmlinuz $(src) - -$(target)/head.o: $(src)/head.S - $(CC) -D__ASSEMBLY__ -c $< -o $@ - -# gzip the kernel image - -piggy.img: $(SYSTEM) - cat $(SYSTEM) | gzip -f -9 > piggy.img - -clean: - rm -f piggy.img $(objtree)/vmlinuz vmlinuz.o decompress.o decompress.bin $(OBJECTS) - diff --git a/trunk/arch/cris/arch-v32/boot/compressed/README b/trunk/arch/cris/arch-v32/boot/compressed/README deleted file mode 100644 index e33691d15c57..000000000000 --- a/trunk/arch/cris/arch-v32/boot/compressed/README +++ /dev/null @@ -1,25 +0,0 @@ -Creation of the self-extracting compressed kernel image (vmlinuz) ------------------------------------------------------------------ -$Id: README,v 1.1 2003/08/21 09:37:03 johana Exp $ - -This can be slightly confusing because it's a process with many steps. - -The kernel object built by the arch/etrax100/Makefile, vmlinux, is split -by that makefile into text and data binary files, vmlinux.text and -vmlinux.data. - -Those files together with a ROM filesystem can be catted together and -burned into a flash or executed directly at the DRAM origin. - -They can also be catted together and compressed with gzip, which is what -happens in this makefile. Together they make up piggy.img. - -The decompressor is built into the file decompress.o. It is turned into -the binary file decompress.bin, which is catted together with piggy.img -into the file vmlinuz. It can be executed in an arbitrary place in flash. - -Be careful - it assumes some things about free locations in DRAM. It -assumes the DRAM starts at 0x40000000 and that it is at least 8 MB, -so it puts its code at 0x40700000, and initial stack at 0x40800000. - --Bjorn diff --git a/trunk/arch/cris/arch-v32/boot/compressed/decompress.ld b/trunk/arch/cris/arch-v32/boot/compressed/decompress.ld deleted file mode 100644 index 3c837feca3ac..000000000000 --- a/trunk/arch/cris/arch-v32/boot/compressed/decompress.ld +++ /dev/null @@ -1,30 +0,0 @@ -/*#OUTPUT_FORMAT(elf32-us-cris) */ -OUTPUT_ARCH (crisv32) - -MEMORY - { - dram : ORIGIN = 0x40700000, - LENGTH = 0x00100000 - } - -SECTIONS -{ - .text : - { - _stext = . ; - *(.text) - *(.rodata) - *(.rodata.*) - _etext = . ; - } > dram - .data : - { - *(.data) - _edata = . ; - } > dram - .bss : - { - *(.bss) - _end = ALIGN( 0x10 ) ; - } > dram -} diff --git a/trunk/arch/cris/arch-v32/boot/compressed/head.S b/trunk/arch/cris/arch-v32/boot/compressed/head.S deleted file mode 100644 index 0c55b83b8287..000000000000 --- a/trunk/arch/cris/arch-v32/boot/compressed/head.S +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Code that sets up the DRAM registers, calls the - * decompressor to unpack the piggybacked kernel, and jumps. - * - * Copyright (C) 1999 - 2003, Axis Communications AB - */ - -#include -#define ASSEMBLER_MACROS_ONLY -#include -#include -#include - -#define RAM_INIT_MAGIC 0x56902387 -#define COMMAND_LINE_MAGIC 0x87109563 - - ;; Exported symbols - - .globl input_data - - .text -start: - di - - ;; Start clocks for used blocks. - move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(config, rw_clk_ctrl, bif, yes) | \ - REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 - move.d $r0, [$r1] - - ;; If booting from NAND flash we first have to copy some - ;; data from NAND flash to internal RAM to get the code - ;; that initializes the SDRAM. Lets copy 20 KB. This - ;; code executes at 0x38010000 if booting from NAND and - ;; we are guaranted that at least 0x200 bytes are good so - ;; lets start from there. The first 8192 bytes in the nand - ;; flash is spliced with zeroes and is thus 16384 bytes. - move.d 0x38010200, $r10 - move.d 0x14200, $r11 ; Start offset in NAND flash 0x10200 + 16384 - move.d 0x5000, $r12 ; Length of copy - - ;; Before this code the tools add a partitiontable so the PC - ;; has an offset from the linked address. -offset1: - lapcq ., $r13 ; get PC - add.d first_copy_complete-offset1, $r13 - -#include "../../lib/nand_init.S" - -first_copy_complete: - ;; Initialze the DRAM registers. - cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? - beq dram_init_finished - nop - -#include "../../lib/dram_init.S" - -dram_init_finished: - lapcq ., $r13 ; get PC - add.d second_copy_complete-dram_init_finished, $r13 - - move.d REG_ADDR(config, regi_config, r_bootsel), $r0 - move.d [$r0], $r0 - and.d REG_MASK(config, r_bootsel, boot_mode), $r0 - cmp.d REG_STATE(config, r_bootsel, boot_mode, nand), $r0 - bne second_copy_complete ; No NAND boot - nop - - ;; Copy 2MB from NAND flash to SDRAM (at 2-4MB into the SDRAM) - move.d 0x40204000, $r10 - move.d 0x8000, $r11 - move.d 0x200000, $r12 - ba copy_nand_to_ram - nop -second_copy_complete: - - ;; Initiate the PA port. - move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 - move.d $r0, [$r1] - - ;; Setup the stack to a suitably high address. - ;; We assume 8 MB is the minimum DRAM and put - ;; the SP at the top for now. - - move.d 0x40800000, $sp - - ;; Figure out where the compressed piggyback image is - ;; in the flash (since we wont try to copy it to DRAM - ;; before unpacking). It is at _edata, but in flash. - ;; Use (_edata - herami) as offset to the current PC. - - move.d REG_ADDR(config, regi_config, r_bootsel), $r0 - move.d [$r0], $r0 - and.d REG_MASK(config, r_bootsel, boot_mode), $r0 - cmp.d REG_STATE(config, r_bootsel, boot_mode, nand), $r0 - beq hereami2 - nop -hereami: - lapcq ., $r5 ; get PC - and.d 0x7fffffff, $r5 ; strip any non-cache bit - move.d $r5, $r0 ; save for later - flash address of 'herami' - add.d _edata, $r5 - sub.d hereami, $r5 ; r5 = flash address of '_edata' - move.d hereami, $r1 ; destination - ba 2f - nop -hereami2: - lapcq ., $r5 ; get PC - and.d 0x00ffffff, $r5 ; strip any non-cache bit - move.d $r5, $r6 - or.d 0x40200000, $r6 - move.d $r6, $r0 ; save for later - flash address of 'herami' - add.d _edata, $r5 - sub.d hereami2, $r5 ; r5 = flash address of '_edata' - add.d 0x40200000, $r5 - move.d hereami2, $r1 ; destination -2: - ;; Copy text+data to DRAM - - move.d _edata, $r2 ; end destination -1: move.w [$r0+], $r3 - move.w $r3, [$r1+] - cmp.d $r2, $r1 - bcs 1b - nop - - move.d input_data, $r0 ; for the decompressor - move.d $r5, [$r0] ; for the decompressor - - ;; Clear the decompressors BSS (between _edata and _end) - - moveq 0, $r0 - move.d _edata, $r1 - move.d _end, $r2 -1: move.w $r0, [$r1+] - cmp.d $r2, $r1 - bcs 1b - nop - - ;; Save command line magic and address. - move.d _cmd_line_magic, $r12 - move.d $r10, [$r12] - move.d _cmd_line_addr, $r12 - move.d $r11, [$r12] - - ;; Do the decompression and save compressed size in _inptr - - jsr decompress_kernel - nop - - ;; Restore command line magic and address. - move.d _cmd_line_magic, $r10 - move.d [$r10], $r10 - move.d _cmd_line_addr, $r11 - move.d [$r11], $r11 - - ;; Put start address of root partition in r9 so the kernel can use it - ;; when mounting from flash - move.d input_data, $r0 - move.d [$r0], $r9 ; flash address of compressed kernel - move.d inptr, $r0 - add.d [$r0], $r9 ; size of compressed kernel - cmp.d 0x40200000, $r9 - blo enter_kernel - nop - sub.d 0x40200000, $r9 - add.d 0x4000, $r9 - -enter_kernel: - ;; Enter the decompressed kernel - move.d RAM_INIT_MAGIC, $r8 ; Tell kernel that DRAM is initialized - jump 0x40004000 ; kernel is linked to this address - nop - - .data - -input_data: - .dword 0 ; used by the decompressor -_cmd_line_magic: - .dword 0 -_cmd_line_addr: - .dword 0 -is_nand_boot: - .dword 0 - -#include "../../lib/hw_settings.S" diff --git a/trunk/arch/cris/arch-v32/boot/compressed/misc.c b/trunk/arch/cris/arch-v32/boot/compressed/misc.c deleted file mode 100644 index 54644238ed59..000000000000 --- a/trunk/arch/cris/arch-v32/boot/compressed/misc.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * misc.c - * - * $Id: misc.c,v 1.8 2005/04/24 18:34:29 starvik Exp $ - * - * This is a collection of several routines from gzip-1.0.3 - * adapted for Linux. - * - * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 - * puts by Nick Holloway 1993, better puts by Martin Mares 1995 - * adoptation for Linux/CRIS Axis Communications AB, 1999 - * - */ - -/* where the piggybacked kernel image expects itself to live. - * it is the same address we use when we network load an uncompressed - * image into DRAM, and it is the address the kernel is linked to live - * at by vmlinux.lds.S - */ - -#define KERNEL_LOAD_ADR 0x40004000 - -#include - -#include -#include -#include -#include - -/* - * gzip declarations - */ - -#define OF(args) args -#define STATIC static - -void* memset(void* s, int c, size_t n); -void* memcpy(void* __dest, __const void* __src, - size_t __n); - -#define memzero(s, n) memset ((s), 0, (n)) - - -typedef unsigned char uch; -typedef unsigned short ush; -typedef unsigned long ulg; - -#define WSIZE 0x8000 /* Window size must be at least 32k, */ - /* and a power of two */ - -static uch *inbuf; /* input buffer */ -static uch window[WSIZE]; /* Sliding window buffer */ - -unsigned inptr = 0; /* index of next byte to be processed in inbuf - * After decompression it will contain the - * compressed size, and head.S will read it. - */ - -static unsigned outcnt = 0; /* bytes in output buffer */ - -/* gzip flag byte */ -#define ASCII_FLAG 0x01 /* bit 0 set: file probably ascii text */ -#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ -#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ -#define COMMENT 0x10 /* bit 4 set: file comment present */ -#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ -#define RESERVED 0xC0 /* bit 6,7: reserved */ - -#define get_byte() inbuf[inptr++] - -/* Diagnostic functions */ -#ifdef DEBUG -# define Assert(cond,msg) {if(!(cond)) error(msg);} -# define Trace(x) fprintf x -# define Tracev(x) {if (verbose) fprintf x ;} -# define Tracevv(x) {if (verbose>1) fprintf x ;} -# define Tracec(c,x) {if (verbose && (c)) fprintf x ;} -# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;} -#else -# define Assert(cond,msg) -# define Trace(x) -# define Tracev(x) -# define Tracevv(x) -# define Tracec(c,x) -# define Tracecv(c,x) -#endif - -static int fill_inbuf(void); -static void flush_window(void); -static void error(char *m); -static void gzip_mark(void **); -static void gzip_release(void **); - -extern char *input_data; /* lives in head.S */ - -static long bytes_out = 0; -static uch *output_data; -static unsigned long output_ptr = 0; - -static void *malloc(int size); -static void free(void *where); -static void error(char *m); -static void gzip_mark(void **); -static void gzip_release(void **); - -static void puts(const char *); - -/* the "heap" is put directly after the BSS ends, at end */ - -extern int _end; -static long free_mem_ptr = (long)&_end; - -#include "../../../../../lib/inflate.c" - -static void *malloc(int size) -{ - void *p; - - if (size <0) error("Malloc error"); - - free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */ - - p = (void *)free_mem_ptr; - free_mem_ptr += size; - - return p; -} - -static void free(void *where) -{ /* Don't care */ -} - -static void gzip_mark(void **ptr) -{ - *ptr = (void *) free_mem_ptr; -} - -static void gzip_release(void **ptr) -{ - free_mem_ptr = (long) *ptr; -} - -/* decompressor info and error messages to serial console */ - -static inline void -serout(const char *s, reg_scope_instances regi_ser) -{ - reg_ser_rs_stat_din rs; - reg_ser_rw_dout dout = {.data = *s}; - - do { - rs = REG_RD(ser, regi_ser, rs_stat_din); - } - while (!rs.tr_rdy);/* Wait for tranceiver. */ - - REG_WR(ser, regi_ser, rw_dout, dout); -} - -static void -puts(const char *s) -{ -#ifndef CONFIG_ETRAX_DEBUG_PORT_NULL - while (*s) { -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - serout(s, regi_ser0); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT1 - serout(s, regi_ser1); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT2 - serout(s, regi_ser2); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT3 - serout(s, regi_ser3); -#endif - *s++; - } -/* CONFIG_ETRAX_DEBUG_PORT_NULL */ -#endif -} - -void* -memset(void* s, int c, size_t n) -{ - int i; - char *ss = (char*)s; - - for (i=0;i> 8); - } - crc = c; - bytes_out += (ulg)outcnt; - output_ptr += (ulg)outcnt; - outcnt = 0; -} - -static void -error(char *x) -{ - puts("\n\n"); - puts(x); - puts("\n\n -- System halted\n"); - - while(1); /* Halt */ -} - -void -setup_normal_output_buffer() -{ - output_data = (char *)KERNEL_LOAD_ADR; -} - -static inline void -serial_setup(reg_scope_instances regi_ser) -{ - reg_ser_rw_xoff xoff; - reg_ser_rw_tr_ctrl tr_ctrl; - reg_ser_rw_rec_ctrl rec_ctrl; - reg_ser_rw_tr_baud_div tr_baud; - reg_ser_rw_rec_baud_div rec_baud; - - /* Turn off XOFF. */ - xoff = REG_RD(ser, regi_ser, rw_xoff); - - xoff.chr = 0; - xoff.automatic = regk_ser_no; - - REG_WR(ser, regi_ser, rw_xoff, xoff); - - /* Set baudrate and stopbits. */ - tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); - rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); - tr_baud = REG_RD(ser, regi_ser, rw_tr_baud_div); - rec_baud = REG_RD(ser, regi_ser, rw_rec_baud_div); - - tr_ctrl.stop_bits = 1; /* 2 stop bits. */ - - /* - * The baudrate setup is a bit fishy, but in the end the tranceiver is - * set to 4800 and the receiver to 115200. The magic value is - * 29.493 MHz. - */ - tr_ctrl.base_freq = regk_ser_f29_493; - rec_ctrl.base_freq = regk_ser_f29_493; - tr_baud.div = (29493000 / 8) / 4800; - rec_baud.div = (29493000 / 8) / 115200; - - REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); - REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud); - REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); - REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud); -} - -void -decompress_kernel() -{ - char revision; - - /* input_data is set in head.S */ - inbuf = input_data; - -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - serial_setup(regi_ser0); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT1 - serial_setup(regi_ser1); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT2 - serial_setup(regi_ser2); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT3 - serial_setup(regi_ser3); -#endif - - setup_normal_output_buffer(); - - makecrc(); - - __asm__ volatile ("move $vr,%0" : "=rm" (revision)); - if (revision < 32) - { - puts("You need an ETRAX FS to run Linux 2.6/crisv32.\n"); - while(1); - } - - puts("Uncompressing Linux...\n"); - gunzip(); - puts("Done. Now booting the kernel.\n"); -} diff --git a/trunk/arch/cris/arch-v32/boot/rescue/Makefile b/trunk/arch/cris/arch-v32/boot/rescue/Makefile deleted file mode 100644 index f668a8198724..000000000000 --- a/trunk/arch/cris/arch-v32/boot/rescue/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -# -# Makefile for rescue code -# -target = $(target_rescue_dir) -src = $(src_rescue_dir) - -CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE) -CFLAGS = -O2 -LD = gcc-cris -mlinux -march=v32 -nostdlib -OBJCOPY = objcopy-cris -OBJCOPYFLAGS = -O binary --remove-section=.bss - -all: $(target)/rescue.bin - -rescue: rescue.bin - # do nothing - -$(target)/rescue.bin: $(target) $(target)/head.o - $(LD) -T $(src)/rescue.ld -o $(target)/rescue.o $(target)/head.o - $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/rescue.o $(target)/rescue.bin - cp -p $(target)/rescue.bin $(objtree) - -$(target): - mkdir -p $(target) - -$(target)/head.o: $(src)/head.S - $(CC) -D__ASSEMBLY__ -c $< -o $*.o - -clean: - rm -f $(target)/*.o $(target)/*.bin - -fastdep: - -modules: - -modules-install: diff --git a/trunk/arch/cris/arch-v32/boot/rescue/head.S b/trunk/arch/cris/arch-v32/boot/rescue/head.S deleted file mode 100644 index 61ede5f30f99..000000000000 --- a/trunk/arch/cris/arch-v32/boot/rescue/head.S +++ /dev/null @@ -1,39 +0,0 @@ -/* $Id: head.S,v 1.4 2004/11/01 16:10:28 starvik Exp $ - * - * This used to be the rescue code but now that is handled by the - * RedBoot based RFL instead. Nothing to see here, move along. - */ - -#include -#include -#include - - .text - - ;; Start clocks for used blocks. - move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(config, rw_clk_ctrl, bif, yes) | \ - REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 - move.d $r0, [$r1] - - ;; Copy 68KB NAND flash to Internal RAM (if NAND boot) - move.d 0x38004000, $r10 - move.d 0x8000, $r11 - move.d 0x11000, $r12 - move.d copy_complete, $r13 - and.d 0x000fffff, $r13 - or.d 0x38000000, $r13 - -#include "../../lib/nand_init.S" - - ;; No NAND found - move.d CONFIG_ETRAX_PTABLE_SECTOR, $r10 - jump $r10 ; Jump to decompresser - nop - -copy_complete: - move.d 0x38000000 + CONFIG_ETRAX_PTABLE_SECTOR, $r10 - jump $r10 ; Jump to decompresser - nop diff --git a/trunk/arch/cris/arch-v32/boot/rescue/rescue.ld b/trunk/arch/cris/arch-v32/boot/rescue/rescue.ld deleted file mode 100644 index 42b11aa122b2..000000000000 --- a/trunk/arch/cris/arch-v32/boot/rescue/rescue.ld +++ /dev/null @@ -1,20 +0,0 @@ -MEMORY - { - flash : ORIGIN = 0x00000000, - LENGTH = 0x00100000 - } - -SECTIONS -{ - .text : - { - stext = . ; - *(.text) - etext = . ; - } > flash - .data : - { - *(.data) - edata = . ; - } > flash -} diff --git a/trunk/arch/cris/arch-v32/drivers/Kconfig b/trunk/arch/cris/arch-v32/drivers/Kconfig deleted file mode 100644 index a33097f95362..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/Kconfig +++ /dev/null @@ -1,625 +0,0 @@ -config ETRAX_ETHERNET - bool "Ethernet support" - depends on ETRAX_ARCH_V32 - select NET_ETHERNET - help - This option enables the ETRAX FS built-in 10/100Mbit Ethernet - controller. - -config ETRAX_ETHERNET_HW_CSUM - bool "Hardware accelerated ethernet checksum and scatter/gather" - depends on ETRAX_ETHERNET - depends on ETRAX_STREAMCOPROC - default y - help - Hardware acceleration of checksumming and scatter/gather - -config ETRAX_ETHERNET_IFACE0 - depends on ETRAX_ETHERNET - bool "Enable network interface 0" - -config ETRAX_ETHERNET_IFACE1 - depends on ETRAX_ETHERNET - bool "Enable network interface 1 (uses DMA6 and DMA7)" - -choice - prompt "Network LED behavior" - depends on ETRAX_ETHERNET - default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY - -config ETRAX_NETWORK_LED_ON_WHEN_LINK - bool "LED_on_when_link" - help - Selecting LED_on_when_link will light the LED when there is a - connection and will flash off when there is activity. - - Selecting LED_on_when_activity will light the LED only when - there is activity. - - This setting will also affect the behaviour of other activity LEDs - e.g. Bluetooth. - -config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY - bool "LED_on_when_activity" - help - Selecting LED_on_when_link will light the LED when there is a - connection and will flash off when there is activity. - - Selecting LED_on_when_activity will light the LED only when - there is activity. - - This setting will also affect the behaviour of other activity LEDs - e.g. Bluetooth. - -endchoice - -config ETRAXFS_SERIAL - bool "Serial-port support" - depends on ETRAX_ARCH_V32 - help - Enables the ETRAX FS serial driver for ser0 (ttyS0) - You probably want this enabled. - -config ETRAX_SERIAL_PORT0 - bool "Serial port 0 enabled" - depends on ETRAXFS_SERIAL - help - Enables the ETRAX FS serial driver for ser0 (ttyS0) - Normally you want this on. You can control what DMA channels to use - if you do not need DMA to something else. - ser0 can use dma4 or dma6 for output and dma5 or dma7 for input. - -choice - prompt "Ser0 DMA in channel " - depends on ETRAX_SERIAL_PORT0 - default ETRAX_SERIAL_PORT0_NO_DMA_IN - help - What DMA channel to use for ser0. - - -config ETRAX_SERIAL_PORT0_NO_DMA_IN - bool "Ser0 uses no DMA for input" - help - Do not use DMA for ser0 input. - -config ETRAX_SERIAL_PORT0_DMA7_IN - bool "Ser0 uses DMA7 for input" - depends on ETRAX_SERIAL_PORT0 - help - Enables the DMA7 input channel for ser0 (ttyS0). - If you do not enable DMA, an interrupt for each character will be - used when receiveing data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -choice - prompt "Ser0 DMA out channel" - depends on ETRAX_SERIAL_PORT0 - default ETRAX_SERIAL_PORT0_NO_DMA_OUT - -config ETRAX_SERIAL_PORT0_NO_DMA_OUT - bool "Ser0 uses no DMA for output" - help - Do not use DMA for ser0 output. - -config ETRAX_SERIAL_PORT0_DMA6_OUT - bool "Ser0 uses DMA6 for output" - depends on ETRAX_SERIAL_PORT0 - help - Enables the DMA6 output channel for ser0 (ttyS0). - If you do not enable DMA, an interrupt for each character will be - used when transmitting data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -config ETRAX_SER0_DTR_BIT - string "Ser 0 DTR bit (empty = not used)" - depends on ETRAX_SERIAL_PORT0 - -config ETRAX_SER0_RI_BIT - string "Ser 0 RI bit (empty = not used)" - depends on ETRAX_SERIAL_PORT0 - -config ETRAX_SER0_DSR_BIT - string "Ser 0 DSR bit (empty = not used)" - depends on ETRAX_SERIAL_PORT0 - -config ETRAX_SER0_CD_BIT - string "Ser 0 CD bit (empty = not used)" - depends on ETRAX_SERIAL_PORT0 - -config ETRAX_SERIAL_PORT1 - bool "Serial port 1 enabled" - depends on ETRAXFS_SERIAL - help - Enables the ETRAX FS serial driver for ser1 (ttyS1). - -choice - prompt "Ser1 DMA in channel " - depends on ETRAX_SERIAL_PORT1 - default ETRAX_SERIAL_PORT1_NO_DMA_IN - help - What DMA channel to use for ser1. - - -config ETRAX_SERIAL_PORT1_NO_DMA_IN - bool "Ser1 uses no DMA for input" - help - Do not use DMA for ser1 input. - -config ETRAX_SERIAL_PORT1_DMA5_IN - bool "Ser1 uses DMA5 for input" - depends on ETRAX_SERIAL_PORT1 - help - Enables the DMA5 input channel for ser1 (ttyS1). - If you do not enable DMA, an interrupt for each character will be - used when receiveing data. - Normally you want this on, unless you use the DMA channel for - something else. - -endchoice - -choice - prompt "Ser1 DMA out channel " - depends on ETRAX_SERIAL_PORT1 - default ETRAX_SERIAL_PORT1_NO_DMA_OUT - help - What DMA channel to use for ser1. - -config ETRAX_SERIAL_PORT1_NO_DMA_OUT - bool "Ser1 uses no DMA for output" - help - Do not use DMA for ser1 output. - -config ETRAX_SERIAL_PORT1_DMA4_OUT - bool "Ser1 uses DMA4 for output" - depends on ETRAX_SERIAL_PORT1 - help - Enables the DMA4 output channel for ser1 (ttyS1). - If you do not enable DMA, an interrupt for each character will be - used when transmitting data. - Normally you want this on, unless you use the DMA channel for - something else. - -endchoice - -config ETRAX_SER1_DTR_BIT - string "Ser 1 DTR bit (empty = not used)" - depends on ETRAX_SERIAL_PORT1 - -config ETRAX_SER1_RI_BIT - string "Ser 1 RI bit (empty = not used)" - depends on ETRAX_SERIAL_PORT1 - -config ETRAX_SER1_DSR_BIT - string "Ser 1 DSR bit (empty = not used)" - depends on ETRAX_SERIAL_PORT1 - -config ETRAX_SER1_CD_BIT - string "Ser 1 CD bit (empty = not used)" - depends on ETRAX_SERIAL_PORT1 - -config ETRAX_SERIAL_PORT2 - bool "Serial port 2 enabled" - depends on ETRAXFS_SERIAL - help - Enables the ETRAX FS serial driver for ser2 (ttyS2). - -choice - prompt "Ser2 DMA in channel " - depends on ETRAX_SERIAL_PORT2 - default ETRAX_SERIAL_PORT2_NO_DMA_IN - help - What DMA channel to use for ser2. - - -config ETRAX_SERIAL_PORT2_NO_DMA_IN - bool "Ser2 uses no DMA for input" - help - Do not use DMA for ser2 input. - -config ETRAX_SERIAL_PORT2_DMA3_IN - bool "Ser2 uses DMA3 for input" - depends on ETRAX_SERIAL_PORT2 - help - Enables the DMA3 input channel for ser2 (ttyS2). - If you do not enable DMA, an interrupt for each character will be - used when receiveing data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -choice - prompt "Ser2 DMA out channel" - depends on ETRAX_SERIAL_PORT2 - default ETRAX_SERIAL_PORT2_NO_DMA_OUT - -config ETRAX_SERIAL_PORT2_NO_DMA_OUT - bool "Ser2 uses no DMA for output" - help - Do not use DMA for ser2 output. - -config ETRAX_SERIAL_PORT2_DMA2_OUT - bool "Ser2 uses DMA2 for output" - depends on ETRAX_SERIAL_PORT2 - help - Enables the DMA2 output channel for ser2 (ttyS2). - If you do not enable DMA, an interrupt for each character will be - used when transmitting data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -config ETRAX_SER2_DTR_BIT - string "Ser 2 DTR bit (empty = not used)" - depends on ETRAX_SERIAL_PORT2 - -config ETRAX_SER2_RI_BIT - string "Ser 2 RI bit (empty = not used)" - depends on ETRAX_SERIAL_PORT2 - -config ETRAX_SER2_DSR_BIT - string "Ser 2 DSR bit (empty = not used)" - depends on ETRAX_SERIAL_PORT2 - -config ETRAX_SER2_CD_BIT - string "Ser 2 CD bit (empty = not used)" - depends on ETRAX_SERIAL_PORT2 - -config ETRAX_SERIAL_PORT3 - bool "Serial port 3 enabled" - depends on ETRAXFS_SERIAL - help - Enables the ETRAX FS serial driver for ser3 (ttyS3). - -choice - prompt "Ser3 DMA in channel " - depends on ETRAX_SERIAL_PORT3 - default ETRAX_SERIAL_PORT3_NO_DMA_IN - help - What DMA channel to use for ser3. - - -config ETRAX_SERIAL_PORT3_NO_DMA_IN - bool "Ser3 uses no DMA for input" - help - Do not use DMA for ser3 input. - -config ETRAX_SERIAL_PORT3_DMA9_IN - bool "Ser3 uses DMA9 for input" - depends on ETRAX_SERIAL_PORT3 - help - Enables the DMA9 input channel for ser3 (ttyS3). - If you do not enable DMA, an interrupt for each character will be - used when receiveing data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -choice - prompt "Ser3 DMA out channel" - depends on ETRAX_SERIAL_PORT3 - default ETRAX_SERIAL_PORT3_NO_DMA_OUT - -config ETRAX_SERIAL_PORT3_NO_DMA_OUT - bool "Ser3 uses no DMA for output" - help - Do not use DMA for ser3 output. - -config ETRAX_SERIAL_PORT3_DMA8_OUT - bool "Ser3 uses DMA8 for output" - depends on ETRAX_SERIAL_PORT3 - help - Enables the DMA8 output channel for ser3 (ttyS3). - If you do not enable DMA, an interrupt for each character will be - used when transmitting data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -config ETRAX_SER3_DTR_BIT - string "Ser 3 DTR bit (empty = not used)" - depends on ETRAX_SERIAL_PORT3 - -config ETRAX_SER3_RI_BIT - string "Ser 3 RI bit (empty = not used)" - depends on ETRAX_SERIAL_PORT3 - -config ETRAX_SER3_DSR_BIT - string "Ser 3 DSR bit (empty = not used)" - depends on ETRAX_SERIAL_PORT3 - -config ETRAX_SER3_CD_BIT - string "Ser 3 CD bit (empty = not used)" - depends on ETRAX_SERIAL_PORT3 - -config ETRAX_RS485 - bool "RS-485 support" - depends on ETRAX_SERIAL - help - Enables support for RS-485 serial communication. For a primer on - RS-485, see . - -config ETRAX_RS485_DISABLE_RECEIVER - bool "Disable serial receiver" - depends on ETRAX_RS485 - help - It is necessary to disable the serial receiver to avoid serial - loopback. Not all products are able to do this in software only. - Axis 2400/2401 must disable receiver. - -config ETRAX_AXISFLASHMAP - bool "Axis flash-map support" - depends on ETRAX_ARCH_V32 - select MTD - select MTD_CFI - select MTD_CFI_AMDSTD - select MTD_OBSOLETE_CHIPS - select MTD_AMDSTD - select MTD_CHAR - select MTD_BLOCK - select MTD_PARTITIONS - select MTD_CONCAT - select MTD_COMPLEX_MAPPINGS - help - This option enables MTD mapping of flash devices. Needed to use - flash memories. If unsure, say Y. - -config ETRAX_SYNCHRONOUS_SERIAL - bool "Synchronous serial-port support" - depends on ETRAX_ARCH_V32 - help - Enables the ETRAX FS synchronous serial driver. - -config ETRAX_SYNCHRONOUS_SERIAL_PORT0 - bool "Synchronous serial port 0 enabled" - depends on ETRAX_SYNCHRONOUS_SERIAL - help - Enabled synchronous serial port 0. - -config ETRAX_SYNCHRONOUS_SERIAL0_DMA - bool "Enable DMA on synchronous serial port 0." - depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0 - help - A synchronous serial port can run in manual or DMA mode. - Selecting this option will make it run in DMA mode. - -config ETRAX_SYNCHRONOUS_SERIAL_PORT1 - bool "Synchronous serial port 1 enabled" - depends on ETRAX_SYNCHRONOUS_SERIAL - help - Enabled synchronous serial port 1. - -config ETRAX_SYNCHRONOUS_SERIAL1_DMA - bool "Enable DMA on synchronous serial port 1." - depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1 - help - A synchronous serial port can run in manual or DMA mode. - Selecting this option will make it run in DMA mode. - -config ETRAX_PTABLE_SECTOR - int "Byte-offset of partition table sector" - depends on ETRAX_AXISFLASHMAP - default "65536" - help - Byte-offset of the partition table in the first flash chip. - The default value is 64kB and should not be changed unless - you know exactly what you are doing. The only valid reason - for changing this is when the flash block size is bigger - than 64kB (e.g. when using two parallel 16 bit flashes). - -config ETRAX_NANDFLASH - bool "NAND flash support" - depends on ETRAX_ARCH_V32 - select MTD_NAND - select MTD_NAND_IDS - help - This option enables MTD mapping of NAND flash devices. Needed to use - NAND flash memories. If unsure, say Y. - -config ETRAX_I2C - bool "I2C driver" - depends on ETRAX_ARCH_V32 - help - This option enabled the I2C driver used by e.g. the RTC driver. - -config ETRAX_I2C_DATA_PORT - string "I2C data pin" - depends on ETRAX_I2C - help - The pin to use for I2C data. - -config ETRAX_I2C_CLK_PORT - string "I2C clock pin" - depends on ETRAX_I2C - help - The pin to use for I2C clock. - -config ETRAX_RTC - bool "Real Time Clock support" - depends on ETRAX_ARCH_V32 - help - Enabled RTC support. - -choice - prompt "RTC chip" - depends on ETRAX_RTC - default ETRAX_PCF8563 - -config ETRAX_PCF8563 - bool "PCF8563" - help - Philips PCF8563 RTC - -endchoice - -config ETRAX_GPIO - bool "GPIO support" - depends on ETRAX_ARCH_V32 - ---help--- - Enables the ETRAX general port device (major 120, minors 0-4). - You can use this driver to access the general port bits. It supports - these ioctl's: - #include - fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob - ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set); - ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear); - err = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READ_INBITS), &val); - Remember that you need to setup the port directions appropriately in - the General configuration. - -config ETRAX_PA_BUTTON_BITMASK - hex "PA-buttons bitmask" - depends on ETRAX_GPIO - default "0x02" - help - This is a bitmask (8 bits) with information about what bits on PA - that are used for buttons. - Most products has a so called TEST button on PA1, if that is true - use 0x02 here. - Use 00 if there are no buttons on PA. - If the bitmask is <> 00 a button driver will be included in the gpio - driver. ETRAX general I/O support must be enabled. - -config ETRAX_PA_CHANGEABLE_DIR - hex "PA user changeable dir mask" - depends on ETRAX_GPIO - default "0x00" - help - This is a bitmask (8 bits) with information of what bits in PA that a - user can change direction on using ioctl's. - Bit set = changeable. - You probably want 0x00 here, but it depends on your hardware. - -config ETRAX_PA_CHANGEABLE_BITS - hex "PA user changeable bits mask" - depends on ETRAX_GPIO - default "0x00" - help - This is a bitmask (8 bits) with information of what bits in PA - that a user can change the value on using ioctl's. - Bit set = changeable. - -config ETRAX_PB_CHANGEABLE_DIR - hex "PB user changeable dir mask" - depends on ETRAX_GPIO - default "0x00000" - help - This is a bitmask (18 bits) with information of what bits in PB - that a user can change direction on using ioctl's. - Bit set = changeable. - You probably want 0x00000 here, but it depends on your hardware. - -config ETRAX_PB_CHANGEABLE_BITS - hex "PB user changeable bits mask" - depends on ETRAX_GPIO - default "0x00000" - help - This is a bitmask (18 bits) with information of what bits in PB - that a user can change the value on using ioctl's. - Bit set = changeable. - -config ETRAX_PC_CHANGEABLE_DIR - hex "PC user changeable dir mask" - depends on ETRAX_GPIO - default "0x00000" - help - This is a bitmask (18 bits) with information of what bits in PC - that a user can change direction on using ioctl's. - Bit set = changeable. - You probably want 0x00000 here, but it depends on your hardware. - -config ETRAX_PC_CHANGEABLE_BITS - hex "PC user changeable bits mask" - depends on ETRAX_GPIO - default "0x00000" - help - This is a bitmask (18 bits) with information of what bits in PC - that a user can change the value on using ioctl's. - Bit set = changeable. - -config ETRAX_PD_CHANGEABLE_DIR - hex "PD user changeable dir mask" - depends on ETRAX_GPIO - default "0x00000" - help - This is a bitmask (18 bits) with information of what bits in PD - that a user can change direction on using ioctl's. - Bit set = changeable. - You probably want 0x00000 here, but it depends on your hardware. - -config ETRAX_PD_CHANGEABLE_BITS - hex "PD user changeable bits mask" - depends on ETRAX_GPIO - default "0x00000" - help - This is a bitmask (18 bits) with information of what bits in PD - that a user can change the value on using ioctl's. - Bit set = changeable. - -config ETRAX_PE_CHANGEABLE_DIR - hex "PE user changeable dir mask" - depends on ETRAX_GPIO - default "0x00000" - help - This is a bitmask (18 bits) with information of what bits in PE - that a user can change direction on using ioctl's. - Bit set = changeable. - You probably want 0x00000 here, but it depends on your hardware. - -config ETRAX_PE_CHANGEABLE_BITS - hex "PE user changeable bits mask" - depends on ETRAX_GPIO - default "0x00000" - help - This is a bitmask (18 bits) with information of what bits in PE - that a user can change the value on using ioctl's. - Bit set = changeable. - -config ETRAX_IDE - bool "ATA/IDE support" - depends on ETRAX_ARCH_V32 - select IDE - select BLK_DEV_IDE - select BLK_DEV_IDEDISK - select BLK_DEV_IDECD - select BLK_DEV_IDEDMA - help - Enables the ETRAX IDE driver. - -config ETRAX_CARDBUS - bool "Cardbus support" - depends on ETRAX_ARCH_V32 - select PCCARD - select CARDBUS - select HOTPLUG - select PCCARD_NONSTATIC - help - Enabled the ETRAX Carbus driver. - -config PCI - bool - depends on ETRAX_CARDBUS - default y - -config ETRAX_IOP_FW_LOAD - tristate "IO-processor hotplug firmware loading support" - depends on ETRAX_ARCH_V32 - select FW_LOADER - help - Enables IO-processor hotplug firmware loading support. - -config ETRAX_STREAMCOPROC - tristate "Stream co-processor driver enabled" - depends on ETRAX_ARCH_V32 - help - This option enables a driver for the stream co-processor - for cryptographic operations. diff --git a/trunk/arch/cris/arch-v32/drivers/Makefile b/trunk/arch/cris/arch-v32/drivers/Makefile deleted file mode 100644 index a359cd20ae75..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Makefile for Etrax-specific drivers -# - -obj-$(CONFIG_ETRAX_STREAMCOPROC) += cryptocop.o -obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o -obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o -obj-$(CONFIG_ETRAX_GPIO) += gpio.o -obj-$(CONFIG_ETRAX_IOP_FW_LOAD) += iop_fw_load.o -obj-$(CONFIG_ETRAX_PCF8563) += pcf8563.o -obj-$(CONFIG_ETRAX_I2C) += i2c.o -obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o -obj-$(CONFIG_PCI) += pci/ diff --git a/trunk/arch/cris/arch-v32/drivers/axisflashmap.c b/trunk/arch/cris/arch-v32/drivers/axisflashmap.c deleted file mode 100644 index 78ed52b1cdac..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/axisflashmap.c +++ /dev/null @@ -1,455 +0,0 @@ -/* - * Physical mapping layer for MTD using the Axis partitiontable format - * - * Copyright (c) 2001, 2002, 2003 Axis Communications AB - * - * This file is under the GPL. - * - * First partition is always sector 0 regardless of if we find a partitiontable - * or not. In the start of the next sector, there can be a partitiontable that - * tells us what other partitions to define. If there isn't, we use a default - * partition split defined below. - * - * Copy of os/lx25/arch/cris/arch-v10/drivers/axisflashmap.c 1.5 - * with minor changes. - * - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) - -#define FLASH_UNCACHED_ADDR KSEG_E -#define FLASH_CACHED_ADDR KSEG_F - -#if CONFIG_ETRAX_FLASH_BUSWIDTH==1 -#define flash_data __u8 -#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2 -#define flash_data __u16 -#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4 -#define flash_data __u16 -#endif - -/* From head.S */ -extern unsigned long romfs_start, romfs_length, romfs_in_flash; - -/* The master mtd for the entire flash. */ -struct mtd_info* axisflash_mtd = NULL; - -/* Map driver functions. */ - -static map_word flash_read(struct map_info *map, unsigned long ofs) -{ - map_word tmp; - tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs); - return tmp; -} - -static void flash_copy_from(struct map_info *map, void *to, - unsigned long from, ssize_t len) -{ - memcpy(to, (void *)(map->map_priv_1 + from), len); -} - -static void flash_write(struct map_info *map, map_word d, unsigned long adr) -{ - *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0]; -} - -/* - * The map for chip select e0. - * - * We run into tricky coherence situations if we mix cached with uncached - * accesses to we only use the uncached version here. - * - * The size field is the total size where the flash chips may be mapped on the - * chip select. MTD probes should find all devices there and it does not matter - * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD - * probes will ignore them. - * - * The start address in map_priv_1 is in virtual memory so we cannot use - * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start - * address of cse0. - */ -static struct map_info map_cse0 = { - .name = "cse0", - .size = MEM_CSE0_SIZE, - .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, - .read = flash_read, - .copy_from = flash_copy_from, - .write = flash_write, - .map_priv_1 = FLASH_UNCACHED_ADDR -}; - -/* - * The map for chip select e1. - * - * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong - * address, but there isn't. - */ -static struct map_info map_cse1 = { - .name = "cse1", - .size = MEM_CSE1_SIZE, - .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, - .read = flash_read, - .copy_from = flash_copy_from, - .write = flash_write, - .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE -}; - -/* If no partition-table was found, we use this default-set. */ -#define MAX_PARTITIONS 7 -#define NUM_DEFAULT_PARTITIONS 3 - -/* - * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the - * size of one flash block and "filesystem"-partition needs 5 blocks to be able - * to use JFFS. - */ -static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = { - { - .name = "boot firmware", - .size = CONFIG_ETRAX_PTABLE_SECTOR, - .offset = 0 - }, - { - .name = "kernel", - .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR), - .offset = CONFIG_ETRAX_PTABLE_SECTOR - }, - { - .name = "filesystem", - .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR, - .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR) - } -}; - -/* Initialize the ones normally used. */ -static struct mtd_partition axis_partitions[MAX_PARTITIONS] = { - { - .name = "part0", - .size = CONFIG_ETRAX_PTABLE_SECTOR, - .offset = 0 - }, - { - .name = "part1", - .size = 0, - .offset = 0 - }, - { - .name = "part2", - .size = 0, - .offset = 0 - }, - { - .name = "part3", - .size = 0, - .offset = 0 - }, - { - .name = "part4", - .size = 0, - .offset = 0 - }, - { - .name = "part5", - .size = 0, - .offset = 0 - }, - { - .name = "part6", - .size = 0, - .offset = 0 - }, -}; - -/* - * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash - * chips in that order (because the amd_flash-driver is faster). - */ -static struct mtd_info *probe_cs(struct map_info *map_cs) -{ - struct mtd_info *mtd_cs = NULL; - - printk(KERN_INFO - "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n", - map_cs->name, map_cs->size, map_cs->map_priv_1); - -#ifdef CONFIG_MTD_AMDSTD - mtd_cs = do_map_probe("amd_flash", map_cs); -#endif -#ifdef CONFIG_MTD_CFI - if (!mtd_cs) { - mtd_cs = do_map_probe("cfi_probe", map_cs); - } -#endif - - return mtd_cs; -} - -/* - * Probe each chip select individually for flash chips. If there are chips on - * both cse0 and cse1, the mtd_info structs will be concatenated to one struct - * so that MTD partitions can cross chip boundries. - * - * The only known restriction to how you can mount your chips is that each - * chip select must hold similar flash chips. But you need external hardware - * to do that anyway and you can put totally different chips on cse0 and cse1 - * so it isn't really much of a restriction. - */ -extern struct mtd_info* __init crisv32_nand_flash_probe (void); -static struct mtd_info *flash_probe(void) -{ - struct mtd_info *mtd_cse0; - struct mtd_info *mtd_cse1; - struct mtd_info *mtd_nand = NULL; - struct mtd_info *mtd_total; - struct mtd_info *mtds[3]; - int count = 0; - - if ((mtd_cse0 = probe_cs(&map_cse0)) != NULL) - mtds[count++] = mtd_cse0; - if ((mtd_cse1 = probe_cs(&map_cse1)) != NULL) - mtds[count++] = mtd_cse1; - -#ifdef CONFIG_ETRAX_NANDFLASH - if ((mtd_nand = crisv32_nand_flash_probe()) != NULL) - mtds[count++] = mtd_nand; -#endif - - if (!mtd_cse0 && !mtd_cse1 && !mtd_nand) { - /* No chip found. */ - return NULL; - } - - if (count > 1) { -#ifdef CONFIG_MTD_CONCAT - /* Since the concatenation layer adds a small overhead we - * could try to figure out if the chips in cse0 and cse1 are - * identical and reprobe the whole cse0+cse1 window. But since - * flash chips are slow, the overhead is relatively small. - * So we use the MTD concatenation layer instead of further - * complicating the probing procedure. - */ - mtd_total = mtd_concat_create(mtds, - count, - "cse0+cse1+nand"); -#else - printk(KERN_ERR "%s and %s: Cannot concatenate due to kernel " - "(mis)configuration!\n", map_cse0.name, map_cse1.name); - mtd_toal = NULL; -#endif - if (!mtd_total) { - printk(KERN_ERR "%s and %s: Concatenation failed!\n", - map_cse0.name, map_cse1.name); - - /* The best we can do now is to only use what we found - * at cse0. - */ - mtd_total = mtd_cse0; - map_destroy(mtd_cse1); - } - } else { - mtd_total = mtd_cse0? mtd_cse0 : mtd_cse1 ? mtd_cse1 : mtd_nand; - - } - - return mtd_total; -} - -extern unsigned long crisv32_nand_boot; -extern unsigned long crisv32_nand_cramfs_offset; - -/* - * Probe the flash chip(s) and, if it succeeds, read the partition-table - * and register the partitions with MTD. - */ -static int __init init_axis_flash(void) -{ - struct mtd_info *mymtd; - int err = 0; - int pidx = 0; - struct partitiontable_head *ptable_head = NULL; - struct partitiontable_entry *ptable; - int use_default_ptable = 1; /* Until proven otherwise. */ - const char *pmsg = KERN_INFO " /dev/flash%d at 0x%08x, size 0x%08x\n"; - static char page[512]; - size_t len; - -#ifndef CONFIG_ETRAXFS_SIM - mymtd = flash_probe(); - mymtd->read(mymtd, CONFIG_ETRAX_PTABLE_SECTOR, 512, &len, page); - ptable_head = (struct partitiontable_head *)(page + PARTITION_TABLE_OFFSET); - - if (!mymtd) { - /* There's no reason to use this module if no flash chip can - * be identified. Make sure that's understood. - */ - printk(KERN_INFO "axisflashmap: Found no flash chip.\n"); - } else { - printk(KERN_INFO "%s: 0x%08x bytes of flash memory.\n", - mymtd->name, mymtd->size); - axisflash_mtd = mymtd; - } - - if (mymtd) { - mymtd->owner = THIS_MODULE; - } - pidx++; /* First partition is always set to the default. */ - - if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC) - && (ptable_head->size < - (MAX_PARTITIONS * sizeof(struct partitiontable_entry) + - PARTITIONTABLE_END_MARKER_SIZE)) - && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) + - ptable_head->size - - PARTITIONTABLE_END_MARKER_SIZE) - == PARTITIONTABLE_END_MARKER)) { - /* Looks like a start, sane length and end of a - * partition table, lets check csum etc. - */ - int ptable_ok = 0; - struct partitiontable_entry *max_addr = - (struct partitiontable_entry *) - ((unsigned long)ptable_head + sizeof(*ptable_head) + - ptable_head->size); - unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR; - unsigned char *p; - unsigned long csum = 0; - - ptable = (struct partitiontable_entry *) - ((unsigned long)ptable_head + sizeof(*ptable_head)); - - /* Lets be PARANOID, and check the checksum. */ - p = (unsigned char*) ptable; - - while (p <= (unsigned char*)max_addr) { - csum += *p++; - csum += *p++; - csum += *p++; - csum += *p++; - } - ptable_ok = (csum == ptable_head->checksum); - - /* Read the entries and use/show the info. */ - printk(KERN_INFO " Found a%s partition table at 0x%p-0x%p.\n", - (ptable_ok ? " valid" : "n invalid"), ptable_head, - max_addr); - - /* We have found a working bootblock. Now read the - * partition table. Scan the table. It ends when - * there is 0xffffffff, that is, empty flash. - */ - while (ptable_ok - && ptable->offset != 0xffffffff - && ptable < max_addr - && pidx < MAX_PARTITIONS) { - - axis_partitions[pidx].offset = offset + ptable->offset + (crisv32_nand_boot ? 16384 : 0); - axis_partitions[pidx].size = ptable->size; - - printk(pmsg, pidx, axis_partitions[pidx].offset, - axis_partitions[pidx].size); - pidx++; - ptable++; - } - use_default_ptable = !ptable_ok; - } - - if (romfs_in_flash) { - /* Add an overlapping device for the root partition (romfs). */ - - axis_partitions[pidx].name = "romfs"; - if (crisv32_nand_boot) { - char* data = kmalloc(1024, GFP_KERNEL); - int len; - int offset = crisv32_nand_cramfs_offset & ~(1024-1); - char* tmp; - - mymtd->read(mymtd, offset, 1024, &len, data); - tmp = &data[crisv32_nand_cramfs_offset % 512]; - axis_partitions[pidx].size = *(unsigned*)(tmp + 4); - axis_partitions[pidx].offset = crisv32_nand_cramfs_offset; - kfree(data); - } else { - axis_partitions[pidx].size = romfs_length; - axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR; - } - - axis_partitions[pidx].mask_flags |= MTD_WRITEABLE; - - printk(KERN_INFO - " Adding readonly flash partition for romfs image:\n"); - printk(pmsg, pidx, axis_partitions[pidx].offset, - axis_partitions[pidx].size); - pidx++; - } - - if (mymtd) { - if (use_default_ptable) { - printk(KERN_INFO " Using default partition table.\n"); - err = add_mtd_partitions(mymtd, axis_default_partitions, - NUM_DEFAULT_PARTITIONS); - } else { - err = add_mtd_partitions(mymtd, axis_partitions, pidx); - } - - if (err) { - panic("axisflashmap could not add MTD partitions!\n"); - } - } -/* CONFIG_EXTRAXFS_SIM */ -#endif - - if (!romfs_in_flash) { - /* Create an RAM device for the root partition (romfs). */ - -#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0) - /* No use trying to boot this kernel from RAM. Panic! */ - printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM " - "device due to kernel (mis)configuration!\n"); - panic("This kernel cannot boot from RAM!\n"); -#else - struct mtd_info *mtd_ram; - - mtd_ram = (struct mtd_info *)kmalloc(sizeof(struct mtd_info), - GFP_KERNEL); - if (!mtd_ram) { - panic("axisflashmap couldn't allocate memory for " - "mtd_info!\n"); - } - - printk(KERN_INFO " Adding RAM partition for romfs image:\n"); - printk(pmsg, pidx, romfs_start, romfs_length); - - err = mtdram_init_device(mtd_ram, (void*)romfs_start, - romfs_length, "romfs"); - if (err) { - panic("axisflashmap could not initialize MTD RAM " - "device!\n"); - } -#endif - } - - return err; -} - -/* This adds the above to the kernels init-call chain. */ -module_init(init_axis_flash); - -EXPORT_SYMBOL(axisflash_mtd); diff --git a/trunk/arch/cris/arch-v32/drivers/cryptocop.c b/trunk/arch/cris/arch-v32/drivers/cryptocop.c deleted file mode 100644 index ca72076c630a..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/cryptocop.c +++ /dev/null @@ -1,3522 +0,0 @@ -/* $Id: cryptocop.c,v 1.13 2005/04/21 17:27:55 henriken Exp $ - * - * Stream co-processor driver for the ETRAX FS - * - * Copyright (C) 2003-2005 Axis Communications AB - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - - - -#define DESCR_ALLOC_PAD (31) - -struct cryptocop_dma_desc { - char *free_buf; /* If non-null will be kfreed in free_cdesc() */ - dma_descr_data *dma_descr; - - unsigned char dma_descr_buf[sizeof(dma_descr_data) + DESCR_ALLOC_PAD]; - - unsigned int from_pool:1; /* If 1 'allocated' from the descriptor pool. */ - struct cryptocop_dma_desc *next; -}; - - -struct cryptocop_int_operation{ - void *alloc_ptr; - cryptocop_session_id sid; - - dma_descr_context ctx_out; - dma_descr_context ctx_in; - - /* DMA descriptors allocated by driver. */ - struct cryptocop_dma_desc *cdesc_out; - struct cryptocop_dma_desc *cdesc_in; - - /* Strcop config to use. */ - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; - - /* DMA descrs provided by consumer. */ - dma_descr_data *ddesc_out; - dma_descr_data *ddesc_in; -}; - - -struct cryptocop_tfrm_ctx { - cryptocop_tfrm_id tid; - unsigned int blocklength; - - unsigned int start_ix; - - struct cryptocop_tfrm_cfg *tcfg; - struct cryptocop_transform_ctx *tctx; - - unsigned char previous_src; - unsigned char current_src; - - /* Values to use in metadata out. */ - unsigned char hash_conf; - unsigned char hash_mode; - unsigned char ciph_conf; - unsigned char cbcmode; - unsigned char decrypt; - - unsigned int requires_padding:1; - unsigned int strict_block_length:1; - unsigned int active:1; - unsigned int done:1; - size_t consumed; - size_t produced; - - /* Pad (input) descriptors to put in the DMA out list when the transform - * output is put on the DMA in list. */ - struct cryptocop_dma_desc *pad_descs; - - struct cryptocop_tfrm_ctx *prev_src; - struct cryptocop_tfrm_ctx *curr_src; - - /* Mapping to HW. */ - unsigned char unit_no; -}; - - -struct cryptocop_private{ - cryptocop_session_id sid; - struct cryptocop_private *next; -}; - -/* Session list. */ - -struct cryptocop_transform_ctx{ - struct cryptocop_transform_init init; - unsigned char dec_key[CRYPTOCOP_MAX_KEY_LENGTH]; - unsigned int dec_key_set:1; - - struct cryptocop_transform_ctx *next; -}; - - -struct cryptocop_session{ - cryptocop_session_id sid; - - struct cryptocop_transform_ctx *tfrm_ctx; - - struct cryptocop_session *next; -}; - -/* Priority levels for jobs sent to the cryptocop. Checksum operations from - kernel have highest priority since TCPIP stack processing must not - be a bottleneck. */ -typedef enum { - cryptocop_prio_kernel_csum = 0, - cryptocop_prio_kernel = 1, - cryptocop_prio_user = 2, - cryptocop_prio_no_prios = 3 -} cryptocop_queue_priority; - -struct cryptocop_prio_queue{ - struct list_head jobs; - cryptocop_queue_priority prio; -}; - -struct cryptocop_prio_job{ - struct list_head node; - cryptocop_queue_priority prio; - - struct cryptocop_operation *oper; - struct cryptocop_int_operation *iop; -}; - -struct ioctl_job_cb_ctx { - unsigned int processed:1; -}; - - -static struct cryptocop_session *cryptocop_sessions = NULL; -spinlock_t cryptocop_sessions_lock; - -/* Next Session ID to assign. */ -static cryptocop_session_id next_sid = 1; - -/* Pad for checksum. */ -static const char csum_zero_pad[1] = {0x00}; - -/* Trash buffer for mem2mem operations. */ -#define MEM2MEM_DISCARD_BUF_LENGTH (512) -static unsigned char mem2mem_discard_buf[MEM2MEM_DISCARD_BUF_LENGTH]; - -/* Descriptor pool. */ -/* FIXME Tweak this value. */ -#define CRYPTOCOP_DESCRIPTOR_POOL_SIZE (100) -static struct cryptocop_dma_desc descr_pool[CRYPTOCOP_DESCRIPTOR_POOL_SIZE]; -static struct cryptocop_dma_desc *descr_pool_free_list; -static int descr_pool_no_free; -static spinlock_t descr_pool_lock; - -/* Lock to stop cryptocop to start processing of a new operation. The holder - of this lock MUST call cryptocop_start_job() after it is unlocked. */ -spinlock_t cryptocop_process_lock; - -static struct cryptocop_prio_queue cryptocop_job_queues[cryptocop_prio_no_prios]; -static spinlock_t cryptocop_job_queue_lock; -static struct cryptocop_prio_job *cryptocop_running_job = NULL; -static spinlock_t running_job_lock; - -/* The interrupt handler appends completed jobs to this list. The scehduled - * tasklet removes them upon sending the response to the crypto consumer. */ -static struct list_head cryptocop_completed_jobs; -static spinlock_t cryptocop_completed_jobs_lock; - -DECLARE_WAIT_QUEUE_HEAD(cryptocop_ioc_process_wq); - - -/** Local functions. **/ - -static int cryptocop_open(struct inode *, struct file *); - -static int cryptocop_release(struct inode *, struct file *); - -static int cryptocop_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg); - -static void cryptocop_start_job(void); - -static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation); -static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation); - -static int cryptocop_job_queue_init(void); -static void cryptocop_job_queue_close(void); - -static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length); - -static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length); - -static int transform_ok(struct cryptocop_transform_init *tinit); - -static struct cryptocop_session *get_session(cryptocop_session_id sid); - -static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid); - -static void delete_internal_operation(struct cryptocop_int_operation *iop); - -static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength); - -static int init_stream_coprocessor(void); - -static void __exit exit_stream_coprocessor(void); - -/*#define LDEBUG*/ -#ifdef LDEBUG -#define DEBUG(s) s -#define DEBUG_API(s) s -static void print_cryptocop_operation(struct cryptocop_operation *cop); -static void print_dma_descriptors(struct cryptocop_int_operation *iop); -static void print_strcop_crypto_op(struct strcop_crypto_op *cop); -static void print_lock_status(void); -static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op); -#define assert(s) do{if (!(s)) panic(#s);} while(0); -#else -#define DEBUG(s) -#define DEBUG_API(s) -#define assert(s) -#endif - - -/* Transform constants. */ -#define DES_BLOCK_LENGTH (8) -#define AES_BLOCK_LENGTH (16) -#define MD5_BLOCK_LENGTH (64) -#define SHA1_BLOCK_LENGTH (64) -#define CSUM_BLOCK_LENGTH (2) -#define MD5_STATE_LENGTH (16) -#define SHA1_STATE_LENGTH (20) - -/* The device number. */ -#define CRYPTOCOP_MAJOR (254) -#define CRYPTOCOP_MINOR (0) - - - -struct file_operations cryptocop_fops = { - owner: THIS_MODULE, - open: cryptocop_open, - release: cryptocop_release, - ioctl: cryptocop_ioctl -}; - - -static void free_cdesc(struct cryptocop_dma_desc *cdesc) -{ - DEBUG(printk("free_cdesc: cdesc 0x%p, from_pool=%d\n", cdesc, cdesc->from_pool)); - if (cdesc->free_buf) kfree(cdesc->free_buf); - - if (cdesc->from_pool) { - unsigned long int flags; - spin_lock_irqsave(&descr_pool_lock, flags); - cdesc->next = descr_pool_free_list; - descr_pool_free_list = cdesc; - ++descr_pool_no_free; - spin_unlock_irqrestore(&descr_pool_lock, flags); - } else { - kfree(cdesc); - } -} - - -static struct cryptocop_dma_desc *alloc_cdesc(int alloc_flag) -{ - int use_pool = (alloc_flag & GFP_ATOMIC) ? 1 : 0; - struct cryptocop_dma_desc *cdesc; - - if (use_pool) { - unsigned long int flags; - spin_lock_irqsave(&descr_pool_lock, flags); - if (!descr_pool_free_list) { - spin_unlock_irqrestore(&descr_pool_lock, flags); - DEBUG_API(printk("alloc_cdesc: pool is empty\n")); - return NULL; - } - cdesc = descr_pool_free_list; - descr_pool_free_list = descr_pool_free_list->next; - --descr_pool_no_free; - spin_unlock_irqrestore(&descr_pool_lock, flags); - cdesc->from_pool = 1; - } else { - cdesc = kmalloc(sizeof(struct cryptocop_dma_desc), alloc_flag); - if (!cdesc) { - DEBUG_API(printk("alloc_cdesc: kmalloc\n")); - return NULL; - } - cdesc->from_pool = 0; - } - cdesc->dma_descr = (dma_descr_data*)(((unsigned long int)cdesc + offsetof(struct cryptocop_dma_desc, dma_descr_buf) + DESCR_ALLOC_PAD) & ~0x0000001F); - - cdesc->next = NULL; - - cdesc->free_buf = NULL; - cdesc->dma_descr->out_eop = 0; - cdesc->dma_descr->in_eop = 0; - cdesc->dma_descr->intr = 0; - cdesc->dma_descr->eol = 0; - cdesc->dma_descr->wait = 0; - cdesc->dma_descr->buf = NULL; - cdesc->dma_descr->after = NULL; - - DEBUG_API(printk("alloc_cdesc: return 0x%p, cdesc->dma_descr=0x%p, from_pool=%d\n", cdesc, cdesc->dma_descr, cdesc->from_pool)); - return cdesc; -} - - -static void setup_descr_chain(struct cryptocop_dma_desc *cd) -{ - DEBUG(printk("setup_descr_chain: entering\n")); - while (cd) { - if (cd->next) { - cd->dma_descr->next = (dma_descr_data*)virt_to_phys(cd->next->dma_descr); - } else { - cd->dma_descr->next = NULL; - } - cd = cd->next; - } - DEBUG(printk("setup_descr_chain: exit\n")); -} - - -/* Create a pad descriptor for the transform. - * Return -1 for error, 0 if pad created. */ -static int create_pad_descriptor(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **pad_desc, int alloc_flag) -{ - struct cryptocop_dma_desc *cdesc = NULL; - int error = 0; - struct strcop_meta_out mo = { - .ciphsel = src_none, - .hashsel = src_none, - .csumsel = src_none - }; - char *pad; - size_t plen; - - DEBUG(printk("create_pad_descriptor: start.\n")); - /* Setup pad descriptor. */ - - DEBUG(printk("create_pad_descriptor: setting up padding.\n")); - cdesc = alloc_cdesc(alloc_flag); - if (!cdesc){ - DEBUG_API(printk("create_pad_descriptor: alloc pad desc\n")); - goto error_cleanup; - } - switch (tc->unit_no) { - case src_md5: - error = create_md5_pad(alloc_flag, tc->consumed, &pad, &plen); - if (error){ - DEBUG_API(printk("create_pad_descriptor: create_md5_pad_failed\n")); - goto error_cleanup; - } - cdesc->free_buf = pad; - mo.hashsel = src_dma; - mo.hashconf = tc->hash_conf; - mo.hashmode = tc->hash_mode; - break; - case src_sha1: - error = create_sha1_pad(alloc_flag, tc->consumed, &pad, &plen); - if (error){ - DEBUG_API(printk("create_pad_descriptor: create_sha1_pad_failed\n")); - goto error_cleanup; - } - cdesc->free_buf = pad; - mo.hashsel = src_dma; - mo.hashconf = tc->hash_conf; - mo.hashmode = tc->hash_mode; - break; - case src_csum: - if (tc->consumed % tc->blocklength){ - pad = (char*)csum_zero_pad; - plen = 1; - } else { - pad = (char*)cdesc; /* Use any pointer. */ - plen = 0; - } - mo.csumsel = src_dma; - break; - } - cdesc->dma_descr->wait = 1; - cdesc->dma_descr->out_eop = 1; /* Since this is a pad output is pushed. EOP is ok here since the padded unit is the only one active. */ - cdesc->dma_descr->buf = (char*)virt_to_phys((char*)pad); - cdesc->dma_descr->after = cdesc->dma_descr->buf + plen; - - cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo); - *pad_desc = cdesc; - - return 0; - - error_cleanup: - if (cdesc) free_cdesc(cdesc); - return -1; -} - - -static int setup_key_dl_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **kd, int alloc_flag) -{ - struct cryptocop_dma_desc *key_desc = alloc_cdesc(alloc_flag); - struct strcop_meta_out mo = {0}; - - DEBUG(printk("setup_key_dl_desc\n")); - - if (!key_desc) { - DEBUG_API(printk("setup_key_dl_desc: failed descriptor allocation.\n")); - return -ENOMEM; - } - - /* Download key. */ - if ((tc->tctx->init.alg == cryptocop_alg_aes) && (tc->tcfg->flags & CRYPTOCOP_DECRYPT)) { - /* Precook the AES decrypt key. */ - if (!tc->tctx->dec_key_set){ - get_aes_decrypt_key(tc->tctx->dec_key, tc->tctx->init.key, tc->tctx->init.keylen); - tc->tctx->dec_key_set = 1; - } - key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->dec_key); - key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8; - } else { - key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->init.key); - key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8; - } - /* Setup metadata. */ - mo.dlkey = 1; - switch (tc->tctx->init.keylen) { - case 64: - mo.decrypt = 0; - mo.hashmode = 0; - break; - case 128: - mo.decrypt = 0; - mo.hashmode = 1; - break; - case 192: - mo.decrypt = 1; - mo.hashmode = 0; - break; - case 256: - mo.decrypt = 1; - mo.hashmode = 1; - break; - default: - break; - } - mo.ciphsel = mo.hashsel = mo.csumsel = src_none; - key_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo); - - key_desc->dma_descr->out_eop = 1; - key_desc->dma_descr->wait = 1; - key_desc->dma_descr->intr = 0; - - *kd = key_desc; - return 0; -} - -static int setup_cipher_iv_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag) -{ - struct cryptocop_dma_desc *iv_desc = alloc_cdesc(alloc_flag); - struct strcop_meta_out mo = {0}; - - DEBUG(printk("setup_cipher_iv_desc\n")); - - if (!iv_desc) { - DEBUG_API(printk("setup_cipher_iv_desc: failed CBC IV descriptor allocation.\n")); - return -ENOMEM; - } - /* Download IV. */ - iv_desc->dma_descr->buf = (char*)virt_to_phys(tc->tcfg->iv); - iv_desc->dma_descr->after = iv_desc->dma_descr->buf + tc->blocklength; - - /* Setup metadata. */ - mo.hashsel = mo.csumsel = src_none; - mo.ciphsel = src_dma; - mo.ciphconf = tc->ciph_conf; - mo.cbcmode = tc->cbcmode; - - iv_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo); - - iv_desc->dma_descr->out_eop = 0; - iv_desc->dma_descr->wait = 1; - iv_desc->dma_descr->intr = 0; - - *id = iv_desc; - return 0; -} - -/* Map the ouput length of the transform to operation output starting on the inject index. */ -static int create_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag) -{ - int err = 0; - struct cryptocop_dma_desc head = {0}; - struct cryptocop_dma_desc *outdesc = &head; - size_t iov_offset = 0; - size_t out_ix = 0; - int outiov_ix = 0; - struct strcop_meta_in mi = {0}; - - size_t out_length = tc->produced; - int rem_length; - int dlength; - - assert(out_length != 0); - if (((tc->produced + tc->tcfg->inject_ix) > operation->tfrm_op.outlen) || (tc->produced && (operation->tfrm_op.outlen == 0))) { - DEBUG_API(printk("create_input_descriptors: operation outdata too small\n")); - return -EINVAL; - } - /* Traverse the out iovec until the result inject index is reached. */ - while ((outiov_ix < operation->tfrm_op.outcount) && ((out_ix + operation->tfrm_op.outdata[outiov_ix].iov_len) <= tc->tcfg->inject_ix)){ - out_ix += operation->tfrm_op.outdata[outiov_ix].iov_len; - outiov_ix++; - } - if (outiov_ix >= operation->tfrm_op.outcount){ - DEBUG_API(printk("create_input_descriptors: operation outdata too small\n")); - return -EINVAL; - } - iov_offset = tc->tcfg->inject_ix - out_ix; - mi.dmasel = tc->unit_no; - - /* Setup the output descriptors. */ - while ((out_length > 0) && (outiov_ix < operation->tfrm_op.outcount)) { - outdesc->next = alloc_cdesc(alloc_flag); - if (!outdesc->next) { - DEBUG_API(printk("create_input_descriptors: alloc_cdesc\n")); - err = -ENOMEM; - goto error_cleanup; - } - outdesc = outdesc->next; - rem_length = operation->tfrm_op.outdata[outiov_ix].iov_len - iov_offset; - dlength = (out_length < rem_length) ? out_length : rem_length; - - DEBUG(printk("create_input_descriptors:\n" - "outiov_ix=%d, rem_length=%d, dlength=%d\n" - "iov_offset=%d, outdata[outiov_ix].iov_len=%d\n" - "outcount=%d, outiov_ix=%d\n", - outiov_ix, rem_length, dlength, iov_offset, operation->tfrm_op.outdata[outiov_ix].iov_len, operation->tfrm_op.outcount, outiov_ix)); - - outdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.outdata[outiov_ix].iov_base + iov_offset); - outdesc->dma_descr->after = outdesc->dma_descr->buf + dlength; - outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); - - out_length -= dlength; - iov_offset += dlength; - if (iov_offset >= operation->tfrm_op.outdata[outiov_ix].iov_len) { - iov_offset = 0; - ++outiov_ix; - } - } - if (out_length > 0){ - DEBUG_API(printk("create_input_descriptors: not enough room for output, %d remained\n", out_length)); - err = -EINVAL; - goto error_cleanup; - } - /* Set sync in last descriptor. */ - mi.sync = 1; - outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); - - *id = head.next; - return 0; - - error_cleanup: - while (head.next) { - outdesc = head.next->next; - free_cdesc(head.next); - head.next = outdesc; - } - return err; -} - - -static int create_output_descriptors(struct cryptocop_operation *operation, int *iniov_ix, int *iniov_offset, size_t desc_len, struct cryptocop_dma_desc **current_out_cdesc, struct strcop_meta_out *meta_out, int alloc_flag) -{ - while (desc_len != 0) { - struct cryptocop_dma_desc *cdesc; - int rem_length = operation->tfrm_op.indata[*iniov_ix].iov_len - *iniov_offset; - int dlength = (desc_len < rem_length) ? desc_len : rem_length; - - cdesc = alloc_cdesc(alloc_flag); - if (!cdesc) { - DEBUG_API(printk("create_output_descriptors: alloc_cdesc\n")); - return -ENOMEM; - } - (*current_out_cdesc)->next = cdesc; - (*current_out_cdesc) = cdesc; - - cdesc->free_buf = NULL; - - cdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.indata[*iniov_ix].iov_base + *iniov_offset); - cdesc->dma_descr->after = cdesc->dma_descr->buf + dlength; - - desc_len -= dlength; - *iniov_offset += dlength; - assert(desc_len >= 0); - if (*iniov_offset >= operation->tfrm_op.indata[*iniov_ix].iov_len) { - *iniov_offset = 0; - ++(*iniov_ix); - if (*iniov_ix > operation->tfrm_op.incount) { - DEBUG_API(printk("create_output_descriptors: not enough indata in operation.")); - return -EINVAL; - } - } - cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, (*meta_out)); - } /* while (desc_len != 0) */ - /* Last DMA descriptor gets a 'wait' bit to signal expected change in metadata. */ - (*current_out_cdesc)->dma_descr->wait = 1; /* This will set extraneous WAIT in some situations, e.g. when padding hashes and checksums. */ - - return 0; -} - - -static int append_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_dma_desc **current_in_cdesc, struct cryptocop_dma_desc **current_out_cdesc, struct cryptocop_tfrm_ctx *tc, int alloc_flag) -{ - DEBUG(printk("append_input_descriptors, tc=0x%p, unit_no=%d\n", tc, tc->unit_no)); - if (tc->tcfg) { - int failed = 0; - struct cryptocop_dma_desc *idescs = NULL; - DEBUG(printk("append_input_descriptors: pushing output, consumed %d produced %d bytes.\n", tc->consumed, tc->produced)); - if (tc->pad_descs) { - DEBUG(printk("append_input_descriptors: append pad descriptors to DMA out list.\n")); - while (tc->pad_descs) { - DEBUG(printk("append descriptor 0x%p\n", tc->pad_descs)); - (*current_out_cdesc)->next = tc->pad_descs; - tc->pad_descs = tc->pad_descs->next; - (*current_out_cdesc) = (*current_out_cdesc)->next; - } - } - - /* Setup and append output descriptors to DMA in list. */ - if (tc->unit_no == src_dma){ - /* mem2mem. Setup DMA in descriptors to discard all input prior to the requested mem2mem data. */ - struct strcop_meta_in mi = {.sync = 0, .dmasel = src_dma}; - unsigned int start_ix = tc->start_ix; - while (start_ix){ - unsigned int desclen = start_ix < MEM2MEM_DISCARD_BUF_LENGTH ? start_ix : MEM2MEM_DISCARD_BUF_LENGTH; - (*current_in_cdesc)->next = alloc_cdesc(alloc_flag); - if (!(*current_in_cdesc)->next){ - DEBUG_API(printk("append_input_descriptors: alloc_cdesc mem2mem discard failed\n")); - return -ENOMEM; - } - (*current_in_cdesc) = (*current_in_cdesc)->next; - (*current_in_cdesc)->dma_descr->buf = (char*)virt_to_phys(mem2mem_discard_buf); - (*current_in_cdesc)->dma_descr->after = (*current_in_cdesc)->dma_descr->buf + desclen; - (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); - start_ix -= desclen; - } - mi.sync = 1; - (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); - } - - failed = create_input_descriptors(operation, tc, &idescs, alloc_flag); - if (failed){ - DEBUG_API(printk("append_input_descriptors: output descriptor setup failed\n")); - return failed; - } - DEBUG(printk("append_input_descriptors: append output descriptors to DMA in list.\n")); - while (idescs) { - DEBUG(printk("append descriptor 0x%p\n", idescs)); - (*current_in_cdesc)->next = idescs; - idescs = idescs->next; - (*current_in_cdesc) = (*current_in_cdesc)->next; - } - } - return 0; -} - - - -static int cryptocop_setup_dma_list(struct cryptocop_operation *operation, struct cryptocop_int_operation **int_op, int alloc_flag) -{ - struct cryptocop_session *sess; - struct cryptocop_transform_ctx *tctx; - - struct cryptocop_tfrm_ctx digest_ctx = { - .previous_src = src_none, - .current_src = src_none, - .start_ix = 0, - .requires_padding = 1, - .strict_block_length = 0, - .hash_conf = 0, - .hash_mode = 0, - .ciph_conf = 0, - .cbcmode = 0, - .decrypt = 0, - .consumed = 0, - .produced = 0, - .pad_descs = NULL, - .active = 0, - .done = 0, - .prev_src = NULL, - .curr_src = NULL, - .tcfg = NULL}; - struct cryptocop_tfrm_ctx cipher_ctx = { - .previous_src = src_none, - .current_src = src_none, - .start_ix = 0, - .requires_padding = 0, - .strict_block_length = 1, - .hash_conf = 0, - .hash_mode = 0, - .ciph_conf = 0, - .cbcmode = 0, - .decrypt = 0, - .consumed = 0, - .produced = 0, - .pad_descs = NULL, - .active = 0, - .done = 0, - .prev_src = NULL, - .curr_src = NULL, - .tcfg = NULL}; - struct cryptocop_tfrm_ctx csum_ctx = { - .previous_src = src_none, - .current_src = src_none, - .start_ix = 0, - .blocklength = 2, - .requires_padding = 1, - .strict_block_length = 0, - .hash_conf = 0, - .hash_mode = 0, - .ciph_conf = 0, - .cbcmode = 0, - .decrypt = 0, - .consumed = 0, - .produced = 0, - .pad_descs = NULL, - .active = 0, - .done = 0, - .tcfg = NULL, - .prev_src = NULL, - .curr_src = NULL, - .unit_no = src_csum}; - struct cryptocop_tfrm_cfg *tcfg = operation->tfrm_op.tfrm_cfg; - - unsigned int indata_ix = 0; - - /* iovec accounting. */ - int iniov_ix = 0; - int iniov_offset = 0; - - /* Operation descriptor cfg traversal pointer. */ - struct cryptocop_desc *odsc; - - int failed = 0; - /* List heads for allocated descriptors. */ - struct cryptocop_dma_desc out_cdesc_head = {0}; - struct cryptocop_dma_desc in_cdesc_head = {0}; - - struct cryptocop_dma_desc *current_out_cdesc = &out_cdesc_head; - struct cryptocop_dma_desc *current_in_cdesc = &in_cdesc_head; - - struct cryptocop_tfrm_ctx *output_tc = NULL; - void *iop_alloc_ptr; - - assert(operation != NULL); - assert(int_op != NULL); - - DEBUG(printk("cryptocop_setup_dma_list: start\n")); - DEBUG(print_cryptocop_operation(operation)); - - sess = get_session(operation->sid); - if (!sess) { - DEBUG_API(printk("cryptocop_setup_dma_list: no session found for operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag); - if (!iop_alloc_ptr) { - DEBUG_API(printk("cryptocop_setup_dma_list: kmalloc cryptocop_int_operation\n")); - failed = -ENOMEM; - goto error_cleanup; - } - (*int_op) = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out)); - DEBUG(memset((*int_op), 0xff, sizeof(struct cryptocop_int_operation))); - (*int_op)->alloc_ptr = iop_alloc_ptr; - DEBUG(printk("cryptocop_setup_dma_list: *int_op=0x%p, alloc_ptr=0x%p\n", *int_op, (*int_op)->alloc_ptr)); - - (*int_op)->sid = operation->sid; - (*int_op)->cdesc_out = NULL; - (*int_op)->cdesc_in = NULL; - (*int_op)->tdes_mode = cryptocop_3des_ede; - (*int_op)->csum_mode = cryptocop_csum_le; - (*int_op)->ddesc_out = NULL; - (*int_op)->ddesc_in = NULL; - - /* Scan operation->tfrm_op.tfrm_cfg for bad configuration and set up the local contexts. */ - if (!tcfg) { - DEBUG_API(printk("cryptocop_setup_dma_list: no configured transforms in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - while (tcfg) { - tctx = get_transform_ctx(sess, tcfg->tid); - if (!tctx) { - DEBUG_API(printk("cryptocop_setup_dma_list: no transform id %d in session.\n", tcfg->tid)); - failed = -EINVAL; - goto error_cleanup; - } - if (tcfg->inject_ix > operation->tfrm_op.outlen){ - DEBUG_API(printk("cryptocop_setup_dma_list: transform id %d inject_ix (%d) > operation->tfrm_op.outlen(%d)", tcfg->tid, tcfg->inject_ix, operation->tfrm_op.outlen)); - failed = -EINVAL; - goto error_cleanup; - } - switch (tctx->init.alg){ - case cryptocop_alg_mem2mem: - if (cipher_ctx.tcfg != NULL){ - DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - /* mem2mem is handled as a NULL cipher. */ - cipher_ctx.cbcmode = 0; - cipher_ctx.decrypt = 0; - cipher_ctx.blocklength = 1; - cipher_ctx.ciph_conf = 0; - cipher_ctx.unit_no = src_dma; - cipher_ctx.tcfg = tcfg; - cipher_ctx.tctx = tctx; - break; - case cryptocop_alg_des: - case cryptocop_alg_3des: - case cryptocop_alg_aes: - /* cipher */ - if (cipher_ctx.tcfg != NULL){ - DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - cipher_ctx.tcfg = tcfg; - cipher_ctx.tctx = tctx; - if (cipher_ctx.tcfg->flags & CRYPTOCOP_DECRYPT){ - cipher_ctx.decrypt = 1; - } - switch (tctx->init.cipher_mode) { - case cryptocop_cipher_mode_ecb: - cipher_ctx.cbcmode = 0; - break; - case cryptocop_cipher_mode_cbc: - cipher_ctx.cbcmode = 1; - break; - default: - DEBUG_API(printk("cryptocop_setup_dma_list: cipher_ctx, bad cipher mode==%d\n", tctx->init.cipher_mode)); - failed = -EINVAL; - goto error_cleanup; - } - DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx, set CBC mode==%d\n", cipher_ctx.cbcmode)); - switch (tctx->init.alg){ - case cryptocop_alg_des: - cipher_ctx.ciph_conf = 0; - cipher_ctx.unit_no = src_des; - cipher_ctx.blocklength = DES_BLOCK_LENGTH; - break; - case cryptocop_alg_3des: - cipher_ctx.ciph_conf = 1; - cipher_ctx.unit_no = src_des; - cipher_ctx.blocklength = DES_BLOCK_LENGTH; - break; - case cryptocop_alg_aes: - cipher_ctx.ciph_conf = 2; - cipher_ctx.unit_no = src_aes; - cipher_ctx.blocklength = AES_BLOCK_LENGTH; - break; - default: - panic("cryptocop_setup_dma_list: impossible algorithm %d\n", tctx->init.alg); - } - (*int_op)->tdes_mode = tctx->init.tdes_mode; - break; - case cryptocop_alg_md5: - case cryptocop_alg_sha1: - /* digest */ - if (digest_ctx.tcfg != NULL){ - DEBUG_API(printk("cryptocop_setup_dma_list: multiple digests in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - digest_ctx.tcfg = tcfg; - digest_ctx.tctx = tctx; - digest_ctx.hash_mode = 0; /* Don't use explicit IV in this API. */ - switch (tctx->init.alg){ - case cryptocop_alg_md5: - digest_ctx.blocklength = MD5_BLOCK_LENGTH; - digest_ctx.unit_no = src_md5; - digest_ctx.hash_conf = 1; /* 1 => MD-5 */ - break; - case cryptocop_alg_sha1: - digest_ctx.blocklength = SHA1_BLOCK_LENGTH; - digest_ctx.unit_no = src_sha1; - digest_ctx.hash_conf = 0; /* 0 => SHA-1 */ - break; - default: - panic("cryptocop_setup_dma_list: impossible digest algorithm\n"); - } - break; - case cryptocop_alg_csum: - /* digest */ - if (csum_ctx.tcfg != NULL){ - DEBUG_API(printk("cryptocop_setup_dma_list: multiple checksums in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - (*int_op)->csum_mode = tctx->init.csum_mode; - csum_ctx.tcfg = tcfg; - csum_ctx.tctx = tctx; - break; - default: - /* no algorithm. */ - DEBUG_API(printk("cryptocop_setup_dma_list: invalid algorithm %d specified in tfrm %d.\n", tctx->init.alg, tcfg->tid)); - failed = -EINVAL; - goto error_cleanup; - } - tcfg = tcfg->next; - } - /* Download key if a cipher is used. */ - if (cipher_ctx.tcfg && (cipher_ctx.tctx->init.alg != cryptocop_alg_mem2mem)){ - struct cryptocop_dma_desc *key_desc = NULL; - - failed = setup_key_dl_desc(&cipher_ctx, &key_desc, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: setup key dl\n")); - goto error_cleanup; - } - current_out_cdesc->next = key_desc; - current_out_cdesc = key_desc; - indata_ix += (unsigned int)(key_desc->dma_descr->after - key_desc->dma_descr->buf); - - /* Download explicit IV if a cipher is used and CBC mode and explicit IV selected. */ - if ((cipher_ctx.tctx->init.cipher_mode == cryptocop_cipher_mode_cbc) && (cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV)) { - struct cryptocop_dma_desc *iv_desc = NULL; - - DEBUG(printk("cryptocop_setup_dma_list: setup cipher CBC IV descriptor.\n")); - - failed = setup_cipher_iv_desc(&cipher_ctx, &iv_desc, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: CBC IV descriptor.\n")); - goto error_cleanup; - } - current_out_cdesc->next = iv_desc; - current_out_cdesc = iv_desc; - indata_ix += (unsigned int)(iv_desc->dma_descr->after - iv_desc->dma_descr->buf); - } - } - - /* Process descriptors. */ - odsc = operation->tfrm_op.desc; - while (odsc) { - struct cryptocop_desc_cfg *dcfg = odsc->cfg; - struct strcop_meta_out meta_out = {0}; - size_t desc_len = odsc->length; - int active_count, eop_needed_count; - - output_tc = NULL; - - DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor\n")); - - while (dcfg) { - struct cryptocop_tfrm_ctx *tc = NULL; - - DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor configuration.\n")); - /* Get the local context for the transform and mark it as the output unit if it produces output. */ - if (digest_ctx.tcfg && (digest_ctx.tcfg->tid == dcfg->tid)){ - tc = &digest_ctx; - } else if (cipher_ctx.tcfg && (cipher_ctx.tcfg->tid == dcfg->tid)){ - tc = &cipher_ctx; - } else if (csum_ctx.tcfg && (csum_ctx.tcfg->tid == dcfg->tid)){ - tc = &csum_ctx; - } - if (!tc) { - DEBUG_API(printk("cryptocop_setup_dma_list: invalid transform %d specified in descriptor.\n", dcfg->tid)); - failed = -EINVAL; - goto error_cleanup; - } - if (tc->done) { - DEBUG_API(printk("cryptocop_setup_dma_list: completed transform %d reused.\n", dcfg->tid)); - failed = -EINVAL; - goto error_cleanup; - } - if (!tc->active) { - tc->start_ix = indata_ix; - tc->active = 1; - } - - tc->previous_src = tc->current_src; - tc->prev_src = tc->curr_src; - /* Map source unit id to DMA source config. */ - switch (dcfg->src){ - case cryptocop_source_dma: - tc->current_src = src_dma; - break; - case cryptocop_source_des: - tc->current_src = src_des; - break; - case cryptocop_source_3des: - tc->current_src = src_des; - break; - case cryptocop_source_aes: - tc->current_src = src_aes; - break; - case cryptocop_source_md5: - case cryptocop_source_sha1: - case cryptocop_source_csum: - case cryptocop_source_none: - default: - /* We do not allow using accumulating style units (SHA-1, MD5, checksum) as sources to other units. - */ - DEBUG_API(printk("cryptocop_setup_dma_list: bad unit source configured %d.\n", dcfg->src)); - failed = -EINVAL; - goto error_cleanup; - } - if (tc->current_src != src_dma) { - /* Find the unit we are sourcing from. */ - if (digest_ctx.unit_no == tc->current_src){ - tc->curr_src = &digest_ctx; - } else if (cipher_ctx.unit_no == tc->current_src){ - tc->curr_src = &cipher_ctx; - } else if (csum_ctx.unit_no == tc->current_src){ - tc->curr_src = &csum_ctx; - } - if ((tc->curr_src == tc) && (tc->unit_no != src_dma)){ - DEBUG_API(printk("cryptocop_setup_dma_list: unit %d configured to source from itself.\n", tc->unit_no)); - failed = -EINVAL; - goto error_cleanup; - } - } else { - tc->curr_src = NULL; - } - - /* Detect source switch. */ - DEBUG(printk("cryptocop_setup_dma_list: tc->active=%d tc->unit_no=%d tc->current_src=%d tc->previous_src=%d, tc->curr_src=0x%p, tc->prev_srv=0x%p\n", tc->active, tc->unit_no, tc->current_src, tc->previous_src, tc->curr_src, tc->prev_src)); - if (tc->active && (tc->current_src != tc->previous_src)) { - /* Only allow source switch when both the old source unit and the new one have - * no pending data to process (i.e. the consumed length must be a multiple of the - * transform blocklength). */ - /* Note: if the src == NULL we are actually sourcing from DMA out. */ - if (((tc->prev_src != NULL) && (tc->prev_src->consumed % tc->prev_src->blocklength)) || - ((tc->curr_src != NULL) && (tc->curr_src->consumed % tc->curr_src->blocklength))) - { - DEBUG_API(printk("cryptocop_setup_dma_list: can only disconnect from or connect to a unit on a multiple of the blocklength, old: cons=%d, prod=%d, block=%d, new: cons=%d prod=%d, block=%d.\n", tc->prev_src ? tc->prev_src->consumed : INT_MIN, tc->prev_src ? tc->prev_src->produced : INT_MIN, tc->prev_src ? tc->prev_src->blocklength : INT_MIN, tc->curr_src ? tc->curr_src->consumed : INT_MIN, tc->curr_src ? tc->curr_src->produced : INT_MIN, tc->curr_src ? tc->curr_src->blocklength : INT_MIN)); - failed = -EINVAL; - goto error_cleanup; - } - } - /* Detect unit deactivation. */ - if (dcfg->last) { - /* Length check of this is handled below. */ - tc->done = 1; - } - dcfg = dcfg->next; - } /* while (dcfg) */ - DEBUG(printk("cryptocop_setup_dma_list: parsing operation descriptor configuration complete.\n")); - - if (cipher_ctx.active && (cipher_ctx.curr_src != NULL) && !cipher_ctx.curr_src->active){ - DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", cipher_ctx.curr_src->unit_no)); - failed = -EINVAL; - goto error_cleanup; - } - if (digest_ctx.active && (digest_ctx.curr_src != NULL) && !digest_ctx.curr_src->active){ - DEBUG_API(printk("cryptocop_setup_dma_list: digest source from inactive unit %d\n", digest_ctx.curr_src->unit_no)); - failed = -EINVAL; - goto error_cleanup; - } - if (csum_ctx.active && (csum_ctx.curr_src != NULL) && !csum_ctx.curr_src->active){ - DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", csum_ctx.curr_src->unit_no)); - failed = -EINVAL; - goto error_cleanup; - } - - /* Update consumed and produced lengths. - - The consumed length accounting here is actually cheating. If a unit source from DMA (or any - other unit that process data in blocks of one octet) it is correct, but if it source from a - block processing unit, i.e. a cipher, it will be temporarily incorrect at some times. However - since it is only allowed--by the HW--to change source to or from a block processing unit at times where that - unit has processed an exact multiple of its block length the end result will be correct. - Beware that if the source change restriction change this code will need to be (much) reworked. - */ - DEBUG(printk("cryptocop_setup_dma_list: desc->length=%d, desc_len=%d.\n", odsc->length, desc_len)); - - if (csum_ctx.active) { - csum_ctx.consumed += desc_len; - if (csum_ctx.done) { - csum_ctx.produced = 2; - } - DEBUG(printk("cryptocop_setup_dma_list: csum_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", csum_ctx.consumed, csum_ctx.produced, csum_ctx.blocklength)); - } - if (digest_ctx.active) { - digest_ctx.consumed += desc_len; - if (digest_ctx.done) { - if (digest_ctx.unit_no == src_md5) { - digest_ctx.produced = MD5_STATE_LENGTH; - } else { - digest_ctx.produced = SHA1_STATE_LENGTH; - } - } - DEBUG(printk("cryptocop_setup_dma_list: digest_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", digest_ctx.consumed, digest_ctx.produced, digest_ctx.blocklength)); - } - if (cipher_ctx.active) { - /* Ciphers are allowed only to source from DMA out. That is filtered above. */ - assert(cipher_ctx.current_src == src_dma); - cipher_ctx.consumed += desc_len; - cipher_ctx.produced = cipher_ctx.blocklength * (cipher_ctx.consumed / cipher_ctx.blocklength); - if (cipher_ctx.cbcmode && !(cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV) && cipher_ctx.produced){ - cipher_ctx.produced -= cipher_ctx.blocklength; /* Compensate for CBC iv. */ - } - DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", cipher_ctx.consumed, cipher_ctx.produced, cipher_ctx.blocklength)); - } - - /* Setup the DMA out descriptors. */ - /* Configure the metadata. */ - active_count = 0; - eop_needed_count = 0; - if (cipher_ctx.active) { - ++active_count; - if (cipher_ctx.unit_no == src_dma){ - /* mem2mem */ - meta_out.ciphsel = src_none; - } else { - meta_out.ciphsel = cipher_ctx.current_src; - } - meta_out.ciphconf = cipher_ctx.ciph_conf; - meta_out.cbcmode = cipher_ctx.cbcmode; - meta_out.decrypt = cipher_ctx.decrypt; - DEBUG(printk("set ciphsel=%d ciphconf=%d cbcmode=%d decrypt=%d\n", meta_out.ciphsel, meta_out.ciphconf, meta_out.cbcmode, meta_out.decrypt)); - if (cipher_ctx.done) ++eop_needed_count; - } else { - meta_out.ciphsel = src_none; - } - - if (digest_ctx.active) { - ++active_count; - meta_out.hashsel = digest_ctx.current_src; - meta_out.hashconf = digest_ctx.hash_conf; - meta_out.hashmode = 0; /* Explicit mode is not used here. */ - DEBUG(printk("set hashsel=%d hashconf=%d hashmode=%d\n", meta_out.hashsel, meta_out.hashconf, meta_out.hashmode)); - if (digest_ctx.done) { - assert(digest_ctx.pad_descs == NULL); - failed = create_pad_descriptor(&digest_ctx, &digest_ctx.pad_descs, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: failed digest pad creation.\n")); - goto error_cleanup; - } - } - } else { - meta_out.hashsel = src_none; - } - - if (csum_ctx.active) { - ++active_count; - meta_out.csumsel = csum_ctx.current_src; - if (csum_ctx.done) { - assert(csum_ctx.pad_descs == NULL); - failed = create_pad_descriptor(&csum_ctx, &csum_ctx.pad_descs, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: failed csum pad creation.\n")); - goto error_cleanup; - } - } - } else { - meta_out.csumsel = src_none; - } - DEBUG(printk("cryptocop_setup_dma_list: %d eop needed, %d active units\n", eop_needed_count, active_count)); - /* Setup DMA out descriptors for the indata. */ - failed = create_output_descriptors(operation, &iniov_ix, &iniov_offset, desc_len, ¤t_out_cdesc, &meta_out, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: create_output_descriptors %d\n", failed)); - goto error_cleanup; - } - /* Setup out EOP. If there are active units that are not done here they cannot get an EOP - * so we ust setup a zero length descriptor to DMA to signal EOP only to done units. - * If there is a pad descriptor EOP for the padded unit will be EOPed by it. - */ - assert(active_count >= eop_needed_count); - assert((eop_needed_count == 0) || (eop_needed_count == 1)); - if (eop_needed_count) { - /* This means that the bulk operation (cipeher/m2m) is terminated. */ - if (active_count > 1) { - /* Use zero length EOP descriptor. */ - struct cryptocop_dma_desc *ed = alloc_cdesc(alloc_flag); - struct strcop_meta_out ed_mo = {0}; - if (!ed) { - DEBUG_API(printk("cryptocop_setup_dma_list: alloc EOP descriptor for cipher\n")); - failed = -ENOMEM; - goto error_cleanup; - } - - assert(cipher_ctx.active && cipher_ctx.done); - - if (cipher_ctx.unit_no == src_dma){ - /* mem2mem */ - ed_mo.ciphsel = src_none; - } else { - ed_mo.ciphsel = cipher_ctx.current_src; - } - ed_mo.ciphconf = cipher_ctx.ciph_conf; - ed_mo.cbcmode = cipher_ctx.cbcmode; - ed_mo.decrypt = cipher_ctx.decrypt; - - ed->free_buf = NULL; - ed->dma_descr->wait = 1; - ed->dma_descr->out_eop = 1; - - ed->dma_descr->buf = (char*)virt_to_phys(&ed); /* Use any valid physical address for zero length descriptor. */ - ed->dma_descr->after = ed->dma_descr->buf; - ed->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, ed_mo); - current_out_cdesc->next = ed; - current_out_cdesc = ed; - } else { - /* Set EOP in the current out descriptor since the only active module is - * the one needing the EOP. */ - - current_out_cdesc->dma_descr->out_eop = 1; - } - } - - if (cipher_ctx.done && cipher_ctx.active) cipher_ctx.active = 0; - if (digest_ctx.done && digest_ctx.active) digest_ctx.active = 0; - if (csum_ctx.done && csum_ctx.active) csum_ctx.active = 0; - indata_ix += odsc->length; - odsc = odsc->next; - } /* while (odsc) */ /* Process descriptors. */ - DEBUG(printk("cryptocop_setup_dma_list: done parsing operation descriptors\n")); - if (cipher_ctx.tcfg && (cipher_ctx.active || !cipher_ctx.done)){ - DEBUG_API(printk("cryptocop_setup_dma_list: cipher operation not terminated.\n")); - failed = -EINVAL; - goto error_cleanup; - } - if (digest_ctx.tcfg && (digest_ctx.active || !digest_ctx.done)){ - DEBUG_API(printk("cryptocop_setup_dma_list: digest operation not terminated.\n")); - failed = -EINVAL; - goto error_cleanup; - } - if (csum_ctx.tcfg && (csum_ctx.active || !csum_ctx.done)){ - DEBUG_API(printk("cryptocop_setup_dma_list: csum operation not terminated.\n")); - failed = -EINVAL; - goto error_cleanup; - } - - failed = append_input_descriptors(operation, ¤t_in_cdesc, ¤t_out_cdesc, &cipher_ctx, alloc_flag); - if (failed){ - DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed)); - goto error_cleanup; - } - failed = append_input_descriptors(operation, ¤t_in_cdesc, ¤t_out_cdesc, &digest_ctx, alloc_flag); - if (failed){ - DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed)); - goto error_cleanup; - } - failed = append_input_descriptors(operation, ¤t_in_cdesc, ¤t_out_cdesc, &csum_ctx, alloc_flag); - if (failed){ - DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed)); - goto error_cleanup; - } - - DEBUG(printk("cryptocop_setup_dma_list: int_op=0x%p, *int_op=0x%p\n", int_op, *int_op)); - (*int_op)->cdesc_out = out_cdesc_head.next; - (*int_op)->cdesc_in = in_cdesc_head.next; - DEBUG(printk("cryptocop_setup_dma_list: out_cdesc_head=0x%p in_cdesc_head=0x%p\n", (*int_op)->cdesc_out, (*int_op)->cdesc_in)); - - setup_descr_chain(out_cdesc_head.next); - setup_descr_chain(in_cdesc_head.next); - - /* Last but not least: mark the last DMA in descriptor for a INTR and EOL and the the - * last DMA out descriptor for EOL. - */ - current_in_cdesc->dma_descr->intr = 1; - current_in_cdesc->dma_descr->eol = 1; - current_out_cdesc->dma_descr->eol = 1; - - /* Setup DMA contexts. */ - (*int_op)->ctx_out.next = NULL; - (*int_op)->ctx_out.eol = 1; - (*int_op)->ctx_out.intr = 0; - (*int_op)->ctx_out.store_mode = 0; - (*int_op)->ctx_out.en = 0; - (*int_op)->ctx_out.dis = 0; - (*int_op)->ctx_out.md0 = 0; - (*int_op)->ctx_out.md1 = 0; - (*int_op)->ctx_out.md2 = 0; - (*int_op)->ctx_out.md3 = 0; - (*int_op)->ctx_out.md4 = 0; - (*int_op)->ctx_out.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_out->dma_descr); - (*int_op)->ctx_out.saved_data_buf = (*int_op)->cdesc_out->dma_descr->buf; /* Already physical address. */ - - (*int_op)->ctx_in.next = NULL; - (*int_op)->ctx_in.eol = 1; - (*int_op)->ctx_in.intr = 0; - (*int_op)->ctx_in.store_mode = 0; - (*int_op)->ctx_in.en = 0; - (*int_op)->ctx_in.dis = 0; - (*int_op)->ctx_in.md0 = 0; - (*int_op)->ctx_in.md1 = 0; - (*int_op)->ctx_in.md2 = 0; - (*int_op)->ctx_in.md3 = 0; - (*int_op)->ctx_in.md4 = 0; - - (*int_op)->ctx_in.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_in->dma_descr); - (*int_op)->ctx_in.saved_data_buf = (*int_op)->cdesc_in->dma_descr->buf; /* Already physical address. */ - - DEBUG(printk("cryptocop_setup_dma_list: done\n")); - return 0; - -error_cleanup: - { - /* Free all allocated resources. */ - struct cryptocop_dma_desc *tmp_cdesc; - while (digest_ctx.pad_descs){ - tmp_cdesc = digest_ctx.pad_descs->next; - free_cdesc(digest_ctx.pad_descs); - digest_ctx.pad_descs = tmp_cdesc; - } - while (csum_ctx.pad_descs){ - tmp_cdesc = csum_ctx.pad_descs->next; - free_cdesc(csum_ctx.pad_descs); - csum_ctx.pad_descs = tmp_cdesc; - } - assert(cipher_ctx.pad_descs == NULL); /* The ciphers are never padded. */ - - if (*int_op != NULL) delete_internal_operation(*int_op); - } - DEBUG_API(printk("cryptocop_setup_dma_list: done with error %d\n", failed)); - return failed; -} - - -static void delete_internal_operation(struct cryptocop_int_operation *iop) -{ - void *ptr = iop->alloc_ptr; - struct cryptocop_dma_desc *cd = iop->cdesc_out; - struct cryptocop_dma_desc *next; - - DEBUG(printk("delete_internal_operation: iop=0x%p, alloc_ptr=0x%p\n", iop, ptr)); - - while (cd) { - next = cd->next; - free_cdesc(cd); - cd = next; - } - cd = iop->cdesc_in; - while (cd) { - next = cd->next; - free_cdesc(cd); - cd = next; - } - kfree(ptr); -} - -#define MD5_MIN_PAD_LENGTH (9) -#define MD5_PAD_LENGTH_FIELD_LENGTH (8) - -static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length) -{ - size_t padlen = MD5_BLOCK_LENGTH - (hashed_length % MD5_BLOCK_LENGTH); - unsigned char *p; - int i; - unsigned long long int bit_length = hashed_length << 3; - - if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH; - - p = kmalloc(padlen, alloc_flag); - if (!pad) return -ENOMEM; - - *p = 0x80; - memset(p+1, 0, padlen - 1); - - DEBUG(printk("create_md5_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length)); - - i = padlen - MD5_PAD_LENGTH_FIELD_LENGTH; - while (bit_length != 0){ - p[i++] = bit_length % 0x100; - bit_length >>= 8; - } - - *pad = (char*)p; - *pad_length = padlen; - - return 0; -} - -#define SHA1_MIN_PAD_LENGTH (9) -#define SHA1_PAD_LENGTH_FIELD_LENGTH (8) - -static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length) -{ - size_t padlen = SHA1_BLOCK_LENGTH - (hashed_length % SHA1_BLOCK_LENGTH); - unsigned char *p; - int i; - unsigned long long int bit_length = hashed_length << 3; - - if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH; - - p = kmalloc(padlen, alloc_flag); - if (!pad) return -ENOMEM; - - *p = 0x80; - memset(p+1, 0, padlen - 1); - - DEBUG(printk("create_sha1_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length)); - - i = padlen - 1; - while (bit_length != 0){ - p[i--] = bit_length % 0x100; - bit_length >>= 8; - } - - *pad = (char*)p; - *pad_length = padlen; - - return 0; -} - - -static int transform_ok(struct cryptocop_transform_init *tinit) -{ - switch (tinit->alg){ - case cryptocop_alg_csum: - switch (tinit->csum_mode){ - case cryptocop_csum_le: - case cryptocop_csum_be: - break; - default: - DEBUG_API(printk("transform_ok: Bad mode set for csum transform\n")); - return -EINVAL; - } - case cryptocop_alg_mem2mem: - case cryptocop_alg_md5: - case cryptocop_alg_sha1: - if (tinit->keylen != 0) { - DEBUG_API(printk("transform_ok: non-zero keylength, %d, for a digest/csum algorithm\n", tinit->keylen)); - return -EINVAL; /* This check is a bit strict. */ - } - break; - case cryptocop_alg_des: - if (tinit->keylen != 64) { - DEBUG_API(printk("transform_ok: keylen %d invalid for DES\n", tinit->keylen)); - return -EINVAL; - } - break; - case cryptocop_alg_3des: - if (tinit->keylen != 192) { - DEBUG_API(printk("transform_ok: keylen %d invalid for 3DES\n", tinit->keylen)); - return -EINVAL; - } - break; - case cryptocop_alg_aes: - if (tinit->keylen != 128 && tinit->keylen != 192 && tinit->keylen != 256) { - DEBUG_API(printk("transform_ok: keylen %d invalid for AES\n", tinit->keylen)); - return -EINVAL; - } - break; - case cryptocop_no_alg: - default: - DEBUG_API(printk("transform_ok: no such algorithm %d\n", tinit->alg)); - return -EINVAL; - } - - switch (tinit->alg){ - case cryptocop_alg_des: - case cryptocop_alg_3des: - case cryptocop_alg_aes: - if (tinit->cipher_mode != cryptocop_cipher_mode_ecb && tinit->cipher_mode != cryptocop_cipher_mode_cbc) return -EINVAL; - default: - break; - } - return 0; -} - - -int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag) -{ - struct cryptocop_session *sess; - struct cryptocop_transform_init *tfrm_in = tinit; - struct cryptocop_transform_init *tmp_in; - int no_tfrms = 0; - int i; - unsigned long int flags; - - init_stream_coprocessor(); /* For safety if we are called early */ - - while (tfrm_in){ - int err; - ++no_tfrms; - if ((err = transform_ok(tfrm_in))) { - DEBUG_API(printk("cryptocop_new_session, bad transform\n")); - return err; - } - tfrm_in = tfrm_in->next; - } - if (0 == no_tfrms) { - DEBUG_API(printk("cryptocop_new_session, no transforms specified\n")); - return -EINVAL; - } - - sess = kmalloc(sizeof(struct cryptocop_session), alloc_flag); - if (!sess){ - DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_session\n")); - return -ENOMEM; - } - - sess->tfrm_ctx = kmalloc(no_tfrms * sizeof(struct cryptocop_transform_ctx), alloc_flag); - if (!sess->tfrm_ctx) { - DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_transform_ctx\n")); - kfree(sess); - return -ENOMEM; - } - - tfrm_in = tinit; - for (i = 0; i < no_tfrms; i++){ - tmp_in = tfrm_in->next; - while (tmp_in){ - if (tmp_in->tid == tfrm_in->tid) { - DEBUG_API(printk("cryptocop_new_session, duplicate transform ids\n")); - kfree(sess->tfrm_ctx); - kfree(sess); - return -EINVAL; - } - tmp_in = tmp_in->next; - } - memcpy(&sess->tfrm_ctx[i].init, tfrm_in, sizeof(struct cryptocop_transform_init)); - sess->tfrm_ctx[i].dec_key_set = 0; - sess->tfrm_ctx[i].next = &sess->tfrm_ctx[i] + 1; - - tfrm_in = tfrm_in->next; - } - sess->tfrm_ctx[i-1].next = NULL; - - spin_lock_irqsave(&cryptocop_sessions_lock, flags); - sess->sid = next_sid; - next_sid++; - /* TODO If we are really paranoid we should do duplicate check to handle sid wraparound. - * OTOH 2^64 is a really large number of session. */ - if (next_sid == 0) next_sid = 1; - - /* Prepend to session list. */ - sess->next = cryptocop_sessions; - cryptocop_sessions = sess; - spin_unlock_irqrestore(&cryptocop_sessions_lock, flags); - *sid = sess->sid; - return 0; -} - - -int cryptocop_free_session(cryptocop_session_id sid) -{ - struct cryptocop_transform_ctx *tc; - struct cryptocop_session *sess = NULL; - struct cryptocop_session *psess = NULL; - unsigned long int flags; - int i; - LIST_HEAD(remove_list); - struct list_head *node, *tmp; - struct cryptocop_prio_job *pj; - - DEBUG(printk("cryptocop_free_session: sid=%lld\n", sid)); - - spin_lock_irqsave(&cryptocop_sessions_lock, flags); - sess = cryptocop_sessions; - while (sess && sess->sid != sid){ - psess = sess; - sess = sess->next; - } - if (sess){ - if (psess){ - psess->next = sess->next; - } else { - cryptocop_sessions = sess->next; - } - } - spin_unlock_irqrestore(&cryptocop_sessions_lock, flags); - - if (!sess) return -EINVAL; - - /* Remove queued jobs. */ - spin_lock_irqsave(&cryptocop_job_queue_lock, flags); - - for (i = 0; i < cryptocop_prio_no_prios; i++){ - if (!list_empty(&(cryptocop_job_queues[i].jobs))){ - list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) { - pj = list_entry(node, struct cryptocop_prio_job, node); - if (pj->oper->sid == sid) { - list_move_tail(node, &remove_list); - } - } - } - } - spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); - - list_for_each_safe(node, tmp, &remove_list) { - list_del(node); - pj = list_entry(node, struct cryptocop_prio_job, node); - pj->oper->operation_status = -EAGAIN; /* EAGAIN is not ideal for job/session terminated but it's the best choice I know of. */ - DEBUG(printk("cryptocop_free_session: pj=0x%p, pj->oper=0x%p, pj->iop=0x%p\n", pj, pj->oper, pj->iop)); - pj->oper->cb(pj->oper, pj->oper->cb_data); - delete_internal_operation(pj->iop); - kfree(pj); - } - - tc = sess->tfrm_ctx; - /* Erase keying data. */ - while (tc){ - DEBUG(printk("cryptocop_free_session: memset keys, tfrm id=%d\n", tc->init.tid)); - memset(tc->init.key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH); - memset(tc->dec_key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH); - tc = tc->next; - } - kfree(sess->tfrm_ctx); - kfree(sess); - - return 0; -} - -static struct cryptocop_session *get_session(cryptocop_session_id sid) -{ - struct cryptocop_session *sess; - unsigned long int flags; - - spin_lock_irqsave(&cryptocop_sessions_lock, flags); - sess = cryptocop_sessions; - while (sess && (sess->sid != sid)){ - sess = sess->next; - } - spin_unlock_irqrestore(&cryptocop_sessions_lock, flags); - - return sess; -} - -static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid) -{ - struct cryptocop_transform_ctx *tc = sess->tfrm_ctx; - - DEBUG(printk("get_transform_ctx, sess=0x%p, tid=%d\n", sess, tid)); - assert(sess != NULL); - while (tc && tc->init.tid != tid){ - DEBUG(printk("tc=0x%p, tc->next=0x%p\n", tc, tc->next)); - tc = tc->next; - } - DEBUG(printk("get_transform_ctx, returning tc=0x%p\n", tc)); - return tc; -} - - - -/* The AES s-transform matrix (s-box). */ -static const u8 aes_sbox[256] = { - 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118, - 202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192, - 183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21, - 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117, - 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132, - 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207, - 208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168, - 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210, - 205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115, - 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219, - 224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121, - 231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8, - 186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138, - 112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158, - 225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223, - 140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22 -}; - -/* AES has a 32 bit word round constants for each round in the - * key schedule. round_constant[i] is really Rcon[i+1] in FIPS187. - */ -static u32 round_constant[11] = { - 0x01000000, 0x02000000, 0x04000000, 0x08000000, - 0x10000000, 0x20000000, 0x40000000, 0x80000000, - 0x1B000000, 0x36000000, 0x6C000000 -}; - -/* Apply the s-box to each of the four occtets in w. */ -static u32 aes_ks_subword(const u32 w) -{ - u8 bytes[4]; - - *(u32*)(&bytes[0]) = w; - bytes[0] = aes_sbox[bytes[0]]; - bytes[1] = aes_sbox[bytes[1]]; - bytes[2] = aes_sbox[bytes[2]]; - bytes[3] = aes_sbox[bytes[3]]; - return *(u32*)(&bytes[0]); -} - -/* The encrypt (forward) Rijndael key schedule algorithm pseudo code: - * (Note that AES words are 32 bit long) - * - * KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)], Nk){ - * word temp - * i = 0 - * while (i < Nk) { - * w[i] = word(key[4*i, 4*i + 1, 4*i + 2, 4*i + 3]) - * i = i + 1 - * } - * i = Nk - * - * while (i < (Nb * (Nr + 1))) { - * temp = w[i - 1] - * if ((i mod Nk) == 0) { - * temp = SubWord(RotWord(temp)) xor Rcon[i/Nk] - * } - * else if ((Nk > 6) && ((i mod Nk) == 4)) { - * temp = SubWord(temp) - * } - * w[i] = w[i - Nk] xor temp - * } - * RotWord(t) does a 8 bit cyclic shift left on a 32 bit word. - * SubWord(t) applies the AES s-box individually to each octet - * in a 32 bit word. - * - * For AES Nk can have the values 4, 6, and 8 (corresponding to - * values for Nr of 10, 12, and 14). Nb is always 4. - * - * To construct w[i], w[i - 1] and w[i - Nk] must be - * available. Consequently we must keep a state of the last Nk words - * to be able to create the last round keys. - */ -static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength) -{ - u32 temp; - u32 w_ring[8]; /* nk is max 8, use elements 0..(nk - 1) as a ringbuffer */ - u8 w_last_ix; - int i; - u8 nr, nk; - - switch (keylength){ - case 128: - nk = 4; - nr = 10; - break; - case 192: - nk = 6; - nr = 12; - break; - case 256: - nk = 8; - nr = 14; - break; - default: - panic("stream co-processor: bad aes key length in get_aes_decrypt_key\n"); - }; - - /* Need to do host byte order correction here since key is byte oriented and the - * kx algorithm is word (u32) oriented. */ - for (i = 0; i < nk; i+=1) { - w_ring[i] = be32_to_cpu(*(u32*)&key[4*i]); - } - - i = (int)nk; - w_last_ix = i - 1; - while (i < (4 * (nr + 2))) { - temp = w_ring[w_last_ix]; - if (!(i % nk)) { - /* RotWord(temp) */ - temp = (temp << 8) | (temp >> 24); - temp = aes_ks_subword(temp); - temp ^= round_constant[i/nk - 1]; - } else if ((nk > 6) && ((i % nk) == 4)) { - temp = aes_ks_subword(temp); - } - w_last_ix = (w_last_ix + 1) % nk; /* This is the same as (i-Nk) mod Nk */ - temp ^= w_ring[w_last_ix]; - w_ring[w_last_ix] = temp; - - /* We need the round keys for round Nr+1 and Nr+2 (round key - * Nr+2 is the round key beyond the last one used when - * encrypting). Rounds are numbered starting from 0, Nr=10 - * implies 11 rounds are used in encryption/decryption. - */ - if (i >= (4 * nr)) { - /* Need to do host byte order correction here, the key - * is byte oriented. */ - *(u32*)dec_key = cpu_to_be32(temp); - dec_key += 4; - } - ++i; - } -} - - -/**** Job/operation management. ****/ - -int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation) -{ - return cryptocop_job_queue_insert(cryptocop_prio_kernel_csum, operation); -} - -int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation) -{ - return cryptocop_job_queue_insert(cryptocop_prio_kernel, operation); -} - -int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation) -{ - return cryptocop_job_queue_insert(cryptocop_prio_user, operation); -} - -static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation) -{ - int ret; - struct cryptocop_prio_job *pj = NULL; - unsigned long int flags; - - DEBUG(printk("cryptocop_job_queue_insert(%d, 0x%p)\n", prio, operation)); - - if (!operation || !operation->cb){ - DEBUG_API(printk("cryptocop_job_queue_insert oper=0x%p, NULL operation or callback\n", operation)); - return -EINVAL; - } - - if ((ret = cryptocop_job_setup(&pj, operation)) != 0){ - DEBUG_API(printk("cryptocop_job_queue_insert: job setup failed\n")); - return ret; - } - assert(pj != NULL); - - spin_lock_irqsave(&cryptocop_job_queue_lock, flags); - list_add_tail(&pj->node, &cryptocop_job_queues[prio].jobs); - spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); - - /* Make sure a job is running */ - cryptocop_start_job(); - return 0; -} - -static void cryptocop_do_tasklet(unsigned long unused); -DECLARE_TASKLET (cryptocop_tasklet, cryptocop_do_tasklet, 0); - -static void cryptocop_do_tasklet(unsigned long unused) -{ - struct list_head *node; - struct cryptocop_prio_job *pj = NULL; - unsigned long flags; - - DEBUG(printk("cryptocop_do_tasklet: entering\n")); - - do { - spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags); - if (!list_empty(&cryptocop_completed_jobs)){ - node = cryptocop_completed_jobs.next; - list_del(node); - pj = list_entry(node, struct cryptocop_prio_job, node); - } else { - pj = NULL; - } - spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags); - if (pj) { - assert(pj->oper != NULL); - - /* Notify consumer of operation completeness. */ - DEBUG(printk("cryptocop_do_tasklet: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); - - pj->oper->operation_status = 0; /* Job is completed. */ - pj->oper->cb(pj->oper, pj->oper->cb_data); - delete_internal_operation(pj->iop); - kfree(pj); - } - } while (pj != NULL); - - DEBUG(printk("cryptocop_do_tasklet: exiting\n")); -} - -static irqreturn_t -dma_done_interrupt(int irq, void *dev_id, struct pt_regs * regs) -{ - struct cryptocop_prio_job *done_job; - reg_dma_rw_ack_intr ack_intr = { - .data = 1, - }; - - REG_WR (dma, regi_dma9, rw_ack_intr, ack_intr); - - DEBUG(printk("cryptocop DMA done\n")); - - spin_lock(&running_job_lock); - if (cryptocop_running_job == NULL){ - printk("stream co-processor got interrupt when not busy\n"); - spin_unlock(&running_job_lock); - return IRQ_HANDLED; - } - done_job = cryptocop_running_job; - cryptocop_running_job = NULL; - spin_unlock(&running_job_lock); - - /* Start processing a job. */ - if (!spin_trylock(&cryptocop_process_lock)){ - DEBUG(printk("cryptocop irq handler, not starting a job\n")); - } else { - cryptocop_start_job(); - spin_unlock(&cryptocop_process_lock); - } - - done_job->oper->operation_status = 0; /* Job is completed. */ - if (done_job->oper->fast_callback){ - /* This operation wants callback from interrupt. */ - done_job->oper->cb(done_job->oper, done_job->oper->cb_data); - delete_internal_operation(done_job->iop); - kfree(done_job); - } else { - spin_lock(&cryptocop_completed_jobs_lock); - list_add_tail(&(done_job->node), &cryptocop_completed_jobs); - spin_unlock(&cryptocop_completed_jobs_lock); - tasklet_schedule(&cryptocop_tasklet); - } - - DEBUG(printk("cryptocop leave irq handler\n")); - return IRQ_HANDLED; -} - - -/* Setup interrupts and DMA channels. */ -static int init_cryptocop(void) -{ - unsigned long flags; - reg_intr_vect_rw_mask intr_mask; - reg_dma_rw_cfg dma_cfg = {.en = 1}; - reg_dma_rw_intr_mask intr_mask_in = {.data = regk_dma_yes}; /* Only want descriptor interrupts from the DMA in channel. */ - reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 }; - reg_strcop_rw_cfg strcop_cfg = { - .ipend = regk_strcop_little, - .td1 = regk_strcop_e, - .td2 = regk_strcop_d, - .td3 = regk_strcop_e, - .ignore_sync = 0, - .en = 1 - }; - - if (request_irq(DMA9_INTR_VECT, dma_done_interrupt, 0, "stream co-processor DMA", NULL)) panic("request_irq stream co-processor irq dma9"); - - (void)crisv32_request_dma(8, "strcop", DMA_PANIC_ON_ERROR, 0, dma_strp); - (void)crisv32_request_dma(9, "strcop", DMA_PANIC_ON_ERROR, 0, dma_strp); - - local_irq_save(flags); - - /* Reset and enable the cryptocop. */ - strcop_cfg.en = 0; - REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); - strcop_cfg.en = 1; - REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); - - /* Enable DMA9 interrupt */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.dma9 = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - /* Enable DMAs. */ - REG_WR(dma, regi_dma9, rw_cfg, dma_cfg); /* input DMA */ - REG_WR(dma, regi_dma8, rw_cfg, dma_cfg); /* output DMA */ - - /* Set up wordsize = 4 for DMAs. */ - DMA_WR_CMD (regi_dma8, regk_dma_set_w_size4); - DMA_WR_CMD (regi_dma9, regk_dma_set_w_size4); - - /* Enable interrupts. */ - REG_WR(dma, regi_dma9, rw_intr_mask, intr_mask_in); - - /* Clear intr ack. */ - REG_WR(dma, regi_dma9, rw_ack_intr, ack_intr); - - local_irq_restore(flags); - - return 0; -} - -/* Free used cryptocop hw resources (interrupt and DMA channels). */ -static void release_cryptocop(void) -{ - unsigned long flags; - reg_intr_vect_rw_mask intr_mask; - reg_dma_rw_cfg dma_cfg = {.en = 0}; - reg_dma_rw_intr_mask intr_mask_in = {0}; - reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 }; - - local_irq_save(flags); - - /* Clear intr ack. */ - REG_WR(dma, regi_dma9, rw_ack_intr, ack_intr); - - /* Disable DMA9 interrupt */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.dma9 = 0; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - /* Disable DMAs. */ - REG_WR(dma, regi_dma9, rw_cfg, dma_cfg); /* input DMA */ - REG_WR(dma, regi_dma8, rw_cfg, dma_cfg); /* output DMA */ - - /* Disable interrupts. */ - REG_WR(dma, regi_dma9, rw_intr_mask, intr_mask_in); - - local_irq_restore(flags); - - free_irq(DMA9_INTR_VECT, NULL); - - (void)crisv32_free_dma(8); - (void)crisv32_free_dma(9); -} - - -/* Init job queue. */ -static int cryptocop_job_queue_init(void) -{ - int i; - - INIT_LIST_HEAD(&cryptocop_completed_jobs); - - for (i = 0; i < cryptocop_prio_no_prios; i++){ - cryptocop_job_queues[i].prio = (cryptocop_queue_priority)i; - INIT_LIST_HEAD(&cryptocop_job_queues[i].jobs); - } - return 0; -} - - -static void cryptocop_job_queue_close(void) -{ - struct list_head *node, *tmp; - struct cryptocop_prio_job *pj = NULL; - unsigned long int process_flags, flags; - int i; - - /* FIXME: This is as yet untested code. */ - - /* Stop strcop from getting an operation to process while we are closing the - module. */ - spin_lock_irqsave(&cryptocop_process_lock, process_flags); - - /* Empty the job queue. */ - spin_lock_irqsave(&cryptocop_process_lock, process_flags); - for (i = 0; i < cryptocop_prio_no_prios; i++){ - if (!list_empty(&(cryptocop_job_queues[i].jobs))){ - list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) { - pj = list_entry(node, struct cryptocop_prio_job, node); - list_del(node); - - /* Call callback to notify consumer of job removal. */ - DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); - pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */ - pj->oper->cb(pj->oper, pj->oper->cb_data); - - delete_internal_operation(pj->iop); - kfree(pj); - } - } - } - spin_unlock_irqrestore(&cryptocop_process_lock, process_flags); - - /* Remove the running job, if any. */ - spin_lock_irqsave(&running_job_lock, flags); - if (cryptocop_running_job){ - reg_strcop_rw_cfg rw_cfg; - reg_dma_rw_cfg dma_out_cfg, dma_in_cfg; - - /* Stop DMA. */ - dma_out_cfg = REG_RD(dma, regi_dma8, rw_cfg); - dma_out_cfg.en = regk_dma_no; - REG_WR(dma, regi_dma8, rw_cfg, dma_out_cfg); - - dma_in_cfg = REG_RD(dma, regi_dma9, rw_cfg); - dma_in_cfg.en = regk_dma_no; - REG_WR(dma, regi_dma9, rw_cfg, dma_in_cfg); - - /* Disble the cryptocop. */ - rw_cfg = REG_RD(strcop, regi_strcop, rw_cfg); - rw_cfg.en = 0; - REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg); - - pj = cryptocop_running_job; - cryptocop_running_job = NULL; - - /* Call callback to notify consumer of job removal. */ - DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); - pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */ - pj->oper->cb(pj->oper, pj->oper->cb_data); - - delete_internal_operation(pj->iop); - kfree(pj); - } - spin_unlock_irqrestore(&running_job_lock, flags); - - /* Remove completed jobs, if any. */ - spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags); - - list_for_each_safe(node, tmp, &cryptocop_completed_jobs) { - pj = list_entry(node, struct cryptocop_prio_job, node); - list_del(node); - /* Call callback to notify consumer of job removal. */ - DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); - pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */ - pj->oper->cb(pj->oper, pj->oper->cb_data); - - delete_internal_operation(pj->iop); - kfree(pj); - } - spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags); -} - - -static void cryptocop_start_job(void) -{ - int i; - struct cryptocop_prio_job *pj; - unsigned long int flags; - unsigned long int running_job_flags; - reg_strcop_rw_cfg rw_cfg = {.en = 1, .ignore_sync = 0}; - - DEBUG(printk("cryptocop_start_job: entering\n")); - - spin_lock_irqsave(&running_job_lock, running_job_flags); - if (cryptocop_running_job != NULL){ - /* Already running. */ - DEBUG(printk("cryptocop_start_job: already running, exit\n")); - spin_unlock_irqrestore(&running_job_lock, running_job_flags); - return; - } - spin_lock_irqsave(&cryptocop_job_queue_lock, flags); - - /* Check the queues in priority order. */ - for (i = cryptocop_prio_kernel_csum; (i < cryptocop_prio_no_prios) && list_empty(&cryptocop_job_queues[i].jobs); i++); - if (i == cryptocop_prio_no_prios) { - spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); - spin_unlock_irqrestore(&running_job_lock, running_job_flags); - DEBUG(printk("cryptocop_start_job: no jobs to run\n")); - return; /* No jobs to run */ - } - DEBUG(printk("starting job for prio %d\n", i)); - - /* TODO: Do not starve lower priority jobs. Let in a lower - * prio job for every N-th processed higher prio job or some - * other scheduling policy. This could reasonably be - * tweakable since the optimal balance would depend on the - * type of load on the system. */ - - /* Pull the DMA lists from the job and start the DMA client. */ - pj = list_entry(cryptocop_job_queues[i].jobs.next, struct cryptocop_prio_job, node); - list_del(&pj->node); - spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); - cryptocop_running_job = pj; - - /* Set config register (3DES and CSUM modes). */ - switch (pj->iop->tdes_mode){ - case cryptocop_3des_eee: - rw_cfg.td1 = regk_strcop_e; - rw_cfg.td2 = regk_strcop_e; - rw_cfg.td3 = regk_strcop_e; - break; - case cryptocop_3des_eed: - rw_cfg.td1 = regk_strcop_e; - rw_cfg.td2 = regk_strcop_e; - rw_cfg.td3 = regk_strcop_d; - break; - case cryptocop_3des_ede: - rw_cfg.td1 = regk_strcop_e; - rw_cfg.td2 = regk_strcop_d; - rw_cfg.td3 = regk_strcop_e; - break; - case cryptocop_3des_edd: - rw_cfg.td1 = regk_strcop_e; - rw_cfg.td2 = regk_strcop_d; - rw_cfg.td3 = regk_strcop_d; - break; - case cryptocop_3des_dee: - rw_cfg.td1 = regk_strcop_d; - rw_cfg.td2 = regk_strcop_e; - rw_cfg.td3 = regk_strcop_e; - break; - case cryptocop_3des_ded: - rw_cfg.td1 = regk_strcop_d; - rw_cfg.td2 = regk_strcop_e; - rw_cfg.td3 = regk_strcop_d; - break; - case cryptocop_3des_dde: - rw_cfg.td1 = regk_strcop_d; - rw_cfg.td2 = regk_strcop_d; - rw_cfg.td3 = regk_strcop_e; - break; - case cryptocop_3des_ddd: - rw_cfg.td1 = regk_strcop_d; - rw_cfg.td2 = regk_strcop_d; - rw_cfg.td3 = regk_strcop_d; - break; - default: - DEBUG(printk("cryptocop_setup_dma_list: bad 3DES mode\n")); - } - switch (pj->iop->csum_mode){ - case cryptocop_csum_le: - rw_cfg.ipend = regk_strcop_little; - break; - case cryptocop_csum_be: - rw_cfg.ipend = regk_strcop_big; - break; - default: - DEBUG(printk("cryptocop_setup_dma_list: bad checksum mode\n")); - } - REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg); - - DEBUG(printk("cryptocop_start_job: starting DMA, new cryptocop_running_job=0x%p\n" - "ctx_in: 0x%p, phys: 0x%p\n" - "ctx_out: 0x%p, phys: 0x%p\n", - pj, - &pj->iop->ctx_in, (char*)virt_to_phys(&pj->iop->ctx_in), - &pj->iop->ctx_out, (char*)virt_to_phys(&pj->iop->ctx_out))); - - /* Start input DMA. */ - DMA_START_CONTEXT(regi_dma9, virt_to_phys(&pj->iop->ctx_in)); - - /* Start output DMA. */ - DMA_START_CONTEXT(regi_dma8, virt_to_phys(&pj->iop->ctx_out)); - - spin_unlock_irqrestore(&running_job_lock, running_job_flags); - DEBUG(printk("cryptocop_start_job: exiting\n")); -} - - -static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation) -{ - int err; - int alloc_flag = operation->in_interrupt ? GFP_ATOMIC : GFP_KERNEL; - void *iop_alloc_ptr = NULL; - - *pj = kmalloc(sizeof (struct cryptocop_prio_job), alloc_flag); - if (!*pj) return -ENOMEM; - - DEBUG(printk("cryptocop_job_setup: operation=0x%p\n", operation)); - - (*pj)->oper = operation; - DEBUG(printk("cryptocop_job_setup, cb=0x%p cb_data=0x%p\n", (*pj)->oper->cb, (*pj)->oper->cb_data)); - - if (operation->use_dmalists) { - DEBUG(print_user_dma_lists(&operation->list_op)); - if (!operation->list_op.inlist || !operation->list_op.outlist || !operation->list_op.out_data_buf || !operation->list_op.in_data_buf){ - DEBUG_API(printk("cryptocop_job_setup: bad indata (use_dmalists)\n")); - kfree(*pj); - return -EINVAL; - } - iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag); - if (!iop_alloc_ptr) { - DEBUG_API(printk("cryptocop_job_setup: kmalloc cryptocop_int_operation\n")); - kfree(*pj); - return -ENOMEM; - } - (*pj)->iop = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out)); - DEBUG(memset((*pj)->iop, 0xff, sizeof(struct cryptocop_int_operation))); - (*pj)->iop->alloc_ptr = iop_alloc_ptr; - (*pj)->iop->sid = operation->sid; - (*pj)->iop->cdesc_out = NULL; - (*pj)->iop->cdesc_in = NULL; - (*pj)->iop->tdes_mode = operation->list_op.tdes_mode; - (*pj)->iop->csum_mode = operation->list_op.csum_mode; - (*pj)->iop->ddesc_out = operation->list_op.outlist; - (*pj)->iop->ddesc_in = operation->list_op.inlist; - - /* Setup DMA contexts. */ - (*pj)->iop->ctx_out.next = NULL; - (*pj)->iop->ctx_out.eol = 1; - (*pj)->iop->ctx_out.saved_data = operation->list_op.outlist; - (*pj)->iop->ctx_out.saved_data_buf = operation->list_op.out_data_buf; - - (*pj)->iop->ctx_in.next = NULL; - (*pj)->iop->ctx_in.eol = 1; - (*pj)->iop->ctx_in.saved_data = operation->list_op.inlist; - (*pj)->iop->ctx_in.saved_data_buf = operation->list_op.in_data_buf; - } else { - if ((err = cryptocop_setup_dma_list(operation, &(*pj)->iop, alloc_flag))) { - DEBUG_API(printk("cryptocop_job_setup: cryptocop_setup_dma_list failed %d\n", err)); - kfree(*pj); - return err; - } - } - DEBUG(print_dma_descriptors((*pj)->iop)); - - DEBUG(printk("cryptocop_job_setup, DMA list setup successful\n")); - - return 0; -} - - -static int cryptocop_open(struct inode *inode, struct file *filp) -{ - int p = MINOR(inode->i_rdev); - - if (p != CRYPTOCOP_MINOR) return -EINVAL; - - filp->private_data = NULL; - return 0; -} - - -static int cryptocop_release(struct inode *inode, struct file *filp) -{ - struct cryptocop_private *dev = filp->private_data; - struct cryptocop_private *dev_next; - - while (dev){ - dev_next = dev->next; - if (dev->sid != CRYPTOCOP_SESSION_ID_NONE) { - (void)cryptocop_free_session(dev->sid); - } - kfree(dev); - dev = dev_next; - } - - return 0; -} - - -static int cryptocop_ioctl_close_session(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) -{ - struct cryptocop_private *dev = filp->private_data; - struct cryptocop_private *prev_dev = NULL; - struct strcop_session_op *sess_op = (struct strcop_session_op *)arg; - struct strcop_session_op sop; - int err; - - DEBUG(printk("cryptocop_ioctl_close_session\n")); - - if (!access_ok(VERIFY_READ, sess_op, sizeof(struct strcop_session_op))) - return -EFAULT; - err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op)); - if (err) return -EFAULT; - - while (dev && (dev->sid != sop.ses_id)) { - prev_dev = dev; - dev = dev->next; - } - if (dev){ - if (prev_dev){ - prev_dev->next = dev->next; - } else { - filp->private_data = dev->next; - } - err = cryptocop_free_session(dev->sid); - if (err) return -EFAULT; - } else { - DEBUG_API(printk("cryptocop_ioctl_close_session: session %lld not found\n", sop.ses_id)); - return -EINVAL; - } - return 0; -} - - -static void ioctl_process_job_callback(struct cryptocop_operation *op, void*cb_data) -{ - struct ioctl_job_cb_ctx *jc = (struct ioctl_job_cb_ctx *)cb_data; - - DEBUG(printk("ioctl_process_job_callback: op=0x%p, cb_data=0x%p\n", op, cb_data)); - - jc->processed = 1; - wake_up(&cryptocop_ioc_process_wq); -} - - -#define CRYPTOCOP_IOCTL_CIPHER_TID (1) -#define CRYPTOCOP_IOCTL_DIGEST_TID (2) -#define CRYPTOCOP_IOCTL_CSUM_TID (3) - -static size_t first_cfg_change_ix(struct strcop_crypto_op *crp_op) -{ - size_t ch_ix = 0; - - if (crp_op->do_cipher) ch_ix = crp_op->cipher_start; - if (crp_op->do_digest && (crp_op->digest_start < ch_ix)) ch_ix = crp_op->digest_start; - if (crp_op->do_csum && (crp_op->csum_start < ch_ix)) ch_ix = crp_op->csum_start; - - DEBUG(printk("first_cfg_change_ix: ix=%d\n", ch_ix)); - return ch_ix; -} - - -static size_t next_cfg_change_ix(struct strcop_crypto_op *crp_op, size_t ix) -{ - size_t ch_ix = INT_MAX; - size_t tmp_ix = 0; - - if (crp_op->do_cipher && ((crp_op->cipher_start + crp_op->cipher_len) > ix)){ - if (crp_op->cipher_start > ix) { - ch_ix = crp_op->cipher_start; - } else { - ch_ix = crp_op->cipher_start + crp_op->cipher_len; - } - } - if (crp_op->do_digest && ((crp_op->digest_start + crp_op->digest_len) > ix)){ - if (crp_op->digest_start > ix) { - tmp_ix = crp_op->digest_start; - } else { - tmp_ix = crp_op->digest_start + crp_op->digest_len; - } - if (tmp_ix < ch_ix) ch_ix = tmp_ix; - } - if (crp_op->do_csum && ((crp_op->csum_start + crp_op->csum_len) > ix)){ - if (crp_op->csum_start > ix) { - tmp_ix = crp_op->csum_start; - } else { - tmp_ix = crp_op->csum_start + crp_op->csum_len; - } - if (tmp_ix < ch_ix) ch_ix = tmp_ix; - } - if (ch_ix == INT_MAX) ch_ix = ix; - DEBUG(printk("next_cfg_change_ix prev ix=%d, next ix=%d\n", ix, ch_ix)); - return ch_ix; -} - - -/* Map map_length bytes from the pages starting on *pageix and *pageoffset to iovecs starting on *iovix. - * Return -1 for ok, 0 for fail. */ -static int map_pages_to_iovec(struct iovec *iov, int iovlen, int *iovix, struct page **pages, int nopages, int *pageix, int *pageoffset, int map_length ) -{ - int tmplen; - - assert(iov != NULL); - assert(iovix != NULL); - assert(pages != NULL); - assert(pageix != NULL); - assert(pageoffset != NULL); - - DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset)); - - while (map_length > 0){ - DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset)); - if (*iovix >= iovlen){ - DEBUG_API(printk("map_page_to_iovec: *iovix=%d >= iovlen=%d\n", *iovix, iovlen)); - return 0; - } - if (*pageix >= nopages){ - DEBUG_API(printk("map_page_to_iovec: *pageix=%d >= nopages=%d\n", *pageix, nopages)); - return 0; - } - iov[*iovix].iov_base = (unsigned char*)page_address(pages[*pageix]) + *pageoffset; - tmplen = PAGE_SIZE - *pageoffset; - if (tmplen < map_length){ - (*pageoffset) = 0; - (*pageix)++; - } else { - tmplen = map_length; - (*pageoffset) += map_length; - } - DEBUG(printk("mapping %d bytes from page %d (or %d) to iovec %d\n", tmplen, *pageix, *pageix-1, *iovix)); - iov[*iovix].iov_len = tmplen; - map_length -= tmplen; - (*iovix)++; - } - DEBUG(printk("map_page_to_iovec, exit, *iovix=%d\n", *iovix)); - return -1; -} - - - -static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) -{ - int i; - struct cryptocop_private *dev = filp->private_data; - struct strcop_crypto_op *crp_oper = (struct strcop_crypto_op *)arg; - struct strcop_crypto_op oper = {0}; - int err = 0; - struct cryptocop_operation *cop = NULL; - - struct ioctl_job_cb_ctx *jc = NULL; - - struct page **inpages = NULL; - struct page **outpages = NULL; - int noinpages = 0; - int nooutpages = 0; - - struct cryptocop_desc descs[5]; /* Max 5 descriptors are needed, there are three transforms that - * can get connected/disconnected on different places in the indata. */ - struct cryptocop_desc_cfg dcfgs[5*3]; - int desc_ix = 0; - int dcfg_ix = 0; - struct cryptocop_tfrm_cfg ciph_tcfg = {0}; - struct cryptocop_tfrm_cfg digest_tcfg = {0}; - struct cryptocop_tfrm_cfg csum_tcfg = {0}; - - unsigned char *digest_result = NULL; - int digest_length = 0; - int cblocklen = 0; - unsigned char csum_result[CSUM_BLOCK_LENGTH]; - struct cryptocop_session *sess; - - int iovlen = 0; - int iovix = 0; - int pageix = 0; - int pageoffset = 0; - - size_t prev_ix = 0; - size_t next_ix; - - int cipher_active, digest_active, csum_active; - int end_digest, end_csum; - int digest_done = 0; - int cipher_done = 0; - int csum_done = 0; - - DEBUG(printk("cryptocop_ioctl_process\n")); - - if (!access_ok(VERIFY_WRITE, crp_oper, sizeof(struct strcop_crypto_op))){ - DEBUG_API(printk("cryptocop_ioctl_process: !access_ok crp_oper!\n")); - return -EFAULT; - } - if (copy_from_user(&oper, crp_oper, sizeof(struct strcop_crypto_op))) { - DEBUG_API(printk("cryptocop_ioctl_process: copy_from_user\n")); - return -EFAULT; - } - DEBUG(print_strcop_crypto_op(&oper)); - - while (dev && dev->sid != oper.ses_id) dev = dev->next; - if (!dev){ - DEBUG_API(printk("cryptocop_ioctl_process: session %lld not found\n", oper.ses_id)); - return -EINVAL; - } - - /* Check buffers. */ - if (((oper.indata + oper.inlen) < oper.indata) || ((oper.cipher_outdata + oper.cipher_outlen) < oper.cipher_outdata)){ - DEBUG_API(printk("cryptocop_ioctl_process: user buffers wrapped around, bad user!\n")); - return -EINVAL; - } - - if (!access_ok(VERIFY_WRITE, oper.cipher_outdata, oper.cipher_outlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: !access_ok out data!\n")); - return -EFAULT; - } - if (!access_ok(VERIFY_READ, oper.indata, oper.inlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: !access_ok in data!\n")); - return -EFAULT; - } - - cop = kmalloc(sizeof(struct cryptocop_operation), GFP_KERNEL); - if (!cop) { - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n")); - return -ENOMEM; - } - jc = kmalloc(sizeof(struct ioctl_job_cb_ctx), GFP_KERNEL); - if (!jc) { - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n")); - err = -ENOMEM; - goto error_cleanup; - } - jc->processed = 0; - - cop->cb_data = jc; - cop->cb = ioctl_process_job_callback; - cop->operation_status = 0; - cop->use_dmalists = 0; - cop->in_interrupt = 0; - cop->fast_callback = 0; - cop->tfrm_op.tfrm_cfg = NULL; - cop->tfrm_op.desc = NULL; - cop->tfrm_op.indata = NULL; - cop->tfrm_op.incount = 0; - cop->tfrm_op.inlen = 0; - cop->tfrm_op.outdata = NULL; - cop->tfrm_op.outcount = 0; - cop->tfrm_op.outlen = 0; - - sess = get_session(oper.ses_id); - if (!sess){ - DEBUG_API(printk("cryptocop_ioctl_process: bad session id.\n")); - kfree(cop); - kfree(jc); - return -EINVAL; - } - - if (oper.do_cipher) { - unsigned int cipher_outlen = 0; - struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_CIPHER_TID); - if (!tc) { - DEBUG_API(printk("cryptocop_ioctl_process: no cipher transform in session.\n")); - err = -EINVAL; - goto error_cleanup; - } - ciph_tcfg.tid = CRYPTOCOP_IOCTL_CIPHER_TID; - ciph_tcfg.inject_ix = 0; - ciph_tcfg.flags = 0; - if ((oper.cipher_start < 0) || (oper.cipher_len <= 0) || (oper.cipher_start > oper.inlen) || ((oper.cipher_start + oper.cipher_len) > oper.inlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: bad cipher length\n")); - kfree(cop); - kfree(jc); - return -EINVAL; - } - cblocklen = tc->init.alg == cryptocop_alg_aes ? AES_BLOCK_LENGTH : DES_BLOCK_LENGTH; - if (oper.cipher_len % cblocklen) { - kfree(cop); - kfree(jc); - DEBUG_API(printk("cryptocop_ioctl_process: cipher inlength not multiple of block length.\n")); - return -EINVAL; - } - cipher_outlen = oper.cipher_len; - if (tc->init.cipher_mode == cryptocop_cipher_mode_cbc){ - if (oper.cipher_explicit) { - ciph_tcfg.flags |= CRYPTOCOP_EXPLICIT_IV; - memcpy(ciph_tcfg.iv, oper.cipher_iv, cblocklen); - } else { - cipher_outlen = oper.cipher_len - cblocklen; - } - } else { - if (oper.cipher_explicit){ - kfree(cop); - kfree(jc); - DEBUG_API(printk("cryptocop_ioctl_process: explicit_iv when not CBC mode\n")); - return -EINVAL; - } - } - if (oper.cipher_outlen != cipher_outlen) { - kfree(cop); - kfree(jc); - DEBUG_API(printk("cryptocop_ioctl_process: cipher_outlen incorrect, should be %d not %d.\n", cipher_outlen, oper.cipher_outlen)); - return -EINVAL; - } - - if (oper.decrypt){ - ciph_tcfg.flags |= CRYPTOCOP_DECRYPT; - } else { - ciph_tcfg.flags |= CRYPTOCOP_ENCRYPT; - } - ciph_tcfg.next = cop->tfrm_op.tfrm_cfg; - cop->tfrm_op.tfrm_cfg = &ciph_tcfg; - } - if (oper.do_digest){ - struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_DIGEST_TID); - if (!tc) { - DEBUG_API(printk("cryptocop_ioctl_process: no digest transform in session.\n")); - err = -EINVAL; - goto error_cleanup; - } - digest_length = tc->init.alg == cryptocop_alg_md5 ? 16 : 20; - digest_result = kmalloc(digest_length, GFP_KERNEL); - if (!digest_result) { - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc digest_result\n")); - err = -EINVAL; - goto error_cleanup; - } - DEBUG(memset(digest_result, 0xff, digest_length)); - - digest_tcfg.tid = CRYPTOCOP_IOCTL_DIGEST_TID; - digest_tcfg.inject_ix = 0; - ciph_tcfg.inject_ix += digest_length; - if ((oper.digest_start < 0) || (oper.digest_len <= 0) || (oper.digest_start > oper.inlen) || ((oper.digest_start + oper.digest_len) > oper.inlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: bad digest length\n")); - err = -EINVAL; - goto error_cleanup; - } - - digest_tcfg.next = cop->tfrm_op.tfrm_cfg; - cop->tfrm_op.tfrm_cfg = &digest_tcfg; - } - if (oper.do_csum){ - csum_tcfg.tid = CRYPTOCOP_IOCTL_CSUM_TID; - csum_tcfg.inject_ix = digest_length; - ciph_tcfg.inject_ix += 2; - - if ((oper.csum_start < 0) || (oper.csum_len <= 0) || (oper.csum_start > oper.inlen) || ((oper.csum_start + oper.csum_len) > oper.inlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: bad csum length\n")); - kfree(cop); - kfree(jc); - return -EINVAL; - } - - csum_tcfg.next = cop->tfrm_op.tfrm_cfg; - cop->tfrm_op.tfrm_cfg = &csum_tcfg; - } - - prev_ix = first_cfg_change_ix(&oper); - if (prev_ix > oper.inlen) { - DEBUG_API(printk("cryptocop_ioctl_process: length mismatch\n")); - nooutpages = noinpages = 0; - err = -EINVAL; - goto error_cleanup; - } - DEBUG(printk("cryptocop_ioctl_process: inlen=%d, cipher_outlen=%d\n", oper.inlen, oper.cipher_outlen)); - - /* Map user pages for in and out data of the operation. */ - noinpages = (((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK) + oper.inlen - 1 - prev_ix + ~PAGE_MASK) >> PAGE_SHIFT; - DEBUG(printk("cryptocop_ioctl_process: noinpages=%d\n", noinpages)); - inpages = kmalloc(noinpages * sizeof(struct page*), GFP_KERNEL); - if (!inpages){ - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc inpages\n")); - nooutpages = noinpages = 0; - err = -ENOMEM; - goto error_cleanup; - } - if (oper.do_cipher){ - nooutpages = (((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) + oper.cipher_outlen - 1 + ~PAGE_MASK) >> PAGE_SHIFT; - DEBUG(printk("cryptocop_ioctl_process: nooutpages=%d\n", nooutpages)); - outpages = kmalloc(nooutpages * sizeof(struct page*), GFP_KERNEL); - if (!outpages){ - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc outpages\n")); - nooutpages = noinpages = 0; - err = -ENOMEM; - goto error_cleanup; - } - } - - /* Acquire the mm page semaphore. */ - down_read(¤t->mm->mmap_sem); - - err = get_user_pages(current, - current->mm, - (unsigned long int)(oper.indata + prev_ix), - noinpages, - 0, /* read access only for in data */ - 0, /* no force */ - inpages, - NULL); - - if (err < 0) { - up_read(¤t->mm->mmap_sem); - nooutpages = noinpages = 0; - DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages indata\n")); - goto error_cleanup; - } - noinpages = err; - if (oper.do_cipher){ - err = get_user_pages(current, - current->mm, - (unsigned long int)oper.cipher_outdata, - nooutpages, - 1, /* write access for out data */ - 0, /* no force */ - outpages, - NULL); - up_read(¤t->mm->mmap_sem); - if (err < 0) { - nooutpages = 0; - DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages outdata\n")); - goto error_cleanup; - } - nooutpages = err; - } else { - up_read(¤t->mm->mmap_sem); - } - - /* Add 6 to nooutpages to make room for possibly inserted buffers for storing digest and - * csum output and splits when units are (dis-)connected. */ - cop->tfrm_op.indata = kmalloc((noinpages) * sizeof(struct iovec), GFP_KERNEL); - cop->tfrm_op.outdata = kmalloc((6 + nooutpages) * sizeof(struct iovec), GFP_KERNEL); - if (!cop->tfrm_op.indata || !cop->tfrm_op.outdata) { - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc iovecs\n")); - err = -ENOMEM; - goto error_cleanup; - } - - cop->tfrm_op.inlen = oper.inlen - prev_ix; - cop->tfrm_op.outlen = 0; - if (oper.do_cipher) cop->tfrm_op.outlen += oper.cipher_outlen; - if (oper.do_digest) cop->tfrm_op.outlen += digest_length; - if (oper.do_csum) cop->tfrm_op.outlen += 2; - - /* Setup the in iovecs. */ - cop->tfrm_op.incount = noinpages; - if (noinpages > 1){ - size_t tmplen = cop->tfrm_op.inlen; - - cop->tfrm_op.indata[0].iov_len = PAGE_SIZE - ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK); - cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK); - tmplen -= cop->tfrm_op.indata[0].iov_len; - for (i = 1; itfrm_op.indata[i].iov_len = tmplen < PAGE_SIZE ? tmplen : PAGE_SIZE; - cop->tfrm_op.indata[i].iov_base = (unsigned char*)page_address(inpages[i]); - tmplen -= PAGE_SIZE; - } - } else { - cop->tfrm_op.indata[0].iov_len = oper.inlen - prev_ix; - cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK); - } - - iovlen = nooutpages + 6; - pageoffset = oper.do_cipher ? ((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) : 0; - - next_ix = next_cfg_change_ix(&oper, prev_ix); - if (prev_ix == next_ix){ - DEBUG_API(printk("cryptocop_ioctl_process: length configuration broken.\n")); - err = -EINVAL; /* This should be impossible barring bugs. */ - goto error_cleanup; - } - while (prev_ix != next_ix){ - end_digest = end_csum = cipher_active = digest_active = csum_active = 0; - descs[desc_ix].cfg = NULL; - descs[desc_ix].length = next_ix - prev_ix; - - if (oper.do_cipher && (oper.cipher_start < next_ix) && (prev_ix < (oper.cipher_start + oper.cipher_len))) { - dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CIPHER_TID; - dcfgs[dcfg_ix].src = cryptocop_source_dma; - cipher_active = 1; - - if (next_ix == (oper.cipher_start + oper.cipher_len)){ - cipher_done = 1; - dcfgs[dcfg_ix].last = 1; - } else { - dcfgs[dcfg_ix].last = 0; - } - dcfgs[dcfg_ix].next = descs[desc_ix].cfg; - descs[desc_ix].cfg = &dcfgs[dcfg_ix]; - ++dcfg_ix; - } - if (oper.do_digest && (oper.digest_start < next_ix) && (prev_ix < (oper.digest_start + oper.digest_len))) { - digest_active = 1; - dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_DIGEST_TID; - dcfgs[dcfg_ix].src = cryptocop_source_dma; - if (next_ix == (oper.digest_start + oper.digest_len)){ - assert(!digest_done); - digest_done = 1; - dcfgs[dcfg_ix].last = 1; - } else { - dcfgs[dcfg_ix].last = 0; - } - dcfgs[dcfg_ix].next = descs[desc_ix].cfg; - descs[desc_ix].cfg = &dcfgs[dcfg_ix]; - ++dcfg_ix; - } - if (oper.do_csum && (oper.csum_start < next_ix) && (prev_ix < (oper.csum_start + oper.csum_len))){ - csum_active = 1; - dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CSUM_TID; - dcfgs[dcfg_ix].src = cryptocop_source_dma; - if (next_ix == (oper.csum_start + oper.csum_len)){ - csum_done = 1; - dcfgs[dcfg_ix].last = 1; - } else { - dcfgs[dcfg_ix].last = 0; - } - dcfgs[dcfg_ix].next = descs[desc_ix].cfg; - descs[desc_ix].cfg = &dcfgs[dcfg_ix]; - ++dcfg_ix; - } - if (!descs[desc_ix].cfg){ - DEBUG_API(printk("cryptocop_ioctl_process: data segment %d (%d to %d) had no active transforms\n", desc_ix, prev_ix, next_ix)); - err = -EINVAL; - goto error_cleanup; - } - descs[desc_ix].next = &(descs[desc_ix]) + 1; - ++desc_ix; - prev_ix = next_ix; - next_ix = next_cfg_change_ix(&oper, prev_ix); - } - if (desc_ix > 0){ - descs[desc_ix-1].next = NULL; - } else { - descs[0].next = NULL; - } - if (oper.do_digest) { - DEBUG(printk("cryptocop_ioctl_process: mapping %d byte digest output to iovec %d\n", digest_length, iovix)); - /* Add outdata iovec, length == */ - cop->tfrm_op.outdata[iovix].iov_base = digest_result; - cop->tfrm_op.outdata[iovix].iov_len = digest_length; - ++iovix; - } - if (oper.do_csum) { - /* Add outdata iovec, length == 2, the length of csum. */ - DEBUG(printk("cryptocop_ioctl_process: mapping 2 byte csum output to iovec %d\n", iovix)); - /* Add outdata iovec, length == */ - cop->tfrm_op.outdata[iovix].iov_base = csum_result; - cop->tfrm_op.outdata[iovix].iov_len = 2; - ++iovix; - } - if (oper.do_cipher) { - if (!map_pages_to_iovec(cop->tfrm_op.outdata, iovlen, &iovix, outpages, nooutpages, &pageix, &pageoffset, oper.cipher_outlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: failed to map pages to iovec.\n")); - err = -ENOSYS; /* This should be impossible barring bugs. */ - goto error_cleanup; - } - } - DEBUG(printk("cryptocop_ioctl_process: setting cop->tfrm_op.outcount %d\n", iovix)); - cop->tfrm_op.outcount = iovix; - assert(iovix <= (nooutpages + 6)); - - cop->sid = oper.ses_id; - cop->tfrm_op.desc = &descs[0]; - - DEBUG(printk("cryptocop_ioctl_process: inserting job, cb_data=0x%p\n", cop->cb_data)); - - if ((err = cryptocop_job_queue_insert_user_job(cop)) != 0) { - DEBUG_API(printk("cryptocop_ioctl_process: insert job %d\n", err)); - err = -EINVAL; - goto error_cleanup; - } - - DEBUG(printk("cryptocop_ioctl_process: begin wait for result\n")); - - wait_event(cryptocop_ioc_process_wq, (jc->processed != 0)); - DEBUG(printk("cryptocop_ioctl_process: end wait for result\n")); - if (!jc->processed){ - printk(KERN_WARNING "cryptocop_ioctl_process: job not processed at completion\n"); - err = -EIO; - goto error_cleanup; - } - - /* Job process done. Cipher output should already be correct in job so no post processing of outdata. */ - DEBUG(printk("cryptocop_ioctl_process: operation_status = %d\n", cop->operation_status)); - if (cop->operation_status == 0){ - if (oper.do_digest){ - DEBUG(printk("cryptocop_ioctl_process: copy %d bytes digest to user\n", digest_length)); - err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, digest), digest_result, digest_length); - if (0 != err){ - DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, digest length %d, err %d\n", digest_length, err)); - err = -EFAULT; - goto error_cleanup; - } - } - if (oper.do_csum){ - DEBUG(printk("cryptocop_ioctl_process: copy 2 bytes checksum to user\n")); - err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, csum), csum_result, 2); - if (0 != err){ - DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, csum, err %d\n", err)); - err = -EFAULT; - goto error_cleanup; - } - } - err = 0; - } else { - DEBUG(printk("cryptocop_ioctl_process: returning err = operation_status = %d\n", cop->operation_status)); - err = cop->operation_status; - } - - error_cleanup: - /* Release page caches. */ - for (i = 0; i < noinpages; i++){ - put_page(inpages[i]); - } - for (i = 0; i < nooutpages; i++){ - int spdl_err; - /* Mark output pages dirty. */ - spdl_err = set_page_dirty_lock(outpages[i]); - DEBUG(if (spdl_err)printk("cryptocop_ioctl_process: set_page_dirty_lock returned %d\n", spdl_err)); - } - for (i = 0; i < nooutpages; i++){ - put_page(outpages[i]); - } - - if (digest_result) kfree(digest_result); - if (inpages) kfree(inpages); - if (outpages) kfree(outpages); - if (cop){ - if (cop->tfrm_op.indata) kfree(cop->tfrm_op.indata); - if (cop->tfrm_op.outdata) kfree(cop->tfrm_op.outdata); - kfree(cop); - } - if (jc) kfree(jc); - - DEBUG(print_lock_status()); - - return err; -} - - -static int cryptocop_ioctl_create_session(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) -{ - cryptocop_session_id sid; - int err; - struct cryptocop_private *dev; - struct strcop_session_op *sess_op = (struct strcop_session_op *)arg; - struct strcop_session_op sop; - struct cryptocop_transform_init *tis = NULL; - struct cryptocop_transform_init ti_cipher = {0}; - struct cryptocop_transform_init ti_digest = {0}; - struct cryptocop_transform_init ti_csum = {0}; - - if (!access_ok(VERIFY_WRITE, sess_op, sizeof(struct strcop_session_op))) - return -EFAULT; - err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op)); - if (err) return -EFAULT; - if (sop.cipher != cryptocop_cipher_none) { - if (!access_ok(VERIFY_READ, sop.key, sop.keylen)) return -EFAULT; - } - DEBUG(printk("cryptocop_ioctl_create_session, sess_op:\n")); - - DEBUG(printk("\tcipher:%d\n" - "\tcipher_mode:%d\n" - "\tdigest:%d\n" - "\tcsum:%d\n", - (int)sop.cipher, - (int)sop.cmode, - (int)sop.digest, - (int)sop.csum)); - - if (sop.cipher != cryptocop_cipher_none){ - /* Init the cipher. */ - switch (sop.cipher){ - case cryptocop_cipher_des: - ti_cipher.alg = cryptocop_alg_des; - break; - case cryptocop_cipher_3des: - ti_cipher.alg = cryptocop_alg_3des; - break; - case cryptocop_cipher_aes: - ti_cipher.alg = cryptocop_alg_aes; - break; - default: - DEBUG_API(printk("create session, bad cipher algorithm %d\n", sop.cipher)); - return -EINVAL; - }; - DEBUG(printk("setting cipher transform %d\n", ti_cipher.alg)); - copy_from_user(ti_cipher.key, sop.key, sop.keylen/8); - ti_cipher.keylen = sop.keylen; - switch (sop.cmode){ - case cryptocop_cipher_mode_cbc: - case cryptocop_cipher_mode_ecb: - ti_cipher.cipher_mode = sop.cmode; - break; - default: - DEBUG_API(printk("create session, bad cipher mode %d\n", sop.cmode)); - return -EINVAL; - } - DEBUG(printk("cryptocop_ioctl_create_session: setting CBC mode %d\n", ti_cipher.cipher_mode)); - switch (sop.des3_mode){ - case cryptocop_3des_eee: - case cryptocop_3des_eed: - case cryptocop_3des_ede: - case cryptocop_3des_edd: - case cryptocop_3des_dee: - case cryptocop_3des_ded: - case cryptocop_3des_dde: - case cryptocop_3des_ddd: - ti_cipher.tdes_mode = sop.des3_mode; - break; - default: - DEBUG_API(printk("create session, bad 3DES mode %d\n", sop.des3_mode)); - return -EINVAL; - } - ti_cipher.tid = CRYPTOCOP_IOCTL_CIPHER_TID; - ti_cipher.next = tis; - tis = &ti_cipher; - } /* if (sop.cipher != cryptocop_cipher_none) */ - if (sop.digest != cryptocop_digest_none){ - DEBUG(printk("setting digest transform\n")); - switch (sop.digest){ - case cryptocop_digest_md5: - ti_digest.alg = cryptocop_alg_md5; - break; - case cryptocop_digest_sha1: - ti_digest.alg = cryptocop_alg_sha1; - break; - default: - DEBUG_API(printk("create session, bad digest algorithm %d\n", sop.digest)); - return -EINVAL; - } - ti_digest.tid = CRYPTOCOP_IOCTL_DIGEST_TID; - ti_digest.next = tis; - tis = &ti_digest; - } /* if (sop.digest != cryptocop_digest_none) */ - if (sop.csum != cryptocop_csum_none){ - DEBUG(printk("setting csum transform\n")); - switch (sop.csum){ - case cryptocop_csum_le: - case cryptocop_csum_be: - ti_csum.csum_mode = sop.csum; - break; - default: - DEBUG_API(printk("create session, bad checksum algorithm %d\n", sop.csum)); - return -EINVAL; - } - ti_csum.alg = cryptocop_alg_csum; - ti_csum.tid = CRYPTOCOP_IOCTL_CSUM_TID; - ti_csum.next = tis; - tis = &ti_csum; - } /* (sop.csum != cryptocop_csum_none) */ - dev = kmalloc(sizeof(struct cryptocop_private), GFP_KERNEL); - if (!dev){ - DEBUG_API(printk("create session, alloc dev\n")); - return -ENOMEM; - } - - err = cryptocop_new_session(&sid, tis, GFP_KERNEL); - DEBUG({ if (err) printk("create session, cryptocop_new_session %d\n", err);}); - - if (err) { - kfree(dev); - return err; - } - sess_op->ses_id = sid; - dev->sid = sid; - dev->next = filp->private_data; - filp->private_data = dev; - - return 0; -} - -static int cryptocop_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) -{ - int err = 0; - if (_IOC_TYPE(cmd) != ETRAXCRYPTOCOP_IOCTYPE) { - DEBUG_API(printk("cryptocop_ioctl: wrong type\n")); - return -ENOTTY; - } - if (_IOC_NR(cmd) > CRYPTOCOP_IO_MAXNR){ - return -ENOTTY; - } - /* Access check of the argument. Some commands, e.g. create session and process op, - needs additional checks. Those are handled in the command handling functions. */ - if (_IOC_DIR(cmd) & _IOC_READ) - err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd)); - else if (_IOC_DIR(cmd) & _IOC_WRITE) - err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd)); - if (err) return -EFAULT; - - switch (cmd) { - case CRYPTOCOP_IO_CREATE_SESSION: - return cryptocop_ioctl_create_session(inode, filp, cmd, arg); - case CRYPTOCOP_IO_CLOSE_SESSION: - return cryptocop_ioctl_close_session(inode, filp, cmd, arg); - case CRYPTOCOP_IO_PROCESS_OP: - return cryptocop_ioctl_process(inode, filp, cmd, arg); - default: - DEBUG_API(printk("cryptocop_ioctl: unknown command\n")); - return -ENOTTY; - } - return 0; -} - - -#ifdef LDEBUG -static void print_dma_descriptors(struct cryptocop_int_operation *iop) -{ - struct cryptocop_dma_desc *cdesc_out = iop->cdesc_out; - struct cryptocop_dma_desc *cdesc_in = iop->cdesc_in; - int i; - - printk("print_dma_descriptors start\n"); - - printk("iop:\n"); - printk("\tsid: 0x%lld\n", iop->sid); - - printk("\tcdesc_out: 0x%p\n", iop->cdesc_out); - printk("\tcdesc_in: 0x%p\n", iop->cdesc_in); - printk("\tddesc_out: 0x%p\n", iop->ddesc_out); - printk("\tddesc_in: 0x%p\n", iop->ddesc_in); - - printk("\niop->ctx_out: 0x%p phys: 0x%p\n", &iop->ctx_out, (char*)virt_to_phys(&iop->ctx_out)); - printk("\tnext: 0x%p\n" - "\tsaved_data: 0x%p\n" - "\tsaved_data_buf: 0x%p\n", - iop->ctx_out.next, - iop->ctx_out.saved_data, - iop->ctx_out.saved_data_buf); - - printk("\niop->ctx_in: 0x%p phys: 0x%p\n", &iop->ctx_in, (char*)virt_to_phys(&iop->ctx_in)); - printk("\tnext: 0x%p\n" - "\tsaved_data: 0x%p\n" - "\tsaved_data_buf: 0x%p\n", - iop->ctx_in.next, - iop->ctx_in.saved_data, - iop->ctx_in.saved_data_buf); - - i = 0; - while (cdesc_out) { - dma_descr_data *td; - printk("cdesc_out %d, desc=0x%p\n", i, cdesc_out->dma_descr); - printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_out->dma_descr)); - td = cdesc_out->dma_descr; - printk("\n\tbuf: 0x%p\n" - "\tafter: 0x%p\n" - "\tmd: 0x%04x\n" - "\tnext: 0x%p\n", - td->buf, - td->after, - td->md, - td->next); - printk("flags:\n" - "\twait:\t%d\n" - "\teol:\t%d\n" - "\touteop:\t%d\n" - "\tineop:\t%d\n" - "\tintr:\t%d\n", - td->wait, - td->eol, - td->out_eop, - td->in_eop, - td->intr); - cdesc_out = cdesc_out->next; - i++; - } - i = 0; - while (cdesc_in) { - dma_descr_data *td; - printk("cdesc_in %d, desc=0x%p\n", i, cdesc_in->dma_descr); - printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_in->dma_descr)); - td = cdesc_in->dma_descr; - printk("\n\tbuf: 0x%p\n" - "\tafter: 0x%p\n" - "\tmd: 0x%04x\n" - "\tnext: 0x%p\n", - td->buf, - td->after, - td->md, - td->next); - printk("flags:\n" - "\twait:\t%d\n" - "\teol:\t%d\n" - "\touteop:\t%d\n" - "\tineop:\t%d\n" - "\tintr:\t%d\n", - td->wait, - td->eol, - td->out_eop, - td->in_eop, - td->intr); - cdesc_in = cdesc_in->next; - i++; - } - - printk("print_dma_descriptors end\n"); -} - - -static void print_strcop_crypto_op(struct strcop_crypto_op *cop) -{ - printk("print_strcop_crypto_op, 0x%p\n", cop); - - /* Indata. */ - printk("indata=0x%p\n" - "inlen=%d\n" - "do_cipher=%d\n" - "decrypt=%d\n" - "cipher_explicit=%d\n" - "cipher_start=%d\n" - "cipher_len=%d\n" - "outdata=0x%p\n" - "outlen=%d\n", - cop->indata, - cop->inlen, - cop->do_cipher, - cop->decrypt, - cop->cipher_explicit, - cop->cipher_start, - cop->cipher_len, - cop->cipher_outdata, - cop->cipher_outlen); - - printk("do_digest=%d\n" - "digest_start=%d\n" - "digest_len=%d\n", - cop->do_digest, - cop->digest_start, - cop->digest_len); - - printk("do_csum=%d\n" - "csum_start=%d\n" - "csum_len=%d\n", - cop->do_csum, - cop->csum_start, - cop->csum_len); -} - -static void print_cryptocop_operation(struct cryptocop_operation *cop) -{ - struct cryptocop_desc *d; - struct cryptocop_tfrm_cfg *tc; - struct cryptocop_desc_cfg *dc; - int i; - - printk("print_cryptocop_operation, cop=0x%p\n\n", cop); - printk("sid: %lld\n", cop->sid); - printk("operation_status=%d\n" - "use_dmalists=%d\n" - "in_interrupt=%d\n" - "fast_callback=%d\n", - cop->operation_status, - cop->use_dmalists, - cop->in_interrupt, - cop->fast_callback); - - if (cop->use_dmalists){ - print_user_dma_lists(&cop->list_op); - } else { - printk("cop->tfrm_op\n" - "tfrm_cfg=0x%p\n" - "desc=0x%p\n" - "indata=0x%p\n" - "incount=%d\n" - "inlen=%d\n" - "outdata=0x%p\n" - "outcount=%d\n" - "outlen=%d\n\n", - cop->tfrm_op.tfrm_cfg, - cop->tfrm_op.desc, - cop->tfrm_op.indata, - cop->tfrm_op.incount, - cop->tfrm_op.inlen, - cop->tfrm_op.outdata, - cop->tfrm_op.outcount, - cop->tfrm_op.outlen); - - tc = cop->tfrm_op.tfrm_cfg; - while (tc){ - printk("tfrm_cfg, 0x%p\n" - "tid=%d\n" - "flags=%d\n" - "inject_ix=%d\n" - "next=0x%p\n", - tc, - tc->tid, - tc->flags, - tc->inject_ix, - tc->next); - tc = tc->next; - } - d = cop->tfrm_op.desc; - while (d){ - printk("\n======================desc, 0x%p\n" - "length=%d\n" - "cfg=0x%p\n" - "next=0x%p\n", - d, - d->length, - d->cfg, - d->next); - dc = d->cfg; - while (dc){ - printk("=========desc_cfg, 0x%p\n" - "tid=%d\n" - "src=%d\n" - "last=%d\n" - "next=0x%p\n", - dc, - dc->tid, - dc->src, - dc->last, - dc->next); - dc = dc->next; - } - d = d->next; - } - printk("\n====iniov\n"); - for (i = 0; i < cop->tfrm_op.incount; i++){ - printk("indata[%d]\n" - "base=0x%p\n" - "len=%d\n", - i, - cop->tfrm_op.indata[i].iov_base, - cop->tfrm_op.indata[i].iov_len); - } - printk("\n====outiov\n"); - for (i = 0; i < cop->tfrm_op.outcount; i++){ - printk("outdata[%d]\n" - "base=0x%p\n" - "len=%d\n", - i, - cop->tfrm_op.outdata[i].iov_base, - cop->tfrm_op.outdata[i].iov_len); - } - } - printk("------------end print_cryptocop_operation\n"); -} - - -static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op) -{ - dma_descr_data *dd; - int i; - - printk("print_user_dma_lists, dma_op=0x%p\n", dma_op); - - printk("out_data_buf = 0x%p, phys_to_virt(out_data_buf) = 0x%p\n", dma_op->out_data_buf, phys_to_virt((unsigned long int)dma_op->out_data_buf)); - printk("in_data_buf = 0x%p, phys_to_virt(in_data_buf) = 0x%p\n", dma_op->in_data_buf, phys_to_virt((unsigned long int)dma_op->in_data_buf)); - - printk("##############outlist\n"); - dd = phys_to_virt((unsigned long int)dma_op->outlist); - i = 0; - while (dd != NULL) { - printk("#%d phys_to_virt(desc) 0x%p\n", i, dd); - printk("\n\tbuf: 0x%p\n" - "\tafter: 0x%p\n" - "\tmd: 0x%04x\n" - "\tnext: 0x%p\n", - dd->buf, - dd->after, - dd->md, - dd->next); - printk("flags:\n" - "\twait:\t%d\n" - "\teol:\t%d\n" - "\touteop:\t%d\n" - "\tineop:\t%d\n" - "\tintr:\t%d\n", - dd->wait, - dd->eol, - dd->out_eop, - dd->in_eop, - dd->intr); - if (dd->eol) - dd = NULL; - else - dd = phys_to_virt((unsigned long int)dd->next); - ++i; - } - - printk("##############inlist\n"); - dd = phys_to_virt((unsigned long int)dma_op->inlist); - i = 0; - while (dd != NULL) { - printk("#%d phys_to_virt(desc) 0x%p\n", i, dd); - printk("\n\tbuf: 0x%p\n" - "\tafter: 0x%p\n" - "\tmd: 0x%04x\n" - "\tnext: 0x%p\n", - dd->buf, - dd->after, - dd->md, - dd->next); - printk("flags:\n" - "\twait:\t%d\n" - "\teol:\t%d\n" - "\touteop:\t%d\n" - "\tineop:\t%d\n" - "\tintr:\t%d\n", - dd->wait, - dd->eol, - dd->out_eop, - dd->in_eop, - dd->intr); - if (dd->eol) - dd = NULL; - else - dd = phys_to_virt((unsigned long int)dd->next); - ++i; - } -} - - -static void print_lock_status(void) -{ - printk("**********************print_lock_status\n"); - printk("cryptocop_completed_jobs_lock %d\n", spin_is_locked(&cryptocop_completed_jobs_lock)); - printk("cryptocop_job_queue_lock %d\n", spin_is_locked(&cryptocop_job_queue_lock)); - printk("descr_pool_lock %d\n", spin_is_locked(&descr_pool_lock)); - printk("cryptocop_sessions_lock %d\n", spin_is_locked(cryptocop_sessions_lock)); - printk("running_job_lock %d\n", spin_is_locked(running_job_lock)); - printk("cryptocop_process_lock %d\n", spin_is_locked(cryptocop_process_lock)); -} -#endif /* LDEBUG */ - - -static const char cryptocop_name[] = "ETRAX FS stream co-processor"; - -static int init_stream_coprocessor(void) -{ - int err; - int i; - static int initialized = 0; - - if (initialized) - return 0; - - initialized = 1; - - printk("ETRAX FS stream co-processor driver v0.01, (c) 2003 Axis Communications AB\n"); - - err = register_chrdev(CRYPTOCOP_MAJOR, cryptocop_name, &cryptocop_fops); - if (err < 0) { - printk(KERN_ERR "stream co-processor: could not get major number.\n"); - return err; - } - - err = init_cryptocop(); - if (err) { - (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name); - return err; - } - err = cryptocop_job_queue_init(); - if (err) { - release_cryptocop(); - (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name); - return err; - } - /* Init the descriptor pool. */ - for (i = 0; i < CRYPTOCOP_DESCRIPTOR_POOL_SIZE - 1; i++) { - descr_pool[i].from_pool = 1; - descr_pool[i].next = &descr_pool[i + 1]; - } - descr_pool[i].from_pool = 1; - descr_pool[i].next = NULL; - descr_pool_free_list = &descr_pool[0]; - descr_pool_no_free = CRYPTOCOP_DESCRIPTOR_POOL_SIZE; - - spin_lock_init(&cryptocop_completed_jobs_lock); - spin_lock_init(&cryptocop_job_queue_lock); - spin_lock_init(&descr_pool_lock); - spin_lock_init(&cryptocop_sessions_lock); - spin_lock_init(&running_job_lock); - spin_lock_init(&cryptocop_process_lock); - - cryptocop_sessions = NULL; - next_sid = 1; - - cryptocop_running_job = NULL; - - printk("stream co-processor: init done.\n"); - return 0; -} - -static void __exit exit_stream_coprocessor(void) -{ - release_cryptocop(); - cryptocop_job_queue_close(); -} - -module_init(init_stream_coprocessor); -module_exit(exit_stream_coprocessor); - diff --git a/trunk/arch/cris/arch-v32/drivers/gpio.c b/trunk/arch/cris/arch-v32/drivers/gpio.c deleted file mode 100644 index a551237dcb5e..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/gpio.c +++ /dev/null @@ -1,766 +0,0 @@ -/* $Id: gpio.c,v 1.16 2005/06/19 17:06:49 starvik Exp $ - * - * ETRAX CRISv32 general port I/O device - * - * Copyright (c) 1999, 2000, 2001, 2002, 2003 Axis Communications AB - * - * Authors: Bjorn Wesen (initial version) - * Ola Knutsson (LED handling) - * Johan Adolfsson (read/set directions, write, port G, - * port to ETRAX FS. - * - * $Log: gpio.c,v $ - * Revision 1.16 2005/06/19 17:06:49 starvik - * Merge of Linux 2.6.12. - * - * Revision 1.15 2005/05/25 08:22:20 starvik - * Changed GPIO port order to fit packages/devices/axis-2.4. - * - * Revision 1.14 2005/04/24 18:35:08 starvik - * Updated with final register headers. - * - * Revision 1.13 2005/03/15 15:43:00 starvik - * dev_id needs to be supplied for shared IRQs. - * - * Revision 1.12 2005/03/10 17:12:00 starvik - * Protect alarm list with spinlock. - * - * Revision 1.11 2005/01/05 06:08:59 starvik - * No need to do local_irq_disable after local_irq_save. - * - * Revision 1.10 2004/11/19 08:38:31 starvik - * Removed old crap. - * - * Revision 1.9 2004/05/14 07:58:02 starvik - * Merge of changes from 2.4 - * - * Revision 1.8 2003/09/11 07:29:50 starvik - * Merge of Linux 2.6.0-test5 - * - * Revision 1.7 2003/07/10 13:25:46 starvik - * Compiles for 2.5.74 - * Lindented ethernet.c - * - * Revision 1.6 2003/07/04 08:27:46 starvik - * Merge of Linux 2.5.74 - * - * Revision 1.5 2003/06/10 08:26:37 johana - * Etrax -> ETRAX CRISv32 - * - * Revision 1.4 2003/06/05 14:22:48 johana - * Initialise some_alarms. - * - * Revision 1.3 2003/06/05 10:15:46 johana - * New INTR_VECT macros. - * Enable interrupts in global config. - * - * Revision 1.2 2003/06/03 15:52:50 johana - * Initial CRIS v32 version. - * - * Revision 1.1 2003/06/03 08:53:15 johana - * Copy of os/lx25/arch/cris/arch-v10/drivers/gpio.c version 1.7. - * - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -/* The following gio ports on ETRAX FS is available: - * pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge - * pb 18 bits - * pc 18 bits - * pd 18 bits - * pe 18 bits - * each port has a rw_px_dout, r_px_din and rw_px_oe register. - */ - -#define GPIO_MAJOR 120 /* experimental MAJOR number */ - -#define D(x) - -#if 0 -static int dp_cnt; -#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0) -#else -#define DP(x) -#endif - -static char gpio_name[] = "etrax gpio"; - -#if 0 -static wait_queue_head_t *gpio_wq; -#endif - -static int gpio_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg); -static ssize_t gpio_write(struct file * file, const char * buf, size_t count, - loff_t *off); -static int gpio_open(struct inode *inode, struct file *filp); -static int gpio_release(struct inode *inode, struct file *filp); -static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait); - -/* private data per open() of this driver */ - -struct gpio_private { - struct gpio_private *next; - /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */ - unsigned char clk_mask; - unsigned char data_mask; - unsigned char write_msb; - unsigned char pad1; - /* These fields are generic */ - unsigned long highalarm, lowalarm; - wait_queue_head_t alarm_wq; - int minor; -}; - -/* linked list of alarms to check for */ - -static struct gpio_private *alarmlist = 0; - -static int gpio_some_alarms = 0; /* Set if someone uses alarm */ -static unsigned long gpio_pa_high_alarms = 0; -static unsigned long gpio_pa_low_alarms = 0; - -static DEFINE_SPINLOCK(alarm_lock); - -#define NUM_PORTS (GPIO_MINOR_LAST+1) -#define GIO_REG_RD_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg ) -#define GIO_REG_WR_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg ) -unsigned long led_dummy; - -static volatile unsigned long *data_out[NUM_PORTS] = { - GIO_REG_WR_ADDR(rw_pa_dout), - GIO_REG_WR_ADDR(rw_pb_dout), - &led_dummy, - GIO_REG_WR_ADDR(rw_pc_dout), - GIO_REG_WR_ADDR(rw_pd_dout), - GIO_REG_WR_ADDR(rw_pe_dout), -}; - -static volatile unsigned long *data_in[NUM_PORTS] = { - GIO_REG_RD_ADDR(r_pa_din), - GIO_REG_RD_ADDR(r_pb_din), - &led_dummy, - GIO_REG_RD_ADDR(r_pc_din), - GIO_REG_RD_ADDR(r_pd_din), - GIO_REG_RD_ADDR(r_pe_din), -}; - -static unsigned long changeable_dir[NUM_PORTS] = { - CONFIG_ETRAX_PA_CHANGEABLE_DIR, - CONFIG_ETRAX_PB_CHANGEABLE_DIR, - 0, - CONFIG_ETRAX_PC_CHANGEABLE_DIR, - CONFIG_ETRAX_PD_CHANGEABLE_DIR, - CONFIG_ETRAX_PE_CHANGEABLE_DIR, -}; - -static unsigned long changeable_bits[NUM_PORTS] = { - CONFIG_ETRAX_PA_CHANGEABLE_BITS, - CONFIG_ETRAX_PB_CHANGEABLE_BITS, - 0, - CONFIG_ETRAX_PC_CHANGEABLE_BITS, - CONFIG_ETRAX_PD_CHANGEABLE_BITS, - CONFIG_ETRAX_PE_CHANGEABLE_BITS, -}; - -static volatile unsigned long *dir_oe[NUM_PORTS] = { - GIO_REG_WR_ADDR(rw_pa_oe), - GIO_REG_WR_ADDR(rw_pb_oe), - &led_dummy, - GIO_REG_WR_ADDR(rw_pc_oe), - GIO_REG_WR_ADDR(rw_pd_oe), - GIO_REG_WR_ADDR(rw_pe_oe), -}; - - - -static unsigned int -gpio_poll(struct file *file, - poll_table *wait) -{ - unsigned int mask = 0; - struct gpio_private *priv = (struct gpio_private *)file->private_data; - unsigned long data; - poll_wait(file, &priv->alarm_wq, wait); - if (priv->minor == GPIO_MINOR_A) { - reg_gio_rw_intr_cfg intr_cfg; - unsigned long tmp; - unsigned long flags; - - local_irq_save(flags); - data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din, REG_RD(gio, regi_gio, r_pa_din)); - /* PA has support for interrupt - * lets activate high for those low and with highalarm set - */ - intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg); - - tmp = ~data & priv->highalarm & 0xFF; - if (tmp & (1 << 0)) { - intr_cfg.pa0 = regk_gio_hi; - } - if (tmp & (1 << 1)) { - intr_cfg.pa1 = regk_gio_hi; - } - if (tmp & (1 << 2)) { - intr_cfg.pa2 = regk_gio_hi; - } - if (tmp & (1 << 3)) { - intr_cfg.pa3 = regk_gio_hi; - } - if (tmp & (1 << 4)) { - intr_cfg.pa4 = regk_gio_hi; - } - if (tmp & (1 << 5)) { - intr_cfg.pa5 = regk_gio_hi; - } - if (tmp & (1 << 6)) { - intr_cfg.pa6 = regk_gio_hi; - } - if (tmp & (1 << 7)) { - intr_cfg.pa7 = regk_gio_hi; - } - /* - * lets activate low for those high and with lowalarm set - */ - tmp = data & priv->lowalarm & 0xFF; - if (tmp & (1 << 0)) { - intr_cfg.pa0 = regk_gio_lo; - } - if (tmp & (1 << 1)) { - intr_cfg.pa1 = regk_gio_lo; - } - if (tmp & (1 << 2)) { - intr_cfg.pa2 = regk_gio_lo; - } - if (tmp & (1 << 3)) { - intr_cfg.pa3 = regk_gio_lo; - } - if (tmp & (1 << 4)) { - intr_cfg.pa4 = regk_gio_lo; - } - if (tmp & (1 << 5)) { - intr_cfg.pa5 = regk_gio_lo; - } - if (tmp & (1 << 6)) { - intr_cfg.pa6 = regk_gio_lo; - } - if (tmp & (1 << 7)) { - intr_cfg.pa7 = regk_gio_lo; - } - - REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg); - local_irq_restore(flags); - } else if (priv->minor <= GPIO_MINOR_E) - data = *data_in[priv->minor]; - else - return 0; - - if ((data & priv->highalarm) || - (~data & priv->lowalarm)) { - mask = POLLIN|POLLRDNORM; - } - - DP(printk("gpio_poll ready: mask 0x%08X\n", mask)); - return mask; -} - -int etrax_gpio_wake_up_check(void) -{ - struct gpio_private *priv = alarmlist; - unsigned long data = 0; - int ret = 0; - while (priv) { - data = *data_in[priv->minor]; - if ((data & priv->highalarm) || - (~data & priv->lowalarm)) { - DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor)); - wake_up_interruptible(&priv->alarm_wq); - ret = 1; - } - priv = priv->next; - } - return ret; -} - -static irqreturn_t -gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - if (gpio_some_alarms) { - return IRQ_RETVAL(etrax_gpio_wake_up_check()); - } - return IRQ_NONE; -} - -static irqreturn_t -gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - reg_gio_rw_intr_mask intr_mask; - reg_gio_r_masked_intr masked_intr; - reg_gio_rw_ack_intr ack_intr; - unsigned long tmp; - unsigned long tmp2; - - /* Find what PA interrupts are active */ - masked_intr = REG_RD(gio, regi_gio, r_masked_intr); - tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr); - - /* Find those that we have enabled */ - spin_lock(&alarm_lock); - tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms); - spin_unlock(&alarm_lock); - - /* Ack them */ - ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp); - REG_WR(gio, regi_gio, rw_ack_intr, ack_intr); - - /* Disable those interrupts.. */ - intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); - tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask); - tmp2 &= ~tmp; - intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2); - REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); - - if (gpio_some_alarms) { - return IRQ_RETVAL(etrax_gpio_wake_up_check()); - } - return IRQ_NONE; -} - - -static ssize_t gpio_write(struct file * file, const char * buf, size_t count, - loff_t *off) -{ - struct gpio_private *priv = (struct gpio_private *)file->private_data; - unsigned char data, clk_mask, data_mask, write_msb; - unsigned long flags; - unsigned long shadow; - volatile unsigned long *port; - ssize_t retval = count; - /* Only bits 0-7 may be used for write operations but allow all - devices except leds... */ - if (priv->minor == GPIO_MINOR_LEDS) { - return -EFAULT; - } - - if (!access_ok(VERIFY_READ, buf, count)) { - return -EFAULT; - } - clk_mask = priv->clk_mask; - data_mask = priv->data_mask; - /* It must have been configured using the IO_CFG_WRITE_MODE */ - /* Perhaps a better error code? */ - if (clk_mask == 0 || data_mask == 0) { - return -EPERM; - } - write_msb = priv->write_msb; - D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb)); - port = data_out[priv->minor]; - - while (count--) { - int i; - data = *buf++; - if (priv->write_msb) { - for (i = 7; i >= 0;i--) { - local_irq_save(flags); - shadow = *port; - *port = shadow &= ~clk_mask; - if (data & 1<i_rdev); - - if (p > GPIO_MINOR_LAST) - return -EINVAL; - - priv = (struct gpio_private *)kmalloc(sizeof(struct gpio_private), - GFP_KERNEL); - - if (!priv) - return -ENOMEM; - - priv->minor = p; - - /* initialize the io/alarm struct and link it into our alarmlist */ - - priv->next = alarmlist; - alarmlist = priv; - priv->clk_mask = 0; - priv->data_mask = 0; - priv->highalarm = 0; - priv->lowalarm = 0; - init_waitqueue_head(&priv->alarm_wq); - - filp->private_data = (void *)priv; - - return 0; -} - -static int -gpio_release(struct inode *inode, struct file *filp) -{ - struct gpio_private *p = alarmlist; - struct gpio_private *todel = (struct gpio_private *)filp->private_data; - /* local copies while updating them: */ - unsigned long a_high, a_low; - unsigned long some_alarms; - - /* unlink from alarmlist and free the private structure */ - - if (p == todel) { - alarmlist = todel->next; - } else { - while (p->next != todel) - p = p->next; - p->next = todel->next; - } - - kfree(todel); - /* Check if there are still any alarms set */ - p = alarmlist; - some_alarms = 0; - a_high = 0; - a_low = 0; - while (p) { - if (p->minor == GPIO_MINOR_A) { - a_high |= p->highalarm; - a_low |= p->lowalarm; - } - - if (p->highalarm | p->lowalarm) { - some_alarms = 1; - } - p = p->next; - } - - spin_lock(&alarm_lock); - gpio_some_alarms = some_alarms; - gpio_pa_high_alarms = a_high; - gpio_pa_low_alarms = a_low; - spin_unlock(&alarm_lock); - - return 0; -} - -/* Main device API. ioctl's to read/set/clear bits, as well as to - * set alarms to wait for using a subsequent select(). - */ - -unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg) -{ - /* Set direction 0=unchanged 1=input, - * return mask with 1=input - */ - unsigned long flags; - unsigned long dir_shadow; - - local_irq_save(flags); - dir_shadow = *dir_oe[priv->minor]; - dir_shadow &= ~(arg & changeable_dir[priv->minor]); - *dir_oe[priv->minor] = dir_shadow; - local_irq_restore(flags); - - if (priv->minor == GPIO_MINOR_A) - dir_shadow ^= 0xFF; /* Only 8 bits */ - else - dir_shadow ^= 0x3FFFF; /* Only 18 bits */ - return dir_shadow; - -} /* setget_input */ - -unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg) -{ - unsigned long flags; - unsigned long dir_shadow; - - local_irq_save(flags); - dir_shadow = *dir_oe[priv->minor]; - dir_shadow |= (arg & changeable_dir[priv->minor]); - *dir_oe[priv->minor] = dir_shadow; - local_irq_restore(flags); - return dir_shadow; -} /* setget_output */ - -static int -gpio_leds_ioctl(unsigned int cmd, unsigned long arg); - -static int -gpio_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) -{ - unsigned long flags; - unsigned long val; - unsigned long shadow; - struct gpio_private *priv = (struct gpio_private *)file->private_data; - if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) { - return -EINVAL; - } - - switch (_IOC_NR(cmd)) { - case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */ - // read the port - return *data_in[priv->minor]; - break; - case IO_SETBITS: - local_irq_save(flags); - if (arg & 0x04) - printk("GPIO SET 2\n"); - // set changeable bits with a 1 in arg - shadow = *data_out[priv->minor]; - shadow |= (arg & changeable_bits[priv->minor]); - *data_out[priv->minor] = shadow; - local_irq_restore(flags); - break; - case IO_CLRBITS: - local_irq_save(flags); - if (arg & 0x04) - printk("GPIO CLR 2\n"); - // clear changeable bits with a 1 in arg - shadow = *data_out[priv->minor]; - shadow &= ~(arg & changeable_bits[priv->minor]); - *data_out[priv->minor] = shadow; - local_irq_restore(flags); - break; - case IO_HIGHALARM: - // set alarm when bits with 1 in arg go high - priv->highalarm |= arg; - spin_lock(&alarm_lock); - gpio_some_alarms = 1; - if (priv->minor == GPIO_MINOR_A) { - gpio_pa_high_alarms |= arg; - } - spin_unlock(&alarm_lock); - break; - case IO_LOWALARM: - // set alarm when bits with 1 in arg go low - priv->lowalarm |= arg; - spin_lock(&alarm_lock); - gpio_some_alarms = 1; - if (priv->minor == GPIO_MINOR_A) { - gpio_pa_low_alarms |= arg; - } - spin_unlock(&alarm_lock); - break; - case IO_CLRALARM: - // clear alarm for bits with 1 in arg - priv->highalarm &= ~arg; - priv->lowalarm &= ~arg; - spin_lock(&alarm_lock); - if (priv->minor == GPIO_MINOR_A) { - if (gpio_pa_high_alarms & arg || - gpio_pa_low_alarms & arg) { - /* Must update the gpio_pa_*alarms masks */ - } - } - spin_unlock(&alarm_lock); - break; - case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */ - /* Read direction 0=input 1=output */ - return *dir_oe[priv->minor]; - case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */ - /* Set direction 0=unchanged 1=input, - * return mask with 1=input - */ - return setget_input(priv, arg); - break; - case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */ - /* Set direction 0=unchanged 1=output, - * return mask with 1=output - */ - return setget_output(priv, arg); - - case IO_CFG_WRITE_MODE: - { - unsigned long dir_shadow; - dir_shadow = *dir_oe[priv->minor]; - - priv->clk_mask = arg & 0xFF; - priv->data_mask = (arg >> 8) & 0xFF; - priv->write_msb = (arg >> 16) & 0x01; - /* Check if we're allowed to change the bits and - * the direction is correct - */ - if (!((priv->clk_mask & changeable_bits[priv->minor]) && - (priv->data_mask & changeable_bits[priv->minor]) && - (priv->clk_mask & dir_shadow) && - (priv->data_mask & dir_shadow))) - { - priv->clk_mask = 0; - priv->data_mask = 0; - return -EPERM; - } - break; - } - case IO_READ_INBITS: - /* *arg is result of reading the input pins */ - val = *data_in[priv->minor]; - if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) - return -EFAULT; - return 0; - break; - case IO_READ_OUTBITS: - /* *arg is result of reading the output shadow */ - val = *data_out[priv->minor]; - if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) - return -EFAULT; - break; - case IO_SETGET_INPUT: - /* bits set in *arg is set to input, - * *arg updated with current input pins. - */ - if (copy_from_user(&val, (unsigned long*)arg, sizeof(val))) - return -EFAULT; - val = setget_input(priv, val); - if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) - return -EFAULT; - break; - case IO_SETGET_OUTPUT: - /* bits set in *arg is set to output, - * *arg updated with current output pins. - */ - if (copy_from_user(&val, (unsigned long*)arg, sizeof(val))) - return -EFAULT; - val = setget_output(priv, val); - if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) - return -EFAULT; - break; - default: - if (priv->minor == GPIO_MINOR_LEDS) - return gpio_leds_ioctl(cmd, arg); - else - return -EINVAL; - } /* switch */ - - return 0; -} - -static int -gpio_leds_ioctl(unsigned int cmd, unsigned long arg) -{ - unsigned char green; - unsigned char red; - - switch (_IOC_NR(cmd)) { - case IO_LEDACTIVE_SET: - green = ((unsigned char) arg) & 1; - red = (((unsigned char) arg) >> 1) & 1; - LED_ACTIVE_SET_G(green); - LED_ACTIVE_SET_R(red); - break; - - default: - return -EINVAL; - } /* switch */ - - return 0; -} - -struct file_operations gpio_fops = { - .owner = THIS_MODULE, - .poll = gpio_poll, - .ioctl = gpio_ioctl, - .write = gpio_write, - .open = gpio_open, - .release = gpio_release, -}; - - -/* main driver initialization routine, called from mem.c */ - -static __init int -gpio_init(void) -{ - int res; - reg_intr_vect_rw_mask intr_mask; - - /* do the formalities */ - - res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops); - if (res < 0) { - printk(KERN_ERR "gpio: couldn't get a major number.\n"); - return res; - } - - /* Clear all leds */ - LED_NETWORK_SET(0); - LED_ACTIVE_SET(0); - LED_DISK_READ(0); - LED_DISK_WRITE(0); - - printk("ETRAX FS GPIO driver v2.5, (c) 2003-2005 Axis Communications AB\n"); - /* We call etrax_gpio_wake_up_check() from timer interrupt and - * from cpu_idle() in kernel/process.c - * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms - * in some tests. - */ - if (request_irq(TIMER_INTR_VECT, gpio_poll_timer_interrupt, - SA_SHIRQ | SA_INTERRUPT,"gpio poll", &alarmlist)) { - printk("err: timer0 irq for gpio\n"); - } - if (request_irq(GEN_IO_INTR_VECT, gpio_pa_interrupt, - SA_SHIRQ | SA_INTERRUPT,"gpio PA", &alarmlist)) { - printk("err: PA irq for gpio\n"); - } - /* enable the gio and timer irq in global config */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.timer = 1; - intr_mask.gen_io = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - return res; -} - -/* this makes sure that gpio_init is called during kernel boot */ - -module_init(gpio_init); diff --git a/trunk/arch/cris/arch-v32/drivers/i2c.c b/trunk/arch/cris/arch-v32/drivers/i2c.c deleted file mode 100644 index 440c20a94963..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/i2c.c +++ /dev/null @@ -1,611 +0,0 @@ -/*!*************************************************************************** -*! -*! FILE NAME : i2c.c -*! -*! DESCRIPTION: implements an interface for IIC/I2C, both directly from other -*! kernel modules (i2c_writereg/readreg) and from userspace using -*! ioctl()'s -*! -*! Nov 30 1998 Torbjorn Eliasson Initial version. -*! Bjorn Wesen Elinux kernel version. -*! Jan 14 2000 Johan Adolfsson Fixed PB shadow register stuff - -*! don't use PB_I2C if DS1302 uses same bits, -*! use PB. -*| June 23 2003 Pieter Grimmerink Added 'i2c_sendnack'. i2c_readreg now -*| generates nack on last received byte, -*| instead of ack. -*| i2c_getack changed data level while clock -*| was high, causing DS75 to see a stop condition -*! -*! --------------------------------------------------------------------------- -*! -*! (C) Copyright 1999-2002 Axis Communications AB, LUND, SWEDEN -*! -*!***************************************************************************/ -/* $Id: i2c.c,v 1.2 2005/05/09 15:29:49 starvik Exp $ */ -/****************** INCLUDE FILES SECTION ***********************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include "i2c.h" - -/****************** I2C DEFINITION SECTION *************************/ - -#define D(x) - -#define I2C_MAJOR 123 /* LOCAL/EXPERIMENTAL */ -static const char i2c_name[] = "i2c"; - -#define CLOCK_LOW_TIME 8 -#define CLOCK_HIGH_TIME 8 -#define START_CONDITION_HOLD_TIME 8 -#define STOP_CONDITION_HOLD_TIME 8 -#define ENABLE_OUTPUT 0x01 -#define ENABLE_INPUT 0x00 -#define I2C_CLOCK_HIGH 1 -#define I2C_CLOCK_LOW 0 -#define I2C_DATA_HIGH 1 -#define I2C_DATA_LOW 0 - -#define i2c_enable() -#define i2c_disable() - -/* enable or disable output-enable, to select output or input on the i2c bus */ - -#define i2c_dir_out() crisv32_io_set_dir(&cris_i2c_data, crisv32_io_dir_out) -#define i2c_dir_in() crisv32_io_set_dir(&cris_i2c_data, crisv32_io_dir_in) - -/* control the i2c clock and data signals */ - -#define i2c_clk(x) crisv32_io_set(&cris_i2c_clk, x) -#define i2c_data(x) crisv32_io_set(&cris_i2c_data, x) - -/* read a bit from the i2c interface */ - -#define i2c_getbit() crisv32_io_rd(&cris_i2c_data) - -#define i2c_delay(usecs) udelay(usecs) - -/****************** VARIABLE SECTION ************************************/ - -static struct crisv32_iopin cris_i2c_clk; -static struct crisv32_iopin cris_i2c_data; - -/****************** FUNCTION DEFINITION SECTION *************************/ - - -/* generate i2c start condition */ - -void -i2c_start(void) -{ - /* - * SCL=1 SDA=1 - */ - i2c_dir_out(); - i2c_delay(CLOCK_HIGH_TIME/6); - i2c_data(I2C_DATA_HIGH); - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - /* - * SCL=1 SDA=0 - */ - i2c_data(I2C_DATA_LOW); - i2c_delay(START_CONDITION_HOLD_TIME); - /* - * SCL=0 SDA=0 - */ - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME); -} - -/* generate i2c stop condition */ - -void -i2c_stop(void) -{ - i2c_dir_out(); - - /* - * SCL=0 SDA=0 - */ - i2c_clk(I2C_CLOCK_LOW); - i2c_data(I2C_DATA_LOW); - i2c_delay(CLOCK_LOW_TIME*2); - /* - * SCL=1 SDA=0 - */ - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME*2); - /* - * SCL=1 SDA=1 - */ - i2c_data(I2C_DATA_HIGH); - i2c_delay(STOP_CONDITION_HOLD_TIME); - - i2c_dir_in(); -} - -/* write a byte to the i2c interface */ - -void -i2c_outbyte(unsigned char x) -{ - int i; - - i2c_dir_out(); - - for (i = 0; i < 8; i++) { - if (x & 0x80) { - i2c_data(I2C_DATA_HIGH); - } else { - i2c_data(I2C_DATA_LOW); - } - - i2c_delay(CLOCK_LOW_TIME/2); - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME/2); - x <<= 1; - } - i2c_data(I2C_DATA_LOW); - i2c_delay(CLOCK_LOW_TIME/2); - - /* - * enable input - */ - i2c_dir_in(); -} - -/* read a byte from the i2c interface */ - -unsigned char -i2c_inbyte(void) -{ - unsigned char aBitByte = 0; - int i; - - /* Switch off I2C to get bit */ - i2c_disable(); - i2c_dir_in(); - i2c_delay(CLOCK_HIGH_TIME/2); - - /* Get bit */ - aBitByte |= i2c_getbit(); - - /* Enable I2C */ - i2c_enable(); - i2c_delay(CLOCK_LOW_TIME/2); - - for (i = 1; i < 8; i++) { - aBitByte <<= 1; - /* Clock pulse */ - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME); - - /* Switch off I2C to get bit */ - i2c_disable(); - i2c_dir_in(); - i2c_delay(CLOCK_HIGH_TIME/2); - - /* Get bit */ - aBitByte |= i2c_getbit(); - - /* Enable I2C */ - i2c_enable(); - i2c_delay(CLOCK_LOW_TIME/2); - } - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - - /* - * we leave the clock low, getbyte is usually followed - * by sendack/nack, they assume the clock to be low - */ - i2c_clk(I2C_CLOCK_LOW); - return aBitByte; -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: i2c_getack -*# -*# DESCRIPTION : checks if ack was received from ic2 -*# -*#--------------------------------------------------------------------------*/ - -int -i2c_getack(void) -{ - int ack = 1; - /* - * enable output - */ - i2c_dir_out(); - /* - * Release data bus by setting - * data high - */ - i2c_data(I2C_DATA_HIGH); - /* - * enable input - */ - i2c_dir_in(); - i2c_delay(CLOCK_HIGH_TIME/4); - /* - * generate ACK clock pulse - */ - i2c_clk(I2C_CLOCK_HIGH); - /* - * Use PORT PB instead of I2C - * for input. (I2C not working) - */ - i2c_clk(1); - i2c_data(1); - /* - * switch off I2C - */ - i2c_data(1); - i2c_disable(); - i2c_dir_in(); - /* - * now wait for ack - */ - i2c_delay(CLOCK_HIGH_TIME/2); - /* - * check for ack - */ - if(i2c_getbit()) - ack = 0; - i2c_delay(CLOCK_HIGH_TIME/2); - if(!ack){ - if(!i2c_getbit()) /* receiver pulld SDA low */ - ack = 1; - i2c_delay(CLOCK_HIGH_TIME/2); - } - - /* - * our clock is high now, make sure data is low - * before we enable our output. If we keep data high - * and enable output, we would generate a stop condition. - */ - i2c_data(I2C_DATA_LOW); - - /* - * end clock pulse - */ - i2c_enable(); - i2c_dir_out(); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_HIGH_TIME/4); - /* - * enable output - */ - i2c_dir_out(); - /* - * remove ACK clock pulse - */ - i2c_data(I2C_DATA_HIGH); - i2c_delay(CLOCK_LOW_TIME/2); - return ack; -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: I2C::sendAck -*# -*# DESCRIPTION : Send ACK on received data -*# -*#--------------------------------------------------------------------------*/ -void -i2c_sendack(void) -{ - /* - * enable output - */ - i2c_delay(CLOCK_LOW_TIME); - i2c_dir_out(); - /* - * set ack pulse high - */ - i2c_data(I2C_DATA_LOW); - /* - * generate clock pulse - */ - i2c_delay(CLOCK_HIGH_TIME/6); - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME/6); - /* - * reset data out - */ - i2c_data(I2C_DATA_HIGH); - i2c_delay(CLOCK_LOW_TIME); - - i2c_dir_in(); -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: i2c_sendnack -*# -*# DESCRIPTION : Sends NACK on received data -*# -*#--------------------------------------------------------------------------*/ -void -i2c_sendnack(void) -{ - /* - * enable output - */ - i2c_delay(CLOCK_LOW_TIME); - i2c_dir_out(); - /* - * set data high - */ - i2c_data(I2C_DATA_HIGH); - /* - * generate clock pulse - */ - i2c_delay(CLOCK_HIGH_TIME/6); - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME); - - i2c_dir_in(); -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: i2c_writereg -*# -*# DESCRIPTION : Writes a value to an I2C device -*# -*#--------------------------------------------------------------------------*/ -int -i2c_writereg(unsigned char theSlave, unsigned char theReg, - unsigned char theValue) -{ - int error, cntr = 3; - unsigned long flags; - - do { - error = 0; - /* - * we don't like to be interrupted - */ - local_irq_save(flags); - - i2c_start(); - /* - * send slave address - */ - i2c_outbyte((theSlave & 0xfe)); - /* - * wait for ack - */ - if(!i2c_getack()) - error = 1; - /* - * now select register - */ - i2c_dir_out(); - i2c_outbyte(theReg); - /* - * now it's time to wait for ack - */ - if(!i2c_getack()) - error |= 2; - /* - * send register register data - */ - i2c_outbyte(theValue); - /* - * now it's time to wait for ack - */ - if(!i2c_getack()) - error |= 4; - /* - * end byte stream - */ - i2c_stop(); - /* - * enable interrupt again - */ - local_irq_restore(flags); - - } while(error && cntr--); - - i2c_delay(CLOCK_LOW_TIME); - - return -error; -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: i2c_readreg -*# -*# DESCRIPTION : Reads a value from the decoder registers. -*# -*#--------------------------------------------------------------------------*/ -unsigned char -i2c_readreg(unsigned char theSlave, unsigned char theReg) -{ - unsigned char b = 0; - int error, cntr = 3; - unsigned long flags; - - do { - error = 0; - /* - * we don't like to be interrupted - */ - local_irq_save(flags); - /* - * generate start condition - */ - i2c_start(); - - /* - * send slave address - */ - i2c_outbyte((theSlave & 0xfe)); - /* - * wait for ack - */ - if(!i2c_getack()) - error = 1; - /* - * now select register - */ - i2c_dir_out(); - i2c_outbyte(theReg); - /* - * now it's time to wait for ack - */ - if(!i2c_getack()) - error = 1; - /* - * repeat start condition - */ - i2c_delay(CLOCK_LOW_TIME); - i2c_start(); - /* - * send slave address - */ - i2c_outbyte(theSlave | 0x01); - /* - * wait for ack - */ - if(!i2c_getack()) - error = 1; - /* - * fetch register - */ - b = i2c_inbyte(); - /* - * last received byte needs to be nacked - * instead of acked - */ - i2c_sendnack(); - /* - * end sequence - */ - i2c_stop(); - /* - * enable interrupt again - */ - local_irq_restore(flags); - - } while(error && cntr--); - - return b; -} - -static int -i2c_open(struct inode *inode, struct file *filp) -{ - return 0; -} - -static int -i2c_release(struct inode *inode, struct file *filp) -{ - return 0; -} - -/* Main device API. ioctl's to write or read to/from i2c registers. - */ - -static int -i2c_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) -{ - if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) { - return -EINVAL; - } - - switch (_IOC_NR(cmd)) { - case I2C_WRITEREG: - /* write to an i2c slave */ - D(printk("i2cw %d %d %d\n", - I2C_ARGSLAVE(arg), - I2C_ARGREG(arg), - I2C_ARGVALUE(arg))); - - return i2c_writereg(I2C_ARGSLAVE(arg), - I2C_ARGREG(arg), - I2C_ARGVALUE(arg)); - case I2C_READREG: - { - unsigned char val; - /* read from an i2c slave */ - D(printk("i2cr %d %d ", - I2C_ARGSLAVE(arg), - I2C_ARGREG(arg))); - val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg)); - D(printk("= %d\n", val)); - return val; - } - default: - return -EINVAL; - - } - - return 0; -} - -static struct file_operations i2c_fops = { - owner: THIS_MODULE, - ioctl: i2c_ioctl, - open: i2c_open, - release: i2c_release, -}; - -int __init -i2c_init(void) -{ - int res; - - /* Setup and enable the Port B I2C interface */ - - crisv32_io_get_name(&cris_i2c_data, CONFIG_ETRAX_I2C_DATA_PORT); - crisv32_io_get_name(&cris_i2c_clk, CONFIG_ETRAX_I2C_CLK_PORT); - - /* register char device */ - - res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops); - if(res < 0) { - printk(KERN_ERR "i2c: couldn't get a major number.\n"); - return res; - } - - printk(KERN_INFO "I2C driver v2.2, (c) 1999-2001 Axis Communications AB\n"); - - return 0; -} - -/* this makes sure that i2c_init is called during boot */ - -module_init(i2c_init); - -/****************** END OF FILE i2c.c ********************************/ diff --git a/trunk/arch/cris/arch-v32/drivers/i2c.h b/trunk/arch/cris/arch-v32/drivers/i2c.h deleted file mode 100644 index bfe1a13f9f35..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/i2c.h +++ /dev/null @@ -1,15 +0,0 @@ - -#include - -/* High level I2C actions */ -int __init i2c_init(void); -int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); -unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg); - -/* Low level I2C */ -void i2c_start(void); -void i2c_stop(void); -void i2c_outbyte(unsigned char x); -unsigned char i2c_inbyte(void); -int i2c_getack(void); -void i2c_sendack(void); diff --git a/trunk/arch/cris/arch-v32/drivers/iop_fw_load.c b/trunk/arch/cris/arch-v32/drivers/iop_fw_load.c deleted file mode 100644 index 11f9895ded50..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/iop_fw_load.c +++ /dev/null @@ -1,219 +0,0 @@ -/* $Id: iop_fw_load.c,v 1.4 2005/04/07 09:27:46 larsv Exp $ - * - * Firmware loader for ETRAX FS IO-Processor - * - * Copyright (C) 2004 Axis Communications AB - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define IOP_TIMEOUT 100 - -static struct device iop_spu_device[2] = { - { .bus_id = "iop-spu0", }, - { .bus_id = "iop-spu1", }, -}; - -static struct device iop_mpu_device = { - .bus_id = "iop-mpu", -}; - -static int wait_mpu_idle(void) -{ - reg_iop_mpu_r_stat mpu_stat; - unsigned int timeout = IOP_TIMEOUT; - - do { - mpu_stat = REG_RD(iop_mpu, regi_iop_mpu, r_stat); - } while (mpu_stat.instr_reg_busy == regk_iop_mpu_yes && --timeout > 0); - if (timeout == 0) { - printk(KERN_ERR "Timeout waiting for MPU to be idle\n"); - return -EBUSY; - } - return 0; -} - -int iop_fw_load_spu(const unsigned char *fw_name, unsigned int spu_inst) -{ - reg_iop_sw_cpu_rw_mc_ctrl mc_ctrl = { - .wr_spu0_mem = regk_iop_sw_cpu_no, - .wr_spu1_mem = regk_iop_sw_cpu_no, - .size = 4, - .cmd = regk_iop_sw_cpu_reg_copy, - .keep_owner = regk_iop_sw_cpu_yes - }; - reg_iop_spu_rw_ctrl spu_ctrl = { - .en = regk_iop_spu_no, - .fsm = regk_iop_spu_no, - }; - reg_iop_sw_cpu_r_mc_stat mc_stat; - const struct firmware *fw_entry; - u32 *data; - unsigned int timeout; - int retval, i; - - if (spu_inst > 1) - return -ENODEV; - - /* get firmware */ - retval = request_firmware(&fw_entry, - fw_name, - &iop_spu_device[spu_inst]); - if (retval != 0) - { - printk(KERN_ERR - "iop_load_spu: Failed to load firmware \"%s\"\n", - fw_name); - return retval; - } - data = (u32 *) fw_entry->data; - - /* acquire ownership of memory controller */ - switch (spu_inst) { - case 0: - mc_ctrl.wr_spu0_mem = regk_iop_sw_cpu_yes; - REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl); - break; - case 1: - mc_ctrl.wr_spu1_mem = regk_iop_sw_cpu_yes; - REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl); - break; - } - timeout = IOP_TIMEOUT; - do { - REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl); - mc_stat = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, r_mc_stat); - } while (mc_stat.owned_by_cpu == regk_iop_sw_cpu_no && --timeout > 0); - if (timeout == 0) { - printk(KERN_ERR "Timeout waiting to acquire MC\n"); - retval = -EBUSY; - goto out; - } - - /* write to SPU memory */ - for (i = 0; i < (fw_entry->size/4); i++) { - switch (spu_inst) { - case 0: - REG_WR_INT(iop_spu, regi_iop_spu0, rw_seq_pc, (i*4)); - break; - case 1: - REG_WR_INT(iop_spu, regi_iop_spu1, rw_seq_pc, (i*4)); - break; - } - REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_data, *data); - data++; - } - - /* release ownership of memory controller */ - (void) REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rs_mc_data); - - out: - release_firmware(fw_entry); - return retval; -} - -int iop_fw_load_mpu(unsigned char *fw_name) -{ - const unsigned int start_addr = 0; - reg_iop_mpu_rw_ctrl mpu_ctrl; - const struct firmware *fw_entry; - u32 *data; - int retval, i; - - /* get firmware */ - retval = request_firmware(&fw_entry, fw_name, &iop_mpu_device); - if (retval != 0) - { - printk(KERN_ERR - "iop_load_spu: Failed to load firmware \"%s\"\n", - fw_name); - return retval; - } - data = (u32 *) fw_entry->data; - - /* disable MPU */ - mpu_ctrl.en = regk_iop_mpu_no; - REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); - /* put start address in R0 */ - REG_WR_VECT(iop_mpu, regi_iop_mpu, rw_r, 0, start_addr); - /* write to memory by executing 'SWX i, 4, R0' for each word */ - if ((retval = wait_mpu_idle()) != 0) - goto out; - REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0)); - for (i = 0; i < (fw_entry->size / 4); i++) { - REG_WR_INT(iop_mpu, regi_iop_mpu, rw_immediate, *data); - if ((retval = wait_mpu_idle()) != 0) - goto out; - data++; - } - - out: - release_firmware(fw_entry); - return retval; -} - -int iop_start_mpu(unsigned int start_addr) -{ - reg_iop_mpu_rw_ctrl mpu_ctrl = { .en = regk_iop_mpu_yes }; - int retval; - - /* disable MPU */ - if ((retval = wait_mpu_idle()) != 0) - goto out; - REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT()); - if ((retval = wait_mpu_idle()) != 0) - goto out; - /* set PC and wait for it to bite */ - if ((retval = wait_mpu_idle()) != 0) - goto out; - REG_WR_INT(iop_mpu, regi_iop_mpu, rw_instr, MPU_BA_I(start_addr)); - if ((retval = wait_mpu_idle()) != 0) - goto out; - /* make sure the MPU starts executing with interrupts disabled */ - REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI()); - if ((retval = wait_mpu_idle()) != 0) - goto out; - /* enable MPU */ - REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); - out: - return retval; -} - -static int __init iop_fw_load_init(void) -{ - device_initialize(&iop_spu_device[0]); - kobject_set_name(&iop_spu_device[0].kobj, "iop-spu0"); - kobject_add(&iop_spu_device[0].kobj); - device_initialize(&iop_spu_device[1]); - kobject_set_name(&iop_spu_device[1].kobj, "iop-spu1"); - kobject_add(&iop_spu_device[1].kobj); - device_initialize(&iop_mpu_device); - kobject_set_name(&iop_mpu_device.kobj, "iop-mpu"); - kobject_add(&iop_mpu_device.kobj); - return 0; -} - -static void __exit iop_fw_load_exit(void) -{ -} - -module_init(iop_fw_load_init); -module_exit(iop_fw_load_exit); - -MODULE_DESCRIPTION("ETRAX FS IO-Processor Firmware Loader"); -MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(iop_fw_load_spu); -EXPORT_SYMBOL(iop_fw_load_mpu); -EXPORT_SYMBOL(iop_start_mpu); diff --git a/trunk/arch/cris/arch-v32/drivers/nandflash.c b/trunk/arch/cris/arch-v32/drivers/nandflash.c deleted file mode 100644 index fc2a619b035d..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/nandflash.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * arch/cris/arch-v32/drivers/nandflash.c - * - * Copyright (c) 2004 - * - * Derived from drivers/mtd/nand/spia.c - * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) - * - * $Id: nandflash.c,v 1.3 2005/06/01 10:57:12 starvik Exp $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CE_BIT 4 -#define CLE_BIT 5 -#define ALE_BIT 6 -#define BY_BIT 7 - -static struct mtd_info *crisv32_mtd = NULL; -/* - * hardware specific access to control-lines -*/ -static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd) -{ - unsigned long flags; - reg_gio_rw_pa_dout dout = REG_RD(gio, regi_gio, rw_pa_dout); - - local_irq_save(flags); - switch(cmd){ - case NAND_CTL_SETCLE: - dout.data |= (1<> BY_BIT); -} - -/* - * Main initialization routine - */ -struct mtd_info* __init crisv32_nand_flash_probe (void) -{ - void __iomem *read_cs; - void __iomem *write_cs; - - reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, rw_grp3_cfg); - reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe); - struct nand_chip *this; - int err = 0; - - /* Allocate memory for MTD device structure and private data */ - crisv32_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip), - GFP_KERNEL); - if (!crisv32_mtd) { - printk ("Unable to allocate CRISv32 NAND MTD device structure.\n"); - err = -ENOMEM; - return NULL; - } - - read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192); - write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192); - - if (!read_cs || !write_cs) { - printk("CRISv32 NAND ioremap failed\n"); - err = -EIO; - goto out_mtd; - } - - /* Get pointer to private data */ - this = (struct nand_chip *) (&crisv32_mtd[1]); - - pa_oe.oe |= 1 << CE_BIT; - pa_oe.oe |= 1 << ALE_BIT; - pa_oe.oe |= 1 << CLE_BIT; - pa_oe.oe &= ~ (1 << BY_BIT); - REG_WR(gio, regi_gio, rw_pa_oe, pa_oe); - - bif_cfg.gated_csp0 = regk_bif_core_rd; - bif_cfg.gated_csp1 = regk_bif_core_wr; - REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); - - /* Initialize structures */ - memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info)); - memset((char *) this, 0, sizeof(struct nand_chip)); - - /* Link the private data with the MTD structure */ - crisv32_mtd->priv = this; - - /* Set address of NAND IO lines */ - this->IO_ADDR_R = read_cs; - this->IO_ADDR_W = write_cs; - this->hwcontrol = crisv32_hwcontrol; - this->dev_ready = crisv32_device_ready; - /* 20 us command delay time */ - this->chip_delay = 20; - this->eccmode = NAND_ECC_SOFT; - - /* Enable the following for a flash based bad block table */ - this->options = NAND_USE_FLASH_BBT; - - /* Scan to find existance of the device */ - if (nand_scan (crisv32_mtd, 1)) { - err = -ENXIO; - goto out_ior; - } - - return crisv32_mtd; - -out_ior: - iounmap((void *)read_cs); - iounmap((void *)write_cs); -out_mtd: - kfree (crisv32_mtd); - return NULL; -} - diff --git a/trunk/arch/cris/arch-v32/drivers/pcf8563.c b/trunk/arch/cris/arch-v32/drivers/pcf8563.c deleted file mode 100644 index f894580b648b..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/pcf8563.c +++ /dev/null @@ -1,341 +0,0 @@ -/* - * PCF8563 RTC - * - * From Phillips' datasheet: - * - * The PCF8563 is a CMOS real-time clock/calendar optimized for low power - * consumption. A programmable clock output, interupt output and voltage - * low detector are also provided. All address and data are transferred - * serially via two-line bidirectional I2C-bus. Maximum bus speed is - * 400 kbits/s. The built-in word address register is incremented - * automatically after each written or read byte. - * - * Copyright (c) 2002-2003, Axis Communications AB - * All rights reserved. - * - * Author: Tobias Anderberg . - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "i2c.h" - -#define PCF8563_MAJOR 121 /* Local major number. */ -#define DEVICE_NAME "rtc" /* Name which is registered in /proc/devices. */ -#define PCF8563_NAME "PCF8563" -#define DRIVER_VERSION "$Revision: 1.1 $" - -/* Two simple wrapper macros, saves a few keystrokes. */ -#define rtc_read(x) i2c_readreg(RTC_I2C_READ, x) -#define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y) - -static const unsigned char days_in_month[] = - { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; - -int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long); -int pcf8563_open(struct inode *, struct file *); -int pcf8563_release(struct inode *, struct file *); - -static struct file_operations pcf8563_fops = { - owner: THIS_MODULE, - ioctl: pcf8563_ioctl, - open: pcf8563_open, - release: pcf8563_release, -}; - -unsigned char -pcf8563_readreg(int reg) -{ - unsigned char res = rtc_read(reg); - - /* The PCF8563 does not return 0 for unimplemented bits */ - switch (reg) { - case RTC_SECONDS: - case RTC_MINUTES: - res &= 0x7F; - break; - case RTC_HOURS: - case RTC_DAY_OF_MONTH: - res &= 0x3F; - break; - case RTC_WEEKDAY: - res &= 0x07; - break; - case RTC_MONTH: - res &= 0x1F; - break; - case RTC_CONTROL1: - res &= 0xA8; - break; - case RTC_CONTROL2: - res &= 0x1F; - break; - case RTC_CLOCKOUT_FREQ: - case RTC_TIMER_CONTROL: - res &= 0x83; - break; - } - return res; -} - -void -pcf8563_writereg(int reg, unsigned char val) -{ -#ifdef CONFIG_ETRAX_RTC_READONLY - if (reg == RTC_CONTROL1 || (reg >= RTC_SECONDS && reg <= RTC_YEAR)) - return; -#endif - - rtc_write(reg, val); -} - -void -get_rtc_time(struct rtc_time *tm) -{ - tm->tm_sec = rtc_read(RTC_SECONDS); - tm->tm_min = rtc_read(RTC_MINUTES); - tm->tm_hour = rtc_read(RTC_HOURS); - tm->tm_mday = rtc_read(RTC_DAY_OF_MONTH); - tm->tm_wday = rtc_read(RTC_WEEKDAY); - tm->tm_mon = rtc_read(RTC_MONTH); - tm->tm_year = rtc_read(RTC_YEAR); - - if (tm->tm_sec & 0x80) - printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time " - "information is no longer guaranteed!\n", PCF8563_NAME); - - tm->tm_year = BCD_TO_BIN(tm->tm_year) + ((tm->tm_mon & 0x80) ? 100 : 0); - tm->tm_sec &= 0x7F; - tm->tm_min &= 0x7F; - tm->tm_hour &= 0x3F; - tm->tm_mday &= 0x3F; - tm->tm_wday &= 0x07; /* Not coded in BCD. */ - tm->tm_mon &= 0x1F; - - BCD_TO_BIN(tm->tm_sec); - BCD_TO_BIN(tm->tm_min); - BCD_TO_BIN(tm->tm_hour); - BCD_TO_BIN(tm->tm_mday); - BCD_TO_BIN(tm->tm_mon); - tm->tm_mon--; /* Month is 1..12 in RTC but 0..11 in linux */ -} - -int __init -pcf8563_init(void) -{ - /* Initiate the i2c protocol. */ - i2c_init(); - - /* - * First of all we need to reset the chip. This is done by - * clearing control1, control2 and clk freq and resetting - * all alarms. - */ - if (rtc_write(RTC_CONTROL1, 0x00) < 0) - goto err; - - if (rtc_write(RTC_CONTROL2, 0x00) < 0) - goto err; - - if (rtc_write(RTC_CLOCKOUT_FREQ, 0x00) < 0) - goto err; - - if (rtc_write(RTC_TIMER_CONTROL, 0x03) < 0) - goto err; - - /* Reset the alarms. */ - if (rtc_write(RTC_MINUTE_ALARM, 0x80) < 0) - goto err; - - if (rtc_write(RTC_HOUR_ALARM, 0x80) < 0) - goto err; - - if (rtc_write(RTC_DAY_ALARM, 0x80) < 0) - goto err; - - if (rtc_write(RTC_WEEKDAY_ALARM, 0x80) < 0) - goto err; - - if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) { - printk(KERN_INFO "%s: Unable to get major numer %d for RTC device.\n", - PCF8563_NAME, PCF8563_MAJOR); - return -1; - } - - printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME, DRIVER_VERSION); - - /* Check for low voltage, and warn about it.. */ - if (rtc_read(RTC_SECONDS) & 0x80) - printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time " - "information is no longer guaranteed!\n", PCF8563_NAME); - - return 0; - -err: - printk(KERN_INFO "%s: Error initializing chip.\n", PCF8563_NAME); - return -1; -} - -void __exit -pcf8563_exit(void) -{ - if (unregister_chrdev(PCF8563_MAJOR, DEVICE_NAME) < 0) { - printk(KERN_INFO "%s: Unable to unregister device.\n", PCF8563_NAME); - } -} - -/* - * ioctl calls for this driver. Why return -ENOTTY upon error? Because - * POSIX says so! - */ -int -pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) -{ - /* Some sanity checks. */ - if (_IOC_TYPE(cmd) != RTC_MAGIC) - return -ENOTTY; - - if (_IOC_NR(cmd) > RTC_MAX_IOCTL) - return -ENOTTY; - - switch (cmd) { - case RTC_RD_TIME: - { - struct rtc_time tm; - - memset(&tm, 0, sizeof (struct rtc_time)); - get_rtc_time(&tm); - - if (copy_to_user((struct rtc_time *) arg, &tm, sizeof tm)) { - return -EFAULT; - } - - return 0; - } - - case RTC_SET_TIME: - { -#ifdef CONFIG_ETRAX_RTC_READONLY - return -EPERM; -#else - int leap; - int year; - int century; - struct rtc_time tm; - - if (!capable(CAP_SYS_TIME)) - return -EPERM; - - if (copy_from_user(&tm, (struct rtc_time *) arg, sizeof tm)) - return -EFAULT; - - /* Convert from struct tm to struct rtc_time. */ - tm.tm_year += 1900; - tm.tm_mon += 1; - - /* - * Check if tm.tm_year is a leap year. A year is a leap - * year if it is divisible by 4 but not 100, except - * that years divisible by 400 _are_ leap years. - */ - year = tm.tm_year; - leap = (tm.tm_mon == 2) && ((year % 4 == 0 && year % 100 != 0) || year % 400 == 0); - - /* Perform some sanity checks. */ - if ((tm.tm_year < 1970) || - (tm.tm_mon > 12) || - (tm.tm_mday == 0) || - (tm.tm_mday > days_in_month[tm.tm_mon] + leap) || - (tm.tm_wday >= 7) || - (tm.tm_hour >= 24) || - (tm.tm_min >= 60) || - (tm.tm_sec >= 60)) - return -EINVAL; - - century = (tm.tm_year >= 2000) ? 0x80 : 0; - tm.tm_year = tm.tm_year % 100; - - BIN_TO_BCD(tm.tm_year); - BIN_TO_BCD(tm.tm_mday); - BIN_TO_BCD(tm.tm_hour); - BIN_TO_BCD(tm.tm_min); - BIN_TO_BCD(tm.tm_sec); - tm.tm_mon |= century; - - rtc_write(RTC_YEAR, tm.tm_year); - rtc_write(RTC_MONTH, tm.tm_mon); - rtc_write(RTC_WEEKDAY, tm.tm_wday); /* Not coded in BCD. */ - rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday); - rtc_write(RTC_HOURS, tm.tm_hour); - rtc_write(RTC_MINUTES, tm.tm_min); - rtc_write(RTC_SECONDS, tm.tm_sec); - - return 0; -#endif /* !CONFIG_ETRAX_RTC_READONLY */ - } - - case RTC_VLOW_RD: - { - int vl_bit = 0; - - if (rtc_read(RTC_SECONDS) & 0x80) { - vl_bit = 1; - printk(KERN_WARNING "%s: RTC Voltage Low - reliable " - "date/time information is no longer guaranteed!\n", - PCF8563_NAME); - } - if (copy_to_user((int *) arg, &vl_bit, sizeof(int))) - return -EFAULT; - - return 0; - } - - case RTC_VLOW_SET: - { - /* Clear the VL bit in the seconds register */ - int ret = rtc_read(RTC_SECONDS); - - rtc_write(RTC_SECONDS, (ret & 0x7F)); - - return 0; - } - - default: - return -ENOTTY; - } - - return 0; -} - -int -pcf8563_open(struct inode *inode, struct file *filp) -{ - MOD_INC_USE_COUNT; - return 0; -} - -int -pcf8563_release(struct inode *inode, struct file *filp) -{ - MOD_DEC_USE_COUNT; - return 0; -} - -module_init(pcf8563_init); -module_exit(pcf8563_exit); diff --git a/trunk/arch/cris/arch-v32/drivers/pci/Makefile b/trunk/arch/cris/arch-v32/drivers/pci/Makefile deleted file mode 100644 index bff7482f2444..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/pci/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for Etrax cardbus driver -# - -obj-$(CONFIG_ETRAX_CARDBUS) += bios.o dma.o diff --git a/trunk/arch/cris/arch-v32/drivers/pci/bios.c b/trunk/arch/cris/arch-v32/drivers/pci/bios.c deleted file mode 100644 index 24bc149889b6..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/pci/bios.c +++ /dev/null @@ -1,131 +0,0 @@ -#include -#include -#include - -void __devinit pcibios_fixup_bus(struct pci_bus *b) -{ -} - -char * __devinit pcibios_setup(char *str) -{ - return NULL; -} - -void pcibios_set_master(struct pci_dev *dev) -{ - u8 lat; - pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); - printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat); - pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); -} - -int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, - enum pci_mmap_state mmap_state, int write_combine) -{ - unsigned long prot; - - /* Leave vm_pgoff as-is, the PCI space address is the physical - * address on this platform. - */ - vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO); - - prot = pgprot_val(vma->vm_page_prot); - vma->vm_page_prot = __pgprot(prot); - - /* Write-combine setting is ignored, it is changed via the mtrr - * interfaces on this platform. - */ - if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, - vma->vm_end - vma->vm_start, - vma->vm_page_prot)) - return -EAGAIN; - - return 0; -} - -void -pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) -{ - if (res->flags & IORESOURCE_IO) { - unsigned long start = res->start; - - if (start & 0x300) { - start = (start + 0x3ff) & ~0x3ff; - res->start = start; - } - } -} - -int pcibios_enable_resources(struct pci_dev *dev, int mask) -{ - u16 cmd, old_cmd; - int idx; - struct resource *r; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - old_cmd = cmd; - for(idx=0; idx<6; idx++) { - /* Only set up the requested stuff */ - if (!(mask & (1<resource[idx]; - if (!r->start && r->end) { - printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); - return -EINVAL; - } - if (r->flags & IORESOURCE_IO) - cmd |= PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - cmd |= PCI_COMMAND_MEMORY; - } - if (dev->resource[PCI_ROM_RESOURCE].start) - cmd |= PCI_COMMAND_MEMORY; - if (cmd != old_cmd) { - printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; -} - -int pcibios_enable_irq(struct pci_dev *dev) -{ - dev->irq = EXT_INTR_VECT; - return 0; -} - -int pcibios_enable_device(struct pci_dev *dev, int mask) -{ - int err; - - if ((err = pcibios_enable_resources(dev, mask)) < 0) - return err; - - return pcibios_enable_irq(dev); -} - -int pcibios_assign_resources(void) -{ - struct pci_dev *dev = NULL; - int idx; - struct resource *r; - - while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - int class = dev->class >> 8; - - /* Don't touch classless devices and host bridges */ - if (!class || class == PCI_CLASS_BRIDGE_HOST) - continue; - - for(idx=0; idx<6; idx++) { - r = &dev->resource[idx]; - - if (!r->start && r->end) - pci_assign_resource(dev, idx); - } - } - return 0; -} - -EXPORT_SYMBOL(pcibios_assign_resources); diff --git a/trunk/arch/cris/arch-v32/drivers/pci/dma.c b/trunk/arch/cris/arch-v32/drivers/pci/dma.c deleted file mode 100644 index 10329306d23c..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/pci/dma.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Dynamic DMA mapping support. - * - * On cris there is no hardware dynamic DMA address translation, - * so consistent alloc/free are merely page allocation/freeing. - * The rest of the dynamic DMA mapping interface is implemented - * in asm/pci.h. - * - * Borrowed from i386. - */ - -#include -#include -#include -#include -#include - -struct dma_coherent_mem { - void *virt_base; - u32 device_base; - int size; - int flags; - unsigned long *bitmap; -}; - -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, unsigned int __nocast gfp) -{ - void *ret; - struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; - int order = get_order(size); - /* ignore region specifiers */ - gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); - - if (mem) { - int page = bitmap_find_free_region(mem->bitmap, mem->size, - order); - if (page >= 0) { - *dma_handle = mem->device_base + (page << PAGE_SHIFT); - ret = mem->virt_base + (page << PAGE_SHIFT); - memset(ret, 0, size); - return ret; - } - if (mem->flags & DMA_MEMORY_EXCLUSIVE) - return NULL; - } - - if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff)) - gfp |= GFP_DMA; - - ret = (void *)__get_free_pages(gfp, order); - - if (ret != NULL) { - memset(ret, 0, size); - *dma_handle = virt_to_phys(ret); - } - return ret; -} - -void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) -{ - struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; - int order = get_order(size); - - if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) { - int page = (vaddr - mem->virt_base) >> PAGE_SHIFT; - - bitmap_release_region(mem->bitmap, page, order); - } else - free_pages((unsigned long)vaddr, order); -} - -int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, - dma_addr_t device_addr, size_t size, int flags) -{ - void __iomem *mem_base; - int pages = size >> PAGE_SHIFT; - int bitmap_size = (pages + 31)/32; - - if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0) - goto out; - if (!size) - goto out; - if (dev->dma_mem) - goto out; - - /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */ - - mem_base = ioremap(bus_addr, size); - if (!mem_base) - goto out; - - dev->dma_mem = kmalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL); - if (!dev->dma_mem) - goto out; - memset(dev->dma_mem, 0, sizeof(struct dma_coherent_mem)); - dev->dma_mem->bitmap = kmalloc(bitmap_size, GFP_KERNEL); - if (!dev->dma_mem->bitmap) - goto free1_out; - memset(dev->dma_mem->bitmap, 0, bitmap_size); - - dev->dma_mem->virt_base = mem_base; - dev->dma_mem->device_base = device_addr; - dev->dma_mem->size = pages; - dev->dma_mem->flags = flags; - - if (flags & DMA_MEMORY_MAP) - return DMA_MEMORY_MAP; - - return DMA_MEMORY_IO; - - free1_out: - kfree(dev->dma_mem->bitmap); - out: - return 0; -} -EXPORT_SYMBOL(dma_declare_coherent_memory); - -void dma_release_declared_memory(struct device *dev) -{ - struct dma_coherent_mem *mem = dev->dma_mem; - - if(!mem) - return; - dev->dma_mem = NULL; - iounmap(mem->virt_base); - kfree(mem->bitmap); - kfree(mem); -} -EXPORT_SYMBOL(dma_release_declared_memory); - -void *dma_mark_declared_memory_occupied(struct device *dev, - dma_addr_t device_addr, size_t size) -{ - struct dma_coherent_mem *mem = dev->dma_mem; - int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT; - int pos, err; - - if (!mem) - return ERR_PTR(-EINVAL); - - pos = (device_addr - mem->device_base) >> PAGE_SHIFT; - err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages)); - if (err != 0) - return ERR_PTR(err); - return mem->virt_base + (pos << PAGE_SHIFT); -} -EXPORT_SYMBOL(dma_mark_declared_memory_occupied); diff --git a/trunk/arch/cris/arch-v32/drivers/sync_serial.c b/trunk/arch/cris/arch-v32/drivers/sync_serial.c deleted file mode 100644 index c85a6df8558f..000000000000 --- a/trunk/arch/cris/arch-v32/drivers/sync_serial.c +++ /dev/null @@ -1,1283 +0,0 @@ -/* - * Simple synchronous serial port driver for ETRAX FS. - * - * Copyright (c) 2005 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* The receiver is a bit tricky beacuse of the continuous stream of data.*/ -/* */ -/* Three DMA descriptors are linked together. Each DMA descriptor is */ -/* responsible for port->bufchunk of a common buffer. */ -/* */ -/* +---------------------------------------------+ */ -/* | +----------+ +----------+ +----------+ | */ -/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */ -/* +----------+ +----------+ +----------+ */ -/* | | | */ -/* v v v */ -/* +-------------------------------------+ */ -/* | BUFFER | */ -/* +-------------------------------------+ */ -/* |<- data_avail ->| */ -/* readp writep */ -/* */ -/* If the application keeps up the pace readp will be right after writep.*/ -/* If the application can't keep the pace we have to throw away data. */ -/* The idea is that readp should be ready with the data pointed out by */ -/* Descr[i] when the DMA has filled in Descr[i+1]. */ -/* Otherwise we will discard */ -/* the rest of the data pointed out by Descr1 and set readp to the start */ -/* of Descr2 */ - -#define SYNC_SERIAL_MAJOR 125 - -/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */ -/* words can be handled */ -#define IN_BUFFER_SIZE 12288 -#define IN_DESCR_SIZE 256 -#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE) -#define OUT_BUFFER_SIZE 4096 - -#define DEFAULT_FRAME_RATE 0 -#define DEFAULT_WORD_RATE 7 - -/* NOTE: Enabling some debug will likely cause overrun or underrun, - * especially if manual mode is use. - */ -#define DEBUG(x) -#define DEBUGREAD(x) -#define DEBUGWRITE(x) -#define DEBUGPOLL(x) -#define DEBUGRXINT(x) -#define DEBUGTXINT(x) - -typedef struct sync_port -{ - reg_scope_instances regi_sser; - reg_scope_instances regi_dmain; - reg_scope_instances regi_dmaout; - - char started; /* 1 if port has been started */ - char port_nbr; /* Port 0 or 1 */ - char busy; /* 1 if port is busy */ - - char enabled; /* 1 if port is enabled */ - char use_dma; /* 1 if port uses dma */ - char tr_running; - - char init_irqs; - int output; - int input; - - volatile unsigned int out_count; /* Remaining bytes for current transfer */ - unsigned char* outp; /* Current position in out_buffer */ - volatile unsigned char* volatile readp; /* Next byte to be read by application */ - volatile unsigned char* volatile writep; /* Next byte to be written by etrax */ - unsigned int in_buffer_size; - unsigned int inbufchunk; - unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32))); - unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32))); - unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32))); - struct dma_descr_data* next_rx_desc; - struct dma_descr_data* prev_rx_desc; - int full; - - dma_descr_data in_descr[NUM_IN_DESCR] __attribute__ ((__aligned__(16))); - dma_descr_context in_context __attribute__ ((__aligned__(32))); - dma_descr_data out_descr __attribute__ ((__aligned__(16))); - dma_descr_context out_context __attribute__ ((__aligned__(32))); - wait_queue_head_t out_wait_q; - wait_queue_head_t in_wait_q; - - spinlock_t lock; -} sync_port; - -static int etrax_sync_serial_init(void); -static void initialize_port(int portnbr); -static inline int sync_data_avail(struct sync_port *port); - -static int sync_serial_open(struct inode *, struct file*); -static int sync_serial_release(struct inode*, struct file*); -static unsigned int sync_serial_poll(struct file *filp, poll_table *wait); - -static int sync_serial_ioctl(struct inode*, struct file*, - unsigned int cmd, unsigned long arg); -static ssize_t sync_serial_write(struct file * file, const char * buf, - size_t count, loff_t *ppos); -static ssize_t sync_serial_read(struct file *file, char *buf, - size_t count, loff_t *ppos); - -#if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ - defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ - (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ - defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)) -#define SYNC_SER_DMA -#endif - -static void send_word(sync_port* port); -static void start_dma(struct sync_port *port, const char* data, int count); -static void start_dma_in(sync_port* port); -#ifdef SYNC_SER_DMA -static irqreturn_t tr_interrupt(int irq, void *dev_id, struct pt_regs * regs); -static irqreturn_t rx_interrupt(int irq, void *dev_id, struct pt_regs * regs); -#endif - -#if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ - !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ - (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ - !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)) -#define SYNC_SER_MANUAL -#endif -#ifdef SYNC_SER_MANUAL -static irqreturn_t manual_interrupt(int irq, void *dev_id, struct pt_regs * regs); -#endif - -/* The ports */ -static struct sync_port ports[]= -{ - { - .regi_sser = regi_sser0, - .regi_dmaout = regi_dma4, - .regi_dmain = regi_dma5, -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) - .use_dma = 1, -#else - .use_dma = 0, -#endif - }, - { - .regi_sser = regi_sser1, - .regi_dmaout = regi_dma6, - .regi_dmain = regi_dma7, -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) - .use_dma = 1, -#else - .use_dma = 0, -#endif - } -}; - -#define NUMBER_OF_PORTS (sizeof(ports)/sizeof(sync_port)) - -static struct file_operations sync_serial_fops = { - .owner = THIS_MODULE, - .write = sync_serial_write, - .read = sync_serial_read, - .poll = sync_serial_poll, - .ioctl = sync_serial_ioctl, - .open = sync_serial_open, - .release = sync_serial_release -}; - -static int __init etrax_sync_serial_init(void) -{ - ports[0].enabled = 0; - ports[1].enabled = 0; - - if (register_chrdev(SYNC_SERIAL_MAJOR,"sync serial", &sync_serial_fops) <0 ) - { - printk("unable to get major for synchronous serial port\n"); - return -EBUSY; - } - - /* Initialize Ports */ -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) - if (crisv32_pinmux_alloc_fixed(pinmux_sser0)) - { - printk("Unable to allocate pins for syncrhronous serial port 0\n"); - return -EIO; - } - ports[0].enabled = 1; - initialize_port(0); -#endif - -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) - if (crisv32_pinmux_alloc_fixed(pinmux_sser1)) - { - printk("Unable to allocate pins for syncrhronous serial port 0\n"); - return -EIO; - } - ports[1].enabled = 1; - initialize_port(1); -#endif - - printk("ETRAX FS synchronous serial port driver\n"); - return 0; -} - -static void __init initialize_port(int portnbr) -{ - struct sync_port* port = &ports[portnbr]; - reg_sser_rw_cfg cfg = {0}; - reg_sser_rw_frm_cfg frm_cfg = {0}; - reg_sser_rw_tr_cfg tr_cfg = {0}; - reg_sser_rw_rec_cfg rec_cfg = {0}; - - DEBUG(printk("Init sync serial port %d\n", portnbr)); - - port->port_nbr = portnbr; - port->init_irqs = 1; - - port->outp = port->out_buffer; - port->output = 1; - port->input = 0; - - port->readp = port->flip; - port->writep = port->flip; - port->in_buffer_size = IN_BUFFER_SIZE; - port->inbufchunk = IN_DESCR_SIZE; - port->next_rx_desc = &port->in_descr[0]; - port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1]; - port->prev_rx_desc->eol = 1; - - init_waitqueue_head(&port->out_wait_q); - init_waitqueue_head(&port->in_wait_q); - - spin_lock_init(&port->lock); - - cfg.out_clk_src = regk_sser_intern_clk; - cfg.out_clk_pol = regk_sser_pos; - cfg.clk_od_mode = regk_sser_no; - cfg.clk_dir = regk_sser_out; - cfg.gate_clk = regk_sser_no; - cfg.base_freq = regk_sser_f29_493; - cfg.clk_div = 256; - REG_WR(sser, port->regi_sser, rw_cfg, cfg); - - frm_cfg.wordrate = DEFAULT_WORD_RATE; - frm_cfg.type = regk_sser_edge; - frm_cfg.frame_pin_dir = regk_sser_out; - frm_cfg.frame_pin_use = regk_sser_frm; - frm_cfg.status_pin_dir = regk_sser_in; - frm_cfg.status_pin_use = regk_sser_hold; - frm_cfg.out_on = regk_sser_tr; - frm_cfg.tr_delay = 1; - REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); - - tr_cfg.urun_stop = regk_sser_no; - tr_cfg.sample_size = 7; - tr_cfg.sh_dir = regk_sser_msbfirst; - tr_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no; - tr_cfg.rate_ctrl = regk_sser_bulk; - tr_cfg.data_pin_use = regk_sser_dout; - tr_cfg.bulk_wspace = 1; - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); - - rec_cfg.sample_size = 7; - rec_cfg.sh_dir = regk_sser_msbfirst; - rec_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no; - rec_cfg.fifo_thr = regk_sser_inf; - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); -} - -static inline int sync_data_avail(struct sync_port *port) -{ - int avail; - unsigned char *start; - unsigned char *end; - - start = (unsigned char*)port->readp; /* cast away volatile */ - end = (unsigned char*)port->writep; /* cast away volatile */ - /* 0123456789 0123456789 - * ----- - ----- - * ^rp ^wp ^wp ^rp - */ - - if (end >= start) - avail = end - start; - else - avail = port->in_buffer_size - (start - end); - return avail; -} - -static inline int sync_data_avail_to_end(struct sync_port *port) -{ - int avail; - unsigned char *start; - unsigned char *end; - - start = (unsigned char*)port->readp; /* cast away volatile */ - end = (unsigned char*)port->writep; /* cast away volatile */ - /* 0123456789 0123456789 - * ----- ----- - * ^rp ^wp ^wp ^rp - */ - - if (end >= start) - avail = end - start; - else - avail = port->flip + port->in_buffer_size - start; - return avail; -} - -static int sync_serial_open(struct inode *inode, struct file *file) -{ - int dev = MINOR(inode->i_rdev); - sync_port* port; - reg_dma_rw_cfg cfg = {.en = regk_dma_yes}; - reg_dma_rw_intr_mask intr_mask = {.data = regk_dma_yes}; - - DEBUG(printk("Open sync serial port %d\n", dev)); - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) - { - DEBUG(printk("Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - /* Allow open this device twice (assuming one reader and one writer) */ - if (port->busy == 2) - { - DEBUG(printk("Device is busy.. \n")); - return -EBUSY; - } - if (port->init_irqs) { - if (port->use_dma) { - if (port == &ports[0]){ -#ifdef SYNC_SER_DMA - if(request_irq(DMA4_INTR_VECT, - tr_interrupt, - 0, - "synchronous serial 0 dma tr", - &ports[0])) { - printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ"); - return -EBUSY; - } else if(request_irq(DMA5_INTR_VECT, - rx_interrupt, - 0, - "synchronous serial 1 dma rx", - &ports[0])) { - free_irq(DMA4_INTR_VECT, &port[0]); - printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ"); - return -EBUSY; - } else if (crisv32_request_dma(SYNC_SER0_TX_DMA_NBR, - "synchronous serial 0 dma tr", - DMA_VERBOSE_ON_ERROR, - 0, - dma_sser0)) { - free_irq(DMA4_INTR_VECT, &port[0]); - free_irq(DMA5_INTR_VECT, &port[0]); - printk(KERN_CRIT "Can't allocate sync serial port 0 TX DMA channel"); - return -EBUSY; - } else if (crisv32_request_dma(SYNC_SER0_RX_DMA_NBR, - "synchronous serial 0 dma rec", - DMA_VERBOSE_ON_ERROR, - 0, - dma_sser0)) { - crisv32_free_dma(SYNC_SER0_TX_DMA_NBR); - free_irq(DMA4_INTR_VECT, &port[0]); - free_irq(DMA5_INTR_VECT, &port[0]); - printk(KERN_CRIT "Can't allocate sync serial port 1 RX DMA channel"); - return -EBUSY; - } -#endif - } - else if (port == &ports[1]){ -#ifdef SYNC_SER_DMA - if (request_irq(DMA6_INTR_VECT, - tr_interrupt, - 0, - "synchronous serial 1 dma tr", - &ports[1])) { - printk(KERN_CRIT "Can't allocate sync serial port 1 IRQ"); - return -EBUSY; - } else if (request_irq(DMA7_INTR_VECT, - rx_interrupt, - 0, - "synchronous serial 1 dma rx", - &ports[1])) { - free_irq(DMA6_INTR_VECT, &ports[1]); - printk(KERN_CRIT "Can't allocate sync serial port 3 IRQ"); - return -EBUSY; - } else if (crisv32_request_dma(SYNC_SER1_TX_DMA_NBR, - "synchronous serial 1 dma tr", - DMA_VERBOSE_ON_ERROR, - 0, - dma_sser1)) { - free_irq(21, &ports[1]); - free_irq(20, &ports[1]); - printk(KERN_CRIT "Can't allocate sync serial port 3 TX DMA channel"); - return -EBUSY; - } else if (crisv32_request_dma(SYNC_SER1_RX_DMA_NBR, - "synchronous serial 3 dma rec", - DMA_VERBOSE_ON_ERROR, - 0, - dma_sser1)) { - crisv32_free_dma(SYNC_SER1_TX_DMA_NBR); - free_irq(DMA6_INTR_VECT, &ports[1]); - free_irq(DMA7_INTR_VECT, &ports[1]); - printk(KERN_CRIT "Can't allocate sync serial port 3 RX DMA channel"); - return -EBUSY; - } -#endif - } - - /* Enable DMAs */ - REG_WR(dma, port->regi_dmain, rw_cfg, cfg); - REG_WR(dma, port->regi_dmaout, rw_cfg, cfg); - /* Enable DMA IRQs */ - REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask); - REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask); - /* Set up wordsize = 2 for DMAs. */ - DMA_WR_CMD (port->regi_dmain, regk_dma_set_w_size1); - DMA_WR_CMD (port->regi_dmaout, regk_dma_set_w_size1); - - start_dma_in(port); - port->init_irqs = 0; - } else { /* !port->use_dma */ -#ifdef SYNC_SER_MANUAL - if (port == &ports[0]) { - if (request_irq(SSER0_INTR_VECT, - manual_interrupt, - 0, - "synchronous serial manual irq", - &ports[0])) { - printk("Can't allocate sync serial manual irq"); - return -EBUSY; - } - } else if (port == &ports[1]) { - if (request_irq(SSER1_INTR_VECT, - manual_interrupt, - 0, - "synchronous serial manual irq", - &ports[1])) { - printk(KERN_CRIT "Can't allocate sync serial manual irq"); - return -EBUSY; - } - } - port->init_irqs = 0; -#else - panic("sync_serial: Manual mode not supported.\n"); -#endif /* SYNC_SER_MANUAL */ - } - } /* port->init_irqs */ - - port->busy++; - return 0; -} - -static int sync_serial_release(struct inode *inode, struct file *file) -{ - int dev = MINOR(inode->i_rdev); - sync_port* port; - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) - { - DEBUG(printk("Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - if (port->busy) - port->busy--; - if (!port->busy) - /* XXX */ ; - return 0; -} - -static unsigned int sync_serial_poll(struct file *file, poll_table *wait) -{ - int dev = MINOR(file->f_dentry->d_inode->i_rdev); - unsigned int mask = 0; - sync_port* port; - DEBUGPOLL( static unsigned int prev_mask = 0; ); - - port = &ports[dev]; - poll_wait(file, &port->out_wait_q, wait); - poll_wait(file, &port->in_wait_q, wait); - /* Some room to write */ - if (port->out_count < OUT_BUFFER_SIZE) - mask |= POLLOUT | POLLWRNORM; - /* At least an inbufchunk of data */ - if (sync_data_avail(port) >= port->inbufchunk) - mask |= POLLIN | POLLRDNORM; - - DEBUGPOLL(if (mask != prev_mask) - printk("sync_serial_poll: mask 0x%08X %s %s\n", mask, - mask&POLLOUT?"POLLOUT":"", mask&POLLIN?"POLLIN":""); - prev_mask = mask; - ); - return mask; -} - -static int sync_serial_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) -{ - int return_val = 0; - int dev = MINOR(file->f_dentry->d_inode->i_rdev); - sync_port* port; - reg_sser_rw_tr_cfg tr_cfg; - reg_sser_rw_rec_cfg rec_cfg; - reg_sser_rw_frm_cfg frm_cfg; - reg_sser_rw_cfg gen_cfg; - reg_sser_rw_intr_mask intr_mask; - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) - { - DEBUG(printk("Invalid minor %d\n", dev)); - return -1; - } - port = &ports[dev]; - spin_lock_irq(&port->lock); - - tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); - rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); - frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg); - gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg); - intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); - - switch(cmd) - { - case SSP_SPEED: - if (GET_SPEED(arg) == CODEC) - { - gen_cfg.base_freq = regk_sser_f32; - /* FREQ = 0 => 4 MHz => clk_div = 7*/ - gen_cfg.clk_div = 6 + (1 << GET_FREQ(arg)); - } - else - { - gen_cfg.base_freq = regk_sser_f29_493; - switch (GET_SPEED(arg)) - { - case SSP150: - gen_cfg.clk_div = 29493000 / (150 * 8) - 1; - break; - case SSP300: - gen_cfg.clk_div = 29493000 / (300 * 8) - 1; - break; - case SSP600: - gen_cfg.clk_div = 29493000 / (600 * 8) - 1; - break; - case SSP1200: - gen_cfg.clk_div = 29493000 / (1200 * 8) - 1; - break; - case SSP2400: - gen_cfg.clk_div = 29493000 / (2400 * 8) - 1; - break; - case SSP4800: - gen_cfg.clk_div = 29493000 / (4800 * 8) - 1; - break; - case SSP9600: - gen_cfg.clk_div = 29493000 / (9600 * 8) - 1; - break; - case SSP19200: - gen_cfg.clk_div = 29493000 / (19200 * 8) - 1; - break; - case SSP28800: - gen_cfg.clk_div = 29493000 / (28800 * 8) - 1; - break; - case SSP57600: - gen_cfg.clk_div = 29493000 / (57600 * 8) - 1; - break; - case SSP115200: - gen_cfg.clk_div = 29493000 / (115200 * 8) - 1; - break; - case SSP230400: - gen_cfg.clk_div = 29493000 / (230400 * 8) - 1; - break; - case SSP460800: - gen_cfg.clk_div = 29493000 / (460800 * 8) - 1; - break; - case SSP921600: - gen_cfg.clk_div = 29493000 / (921600 * 8) - 1; - break; - case SSP3125000: - gen_cfg.base_freq = regk_sser_f100; - gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1; - break; - - } - } - frm_cfg.wordrate = GET_WORD_RATE(arg); - - break; - case SSP_MODE: - switch(arg) - { - case MASTER_OUTPUT: - port->output = 1; - port->input = 0; - gen_cfg.clk_dir = regk_sser_out; - break; - case SLAVE_OUTPUT: - port->output = 1; - port->input = 0; - gen_cfg.clk_dir = regk_sser_in; - break; - case MASTER_INPUT: - port->output = 0; - port->input = 1; - gen_cfg.clk_dir = regk_sser_out; - break; - case SLAVE_INPUT: - port->output = 0; - port->input = 1; - gen_cfg.clk_dir = regk_sser_in; - break; - case MASTER_BIDIR: - port->output = 1; - port->input = 1; - gen_cfg.clk_dir = regk_sser_out; - break; - case SLAVE_BIDIR: - port->output = 1; - port->input = 1; - gen_cfg.clk_dir = regk_sser_in; - break; - default: - spin_unlock_irq(&port->lock); - return -EINVAL; - - } - if (!port->use_dma || (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT)) - intr_mask.rdav = regk_sser_yes; - break; - case SSP_FRAME_SYNC: - if (arg & NORMAL_SYNC) - frm_cfg.tr_delay = 1; - else if (arg & EARLY_SYNC) - frm_cfg.tr_delay = 0; - - tr_cfg.bulk_wspace = frm_cfg.tr_delay; - frm_cfg.early_wend = regk_sser_yes; - if (arg & BIT_SYNC) - frm_cfg.type = regk_sser_edge; - else if (arg & WORD_SYNC) - frm_cfg.type = regk_sser_level; - else if (arg & EXTENDED_SYNC) - frm_cfg.early_wend = regk_sser_no; - - if (arg & SYNC_ON) - frm_cfg.frame_pin_use = regk_sser_frm; - else if (arg & SYNC_OFF) - frm_cfg.frame_pin_use = regk_sser_gio0; - - if (arg & WORD_SIZE_8) - rec_cfg.sample_size = tr_cfg.sample_size = 7; - else if (arg & WORD_SIZE_12) - rec_cfg.sample_size = tr_cfg.sample_size = 11; - else if (arg & WORD_SIZE_16) - rec_cfg.sample_size = tr_cfg.sample_size = 15; - else if (arg & WORD_SIZE_24) - rec_cfg.sample_size = tr_cfg.sample_size = 23; - else if (arg & WORD_SIZE_32) - rec_cfg.sample_size = tr_cfg.sample_size = 31; - - if (arg & BIT_ORDER_MSB) - rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst; - else if (arg & BIT_ORDER_LSB) - rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_lsbfirst; - - if (arg & FLOW_CONTROL_ENABLE) - rec_cfg.fifo_thr = regk_sser_thr16; - else if (arg & FLOW_CONTROL_DISABLE) - rec_cfg.fifo_thr = regk_sser_inf; - - if (arg & CLOCK_NOT_GATED) - gen_cfg.gate_clk = regk_sser_no; - else if (arg & CLOCK_GATED) - gen_cfg.gate_clk = regk_sser_yes; - - break; - case SSP_IPOLARITY: - /* NOTE!! negedge is considered NORMAL */ - if (arg & CLOCK_NORMAL) - rec_cfg.clk_pol = regk_sser_neg; - else if (arg & CLOCK_INVERT) - rec_cfg.clk_pol = regk_sser_pos; - - if (arg & FRAME_NORMAL) - frm_cfg.level = regk_sser_pos_hi; - else if (arg & FRAME_INVERT) - frm_cfg.level = regk_sser_neg_lo; - - if (arg & STATUS_NORMAL) - gen_cfg.hold_pol = regk_sser_pos; - else if (arg & STATUS_INVERT) - gen_cfg.hold_pol = regk_sser_neg; - break; - case SSP_OPOLARITY: - if (arg & CLOCK_NORMAL) - gen_cfg.out_clk_pol = regk_sser_neg; - else if (arg & CLOCK_INVERT) - gen_cfg.out_clk_pol = regk_sser_pos; - - if (arg & FRAME_NORMAL) - frm_cfg.level = regk_sser_pos_hi; - else if (arg & FRAME_INVERT) - frm_cfg.level = regk_sser_neg_lo; - - if (arg & STATUS_NORMAL) - gen_cfg.hold_pol = regk_sser_pos; - else if (arg & STATUS_INVERT) - gen_cfg.hold_pol = regk_sser_neg; - break; - case SSP_SPI: - rec_cfg.fifo_thr = regk_sser_inf; - rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst; - rec_cfg.sample_size = tr_cfg.sample_size = 7; - frm_cfg.frame_pin_use = regk_sser_frm; - frm_cfg.type = regk_sser_level; - frm_cfg.tr_delay = 1; - frm_cfg.level = regk_sser_neg_lo; - if (arg & SPI_SLAVE) - { - rec_cfg.clk_pol = regk_sser_neg; - gen_cfg.clk_dir = regk_sser_in; - port->input = 1; - port->output = 0; - } - else - { - gen_cfg.out_clk_pol = regk_sser_pos; - port->input = 0; - port->output = 1; - gen_cfg.clk_dir = regk_sser_out; - } - break; - case SSP_INBUFCHUNK: - break; - default: - return_val = -1; - } - - - if (port->started) - { - tr_cfg.tr_en = port->output; - rec_cfg.rec_en = port->input; - } - - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); - REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); - REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); - REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); - - spin_unlock_irq(&port->lock); - return return_val; -} - -static ssize_t sync_serial_write(struct file * file, const char * buf, - size_t count, loff_t *ppos) -{ - int dev = MINOR(file->f_dentry->d_inode->i_rdev); - DECLARE_WAITQUEUE(wait, current); - sync_port *port; - unsigned long c, c1; - unsigned long free_outp; - unsigned long outp; - unsigned long out_buffer; - unsigned long flags; - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) - { - DEBUG(printk("Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - - DEBUGWRITE(printk("W d%d c %lu (%d/%d)\n", port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE)); - /* Space to end of buffer */ - /* - * out_buffer 012345<- c ->OUT_BUFFER_SIZE - * outp^ +out_count - ^free_outp - * out_buffer 45<- c ->0123OUT_BUFFER_SIZE - * +out_count outp^ - * free_outp - * - */ - - /* Read variables that may be updated by interrupts */ - spin_lock_irqsave(&port->lock, flags); - count = count > OUT_BUFFER_SIZE - port->out_count ? OUT_BUFFER_SIZE - port->out_count : count; - outp = (unsigned long)port->outp; - free_outp = outp + port->out_count; - spin_unlock_irqrestore(&port->lock, flags); - out_buffer = (unsigned long)port->out_buffer; - - /* Find out where and how much to write */ - if (free_outp >= out_buffer + OUT_BUFFER_SIZE) - free_outp -= OUT_BUFFER_SIZE; - if (free_outp >= outp) - c = out_buffer + OUT_BUFFER_SIZE - free_outp; - else - c = outp - free_outp; - if (c > count) - c = count; - -// DEBUGWRITE(printk("w op %08lX fop %08lX c %lu\n", outp, free_outp, c)); - if (copy_from_user((void*)free_outp, buf, c)) - return -EFAULT; - - if (c != count) { - buf += c; - c1 = count - c; - DEBUGWRITE(printk("w2 fi %lu c %lu c1 %lu\n", free_outp-out_buffer, c, c1)); - if (copy_from_user((void*)out_buffer, buf, c1)) - return -EFAULT; - } - spin_lock_irqsave(&port->lock, flags); - port->out_count += count; - spin_unlock_irqrestore(&port->lock, flags); - - /* Make sure transmitter/receiver is running */ - if (!port->started) - { - reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); - reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); - reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); - cfg.en = regk_sser_yes; - tr_cfg.tr_en = port->output; - rec_cfg.rec_en = port->input; - REG_WR(sser, port->regi_sser, rw_cfg, cfg); - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); - port->started = 1; - } - - if (file->f_flags & O_NONBLOCK) { - spin_lock_irqsave(&port->lock, flags); - if (!port->tr_running) { - if (!port->use_dma) { - reg_sser_rw_intr_mask intr_mask; - intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); - /* Start sender by writing data */ - send_word(port); - /* and enable transmitter ready IRQ */ - intr_mask.trdy = 1; - REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); - } else { - start_dma(port, (unsigned char* volatile )port->outp, c); - } - } - spin_unlock_irqrestore(&port->lock, flags); - DEBUGWRITE(printk("w d%d c %lu NB\n", - port->port_nbr, count)); - return count; - } - - /* Sleep until all sent */ - - add_wait_queue(&port->out_wait_q, &wait); - set_current_state(TASK_INTERRUPTIBLE); - spin_lock_irqsave(&port->lock, flags); - if (!port->tr_running) { - if (!port->use_dma) { - reg_sser_rw_intr_mask intr_mask; - intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); - /* Start sender by writing data */ - send_word(port); - /* and enable transmitter ready IRQ */ - intr_mask.trdy = 1; - REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); - } else { - start_dma(port, port->outp, c); - } - } - spin_unlock_irqrestore(&port->lock, flags); - schedule(); - set_current_state(TASK_RUNNING); - remove_wait_queue(&port->out_wait_q, &wait); - if (signal_pending(current)) - { - return -EINTR; - } - DEBUGWRITE(printk("w d%d c %lu\n", port->port_nbr, count)); - return count; -} - -static ssize_t sync_serial_read(struct file * file, char * buf, - size_t count, loff_t *ppos) -{ - int dev = MINOR(file->f_dentry->d_inode->i_rdev); - int avail; - sync_port *port; - unsigned char* start; - unsigned char* end; - unsigned long flags; - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) - { - DEBUG(printk("Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - - DEBUGREAD(printk("R%d c %d ri %lu wi %lu /%lu\n", dev, count, port->readp - port->flip, port->writep - port->flip, port->in_buffer_size)); - - if (!port->started) - { - reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); - reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); - reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); - cfg.en = regk_sser_yes; - tr_cfg.tr_en = regk_sser_yes; - rec_cfg.rec_en = regk_sser_yes; - REG_WR(sser, port->regi_sser, rw_cfg, cfg); - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); - port->started = 1; - } - - - /* Calculate number of available bytes */ - /* Save pointers to avoid that they are modified by interrupt */ - spin_lock_irqsave(&port->lock, flags); - start = (unsigned char*)port->readp; /* cast away volatile */ - end = (unsigned char*)port->writep; /* cast away volatile */ - spin_unlock_irqrestore(&port->lock, flags); - while ((start == end) && !port->full) /* No data */ - { - if (file->f_flags & O_NONBLOCK) - { - return -EAGAIN; - } - - interruptible_sleep_on(&port->in_wait_q); - if (signal_pending(current)) - { - return -EINTR; - } - spin_lock_irqsave(&port->lock, flags); - start = (unsigned char*)port->readp; /* cast away volatile */ - end = (unsigned char*)port->writep; /* cast away volatile */ - spin_unlock_irqrestore(&port->lock, flags); - } - - /* Lazy read, never return wrapped data. */ - if (port->full) - avail = port->in_buffer_size; - else if (end > start) - avail = end - start; - else - avail = port->flip + port->in_buffer_size - start; - - count = count > avail ? avail : count; - if (copy_to_user(buf, start, count)) - return -EFAULT; - /* Disable interrupts while updating readp */ - spin_lock_irqsave(&port->lock, flags); - port->readp += count; - if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */ - port->readp = port->flip; - port->full = 0; - spin_unlock_irqrestore(&port->lock, flags); - DEBUGREAD(printk("r %d\n", count)); - return count; -} - -static void send_word(sync_port* port) -{ - reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); - reg_sser_rw_tr_data tr_data = {0}; - - switch(tr_cfg.sample_size) - { - case 8: - port->out_count--; - tr_data.data = *port->outp++; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - break; - case 12: - { - int data = (*port->outp++) << 8; - data |= *port->outp++; - port->out_count-=2; - tr_data.data = data; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - } - break; - case 16: - port->out_count-=2; - tr_data.data = *(unsigned short *)port->outp; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - port->outp+=2; - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - break; - case 24: - port->out_count-=3; - tr_data.data = *(unsigned short *)port->outp; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - port->outp+=2; - tr_data.data = *port->outp++; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - break; - case 32: - port->out_count-=4; - tr_data.data = *(unsigned short *)port->outp; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - port->outp+=2; - tr_data.data = *(unsigned short *)port->outp; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - port->outp+=2; - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - break; - } -} - - -static void start_dma(struct sync_port* port, const char* data, int count) -{ - port->tr_running = 1; - port->out_descr.buf = (char*)virt_to_phys((char*)data); - port->out_descr.after = port->out_descr.buf + count; - port->out_descr.eol = port->out_descr.intr = 1; - - port->out_context.saved_data = (dma_descr_data*)virt_to_phys(&port->out_descr); - port->out_context.saved_data_buf = port->out_descr.buf; - - DMA_START_CONTEXT(port->regi_dmaout, virt_to_phys((char*)&port->out_context)); - DEBUGTXINT(printk("dma %08lX c %d\n", (unsigned long)data, count)); -} - -static void start_dma_in(sync_port* port) -{ - int i; - char* buf; - port->writep = port->flip; - - if (port->writep > port->flip + port->in_buffer_size) - { - panic("Offset too large in sync serial driver\n"); - return; - } - buf = (char*)virt_to_phys(port->in_buffer); - for (i = 0; i < NUM_IN_DESCR; i++) { - port->in_descr[i].buf = buf; - port->in_descr[i].after = buf + port->inbufchunk; - port->in_descr[i].intr = 1; - port->in_descr[i].next = (dma_descr_data*)virt_to_phys(&port->in_descr[i+1]); - port->in_descr[i].buf = buf; - buf += port->inbufchunk; - } - /* Link the last descriptor to the first */ - port->in_descr[i-1].next = (dma_descr_data*)virt_to_phys(&port->in_descr[0]); - port->in_descr[i-1].eol = regk_sser_yes; - port->next_rx_desc = &port->in_descr[0]; - port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1]; - port->in_context.saved_data = (dma_descr_data*)virt_to_phys(&port->in_descr[0]); - port->in_context.saved_data_buf = port->in_descr[0].buf; - DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context)); -} - -#ifdef SYNC_SER_DMA -static irqreturn_t tr_interrupt(int irq, void *dev_id, struct pt_regs * regs) -{ - reg_dma_r_masked_intr masked; - reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes}; - int i; - struct dma_descr_data *descr; - unsigned int sentl; - int found = 0; - - for (i = 0; i < NUMBER_OF_PORTS; i++) - { - sync_port *port = &ports[i]; - if (!port->enabled || !port->use_dma ) - continue; - - masked = REG_RD(dma, port->regi_dmaout, r_masked_intr); - - if (masked.data) /* IRQ active for the port? */ - { - found = 1; - /* Clear IRQ */ - REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr); - descr = &port->out_descr; - sentl = descr->after - descr->buf; - port->out_count -= sentl; - port->outp += sentl; - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - if (port->out_count) { - int c; - c = port->out_buffer + OUT_BUFFER_SIZE - port->outp; - if (c > port->out_count) - c = port->out_count; - DEBUGTXINT(printk("tx_int DMAWRITE %i %i\n", sentl, c)); - start_dma(port, port->outp, c); - } else { - DEBUGTXINT(printk("tx_int DMA stop %i\n", sentl)); - port->tr_running = 0; - } - wake_up_interruptible(&port->out_wait_q); /* wake up the waiting process */ - } - } - return IRQ_RETVAL(found); -} /* tr_interrupt */ - -static irqreturn_t rx_interrupt(int irq, void *dev_id, struct pt_regs * regs) -{ - reg_dma_r_masked_intr masked; - reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes}; - - int i; - int found = 0; - - for (i = 0; i < NUMBER_OF_PORTS; i++) - { - sync_port *port = &ports[i]; - - if (!port->enabled || !port->use_dma ) - continue; - - masked = REG_RD(dma, port->regi_dmain, r_masked_intr); - - if (masked.data) /* Descriptor interrupt */ - { - found = 1; - while (REG_RD(dma, port->regi_dmain, rw_data) != - virt_to_phys(port->next_rx_desc)) { - - if (port->writep + port->inbufchunk > port->flip + port->in_buffer_size) { - int first_size = port->flip + port->in_buffer_size - port->writep; - memcpy((char*)port->writep, phys_to_virt((unsigned)port->next_rx_desc->buf), first_size); - memcpy(port->flip, phys_to_virt((unsigned)port->next_rx_desc->buf+first_size), port->inbufchunk - first_size); - port->writep = port->flip + port->inbufchunk - first_size; - } else { - memcpy((char*)port->writep, - phys_to_virt((unsigned)port->next_rx_desc->buf), - port->inbufchunk); - port->writep += port->inbufchunk; - if (port->writep >= port->flip + port->in_buffer_size) - port->writep = port->flip; - } - if (port->writep == port->readp) - { - port->full = 1; - } - - port->next_rx_desc->eol = 0; - port->prev_rx_desc->eol = 1; - port->prev_rx_desc = phys_to_virt((unsigned)port->next_rx_desc); - port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next); - wake_up_interruptible(&port->in_wait_q); /* wake up the waiting process */ - DMA_CONTINUE(port->regi_dmain); - REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr); - - } - } - } - return IRQ_RETVAL(found); -} /* rx_interrupt */ -#endif /* SYNC_SER_DMA */ - -#ifdef SYNC_SER_MANUAL -static irqreturn_t manual_interrupt(int irq, void *dev_id, struct pt_regs * regs) -{ - int i; - int found = 0; - reg_sser_r_masked_intr masked; - - for (i = 0; i < NUMBER_OF_PORTS; i++) - { - sync_port* port = &ports[i]; - - if (!port->enabled || port->use_dma) - { - continue; - } - - masked = REG_RD(sser, port->regi_sser, r_masked_intr); - if (masked.rdav) /* Data received? */ - { - reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); - reg_sser_r_rec_data data = REG_RD(sser, port->regi_sser, r_rec_data); - found = 1; - /* Read data */ - switch(rec_cfg.sample_size) - { - case 8: - *port->writep++ = data.data & 0xff; - break; - case 12: - *port->writep = (data.data & 0x0ff0) >> 4; - *(port->writep + 1) = data.data & 0x0f; - port->writep+=2; - break; - case 16: - *(unsigned short*)port->writep = data.data; - port->writep+=2; - break; - case 24: - *(unsigned int*)port->writep = data.data; - port->writep+=3; - break; - case 32: - *(unsigned int*)port->writep = data.data; - port->writep+=4; - break; - } - - if (port->writep >= port->flip + port->in_buffer_size) /* Wrap? */ - port->writep = port->flip; - if (port->writep == port->readp) { - /* receive buffer overrun, discard oldest data - */ - port->readp++; - if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */ - port->readp = port->flip; - } - if (sync_data_avail(port) >= port->inbufchunk) - wake_up_interruptible(&port->in_wait_q); /* Wake up application */ - } - - if (masked.trdy) /* Transmitter ready? */ - { - found = 1; - if (port->out_count > 0) /* More data to send */ - send_word(port); - else /* transmission finished */ - { - reg_sser_rw_intr_mask intr_mask; - intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); - intr_mask.trdy = 0; - REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); - wake_up_interruptible(&port->out_wait_q); /* Wake up application */ - } - } - } - return IRQ_RETVAL(found); -} -#endif - -module_init(etrax_sync_serial_init); diff --git a/trunk/arch/cris/arch-v32/kernel/Makefile b/trunk/arch/cris/arch-v32/kernel/Makefile deleted file mode 100644 index 5d5b613cde8c..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# $Id: Makefile,v 1.11 2004/12/17 10:16:13 starvik Exp $ -# -# Makefile for the linux kernel. -# - -extra-y := head.o - - -obj-y := entry.o traps.o irq.o debugport.o dma.o pinmux.o \ - process.o ptrace.o setup.o signal.o traps.o time.o \ - arbiter.o io.o - -obj-$(CONFIG_ETRAXFS_SIM) += vcs_hook.o - -obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o -obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o -obj-$(CONFIG_MODULES) += crisksyms.o - -clean: - diff --git a/trunk/arch/cris/arch-v32/kernel/arbiter.c b/trunk/arch/cris/arch-v32/kernel/arbiter.c deleted file mode 100644 index 3870d2fd5160..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/arbiter.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Memory arbiter functions. Allocates bandwith through the - * arbiter and sets up arbiter breakpoints. - * - * The algorithm first assigns slots to the clients that has specified - * bandwith (e.g. ethernet) and then the remaining slots are divided - * on all the active clients. - * - * Copyright (c) 2004, 2005 Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct crisv32_watch_entry -{ - unsigned long instance; - watch_callback* cb; - unsigned long start; - unsigned long end; - int used; -}; - -#define NUMBER_OF_BP 4 -#define NBR_OF_CLIENTS 14 -#define NBR_OF_SLOTS 64 -#define SDRAM_BANDWIDTH 100000000 /* Some kind of expected value */ -#define INTMEM_BANDWIDTH 400000000 -#define NBR_OF_REGIONS 2 - -static struct crisv32_watch_entry watches[NUMBER_OF_BP] = -{ - {regi_marb_bp0}, - {regi_marb_bp1}, - {regi_marb_bp2}, - {regi_marb_bp3} -}; - -static int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS]; -static int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS]; -static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH}; - -DEFINE_SPINLOCK(arbiter_lock); - -static irqreturn_t -crisv32_arbiter_irq(int irq, void* dev_id, struct pt_regs* regs); - -static void crisv32_arbiter_config(int region) -{ - int slot; - int client; - int interval = 0; - int val[NBR_OF_SLOTS]; - - for (slot = 0; slot < NBR_OF_SLOTS; slot++) - val[slot] = NBR_OF_CLIENTS + 1; - - for (client = 0; client < NBR_OF_CLIENTS; client++) - { - int pos; - if (!requested_slots[region][client]) - continue; - interval = NBR_OF_SLOTS / requested_slots[region][client]; - pos = 0; - while (pos < NBR_OF_SLOTS) - { - if (val[pos] != NBR_OF_CLIENTS + 1) - pos++; - else - { - val[pos] = client; - pos += interval; - } - } - } - - client = 0; - for (slot = 0; slot < NBR_OF_SLOTS; slot++) - { - if (val[slot] == NBR_OF_CLIENTS + 1) - { - int first = client; - while(!active_clients[region][client]) { - client = (client + 1) % NBR_OF_CLIENTS; - if (client == first) - break; - } - val[slot] = client; - client = (client + 1) % NBR_OF_CLIENTS; - } - if (region == EXT_REGION) - REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot, val[slot]); - else if (region == INT_REGION) - REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot, val[slot]); - } -} - -extern char _stext, _etext; - -static void crisv32_arbiter_init(void) -{ - static int initialized = 0; - - if (initialized) - return; - - initialized = 1; - - /* CPU caches are active. */ - active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1; - crisv32_arbiter_config(EXT_REGION); - crisv32_arbiter_config(INT_REGION); - - if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, SA_INTERRUPT, - "arbiter", NULL)) - printk(KERN_ERR "Couldn't allocate arbiter IRQ\n"); - -#ifndef CONFIG_ETRAX_KGDB - /* Global watch for writes to kernel text segment. */ - crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext, - arbiter_all_clients, arbiter_all_write, NULL); -#endif -} - - - -int crisv32_arbiter_allocate_bandwith(int client, int region, - unsigned long bandwidth) -{ - int i; - int total_assigned = 0; - int total_clients = 0; - int req; - - crisv32_arbiter_init(); - - for (i = 0; i < NBR_OF_CLIENTS; i++) - { - total_assigned += requested_slots[region][i]; - total_clients += active_clients[region][i]; - } - req = NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth); - - if (total_assigned + total_clients + req + 1 > NBR_OF_SLOTS) - return -ENOMEM; - - active_clients[region][client] = 1; - requested_slots[region][client] = req; - crisv32_arbiter_config(region); - - return 0; -} - -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback* cb) -{ - int i; - - crisv32_arbiter_init(); - - if (start > 0x80000000) { - printk("Arbiter: %lX doesn't look like a physical address", start); - return -EFAULT; - } - - spin_lock(&arbiter_lock); - - for (i = 0; i < NUMBER_OF_BP; i++) { - if (!watches[i].used) { - reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask); - - watches[i].used = 1; - watches[i].start = start; - watches[i].end = start + size; - watches[i].cb = cb; - - REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr, watches[i].start); - REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr, watches[i].end); - REG_WR_INT(marb_bp, watches[i].instance, rw_op, accesses); - REG_WR_INT(marb_bp, watches[i].instance, rw_clients, clients); - - if (i == 0) - intr_mask.bp0 = regk_marb_yes; - else if (i == 1) - intr_mask.bp1 = regk_marb_yes; - else if (i == 2) - intr_mask.bp2 = regk_marb_yes; - else if (i == 3) - intr_mask.bp3 = regk_marb_yes; - - REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); - spin_unlock(&arbiter_lock); - - return i; - } - } - spin_unlock(&arbiter_lock); - return -ENOMEM; -} - -int crisv32_arbiter_unwatch(int id) -{ - reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask); - - crisv32_arbiter_init(); - - spin_lock(&arbiter_lock); - - if ((id < 0) || (id >= NUMBER_OF_BP) || (!watches[id].used)) { - spin_unlock(&arbiter_lock); - return -EINVAL; - } - - memset(&watches[id], 0, sizeof(struct crisv32_watch_entry)); - - if (id == 0) - intr_mask.bp0 = regk_marb_no; - else if (id == 1) - intr_mask.bp2 = regk_marb_no; - else if (id == 2) - intr_mask.bp2 = regk_marb_no; - else if (id == 3) - intr_mask.bp3 = regk_marb_no; - - REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); - - spin_unlock(&arbiter_lock); - return 0; -} - -extern void show_registers(struct pt_regs *regs); - -static irqreturn_t -crisv32_arbiter_irq(int irq, void* dev_id, struct pt_regs* regs) -{ - reg_marb_r_masked_intr masked_intr = REG_RD(marb, regi_marb, r_masked_intr); - reg_marb_bp_r_brk_clients r_clients; - reg_marb_bp_r_brk_addr r_addr; - reg_marb_bp_r_brk_op r_op; - reg_marb_bp_r_brk_first_client r_first; - reg_marb_bp_r_brk_size r_size; - reg_marb_bp_rw_ack ack = {0}; - reg_marb_rw_ack_intr ack_intr = {.bp0=1,.bp1=1,.bp2=1,.bp3=1}; - struct crisv32_watch_entry* watch; - - if (masked_intr.bp0) { - watch = &watches[0]; - ack_intr.bp0 = regk_marb_yes; - } else if (masked_intr.bp1) { - watch = &watches[1]; - ack_intr.bp1 = regk_marb_yes; - } else if (masked_intr.bp2) { - watch = &watches[2]; - ack_intr.bp2 = regk_marb_yes; - } else if (masked_intr.bp3) { - watch = &watches[3]; - ack_intr.bp3 = regk_marb_yes; - } else { - return IRQ_NONE; - } - - /* Retrieve all useful information and print it. */ - r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients); - r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr); - r_op = REG_RD(marb_bp, watch->instance, r_brk_op); - r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client); - r_size = REG_RD(marb_bp, watch->instance, r_brk_size); - - printk("Arbiter IRQ\n"); - printk("Clients %X addr %X op %X first %X size %X\n", - REG_TYPE_CONV(int, reg_marb_bp_r_brk_clients, r_clients), - REG_TYPE_CONV(int, reg_marb_bp_r_brk_addr, r_addr), - REG_TYPE_CONV(int, reg_marb_bp_r_brk_op, r_op), - REG_TYPE_CONV(int, reg_marb_bp_r_brk_first_client, r_first), - REG_TYPE_CONV(int, reg_marb_bp_r_brk_size, r_size)); - - REG_WR(marb_bp, watch->instance, rw_ack, ack); - REG_WR(marb, regi_marb, rw_ack_intr, ack_intr); - - printk("IRQ occured at %lX\n", regs->erp); - - if (watch->cb) - watch->cb(); - - - return IRQ_HANDLED; -} diff --git a/trunk/arch/cris/arch-v32/kernel/asm-offsets.c b/trunk/arch/cris/arch-v32/kernel/asm-offsets.c deleted file mode 100644 index 15b3d93a0496..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/asm-offsets.c +++ /dev/null @@ -1,49 +0,0 @@ -#include -#include - -/* - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed to extract - * and format the required data. - */ - -#define DEFINE(sym, val) \ - asm volatile("\n->" #sym " %0 " #val : : "i" (val)) - -#define BLANK() asm volatile("\n->" : : ) - -int main(void) -{ -#define ENTRY(entry) DEFINE(PT_ ## entry, offsetof(struct pt_regs, entry)) - ENTRY(orig_r10); - ENTRY(r13); - ENTRY(r12); - ENTRY(r11); - ENTRY(r10); - ENTRY(r9); - ENTRY(acr); - ENTRY(srs); - ENTRY(mof); - ENTRY(ccs); - ENTRY(srp); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry)) - ENTRY(task); - ENTRY(flags); - ENTRY(preempt_count); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(THREAD_ ## entry, offsetof(struct thread_struct, entry)) - ENTRY(ksp); - ENTRY(usp); - ENTRY(ccs); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(TASK_ ## entry, offsetof(struct task_struct, entry)) - ENTRY(pid); - BLANK(); - DEFINE(LCLONE_VM, CLONE_VM); - DEFINE(LCLONE_UNTRACED, CLONE_UNTRACED); - return 0; -} diff --git a/trunk/arch/cris/arch-v32/kernel/crisksyms.c b/trunk/arch/cris/arch-v32/kernel/crisksyms.c deleted file mode 100644 index 2c3bb9a0afe2..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/crisksyms.c +++ /dev/null @@ -1,24 +0,0 @@ -#include -#include -#include -#include -#include -#include - -/* Functions for allocating DMA channels */ -EXPORT_SYMBOL(crisv32_request_dma); -EXPORT_SYMBOL(crisv32_free_dma); - -/* Functions for handling internal RAM */ -EXPORT_SYMBOL(crisv32_intmem_alloc); -EXPORT_SYMBOL(crisv32_intmem_free); -EXPORT_SYMBOL(crisv32_intmem_phys_to_virt); -EXPORT_SYMBOL(crisv32_intmem_virt_to_phys); - -/* Functions for handling pinmux */ -EXPORT_SYMBOL(crisv32_pinmux_alloc); -EXPORT_SYMBOL(crisv32_pinmux_dealloc); - -/* Functions masking/unmasking interrupts */ -EXPORT_SYMBOL(mask_irq); -EXPORT_SYMBOL(unmask_irq); diff --git a/trunk/arch/cris/arch-v32/kernel/debugport.c b/trunk/arch/cris/arch-v32/kernel/debugport.c deleted file mode 100644 index ffc1ebf2dfee..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/debugport.c +++ /dev/null @@ -1,461 +0,0 @@ -/* - * Copyright (C) 2003, Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -struct dbg_port -{ - unsigned char nbr; - unsigned long instance; - unsigned int started; - unsigned long baudrate; - unsigned char parity; - unsigned int bits; -}; - -struct dbg_port ports[] = -{ - { - 0, - regi_ser0, - 0, - 115200, - 'N', - 8 - }, - { - 1, - regi_ser1, - 0, - 115200, - 'N', - 8 - }, - { - 2, - regi_ser2, - 0, - 115200, - 'N', - 8 - }, - { - 3, - regi_ser3, - 0, - 115200, - 'N', - 8 - } -}; -static struct dbg_port *port = -#if defined(CONFIG_ETRAX_DEBUG_PORT0) -&ports[0]; -#elif defined(CONFIG_ETRAX_DEBUG_PORT1) -&ports[1]; -#elif defined(CONFIG_ETRAX_DEBUG_PORT2) -&ports[2]; -#elif defined(CONFIG_ETRAX_DEBUG_PORT3) -&ports[3]; -#else -NULL; -#endif - -#ifdef CONFIG_ETRAX_KGDB -static struct dbg_port *kgdb_port = -#if defined(CONFIG_ETRAX_KGDB_PORT0) -&ports[0]; -#elif defined(CONFIG_ETRAX_KGDB_PORT1) -&ports[1]; -#elif defined(CONFIG_ETRAX_KGDB_PORT2) -&ports[2]; -#elif defined(CONFIG_ETRAX_KGDB_PORT3) -&ports[3]; -#else -NULL; -#endif -#endif - -#ifdef CONFIG_ETRAXFS_SIM -extern void print_str( const char *str ); -static char buffer[1024]; -static char msg[] = "Debug: "; -static int buffer_pos = sizeof(msg) - 1; -#endif - -extern struct tty_driver *serial_driver; - -static void -start_port(struct dbg_port* p) -{ - if (!p) - return; - - if (p->started) - return; - p->started = 1; - - if (p->nbr == 1) - crisv32_pinmux_alloc_fixed(pinmux_ser1); - else if (p->nbr == 2) - crisv32_pinmux_alloc_fixed(pinmux_ser2); - else if (p->nbr == 3) - crisv32_pinmux_alloc_fixed(pinmux_ser3); - - /* Set up serial port registers */ - reg_ser_rw_tr_ctrl tr_ctrl = {0}; - reg_ser_rw_tr_dma_en tr_dma_en = {0}; - - reg_ser_rw_rec_ctrl rec_ctrl = {0}; - reg_ser_rw_tr_baud_div tr_baud_div = {0}; - reg_ser_rw_rec_baud_div rec_baud_div = {0}; - - tr_ctrl.base_freq = rec_ctrl.base_freq = regk_ser_f29_493; - tr_dma_en.en = rec_ctrl.dma_mode = regk_ser_no; - tr_baud_div.div = rec_baud_div.div = 29493000 / p->baudrate / 8; - tr_ctrl.en = rec_ctrl.en = 1; - - if (p->parity == 'O') - { - tr_ctrl.par_en = regk_ser_yes; - tr_ctrl.par = regk_ser_odd; - rec_ctrl.par_en = regk_ser_yes; - rec_ctrl.par = regk_ser_odd; - } - else if (p->parity == 'E') - { - tr_ctrl.par_en = regk_ser_yes; - tr_ctrl.par = regk_ser_even; - rec_ctrl.par_en = regk_ser_yes; - rec_ctrl.par = regk_ser_odd; - } - - if (p->bits == 7) - { - tr_ctrl.data_bits = regk_ser_bits7; - rec_ctrl.data_bits = regk_ser_bits7; - } - - REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div); - REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div); - REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en); - REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl); - REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl); -} - -/* No debug */ -#ifdef CONFIG_ETRAX_DEBUG_PORT_NULL - -static void -console_write(struct console *co, const char *buf, unsigned int len) -{ - return; -} - -/* Target debug */ -#elif !defined(CONFIG_ETRAXFS_SIM) - -static void -console_write_direct(struct console *co, const char *buf, unsigned int len) -{ - int i; - reg_ser_r_stat_din stat; - reg_ser_rw_tr_dma_en tr_dma_en, old; - - /* Switch to manual mode */ - tr_dma_en = old = REG_RD (ser, port->instance, rw_tr_dma_en); - if (tr_dma_en.en == regk_ser_yes) { - tr_dma_en.en = regk_ser_no; - REG_WR(ser, port->instance, rw_tr_dma_en, tr_dma_en); - } - - /* Send data */ - for (i = 0; i < len; i++) { - /* LF -> CRLF */ - if (buf[i] == '\n') { - do { - stat = REG_RD (ser, port->instance, r_stat_din); - } while (!stat.tr_rdy); - REG_WR_INT (ser, port->instance, rw_dout, '\r'); - } - /* Wait until transmitter is ready and send.*/ - do { - stat = REG_RD (ser, port->instance, r_stat_din); - } while (!stat.tr_rdy); - REG_WR_INT (ser, port->instance, rw_dout, buf[i]); - } - - /* Restore mode */ - if (tr_dma_en.en != old.en) - REG_WR(ser, port->instance, rw_tr_dma_en, old); -} - -static void -console_write(struct console *co, const char *buf, unsigned int len) -{ - if (!port) - return; - console_write_direct(co, buf, len); -} - - - -#else - -/* VCS debug */ - -static void -console_write(struct console *co, const char *buf, unsigned int len) -{ - char* pos; - pos = memchr(buf, '\n', len); - if (pos) { - int l = ++pos - buf; - memcpy(buffer + buffer_pos, buf, l); - memcpy(buffer, msg, sizeof(msg) - 1); - buffer[buffer_pos + l] = '\0'; - print_str(buffer); - buffer_pos = sizeof(msg) - 1; - if (pos - buf != len) { - memcpy(buffer + buffer_pos, pos, len - l); - buffer_pos += len - l; - } - } else { - memcpy(buffer + buffer_pos, buf, len); - buffer_pos += len; - } -} - -#endif - -int raw_printk(const char *fmt, ...) -{ - static char buf[1024]; - int printed_len; - va_list args; - va_start(args, fmt); - printed_len = vsnprintf(buf, sizeof(buf), fmt, args); - va_end(args); - console_write(NULL, buf, strlen(buf)); - return printed_len; -} - -void -stupid_debug(char* buf) -{ - console_write(NULL, buf, strlen(buf)); -} - -#ifdef CONFIG_ETRAX_KGDB -/* Use polling to get a single character from the kernel debug port */ -int -getDebugChar(void) -{ - reg_ser_rs_status_data stat; - reg_ser_rw_ack_intr ack_intr = { 0 }; - - do { - stat = REG_RD(ser, kgdb_instance, rs_status_data); - } while (!stat.data_avail); - - /* Ack the data_avail interrupt. */ - ack_intr.data_avail = 1; - REG_WR(ser, kgdb_instance, rw_ack_intr, ack_intr); - - return stat.data; -} - -/* Use polling to put a single character to the kernel debug port */ -void -putDebugChar(int val) -{ - reg_ser_r_status_data stat; - do { - stat = REG_RD (ser, kgdb_instance, r_status_data); - } while (!stat.tr_ready); - REG_WR (ser, kgdb_instance, rw_data_out, REG_TYPE_CONV(reg_ser_rw_data_out, int, val)); -} -#endif /* CONFIG_ETRAX_KGDB */ - -static int __init -console_setup(struct console *co, char *options) -{ - char* s; - - if (options) { - port = &ports[co->index]; - port->baudrate = 115200; - port->parity = 'N'; - port->bits = 8; - port->baudrate = simple_strtoul(options, NULL, 10); - s = options; - while(*s >= '0' && *s <= '9') - s++; - if (*s) port->parity = *s++; - if (*s) port->bits = *s++ - '0'; - port->started = 0; - start_port(port); - } - return 0; -} - -/* This is a dummy serial device that throws away anything written to it. - * This is used when no debug output is wanted. - */ -static struct tty_driver dummy_driver; - -static int dummy_open(struct tty_struct *tty, struct file * filp) -{ - return 0; -} - -static void dummy_close(struct tty_struct *tty, struct file * filp) -{ -} - -static int dummy_write(struct tty_struct * tty, - const unsigned char *buf, int count) -{ - return count; -} - -static int -dummy_write_room(struct tty_struct *tty) -{ - return 8192; -} - -void __init -init_dummy_console(void) -{ - memset(&dummy_driver, 0, sizeof(struct tty_driver)); - dummy_driver.driver_name = "serial"; - dummy_driver.name = "ttyS"; - dummy_driver.major = TTY_MAJOR; - dummy_driver.minor_start = 68; - dummy_driver.num = 1; /* etrax100 has 4 serial ports */ - dummy_driver.type = TTY_DRIVER_TYPE_SERIAL; - dummy_driver.subtype = SERIAL_TYPE_NORMAL; - dummy_driver.init_termios = tty_std_termios; - dummy_driver.init_termios.c_cflag = - B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */ - dummy_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS; - - dummy_driver.open = dummy_open; - dummy_driver.close = dummy_close; - dummy_driver.write = dummy_write; - dummy_driver.write_room = dummy_write_room; - if (tty_register_driver(&dummy_driver)) - panic("Couldn't register dummy serial driver\n"); -} - -static struct tty_driver* -crisv32_console_device(struct console* co, int *index) -{ - if (port) - *index = port->nbr; - return port ? serial_driver : &dummy_driver; -} - -static struct console sercons = { - name : "ttyS", - write: console_write, - read : NULL, - device : crisv32_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : -1, - cflag : 0, - next : NULL -}; -static struct console sercons0 = { - name : "ttyS", - write: console_write, - read : NULL, - device : crisv32_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : 0, - cflag : 0, - next : NULL -}; - -static struct console sercons1 = { - name : "ttyS", - write: console_write, - read : NULL, - device : crisv32_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : 1, - cflag : 0, - next : NULL -}; -static struct console sercons2 = { - name : "ttyS", - write: console_write, - read : NULL, - device : crisv32_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : 2, - cflag : 0, - next : NULL -}; -static struct console sercons3 = { - name : "ttyS", - write: console_write, - read : NULL, - device : crisv32_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : 3, - cflag : 0, - next : NULL -}; - -/* Register console for printk's, etc. */ -int __init -init_etrax_debug(void) -{ - static int first = 1; - - if (!first) { - unregister_console(&sercons); - register_console(&sercons0); - register_console(&sercons1); - register_console(&sercons2); - register_console(&sercons3); - init_dummy_console(); - return 0; - } - first = 0; - register_console(&sercons); - start_port(port); - -#ifdef CONFIG_ETRAX_KGDB - start_port(kgdb_port); -#endif /* CONFIG_ETRAX_KGDB */ - return 0; -} - -__initcall(init_etrax_debug); diff --git a/trunk/arch/cris/arch-v32/kernel/dma.c b/trunk/arch/cris/arch-v32/kernel/dma.c deleted file mode 100644 index b92e85799b44..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/dma.c +++ /dev/null @@ -1,224 +0,0 @@ -/* Wrapper for DMA channel allocator that starts clocks etc */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static char used_dma_channels[MAX_DMA_CHANNELS]; -static const char * used_dma_channels_users[MAX_DMA_CHANNELS]; - -static DEFINE_SPINLOCK(dma_lock); - -int crisv32_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, unsigned int bandwidth, - enum dma_owner owner) -{ - unsigned long flags; - reg_config_rw_clk_ctrl clk_ctrl; - reg_strmux_rw_cfg strmux_cfg; - - if (crisv32_arbiter_allocate_bandwith(dmanr, - options & DMA_INT_MEM ? INT_REGION : EXT_REGION, - bandwidth)) - return -ENOMEM; - - spin_lock_irqsave(&dma_lock, flags); - - if (used_dma_channels[dmanr]) { - spin_unlock_irqrestore(&dma_lock, flags); - if (options & DMA_VERBOSE_ON_ERROR) { - printk("Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]); - } - if (options & DMA_PANIC_ON_ERROR) - panic("request_dma error!"); - return -EBUSY; - } - clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); - strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg); - - switch(dmanr) - { - case 0: - case 1: - clk_ctrl.dma01_eth0 = 1; - break; - case 2: - case 3: - clk_ctrl.dma23 = 1; - break; - case 4: - case 5: - clk_ctrl.dma45 = 1; - break; - case 6: - case 7: - clk_ctrl.dma67 = 1; - break; - case 8: - case 9: - clk_ctrl.dma89_strcop = 1; - break; -#if MAX_DMA_CHANNELS-1 != 9 -#error Check dma.c -#endif - default: - spin_unlock_irqrestore(&dma_lock, flags); - if (options & DMA_VERBOSE_ON_ERROR) { - printk("Failed to request DMA %i for %s, only 0-%i valid)\n", dmanr, device_id, MAX_DMA_CHANNELS-1); - } - - if (options & DMA_PANIC_ON_ERROR) - panic("request_dma error!"); - return -EINVAL; - } - - switch(owner) - { - case dma_eth0: - if (dmanr == 0) - strmux_cfg.dma0 = regk_strmux_eth0; - else if (dmanr == 1) - strmux_cfg.dma1 = regk_strmux_eth0; - else - panic("Invalid DMA channel for eth0\n"); - break; - case dma_eth1: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_eth1; - else if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_eth1; - else - panic("Invalid DMA channel for eth1\n"); - break; - case dma_iop0: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_iop0; - else if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_iop0; - else - panic("Invalid DMA channel for iop0\n"); - break; - case dma_iop1: - if (dmanr == 4) - strmux_cfg.dma4 = regk_strmux_iop1; - else if (dmanr == 5) - strmux_cfg.dma5 = regk_strmux_iop1; - else - panic("Invalid DMA channel for iop1\n"); - break; - case dma_ser0: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_ser0; - else if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_ser0; - else - panic("Invalid DMA channel for ser0\n"); - break; - case dma_ser1: - if (dmanr == 4) - strmux_cfg.dma4 = regk_strmux_ser1; - else if (dmanr == 5) - strmux_cfg.dma5 = regk_strmux_ser1; - else - panic("Invalid DMA channel for ser1\n"); - break; - case dma_ser2: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_ser2; - else if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_ser2; - else - panic("Invalid DMA channel for ser2\n"); - break; - case dma_ser3: - if (dmanr == 8) - strmux_cfg.dma8 = regk_strmux_ser3; - else if (dmanr == 9) - strmux_cfg.dma9 = regk_strmux_ser3; - else - panic("Invalid DMA channel for ser3\n"); - break; - case dma_sser0: - if (dmanr == 4) - strmux_cfg.dma4 = regk_strmux_sser0; - else if (dmanr == 5) - strmux_cfg.dma5 = regk_strmux_sser0; - else - panic("Invalid DMA channel for sser0\n"); - break; - case dma_sser1: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_sser1; - else if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_sser1; - else - panic("Invalid DMA channel for sser1\n"); - break; - case dma_ata: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_ata; - else if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_ata; - else - panic("Invalid DMA channel for ata\n"); - break; - case dma_strp: - if (dmanr == 8) - strmux_cfg.dma8 = regk_strmux_strcop; - else if (dmanr == 9) - strmux_cfg.dma9 = regk_strmux_strcop; - else - panic("Invalid DMA channel for strp\n"); - break; - case dma_ext0: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_ext0; - else - panic("Invalid DMA channel for ext0\n"); - break; - case dma_ext1: - if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_ext1; - else - panic("Invalid DMA channel for ext1\n"); - break; - case dma_ext2: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_ext2; - else if (dmanr == 8) - strmux_cfg.dma8 = regk_strmux_ext2; - else - panic("Invalid DMA channel for ext2\n"); - break; - case dma_ext3: - if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_ext3; - else if (dmanr == 9) - strmux_cfg.dma9 = regk_strmux_ext2; - else - panic("Invalid DMA channel for ext2\n"); - break; - } - - used_dma_channels[dmanr] = 1; - used_dma_channels_users[dmanr] = device_id; - REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); - REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg); - spin_unlock_irqrestore(&dma_lock,flags); - return 0; -} - -void crisv32_free_dma(unsigned int dmanr) -{ - spin_lock(&dma_lock); - used_dma_channels[dmanr] = 0; - spin_unlock(&dma_lock); -} diff --git a/trunk/arch/cris/arch-v32/kernel/entry.S b/trunk/arch/cris/arch-v32/kernel/entry.S deleted file mode 100644 index a8ed55e5b403..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/entry.S +++ /dev/null @@ -1,820 +0,0 @@ -/* - * Copyright (C) 2000-2003 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * Tobias Anderberg (tobiasa@axis.com), CRISv32 port. - * - * Code for the system-call and fault low-level handling routines. - * - * NOTE: This code handles signal-recognition, which happens every time - * after a timer-interrupt and after each system call. - * - * Stack layout in 'ret_from_system_call': - * ptrace needs to have all regs on the stack. - * if the order here is changed, it needs to be - * updated in fork.c:copy_process, signal.c:do_signal, - * ptrace.c and ptrace.h - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - - ;; Exported functions. - .globl system_call - .globl ret_from_intr - .globl ret_from_fork - .globl resume - .globl multiple_interrupt - .globl nmi_interrupt - .globl spurious_interrupt - .globl do_sigtrap - .globl gdb_handle_exception - .globl sys_call_table - - ; Check if preemptive kernel scheduling should be done. -#ifdef CONFIG_PREEMPT -_resume_kernel: - di - ; Load current task struct. - movs.w -8192, $r0 ; THREAD_SIZE = 8192 - and.d $sp, $r0 - - addoq +TI_preempt_count, $r0, $acr - move.d [$acr], $r10 ; Preemption disabled? - bne _Rexit - nop - -_need_resched: - addoq +TI_flags, $r0, $acr - move.d [$acr], $r10 - btstq TIF_NEED_RESCHED, $r10 ; Check if need_resched is set. - bpl _Rexit - nop - - ; Do preemptive kernel scheduling. - jsr preempt_schedule_irq - nop - - ; Load new task struct. - movs.w -8192, $r0 ; THREAD_SIZE = 8192. - and.d $sp, $r0 - - ; One more time with new task. - ba _need_resched - nop -#else -#define _resume_kernel _Rexit -#endif - - ; Called at exit from fork. schedule_tail must be called to drop - ; spinlock if CONFIG_PREEMPT. -ret_from_fork: - jsr schedule_tail - nop - ba ret_from_sys_call - nop - -ret_from_intr: - ;; Check for resched if preemptive kernel, or if we're going back to - ;; user-mode. This test matches the user_regs(regs) macro. Don't simply - ;; test CCS since that doesn't necessarily reflect what mode we'll - ;; return into. - addoq +PT_ccs, $sp, $acr - move.d [$acr], $r0 - btstq 16, $r0 ; User-mode flag. - bpl _resume_kernel - - ; Note that di below is in delay slot. - -_resume_userspace: - di ; So need_resched and sigpending don't change. - - movs.w -8192, $r0 ; THREAD_SIZE == 8192 - and.d $sp, $r0 - - addoq +TI_flags, $r0, $acr ; current->work - move.d [$acr], $r10 - and.d _TIF_WORK_MASK, $r10 ; Work to be done on return? - bne _work_pending - nop - ba _Rexit - nop - - ;; The system_call is called by a BREAK instruction, which looks pretty - ;; much like any other exception. - ;; - ;; System calls can't be made from interrupts but we still stack ERP - ;; to have a complete stack frame. - ;; - ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12, - ;; r13,mof,srp - ;; - ;; This function looks on the _surface_ like spaghetti programming, but it's - ;; really designed so that the fast-path does not force cache-loading of - ;; non-used instructions. Only the non-common cases cause the outlined code - ;; to run.. - -system_call: - ;; Stack-frame similar to the irq heads, which is reversed in - ;; ret_from_sys_call. - subq 12, $sp ; Skip EXS, EDA. - move $erp, [$sp] - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $ccs, [$sp] - subq 4, $sp - ei ; Allow IRQs while handling system call - move $spc, [$sp] - subq 4, $sp - move $mof, [$sp] - subq 4, $sp - move $srs, [$sp] - subq 4, $sp - move.d $acr, [$sp] - subq 14*4, $sp ; Make room for R0-R13. - movem $r13, [$sp] ; Push R0-R13 - subq 4, $sp - move.d $r10, [$sp] ; Push orig_r10. - -; Set S-bit when kernel debugging to keep hardware breakpoints active. -#ifdef CONFIG_ETRAX_KGDB - move $ccs, $r0 - or.d (1<<9), $r0 - move $r0, $ccs -#endif - - movs.w -ENOSYS, $r0 - addoq +PT_r10, $sp, $acr - move.d $r0, [$acr] - - ;; Check if this process is syscall-traced. - movs.w -8192, $r0 ; THREAD_SIZE == 8192 - and.d $sp, $r0 - - addoq +TI_flags, $r0, $acr - move.d [$acr], $r0 - btstq TIF_SYSCALL_TRACE, $r0 - bmi _syscall_trace_entry - nop - -_syscall_traced: - ;; Check for sanity in the requested syscall number. - cmpu.w NR_syscalls, $r9 - bhs ret_from_sys_call - lslq 2, $r9 ; Multiply by 4, in the delay slot. - - ;; The location on the stack for the register structure is passed as a - ;; seventh argument. Some system calls need this. - move.d $sp, $r0 - subq 4, $sp - move.d $r0, [$sp] - - ;; The registers carrying parameters (R10-R13) are intact. The optional - ;; fifth and sixth parameters is in MOF and SRP respectivly. Put them - ;; back on the stack. - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $mof, [$sp] - - ;; Actually to the system call. - addo.d +sys_call_table, $r9, $acr - move.d [$acr], $acr - jsr $acr - nop - - addq 3*4, $sp ; Pop the mof, srp and regs parameters. - addoq +PT_r10, $sp, $acr - move.d $r10, [$acr] ; Save the return value. - - moveq 1, $r9 ; "Parameter" to ret_from_sys_call to - ; show it was a sys call. - - ;; Fall through into ret_from_sys_call to return. - -ret_from_sys_call: - ;; R9 is a parameter: - ;; >= 1 from syscall - ;; 0 from irq - - ;; Get the current task-struct pointer. - movs.w -8192, $r0 ; THREAD_SIZE == 8192 - and.d $sp, $r0 - - di ; Make sure need_resched and sigpending don't change. - - addoq +TI_flags, $r0, $acr - move.d [$acr], $r1 - and.d _TIF_ALLWORK_MASK, $r1 - bne _syscall_exit_work - nop - -_Rexit: - ;; This epilogue MUST match the prologues in multiple_interrupt, irq.h - ;; and ptregs.h. - addq 4, $sp ; Skip orig_r10. - movem [$sp+], $r13 ; Registers R0-R13. - move.d [$sp+], $acr - move [$sp], $srs - addq 4, $sp - move [$sp+], $mof - move [$sp+], $spc - move [$sp+], $ccs - move [$sp+], $srp - move [$sp+], $erp - addq 8, $sp ; Skip EXS, EDA. - jump $erp - rfe ; Restore condition code stack in delay-slot. - - ;; We get here after doing a syscall if extra work might need to be done - ;; perform syscall exit tracing if needed. - -_syscall_exit_work: - ;; R0 contains current at this point and irq's are disabled. - - addoq +TI_flags, $r0, $acr - move.d [$acr], $r1 - btstq TIF_SYSCALL_TRACE, $r1 - bpl _work_pending - nop - ei - move.d $r9, $r1 ; Preserve R9. - jsr do_syscall_trace - nop - move.d $r1, $r9 - ba _resume_userspace - nop - -_work_pending: - addoq +TI_flags, $r0, $acr - move.d [$acr], $r10 - btstq TIF_NEED_RESCHED, $r10 ; Need resched? - bpl _work_notifysig ; No, must be signal/notify. - nop - -_work_resched: - move.d $r9, $r1 ; Preserve R9. - jsr schedule - nop - move.d $r1, $r9 - di - - addoq +TI_flags, $r0, $acr - move.d [$acr], $r1 - and.d _TIF_WORK_MASK, $r1 ; Ignore sycall trace counter. - beq _Rexit - nop - btstq TIF_NEED_RESCHED, $r1 - bmi _work_resched ; current->work.need_resched. - nop - -_work_notifysig: - ;; Deal with pending signals and notify-resume requests. - - addoq +TI_flags, $r0, $acr - move.d [$acr], $r13 ; The thread_info_flags parameter. - move.d $r9, $r10 ; do_notify_resume syscall/irq param. - moveq 0, $r11 ; oldset param - 0 in this case. - move.d $sp, $r12 ; The regs param. - jsr do_notify_resume - nop - - ba _Rexit - nop - - ;; We get here as a sidetrack when we've entered a syscall with the - ;; trace-bit set. We need to call do_syscall_trace and then continue - ;; with the call. - -_syscall_trace_entry: - ;; PT_r10 in the frame contains -ENOSYS as required, at this point. - - jsr do_syscall_trace - nop - - ;; Now re-enter the syscall code to do the syscall itself. We need to - ;; restore R9 here to contain the wanted syscall, and the other - ;; parameter-bearing registers. - addoq +PT_r9, $sp, $acr - move.d [$acr], $r9 - addoq +PT_orig_r10, $sp, $acr - move.d [$acr], $r10 ; PT_r10 is already -ENOSYS. - addoq +PT_r11, $sp, $acr - move.d [$acr], $r11 - addoq +PT_r12, $sp, $acr - move.d [$acr], $r12 - addoq +PT_r13, $sp, $acr - move.d [$acr], $r13 - addoq +PT_mof, $sp, $acr - move [$acr], $mof - addoq +PT_srp, $sp, $acr - move [$acr], $srp - - ba _syscall_traced - nop - - ;; Resume performs the actual task-switching, by switching stack - ;; pointers. Input arguments are: - ;; - ;; R10 = prev - ;; R11 = next - ;; R12 = thread offset in task struct. - ;; - ;; Returns old current in R10. - -resume: - subq 4, $sp - move $srp, [$sp] ; Keep old/new PC on the stack. - add.d $r12, $r10 ; R10 = current tasks tss. - addoq +THREAD_ccs, $r10, $acr - move $ccs, [$acr] ; Save IRQ enable state. - di - - addoq +THREAD_usp, $r10, $acr - move $usp, [$acr] ; Save user-mode stackpointer. - - ;; See copy_thread for the reason why register R9 is saved. - subq 10*4, $sp - movem $r9, [$sp] ; Save non-scratch registers and R9. - - addoq +THREAD_ksp, $r10, $acr - move.d $sp, [$acr] ; Save kernel SP for old task. - - move.d $sp, $r10 ; Return last running task in R10. - and.d -8192, $r10 ; Get thread_info from stackpointer. - addoq +TI_task, $r10, $acr - move.d [$acr], $r10 ; Get task. - add.d $r12, $r11 ; Find the new tasks tss. - addoq +THREAD_ksp, $r11, $acr - move.d [$acr], $sp ; Switch to new stackframe. - movem [$sp+], $r9 ; Restore non-scratch registers and R9. - - addoq +THREAD_usp, $r11, $acr - move [$acr], $usp ; Restore user-mode stackpointer. - - addoq +THREAD_ccs, $r11, $acr - move [$acr], $ccs ; Restore IRQ enable status. - move.d [$sp+], $acr - jump $acr ; Restore PC. - nop - -nmi_interrupt: - -;; If we receive a watchdog interrupt while it is not expected, then set -;; up a canonical frame and dump register contents before dying. - - ;; This prologue MUST match the one in irq.h and the struct in ptregs.h! - subq 12, $sp ; Skip EXS, EDA. - move $nrp, [$sp] - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $ccs, [$sp] - subq 4, $sp - move $spc, [$sp] - subq 4, $sp - move $mof, [$sp] - subq 4, $sp - move $srs, [$sp] - subq 4, $sp - move.d $acr, [$sp] - subq 14*4, $sp ; Make room for R0-R13. - movem $r13, [$sp] ; Push R0-R13. - subq 4, $sp - move.d $r10, [$sp] ; Push orig_r10. - move.d REG_ADDR(intr_vect, regi_irq, r_nmi), $r0 - move.d [$r0], $r0 - btstq REG_BIT(intr_vect, r_nmi, watchdog), $r0 - bpl 1f - nop - jsr handle_watchdog_bite ; In time.c. - move.d $sp, $r10 ; Pointer to registers -1: btstq REG_BIT(intr_vect, r_nmi, ext), $r0 - bpl 1f - nop - jsr handle_nmi - move.d $sp, $r10 ; Pointer to registers -1: addq 4, $sp ; Skip orig_r10 - movem [$sp+], $r13 - move.d [$sp+], $acr - move [$sp], $srs - addq 4, $sp - move [$sp+], $mof - move [$sp+], $spc - move [$sp+], $ccs - move [$sp+], $srp - move [$sp+], $nrp - addq 8, $sp ; Skip EXS, EDA. - jump $nrp - rfn - - .comm cause_of_death, 4 ;; Don't declare this anywhere. - -spurious_interrupt: - di - jump hard_reset_now - nop - - ;; This handles the case when multiple interrupts arrive at the same - ;; time. Jump to the first set interrupt bit in a priotiry fashion. The - ;; hardware will call the unserved interrupts after the handler - ;; finishes. -multiple_interrupt: - ;; This prologue MUST match the one in irq.h and the struct in ptregs.h! - subq 12, $sp ; Skip EXS, EDA. - move $erp, [$sp] - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $ccs, [$sp] - subq 4, $sp - move $spc, [$sp] - subq 4, $sp - move $mof, [$sp] - subq 4, $sp - move $srs, [$sp] - subq 4, $sp - move.d $acr, [$sp] - subq 14*4, $sp ; Make room for R0-R13. - movem $r13, [$sp] ; Push R0-R13. - subq 4, $sp - move.d $r10, [$sp] ; Push orig_r10. - -; Set S-bit when kernel debugging to keep hardware breakpoints active. -#ifdef CONFIG_ETRAX_KGDB - move $ccs, $r0 - or.d (1<<9), $r0 - move $r0, $ccs -#endif - - jsr crisv32_do_multiple - move.d $sp, $r10 - jump ret_from_intr - nop - -do_sigtrap: - ;; Sigtraps the process that executed the BREAK instruction. Creates a - ;; frame that Rexit expects. - subq 4, $sp - move $eda, [$sp] - subq 4, $sp - move $exs, [$sp] - subq 4, $sp - move $erp, [$sp] - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $ccs, [$sp] - subq 4, $sp - move $spc, [$sp] - subq 4, $sp - move $mof, [$sp] - subq 4, $sp - move $srs, [$sp] - subq 4, $sp - move.d $acr, [$sp] - di ; Need to disable irq's at this point. - subq 14*4, $sp ; Make room for r0-r13. - movem $r13, [$sp] ; Push the r0-r13 registers. - subq 4, $sp - move.d $r10, [$sp] ; Push orig_r10. - - movs.w -8192, $r9 ; THREAD_SIZE == 8192 - and.d $sp, $r9 - - ;; thread_info as first parameter - move.d $r9, $r10 - moveq 5, $r11 ; SIGTRAP as second argument. - jsr ugdb_trap_user - nop - jump ret_from_intr ; Use the return routine for interrupts. - nop - -gdb_handle_exception: - subq 4, $sp - move.d $r0, [$sp] -#ifdef CONFIG_ETRAX_KGDB - move $ccs, $r0 ; U-flag not affected by previous insns. - btstq 16, $r0 ; Test the U-flag. - bmi _ugdb_handle_exception ; Go to user mode debugging. - nop ; Empty delay-slot (cannot pop R0 here). - ba kgdb_handle_exception ; Go to kernel debugging. - move.d [$sp+], $r0 ; Restore R0 in delay slot. -#endif - -_ugdb_handle_exception: - ba do_sigtrap ; SIGTRAP the offending process. - move.d [$sp+], $r0 ; Restore R0 in delay slot. - - .data - - .section .rodata,"a" -sys_call_table: - .long sys_restart_syscall ; 0 - old "setup()" system call, used - ; for restarting. - .long sys_exit - .long sys_fork - .long sys_read - .long sys_write - .long sys_open /* 5 */ - .long sys_close - .long sys_waitpid - .long sys_creat - .long sys_link - .long sys_unlink /* 10 */ - .long sys_execve - .long sys_chdir - .long sys_time - .long sys_mknod - .long sys_chmod /* 15 */ - .long sys_lchown16 - .long sys_ni_syscall /* old break syscall holder */ - .long sys_stat - .long sys_lseek - .long sys_getpid /* 20 */ - .long sys_mount - .long sys_oldumount - .long sys_setuid16 - .long sys_getuid16 - .long sys_stime /* 25 */ - .long sys_ptrace - .long sys_alarm - .long sys_fstat - .long sys_pause - .long sys_utime /* 30 */ - .long sys_ni_syscall /* old stty syscall holder */ - .long sys_ni_syscall /* old gtty syscall holder */ - .long sys_access - .long sys_nice - .long sys_ni_syscall /* 35 old ftime syscall holder */ - .long sys_sync - .long sys_kill - .long sys_rename - .long sys_mkdir - .long sys_rmdir /* 40 */ - .long sys_dup - .long sys_pipe - .long sys_times - .long sys_ni_syscall /* old prof syscall holder */ - .long sys_brk /* 45 */ - .long sys_setgid16 - .long sys_getgid16 - .long sys_signal - .long sys_geteuid16 - .long sys_getegid16 /* 50 */ - .long sys_acct - .long sys_umount /* recycled never used phys( */ - .long sys_ni_syscall /* old lock syscall holder */ - .long sys_ioctl - .long sys_fcntl /* 55 */ - .long sys_ni_syscall /* old mpx syscall holder */ - .long sys_setpgid - .long sys_ni_syscall /* old ulimit syscall holder */ - .long sys_ni_syscall /* old sys_olduname holder */ - .long sys_umask /* 60 */ - .long sys_chroot - .long sys_ustat - .long sys_dup2 - .long sys_getppid - .long sys_getpgrp /* 65 */ - .long sys_setsid - .long sys_sigaction - .long sys_sgetmask - .long sys_ssetmask - .long sys_setreuid16 /* 70 */ - .long sys_setregid16 - .long sys_sigsuspend - .long sys_sigpending - .long sys_sethostname - .long sys_setrlimit /* 75 */ - .long sys_old_getrlimit - .long sys_getrusage - .long sys_gettimeofday - .long sys_settimeofday - .long sys_getgroups16 /* 80 */ - .long sys_setgroups16 - .long sys_select /* was old_select in Linux/E100 */ - .long sys_symlink - .long sys_lstat - .long sys_readlink /* 85 */ - .long sys_uselib - .long sys_swapon - .long sys_reboot - .long old_readdir - .long old_mmap /* 90 */ - .long sys_munmap - .long sys_truncate - .long sys_ftruncate - .long sys_fchmod - .long sys_fchown16 /* 95 */ - .long sys_getpriority - .long sys_setpriority - .long sys_ni_syscall /* old profil syscall holder */ - .long sys_statfs - .long sys_fstatfs /* 100 */ - .long sys_ni_syscall /* sys_ioperm in i386 */ - .long sys_socketcall - .long sys_syslog - .long sys_setitimer - .long sys_getitimer /* 105 */ - .long sys_newstat - .long sys_newlstat - .long sys_newfstat - .long sys_ni_syscall /* old sys_uname holder */ - .long sys_ni_syscall /* sys_iopl in i386 */ - .long sys_vhangup - .long sys_ni_syscall /* old "idle" system call */ - .long sys_ni_syscall /* vm86old in i386 */ - .long sys_wait4 - .long sys_swapoff /* 115 */ - .long sys_sysinfo - .long sys_ipc - .long sys_fsync - .long sys_sigreturn - .long sys_clone /* 120 */ - .long sys_setdomainname - .long sys_newuname - .long sys_ni_syscall /* sys_modify_ldt */ - .long sys_adjtimex - .long sys_mprotect /* 125 */ - .long sys_sigprocmask - .long sys_ni_syscall /* old "create_module" */ - .long sys_init_module - .long sys_delete_module - .long sys_ni_syscall /* 130: old "get_kernel_syms" */ - .long sys_quotactl - .long sys_getpgid - .long sys_fchdir - .long sys_bdflush - .long sys_sysfs /* 135 */ - .long sys_personality - .long sys_ni_syscall /* for afs_syscall */ - .long sys_setfsuid16 - .long sys_setfsgid16 - .long sys_llseek /* 140 */ - .long sys_getdents - .long sys_select - .long sys_flock - .long sys_msync - .long sys_readv /* 145 */ - .long sys_writev - .long sys_getsid - .long sys_fdatasync - .long sys_sysctl - .long sys_mlock /* 150 */ - .long sys_munlock - .long sys_mlockall - .long sys_munlockall - .long sys_sched_setparam - .long sys_sched_getparam /* 155 */ - .long sys_sched_setscheduler - .long sys_sched_getscheduler - .long sys_sched_yield - .long sys_sched_get_priority_max - .long sys_sched_get_priority_min /* 160 */ - .long sys_sched_rr_get_interval - .long sys_nanosleep - .long sys_mremap - .long sys_setresuid16 - .long sys_getresuid16 /* 165 */ - .long sys_ni_syscall /* sys_vm86 */ - .long sys_ni_syscall /* Old sys_query_module */ - .long sys_poll - .long sys_nfsservctl - .long sys_setresgid16 /* 170 */ - .long sys_getresgid16 - .long sys_prctl - .long sys_rt_sigreturn - .long sys_rt_sigaction - .long sys_rt_sigprocmask /* 175 */ - .long sys_rt_sigpending - .long sys_rt_sigtimedwait - .long sys_rt_sigqueueinfo - .long sys_rt_sigsuspend - .long sys_pread64 /* 180 */ - .long sys_pwrite64 - .long sys_chown16 - .long sys_getcwd - .long sys_capget - .long sys_capset /* 185 */ - .long sys_sigaltstack - .long sys_sendfile - .long sys_ni_syscall /* streams1 */ - .long sys_ni_syscall /* streams2 */ - .long sys_vfork /* 190 */ - .long sys_getrlimit - .long sys_mmap2 - .long sys_truncate64 - .long sys_ftruncate64 - .long sys_stat64 /* 195 */ - .long sys_lstat64 - .long sys_fstat64 - .long sys_lchown - .long sys_getuid - .long sys_getgid /* 200 */ - .long sys_geteuid - .long sys_getegid - .long sys_setreuid - .long sys_setregid - .long sys_getgroups /* 205 */ - .long sys_setgroups - .long sys_fchown - .long sys_setresuid - .long sys_getresuid - .long sys_setresgid /* 210 */ - .long sys_getresgid - .long sys_chown - .long sys_setuid - .long sys_setgid - .long sys_setfsuid /* 215 */ - .long sys_setfsgid - .long sys_pivot_root - .long sys_mincore - .long sys_madvise - .long sys_getdents64 /* 220 */ - .long sys_fcntl64 - .long sys_ni_syscall /* reserved for TUX */ - .long sys_ni_syscall - .long sys_gettid - .long sys_readahead /* 225 */ - .long sys_setxattr - .long sys_lsetxattr - .long sys_fsetxattr - .long sys_getxattr - .long sys_lgetxattr /* 230 */ - .long sys_fgetxattr - .long sys_listxattr - .long sys_llistxattr - .long sys_flistxattr - .long sys_removexattr /* 235 */ - .long sys_lremovexattr - .long sys_fremovexattr - .long sys_tkill - .long sys_sendfile64 - .long sys_futex /* 240 */ - .long sys_sched_setaffinity - .long sys_sched_getaffinity - .long sys_ni_syscall /* sys_set_thread_area */ - .long sys_ni_syscall /* sys_get_thread_area */ - .long sys_io_setup /* 245 */ - .long sys_io_destroy - .long sys_io_getevents - .long sys_io_submit - .long sys_io_cancel - .long sys_fadvise64 /* 250 */ - .long sys_ni_syscall - .long sys_exit_group - .long sys_lookup_dcookie - .long sys_epoll_create - .long sys_epoll_ctl /* 255 */ - .long sys_epoll_wait - .long sys_remap_file_pages - .long sys_set_tid_address - .long sys_timer_create - .long sys_timer_settime /* 260 */ - .long sys_timer_gettime - .long sys_timer_getoverrun - .long sys_timer_delete - .long sys_clock_settime - .long sys_clock_gettime /* 265 */ - .long sys_clock_getres - .long sys_clock_nanosleep - .long sys_statfs64 - .long sys_fstatfs64 - .long sys_tgkill /* 270 */ - .long sys_utimes - .long sys_fadvise64_64 - .long sys_ni_syscall /* sys_vserver */ - .long sys_ni_syscall /* sys_mbind */ - .long sys_ni_syscall /* 275 sys_get_mempolicy */ - .long sys_ni_syscall /* sys_set_mempolicy */ - .long sys_mq_open - .long sys_mq_unlink - .long sys_mq_timedsend - .long sys_mq_timedreceive /* 280 */ - .long sys_mq_notify - .long sys_mq_getsetattr - .long sys_ni_syscall /* reserved for kexec */ - .long sys_waitid - - /* - * NOTE!! This doesn't have to be exact - we just have - * to make sure we have _enough_ of the "sys_ni_syscall" - * entries. Don't panic if you notice that this hasn't - * been shrunk every time we add a new system call. - */ - - .rept NR_syscalls - (.-sys_call_table) / 4 - .long sys_ni_syscall - .endr - diff --git a/trunk/arch/cris/arch-v32/kernel/fasttimer.c b/trunk/arch/cris/arch-v32/kernel/fasttimer.c deleted file mode 100644 index ea2b4a97c8c7..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/fasttimer.c +++ /dev/null @@ -1,996 +0,0 @@ -/* $Id: fasttimer.c,v 1.11 2005/01/04 11:15:46 starvik Exp $ - * linux/arch/cris/kernel/fasttimer.c - * - * Fast timers for ETRAX FS - * This may be useful in other OS than Linux so use 2 space indentation... - * - * $Log: fasttimer.c,v $ - * Revision 1.11 2005/01/04 11:15:46 starvik - * Don't share timer IRQ. - * - * Revision 1.10 2004/12/07 09:19:38 starvik - * Corrected includes. - * Use correct interrupt macros. - * - * Revision 1.9 2004/05/14 10:18:58 starvik - * Export fast_timer_list - * - * Revision 1.8 2004/05/14 07:58:03 starvik - * Merge of changes from 2.4 - * - * Revision 1.7 2003/07/10 12:06:14 starvik - * Return IRQ_NONE if irq wasn't handled - * - * Revision 1.6 2003/07/04 08:27:49 starvik - * Merge of Linux 2.5.74 - * - * Revision 1.5 2003/06/05 10:16:22 johana - * New INTR_VECT macros. - * - * Revision 1.4 2003/06/03 08:49:45 johana - * Fixed typo. - * - * Revision 1.3 2003/06/02 12:51:27 johana - * Now compiles. - * Commented some include files that probably can be removed. - * - * Revision 1.2 2003/06/02 12:09:41 johana - * Ported to ETRAX FS using the trig interrupt instead of timer1. - * - * Revision 1.3 2002/12/12 08:26:32 starvik - * Don't use C-comments inside CVS comments - * - * Revision 1.2 2002/12/11 15:42:02 starvik - * Extracted v10 (ETRAX 100LX) specific stuff from arch/cris/kernel/ - * - * Revision 1.1 2002/11/18 07:58:06 starvik - * Fast timers (from Linux 2.4) - * - * Revision 1.5 2002/10/15 06:21:39 starvik - * Added call to init_waitqueue_head - * - * Revision 1.4 2002/05/28 17:47:59 johana - * Added del_fast_timer() - * - * Revision 1.3 2002/05/28 16:16:07 johana - * Handle empty fast_timer_list - * - * Revision 1.2 2002/05/27 15:38:42 johana - * Made it compile without warnings on Linux 2.4. - * (includes, wait_queue, PROC_FS and snprintf) - * - * Revision 1.1 2002/05/27 15:32:25 johana - * arch/etrax100/kernel/fasttimer.c v1.8 from the elinux tree. - * - * Revision 1.8 2001/11/27 13:50:40 pkj - * Disable interrupts while stopping the timer and while modifying the - * list of active timers in timer1_handler() as it may be interrupted - * by other interrupts (e.g., the serial interrupt) which may add fast - * timers. - * - * Revision 1.7 2001/11/22 11:50:32 pkj - * * Only store information about the last 16 timers. - * * proc_fasttimer_read() now uses an allocated buffer, since it - * requires more space than just a page even for only writing the - * last 16 timers. The buffer is only allocated on request, so - * unless /proc/fasttimer is read, it is never allocated. - * * Renamed fast_timer_started to fast_timers_started to match - * fast_timers_added and fast_timers_expired. - * * Some clean-up. - * - * Revision 1.6 2000/12/13 14:02:08 johana - * Removed volatile for fast_timer_list - * - * Revision 1.5 2000/12/13 13:55:35 johana - * Added DEBUG_LOG, added som cli() and cleanup - * - * Revision 1.4 2000/12/05 13:48:50 johana - * Added range check when writing proc file, modified timer int handling - * - * Revision 1.3 2000/11/23 10:10:20 johana - * More debug/logging possibilities. - * Moved GET_JIFFIES_USEC() to timex.h and time.c - * - * Revision 1.2 2000/11/01 13:41:04 johana - * Clean up and bugfixes. - * Created new do_gettimeofday_fast() that gets a timeval struct - * with time based on jiffies and *R_TIMER0_DATA, uses a table - * for fast conversion of timer value to microseconds. - * (Much faster the standard do_gettimeofday() and we don't really - * wan't to use the true time - we wan't the "uptime" so timers don't screw up - * when we change the time. - * TODO: Add efficient support for continuous timers as well. - * - * Revision 1.1 2000/10/26 15:49:16 johana - * Added fasttimer, highresolution timers. - * - * Copyright (C) 2000,2001 2002, 2003 Axis Communications AB, Lund, Sweden - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -/* - * timer0 is running at 100MHz and generating jiffies timer ticks - * at 100 or 1000 HZ. - * fasttimer gives an API that gives timers that expire "between" the jiffies - * giving microsecond resolution (10 ns). - * fasttimer uses reg_timer_rw_trig register to get interrupt when - * r_time reaches a certain value. - */ - - -#define DEBUG_LOG_INCLUDED -#define FAST_TIMER_LOG -//#define FAST_TIMER_TEST - -#define FAST_TIMER_SANITY_CHECKS - -#ifdef FAST_TIMER_SANITY_CHECKS -#define SANITYCHECK(x) x -static int sanity_failed = 0; -#else -#define SANITYCHECK(x) -#endif - -#define D1(x) -#define D2(x) -#define DP(x) - -#define __INLINE__ inline - -static int fast_timer_running = 0; -static int fast_timers_added = 0; -static int fast_timers_started = 0; -static int fast_timers_expired = 0; -static int fast_timers_deleted = 0; -static int fast_timer_is_init = 0; -static int fast_timer_ints = 0; - -struct fast_timer *fast_timer_list = NULL; - -#ifdef DEBUG_LOG_INCLUDED -#define DEBUG_LOG_MAX 128 -static const char * debug_log_string[DEBUG_LOG_MAX]; -static unsigned long debug_log_value[DEBUG_LOG_MAX]; -static int debug_log_cnt = 0; -static int debug_log_cnt_wrapped = 0; - -#define DEBUG_LOG(string, value) \ -{ \ - unsigned long log_flags; \ - local_irq_save(log_flags); \ - debug_log_string[debug_log_cnt] = (string); \ - debug_log_value[debug_log_cnt] = (unsigned long)(value); \ - if (++debug_log_cnt >= DEBUG_LOG_MAX) \ - { \ - debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \ - debug_log_cnt_wrapped = 1; \ - } \ - local_irq_restore(log_flags); \ -} -#else -#define DEBUG_LOG(string, value) -#endif - - -#define NUM_TIMER_STATS 16 -#ifdef FAST_TIMER_LOG -struct fast_timer timer_added_log[NUM_TIMER_STATS]; -struct fast_timer timer_started_log[NUM_TIMER_STATS]; -struct fast_timer timer_expired_log[NUM_TIMER_STATS]; -#endif - -int timer_div_settings[NUM_TIMER_STATS]; -int timer_delay_settings[NUM_TIMER_STATS]; - - -static void -timer_trig_handler(void); - - - -/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */ -void __INLINE__ do_gettimeofday_fast(struct timeval *tv) -{ - unsigned long sec = jiffies; - unsigned long usec = GET_JIFFIES_USEC(); - - usec += (sec % HZ) * (1000000 / HZ); - sec = sec / HZ; - - if (usec > 1000000) - { - usec -= 1000000; - sec++; - } - tv->tv_sec = sec; - tv->tv_usec = usec; -} - -int __INLINE__ timeval_cmp(struct timeval *t0, struct timeval *t1) -{ - if (t0->tv_sec < t1->tv_sec) - { - return -1; - } - else if (t0->tv_sec > t1->tv_sec) - { - return 1; - } - if (t0->tv_usec < t1->tv_usec) - { - return -1; - } - else if (t0->tv_usec > t1->tv_usec) - { - return 1; - } - return 0; -} - -/* Called with ints off */ -void __INLINE__ start_timer_trig(unsigned long delay_us) -{ - reg_timer_rw_ack_intr ack_intr = { 0 }; - reg_timer_rw_intr_mask intr_mask; - reg_timer_rw_trig trig; - reg_timer_rw_trig_cfg trig_cfg = { 0 }; - reg_timer_r_time r_time; - - r_time = REG_RD(timer, regi_timer, r_time); - - D1(printk("start_timer_trig : %d us freq: %i div: %i\n", - delay_us, freq_index, div)); - /* Clear trig irq */ - intr_mask = REG_RD(timer, regi_timer, rw_intr_mask); - intr_mask.trig = 0; - REG_WR(timer, regi_timer, rw_intr_mask, intr_mask); - - /* Set timer values */ - /* r_time is 100MHz (10 ns resolution) */ - trig = r_time + delay_us*(1000/10); - - timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = trig; - timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us; - - /* Ack interrupt */ - ack_intr.trig = 1; - REG_WR(timer, regi_timer, rw_ack_intr, ack_intr); - - /* Start timer */ - REG_WR(timer, regi_timer, rw_trig, trig); - trig_cfg.tmr = regk_timer_time; - REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg); - - /* Check if we have already passed the trig time */ - r_time = REG_RD(timer, regi_timer, r_time); - if (r_time < trig) { - /* No, Enable trig irq */ - intr_mask = REG_RD(timer, regi_timer, rw_intr_mask); - intr_mask.trig = 1; - REG_WR(timer, regi_timer, rw_intr_mask, intr_mask); - fast_timers_started++; - fast_timer_running = 1; - } - else - { - /* We have passed the time, disable trig point, ack intr */ - trig_cfg.tmr = regk_timer_off; - REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg); - REG_WR(timer, regi_timer, rw_ack_intr, ack_intr); - /* call the int routine directly */ - timer_trig_handler(); - } - -} - -/* In version 1.4 this function takes 27 - 50 us */ -void start_one_shot_timer(struct fast_timer *t, - fast_timer_function_type *function, - unsigned long data, - unsigned long delay_us, - const char *name) -{ - unsigned long flags; - struct fast_timer *tmp; - - D1(printk("sft %s %d us\n", name, delay_us)); - - local_irq_save(flags); - - do_gettimeofday_fast(&t->tv_set); - tmp = fast_timer_list; - - SANITYCHECK({ /* Check so this is not in the list already... */ - while (tmp != NULL) - { - if (tmp == t) - { - printk("timer name: %s data: 0x%08lX already in list!\n", name, data); - sanity_failed++; - return; - } - else - { - tmp = tmp->next; - } - } - tmp = fast_timer_list; - }); - - t->delay_us = delay_us; - t->function = function; - t->data = data; - t->name = name; - - t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000; - t->tv_expires.tv_sec = t->tv_set.tv_sec + delay_us / 1000000; - if (t->tv_expires.tv_usec > 1000000) - { - t->tv_expires.tv_usec -= 1000000; - t->tv_expires.tv_sec++; - } -#ifdef FAST_TIMER_LOG - timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t; -#endif - fast_timers_added++; - - /* Check if this should timeout before anything else */ - if (tmp == NULL || timeval_cmp(&t->tv_expires, &tmp->tv_expires) < 0) - { - /* Put first in list and modify the timer value */ - t->prev = NULL; - t->next = fast_timer_list; - if (fast_timer_list) - { - fast_timer_list->prev = t; - } - fast_timer_list = t; -#ifdef FAST_TIMER_LOG - timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; -#endif - start_timer_trig(delay_us); - } else { - /* Put in correct place in list */ - while (tmp->next && - timeval_cmp(&t->tv_expires, &tmp->next->tv_expires) > 0) - { - tmp = tmp->next; - } - /* Insert t after tmp */ - t->prev = tmp; - t->next = tmp->next; - if (tmp->next) - { - tmp->next->prev = t; - } - tmp->next = t; - } - - D2(printk("start_one_shot_timer: %d us done\n", delay_us)); - - local_irq_restore(flags); -} /* start_one_shot_timer */ - -static inline int fast_timer_pending (const struct fast_timer * t) -{ - return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list); -} - -static inline int detach_fast_timer (struct fast_timer *t) -{ - struct fast_timer *next, *prev; - if (!fast_timer_pending(t)) - return 0; - next = t->next; - prev = t->prev; - if (next) - next->prev = prev; - if (prev) - prev->next = next; - else - fast_timer_list = next; - fast_timers_deleted++; - return 1; -} - -int del_fast_timer(struct fast_timer * t) -{ - unsigned long flags; - int ret; - - local_irq_save(flags); - ret = detach_fast_timer(t); - t->next = t->prev = NULL; - local_irq_restore(flags); - return ret; -} /* del_fast_timer */ - - -/* Interrupt routines or functions called in interrupt context */ - -/* Timer interrupt handler for trig interrupts */ - -static irqreturn_t -timer_trig_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - reg_timer_r_masked_intr masked_intr; - - /* Check if the timer interrupt is for us (a trig int) */ - masked_intr = REG_RD(timer, regi_timer, r_masked_intr); - if (!masked_intr.trig) - return IRQ_NONE; - timer_trig_handler(); - return IRQ_HANDLED; -} - -static void timer_trig_handler(void) -{ - reg_timer_rw_ack_intr ack_intr = { 0 }; - reg_timer_rw_intr_mask intr_mask; - reg_timer_rw_trig_cfg trig_cfg = { 0 }; - struct fast_timer *t; - unsigned long flags; - - local_irq_save(flags); - - /* Clear timer trig interrupt */ - intr_mask = REG_RD(timer, regi_timer, rw_intr_mask); - intr_mask.trig = 0; - REG_WR(timer, regi_timer, rw_intr_mask, intr_mask); - - /* First stop timer, then ack interrupt */ - /* Stop timer */ - trig_cfg.tmr = regk_timer_off; - REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg); - - /* Ack interrupt */ - ack_intr.trig = 1; - REG_WR(timer, regi_timer, rw_ack_intr, ack_intr); - - fast_timer_running = 0; - fast_timer_ints++; - - local_irq_restore(flags); - - t = fast_timer_list; - while (t) - { - struct timeval tv; - - /* Has it really expired? */ - do_gettimeofday_fast(&tv); - D1(printk("t: %is %06ius\n", tv.tv_sec, tv.tv_usec)); - - if (timeval_cmp(&t->tv_expires, &tv) <= 0) - { - /* Yes it has expired */ -#ifdef FAST_TIMER_LOG - timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t; -#endif - fast_timers_expired++; - - /* Remove this timer before call, since it may reuse the timer */ - local_irq_save(flags); - if (t->prev) - { - t->prev->next = t->next; - } - else - { - fast_timer_list = t->next; - } - if (t->next) - { - t->next->prev = t->prev; - } - t->prev = NULL; - t->next = NULL; - local_irq_restore(flags); - - if (t->function != NULL) - { - t->function(t->data); - } - else - { - DEBUG_LOG("!trimertrig %i function==NULL!\n", fast_timer_ints); - } - } - else - { - /* Timer is to early, let's set it again using the normal routines */ - D1(printk(".\n")); - } - - local_irq_save(flags); - if ((t = fast_timer_list) != NULL) - { - /* Start next timer.. */ - long us; - struct timeval tv; - - do_gettimeofday_fast(&tv); - us = ((t->tv_expires.tv_sec - tv.tv_sec) * 1000000 + - t->tv_expires.tv_usec - tv.tv_usec); - if (us > 0) - { - if (!fast_timer_running) - { -#ifdef FAST_TIMER_LOG - timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; -#endif - start_timer_trig(us); - } - local_irq_restore(flags); - break; - } - else - { - /* Timer already expired, let's handle it better late than never. - * The normal loop handles it - */ - D1(printk("e! %d\n", us)); - } - } - local_irq_restore(flags); - } - - if (!t) - { - D1(printk("ttrig stop!\n")); - } -} - -static void wake_up_func(unsigned long data) -{ -#ifdef DECLARE_WAITQUEUE - wait_queue_head_t *sleep_wait_p = (wait_queue_head_t*)data; -#else - struct wait_queue **sleep_wait_p = (struct wait_queue **)data; -#endif - wake_up(sleep_wait_p); -} - - -/* Useful API */ - -void schedule_usleep(unsigned long us) -{ - struct fast_timer t; -#ifdef DECLARE_WAITQUEUE - wait_queue_head_t sleep_wait; - init_waitqueue_head(&sleep_wait); - { - DECLARE_WAITQUEUE(wait, current); -#else - struct wait_queue *sleep_wait = NULL; - struct wait_queue wait = { current, NULL }; -#endif - - D1(printk("schedule_usleep(%d)\n", us)); - add_wait_queue(&sleep_wait, &wait); - set_current_state(TASK_INTERRUPTIBLE); - start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us, - "usleep"); - schedule(); - set_current_state(TASK_RUNNING); - remove_wait_queue(&sleep_wait, &wait); - D1(printk("done schedule_usleep(%d)\n", us)); -#ifdef DECLARE_WAITQUEUE - } -#endif -} - -#ifdef CONFIG_PROC_FS -static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) - ,int *eof, void *data_unused -#else - ,int unused -#endif - ); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) -static struct proc_dir_entry *fasttimer_proc_entry; -#else -static struct proc_dir_entry fasttimer_proc_entry = -{ - 0, 9, "fasttimer", - S_IFREG | S_IRUGO, 1, 0, 0, - 0, NULL /* ops -- default to array */, - &proc_fasttimer_read /* get_info */, -}; -#endif -#endif /* CONFIG_PROC_FS */ - -#ifdef CONFIG_PROC_FS - -/* This value is very much based on testing */ -#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300) - -static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) - ,int *eof, void *data_unused -#else - ,int unused -#endif - ) -{ - unsigned long flags; - int i = 0; - int num_to_show; - struct timeval tv; - struct fast_timer *t, *nextt; - static char *bigbuf = NULL; - static unsigned long used; - - if (!bigbuf && !(bigbuf = vmalloc(BIG_BUF_SIZE))) - { - used = 0; - bigbuf[0] = '\0'; - return 0; - } - - if (!offset || !used) - { - do_gettimeofday_fast(&tv); - - used = 0; - used += sprintf(bigbuf + used, "Fast timers added: %i\n", - fast_timers_added); - used += sprintf(bigbuf + used, "Fast timers started: %i\n", - fast_timers_started); - used += sprintf(bigbuf + used, "Fast timer interrupts: %i\n", - fast_timer_ints); - used += sprintf(bigbuf + used, "Fast timers expired: %i\n", - fast_timers_expired); - used += sprintf(bigbuf + used, "Fast timers deleted: %i\n", - fast_timers_deleted); - used += sprintf(bigbuf + used, "Fast timer running: %s\n", - fast_timer_running ? "yes" : "no"); - used += sprintf(bigbuf + used, "Current time: %lu.%06lu\n", - (unsigned long)tv.tv_sec, - (unsigned long)tv.tv_usec); -#ifdef FAST_TIMER_SANITY_CHECKS - used += sprintf(bigbuf + used, "Sanity failed: %i\n", - sanity_failed); -#endif - used += sprintf(bigbuf + used, "\n"); - -#ifdef DEBUG_LOG_INCLUDED - { - int end_i = debug_log_cnt; - i = 0; - - if (debug_log_cnt_wrapped) - { - i = debug_log_cnt; - } - - while ((i != end_i || (debug_log_cnt_wrapped && !used)) && - used+100 < BIG_BUF_SIZE) - { - used += sprintf(bigbuf + used, debug_log_string[i], - debug_log_value[i]); - i = (i+1) % DEBUG_LOG_MAX; - } - } - used += sprintf(bigbuf + used, "\n"); -#endif - - num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started: - NUM_TIMER_STATS); - used += sprintf(bigbuf + used, "Timers started: %i\n", fast_timers_started); - for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE) ; i++) - { - int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS; - -#if 1 //ndef FAST_TIMER_LOG - used += sprintf(bigbuf + used, "div: %i delay: %i" - "\n", - timer_div_settings[cur], - timer_delay_settings[cur] - ); -#endif -#ifdef FAST_TIMER_LOG - t = &timer_started_log[cur]; - used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu " - "d: %6li us data: 0x%08lX" - "\n", - t->name, - (unsigned long)t->tv_set.tv_sec, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_sec, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data - ); -#endif - } - used += sprintf(bigbuf + used, "\n"); - -#ifdef FAST_TIMER_LOG - num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added: - NUM_TIMER_STATS); - used += sprintf(bigbuf + used, "Timers added: %i\n", fast_timers_added); - for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE); i++) - { - t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS]; - used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu " - "d: %6li us data: 0x%08lX" - "\n", - t->name, - (unsigned long)t->tv_set.tv_sec, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_sec, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data - ); - } - used += sprintf(bigbuf + used, "\n"); - - num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired: - NUM_TIMER_STATS); - used += sprintf(bigbuf + used, "Timers expired: %i\n", fast_timers_expired); - for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE); i++) - { - t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS]; - used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu " - "d: %6li us data: 0x%08lX" - "\n", - t->name, - (unsigned long)t->tv_set.tv_sec, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_sec, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data - ); - } - used += sprintf(bigbuf + used, "\n"); -#endif - - used += sprintf(bigbuf + used, "Active timers:\n"); - local_irq_save(flags); - local_irq_save(flags); - t = fast_timer_list; - while (t != NULL && (used+100 < BIG_BUF_SIZE)) - { - nextt = t->next; - local_irq_restore(flags); - used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu " - "d: %6li us data: 0x%08lX" -/* " func: 0x%08lX" */ - "\n", - t->name, - (unsigned long)t->tv_set.tv_sec, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_sec, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data -/* , t->function */ - ); - local_irq_disable(); - if (t->next != nextt) - { - printk("timer removed!\n"); - } - t = nextt; - } - local_irq_restore(flags); - } - - if (used - offset < len) - { - len = used - offset; - } - - memcpy(buf, bigbuf + offset, len); - *start = buf; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) - *eof = 1; -#endif - - return len; -} -#endif /* PROC_FS */ - -#ifdef FAST_TIMER_TEST -static volatile unsigned long i = 0; -static volatile int num_test_timeout = 0; -static struct fast_timer tr[10]; -static int exp_num[10]; - -static struct timeval tv_exp[100]; - -static void test_timeout(unsigned long data) -{ - do_gettimeofday_fast(&tv_exp[data]); - exp_num[data] = num_test_timeout; - - num_test_timeout++; -} - -static void test_timeout1(unsigned long data) -{ - do_gettimeofday_fast(&tv_exp[data]); - exp_num[data] = num_test_timeout; - if (data < 7) - { - start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1"); - i++; - } - num_test_timeout++; -} - -DP( -static char buf0[2000]; -static char buf1[2000]; -static char buf2[2000]; -static char buf3[2000]; -static char buf4[2000]; -); - -static char buf5[6000]; -static int j_u[1000]; - -static void fast_timer_test(void) -{ - int prev_num; - int j; - - struct timeval tv, tv0, tv1, tv2; - - printk("fast_timer_test() start\n"); - do_gettimeofday_fast(&tv); - - for (j = 0; j < 1000; j++) - { - j_u[j] = GET_JIFFIES_USEC(); - } - for (j = 0; j < 100; j++) - { - do_gettimeofday_fast(&tv_exp[j]); - } - printk("fast_timer_test() %is %06i\n", tv.tv_sec, tv.tv_usec); - - for (j = 0; j < 1000; j++) - { - printk("%i %i %i %i %i\n",j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]); - j += 4; - } - for (j = 0; j < 100; j++) - { - printk("%i.%i %i.%i %i.%i %i.%i %i.%i\n", - tv_exp[j].tv_sec,tv_exp[j].tv_usec, - tv_exp[j+1].tv_sec,tv_exp[j+1].tv_usec, - tv_exp[j+2].tv_sec,tv_exp[j+2].tv_usec, - tv_exp[j+3].tv_sec,tv_exp[j+3].tv_usec, - tv_exp[j+4].tv_sec,tv_exp[j+4].tv_usec); - j += 4; - } - do_gettimeofday_fast(&tv0); - start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0"); - DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1"); - DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2"); - DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3"); - DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx"); - DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0)); - i++; - do_gettimeofday_fast(&tv1); - - proc_fasttimer_read(buf5, NULL, 0, 0, 0); - - prev_num = num_test_timeout; - while (num_test_timeout < i) - { - if (num_test_timeout != prev_num) - { - prev_num = num_test_timeout; - } - } - do_gettimeofday_fast(&tv2); - printk("Timers started %is %06i\n", tv0.tv_sec, tv0.tv_usec); - printk("Timers started at %is %06i\n", tv1.tv_sec, tv1.tv_usec); - printk("Timers done %is %06i\n", tv2.tv_sec, tv2.tv_usec); - DP(printk("buf0:\n"); - printk(buf0); - printk("buf1:\n"); - printk(buf1); - printk("buf2:\n"); - printk(buf2); - printk("buf3:\n"); - printk(buf3); - printk("buf4:\n"); - printk(buf4); - ); - printk("buf5:\n"); - printk(buf5); - - printk("timers set:\n"); - for(j = 0; jname, - t->tv_set.tv_sec, - t->tv_set.tv_usec, - t->tv_expires.tv_sec, - t->tv_expires.tv_usec, - t->data, - t->function - ); - - printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n", - t->delay_us, - tv_exp[j].tv_sec, - tv_exp[j].tv_usec, - exp_num[j], - (tv_exp[j].tv_sec - t->tv_expires.tv_sec)*1000000 + tv_exp[j].tv_usec - t->tv_expires.tv_usec); - } - proc_fasttimer_read(buf5, NULL, 0, 0, 0); - printk("buf5 after all done:\n"); - printk(buf5); - printk("fast_timer_test() done\n"); -} -#endif - - -void fast_timer_init(void) -{ - /* For some reason, request_irq() hangs when called froom time_init() */ - if (!fast_timer_is_init) - { - printk("fast_timer_init()\n"); - -#ifdef CONFIG_PROC_FS -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) - if ((fasttimer_proc_entry = create_proc_entry( "fasttimer", 0, 0 ))) - fasttimer_proc_entry->read_proc = proc_fasttimer_read; -#else - proc_register_dynamic(&proc_root, &fasttimer_proc_entry); -#endif -#endif /* PROC_FS */ - if(request_irq(TIMER_INTR_VECT, timer_trig_interrupt, SA_INTERRUPT, - "fast timer int", NULL)) - { - printk("err: timer1 irq\n"); - } - fast_timer_is_init = 1; -#ifdef FAST_TIMER_TEST - printk("do test\n"); - fast_timer_test(); -#endif - } -} diff --git a/trunk/arch/cris/arch-v32/kernel/head.S b/trunk/arch/cris/arch-v32/kernel/head.S deleted file mode 100644 index 3cfe57dc391d..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/head.S +++ /dev/null @@ -1,448 +0,0 @@ -/* - * CRISv32 kernel startup code. - * - * Copyright (C) 2003, Axis Communications AB - */ - -#include - -#define ASSEMBLER_MACROS_ONLY - -/* - * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so - * -traditional must not be used when assembling this file. - */ -#include -#include -#include -#include -#include - -#define CRAMFS_MAGIC 0x28cd3d45 -#define RAM_INIT_MAGIC 0x56902387 -#define COMMAND_LINE_MAGIC 0x87109563 - - ;; NOTE: R8 and R9 carry information from the decompressor (if the - ;; kernel was compressed). They must not be used in the code below - ;; until they are read! - - ;; Exported symbols. - .global etrax_irv - .global romfs_start - .global romfs_length - .global romfs_in_flash - .global swapper_pg_dir - .global crisv32_nand_boot - .global crisv32_nand_cramfs_offset - - ;; Dummy section to make it bootable with current VCS simulator -#ifdef CONFIG_ETRAXFS_SIM - .section ".boot", "ax" - ba tstart - nop -#endif - - .text -tstart: - ;; This is the entry point of the kernel. The CPU is currently in - ;; supervisor mode. - ;; - ;; 0x00000000 if flash. - ;; 0x40004000 if DRAM. - ;; - di - - ;; Start clocks for used blocks. - move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(config, rw_clk_ctrl, bif, yes) | \ - REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 - move.d $r0, [$r1] - - ;; Set up waitstates etc - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 - move.d $r1, [$r0] - -#ifdef CONFIG_ETRAXFS_SIM - ;; Set up minimal flash waitstates - move.d 0, $r10 - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11 - move.d $r10, [$r11] -#endif - - ;; Setup and enable the MMU. Use same configuration for both the data - ;; and the instruction MMU. - ;; - ;; Note; 3 cycles is needed for a bank-select to take effect. Further; - ;; bank 1 is the instruction MMU, bank 2 is the data MMU. -#ifndef CONFIG_ETRAXFS_SIM - move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0 -#else - ;; Map the virtual DRAM to the RW eprom area at address 0. - ;; Also map 0xa for the hook calls, - move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa), $r0 -#endif - - ;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00. - move.d REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4) \ - | REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1 - - ;; Enable certain page protections and setup linear mapping - ;; for f,e,c,b,4,0. -#ifndef CONFIG_ETRAXFS_SIM - move.d REG_STATE(mmu, rw_mm_cfg, we, on) \ - | REG_STATE(mmu, rw_mm_cfg, acc, on) \ - | REG_STATE(mmu, rw_mm_cfg, ex, on) \ - | REG_STATE(mmu, rw_mm_cfg, inv, on) \ - | REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_d, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_a, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2 -#else - move.d REG_STATE(mmu, rw_mm_cfg, we, on) \ - | REG_STATE(mmu, rw_mm_cfg, acc, on) \ - | REG_STATE(mmu, rw_mm_cfg, ex, on) \ - | REG_STATE(mmu, rw_mm_cfg, inv, on) \ - | REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_d, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_a, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2 -#endif - - ;; Update instruction MMU. - move 1, $srs - nop - nop - nop - move $r0, $s2 ; kbase_hi. - move $r1, $s1 ; kbase_lo. - move $r2, $s0 ; mm_cfg, virtual memory configuration. - - ;; Update data MMU. - move 2, $srs - nop - nop - nop - move $r0, $s2 ; kbase_hi. - move $r1, $s1 ; kbase_lo - move $r2, $s0 ; mm_cfg, virtual memory configuration. - - ;; Enable data and instruction MMU. - move 0, $srs - moveq 0xf, $r0 ; IMMU, DMMU, DCache, Icache on - nop - nop - nop - move $r0, $s0 - nop - nop - nop - -#ifdef CONFIG_SMP - ;; Read CPU ID - move 0, $srs - nop - nop - nop - move $s10, $r0 - cmpq 0, $r0 - beq master_cpu - nop -slave_cpu: - ; A slave waits for cpu_now_booting to be equal to CPU ID. - move.d cpu_now_booting, $r1 -slave_wait: - cmp.d [$r1], $r0 - bne slave_wait - nop - ; Time to boot-up. Get stack location provided by master CPU. - move.d smp_init_current_idle_thread, $r1 - move.d [$r1], $sp - add.d 8192, $sp - move.d ebp_start, $r0 ; Defined in linker-script. - move $r0, $ebp - jsr smp_callin - nop -master_cpu: -#endif -#ifndef CONFIG_ETRAXFS_SIM - ;; Check if starting from DRAM or flash. - lapcq ., $r0 - and.d 0x7fffffff, $r0 ; Mask off the non-cache bit. - cmp.d 0x10000, $r0 ; Arbitrary, something above this code. - blo _inflash0 - nop -#endif - - jump _inram ; Jump to cached RAM. - nop - - ;; Jumpgate. -_inflash0: - jump _inflash - nop - - ;; Put the following in a section so that storage for it can be - ;; reclaimed after init is finished. - .section ".init.text", "ax" - -_inflash: - - ;; Initialize DRAM. - cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? - beq _dram_initialized - nop - -#include "../lib/dram_init.S" - -_dram_initialized: - ;; Copy the text and data section to DRAM. This depends on that the - ;; variables used below are correctly set up by the linker script. - ;; The calculated value stored in R4 is used below. - moveq 0, $r0 ; Source. - move.d text_start, $r1 ; Destination. - move.d __vmlinux_end, $r2 - move.d $r2, $r4 - sub.d $r1, $r4 -1: move.w [$r0+], $r3 - move.w $r3, [$r1+] - cmp.d $r2, $r1 - blo 1b - nop - - ;; Keep CRAMFS in flash. - moveq 0, $r0 - move.d romfs_length, $r1 - move.d $r0, [$r1] - move.d [$r4], $r0 ; cramfs_super.magic - cmp.d CRAMFS_MAGIC, $r0 - bne 1f - nop - - addoq +4, $r4, $acr - move.d [$acr], $r0 - move.d romfs_length, $r1 - move.d $r0, [$r1] - add.d 0xf0000000, $r4 ; Add cached flash start in virtual memory. - move.d romfs_start, $r1 - move.d $r4, [$r1] -1: moveq 1, $r0 - move.d romfs_in_flash, $r1 - move.d $r0, [$r1] - - jump _start_it ; Jump to cached code. - nop - -_inram: - ;; Check if booting from NAND flash (in that case we just remember the offset - ;; into the flash where cramfs should be). - move.d REG_ADDR(config, regi_config, r_bootsel), $r0 - move.d [$r0], $r0 - and.d REG_MASK(config, r_bootsel, boot_mode), $r0 - cmp.d REG_STATE(config, r_bootsel, boot_mode, nand), $r0 - bne move_cramfs - moveq 1,$r0 - move.d crisv32_nand_boot, $r1 - move.d $r0, [$r1] - move.d crisv32_nand_cramfs_offset, $r1 - move.d $r9, [$r1] - moveq 1, $r0 - move.d romfs_in_flash, $r1 - move.d $r0, [$r1] - jump _start_it - nop - -move_cramfs: - ;; Move the cramfs after BSS. - moveq 0, $r0 - move.d romfs_length, $r1 - move.d $r0, [$r1] - -#ifndef CONFIG_ETRAXFS_SIM - ;; The kernel could have been unpacked to DRAM by the loader, but - ;; the cramfs image could still be inte the flash immediately - ;; following the compressed kernel image. The loaded passes the address - ;; of the bute succeeding the last compressed byte in the flash in - ;; register R9 when starting the kernel. - cmp.d 0x0ffffff8, $r9 - bhs _no_romfs_in_flash ; R9 points outside the flash area. - nop -#else - ba _no_romfs_in_flash - nop -#endif - move.d [$r9], $r0 ; cramfs_super.magic - cmp.d CRAMFS_MAGIC, $r0 - bne _no_romfs_in_flash - nop - - addoq +4, $r9, $acr - move.d [$acr], $r0 - move.d romfs_length, $r1 - move.d $r0, [$r1] - add.d 0xf0000000, $r9 ; Add cached flash start in virtual memory. - move.d romfs_start, $r1 - move.d $r9, [$r1] - moveq 1, $r0 - move.d romfs_in_flash, $r1 - move.d $r0, [$r1] - - jump _start_it ; Jump to cached code. - nop - -_no_romfs_in_flash: - ;; Look for cramfs. -#ifndef CONFIG_ETRAXFS_SIM - move.d __vmlinux_end, $r0 -#else - move.d __end, $r0 -#endif - move.d [$r0], $r1 - cmp.d CRAMFS_MAGIC, $r1 - bne 2f - nop - - addoq +4, $r0, $acr - move.d [$acr], $r2 - move.d _end, $r1 - move.d romfs_start, $r3 - move.d $r1, [$r3] - move.d romfs_length, $r3 - move.d $r2, [$r3] - -#ifndef CONFIG_ETRAXFS_SIM - add.d $r2, $r0 - add.d $r2, $r1 - - lsrq 1, $r2 ; Size is in bytes, we copy words. - addq 1, $r2 -1: - move.w [$r0], $r3 - move.w $r3, [$r1] - subq 2, $r0 - subq 2, $r1 - subq 1, $r2 - bne 1b - nop -#endif - -2: - moveq 0, $r0 - move.d romfs_in_flash, $r1 - move.d $r0, [$r1] - - jump _start_it ; Jump to cached code. - nop - -_start_it: - - ;; Check if kernel command line is supplied - cmp.d COMMAND_LINE_MAGIC, $r10 - bne no_command_line - nop - - move.d 256, $r13 - move.d cris_command_line, $r10 - or.d 0x80000000, $r11 ; Make it virtual -1: - move.b [$r11+], $r12 - move.b $r12, [$r10+] - subq 1, $r13 - bne 1b - nop - -no_command_line: - - ;; The kernel stack contains a task structure for each task. This - ;; the initial kernel stack is in the same page as the init_task, - ;; but starts at the top of the page, i.e. + 8192 bytes. - move.d init_thread_union + 8192, $sp - move.d ebp_start, $r0 ; Defined in linker-script. - move $r0, $ebp - move.d etrax_irv, $r1 ; Set the exception base register and pointer. - move.d $r0, [$r1] - -#ifndef CONFIG_ETRAXFS_SIM - ;; Clear the BSS region from _bss_start to _end. - move.d __bss_start, $r0 - move.d _end, $r1 -1: clear.d [$r0+] - cmp.d $r1, $r0 - blo 1b - nop -#endif - -#ifdef CONFIG_ETRAXFS_SIM - /* Set the watchdog timeout to something big. Will be removed when */ - /* watchdog can be disabled with command line option */ - move.d 0x7fffffff, $r10 - jsr CPU_WATCHDOG_TIMEOUT - nop -#endif - - ; Initialize registers to increase determinism - move.d __bss_start, $r0 - movem [$r0], $r13 - - jump start_kernel ; Jump to start_kernel() in init/main.c. - nop - - .data -etrax_irv: - .dword 0 -romfs_start: - .dword 0 -romfs_length: - .dword 0 -romfs_in_flash: - .dword 0 -crisv32_nand_boot: - .dword 0 -crisv32_nand_cramfs_offset: - .dword 0 - -swapper_pg_dir = 0xc0002000 - - .section ".init.data", "aw" - -#include "../lib/hw_settings.S" diff --git a/trunk/arch/cris/arch-v32/kernel/io.c b/trunk/arch/cris/arch-v32/kernel/io.c deleted file mode 100644 index 6bc9f263c3d6..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/io.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Helper functions for I/O pins. - * - * Copyright (c) 2004 Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct crisv32_ioport crisv32_ioports[] = -{ - { - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pa_oe), - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pa_dout), - (unsigned long*)REG_ADDR(gio, regi_gio, r_pa_din), - 8 - }, - { - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pb_oe), - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pb_dout), - (unsigned long*)REG_ADDR(gio, regi_gio, r_pb_din), - 18 - }, - { - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pc_oe), - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pc_dout), - (unsigned long*)REG_ADDR(gio, regi_gio, r_pc_din), - 18 - }, - { - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pd_oe), - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pd_dout), - (unsigned long*)REG_ADDR(gio, regi_gio, r_pd_din), - 18 - }, - { - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pe_oe), - (unsigned long*)REG_ADDR(gio, regi_gio, rw_pe_dout), - (unsigned long*)REG_ADDR(gio, regi_gio, r_pe_din), - 18 - } -}; - -#define NBR_OF_PORTS sizeof(crisv32_ioports)/sizeof(struct crisv32_ioport) - -struct crisv32_iopin crisv32_led1_green; -struct crisv32_iopin crisv32_led1_red; -struct crisv32_iopin crisv32_led2_green; -struct crisv32_iopin crisv32_led2_red; -struct crisv32_iopin crisv32_led3_green; -struct crisv32_iopin crisv32_led3_red; - -/* Dummy port used when green LED and red LED is on the same bit */ -static unsigned long io_dummy; -static struct crisv32_ioport dummy_port = -{ - &io_dummy, - &io_dummy, - &io_dummy, - 18 -}; -static struct crisv32_iopin dummy_led = -{ - &dummy_port, - 0 -}; - -static int __init crisv32_io_init(void) -{ - int ret = 0; - /* Initialize LEDs */ - ret += crisv32_io_get_name(&crisv32_led1_green, CONFIG_ETRAX_LED1G); - ret += crisv32_io_get_name(&crisv32_led1_red, CONFIG_ETRAX_LED1R); - ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_LED2G); - ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_LED2R); - ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_LED3G); - ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_LED3R); - crisv32_io_set_dir(&crisv32_led1_green, crisv32_io_dir_out); - crisv32_io_set_dir(&crisv32_led1_red, crisv32_io_dir_out); - crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out); - crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out); - crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out); - crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out); - - if (!strcmp(CONFIG_ETRAX_LED1G, CONFIG_ETRAX_LED1R)) - crisv32_led1_red = dummy_led; - if (!strcmp(CONFIG_ETRAX_LED2G, CONFIG_ETRAX_LED2R)) - crisv32_led2_red = dummy_led; - - return ret; -} - -__initcall(crisv32_io_init); - -int crisv32_io_get(struct crisv32_iopin* iopin, - unsigned int port, unsigned int pin) -{ - if (port > NBR_OF_PORTS) - return -EINVAL; - if (port > crisv32_ioports[port].pin_count) - return -EINVAL; - - iopin->bit = 1 << pin; - iopin->port = &crisv32_ioports[port]; - - if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio)) - return -EIO; - - return 0; -} - -int crisv32_io_get_name(struct crisv32_iopin* iopin, - char* name) -{ - int port; - int pin; - - if (toupper(*name) == 'P') - name++; - - if (toupper(*name) < 'A' || toupper(*name) > 'E') - return -EINVAL; - - port = toupper(*name) - 'A'; - name++; - pin = simple_strtoul(name, NULL, 10); - - if (pin < 0 || pin > crisv32_ioports[port].pin_count) - return -EINVAL; - - iopin->bit = 1 << pin; - iopin->port = &crisv32_ioports[port]; - - if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio)) - return -EIO; - - return 0; -} - -#ifdef CONFIG_PCI -/* PCI I/O access stuff */ -struct cris_io_operations* cris_iops = NULL; -EXPORT_SYMBOL(cris_iops); -#endif - diff --git a/trunk/arch/cris/arch-v32/kernel/irq.c b/trunk/arch/cris/arch-v32/kernel/irq.c deleted file mode 100644 index c78cc2685133..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/irq.c +++ /dev/null @@ -1,413 +0,0 @@ -/* - * Copyright (C) 2003, Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CPU_FIXED -1 - -/* IRQ masks (refer to comment for crisv32_do_multiple) */ -#define TIMER_MASK (1 << (TIMER_INTR_VECT - FIRST_IRQ)) -#ifdef CONFIG_ETRAX_KGDB -#if defined(CONFIG_ETRAX_KGDB_PORT0) -#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ)) -#elif defined(CONFIG_ETRAX_KGDB_PORT1) -#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ)) -#elif defined(CONFIG_ETRAX_KGB_PORT2) -#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ)) -#elif defined(CONFIG_ETRAX_KGDB_PORT3) -#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ)) -#endif -#endif - -DEFINE_SPINLOCK(irq_lock); - -struct cris_irq_allocation -{ - int cpu; /* The CPU to which the IRQ is currently allocated. */ - cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */ -}; - -struct cris_irq_allocation irq_allocations[NR_IRQS] = - {[0 ... NR_IRQS - 1] = {0, CPU_MASK_ALL}}; - -static unsigned long irq_regs[NR_CPUS] = -{ - regi_irq, -#ifdef CONFIG_SMP - regi_irq2, -#endif -}; - -unsigned long cpu_irq_counters[NR_CPUS]; -unsigned long irq_counters[NR_REAL_IRQS]; - -/* From irq.c. */ -extern void weird_irq(void); - -/* From entry.S. */ -extern void system_call(void); -extern void nmi_interrupt(void); -extern void multiple_interrupt(void); -extern void gdb_handle_exception(void); -extern void i_mmu_refill(void); -extern void i_mmu_invalid(void); -extern void i_mmu_access(void); -extern void i_mmu_execute(void); -extern void d_mmu_refill(void); -extern void d_mmu_invalid(void); -extern void d_mmu_access(void); -extern void d_mmu_write(void); - -/* From kgdb.c. */ -extern void kgdb_init(void); -extern void breakpoint(void); - -/* - * Build the IRQ handler stubs using macros from irq.h. First argument is the - * IRQ number, the second argument is the corresponding bit in - * intr_rw_vect_mask found in asm/arch/hwregs/intr_vect_defs.h. - */ -BUILD_IRQ(0x31, (1 << 0)) /* memarb */ -BUILD_IRQ(0x32, (1 << 1)) /* gen_io */ -BUILD_IRQ(0x33, (1 << 2)) /* iop0 */ -BUILD_IRQ(0x34, (1 << 3)) /* iop1 */ -BUILD_IRQ(0x35, (1 << 4)) /* iop2 */ -BUILD_IRQ(0x36, (1 << 5)) /* iop3 */ -BUILD_IRQ(0x37, (1 << 6)) /* dma0 */ -BUILD_IRQ(0x38, (1 << 7)) /* dma1 */ -BUILD_IRQ(0x39, (1 << 8)) /* dma2 */ -BUILD_IRQ(0x3a, (1 << 9)) /* dma3 */ -BUILD_IRQ(0x3b, (1 << 10)) /* dma4 */ -BUILD_IRQ(0x3c, (1 << 11)) /* dma5 */ -BUILD_IRQ(0x3d, (1 << 12)) /* dma6 */ -BUILD_IRQ(0x3e, (1 << 13)) /* dma7 */ -BUILD_IRQ(0x3f, (1 << 14)) /* dma8 */ -BUILD_IRQ(0x40, (1 << 15)) /* dma9 */ -BUILD_IRQ(0x41, (1 << 16)) /* ata */ -BUILD_IRQ(0x42, (1 << 17)) /* sser0 */ -BUILD_IRQ(0x43, (1 << 18)) /* sser1 */ -BUILD_IRQ(0x44, (1 << 19)) /* ser0 */ -BUILD_IRQ(0x45, (1 << 20)) /* ser1 */ -BUILD_IRQ(0x46, (1 << 21)) /* ser2 */ -BUILD_IRQ(0x47, (1 << 22)) /* ser3 */ -BUILD_IRQ(0x48, (1 << 23)) -BUILD_IRQ(0x49, (1 << 24)) /* eth0 */ -BUILD_IRQ(0x4a, (1 << 25)) /* eth1 */ -BUILD_TIMER_IRQ(0x4b, (1 << 26))/* timer */ -BUILD_IRQ(0x4c, (1 << 27)) /* bif_arb */ -BUILD_IRQ(0x4d, (1 << 28)) /* bif_dma */ -BUILD_IRQ(0x4e, (1 << 29)) /* ext */ -BUILD_IRQ(0x4f, (1 << 29)) /* ipi */ - -/* Pointers to the low-level handlers. */ -static void (*interrupt[NR_IRQS])(void) = { - IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt, - IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt, - IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt, - IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt, - IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt, - IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt, - IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt, - IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt, - IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt, - IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt, - IRQ0x4f_interrupt -}; - -void -block_irq(int irq, int cpu) -{ - int intr_mask; - unsigned long flags; - - spin_lock_irqsave(&irq_lock, flags); - intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask); - - /* Remember; 1 let thru, 0 block. */ - intr_mask &= ~(1 << (irq - FIRST_IRQ)); - - REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask); - spin_unlock_irqrestore(&irq_lock, flags); -} - -void -unblock_irq(int irq, int cpu) -{ - int intr_mask; - unsigned long flags; - - spin_lock_irqsave(&irq_lock, flags); - intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask); - - /* Remember; 1 let thru, 0 block. */ - intr_mask |= (1 << (irq - FIRST_IRQ)); - - REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask); - spin_unlock_irqrestore(&irq_lock, flags); -} - -/* Find out which CPU the irq should be allocated to. */ -static int irq_cpu(int irq) -{ - int cpu; - unsigned long flags; - - spin_lock_irqsave(&irq_lock, flags); - cpu = irq_allocations[irq - FIRST_IRQ].cpu; - - /* Fixed interrupts stay on the local CPU. */ - if (cpu == CPU_FIXED) - { - spin_unlock_irqrestore(&irq_lock, flags); - return smp_processor_id(); - } - - - /* Let the interrupt stay if possible */ - if (cpu_isset(cpu, irq_allocations[irq - FIRST_IRQ].mask)) - goto out; - - /* IRQ must be moved to another CPU. */ - cpu = first_cpu(irq_allocations[irq - FIRST_IRQ].mask); - irq_allocations[irq - FIRST_IRQ].cpu = cpu; -out: - spin_unlock_irqrestore(&irq_lock, flags); - return cpu; -} - -void -mask_irq(int irq) -{ - int cpu; - - for (cpu = 0; cpu < NR_CPUS; cpu++) - block_irq(irq, cpu); -} - -void -unmask_irq(int irq) -{ - unblock_irq(irq, irq_cpu(irq)); -} - - -static unsigned int startup_crisv32_irq(unsigned int irq) -{ - unmask_irq(irq); - return 0; -} - -static void shutdown_crisv32_irq(unsigned int irq) -{ - mask_irq(irq); -} - -static void enable_crisv32_irq(unsigned int irq) -{ - unmask_irq(irq); -} - -static void disable_crisv32_irq(unsigned int irq) -{ - mask_irq(irq); -} - -static void ack_crisv32_irq(unsigned int irq) -{ -} - -static void end_crisv32_irq(unsigned int irq) -{ -} - -void set_affinity_crisv32_irq(unsigned int irq, cpumask_t dest) -{ - unsigned long flags; - spin_lock_irqsave(&irq_lock, flags); - irq_allocations[irq - FIRST_IRQ].mask = dest; - spin_unlock_irqrestore(&irq_lock, flags); -} - -static struct hw_interrupt_type crisv32_irq_type = { - .typename = "CRISv32", - .startup = startup_crisv32_irq, - .shutdown = shutdown_crisv32_irq, - .enable = enable_crisv32_irq, - .disable = disable_crisv32_irq, - .ack = ack_crisv32_irq, - .end = end_crisv32_irq, - .set_affinity = set_affinity_crisv32_irq -}; - -void -set_exception_vector(int n, irqvectptr addr) -{ - etrax_irv->v[n] = (irqvectptr) addr; -} - -extern void do_IRQ(int irq, struct pt_regs * regs); - -void -crisv32_do_IRQ(int irq, int block, struct pt_regs* regs) -{ - /* Interrupts that may not be moved to another CPU and - * are SA_INTERRUPT may skip blocking. This is currently - * only valid for the timer IRQ and the IPI and is used - * for the timer interrupt to avoid watchdog starvation. - */ - if (!block) { - do_IRQ(irq, regs); - return; - } - - block_irq(irq, smp_processor_id()); - do_IRQ(irq, regs); - - unblock_irq(irq, irq_cpu(irq)); -} - -/* If multiple interrupts occur simultaneously we get a multiple - * interrupt from the CPU and software has to sort out which - * interrupts that happened. There are two special cases here: - * - * 1. Timer interrupts may never be blocked because of the - * watchdog (refer to comment in include/asr/arch/irq.h) - * 2. GDB serial port IRQs are unhandled here and will be handled - * as a single IRQ when it strikes again because the GDB - * stubb wants to save the registers in its own fashion. - */ -void -crisv32_do_multiple(struct pt_regs* regs) -{ - int cpu; - int mask; - int masked; - int bit; - - cpu = smp_processor_id(); - - /* An extra irq_enter here to prevent softIRQs to run after - * each do_IRQ. This will decrease the interrupt latency. - */ - irq_enter(); - - /* Get which IRQs that happend. */ - masked = REG_RD_INT(intr_vect, irq_regs[cpu], r_masked_vect); - - /* Calculate new IRQ mask with these IRQs disabled. */ - mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask); - mask &= ~masked; - - /* Timer IRQ is never masked */ - if (masked & TIMER_MASK) - mask |= TIMER_MASK; - - /* Block all the IRQs */ - REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask); - - /* Check for timer IRQ and handle it special. */ - if (masked & TIMER_MASK) { - masked &= ~TIMER_MASK; - do_IRQ(TIMER_INTR_VECT, regs); - } - -#ifdef IGNORE_MASK - /* Remove IRQs that can't be handled as multiple. */ - masked &= ~IGNORE_MASK; -#endif - - /* Handle the rest of the IRQs. */ - for (bit = 0; bit < 32; bit++) - { - if (masked & (1 << bit)) - do_IRQ(bit + FIRST_IRQ, regs); - } - - /* Unblock all the IRQs. */ - mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask); - mask |= masked; - REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask); - - /* This irq_exit() will trigger the soft IRQs. */ - irq_exit(); -} - -/* - * This is called by start_kernel. It fixes the IRQ masks and setup the - * interrupt vector table to point to bad_interrupt pointers. - */ -void __init -init_IRQ(void) -{ - int i; - int j; - reg_intr_vect_rw_mask vect_mask = {0}; - - /* Clear all interrupts masks. */ - REG_WR(intr_vect, regi_irq, rw_mask, vect_mask); - - for (i = 0; i < 256; i++) - etrax_irv->v[i] = weird_irq; - - /* Point all IRQ's to bad handlers. */ - for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) { - irq_desc[j].handler = &crisv32_irq_type; - set_exception_vector(i, interrupt[j]); - } - - /* Mark Timer and IPI IRQs as CPU local */ - irq_allocations[TIMER_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED; - irq_desc[TIMER_INTR_VECT].status |= IRQ_PER_CPU; - irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED; - irq_desc[IPI_INTR_VECT].status |= IRQ_PER_CPU; - - set_exception_vector(0x00, nmi_interrupt); - set_exception_vector(0x30, multiple_interrupt); - - /* Set up handler for various MMU bus faults. */ - set_exception_vector(0x04, i_mmu_refill); - set_exception_vector(0x05, i_mmu_invalid); - set_exception_vector(0x06, i_mmu_access); - set_exception_vector(0x07, i_mmu_execute); - set_exception_vector(0x08, d_mmu_refill); - set_exception_vector(0x09, d_mmu_invalid); - set_exception_vector(0x0a, d_mmu_access); - set_exception_vector(0x0b, d_mmu_write); - - /* The system-call trap is reached by "break 13". */ - set_exception_vector(0x1d, system_call); - - /* Exception handlers for debugging, both user-mode and kernel-mode. */ - - /* Break 8. */ - set_exception_vector(0x18, gdb_handle_exception); - /* Hardware single step. */ - set_exception_vector(0x3, gdb_handle_exception); - /* Hardware breakpoint. */ - set_exception_vector(0xc, gdb_handle_exception); - -#ifdef CONFIG_ETRAX_KGDB - kgdb_init(); - /* Everything is set up; now trap the kernel. */ - breakpoint(); -#endif -} - diff --git a/trunk/arch/cris/arch-v32/kernel/kgdb.c b/trunk/arch/cris/arch-v32/kernel/kgdb.c deleted file mode 100644 index 480e56348be2..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/kgdb.c +++ /dev/null @@ -1,1660 +0,0 @@ -/* - * arch/cris/arch-v32/kernel/kgdb.c - * - * CRIS v32 version by Orjan Friberg, Axis Communications AB. - * - * S390 version - * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation - * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), - * - * Originally written by Glenn Engel, Lake Stevens Instrument Division - * - * Contributed by HP Systems - * - * Modified for SPARC by Stu Grossman, Cygnus Support. - * - * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse - * Send complaints, suggestions etc. to - * - * Copyright (C) 1995 Andreas Busse - */ - -/* FIXME: Check the documentation. */ - -/* - * kgdb usage notes: - * ----------------- - * - * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be - * built with different gcc flags: "-g" is added to get debug infos, and - * "-fomit-frame-pointer" is omitted to make debugging easier. Since the - * resulting kernel will be quite big (approx. > 7 MB), it will be stripped - * before compresion. Such a kernel will behave just as usually, except if - * given a "debug=" command line option. (Only serial devices are - * allowed for , i.e. no printers or the like; possible values are - * machine depedend and are the same as for the usual debug device, the one - * for logging kernel messages.) If that option is given and the device can be - * initialized, the kernel will connect to the remote gdb in trap_init(). The - * serial parameters are fixed to 8N1 and 115200 bps, for easyness of - * implementation. - * - * To start a debugging session, start that gdb with the debugging kernel - * image (the one with the symbols, vmlinux.debug) named on the command line. - * This file will be used by gdb to get symbol and debugging infos about the - * kernel. Next, select remote debug mode by - * target remote - * where is the name of the serial device over which the debugged - * machine is connected. Maybe you have to adjust the baud rate by - * set remotebaud - * or also other parameters with stty: - * shell stty ... #. - * - * where - * :: - * :: < two hex digits computed as modulo 256 sum of > - * - * When a packet is received, it is first acknowledged with either '+' or '-'. - * '+' indicates a successful transfer. '-' indicates a failed transfer. - * - * Example: - * - * Host: Reply: - * $m0,10#2a +$00010203040506070809101112131415#42 - * - */ - - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -/* From entry.S. */ -extern void gdb_handle_exception(void); -/* From kgdb_asm.S. */ -extern void kgdb_handle_exception(void); - -static int kgdb_started = 0; - -/********************************* Register image ****************************/ - -typedef -struct register_image -{ - /* Offset */ - unsigned int r0; /* 0x00 */ - unsigned int r1; /* 0x04 */ - unsigned int r2; /* 0x08 */ - unsigned int r3; /* 0x0C */ - unsigned int r4; /* 0x10 */ - unsigned int r5; /* 0x14 */ - unsigned int r6; /* 0x18 */ - unsigned int r7; /* 0x1C */ - unsigned int r8; /* 0x20; Frame pointer (if any) */ - unsigned int r9; /* 0x24 */ - unsigned int r10; /* 0x28 */ - unsigned int r11; /* 0x2C */ - unsigned int r12; /* 0x30 */ - unsigned int r13; /* 0x34 */ - unsigned int sp; /* 0x38; R14, Stack pointer */ - unsigned int acr; /* 0x3C; R15, Address calculation register. */ - - unsigned char bz; /* 0x40; P0, 8-bit zero register */ - unsigned char vr; /* 0x41; P1, Version register (8-bit) */ - unsigned int pid; /* 0x42; P2, Process ID */ - unsigned char srs; /* 0x46; P3, Support register select (8-bit) */ - unsigned short wz; /* 0x47; P4, 16-bit zero register */ - unsigned int exs; /* 0x49; P5, Exception status */ - unsigned int eda; /* 0x4D; P6, Exception data address */ - unsigned int mof; /* 0x51; P7, Multiply overflow register */ - unsigned int dz; /* 0x55; P8, 32-bit zero register */ - unsigned int ebp; /* 0x59; P9, Exception base pointer */ - unsigned int erp; /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */ - unsigned int srp; /* 0x61; P11, Subroutine return pointer */ - unsigned int nrp; /* 0x65; P12, NMI return pointer */ - unsigned int ccs; /* 0x69; P13, Condition code stack */ - unsigned int usp; /* 0x6D; P14, User mode stack pointer */ - unsigned int spc; /* 0x71; P15, Single step PC */ - unsigned int pc; /* 0x75; Pseudo register (for the most part set to ERP). */ - -} registers; - -typedef -struct bp_register_image -{ - /* Support register bank 0. */ - unsigned int s0_0; - unsigned int s1_0; - unsigned int s2_0; - unsigned int s3_0; - unsigned int s4_0; - unsigned int s5_0; - unsigned int s6_0; - unsigned int s7_0; - unsigned int s8_0; - unsigned int s9_0; - unsigned int s10_0; - unsigned int s11_0; - unsigned int s12_0; - unsigned int s13_0; - unsigned int s14_0; - unsigned int s15_0; - - /* Support register bank 1. */ - unsigned int s0_1; - unsigned int s1_1; - unsigned int s2_1; - unsigned int s3_1; - unsigned int s4_1; - unsigned int s5_1; - unsigned int s6_1; - unsigned int s7_1; - unsigned int s8_1; - unsigned int s9_1; - unsigned int s10_1; - unsigned int s11_1; - unsigned int s12_1; - unsigned int s13_1; - unsigned int s14_1; - unsigned int s15_1; - - /* Support register bank 2. */ - unsigned int s0_2; - unsigned int s1_2; - unsigned int s2_2; - unsigned int s3_2; - unsigned int s4_2; - unsigned int s5_2; - unsigned int s6_2; - unsigned int s7_2; - unsigned int s8_2; - unsigned int s9_2; - unsigned int s10_2; - unsigned int s11_2; - unsigned int s12_2; - unsigned int s13_2; - unsigned int s14_2; - unsigned int s15_2; - - /* Support register bank 3. */ - unsigned int s0_3; /* BP_CTRL */ - unsigned int s1_3; /* BP_I0_START */ - unsigned int s2_3; /* BP_I0_END */ - unsigned int s3_3; /* BP_D0_START */ - unsigned int s4_3; /* BP_D0_END */ - unsigned int s5_3; /* BP_D1_START */ - unsigned int s6_3; /* BP_D1_END */ - unsigned int s7_3; /* BP_D2_START */ - unsigned int s8_3; /* BP_D2_END */ - unsigned int s9_3; /* BP_D3_START */ - unsigned int s10_3; /* BP_D3_END */ - unsigned int s11_3; /* BP_D4_START */ - unsigned int s12_3; /* BP_D4_END */ - unsigned int s13_3; /* BP_D5_START */ - unsigned int s14_3; /* BP_D5_END */ - unsigned int s15_3; /* BP_RESERVED */ - -} support_registers; - -enum register_name -{ - R0, R1, R2, R3, - R4, R5, R6, R7, - R8, R9, R10, R11, - R12, R13, SP, ACR, - - BZ, VR, PID, SRS, - WZ, EXS, EDA, MOF, - DZ, EBP, ERP, SRP, - NRP, CCS, USP, SPC, - PC, - - S0, S1, S2, S3, - S4, S5, S6, S7, - S8, S9, S10, S11, - S12, S13, S14, S15 - -}; - -/* The register sizes of the registers in register_name. An unimplemented register - is designated by size 0 in this array. */ -static int register_size[] = -{ - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - - 1, 1, 4, 1, - 2, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - - 4, - - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4 - -}; - -/* Contains the register image of the kernel. - (Global so that they can be reached from assembler code.) */ -registers reg; -support_registers sreg; - -/************** Prototypes for local library functions ***********************/ - -/* Copy of strcpy from libc. */ -static char *gdb_cris_strcpy(char *s1, const char *s2); - -/* Copy of strlen from libc. */ -static int gdb_cris_strlen(const char *s); - -/* Copy of memchr from libc. */ -static void *gdb_cris_memchr(const void *s, int c, int n); - -/* Copy of strtol from libc. Does only support base 16. */ -static int gdb_cris_strtol(const char *s, char **endptr, int base); - -/********************** Prototypes for local functions. **********************/ - -/* Write a value to a specified register regno in the register image - of the current thread. */ -static int write_register(int regno, char *val); - -/* Read a value from a specified register in the register image. Returns the - status of the read operation. The register value is returned in valptr. */ -static int read_register(char regno, unsigned int *valptr); - -/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */ -int getDebugChar(void); - -#ifdef CONFIG_ETRAXFS_SIM -int getDebugChar(void) -{ - return socketread(); -} -#endif - -/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */ -void putDebugChar(int val); - -#ifdef CONFIG_ETRAXFS_SIM -void putDebugChar(int val) -{ - socketwrite((char *)&val, 1); -} -#endif - -/* Returns the character equivalent of a nibble, bit 7, 6, 5, and 4 of a byte, - represented by int x. */ -static char highhex(int x); - -/* Returns the character equivalent of a nibble, bit 3, 2, 1, and 0 of a byte, - represented by int x. */ -static char lowhex(int x); - -/* Returns the integer equivalent of a hexadecimal character. */ -static int hex(char ch); - -/* Convert the memory, pointed to by mem into hexadecimal representation. - Put the result in buf, and return a pointer to the last character - in buf (null). */ -static char *mem2hex(char *buf, unsigned char *mem, int count); - -/* Convert the array, in hexadecimal representation, pointed to by buf into - binary representation. Put the result in mem, and return a pointer to - the character after the last byte written. */ -static unsigned char *hex2mem(unsigned char *mem, char *buf, int count); - -/* Put the content of the array, in binary representation, pointed to by buf - into memory pointed to by mem, and return a pointer to - the character after the last byte written. */ -static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count); - -/* Await the sequence $# and store in the array buffer - returned. */ -static void getpacket(char *buffer); - -/* Send $# from the in the array buffer. */ -static void putpacket(char *buffer); - -/* Build and send a response packet in order to inform the host the - stub is stopped. */ -static void stub_is_stopped(int sigval); - -/* All expected commands are sent from remote.c. Send a response according - to the description in remote.c. Not static since it needs to be reached - from assembler code. */ -void handle_exception(int sigval); - -/* Performs a complete re-start from scratch. ETRAX specific. */ -static void kill_restart(void); - -/******************** Prototypes for global functions. ***********************/ - -/* The string str is prepended with the GDB printout token and sent. */ -void putDebugString(const unsigned char *str, int len); - -/* A static breakpoint to be used at startup. */ -void breakpoint(void); - -/* Avoid warning as the internal_stack is not used in the C-code. */ -#define USEDVAR(name) { if (name) { ; } } -#define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) } - -/********************************** Packet I/O ******************************/ -/* BUFMAX defines the maximum number of characters in - inbound/outbound buffers */ -/* FIXME: How do we know it's enough? */ -#define BUFMAX 512 - -/* Run-length encoding maximum length. Send 64 at most. */ -#define RUNLENMAX 64 - -/* Definition of all valid hexadecimal characters */ -static const char hexchars[] = "0123456789abcdef"; - -/* The inbound/outbound buffers used in packet I/O */ -static char input_buffer[BUFMAX]; -static char output_buffer[BUFMAX]; - -/* Error and warning messages. */ -enum error_type -{ - SUCCESS, E01, E02, E03, E04, E05, E06, -}; - -static char *error_message[] = -{ - "", - "E01 Set current or general thread - H[c,g] - internal error.", - "E02 Change register content - P - cannot change read-only register.", - "E03 Thread is not alive.", /* T, not used. */ - "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.", - "E05 Change register content - P - the register is not implemented..", - "E06 Change memory content - M - internal error.", -}; - -/********************************** Breakpoint *******************************/ -/* Use an internal stack in the breakpoint and interrupt response routines. - FIXME: How do we know the size of this stack is enough? - Global so it can be reached from assembler code. */ -#define INTERNAL_STACK_SIZE 1024 -char internal_stack[INTERNAL_STACK_SIZE]; - -/* Due to the breakpoint return pointer, a state variable is needed to keep - track of whether it is a static (compiled) or dynamic (gdb-invoked) - breakpoint to be handled. A static breakpoint uses the content of register - ERP as it is whereas a dynamic breakpoint requires subtraction with 2 - in order to execute the instruction. The first breakpoint is static; all - following are assumed to be dynamic. */ -static int dynamic_bp = 0; - -/********************************* String library ****************************/ -/* Single-step over library functions creates trap loops. */ - -/* Copy char s2[] to s1[]. */ -static char* -gdb_cris_strcpy(char *s1, const char *s2) -{ - char *s = s1; - - for (s = s1; (*s++ = *s2++) != '\0'; ) - ; - return s1; -} - -/* Find length of s[]. */ -static int -gdb_cris_strlen(const char *s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; sc++) - ; - return (sc - s); -} - -/* Find first occurrence of c in s[n]. */ -static void* -gdb_cris_memchr(const void *s, int c, int n) -{ - const unsigned char uc = c; - const unsigned char *su; - - for (su = s; 0 < n; ++su, --n) - if (*su == uc) - return (void *)su; - return NULL; -} -/******************************* Standard library ****************************/ -/* Single-step over library functions creates trap loops. */ -/* Convert string to long. */ -static int -gdb_cris_strtol(const char *s, char **endptr, int base) -{ - char *s1; - char *sd; - int x = 0; - - for (s1 = (char*)s; (sd = gdb_cris_memchr(hexchars, *s1, base)) != NULL; ++s1) - x = x * base + (sd - hexchars); - - if (endptr) { - /* Unconverted suffix is stored in endptr unless endptr is NULL. */ - *endptr = s1; - } - - return x; -} - -/********************************* Register image ****************************/ - -/* Write a value to a specified register in the register image of the current - thread. Returns status code SUCCESS, E02 or E05. */ -static int -write_register(int regno, char *val) -{ - int status = SUCCESS; - - if (regno >= R0 && regno <= ACR) { - /* Consecutive 32-bit registers. */ - hex2mem((unsigned char *)®.r0 + (regno - R0) * sizeof(unsigned int), - val, sizeof(unsigned int)); - - } else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) { - /* Read-only registers. */ - status = E02; - - } else if (regno == PID) { - /* 32-bit register. (Even though we already checked SRS and WZ, we cannot - combine this with the EXS - SPC write since SRS and WZ have different size.) */ - hex2mem((unsigned char *)®.pid, val, sizeof(unsigned int)); - - } else if (regno == SRS) { - /* 8-bit register. */ - hex2mem((unsigned char *)®.srs, val, sizeof(unsigned char)); - - } else if (regno >= EXS && regno <= SPC) { - /* Consecutive 32-bit registers. */ - hex2mem((unsigned char *)®.exs + (regno - EXS) * sizeof(unsigned int), - val, sizeof(unsigned int)); - - } else if (regno == PC) { - /* Pseudo-register. Treat as read-only. */ - status = E02; - - } else if (regno >= S0 && regno <= S15) { - /* 32-bit registers. */ - hex2mem((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int), val, sizeof(unsigned int)); - } else { - /* Non-existing register. */ - status = E05; - } - return status; -} - -/* Read a value from a specified register in the register image. Returns the - value in the register or -1 for non-implemented registers. */ -static int -read_register(char regno, unsigned int *valptr) -{ - int status = SUCCESS; - - /* We read the zero registers from the register struct (instead of just returning 0) - to catch errors. */ - - if (regno >= R0 && regno <= ACR) { - /* Consecutive 32-bit registers. */ - *valptr = *(unsigned int *)((char *)®.r0 + (regno - R0) * sizeof(unsigned int)); - - } else if (regno == BZ || regno == VR) { - /* Consecutive 8-bit registers. */ - *valptr = (unsigned int)(*(unsigned char *) - ((char *)®.bz + (regno - BZ) * sizeof(char))); - - } else if (regno == PID) { - /* 32-bit register. */ - *valptr = *(unsigned int *)((char *)®.pid); - - } else if (regno == SRS) { - /* 8-bit register. */ - *valptr = (unsigned int)(*(unsigned char *)((char *)®.srs)); - - } else if (regno == WZ) { - /* 16-bit register. */ - *valptr = (unsigned int)(*(unsigned short *)(char *)®.wz); - - } else if (regno >= EXS && regno <= PC) { - /* Consecutive 32-bit registers. */ - *valptr = *(unsigned int *)((char *)®.exs + (regno - EXS) * sizeof(unsigned int)); - - } else if (regno >= S0 && regno <= S15) { - /* Consecutive 32-bit registers, located elsewhere. */ - *valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int)); - - } else { - /* Non-existing register. */ - status = E05; - } - return status; - -} - -/********************************** Packet I/O ******************************/ -/* Returns the character equivalent of a nibble, bit 7, 6, 5, and 4 of a byte, - represented by int x. */ -static inline char -highhex(int x) -{ - return hexchars[(x >> 4) & 0xf]; -} - -/* Returns the character equivalent of a nibble, bit 3, 2, 1, and 0 of a byte, - represented by int x. */ -static inline char -lowhex(int x) -{ - return hexchars[x & 0xf]; -} - -/* Returns the integer equivalent of a hexadecimal character. */ -static int -hex(char ch) -{ - if ((ch >= 'a') && (ch <= 'f')) - return (ch - 'a' + 10); - if ((ch >= '0') && (ch <= '9')) - return (ch - '0'); - if ((ch >= 'A') && (ch <= 'F')) - return (ch - 'A' + 10); - return -1; -} - -/* Convert the memory, pointed to by mem into hexadecimal representation. - Put the result in buf, and return a pointer to the last character - in buf (null). */ - -static char * -mem2hex(char *buf, unsigned char *mem, int count) -{ - int i; - int ch; - - if (mem == NULL) { - /* Invalid address, caught by 'm' packet handler. */ - for (i = 0; i < count; i++) { - *buf++ = '0'; - *buf++ = '0'; - } - } else { - /* Valid mem address. */ - for (i = 0; i < count; i++) { - ch = *mem++; - *buf++ = highhex (ch); - *buf++ = lowhex (ch); - } - } - /* Terminate properly. */ - *buf = '\0'; - return buf; -} - -/* Same as mem2hex, but puts it in network byte order. */ -static char * -mem2hex_nbo(char *buf, unsigned char *mem, int count) -{ - int i; - int ch; - - mem += count - 1; - for (i = 0; i < count; i++) { - ch = *mem--; - *buf++ = highhex (ch); - *buf++ = lowhex (ch); - } - - /* Terminate properly. */ - *buf = '\0'; - return buf; -} - -/* Convert the array, in hexadecimal representation, pointed to by buf into - binary representation. Put the result in mem, and return a pointer to - the character after the last byte written. */ -static unsigned char* -hex2mem(unsigned char *mem, char *buf, int count) -{ - int i; - unsigned char ch; - for (i = 0; i < count; i++) { - ch = hex (*buf++) << 4; - ch = ch + hex (*buf++); - *mem++ = ch; - } - return mem; -} - -/* Put the content of the array, in binary representation, pointed to by buf - into memory pointed to by mem, and return a pointer to the character after - the last byte written. - Gdb will escape $, #, and the escape char (0x7d). */ -static unsigned char* -bin2mem(unsigned char *mem, unsigned char *buf, int count) -{ - int i; - unsigned char *next; - for (i = 0; i < count; i++) { - /* Check for any escaped characters. Be paranoid and - only unescape chars that should be escaped. */ - if (*buf == 0x7d) { - next = buf + 1; - if (*next == 0x3 || *next == 0x4 || *next == 0x5D) { - /* #, $, ESC */ - buf++; - *buf += 0x20; - } - } - *mem++ = *buf++; - } - return mem; -} - -/* Await the sequence $# and store in the array buffer - returned. */ -static void -getpacket(char *buffer) -{ - unsigned char checksum; - unsigned char xmitcsum; - int i; - int count; - char ch; - - do { - while((ch = getDebugChar ()) != '$') - /* Wait for the start character $ and ignore all other characters */; - checksum = 0; - xmitcsum = -1; - count = 0; - /* Read until a # or the end of the buffer is reached */ - while (count < BUFMAX) { - ch = getDebugChar(); - if (ch == '#') - break; - checksum = checksum + ch; - buffer[count] = ch; - count = count + 1; - } - - if (count >= BUFMAX) - continue; - - buffer[count] = 0; - - if (ch == '#') { - xmitcsum = hex(getDebugChar()) << 4; - xmitcsum += hex(getDebugChar()); - if (checksum != xmitcsum) { - /* Wrong checksum */ - putDebugChar('-'); - } else { - /* Correct checksum */ - putDebugChar('+'); - /* If sequence characters are received, reply with them */ - if (buffer[2] == ':') { - putDebugChar(buffer[0]); - putDebugChar(buffer[1]); - /* Remove the sequence characters from the buffer */ - count = gdb_cris_strlen(buffer); - for (i = 3; i <= count; i++) - buffer[i - 3] = buffer[i]; - } - } - } - } while (checksum != xmitcsum); -} - -/* Send $# from the in the array buffer. */ - -static void -putpacket(char *buffer) -{ - int checksum; - int runlen; - int encode; - - do { - char *src = buffer; - putDebugChar('$'); - checksum = 0; - while (*src) { - /* Do run length encoding */ - putDebugChar(*src); - checksum += *src; - runlen = 0; - while (runlen < RUNLENMAX && *src == src[runlen]) { - runlen++; - } - if (runlen > 3) { - /* Got a useful amount */ - putDebugChar ('*'); - checksum += '*'; - encode = runlen + ' ' - 4; - putDebugChar(encode); - checksum += encode; - src += runlen; - } else { - src++; - } - } - putDebugChar('#'); - putDebugChar(highhex (checksum)); - putDebugChar(lowhex (checksum)); - } while(kgdb_started && (getDebugChar() != '+')); -} - -/* The string str is prepended with the GDB printout token and sent. Required - in traditional implementations. */ -void -putDebugString(const unsigned char *str, int len) -{ - /* Move SPC forward if we are single-stepping. */ - asm("spchere:"); - asm("move $spc, $r10"); - asm("cmp.d spchere, $r10"); - asm("bne nosstep"); - asm("nop"); - asm("move.d spccont, $r10"); - asm("move $r10, $spc"); - asm("nosstep:"); - - output_buffer[0] = 'O'; - mem2hex(&output_buffer[1], (unsigned char *)str, len); - putpacket(output_buffer); - - asm("spccont:"); -} - -/********************************** Handle exceptions ************************/ -/* Build and send a response packet in order to inform the host the - stub is stopped. TAAn...:r...;n...:r...;n...:r...; - AA = signal number - n... = register number (hex) - r... = register contents - n... = `thread' - r... = thread process ID. This is a hex integer. - n... = other string not starting with valid hex digit. - gdb should ignore this n,r pair and go on to the next. - This way we can extend the protocol. */ -static void -stub_is_stopped(int sigval) -{ - char *ptr = output_buffer; - unsigned int reg_cont; - - /* Send trap type (converted to signal) */ - - *ptr++ = 'T'; - *ptr++ = highhex(sigval); - *ptr++ = lowhex(sigval); - - if (((reg.exs & 0xff00) >> 8) == 0xc) { - - /* Some kind of hardware watchpoint triggered. Find which one - and determine its type (read/write/access). */ - int S, bp, trig_bits = 0, rw_bits = 0; - int trig_mask = 0; - unsigned int *bp_d_regs = &sreg.s3_3; - /* In a lot of cases, the stopped data address will simply be EDA. - In some cases, we adjust it to match the watched data range. - (We don't want to change the actual EDA though). */ - unsigned int stopped_data_address; - /* The S field of EXS. */ - S = (reg.exs & 0xffff0000) >> 16; - - if (S & 1) { - /* Instruction watchpoint. */ - /* FIXME: Check against, and possibly adjust reported EDA. */ - } else { - /* Data watchpoint. Find the one that triggered. */ - for (bp = 0; bp < 6; bp++) { - - /* Dx_RD, Dx_WR in the S field of EXS for this BP. */ - int bitpos_trig = 1 + bp * 2; - /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */ - int bitpos_config = 2 + bp * 4; - - /* Get read/write trig bits for this BP. */ - trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig; - - /* Read/write config bits for this BP. */ - rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config; - if (trig_bits) { - /* Sanity check: the BP shouldn't trigger for accesses - that it isn't configured for. */ - if ((rw_bits == 0x1 && trig_bits != 0x1) || - (rw_bits == 0x2 && trig_bits != 0x2)) - panic("Invalid r/w trigging for this BP"); - - /* Mark this BP as trigged for future reference. */ - trig_mask |= (1 << bp); - - if (reg.eda >= bp_d_regs[bp * 2] && - reg.eda <= bp_d_regs[bp * 2 + 1]) { - /* EDA withing range for this BP; it must be the one - we're looking for. */ - stopped_data_address = reg.eda; - break; - } - } - } - if (bp < 6) { - /* Found a trigged BP with EDA within its configured data range. */ - } else if (trig_mask) { - /* Something triggered, but EDA doesn't match any BP's range. */ - for (bp = 0; bp < 6; bp++) { - /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */ - int bitpos_config = 2 + bp * 4; - - /* Read/write config bits for this BP (needed later). */ - rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config; - - if (trig_mask & (1 << bp)) { - /* EDA within 31 bytes of the configured start address? */ - if (reg.eda + 31 >= bp_d_regs[bp * 2]) { - /* Changing the reported address to match - the start address of the first applicable BP. */ - stopped_data_address = bp_d_regs[bp * 2]; - break; - } else { - /* We continue since we might find another useful BP. */ - printk("EDA doesn't match trigged BP's range"); - } - } - } - } - - /* No match yet? */ - BUG_ON(bp >= 6); - /* Note that we report the type according to what the BP is configured - for (otherwise we'd never report an 'awatch'), not according to how - it trigged. We did check that the trigged bits match what the BP is - configured for though. */ - if (rw_bits == 0x1) { - /* read */ - strncpy(ptr, "rwatch", 6); - ptr += 6; - } else if (rw_bits == 0x2) { - /* write */ - strncpy(ptr, "watch", 5); - ptr += 5; - } else if (rw_bits == 0x3) { - /* access */ - strncpy(ptr, "awatch", 6); - ptr += 6; - } else { - panic("Invalid r/w bits for this BP."); - } - - *ptr++ = ':'; - /* Note that we don't read_register(EDA, ...) */ - ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]); - *ptr++ = ';'; - } - } - /* Only send PC, frame and stack pointer. */ - read_register(PC, ®_cont); - *ptr++ = highhex(PC); - *ptr++ = lowhex(PC); - *ptr++ = ':'; - ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[PC]); - *ptr++ = ';'; - - read_register(R8, ®_cont); - *ptr++ = highhex(R8); - *ptr++ = lowhex(R8); - *ptr++ = ':'; - ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[R8]); - *ptr++ = ';'; - - read_register(SP, ®_cont); - *ptr++ = highhex(SP); - *ptr++ = lowhex(SP); - *ptr++ = ':'; - ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[SP]); - *ptr++ = ';'; - - /* Send ERP as well; this will save us an entire register fetch in some cases. */ - read_register(ERP, ®_cont); - *ptr++ = highhex(ERP); - *ptr++ = lowhex(ERP); - *ptr++ = ':'; - ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[ERP]); - *ptr++ = ';'; - - /* null-terminate and send it off */ - *ptr = 0; - putpacket(output_buffer); -} - -/* Returns the size of an instruction that has a delay slot. */ - -int insn_size(unsigned long pc) -{ - unsigned short opcode = *(unsigned short *)pc; - int size = 0; - - switch ((opcode & 0x0f00) >> 8) { - case 0x0: - case 0x9: - case 0xb: - size = 2; - break; - case 0xe: - case 0xf: - size = 6; - break; - case 0xd: - /* Could be 4 or 6; check more bits. */ - if ((opcode & 0xff) == 0xff) - size = 4; - else - size = 6; - break; - default: - panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc); - } - - return size; -} - -void register_fixup(int sigval) -{ - /* Compensate for ACR push at the beginning of exception handler. */ - reg.sp += 4; - - /* Standard case. */ - reg.pc = reg.erp; - if (reg.erp & 0x1) { - /* Delay slot bit set. Report as stopped on proper instruction. */ - if (reg.spc) { - /* Rely on SPC if set. */ - reg.pc = reg.spc; - } else { - /* Calculate the PC from the size of the instruction - that the delay slot we're in belongs to. */ - reg.pc += insn_size(reg.erp & ~1) - 1 ; - } - } - - if ((reg.exs & 0x3) == 0x0) { - /* Bits 1 - 0 indicate the type of memory operation performed - by the interrupted instruction. 0 means no memory operation, - and EDA is undefined in that case. We zero it to avoid confusion. */ - reg.eda = 0; - } - - if (sigval == SIGTRAP) { - /* Break 8, single step or hardware breakpoint exception. */ - - /* Check IDX field of EXS. */ - if (((reg.exs & 0xff00) >> 8) == 0x18) { - - /* Break 8. */ - - /* Static (compiled) breakpoints must return to the next instruction - in order to avoid infinite loops (default value of ERP). Dynamic - (gdb-invoked) must subtract the size of the break instruction from - the ERP so that the instruction that was originally in the break - instruction's place will be run when we return from the exception. */ - if (!dynamic_bp) { - /* Assuming that all breakpoints are dynamic from now on. */ - dynamic_bp = 1; - } else { - - /* Only if not in a delay slot. */ - if (!(reg.erp & 0x1)) { - reg.erp -= 2; - reg.pc -= 2; - } - } - - } else if (((reg.exs & 0xff00) >> 8) == 0x3) { - /* Single step. */ - /* Don't fiddle with S1. */ - - } else if (((reg.exs & 0xff00) >> 8) == 0xc) { - - /* Hardware watchpoint exception. */ - - /* SPC has been updated so that we will get a single step exception - when we return, but we don't want that. */ - reg.spc = 0; - - /* Don't fiddle with S1. */ - } - - } else if (sigval == SIGINT) { - /* Nothing special. */ - } -} - -static void insert_watchpoint(char type, int addr, int len) -{ - /* Breakpoint/watchpoint types (GDB terminology): - 0 = memory breakpoint for instructions - (not supported; done via memory write instead) - 1 = hardware breakpoint for instructions (supported) - 2 = write watchpoint (supported) - 3 = read watchpoint (supported) - 4 = access watchpoint (supported) */ - - if (type < '1' || type > '4') { - output_buffer[0] = 0; - return; - } - - /* Read watchpoints are set as access watchpoints, because of GDB's - inability to deal with pure read watchpoints. */ - if (type == '3') - type = '4'; - - if (type == '1') { - /* Hardware (instruction) breakpoint. */ - /* Bit 0 in BP_CTRL holds the configuration for I0. */ - if (sreg.s0_3 & 0x1) { - /* Already in use. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - return; - } - /* Configure. */ - sreg.s1_3 = addr; - sreg.s2_3 = (addr + len - 1); - sreg.s0_3 |= 1; - } else { - int bp; - unsigned int *bp_d_regs = &sreg.s3_3; - - /* The watchpoint allocation scheme is the simplest possible. - For example, if a region is watched for read and - a write watch is requested, a new watchpoint will - be used. Also, if a watch for a region that is already - covered by one or more existing watchpoints, a new - watchpoint will be used. */ - - /* First, find a free data watchpoint. */ - for (bp = 0; bp < 6; bp++) { - /* Each data watchpoint's control registers occupy 2 bits - (hence the 3), starting at bit 2 for D0 (hence the 2) - with 4 bits between for each watchpoint (yes, the 4). */ - if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) { - break; - } - } - - if (bp > 5) { - /* We're out of watchpoints. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - return; - } - - /* Configure the control register first. */ - if (type == '3' || type == '4') { - /* Trigger on read. */ - sreg.s0_3 |= (1 << (2 + bp * 4)); - } - if (type == '2' || type == '4') { - /* Trigger on write. */ - sreg.s0_3 |= (2 << (2 + bp * 4)); - } - - /* Ugly pointer arithmetics to configure the watched range. */ - bp_d_regs[bp * 2] = addr; - bp_d_regs[bp * 2 + 1] = (addr + len - 1); - } - - /* Set the S1 flag to enable watchpoints. */ - reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); - gdb_cris_strcpy(output_buffer, "OK"); -} - -static void remove_watchpoint(char type, int addr, int len) -{ - /* Breakpoint/watchpoint types: - 0 = memory breakpoint for instructions - (not supported; done via memory write instead) - 1 = hardware breakpoint for instructions (supported) - 2 = write watchpoint (supported) - 3 = read watchpoint (supported) - 4 = access watchpoint (supported) */ - if (type < '1' || type > '4') { - output_buffer[0] = 0; - return; - } - - /* Read watchpoints are set as access watchpoints, because of GDB's - inability to deal with pure read watchpoints. */ - if (type == '3') - type = '4'; - - if (type == '1') { - /* Hardware breakpoint. */ - /* Bit 0 in BP_CTRL holds the configuration for I0. */ - if (!(sreg.s0_3 & 0x1)) { - /* Not in use. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - return; - } - /* Deconfigure. */ - sreg.s1_3 = 0; - sreg.s2_3 = 0; - sreg.s0_3 &= ~1; - } else { - int bp; - unsigned int *bp_d_regs = &sreg.s3_3; - /* Try to find a watchpoint that is configured for the - specified range, then check that read/write also matches. */ - - /* Ugly pointer arithmetic, since I cannot rely on a - single switch (addr) as there may be several watchpoints with - the same start address for example. */ - - for (bp = 0; bp < 6; bp++) { - if (bp_d_regs[bp * 2] == addr && - bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { - /* Matching range. */ - int bitpos = 2 + bp * 4; - int rw_bits; - - /* Read/write bits for this BP. */ - rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos; - - if ((type == '3' && rw_bits == 0x1) || - (type == '2' && rw_bits == 0x2) || - (type == '4' && rw_bits == 0x3)) { - /* Read/write matched. */ - break; - } - } - } - - if (bp > 5) { - /* No watchpoint matched. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - return; - } - - /* Found a matching watchpoint. Now, deconfigure it by - both disabling read/write in bp_ctrl and zeroing its - start/end addresses. */ - sreg.s0_3 &= ~(3 << (2 + (bp * 4))); - bp_d_regs[bp * 2] = 0; - bp_d_regs[bp * 2 + 1] = 0; - } - - /* Note that we don't clear the S1 flag here. It's done when continuing. */ - gdb_cris_strcpy(output_buffer, "OK"); -} - - - -/* All expected commands are sent from remote.c. Send a response according - to the description in remote.c. */ -void -handle_exception(int sigval) -{ - /* Avoid warning of not used. */ - - USEDFUN(handle_exception); - USEDVAR(internal_stack[0]); - - register_fixup(sigval); - - /* Send response. */ - stub_is_stopped(sigval); - - for (;;) { - output_buffer[0] = '\0'; - getpacket(input_buffer); - switch (input_buffer[0]) { - case 'g': - /* Read registers: g - Success: Each byte of register data is described by two hex digits. - Registers are in the internal order for GDB, and the bytes - in a register are in the same order the machine uses. - Failure: void. */ - { - char *buf; - /* General and special registers. */ - buf = mem2hex(output_buffer, (char *)®, sizeof(registers)); - /* Support registers. */ - /* -1 because of the null termination that mem2hex adds. */ - mem2hex(buf, - (char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)), - 16 * sizeof(unsigned int)); - break; - } - case 'G': - /* Write registers. GXX..XX - Each byte of register data is described by two hex digits. - Success: OK - Failure: void. */ - /* General and special registers. */ - hex2mem((char *)®, &input_buffer[1], sizeof(registers)); - /* Support registers. */ - hex2mem((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)), - &input_buffer[1] + sizeof(registers), - 16 * sizeof(unsigned int)); - gdb_cris_strcpy(output_buffer, "OK"); - break; - - case 'P': - /* Write register. Pn...=r... - Write register n..., hex value without 0x, with value r..., - which contains a hex value without 0x and two hex digits - for each byte in the register (target byte order). P1f=11223344 means - set register 31 to 44332211. - Success: OK - Failure: E02, E05 */ - { - char *suffix; - int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16); - int status; - - status = write_register(regno, suffix+1); - - switch (status) { - case E02: - /* Do not support read-only registers. */ - gdb_cris_strcpy(output_buffer, error_message[E02]); - break; - case E05: - /* Do not support non-existing registers. */ - gdb_cris_strcpy(output_buffer, error_message[E05]); - break; - default: - /* Valid register number. */ - gdb_cris_strcpy(output_buffer, "OK"); - break; - } - } - break; - - case 'm': - /* Read from memory. mAA..AA,LLLL - AA..AA is the address and LLLL is the length. - Success: XX..XX is the memory content. Can be fewer bytes than - requested if only part of the data may be read. m6000120a,6c means - retrieve 108 byte from base address 6000120a. - Failure: void. */ - { - char *suffix; - unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1], - &suffix, 16); - int len = gdb_cris_strtol(suffix+1, 0, 16); - - /* Bogus read (i.e. outside the kernel's - segment)? . */ - if (!((unsigned int)addr >= 0xc0000000 && - (unsigned int)addr < 0xd0000000)) - addr = NULL; - - mem2hex(output_buffer, addr, len); - } - break; - - case 'X': - /* Write to memory. XAA..AA,LLLL:XX..XX - AA..AA is the start address, LLLL is the number of bytes, and - XX..XX is the binary data. - Success: OK - Failure: void. */ - case 'M': - /* Write to memory. MAA..AA,LLLL:XX..XX - AA..AA is the start address, LLLL is the number of bytes, and - XX..XX is the hexadecimal data. - Success: OK - Failure: void. */ - { - char *lenptr; - char *dataptr; - unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1], - &lenptr, 16); - int len = gdb_cris_strtol(lenptr+1, &dataptr, 16); - if (*lenptr == ',' && *dataptr == ':') { - if (input_buffer[0] == 'M') { - hex2mem(addr, dataptr + 1, len); - } else /* X */ { - bin2mem(addr, dataptr + 1, len); - } - gdb_cris_strcpy(output_buffer, "OK"); - } - else { - gdb_cris_strcpy(output_buffer, error_message[E06]); - } - } - break; - - case 'c': - /* Continue execution. cAA..AA - AA..AA is the address where execution is resumed. If AA..AA is - omitted, resume at the present address. - Success: return to the executing thread. - Failure: will never know. */ - - if (input_buffer[1] != '\0') { - /* FIXME: Doesn't handle address argument. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - break; - } - - /* Before continuing, make sure everything is set up correctly. */ - - /* Set the SPC to some unlikely value. */ - reg.spc = 0; - /* Set the S1 flag to 0 unless some watchpoint is enabled (since setting - S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL - are reserved, so don't check against those). */ - if ((sreg.s0_3 & 0x3fff) == 0) { - reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT)); - } - - return; - - case 's': - /* Step. sAA..AA - AA..AA is the address where execution is resumed. If AA..AA is - omitted, resume at the present address. Success: return to the - executing thread. Failure: will never know. */ - - if (input_buffer[1] != '\0') { - /* FIXME: Doesn't handle address argument. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - break; - } - - /* Set the SPC to PC, which is where we'll return - (deduced previously). */ - reg.spc = reg.pc; - - /* Set the S1 (first stacked, not current) flag, which will - kick into action when we rfe. */ - reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); - return; - - case 'Z': - - /* Insert breakpoint or watchpoint, Ztype,addr,length. - Remote protocol says: A remote target shall return an empty string - for an unrecognized breakpoint or watchpoint packet type. */ - { - char *lenptr; - char *dataptr; - int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16); - int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16); - char type = input_buffer[1]; - - insert_watchpoint(type, addr, len); - break; - } - - case 'z': - /* Remove breakpoint or watchpoint, Ztype,addr,length. - Remote protocol says: A remote target shall return an empty string - for an unrecognized breakpoint or watchpoint packet type. */ - { - char *lenptr; - char *dataptr; - int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16); - int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16); - char type = input_buffer[1]; - - remove_watchpoint(type, addr, len); - break; - } - - - case '?': - /* The last signal which caused a stop. ? - Success: SAA, where AA is the signal number. - Failure: void. */ - output_buffer[0] = 'S'; - output_buffer[1] = highhex(sigval); - output_buffer[2] = lowhex(sigval); - output_buffer[3] = 0; - break; - - case 'D': - /* Detach from host. D - Success: OK, and return to the executing thread. - Failure: will never know */ - putpacket("OK"); - return; - - case 'k': - case 'r': - /* kill request or reset request. - Success: restart of target. - Failure: will never know. */ - kill_restart(); - break; - - case 'C': - case 'S': - case '!': - case 'R': - case 'd': - /* Continue with signal sig. Csig;AA..AA - Step with signal sig. Ssig;AA..AA - Use the extended remote protocol. ! - Restart the target system. R0 - Toggle debug flag. d - Search backwards. tAA:PP,MM - Not supported: E04 */ - - /* FIXME: What's the difference between not supported - and ignored (below)? */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - break; - - default: - /* The stub should ignore other request and send an empty - response ($#). This way we can extend the protocol and GDB - can tell whether the stub it is talking to uses the old or the new. */ - output_buffer[0] = 0; - break; - } - putpacket(output_buffer); - } -} - -void -kgdb_init(void) -{ - reg_intr_vect_rw_mask intr_mask; - reg_ser_rw_intr_mask ser_intr_mask; - - /* Configure the kgdb serial port. */ -#if defined(CONFIG_ETRAX_KGDB_PORT0) - /* Note: no shortcut registered (not handled by multiple_interrupt). - See entry.S. */ - set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception); - /* Enable the ser irq in the global config. */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.ser0 = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask); - ser_intr_mask.data_avail = regk_ser_yes; - REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask); -#elif defined(CONFIG_ETRAX_KGDB_PORT1) - /* Note: no shortcut registered (not handled by multiple_interrupt). - See entry.S. */ - set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception); - /* Enable the ser irq in the global config. */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.ser1 = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask); - ser_intr_mask.data_avail = regk_ser_yes; - REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask); -#elif defined(CONFIG_ETRAX_KGDB_PORT2) - /* Note: no shortcut registered (not handled by multiple_interrupt). - See entry.S. */ - set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception); - /* Enable the ser irq in the global config. */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.ser2 = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask); - ser_intr_mask.data_avail = regk_ser_yes; - REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask); -#elif defined(CONFIG_ETRAX_KGDB_PORT3) - /* Note: no shortcut registered (not handled by multiple_interrupt). - See entry.S. */ - set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception); - /* Enable the ser irq in the global config. */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.ser3 = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask); - ser_intr_mask.data_avail = regk_ser_yes; - REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask); -#endif - -} -/* Performs a complete re-start from scratch. */ -static void -kill_restart(void) -{ - machine_restart(""); -} - -/* Use this static breakpoint in the start-up only. */ - -void -breakpoint(void) -{ - kgdb_started = 1; - dynamic_bp = 0; /* This is a static, not a dynamic breakpoint. */ - __asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */ -} - -/****************************** End of file **********************************/ diff --git a/trunk/arch/cris/arch-v32/kernel/kgdb_asm.S b/trunk/arch/cris/arch-v32/kernel/kgdb_asm.S deleted file mode 100644 index b350dd279ed2..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/kgdb_asm.S +++ /dev/null @@ -1,552 +0,0 @@ -/* - * Copyright (C) 2004 Axis Communications AB - * - * Code for handling break 8, hardware breakpoint, single step, and serial - * port exceptions for kernel debugging purposes. - */ - -#include -#include - - ;; Exported functions. - .globl kgdb_handle_exception - -kgdb_handle_exception: - -;; Create a register image of the caller. -;; -;; First of all, save the ACR on the stack since we need it for address calculations. -;; We put it into the register struct later. - - subq 4, $sp - move.d $acr, [$sp] - -;; Now we are free to use ACR all we want. -;; If we were running this handler with interrupts on, we would have to be careful -;; to save and restore CCS manually, but since we aren't we treat it like every other -;; register. - - move.d reg, $acr - move.d $r0, [$acr] ; Save R0 (start of register struct) - addq 4, $acr - move.d $r1, [$acr] ; Save R1 - addq 4, $acr - move.d $r2, [$acr] ; Save R2 - addq 4, $acr - move.d $r3, [$acr] ; Save R3 - addq 4, $acr - move.d $r4, [$acr] ; Save R4 - addq 4, $acr - move.d $r5, [$acr] ; Save R5 - addq 4, $acr - move.d $r6, [$acr] ; Save R6 - addq 4, $acr - move.d $r7, [$acr] ; Save R7 - addq 4, $acr - move.d $r8, [$acr] ; Save R8 - addq 4, $acr - move.d $r9, [$acr] ; Save R9 - addq 4, $acr - move.d $r10, [$acr] ; Save R10 - addq 4, $acr - move.d $r11, [$acr] ; Save R11 - addq 4, $acr - move.d $r12, [$acr] ; Save R12 - addq 4, $acr - move.d $r13, [$acr] ; Save R13 - addq 4, $acr - move.d $sp, [$acr] ; Save SP (R14) - addq 4, $acr - - ;; The ACR register is already saved on the stack, so pop it from there. - move.d [$sp],$r0 - move.d $r0, [$acr] - addq 4, $acr - - move $bz, [$acr] - addq 1, $acr - move $vr, [$acr] - addq 1, $acr - move $pid, [$acr] - addq 4, $acr - move $srs, [$acr] - addq 1, $acr - move $wz, [$acr] - addq 2, $acr - move $exs, [$acr] - addq 4, $acr - move $eda, [$acr] - addq 4, $acr - move $mof, [$acr] - addq 4, $acr - move $dz, [$acr] - addq 4, $acr - move $ebp, [$acr] - addq 4, $acr - move $erp, [$acr] - addq 4, $acr - move $srp, [$acr] - addq 4, $acr - move $nrp, [$acr] - addq 4, $acr - move $ccs, [$acr] - addq 4, $acr - move $usp, [$acr] - addq 4, $acr - move $spc, [$acr] - addq 4, $acr - -;; Skip the pseudo-PC. - addq 4, $acr - -;; Save the support registers in bank 0 - 3. - clear.d $r1 ; Bank counter - move.d sreg, $acr - -;; Bank 0 - move $r1, $srs - nop - nop - nop - move $s0, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s1, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s2, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s3, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s4, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s5, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s6, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s7, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s8, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s9, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s10, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s11, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s12, $r0 - move.d $r0, [$acr] - addq 4, $acr - - ;; Nothing in S13 - S15, bank 0 - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - -;; Bank 1 and bank 2 have the same layout, hence the loop. - addq 1, $r1 -1: - move $r1, $srs - nop - nop - nop - move $s0, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s1, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s2, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s3, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s4, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s5, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s6, $r0 - move.d $r0, [$acr] - addq 4, $acr - - ;; Nothing in S7 - S15, bank 1 and 2 - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - - addq 1, $r1 - cmpq 3, $r1 - bne 1b - nop - -;; Bank 3 - move $r1, $srs - nop - nop - nop - move $s0, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s1, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s2, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s3, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s4, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s5, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s6, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s7, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s8, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s9, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s10, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s11, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s12, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s13, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s14, $r0 - move.d $r0, [$acr] - addq 4, $acr -;; Nothing in S15, bank 3 - clear.d [$acr] - addq 4, $acr - -;; Check what got us here: get IDX field of EXS. - move $exs, $r10 - and.d 0xff00, $r10 - lsrq 8, $r10 -#if defined(CONFIG_ETRAX_KGDB_PORT0) - cmp.d SER0_INTR_VECT, $r10 ; IRQ for serial port 0 - beq sigint - nop -#elif defined(CONFIG_ETRAX_KGDB_PORT1) - cmp.d SER1_INTR_VECT, $r10 ; IRQ for serial port 1 - beq sigint - nop -#elif defined(CONFIG_ETRAX_KGDB_PORT2) - cmp.d SER2_INTR_VECT, $r10 ; IRQ for serial port 2 - beq sigint - nop -#elif defined(CONFIG_ETRAX_KGDB_PORT3) - cmp.d SER3_INTR_VECT, $r10 ; IRQ for serial port 3 - beq sigint - nop -#endif -;; Multiple interrupt must be due to serial break. - cmp.d 0x30, $r10 ; Multiple interrupt - beq sigint - nop -;; Neither of those? Then it's a sigtrap. - ba handle_comm - moveq 5, $r10 ; Set SIGTRAP (delay slot) - -sigint: - ;; Serial interrupt; get character - jsr getDebugChar - nop ; Delay slot - cmp.b 3, $r10 ; \003 (Ctrl-C)? - bne return ; No, get out of here - nop - moveq 2, $r10 ; Set SIGINT - -;; -;; Handle the communication -;; -handle_comm: - move.d internal_stack+1020, $sp ; Use the internal stack which grows upwards - jsr handle_exception ; Interactive routine - nop - -;; -;; Return to the caller -;; -return: - -;; First of all, write the support registers. - clear.d $r1 ; Bank counter - move.d sreg, $acr - -;; Bank 0 - move $r1, $srs - nop - nop - nop - move.d [$acr], $r0 - move $r0, $s0 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s1 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s2 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s3 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s4 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s5 - addq 4, $acr - -;; Nothing in S6 - S7, bank 0. - addq 4, $acr - addq 4, $acr - - move.d [$acr], $r0 - move $r0, $s8 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s9 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s10 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s11 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s12 - addq 4, $acr - -;; Nothing in S13 - S15, bank 0 - addq 4, $acr - addq 4, $acr - addq 4, $acr - -;; Bank 1 and bank 2 have the same layout, hence the loop. - addq 1, $r1 -2: - move $r1, $srs - nop - nop - nop - move.d [$acr], $r0 - move $r0, $s0 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s1 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s2 - addq 4, $acr - -;; S3 (MM_CAUSE) is read-only. - addq 4, $acr - - move.d [$acr], $r0 - move $r0, $s4 - addq 4, $acr - -;; FIXME: Actually write S5/S6? (Affects MM_CAUSE.) - addq 4, $acr - addq 4, $acr - -;; Nothing in S7 - S15, bank 1 and 2 - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - - addq 1, $r1 - cmpq 3, $r1 - bne 2b - nop - -;; Bank 3 - move $r1, $srs - nop - nop - nop - move.d [$acr], $r0 - move $r0, $s0 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s1 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s2 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s3 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s4 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s5 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s6 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s7 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s8 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s9 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s10 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s11 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s12 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s13 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s14 - addq 4, $acr - -;; Nothing in S15, bank 3 - addq 4, $acr - -;; Now, move on to the regular register restoration process. - - move.d reg, $acr ; Reset ACR to point at the beginning of the register image - move.d [$acr], $r0 ; Restore R0 - addq 4, $acr - move.d [$acr], $r1 ; Restore R1 - addq 4, $acr - move.d [$acr], $r2 ; Restore R2 - addq 4, $acr - move.d [$acr], $r3 ; Restore R3 - addq 4, $acr - move.d [$acr], $r4 ; Restore R4 - addq 4, $acr - move.d [$acr], $r5 ; Restore R5 - addq 4, $acr - move.d [$acr], $r6 ; Restore R6 - addq 4, $acr - move.d [$acr], $r7 ; Restore R7 - addq 4, $acr - move.d [$acr], $r8 ; Restore R8 - addq 4, $acr - move.d [$acr], $r9 ; Restore R9 - addq 4, $acr - move.d [$acr], $r10 ; Restore R10 - addq 4, $acr - move.d [$acr], $r11 ; Restore R11 - addq 4, $acr - move.d [$acr], $r12 ; Restore R12 - addq 4, $acr - move.d [$acr], $r13 ; Restore R13 - -;; -;; We restore all registers, even though some of them probably haven't changed. -;; - - addq 4, $acr - move.d [$acr], $sp ; Restore SP (R14) - - ;; ACR cannot be restored just yet. - addq 8, $acr - - ;; Skip BZ, VR. - addq 2, $acr - - move [$acr], $pid ; Restore PID - addq 4, $acr - move [$acr], $srs ; Restore SRS - nop - nop - nop - addq 1, $acr - - ;; Skip WZ. - addq 2, $acr - - move [$acr], $exs ; Restore EXS. - addq 4, $acr - move [$acr], $eda ; Restore EDA. - addq 4, $acr - move [$acr], $mof ; Restore MOF. - - ;; Skip DZ. - addq 8, $acr - - move [$acr], $ebp ; Restore EBP. - addq 4, $acr - move [$acr], $erp ; Restore ERP. - addq 4, $acr - move [$acr], $srp ; Restore SRP. - addq 4, $acr - move [$acr], $nrp ; Restore NRP. - addq 4, $acr - move [$acr], $ccs ; Restore CCS like an ordinary register. - addq 4, $acr - move [$acr], $usp ; Restore USP - addq 4, $acr - move [$acr], $spc ; Restore SPC - ; No restoration of pseudo-PC of course. - - move.d reg, $acr ; Reset ACR to point at the beginning of the register image - add.d 15*4, $acr - move.d [$acr], $acr ; Finally, restore ACR. - rete ; Same as jump ERP - rfe ; Shifts CCS diff --git a/trunk/arch/cris/arch-v32/kernel/pinmux.c b/trunk/arch/cris/arch-v32/kernel/pinmux.c deleted file mode 100644 index a2b8aa37c1bf..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/pinmux.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Allocator for I/O pins. All pins are allocated to GPIO at bootup. - * Unassigned pins and GPIO pins can be allocated to a fixed interface - * or the I/O processor instead. - * - * Copyright (c) 2004 Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG - -#define PORT_PINS 18 -#define PORTS 4 - -static char pins[PORTS][PORT_PINS]; -static DEFINE_SPINLOCK(pinmux_lock); - -static void crisv32_pinmux_set(int port); - -int -crisv32_pinmux_init(void) -{ - static int initialized = 0; - - if (!initialized) { - reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa); - initialized = 1; - pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 = - pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes; - REG_WR(pinmux, regi_pinmux, rw_pa, pa); - crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio); - crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio); - crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio); - crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio); - } - - return 0; -} - -int -crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode) -{ - int i; - unsigned long flags; - - crisv32_pinmux_init(); - - if (port > PORTS) - return -EINVAL; - - spin_lock_irqsave(&pinmux_lock, flags); - - for (i = first_pin; i <= last_pin; i++) - { - if ((pins[port][i] != pinmux_none) && (pins[port][i] != pinmux_gpio) && - (pins[port][i] != mode)) - { - spin_unlock_irqrestore(&pinmux_lock, flags); -#ifdef DEBUG - panic("Pinmux alloc failed!\n"); -#endif - return -EPERM; - } - } - - for (i = first_pin; i <= last_pin; i++) - pins[port][i] = mode; - - crisv32_pinmux_set(port); - - spin_unlock_irqrestore(&pinmux_lock, flags); - - return 0; -} - -int -crisv32_pinmux_alloc_fixed(enum fixed_function function) -{ - int ret = -EINVAL; - char saved[sizeof pins]; - unsigned long flags; - - spin_lock_irqsave(&pinmux_lock, flags); - - /* Save internal data for recovery */ - memcpy(saved, pins, sizeof pins); - - reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); - - switch(function) - { - case pinmux_ser1: - ret = crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed); - hwprot.ser1 = regk_pinmux_yes; - break; - case pinmux_ser2: - ret = crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed); - hwprot.ser2 = regk_pinmux_yes; - break; - case pinmux_ser3: - ret = crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed); - hwprot.ser3 = regk_pinmux_yes; - break; - case pinmux_sser0: - ret = crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); - hwprot.sser0 = regk_pinmux_yes; - break; - case pinmux_sser1: - ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); - hwprot.sser1 = regk_pinmux_yes; - break; - case pinmux_ata0: - ret = crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed); - hwprot.ata0 = regk_pinmux_yes; - break; - case pinmux_ata1: - ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed); - hwprot.ata1 = regk_pinmux_yes; - break; - case pinmux_ata2: - ret = crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed); - hwprot.ata2 = regk_pinmux_yes; - break; - case pinmux_ata3: - ret = crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed); - hwprot.ata2 = regk_pinmux_yes; - break; - case pinmux_ata: - ret = crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed); - hwprot.ata = regk_pinmux_yes; - break; - case pinmux_eth1: - ret = crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed); - hwprot.eth1 = regk_pinmux_yes; - hwprot.eth1_mgm = regk_pinmux_yes; - break; - case pinmux_timer: - ret = crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); - hwprot.timer = regk_pinmux_yes; - spin_unlock_irqrestore(&pinmux_lock, flags); - return ret; - } - - if (!ret) - REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); - else - memcpy(pins, saved, sizeof pins); - - spin_unlock_irqrestore(&pinmux_lock, flags); - - return ret; -} - -void -crisv32_pinmux_set(int port) -{ - int i; - int gpio_val = 0; - int iop_val = 0; - - for (i = 0; i < PORT_PINS; i++) - { - if (pins[port][i] == pinmux_gpio) - gpio_val |= (1 << i); - else if (pins[port][i] == pinmux_iop) - iop_val |= (1 << i); - } - - REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8*port, gpio_val); - REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8*port, iop_val); - -#ifdef DEBUG - crisv32_pinmux_dump(); -#endif -} - -int -crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) -{ - int i; - unsigned long flags; - - crisv32_pinmux_init(); - - if (port > PORTS) - return -EINVAL; - - spin_lock_irqsave(&pinmux_lock, flags); - - for (i = first_pin; i <= last_pin; i++) - pins[port][i] = pinmux_none; - - crisv32_pinmux_set(port); - spin_unlock_irqrestore(&pinmux_lock, flags); - - return 0; -} - -void -crisv32_pinmux_dump(void) -{ - int i, j; - - crisv32_pinmux_init(); - - for (i = 0; i < PORTS; i++) - { - printk("Port %c\n", 'B'+i); - for (j = 0; j < PORT_PINS; j++) - printk(" Pin %d = %d\n", j, pins[i][j]); - } -} - -__initcall(crisv32_pinmux_init); diff --git a/trunk/arch/cris/arch-v32/kernel/process.c b/trunk/arch/cris/arch-v32/kernel/process.c deleted file mode 100644 index 882be42114f7..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/process.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright (C) 2000-2003 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * Mikael Starvik (starvik@axis.com) - * Tobias Anderberg (tobiasa@axis.com), CRISv32 port. - * - * This file handles the architecture-dependent parts of process handling.. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void stop_watchdog(void); - -#ifdef CONFIG_ETRAX_GPIO -extern void etrax_gpio_wake_up_check(void); /* Defined in drivers/gpio.c. */ -#endif - -extern int cris_hlt_counter; - -/* We use this if we don't have any better idle routine. */ -void default_idle(void) -{ - local_irq_disable(); - if (!need_resched() && !cris_hlt_counter) { - /* Halt until exception. */ - __asm__ volatile("ei \n\t" - "halt "); - } - local_irq_enable(); -} - -/* - * Free current thread data structures etc.. - */ - -extern void deconfigure_bp(long pid); -void exit_thread(void) -{ - deconfigure_bp(current->pid); -} - -/* - * If the watchdog is enabled, disable interrupts and enter an infinite loop. - * The watchdog will reset the CPU after 0.1s. If the watchdog isn't enabled - * then enable it and wait. - */ -extern void arch_enable_nmi(void); - -void -hard_reset_now(void) -{ - /* - * Don't declare this variable elsewhere. We don't want any other - * code to know about it than the watchdog handler in entry.S and - * this code, implementing hard reset through the watchdog. - */ -#if defined(CONFIG_ETRAX_WATCHDOG) - extern int cause_of_death; -#endif - - printk("*** HARD RESET ***\n"); - local_irq_disable(); - -#if defined(CONFIG_ETRAX_WATCHDOG) - cause_of_death = 0xbedead; -#else -{ - reg_timer_rw_wd_ctrl wd_ctrl = {0}; - - stop_watchdog(); - - wd_ctrl.key = 16; /* Arbitrary key. */ - wd_ctrl.cnt = 1; /* Minimum time. */ - wd_ctrl.cmd = regk_timer_start; - - arch_enable_nmi(); - REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl); -} -#endif - - while (1) - ; /* Wait for reset. */ -} - -/* - * Return saved PC of a blocked thread. - */ -unsigned long thread_saved_pc(struct task_struct *t) -{ - return (unsigned long)user_regs(t->thread_info)->erp; -} - -static void -kernel_thread_helper(void* dummy, int (*fn)(void *), void * arg) -{ - fn(arg); - do_exit(-1); /* Should never be called, return bad exit value. */ -} - -/* Create a kernel thread. */ -int -kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) -{ - struct pt_regs regs; - - memset(®s, 0, sizeof(regs)); - - /* Don't use r10 since that is set to 0 in copy_thread. */ - regs.r11 = (unsigned long) fn; - regs.r12 = (unsigned long) arg; - regs.erp = (unsigned long) kernel_thread_helper; - regs.ccs = 1 << (I_CCS_BITNR + CCS_SHIFT); - - /* Create the new process. */ - return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); -} - -/* - * Setup the child's kernel stack with a pt_regs and call switch_stack() on it. - * It will be unnested during _resume and _ret_from_sys_call when the new thread - * is scheduled. - * - * Also setup the thread switching structure which is used to keep - * thread-specific data during _resumes. - */ - -extern asmlinkage void ret_from_fork(void); - -int -copy_thread(int nr, unsigned long clone_flags, unsigned long usp, - unsigned long unused, - struct task_struct *p, struct pt_regs *regs) -{ - struct pt_regs *childregs; - struct switch_stack *swstack; - - /* - * Put the pt_regs structure at the end of the new kernel stack page and - * fix it up. Note: the task_struct doubles as the kernel stack for the - * task. - */ - childregs = user_regs(p->thread_info); - *childregs = *regs; /* Struct copy of pt_regs. */ - p->set_child_tid = p->clear_child_tid = NULL; - childregs->r10 = 0; /* Child returns 0 after a fork/clone. */ - - /* Set a new TLS ? - * The TLS is in $mof beacuse it is the 5th argument to sys_clone. - */ - if (p->mm && (clone_flags & CLONE_SETTLS)) { - p->thread_info->tls = regs->mof; - } - - /* Put the switch stack right below the pt_regs. */ - swstack = ((struct switch_stack *) childregs) - 1; - - /* Paramater to ret_from_sys_call. 0 is don't restart the syscall. */ - swstack->r9 = 0; - - /* - * We want to return into ret_from_sys_call after the _resume. - * ret_from_fork will call ret_from_sys_call. - */ - swstack->return_ip = (unsigned long) ret_from_fork; - - /* Fix the user-mode and kernel-mode stackpointer. */ - p->thread.usp = usp; - p->thread.ksp = (unsigned long) swstack; - - return 0; -} - -/* - * Be aware of the "magic" 7th argument in the four system-calls below. - * They need the latest stackframe, which is put as the 7th argument by - * entry.S. The previous arguments are dummies or actually used, but need - * to be defined to reach the 7th argument. - * - * N.B.: Another method to get the stackframe is to use current_regs(). But - * it returns the latest stack-frame stacked when going from _user mode_ and - * some of these (at least sys_clone) are called from kernel-mode sometimes - * (for example during kernel_thread, above) and thus cannot use it. Thus, - * to be sure not to get any surprises, we use the method for the other calls - * as well. - */ -asmlinkage int -sys_fork(long r10, long r11, long r12, long r13, long mof, long srp, - struct pt_regs *regs) -{ - return do_fork(SIGCHLD, rdusp(), regs, 0, NULL, NULL); -} - -/* FIXME: Is parent_tid/child_tid really third/fourth argument? Update lib? */ -asmlinkage int -sys_clone(unsigned long newusp, unsigned long flags, int *parent_tid, int *child_tid, - unsigned long tls, long srp, struct pt_regs *regs) -{ - if (!newusp) - newusp = rdusp(); - - return do_fork(flags, newusp, regs, 0, parent_tid, child_tid); -} - -/* - * vfork is a system call in i386 because of register-pressure - maybe - * we can remove it and handle it in libc but we put it here until then. - */ -asmlinkage int -sys_vfork(long r10, long r11, long r12, long r13, long mof, long srp, - struct pt_regs *regs) -{ - return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0, NULL, NULL); -} - -/* sys_execve() executes a new program. */ -asmlinkage int -sys_execve(const char *fname, char **argv, char **envp, long r13, long mof, long srp, - struct pt_regs *regs) -{ - int error; - char *filename; - - filename = getname(fname); - error = PTR_ERR(filename); - - if (IS_ERR(filename)) - goto out; - - error = do_execve(filename, argv, envp, regs); - putname(filename); - out: - return error; -} - -unsigned long -get_wchan(struct task_struct *p) -{ - /* TODO */ - return 0; -} -#undef last_sched -#undef first_sched - -void show_regs(struct pt_regs * regs) -{ - unsigned long usp = rdusp(); - printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n", - regs->erp, regs->srp, regs->ccs, usp, regs->mof); - - printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", - regs->r0, regs->r1, regs->r2, regs->r3); - - printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", - regs->r4, regs->r5, regs->r6, regs->r7); - - printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", - regs->r8, regs->r9, regs->r10, regs->r11); - - printk("r12: %08lx r13: %08lx oR10: %08lx\n", - regs->r12, regs->r13, regs->orig_r10); -} diff --git a/trunk/arch/cris/arch-v32/kernel/ptrace.c b/trunk/arch/cris/arch-v32/kernel/ptrace.c deleted file mode 100644 index 208489da2a87..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/ptrace.c +++ /dev/null @@ -1,597 +0,0 @@ -/* - * Copyright (C) 2000-2003, Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* - * Determines which bits in CCS the user has access to. - * 1 = access, 0 = no access. - */ -#define CCS_MASK 0x00087c00 /* SXNZVC */ - -#define SBIT_USER (1 << (S_CCS_BITNR + CCS_SHIFT)) - -static int put_debugreg(long pid, unsigned int regno, long data); -static long get_debugreg(long pid, unsigned int regno); -static unsigned long get_pseudo_pc(struct task_struct *child); -void deconfigure_bp(long pid); - -extern unsigned long cris_signal_return_page; - -/* - * Get contents of register REGNO in task TASK. - */ -long get_reg(struct task_struct *task, unsigned int regno) -{ - /* USP is a special case, it's not in the pt_regs struct but - * in the tasks thread struct - */ - unsigned long ret; - - if (regno <= PT_EDA) - ret = ((unsigned long *)user_regs(task->thread_info))[regno]; - else if (regno == PT_USP) - ret = task->thread.usp; - else if (regno == PT_PPC) - ret = get_pseudo_pc(task); - else if (regno <= PT_MAX) - ret = get_debugreg(task->pid, regno); - else - ret = 0; - - return ret; -} - -/* - * Write contents of register REGNO in task TASK. - */ -int put_reg(struct task_struct *task, unsigned int regno, unsigned long data) -{ - if (regno <= PT_EDA) - ((unsigned long *)user_regs(task->thread_info))[regno] = data; - else if (regno == PT_USP) - task->thread.usp = data; - else if (regno == PT_PPC) { - /* Write pseudo-PC to ERP only if changed. */ - if (data != get_pseudo_pc(task)) - ((unsigned long *)user_regs(task->thread_info))[PT_ERP] = data; - } else if (regno <= PT_MAX) - return put_debugreg(task->pid, regno, data); - else - return -1; - return 0; -} - -/* - * Called by kernel/ptrace.c when detaching. - * - * Make sure the single step bit is not set. - */ -void -ptrace_disable(struct task_struct *child) -{ - unsigned long tmp; - - /* Deconfigure SPC and S-bit. */ - tmp = get_reg(child, PT_CCS) & ~SBIT_USER; - put_reg(child, PT_CCS, tmp); - put_reg(child, PT_SPC, 0); - - /* Deconfigure any watchpoints associated with the child. */ - deconfigure_bp(child->pid); -} - - -asmlinkage int -sys_ptrace(long request, long pid, long addr, long data) -{ - struct task_struct *child; - int ret; - unsigned long __user *datap = (unsigned long __user *)data; - - lock_kernel(); - ret = -EPERM; - - if (request == PTRACE_TRACEME) { - /* are we already being traced? */ - if (current->ptrace & PT_PTRACED) - goto out; - ret = security_ptrace(current->parent, current); - if (ret) - goto out; - /* set the ptrace bit in the process flags. */ - current->ptrace |= PT_PTRACED; - ret = 0; - goto out; - } - - ret = -ESRCH; - read_lock(&tasklist_lock); - child = find_task_by_pid(pid); - - if (child) - get_task_struct(child); - - read_unlock(&tasklist_lock); - - if (!child) - goto out; - - ret = -EPERM; - - if (pid == 1) /* Leave the init process alone! */ - goto out_tsk; - - if (request == PTRACE_ATTACH) { - ret = ptrace_attach(child); - goto out_tsk; - } - - ret = ptrace_check_attach(child, request == PTRACE_KILL); - if (ret < 0) - goto out_tsk; - - switch (request) { - /* Read word at location address. */ - case PTRACE_PEEKTEXT: - case PTRACE_PEEKDATA: { - unsigned long tmp; - int copied; - - ret = -EIO; - - /* The signal trampoline page is outside the normal user-addressable - * space but still accessible. This is hack to make it possible to - * access the signal handler code in GDB. - */ - if ((addr & PAGE_MASK) == cris_signal_return_page) { - /* The trampoline page is globally mapped, no page table to traverse.*/ - tmp = *(unsigned long*)addr; - } else { - copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); - - if (copied != sizeof(tmp)) - break; - } - - ret = put_user(tmp,datap); - break; - } - - /* Read the word at location address in the USER area. */ - case PTRACE_PEEKUSR: { - unsigned long tmp; - - ret = -EIO; - if ((addr & 3) || addr < 0 || addr > PT_MAX << 2) - break; - - tmp = get_reg(child, addr >> 2); - ret = put_user(tmp, datap); - break; - } - - /* Write the word at location address. */ - case PTRACE_POKETEXT: - case PTRACE_POKEDATA: - ret = 0; - - if (access_process_vm(child, addr, &data, sizeof(data), 1) == sizeof(data)) - break; - - ret = -EIO; - break; - - /* Write the word at location address in the USER area. */ - case PTRACE_POKEUSR: - ret = -EIO; - if ((addr & 3) || addr < 0 || addr > PT_MAX << 2) - break; - - addr >>= 2; - - if (addr == PT_CCS) { - /* don't allow the tracing process to change stuff like - * interrupt enable, kernel/user bit, dma enables etc. - */ - data &= CCS_MASK; - data |= get_reg(child, PT_CCS) & ~CCS_MASK; - } - if (put_reg(child, addr, data)) - break; - ret = 0; - break; - - case PTRACE_SYSCALL: - case PTRACE_CONT: - ret = -EIO; - - if (!valid_signal(data)) - break; - - /* Continue means no single-step. */ - put_reg(child, PT_SPC, 0); - - if (!get_debugreg(child->pid, PT_BP_CTRL)) { - unsigned long tmp; - /* If no h/w bp configured, disable S bit. */ - tmp = get_reg(child, PT_CCS) & ~SBIT_USER; - put_reg(child, PT_CCS, tmp); - } - - if (request == PTRACE_SYSCALL) { - set_tsk_thread_flag(child, TIF_SYSCALL_TRACE); - } - else { - clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); - } - - child->exit_code = data; - - /* TODO: make sure any pending breakpoint is killed */ - wake_up_process(child); - ret = 0; - - break; - - /* Make the child exit by sending it a sigkill. */ - case PTRACE_KILL: - ret = 0; - - if (child->exit_state == EXIT_ZOMBIE) - break; - - child->exit_code = SIGKILL; - - /* Deconfigure single-step and h/w bp. */ - ptrace_disable(child); - - /* TODO: make sure any pending breakpoint is killed */ - wake_up_process(child); - break; - - /* Set the trap flag. */ - case PTRACE_SINGLESTEP: { - unsigned long tmp; - ret = -EIO; - - /* Set up SPC if not set already (in which case we have - no other choice but to trust it). */ - if (!get_reg(child, PT_SPC)) { - /* In case we're stopped in a delay slot. */ - tmp = get_reg(child, PT_ERP) & ~1; - put_reg(child, PT_SPC, tmp); - } - tmp = get_reg(child, PT_CCS) | SBIT_USER; - put_reg(child, PT_CCS, tmp); - - if (!valid_signal(data)) - break; - - clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); - - /* TODO: set some clever breakpoint mechanism... */ - - child->exit_code = data; - wake_up_process(child); - ret = 0; - break; - - } - case PTRACE_DETACH: - ret = ptrace_detach(child, data); - break; - - /* Get all GP registers from the child. */ - case PTRACE_GETREGS: { - int i; - unsigned long tmp; - - for (i = 0; i <= PT_MAX; i++) { - tmp = get_reg(child, i); - - if (put_user(tmp, datap)) { - ret = -EFAULT; - goto out_tsk; - } - - datap++; - } - - ret = 0; - break; - } - - /* Set all GP registers in the child. */ - case PTRACE_SETREGS: { - int i; - unsigned long tmp; - - for (i = 0; i <= PT_MAX; i++) { - if (get_user(tmp, datap)) { - ret = -EFAULT; - goto out_tsk; - } - - if (i == PT_CCS) { - tmp &= CCS_MASK; - tmp |= get_reg(child, PT_CCS) & ~CCS_MASK; - } - - put_reg(child, i, tmp); - datap++; - } - - ret = 0; - break; - } - - default: - ret = ptrace_request(child, request, addr, data); - break; - } -out_tsk: - put_task_struct(child); -out: - unlock_kernel(); - return ret; -} - -void do_syscall_trace(void) -{ - if (!test_thread_flag(TIF_SYSCALL_TRACE)) - return; - - if (!(current->ptrace & PT_PTRACED)) - return; - - /* the 0x80 provides a way for the tracing parent to distinguish - between a syscall stop and SIGTRAP delivery */ - ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) - ? 0x80 : 0)); - - /* - * This isn't the same as continuing with a signal, but it will do for - * normal use. - */ - if (current->exit_code) { - send_sig(current->exit_code, current, 1); - current->exit_code = 0; - } -} - -/* Returns the size of an instruction that has a delay slot. */ - -static int insn_size(struct task_struct *child, unsigned long pc) -{ - unsigned long opcode; - int copied; - int opsize = 0; - - /* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */ - copied = access_process_vm(child, pc, &opcode, sizeof(opcode), 0); - if (copied != sizeof(opcode)) - return 0; - - switch ((opcode & 0x0f00) >> 8) { - case 0x0: - case 0x9: - case 0xb: - opsize = 2; - break; - case 0xe: - case 0xf: - opsize = 6; - break; - case 0xd: - /* Could be 4 or 6; check more bits. */ - if ((opcode & 0xff) == 0xff) - opsize = 4; - else - opsize = 6; - break; - default: - panic("ERROR: Couldn't find size of opcode 0x%lx at 0x%lx\n", - opcode, pc); - } - - return opsize; -} - -static unsigned long get_pseudo_pc(struct task_struct *child) -{ - /* Default value for PC is ERP. */ - unsigned long pc = get_reg(child, PT_ERP); - - if (pc & 0x1) { - unsigned long spc = get_reg(child, PT_SPC); - /* Delay slot bit set. Report as stopped on proper - instruction. */ - if (spc) { - /* Rely on SPC if set. FIXME: We might want to check - that EXS indicates we stopped due to a single-step - exception. */ - pc = spc; - } else { - /* Calculate the PC from the size of the instruction - that the delay slot we're in belongs to. */ - pc += insn_size(child, pc & ~1) - 1; - } - } - return pc; -} - -static long bp_owner = 0; - -/* Reachable from exit_thread in signal.c, so not static. */ -void deconfigure_bp(long pid) -{ - int bp; - - /* Only deconfigure if the pid is the owner. */ - if (bp_owner != pid) - return; - - for (bp = 0; bp < 6; bp++) { - unsigned long tmp; - /* Deconfigure start and end address (also gets rid of ownership). */ - put_debugreg(pid, PT_BP + 3 + (bp * 2), 0); - put_debugreg(pid, PT_BP + 4 + (bp * 2), 0); - - /* Deconfigure relevant bits in control register. */ - tmp = get_debugreg(pid, PT_BP_CTRL) & ~(3 << (2 + (bp * 4))); - put_debugreg(pid, PT_BP_CTRL, tmp); - } - /* No owner now. */ - bp_owner = 0; -} - -static int put_debugreg(long pid, unsigned int regno, long data) -{ - int ret = 0; - register int old_srs; - -#ifdef CONFIG_ETRAX_KGDB - /* Ignore write, but pretend it was ok if value is 0 - (we don't want POKEUSR/SETREGS failing unnessecarily). */ - return (data == 0) ? ret : -1; -#endif - - /* Simple owner management. */ - if (!bp_owner) - bp_owner = pid; - else if (bp_owner != pid) { - /* Ignore write, but pretend it was ok if value is 0 - (we don't want POKEUSR/SETREGS failing unnessecarily). */ - return (data == 0) ? ret : -1; - } - - /* Remember old SRS. */ - SPEC_REG_RD(SPEC_REG_SRS, old_srs); - /* Switch to BP bank. */ - SUPP_BANK_SEL(BANK_BP); - - switch (regno - PT_BP) { - case 0: - SUPP_REG_WR(0, data); break; - case 1: - case 2: - if (data) - ret = -1; - break; - case 3: - SUPP_REG_WR(3, data); break; - case 4: - SUPP_REG_WR(4, data); break; - case 5: - SUPP_REG_WR(5, data); break; - case 6: - SUPP_REG_WR(6, data); break; - case 7: - SUPP_REG_WR(7, data); break; - case 8: - SUPP_REG_WR(8, data); break; - case 9: - SUPP_REG_WR(9, data); break; - case 10: - SUPP_REG_WR(10, data); break; - case 11: - SUPP_REG_WR(11, data); break; - case 12: - SUPP_REG_WR(12, data); break; - case 13: - SUPP_REG_WR(13, data); break; - case 14: - SUPP_REG_WR(14, data); break; - default: - ret = -1; - break; - } - - /* Restore SRS. */ - SPEC_REG_WR(SPEC_REG_SRS, old_srs); - /* Just for show. */ - NOP(); - NOP(); - NOP(); - - return ret; -} - -static long get_debugreg(long pid, unsigned int regno) -{ - register int old_srs; - register long data; - - if (pid != bp_owner) { - return 0; - } - - /* Remember old SRS. */ - SPEC_REG_RD(SPEC_REG_SRS, old_srs); - /* Switch to BP bank. */ - SUPP_BANK_SEL(BANK_BP); - - switch (regno - PT_BP) { - case 0: - SUPP_REG_RD(0, data); break; - case 1: - case 2: - /* error return value? */ - data = 0; - break; - case 3: - SUPP_REG_RD(3, data); break; - case 4: - SUPP_REG_RD(4, data); break; - case 5: - SUPP_REG_RD(5, data); break; - case 6: - SUPP_REG_RD(6, data); break; - case 7: - SUPP_REG_RD(7, data); break; - case 8: - SUPP_REG_RD(8, data); break; - case 9: - SUPP_REG_RD(9, data); break; - case 10: - SUPP_REG_RD(10, data); break; - case 11: - SUPP_REG_RD(11, data); break; - case 12: - SUPP_REG_RD(12, data); break; - case 13: - SUPP_REG_RD(13, data); break; - case 14: - SUPP_REG_RD(14, data); break; - default: - /* error return value? */ - data = 0; - } - - /* Restore SRS. */ - SPEC_REG_WR(SPEC_REG_SRS, old_srs); - /* Just for show. */ - NOP(); - NOP(); - NOP(); - - return data; -} diff --git a/trunk/arch/cris/arch-v32/kernel/setup.c b/trunk/arch/cris/arch-v32/kernel/setup.c deleted file mode 100644 index b17a39a2e164..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/setup.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Display CPU info in /proc/cpuinfo. - * - * Copyright (C) 2003, Axis Communications AB. - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_PROC_FS - -#define HAS_FPU 0x0001 -#define HAS_MMU 0x0002 -#define HAS_ETHERNET100 0x0004 -#define HAS_TOKENRING 0x0008 -#define HAS_SCSI 0x0010 -#define HAS_ATA 0x0020 -#define HAS_USB 0x0040 -#define HAS_IRQ_BUG 0x0080 -#define HAS_MMU_BUG 0x0100 - -struct cpu_info { - char *cpu_model; - unsigned short rev; - unsigned short cache_size; - unsigned short flags; -}; - -/* Some of these model are here for historical reasons only. */ -static struct cpu_info cpinfo[] = { - {"ETRAX 1", 0, 0, 0}, - {"ETRAX 2", 1, 0, 0}, - {"ETRAX 3", 2, 0, 0}, - {"ETRAX 4", 3, 0, 0}, - {"Simulator", 7, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA}, - {"ETRAX 100", 8, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG}, - {"ETRAX 100", 9, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA}, - - {"ETRAX 100LX", 10, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB - | HAS_MMU | HAS_MMU_BUG}, - - {"ETRAX 100LX v2", 11, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB - | HAS_MMU}, - - {"ETRAX FS", 32, 32, HAS_ETHERNET100 | HAS_ATA | HAS_MMU}, - - {"Unknown", 0, 0, 0} -}; - -int -show_cpuinfo(struct seq_file *m, void *v) -{ - int i; - int cpu = (int)v - 1; - int entries; - unsigned long revision; - struct cpu_info *info; - - entries = sizeof cpinfo / sizeof(struct cpu_info); - info = &cpinfo[entries - 1]; - -#ifdef CONFIG_SMP - if (!cpu_online(cpu)) - return 0; -#endif - - revision = rdvr(); - - for (i = 0; i < entries; i++) { - if (cpinfo[i].rev == revision) { - info = &cpinfo[i]; - break; - } - } - - return seq_printf(m, - "processor\t: %d\n" - "cpu\t\t: CRIS\n" - "cpu revision\t: %lu\n" - "cpu model\t: %s\n" - "cache size\t: %d KB\n" - "fpu\t\t: %s\n" - "mmu\t\t: %s\n" - "mmu DMA bug\t: %s\n" - "ethernet\t: %s Mbps\n" - "token ring\t: %s\n" - "scsi\t\t: %s\n" - "ata\t\t: %s\n" - "usb\t\t: %s\n" - "bogomips\t: %lu.%02lu\n\n", - - cpu, - revision, - info->cpu_model, - info->cache_size, - info->flags & HAS_FPU ? "yes" : "no", - info->flags & HAS_MMU ? "yes" : "no", - info->flags & HAS_MMU_BUG ? "yes" : "no", - info->flags & HAS_ETHERNET100 ? "10/100" : "10", - info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no", - info->flags & HAS_SCSI ? "yes" : "no", - info->flags & HAS_ATA ? "yes" : "no", - info->flags & HAS_USB ? "yes" : "no", - (loops_per_jiffy * HZ + 500) / 500000, - ((loops_per_jiffy * HZ + 500) / 5000) % 100); -} - -#endif /* CONFIG_PROC_FS */ - -void -show_etrax_copyright(void) -{ - printk(KERN_INFO - "Linux/CRISv32 port on ETRAX FS (C) 2003, 2004 Axis Communications AB\n"); -} diff --git a/trunk/arch/cris/arch-v32/kernel/signal.c b/trunk/arch/cris/arch-v32/kernel/signal.c deleted file mode 100644 index fb4c79d5b76b..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/signal.c +++ /dev/null @@ -1,708 +0,0 @@ -/* - * Copyright (C) 2003, Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -extern unsigned long cris_signal_return_page; - -/* Flag to check if a signal is blockable. */ -#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) - -/* - * A syscall in CRIS is really a "break 13" instruction, which is 2 - * bytes. The registers is manipulated so upon return the instruction - * will be executed again. - * - * This relies on that PC points to the instruction after the break call. - */ -#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->erp -= 2; - -/* Signal frames. */ -struct signal_frame { - struct sigcontext sc; - unsigned long extramask[_NSIG_WORDS - 1]; - unsigned char retcode[8]; /* Trampoline code. */ -}; - -struct rt_signal_frame { - struct siginfo *pinfo; - void *puc; - struct siginfo info; - struct ucontext uc; - unsigned char retcode[8]; /* Trampoline code. */ -}; - -int do_signal(int restart, sigset_t *oldset, struct pt_regs *regs); -void keep_debug_flags(unsigned long oldccs, unsigned long oldspc, - struct pt_regs *regs); -/* - * Swap in the new signal mask, and wait for a signal. Define some - * dummy arguments to be able to reach the regs argument. - */ -int -sys_sigsuspend(old_sigset_t mask, long r11, long r12, long r13, long mof, - long srp, struct pt_regs *regs) -{ - sigset_t saveset; - - mask &= _BLOCKABLE; - - spin_lock_irq(¤t->sighand->siglock); - - saveset = current->blocked; - - siginitset(¤t->blocked, mask); - - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - regs->r10 = -EINTR; - - while (1) { - current->state = TASK_INTERRUPTIBLE; - schedule(); - - if (do_signal(0, &saveset, regs)) { - /* - * This point is reached twice: once to call - * the signal handler, then again to return - * from the sigsuspend system call. When - * calling the signal handler, R10 hold the - * signal number as set by do_signal(). The - * sigsuspend call will always return with - * the restored value above; -EINTR. - */ - return regs->r10; - } - } -} - -/* Define some dummy arguments to be able to reach the regs argument. */ -int -sys_rt_sigsuspend(sigset_t *unewset, size_t sigsetsize, long r12, long r13, - long mof, long srp, struct pt_regs *regs) -{ - sigset_t saveset; - sigset_t newset; - - if (sigsetsize != sizeof(sigset_t)) - return -EINVAL; - - if (copy_from_user(&newset, unewset, sizeof(newset))) - return -EFAULT; - - sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - - saveset = current->blocked; - current->blocked = newset; - - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - regs->r10 = -EINTR; - - while (1) { - current->state = TASK_INTERRUPTIBLE; - schedule(); - - if (do_signal(0, &saveset, regs)) { - /* See comment in function above. */ - return regs->r10; - } - } -} - -int -sys_sigaction(int signal, const struct old_sigaction *act, - struct old_sigaction *oact) -{ - int retval; - struct k_sigaction newk; - struct k_sigaction oldk; - - if (act) { - old_sigset_t mask; - - if (!access_ok(VERIFY_READ, act, sizeof(*act)) || - __get_user(newk.sa.sa_handler, &act->sa_handler) || - __get_user(newk.sa.sa_restorer, &act->sa_restorer)) - return -EFAULT; - - __get_user(newk.sa.sa_flags, &act->sa_flags); - __get_user(mask, &act->sa_mask); - siginitset(&newk.sa.sa_mask, mask); - } - - retval = do_sigaction(signal, act ? &newk : NULL, oact ? &oldk : NULL); - - if (!retval && oact) { - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || - __put_user(oldk.sa.sa_handler, &oact->sa_handler) || - __put_user(oldk.sa.sa_restorer, &oact->sa_restorer)) - return -EFAULT; - - __put_user(oldk.sa.sa_flags, &oact->sa_flags); - __put_user(oldk.sa.sa_mask.sig[0], &oact->sa_mask); - } - - return retval; -} - -int -sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss) -{ - return do_sigaltstack(uss, uoss, rdusp()); -} - -static int -restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) -{ - unsigned int err = 0; - unsigned long old_usp; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - /* - * Restore the registers from &sc->regs. sc is already checked - * for VERIFY_READ since the signal_frame was previously - * checked in sys_sigreturn(). - */ - if (__copy_from_user(regs, sc, sizeof(struct pt_regs))) - goto badframe; - - /* Make that the user-mode flag is set. */ - regs->ccs |= (1 << (U_CCS_BITNR + CCS_SHIFT)); - - /* Restore the old USP. */ - err |= __get_user(old_usp, &sc->usp); - wrusp(old_usp); - - return err; - -badframe: - return 1; -} - -/* Define some dummy arguments to be able to reach the regs argument. */ -asmlinkage int -sys_sigreturn(long r10, long r11, long r12, long r13, long mof, long srp, - struct pt_regs *regs) -{ - sigset_t set; - struct signal_frame __user *frame; - unsigned long oldspc = regs->spc; - unsigned long oldccs = regs->ccs; - - frame = (struct signal_frame *) rdusp(); - - /* - * Since the signal is stacked on a dword boundary, the frame - * should be dword aligned here as well. It it's not, then the - * user is trying some funny business. - */ - if (((long)frame) & 3) - goto badframe; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - - if (__get_user(set.sig[0], &frame->sc.oldmask) || - (_NSIG_WORDS > 1 && __copy_from_user(&set.sig[1], - frame->extramask, - sizeof(frame->extramask)))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - - current->blocked = set; - - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - if (restore_sigcontext(regs, &frame->sc)) - goto badframe; - - keep_debug_flags(oldccs, oldspc, regs); - - return regs->r10; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -/* Define some dummy variables to be able to reach the regs argument. */ -asmlinkage int -sys_rt_sigreturn(long r10, long r11, long r12, long r13, long mof, long srp, - struct pt_regs *regs) -{ - sigset_t set; - struct rt_signal_frame __user *frame; - unsigned long oldspc = regs->spc; - unsigned long oldccs = regs->ccs; - - frame = (struct rt_signal_frame *) rdusp(); - - /* - * Since the signal is stacked on a dword boundary, the frame - * should be dword aligned here as well. It it's not, then the - * user is trying some funny business. - */ - if (((long)frame) & 3) - goto badframe; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - - current->blocked = set; - - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - if (restore_sigcontext(regs, &frame->uc.uc_mcontext)) - goto badframe; - - if (do_sigaltstack(&frame->uc.uc_stack, NULL, rdusp()) == -EFAULT) - goto badframe; - - keep_debug_flags(oldccs, oldspc, regs); - - return regs->r10; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -/* Setup a signal frame. */ -static int -setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, - unsigned long mask) -{ - int err; - unsigned long usp; - - err = 0; - usp = rdusp(); - - /* - * Copy the registers. They are located first in sc, so it's - * possible to use sc directly. - */ - err |= __copy_to_user(sc, regs, sizeof(struct pt_regs)); - - err |= __put_user(mask, &sc->oldmask); - err |= __put_user(usp, &sc->usp); - - return err; -} - -/* Figure out where to put the new signal frame - usually on the stack. */ -static inline void __user * -get_sigframe(struct k_sigaction *ka, struct pt_regs * regs, size_t frame_size) -{ - unsigned long sp; - - sp = rdusp(); - - /* This is the X/Open sanctioned signal stack switching. */ - if (ka->sa.sa_flags & SA_ONSTACK) { - if (!on_sig_stack(sp)) - sp = current->sas_ss_sp + current->sas_ss_size; - } - - /* Make sure the frame is dword-aligned. */ - sp &= ~3; - - return (void __user *)(sp - frame_size); -} - -/* Grab and setup a signal frame. - * - * Basically a lot of state-info is stacked, and arranged for the - * user-mode program to return to the kernel using either a trampiline - * which performs the syscall sigreturn(), or a provided user-mode - * trampoline. - */ -static void -setup_frame(int sig, struct k_sigaction *ka, sigset_t *set, - struct pt_regs * regs) -{ - int err; - unsigned long return_ip; - struct signal_frame __user *frame; - - err = 0; - frame = get_sigframe(ka, regs, sizeof(*frame)); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - goto give_sigsegv; - - err |= setup_sigcontext(&frame->sc, regs, set->sig[0]); - - if (err) - goto give_sigsegv; - - if (_NSIG_WORDS > 1) { - err |= __copy_to_user(frame->extramask, &set->sig[1], - sizeof(frame->extramask)); - } - - if (err) - goto give_sigsegv; - - /* - * Set up to return from user-space. If provided, use a stub - * already located in user-space. - */ - if (ka->sa.sa_flags & SA_RESTORER) { - return_ip = (unsigned long)ka->sa.sa_restorer; - } else { - /* Trampoline - the desired return ip is in the signal return page. */ - return_ip = cris_signal_return_page; - - /* - * This is movu.w __NR_sigreturn, r9; break 13; - * - * WE DO NOT USE IT ANY MORE! It's only left here for historical - * reasons and because gdb uses it as a signature to notice - * signal handler stack frames. - */ - err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0)); - err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2)); - err |= __put_user(0xe93d, (short __user*)(frame->retcode+4)); - } - - if (err) - goto give_sigsegv; - - /* - * Set up registers for signal handler. - * - * Where the code enters now. - * Where the code enter later. - * First argument, signo. - */ - regs->erp = (unsigned long) ka->sa.sa_handler; - regs->srp = return_ip; - regs->r10 = sig; - - /* Actually move the USP to reflect the stacked frame. */ - wrusp((unsigned long)frame); - - return; - -give_sigsegv: - if (sig == SIGSEGV) - ka->sa.sa_handler = SIG_DFL; - - force_sig(SIGSEGV, current); -} - -static void -setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs * regs) -{ - int err; - unsigned long return_ip; - struct rt_signal_frame __user *frame; - - err = 0; - frame = get_sigframe(ka, regs, sizeof(*frame)); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - goto give_sigsegv; - - /* TODO: what is the current->exec_domain stuff and invmap ? */ - - err |= __put_user(&frame->info, &frame->pinfo); - err |= __put_user(&frame->uc, &frame->puc); - err |= copy_siginfo_to_user(&frame->info, info); - - if (err) - goto give_sigsegv; - - /* Clear all the bits of the ucontext we don't use. */ - err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext)); - err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]); - err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); - - if (err) - goto give_sigsegv; - - /* - * Set up to return from user-space. If provided, use a stub - * already located in user-space. - */ - if (ka->sa.sa_flags & SA_RESTORER) { - return_ip = (unsigned long) ka->sa.sa_restorer; - } else { - /* Trampoline - the desired return ip is in the signal return page. */ - return_ip = cris_signal_return_page + 6; - - /* - * This is movu.w __NR_rt_sigreturn, r9; break 13; - * - * WE DO NOT USE IT ANY MORE! It's only left here for historical - * reasons and because gdb uses it as a signature to notice - * signal handler stack frames. - */ - err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0)); - - err |= __put_user(__NR_rt_sigreturn, - (short __user*)(frame->retcode+2)); - - err |= __put_user(0xe93d, (short __user*)(frame->retcode+4)); - } - - if (err) - goto give_sigsegv; - - /* - * Set up registers for signal handler. - * - * Where the code enters now. - * Where the code enters later. - * First argument is signo. - * Second argument is (siginfo_t *). - * Third argument is unused. - */ - regs->erp = (unsigned long) ka->sa.sa_handler; - regs->srp = return_ip; - regs->r10 = sig; - regs->r11 = (unsigned long) &frame->info; - regs->r12 = 0; - - /* Actually move the usp to reflect the stacked frame. */ - wrusp((unsigned long)frame); - - return; - -give_sigsegv: - if (sig == SIGSEGV) - ka->sa.sa_handler = SIG_DFL; - - force_sig(SIGSEGV, current); -} - -/* Invoke a singal handler to, well, handle the signal. */ -extern inline void -handle_signal(int canrestart, unsigned long sig, - siginfo_t *info, struct k_sigaction *ka, - sigset_t *oldset, struct pt_regs * regs) -{ - /* Check if this got called from a system call. */ - if (canrestart) { - /* If so, check system call restarting. */ - switch (regs->r10) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - /* - * This means that the syscall should - * only be restarted if there was no - * handler for the signal, and since - * this point isn't reached unless - * there is a handler, there's no need - * to restart. - */ - regs->r10 = -EINTR; - break; - - case -ERESTARTSYS: - /* - * This means restart the syscall if - * there is no handler, or the handler - * was registered with SA_RESTART. - */ - if (!(ka->sa.sa_flags & SA_RESTART)) { - regs->r10 = -EINTR; - break; - } - - /* Fall through. */ - - case -ERESTARTNOINTR: - /* - * This means that the syscall should - * be called again after the signal - * handler returns. - */ - RESTART_CRIS_SYS(regs); - break; - } - } - - /* Set up the stack frame. */ - if (ka->sa.sa_flags & SA_SIGINFO) - setup_rt_frame(sig, ka, info, oldset, regs); - else - setup_frame(sig, ka, oldset, regs); - - if (ka->sa.sa_flags & SA_ONESHOT) - ka->sa.sa_handler = SIG_DFL; - - if (!(ka->sa.sa_flags & SA_NODEFER)) { - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); - sigaddset(¤t->blocked,sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - } -} - -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - * - * Also note that the regs structure given here as an argument, is the latest - * pushed pt_regs. It may or may not be the same as the first pushed registers - * when the initial usermode->kernelmode transition took place. Therefore - * we can use user_mode(regs) to see if we came directly from kernel or user - * mode below. - */ -int -do_signal(int canrestart, sigset_t *oldset, struct pt_regs *regs) -{ - int signr; - siginfo_t info; - struct k_sigaction ka; - - /* - * The common case should go fast, which is why this point is - * reached from kernel-mode. If that's the case, just return - * without doing anything. - */ - if (!user_mode(regs)) - return 1; - - if (!oldset) - oldset = ¤t->blocked; - - signr = get_signal_to_deliver(&info, &ka, regs, NULL); - - if (signr > 0) { - /* Deliver the signal. */ - handle_signal(canrestart, signr, &info, &ka, oldset, regs); - return 1; - } - - /* Got here from a system call? */ - if (canrestart) { - /* Restart the system call - no handlers present. */ - if (regs->r10 == -ERESTARTNOHAND || - regs->r10 == -ERESTARTSYS || - regs->r10 == -ERESTARTNOINTR) { - RESTART_CRIS_SYS(regs); - } - - if (regs->r10 == -ERESTART_RESTARTBLOCK){ - regs->r10 = __NR_restart_syscall; - regs->erp -= 2; - } - } - - return 0; -} - -asmlinkage void -ugdb_trap_user(struct thread_info *ti, int sig) -{ - if (((user_regs(ti)->exs & 0xff00) >> 8) != SINGLE_STEP_INTR_VECT) { - /* Zero single-step PC if the reason we stopped wasn't a single - step exception. This is to avoid relying on it when it isn't - reliable. */ - user_regs(ti)->spc = 0; - } - /* FIXME: Filter out false h/w breakpoint hits (i.e. EDA - not withing any configured h/w breakpoint range). Synchronize with - what already exists for kernel debugging. */ - if (((user_regs(ti)->exs & 0xff00) >> 8) == BREAK_8_INTR_VECT) { - /* Break 8: subtract 2 from ERP unless in a delay slot. */ - if (!(user_regs(ti)->erp & 0x1)) - user_regs(ti)->erp -= 2; - } - sys_kill(ti->task->pid, sig); -} - -void -keep_debug_flags(unsigned long oldccs, unsigned long oldspc, - struct pt_regs *regs) -{ - if (oldccs & (1 << Q_CCS_BITNR)) { - /* Pending single step due to single-stepping the break 13 - in the signal trampoline: keep the Q flag. */ - regs->ccs |= (1 << Q_CCS_BITNR); - /* S flag should be set - complain if it's not. */ - if (!(oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT)))) { - printk("Q flag but no S flag?"); - } - regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); - /* Assume the SPC is valid and interesting. */ - regs->spc = oldspc; - - } else if (oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT))) { - /* If a h/w bp was set in the signal handler we need - to keep the S flag. */ - regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); - /* Don't keep the old SPC though; if we got here due to - a single-step, the Q flag should have been set. */ - } else if (regs->spc) { - /* If we were single-stepping *before* the signal was taken, - we don't want to restore that state now, because GDB will - have forgotten all about it. */ - regs->spc = 0; - regs->ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT)); - } -} - -/* Set up the trampolines on the signal return page. */ -int __init -cris_init_signal(void) -{ - u16* data = (u16*)kmalloc(PAGE_SIZE, GFP_KERNEL); - - /* This is movu.w __NR_sigreturn, r9; break 13; */ - data[0] = 0x9c5f; - data[1] = __NR_sigreturn; - data[2] = 0xe93d; - /* This is movu.w __NR_rt_sigreturn, r9; break 13; */ - data[3] = 0x9c5f; - data[4] = __NR_rt_sigreturn; - data[5] = 0xe93d; - - /* Map to userspace with appropriate permissions (no write access...) */ - cris_signal_return_page = (unsigned long) - __ioremap_prot(virt_to_phys(data), PAGE_SIZE, PAGE_SIGNAL_TRAMPOLINE); - - return 0; -} - -__initcall(cris_init_signal); diff --git a/trunk/arch/cris/arch-v32/kernel/smp.c b/trunk/arch/cris/arch-v32/kernel/smp.c deleted file mode 100644 index 2c5cae04a95c..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/smp.c +++ /dev/null @@ -1,348 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define IPI_SCHEDULE 1 -#define IPI_CALL 2 -#define IPI_FLUSH_TLB 4 - -#define FLUSH_ALL (void*)0xffffffff - -/* Vector of locks used for various atomic operations */ -spinlock_t cris_atomic_locks[] = { [0 ... LOCK_COUNT - 1] = SPIN_LOCK_UNLOCKED}; - -/* CPU masks */ -cpumask_t cpu_online_map = CPU_MASK_NONE; -cpumask_t phys_cpu_present_map = CPU_MASK_NONE; - -/* Variables used during SMP boot */ -volatile int cpu_now_booting = 0; -volatile struct thread_info *smp_init_current_idle_thread; - -/* Variables used during IPI */ -static DEFINE_SPINLOCK(call_lock); -static DEFINE_SPINLOCK(tlbstate_lock); - -struct call_data_struct { - void (*func) (void *info); - void *info; - int wait; -}; - -static struct call_data_struct * call_data; - -static struct mm_struct* flush_mm; -static struct vm_area_struct* flush_vma; -static unsigned long flush_addr; - -extern int setup_irq(int, struct irqaction *); - -/* Mode registers */ -static unsigned long irq_regs[NR_CPUS] = -{ - regi_irq, - regi_irq2 -}; - -static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id, struct pt_regs *regs); -static int send_ipi(int vector, int wait, cpumask_t cpu_mask); -static struct irqaction irq_ipi = { crisv32_ipi_interrupt, SA_INTERRUPT, - CPU_MASK_NONE, "ipi", NULL, NULL}; - -extern void cris_mmu_init(void); -extern void cris_timer_init(void); - -/* SMP initialization */ -void __init smp_prepare_cpus(unsigned int max_cpus) -{ - int i; - - /* From now on we can expect IPIs so set them up */ - setup_irq(IPI_INTR_VECT, &irq_ipi); - - /* Mark all possible CPUs as present */ - for (i = 0; i < max_cpus; i++) - cpu_set(i, phys_cpu_present_map); -} - -void __devinit smp_prepare_boot_cpu(void) -{ - /* PGD pointer has moved after per_cpu initialization so - * update the MMU. - */ - pgd_t **pgd; - pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id()); - - SUPP_BANK_SEL(1); - SUPP_REG_WR(RW_MM_TLB_PGD, pgd); - SUPP_BANK_SEL(2); - SUPP_REG_WR(RW_MM_TLB_PGD, pgd); - - cpu_set(0, cpu_online_map); - cpu_set(0, phys_cpu_present_map); -} - -void __init smp_cpus_done(unsigned int max_cpus) -{ -} - -/* Bring one cpu online.*/ -static int __init -smp_boot_one_cpu(int cpuid) -{ - unsigned timeout; - struct task_struct *idle; - - idle = fork_idle(cpuid); - if (IS_ERR(idle)) - panic("SMP: fork failed for CPU:%d", cpuid); - - idle->thread_info->cpu = cpuid; - - /* Information to the CPU that is about to boot */ - smp_init_current_idle_thread = idle->thread_info; - cpu_now_booting = cpuid; - - /* Wait for CPU to come online */ - for (timeout = 0; timeout < 10000; timeout++) { - if(cpu_online(cpuid)) { - cpu_now_booting = 0; - smp_init_current_idle_thread = NULL; - return 0; /* CPU online */ - } - udelay(100); - barrier(); - } - - put_task_struct(idle); - idle = NULL; - - printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid); - return -1; -} - -/* Secondary CPUs starts uing C here. Here we need to setup CPU - * specific stuff such as the local timer and the MMU. */ -void __init smp_callin(void) -{ - extern void cpu_idle(void); - - int cpu = cpu_now_booting; - reg_intr_vect_rw_mask vect_mask = {0}; - - /* Initialise the idle task for this CPU */ - atomic_inc(&init_mm.mm_count); - current->active_mm = &init_mm; - - /* Set up MMU */ - cris_mmu_init(); - __flush_tlb_all(); - - /* Setup local timer. */ - cris_timer_init(); - - /* Enable IRQ and idle */ - REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask); - unmask_irq(IPI_INTR_VECT); - unmask_irq(TIMER_INTR_VECT); - local_irq_enable(); - - cpu_set(cpu, cpu_online_map); - cpu_idle(); -} - -/* Stop execution on this CPU.*/ -void stop_this_cpu(void* dummy) -{ - local_irq_disable(); - asm volatile("halt"); -} - -/* Other calls */ -void smp_send_stop(void) -{ - smp_call_function(stop_this_cpu, NULL, 1, 0); -} - -int setup_profiling_timer(unsigned int multiplier) -{ - return -EINVAL; -} - - -/* cache_decay_ticks is used by the scheduler to decide if a process - * is "hot" on one CPU. A higher value means a higher penalty to move - * a process to another CPU. Our cache is rather small so we report - * 1 tick. - */ -unsigned long cache_decay_ticks = 1; - -int __devinit __cpu_up(unsigned int cpu) -{ - smp_boot_one_cpu(cpu); - return cpu_online(cpu) ? 0 : -ENOSYS; -} - -void smp_send_reschedule(int cpu) -{ - cpumask_t cpu_mask = CPU_MASK_NONE; - cpu_set(cpu, cpu_mask); - send_ipi(IPI_SCHEDULE, 0, cpu_mask); -} - -/* TLB flushing - * - * Flush needs to be done on the local CPU and on any other CPU that - * may have the same mapping. The mm->cpu_vm_mask is used to keep track - * of which CPUs that a specific process has been executed on. - */ -void flush_tlb_common(struct mm_struct* mm, struct vm_area_struct* vma, unsigned long addr) -{ - unsigned long flags; - cpumask_t cpu_mask; - - spin_lock_irqsave(&tlbstate_lock, flags); - cpu_mask = (mm == FLUSH_ALL ? CPU_MASK_ALL : mm->cpu_vm_mask); - cpu_clear(smp_processor_id(), cpu_mask); - flush_mm = mm; - flush_vma = vma; - flush_addr = addr; - send_ipi(IPI_FLUSH_TLB, 1, cpu_mask); - spin_unlock_irqrestore(&tlbstate_lock, flags); -} - -void flush_tlb_all(void) -{ - __flush_tlb_all(); - flush_tlb_common(FLUSH_ALL, FLUSH_ALL, 0); -} - -void flush_tlb_mm(struct mm_struct *mm) -{ - __flush_tlb_mm(mm); - flush_tlb_common(mm, FLUSH_ALL, 0); - /* No more mappings in other CPUs */ - cpus_clear(mm->cpu_vm_mask); - cpu_set(smp_processor_id(), mm->cpu_vm_mask); -} - -void flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr) -{ - __flush_tlb_page(vma, addr); - flush_tlb_common(vma->vm_mm, vma, addr); -} - -/* Inter processor interrupts - * - * The IPIs are used for: - * * Force a schedule on a CPU - * * FLush TLB on other CPUs - * * Call a function on other CPUs - */ - -int send_ipi(int vector, int wait, cpumask_t cpu_mask) -{ - int i = 0; - reg_intr_vect_rw_ipi ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi); - int ret = 0; - - /* Calculate CPUs to send to. */ - cpus_and(cpu_mask, cpu_mask, cpu_online_map); - - /* Send the IPI. */ - for_each_cpu_mask(i, cpu_mask) - { - ipi.vector |= vector; - REG_WR(intr_vect, irq_regs[i], rw_ipi, ipi); - } - - /* Wait for IPI to finish on other CPUS */ - if (wait) { - for_each_cpu_mask(i, cpu_mask) { - int j; - for (j = 0 ; j < 1000; j++) { - ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi); - if (!ipi.vector) - break; - udelay(100); - } - - /* Timeout? */ - if (ipi.vector) { - printk("SMP call timeout from %d to %d\n", smp_processor_id(), i); - ret = -ETIMEDOUT; - dump_stack(); - } - } - } - return ret; -} - -/* - * You must not call this function with disabled interrupts or from a - * hardware interrupt handler or from a bottom half handler. - */ -int smp_call_function(void (*func)(void *info), void *info, - int nonatomic, int wait) -{ - cpumask_t cpu_mask = CPU_MASK_ALL; - struct call_data_struct data; - int ret; - - cpu_clear(smp_processor_id(), cpu_mask); - - WARN_ON(irqs_disabled()); - - data.func = func; - data.info = info; - data.wait = wait; - - spin_lock(&call_lock); - call_data = &data; - ret = send_ipi(IPI_CALL, wait, cpu_mask); - spin_unlock(&call_lock); - - return ret; -} - -irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - void (*func) (void *info) = call_data->func; - void *info = call_data->info; - reg_intr_vect_rw_ipi ipi; - - ipi = REG_RD(intr_vect, irq_regs[smp_processor_id()], rw_ipi); - - if (ipi.vector & IPI_CALL) { - func(info); - } - if (ipi.vector & IPI_FLUSH_TLB) { - if (flush_mm == FLUSH_ALL) - __flush_tlb_all(); - else if (flush_vma == FLUSH_ALL) - __flush_tlb_mm(flush_mm); - else - __flush_tlb_page(flush_vma, flush_addr); - } - - ipi.vector = 0; - REG_WR(intr_vect, irq_regs[smp_processor_id()], rw_ipi, ipi); - - return IRQ_HANDLED; -} - diff --git a/trunk/arch/cris/arch-v32/kernel/time.c b/trunk/arch/cris/arch-v32/kernel/time.c deleted file mode 100644 index d48e397f5fa4..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/time.c +++ /dev/null @@ -1,341 +0,0 @@ -/* $Id: time.c,v 1.19 2005/04/29 05:40:09 starvik Exp $ - * - * linux/arch/cris/arch-v32/kernel/time.c - * - * Copyright (C) 2003 Axis Communications AB - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* Watchdog defines */ -#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */ -#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */ -#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1) /* Number of 763 counts before watchdog bites */ - -unsigned long timer_regs[NR_CPUS] = -{ - regi_timer, -#ifdef CONFIG_SMP - regi_timer2 -#endif -}; - -extern void update_xtime_from_cmos(void); -extern int set_rtc_mmss(unsigned long nowtime); -extern int setup_irq(int, struct irqaction *); -extern int have_rtc; - -unsigned long get_ns_in_jiffie(void) -{ - reg_timer_r_tmr0_data data; - unsigned long ns; - - data = REG_RD(timer, regi_timer, r_tmr0_data); - ns = (TIMER0_DIV - data) * 10; - return ns; -} - -unsigned long do_slow_gettimeoffset(void) -{ - unsigned long count; - unsigned long usec_count = 0; - - static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */ - static unsigned long jiffies_p = 0; - - /* - * cache volatile jiffies temporarily; we have IRQs turned off. - */ - unsigned long jiffies_t; - - /* The timer interrupt comes from Etrax timer 0. In order to get - * better precision, we check the current value. It might have - * underflowed already though. - */ - - count = REG_RD(timer, regi_timer, r_tmr0_data); - jiffies_t = jiffies; - - /* - * avoiding timer inconsistencies (they are rare, but they happen)... - * there are one problem that must be avoided here: - * 1. the timer counter underflows - */ - if( jiffies_t == jiffies_p ) { - if( count > count_p ) { - /* Timer wrapped, use new count and prescale - * increase the time corresponding to one jiffie - */ - usec_count = 1000000/HZ; - } - } else - jiffies_p = jiffies_t; - count_p = count; - /* Convert timer value to usec */ - /* 100 MHz timer, divide by 100 to get usec */ - usec_count += (TIMER0_DIV - count) / 100; - return usec_count; -} - -/* From timer MDS describing the hardware watchdog: - * 4.3.1 Watchdog Operation - * The watchdog timer is an 8-bit timer with a configurable start value. - * Once started the whatchdog counts downwards with a frequency of 763 Hz - * (100/131072 MHz). When the watchdog counts down to 1, it generates an - * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the - * chip. - */ -/* This gives us 1.3 ms to do something useful when the NMI comes */ - -/* right now, starting the watchdog is the same as resetting it */ -#define start_watchdog reset_watchdog - -#if defined(CONFIG_ETRAX_WATCHDOG) -static short int watchdog_key = 42; /* arbitrary 7 bit number */ -#endif - -/* number of pages to consider "out of memory". it is normal that the memory - * is used though, so put this really low. - */ - -#define WATCHDOG_MIN_FREE_PAGES 8 - -void -reset_watchdog(void) -{ -#if defined(CONFIG_ETRAX_WATCHDOG) - reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; - - /* only keep watchdog happy as long as we have memory left! */ - if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { - /* reset the watchdog with the inverse of the old key */ - watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */ - wd_ctrl.cnt = ETRAX_WD_CNT; - wd_ctrl.cmd = regk_timer_start; - wd_ctrl.key = watchdog_key; - REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl); - } -#endif -} - -/* stop the watchdog - we still need the correct key */ - -void -stop_watchdog(void) -{ -#if defined(CONFIG_ETRAX_WATCHDOG) - reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; - watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */ - wd_ctrl.cnt = ETRAX_WD_CNT; - wd_ctrl.cmd = regk_timer_stop; - wd_ctrl.key = watchdog_key; - REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl); -#endif -} - -extern void show_registers(struct pt_regs *regs); - -void -handle_watchdog_bite(struct pt_regs* regs) -{ -#if defined(CONFIG_ETRAX_WATCHDOG) - extern int cause_of_death; - - raw_printk("Watchdog bite\n"); - - /* Check if forced restart or unexpected watchdog */ - if (cause_of_death == 0xbedead) { - while(1); - } - - /* Unexpected watchdog, stop the watchdog and dump registers*/ - stop_watchdog(); - raw_printk("Oops: bitten by watchdog\n"); - show_registers(regs); -#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY - reset_watchdog(); -#endif - while(1) /* nothing */; -#endif -} - -/* last time the cmos clock got updated */ -static long last_rtc_update = 0; - -/* - * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick - */ - -//static unsigned short myjiff; /* used by our debug routine print_timestamp */ - -extern void cris_do_profile(struct pt_regs *regs); - -static inline irqreturn_t -timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - int cpu = smp_processor_id(); - reg_timer_r_masked_intr masked_intr; - reg_timer_rw_ack_intr ack_intr = { 0 }; - - /* Check if the timer interrupt is for us (a tmr0 int) */ - masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr); - if (!masked_intr.tmr0) - return IRQ_NONE; - - /* acknowledge the timer irq */ - ack_intr.tmr0 = 1; - REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr); - - /* reset watchdog otherwise it resets us! */ - reset_watchdog(); - - /* Update statistics. */ - update_process_times(user_mode(regs)); - - cris_do_profile(regs); /* Save profiling information */ - - /* The master CPU is responsible for the time keeping. */ - if (cpu != 0) - return IRQ_HANDLED; - - /* call the real timer interrupt handler */ - do_timer(regs); - - /* - * If we have an externally synchronized Linux clock, then update - * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be - * called as close as possible to 500 ms before the new second starts. - * - * The division here is not time critical since it will run once in - * 11 minutes - */ - if ((time_status & STA_UNSYNC) == 0 && - xtime.tv_sec > last_rtc_update + 660 && - (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 && - (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) { - if (set_rtc_mmss(xtime.tv_sec) == 0) - last_rtc_update = xtime.tv_sec; - else - last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */ - } - return IRQ_HANDLED; -} - -/* timer is SA_SHIRQ so drivers can add stuff to the timer irq chain - * it needs to be SA_INTERRUPT to make the jiffies update work properly - */ - -static struct irqaction irq_timer = { timer_interrupt, SA_SHIRQ | SA_INTERRUPT, - CPU_MASK_NONE, "timer", NULL, NULL}; - -void __init -cris_timer_init(void) -{ - int cpu = smp_processor_id(); - reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 }; - reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV; - reg_timer_rw_intr_mask timer_intr_mask; - - /* Setup the etrax timers - * Base frequency is 100MHz, divider 1000000 -> 100 HZ - * We use timer0, so timer1 is free. - * The trig timer is used by the fasttimer API if enabled. - */ - - tmr0_ctrl.op = regk_timer_ld; - tmr0_ctrl.freq = regk_timer_f100; - REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div); - REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */ - tmr0_ctrl.op = regk_timer_run; - REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */ - - /* enable the timer irq */ - timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask); - timer_intr_mask.tmr0 = 1; - REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask); -} - -void __init -time_init(void) -{ - reg_intr_vect_rw_mask intr_mask; - - /* probe for the RTC and read it if it exists - * Before the RTC can be probed the loops_per_usec variable needs - * to be initialized to make usleep work. A better value for - * loops_per_usec is calculated by the kernel later once the - * clock has started. - */ - loops_per_usec = 50; - - if(RTC_INIT() < 0) { - /* no RTC, start at 1980 */ - xtime.tv_sec = 0; - xtime.tv_nsec = 0; - have_rtc = 0; - } else { - /* get the current time */ - have_rtc = 1; - update_xtime_from_cmos(); - } - - /* - * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the - * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC). - */ - set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); - - /* Start CPU local timer */ - cris_timer_init(); - - /* enable the timer irq in global config */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.timer = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - /* now actually register the timer irq handler that calls timer_interrupt() */ - - setup_irq(TIMER_INTR_VECT, &irq_timer); - - /* enable watchdog if we should use one */ - -#if defined(CONFIG_ETRAX_WATCHDOG) - printk("Enabling watchdog...\n"); - start_watchdog(); - - /* If we use the hardware watchdog, we want to trap it as an NMI - and dump registers before it resets us. For this to happen, we - must set the "m" NMI enable flag (which once set, is unset only - when an NMI is taken). - - The same goes for the external NMI, but that doesn't have any - driver or infrastructure support yet. */ - { - unsigned long flags; - local_save_flags(flags); - flags |= (1<<30); /* NMI M flag is at bit 30 */ - local_irq_restore(flags); - } -#endif -} diff --git a/trunk/arch/cris/arch-v32/kernel/traps.c b/trunk/arch/cris/arch-v32/kernel/traps.c deleted file mode 100644 index 6e3787045560..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/traps.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (C) 2003, Axis Communications AB. - */ - -#include -#include -#include - -#include - -extern void reset_watchdog(void); -extern void stop_watchdog(void); - -extern int raw_printk(const char *fmt, ...); - -void -show_registers(struct pt_regs *regs) -{ - /* - * It's possible to use either the USP register or current->thread.usp. - * USP might not correspond to the current proccess for all cases this - * function is called, and current->thread.usp isn't up to date for the - * current proccess. Experience shows that using USP is the way to go. - */ - unsigned long usp; - unsigned long d_mmu_cause; - unsigned long i_mmu_cause; - - usp = rdusp(); - - raw_printk("CPU: %d\n", smp_processor_id()); - - raw_printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n", - regs->erp, regs->srp, regs->ccs, usp, regs->mof); - - raw_printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", - regs->r0, regs->r1, regs->r2, regs->r3); - - raw_printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", - regs->r4, regs->r5, regs->r6, regs->r7); - - raw_printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", - regs->r8, regs->r9, regs->r10, regs->r11); - - raw_printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n", - regs->r12, regs->r13, regs->orig_r10, regs->acr); - - raw_printk("sp: %08lx\n", regs); - - SUPP_BANK_SEL(BANK_IM); - SUPP_REG_RD(RW_MM_CAUSE, i_mmu_cause); - - SUPP_BANK_SEL(BANK_DM); - SUPP_REG_RD(RW_MM_CAUSE, d_mmu_cause); - - raw_printk(" Data MMU Cause: %08lx\n", d_mmu_cause); - raw_printk("Instruction MMU Cause: %08lx\n", i_mmu_cause); - - raw_printk("Process %s (pid: %d, stackpage: %08lx)\n", - current->comm, current->pid, (unsigned long) current); - - /* Show additional info if in kernel-mode. */ - if (!user_mode(regs)) { - int i; - unsigned char c; - - show_stack(NULL, (unsigned long *) usp); - - /* - * If the previous stack-dump wasn't a kernel one, dump the - * kernel stack now. - */ - if (usp != 0) - show_stack(NULL, NULL); - - raw_printk("\nCode: "); - - if (regs->erp < PAGE_OFFSET) - goto bad_value; - - /* - * Quite often the value at regs->erp doesn't point to the - * interesting instruction, which often is the previous - * instruction. So dump at an offset large enough that the - * instruction decoding should be in sync at the interesting - * point, but small enough to fit on a row. The regs->erp - * location is pointed out in a ksymoops-friendly way by - * wrapping the byte for that address in parenthesis. - */ - for (i = -12; i < 12; i++) { - if (__get_user(c, &((unsigned char *) regs->erp)[i])) { -bad_value: - raw_printk(" Bad IP value."); - break; - } - - if (i == 0) - raw_printk("(%02x) ", c); - else - raw_printk("%02x ", c); - } - - raw_printk("\n"); - } -} - -/* - * This gets called from entry.S when the watchdog has bitten. Show something - * similiar to an Oops dump, and if the kernel if configured to be a nice doggy; - * halt instead of reboot. - */ -void -watchdog_bite_hook(struct pt_regs *regs) -{ -#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY - local_irq_disable(); - stop_watchdog(); - show_registers(regs); - - while (1) - ; /* Do nothing. */ -#else - show_registers(regs); -#endif -} - -/* This is normally the Oops function. */ -void -die_if_kernel(const char *str, struct pt_regs *regs, long err) -{ - if (user_mode(regs)) - return; - -#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY - /* - * This printout might take too long and could trigger - * the watchdog normally. If NICE_DOGGY is set, simply - * stop the watchdog during the printout. - */ - stop_watchdog(); -#endif - - raw_printk("%s: %04lx\n", str, err & 0xffff); - - show_registers(regs); - -#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY - reset_watchdog(); -#endif - - do_exit(SIGSEGV); -} - -void arch_enable_nmi(void) -{ - unsigned long flags; - local_save_flags(flags); - flags |= (1<<30); /* NMI M flag is at bit 30 */ - local_irq_restore(flags); -} diff --git a/trunk/arch/cris/arch-v32/kernel/vcs_hook.c b/trunk/arch/cris/arch-v32/kernel/vcs_hook.c deleted file mode 100644 index 64d71c54c22c..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/vcs_hook.c +++ /dev/null @@ -1,96 +0,0 @@ -// $Id: vcs_hook.c,v 1.2 2003/08/12 12:01:06 starvik Exp $ -// -// Call simulator hook. This is the part running in the -// simulated program. -// - -#include "vcs_hook.h" -#include -#include -#include - -#define HOOK_TRIG_ADDR 0xb7000000 /* hook cvlog model reg address */ -#define HOOK_MEM_BASE_ADDR 0xa0000000 /* csp4 (shared mem) base addr */ - -#define HOOK_DATA(offset) ((unsigned*) HOOK_MEM_BASE_ADDR)[offset] -#define VHOOK_DATA(offset) ((volatile unsigned*) HOOK_MEM_BASE_ADDR)[offset] -#define HOOK_TRIG(funcid) do { *((unsigned *) HOOK_TRIG_ADDR) = funcid; } while(0) -#define HOOK_DATA_BYTE(offset) ((unsigned char*) HOOK_MEM_BASE_ADDR)[offset] - - -// ------------------------------------------------------------------ hook_call -int hook_call( unsigned id, unsigned pcnt, ...) { - va_list ap; - unsigned i; - unsigned ret; -#ifdef USING_SOS - PREEMPT_OFF_SAVE(); -#endif - - // pass parameters - HOOK_DATA(0) = id; - - /* Have to make hook_print_str a special case since we call with a - parameter of byte type. Should perhaps be a separate - hook_call. */ - - if (id == hook_print_str) { - int i; - char *str; - - HOOK_DATA(1) = pcnt; - - va_start(ap, pcnt); - str = (char*)va_arg(ap,unsigned); - - for (i=0; i!=pcnt; i++) { - HOOK_DATA_BYTE(8+i) = str[i]; - } - HOOK_DATA_BYTE(8+i) = 0; /* null byte */ - } - else { - va_start(ap, pcnt); - for( i = 1; i <= pcnt; i++ ) HOOK_DATA(i) = va_arg(ap,unsigned); - va_end(ap); - } - - // read from mem to make sure data has propagated to memory before trigging - *((volatile unsigned*) HOOK_MEM_BASE_ADDR); - - // trigger hook - HOOK_TRIG(id); - - // wait for call to finish - while( VHOOK_DATA(0) > 0 ) {} - - // extract return value - - ret = VHOOK_DATA(1); - -#ifdef USING_SOS - PREEMPT_RESTORE(); -#endif - return ret; -} - -unsigned -hook_buf(unsigned i) -{ - return (HOOK_DATA(i)); -} - -void print_str( const char *str ) { - int i; - for (i=1; str[i]; i++); /* find null at end of string */ - hook_call(hook_print_str, i, str); -} - -// --------------------------------------------------------------- CPU_KICK_DOG -void CPU_KICK_DOG(void) { - (void) hook_call( hook_kick_dog, 0 ); -} - -// ------------------------------------------------------- CPU_WATCHDOG_TIMEOUT -void CPU_WATCHDOG_TIMEOUT( unsigned t ) { - (void) hook_call( hook_dog_timeout, 1, t ); -} diff --git a/trunk/arch/cris/arch-v32/kernel/vcs_hook.h b/trunk/arch/cris/arch-v32/kernel/vcs_hook.h deleted file mode 100644 index 7d73709e3cc6..000000000000 --- a/trunk/arch/cris/arch-v32/kernel/vcs_hook.h +++ /dev/null @@ -1,42 +0,0 @@ -// $Id: vcs_hook.h,v 1.1 2003/08/12 12:01:06 starvik Exp $ -// -// Call simulator hook functions - -#ifndef HOOK_H -#define HOOK_H - -int hook_call( unsigned id, unsigned pcnt, ...); - -enum hook_ids { - hook_debug_on = 1, - hook_debug_off, - hook_stop_sim_ok, - hook_stop_sim_fail, - hook_alloc_shared, - hook_ptr_shared, - hook_free_shared, - hook_file2shared, - hook_cmp_shared, - hook_print_params, - hook_sim_time, - hook_stop_sim, - hook_kick_dog, - hook_dog_timeout, - hook_rand, - hook_srand, - hook_rand_range, - hook_print_str, - hook_print_hex, - hook_cmp_offset_shared, - hook_fill_random_shared, - hook_alloc_random_data, - hook_calloc_random_data, - hook_print_int, - hook_print_uint, - hook_fputc, - hook_init_fd, - hook_sbrk - -}; - -#endif diff --git a/trunk/arch/cris/arch-v32/lib/Makefile b/trunk/arch/cris/arch-v32/lib/Makefile deleted file mode 100644 index 05b3ec6978d6..000000000000 --- a/trunk/arch/cris/arch-v32/lib/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for Etrax-specific library files.. -# - -lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o csumcpfruser.o spinlock.o - diff --git a/trunk/arch/cris/arch-v32/lib/checksum.S b/trunk/arch/cris/arch-v32/lib/checksum.S deleted file mode 100644 index 32e66181b826..000000000000 --- a/trunk/arch/cris/arch-v32/lib/checksum.S +++ /dev/null @@ -1,111 +0,0 @@ -/* - * A fast checksum routine using movem - * Copyright (c) 1998-2001, 2003 Axis Communications AB - * - * csum_partial(const unsigned char * buff, int len, unsigned int sum) - */ - - .globl csum_partial -csum_partial: - - ;; r10 - src - ;; r11 - length - ;; r12 - checksum - - ;; check for breakeven length between movem and normal word looping versions - ;; we also do _NOT_ want to compute a checksum over more than the - ;; actual length when length < 40 - - cmpu.w 80,$r11 - blo _word_loop - nop - - ;; need to save the registers we use below in the movem loop - ;; this overhead is why we have a check above for breakeven length - ;; only r0 - r8 have to be saved, the other ones are clobber-able - ;; according to the ABI - - subq 9*4,$sp - subq 10*4,$r11 ; update length for the first loop - movem $r8,[$sp] - - ;; do a movem checksum - -_mloop: movem [$r10+],$r9 ; read 10 longwords - - ;; perform dword checksumming on the 10 longwords - - add.d $r0,$r12 - addc $r1,$r12 - addc $r2,$r12 - addc $r3,$r12 - addc $r4,$r12 - addc $r5,$r12 - addc $r6,$r12 - addc $r7,$r12 - addc $r8,$r12 - addc $r9,$r12 - - ;; fold the carry into the checksum, to avoid having to loop the carry - ;; back into the top - - addc 0,$r12 - addc 0,$r12 ; do it again, since we might have generated a carry - - subq 10*4,$r11 - bge _mloop - nop - - addq 10*4,$r11 ; compensate for last loop underflowing length - - movem [$sp+],$r8 ; restore regs - -_word_loop: - ;; only fold if there is anything to fold. - - cmpq 0,$r12 - beq _no_fold - - ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below. - ;; r9 and r13 can be used as temporaries. - - moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9 - lsrq 16,$r9 - - move.d $r12,$r13 - lsrq 16,$r13 ; r13 = checksum >> 16 - and.d $r9,$r12 ; checksum = checksum & 0xffff - add.d $r13,$r12 ; checksum += r13 - move.d $r12,$r13 ; do the same again, maybe we got a carry last add - lsrq 16,$r13 - and.d $r9,$r12 - add.d $r13,$r12 - -_no_fold: - cmpq 2,$r11 - blt _no_words - nop - - ;; checksum the rest of the words - - subq 2,$r11 - -_wloop: subq 2,$r11 - bge _wloop - addu.w [$r10+],$r12 - - addq 2,$r11 - -_no_words: - ;; see if we have one odd byte more - cmpq 1,$r11 - beq _do_byte - nop - ret - move.d $r12,$r10 - -_do_byte: - ;; copy and checksum the last byte - addu.b [$r10],$r12 - ret - move.d $r12,$r10 diff --git a/trunk/arch/cris/arch-v32/lib/checksumcopy.S b/trunk/arch/cris/arch-v32/lib/checksumcopy.S deleted file mode 100644 index 9303ccbadc6d..000000000000 --- a/trunk/arch/cris/arch-v32/lib/checksumcopy.S +++ /dev/null @@ -1,120 +0,0 @@ -/* - * A fast checksum+copy routine using movem - * Copyright (c) 1998, 2001, 2003 Axis Communications AB - * - * Authors: Bjorn Wesen - * - * csum_partial_copy_nocheck(const char *src, char *dst, - * int len, unsigned int sum) - */ - - .globl csum_partial_copy_nocheck -csum_partial_copy_nocheck: - - ;; r10 - src - ;; r11 - dst - ;; r12 - length - ;; r13 - checksum - - ;; check for breakeven length between movem and normal word looping versions - ;; we also do _NOT_ want to compute a checksum over more than the - ;; actual length when length < 40 - - cmpu.w 80,$r12 - blo _word_loop - nop - - ;; need to save the registers we use below in the movem loop - ;; this overhead is why we have a check above for breakeven length - ;; only r0 - r8 have to be saved, the other ones are clobber-able - ;; according to the ABI - - subq 9*4,$sp - subq 10*4,$r12 ; update length for the first loop - movem $r8,[$sp] - - ;; do a movem copy and checksum - -1: ;; A failing userspace access (the read) will have this as PC. -_mloop: movem [$r10+],$r9 ; read 10 longwords - movem $r9,[$r11+] ; write 10 longwords - - ;; perform dword checksumming on the 10 longwords - - add.d $r0,$r13 - addc $r1,$r13 - addc $r2,$r13 - addc $r3,$r13 - addc $r4,$r13 - addc $r5,$r13 - addc $r6,$r13 - addc $r7,$r13 - addc $r8,$r13 - addc $r9,$r13 - - ;; fold the carry into the checksum, to avoid having to loop the carry - ;; back into the top - - addc 0,$r13 - addc 0,$r13 ; do it again, since we might have generated a carry - - subq 10*4,$r12 - bge _mloop - nop - - addq 10*4,$r12 ; compensate for last loop underflowing length - - movem [$sp+],$r8 ; restore regs - -_word_loop: - ;; only fold if there is anything to fold. - - cmpq 0,$r13 - beq _no_fold - - ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below - ;; r9 can be used as temporary. - - move.d $r13,$r9 - lsrq 16,$r9 ; r0 = checksum >> 16 - and.d 0xffff,$r13 ; checksum = checksum & 0xffff - add.d $r9,$r13 ; checksum += r0 - move.d $r13,$r9 ; do the same again, maybe we got a carry last add - lsrq 16,$r9 - and.d 0xffff,$r13 - add.d $r9,$r13 - -_no_fold: - cmpq 2,$r12 - blt _no_words - nop - - ;; copy and checksum the rest of the words - - subq 2,$r12 - -2: ;; A failing userspace access for the read below will have this as PC. -_wloop: move.w [$r10+],$r9 - addu.w $r9,$r13 - subq 2,$r12 - bge _wloop - move.w $r9,[$r11+] - - addq 2,$r12 - -_no_words: - ;; see if we have one odd byte more - cmpq 1,$r12 - beq _do_byte - nop - ret - move.d $r13,$r10 - -_do_byte: - ;; copy and checksum the last byte -3: ;; A failing userspace access for the read below will have this as PC. - move.b [$r10],$r9 - addu.b $r9,$r13 - move.b $r9,[$r11] - ret - move.d $r13,$r10 diff --git a/trunk/arch/cris/arch-v32/lib/csumcpfruser.S b/trunk/arch/cris/arch-v32/lib/csumcpfruser.S deleted file mode 100644 index 600ec16b9f28..000000000000 --- a/trunk/arch/cris/arch-v32/lib/csumcpfruser.S +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into - * csum_partial_copy_from_user by adding exception records. - * - * Copyright (C) 2001, 2003 Axis Communications AB. - * - * Author: Hans-Peter Nilsson. - */ - -#include - -/* Same function body, but a different name. If we just added exception - records to _csum_partial_copy_nocheck and made it generic, we wouldn't - know a user fault from a kernel fault and we would have overhead in - each kernel caller for the error-pointer argument. - - unsigned int csum_partial_copy_from_user - (const char *src, char *dst, int len, unsigned int sum, int *errptr); - - Note that the errptr argument is only set if we encounter an error. - It is conveniently located on the stack, so the normal function body - does not have to handle it. */ - -#define csum_partial_copy_nocheck csum_partial_copy_from_user - -/* There are local labels numbered 1, 2 and 3 present to mark the - different from-user accesses. */ -#include "checksumcopy.S" - - .section .fixup,"ax" - -;; Here from the movem loop; restore stack. -4: - movem [$sp+],$r8 -;; r12 is already decremented. Add back chunk_size-2. - addq 40-2,$r12 - -;; Here from the word loop; r12 is off by 2; add it back. -5: - addq 2,$r12 - -;; Here from a failing single byte. -6: - -;; Signal in *errptr that we had a failing access. - move.d [$sp],$acr - moveq -EFAULT,$r9 - subq 4,$sp - move.d $r9,[$acr] - -;; Clear the rest of the destination area using memset. Preserve the -;; checksum for the readable bytes. - move.d $r13,[$sp] - subq 4,$sp - move.d $r11,$r10 - move $srp,[$sp] - jsr memset - clear.d $r11 - - move [$sp+],$srp - ret - move.d [$sp+],$r10 - - .previous - .section __ex_table,"a" - .dword 1b,4b - .dword 2b,5b - .dword 3b,6b - .previous diff --git a/trunk/arch/cris/arch-v32/lib/dram_init.S b/trunk/arch/cris/arch-v32/lib/dram_init.S deleted file mode 100644 index 47b6cf5f4afd..000000000000 --- a/trunk/arch/cris/arch-v32/lib/dram_init.S +++ /dev/null @@ -1,120 +0,0 @@ -/* $Id: dram_init.S,v 1.4 2005/04/24 18:48:32 starvik Exp $ - * - * DRAM/SDRAM initialization - alter with care - * This file is intended to be included from other assembler files - * - * Note: This file may not modify r8 or r9 because they are used to - * carry information from the decompresser to the kernel - * - * Copyright (C) 2000-2003 Axis Communications AB - * - * Authors: Mikael Starvik (starvik@axis.com) - */ - -/* Just to be certain the config file is included, we include it here - * explicitely instead of depending on it being included in the file that - * uses this code. - */ - -#include -#include -#include - - ;; WARNING! The registers r8 and r9 are used as parameters carrying - ;; information from the decompressor (if the kernel was compressed). - ;; They should not be used in the code below. - - ; Refer to BIF MDS for a description of SDRAM initialization - - ; Bank configuration - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0 - move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0 - move.d CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1 - move.d $r1, [$r0] - - ; Calculate value of mrs_data - ; CAS latency = 2 && bus_width = 32 => 0x40 - ; CAS latency = 3 && bus_width = 32 => 0x60 - ; CAS latency = 2 && bus_width = 16 => 0x20 - ; CAS latency = 3 && bus_width = 16 => 0x30 - - ; Check if value is already supplied in kernel config - move.d CONFIG_ETRAX_SDRAM_COMMAND, $r2 - bne _set_timing - nop - - move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2 - move.d CONFIG_ETRAX_SDRAM_TIMING, $r1 - and.d 0x07, $r1 ; Get CAS latency - cmpq 2, $r1 ; CL = 2 ? - beq _bw_check - nop - move.d 0x60, $r4 - -_bw_check: - ; Assume that group 0 width is equal to group 1. This assumption - ; is wrong for a group 1 only hardware (such as the grand old - ; StorPoint+). - move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1 - and.d 0x200, $r1 ; DRAM width is bit 9 - beq _set_timing - lslq 2, $r4 ; mrs_data starts at bit 2 - lsrq 1, $r4 ; 16 bits. Shift down value. - - ; Set timing parameters (refresh off to avoid Guinness TR 83) -_set_timing: - move.d CONFIG_ETRAX_SDRAM_TIMING, $r1 - and.d ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1 - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0 - move.d $r1, [$r0] - - ; Issue NOP command - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5 - moveq regk_bif_core_nop, $r1 - move.d $r1, [$r5] - - ; Wait 200us - move.d 10000, $r2 -1: bne 1b - subq 1, $r2 - - ; Issue initialization command sequence - move.d _sdram_commands_start, $r2 - and.d 0x000fffff, $r2 ; Make sure commands are read from flash - move.d _sdram_commands_end, $r3 - and.d 0x000fffff, $r3 -1: clear.d $r6 - move.b [$r2+], $r6 ; Load command - or.d $r4, $r6 ; Add calculated mrs - move.d $r6, [$r5] ; Write rw_sdram_cmd - ; Wait 80 ns between each command - move.d 4000, $r7 -2: bne 2b - subq 1, $r7 - cmp.d $r2, $r3 ; Last command? - bne 1b - nop - - ; Start refresh - move.d CONFIG_ETRAX_SDRAM_TIMING, $r1 - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0 - move.d $r1, [$r0] - - ; Initialization finished - ba _sdram_commands_end - nop - -_sdram_commands_start: - .byte regk_bif_core_pre ; Precharge - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_mrs ; mrs -_sdram_commands_end: diff --git a/trunk/arch/cris/arch-v32/lib/hw_settings.S b/trunk/arch/cris/arch-v32/lib/hw_settings.S deleted file mode 100644 index 5182e8c2cff2..000000000000 --- a/trunk/arch/cris/arch-v32/lib/hw_settings.S +++ /dev/null @@ -1,73 +0,0 @@ -/* - * $Id: hw_settings.S,v 1.3 2005/04/24 18:36:57 starvik Exp $ - * - * This table is used by some tools to extract hardware parameters. - * The table should be included in the kernel and the decompressor. - * Don't forget to update the tools if you change this table. - * - * Copyright (C) 2001 Axis Communications AB - * - * Authors: Mikael Starvik (starvik@axis.com) - */ - -#include -#include -#include -#include - - .ascii "HW_PARAM_MAGIC" ; Magic number - .dword 0xc0004000 ; Kernel start address - - ; Debug port -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - .dword 0 -#elif defined(CONFIG_ETRAX_DEBUG_PORT1) - .dword 1 -#elif defined(CONFIG_ETRAX_DEBUG_PORT2) - .dword 2 -#elif defined(CONFIG_ETRAX_DEBUG_PORT3) - .dword 3 -#else - .dword 4 ; No debug -#endif - - ; Register values - .dword REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg) - .dword CONFIG_ETRAX_MEM_GRP1_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg) - .dword CONFIG_ETRAX_MEM_GRP2_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg) - .dword CONFIG_ETRAX_MEM_GRP3_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg) - .dword CONFIG_ETRAX_MEM_GRP4_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0) - .dword CONFIG_ETRAX_SDRAM_GRP0_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1) - .dword CONFIG_ETRAX_SDRAM_GRP1_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing) - .dword CONFIG_ETRAX_SDRAM_TIMING - .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd) - .dword CONFIG_ETRAX_SDRAM_COMMAND - - .dword REG_ADDR(gio, regi_gio, rw_pa_dout) - .dword CONFIG_ETRAX_DEF_GIO_PA_OUT - .dword REG_ADDR(gio, regi_gio, rw_pa_oe) - .dword CONFIG_ETRAX_DEF_GIO_PA_OE - .dword REG_ADDR(gio, regi_gio, rw_pb_dout) - .dword CONFIG_ETRAX_DEF_GIO_PB_OUT - .dword REG_ADDR(gio, regi_gio, rw_pb_oe) - .dword CONFIG_ETRAX_DEF_GIO_PB_OE - .dword REG_ADDR(gio, regi_gio, rw_pc_dout) - .dword CONFIG_ETRAX_DEF_GIO_PC_OUT - .dword REG_ADDR(gio, regi_gio, rw_pc_oe) - .dword CONFIG_ETRAX_DEF_GIO_PC_OE - .dword REG_ADDR(gio, regi_gio, rw_pd_dout) - .dword CONFIG_ETRAX_DEF_GIO_PD_OUT - .dword REG_ADDR(gio, regi_gio, rw_pd_oe) - .dword CONFIG_ETRAX_DEF_GIO_PD_OE - .dword REG_ADDR(gio, regi_gio, rw_pe_dout) - .dword CONFIG_ETRAX_DEF_GIO_PE_OUT - .dword REG_ADDR(gio, regi_gio, rw_pe_oe) - .dword CONFIG_ETRAX_DEF_GIO_PE_OE - - .dword 0 ; No more register values diff --git a/trunk/arch/cris/arch-v32/lib/memset.c b/trunk/arch/cris/arch-v32/lib/memset.c deleted file mode 100644 index ffca1214674e..000000000000 --- a/trunk/arch/cris/arch-v32/lib/memset.c +++ /dev/null @@ -1,253 +0,0 @@ -/*#************************************************************************#*/ -/*#-------------------------------------------------------------------------*/ -/*# */ -/*# FUNCTION NAME: memset() */ -/*# */ -/*# PARAMETERS: void* dst; Destination address. */ -/*# int c; Value of byte to write. */ -/*# int len; Number of bytes to write. */ -/*# */ -/*# RETURNS: dst. */ -/*# */ -/*# DESCRIPTION: Sets the memory dst of length len bytes to c, as standard. */ -/*# Framework taken from memcpy. This routine is */ -/*# very sensitive to compiler changes in register allocation. */ -/*# Should really be rewritten to avoid this problem. */ -/*# */ -/*#-------------------------------------------------------------------------*/ -/*# */ -/*# HISTORY */ -/*# */ -/*# DATE NAME CHANGES */ -/*# ---- ---- ------- */ -/*# 990713 HP Tired of watching this function (or */ -/*# really, the nonoptimized generic */ -/*# implementation) take up 90% of simulator */ -/*# output. Measurements needed. */ -/*# */ -/*#-------------------------------------------------------------------------*/ - -#include - -/* No, there's no macro saying 12*4, since it is "hard" to get it into - the asm in a good way. Thus better to expose the problem everywhere. - */ - -/* Assuming 1 cycle per dword written or read (ok, not really true), and - one per instruction, then 43+3*(n/48-1) <= 24+24*(n/48-1) - so n >= 45.7; n >= 0.9; we win on the first full 48-byte block to set. */ - -#define ZERO_BLOCK_SIZE (1*12*4) - -void *memset(void *pdst, - int c, - size_t plen) -{ - /* Ok. Now we want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. */ - - register char *return_dst __asm__ ("r10") = pdst; - register int n __asm__ ("r12") = plen; - register int lc __asm__ ("r11") = c; - - /* Most apps use memset sanely. Only those memsetting about 3..4 - bytes or less get penalized compared to the generic implementation - - and that's not really sane use. */ - - /* Ugh. This is fragile at best. Check with newer GCC releases, if - they compile cascaded "x |= x << 8" sanely! */ - __asm__("movu.b %0,$r13 \n\ - lslq 8,$r13 \n\ - move.b %0,$r13 \n\ - move.d $r13,%0 \n\ - lslq 16,$r13 \n\ - or.d $r13,%0" - : "=r" (lc) : "0" (lc) : "r13"); - - { - register char *dst __asm__ ("r13") = pdst; - - /* This is NONPORTABLE, but since this whole routine is */ - /* grossly nonportable that doesn't matter. */ - - if (((unsigned long) pdst & 3) != 0 - /* Oops! n=0 must be a legal call, regardless of alignment. */ - && n >= 3) - { - if ((unsigned long)dst & 1) - { - *dst = (char) lc; - n--; - dst++; - } - - if ((unsigned long)dst & 2) - { - *(short *)dst = lc; - n -= 2; - dst += 2; - } - } - - /* Now the fun part. For the threshold value of this, check the equation - above. */ - /* Decide which copying method to use. */ - if (n >= ZERO_BLOCK_SIZE) - { - /* For large copies we use 'movem' */ - - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. - - This method is not foolproof; it assumes that the "asm reg" - declarations at the beginning of the function really are used - here (beware: they may be moved to temporary registers). - This way, we do not have to save/move the registers around into - temporaries; we can safely use them straight away. - - If you want to check that the allocation was right; then - check the equalities in the first comment. It should say - "r13=r13, r12=r12, r11=r11" */ - __asm__ volatile (" \n\ - ;; Check that the register asm declaration got right. \n\ - ;; The GCC manual says it will work, but there *has* been bugs. \n\ - .ifnc %0-%1-%4,$r13-$r12-$r11 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll clobber in the movem process \n\ - ;; on the stack. Don't mention them to gcc, it will only be \n\ - ;; upset. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - move.d $r11,$r0 \n\ - move.d $r11,$r1 \n\ - move.d $r11,$r2 \n\ - move.d $r11,$r3 \n\ - move.d $r11,$r4 \n\ - move.d $r11,$r5 \n\ - move.d $r11,$r6 \n\ - move.d $r11,$r7 \n\ - move.d $r11,$r8 \n\ - move.d $r11,$r9 \n\ - move.d $r11,$r10 \n\ - \n\ - ;; Now we've got this: \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 12*4,$r12 \n\ -0: \n\ - subq 12*4,$r12 \n\ - bge 0b \n\ - movem $r11,[$r13+] \n\ - \n\ - addq 12*4,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10" - - /* Outputs */ : "=r" (dst), "=r" (n) - /* Inputs */ : "0" (dst), "1" (n), "r" (lc)); - } - - /* Either we directly starts copying, using dword copying - in a loop, or we copy as much as possible with 'movem' - and then the last block (<44 bytes) is copied here. - This will work since 'movem' will have updated src,dst,n. */ - - while ( n >= 16 ) - { - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - n -= 16; - } - - /* A switch() is definitely the fastest although it takes a LOT of code. - * Particularly if you inline code this. - */ - switch (n) - { - case 0: - break; - case 1: - *(char*)dst = (char) lc; - break; - case 2: - *(short*)dst = (short) lc; - break; - case 3: - *((short*)dst)++ = (short) lc; - *(char*)dst = (char) lc; - break; - case 4: - *((long*)dst)++ = lc; - break; - case 5: - *((long*)dst)++ = lc; - *(char*)dst = (char) lc; - break; - case 6: - *((long*)dst)++ = lc; - *(short*)dst = (short) lc; - break; - case 7: - *((long*)dst)++ = lc; - *((short*)dst)++ = (short) lc; - *(char*)dst = (char) lc; - break; - case 8: - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - break; - case 9: - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *(char*)dst = (char) lc; - break; - case 10: - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *(short*)dst = (short) lc; - break; - case 11: - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *((short*)dst)++ = (short) lc; - *(char*)dst = (char) lc; - break; - case 12: - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - break; - case 13: - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *(char*)dst = (char) lc; - break; - case 14: - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *(short*)dst = (short) lc; - break; - case 15: - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *((long*)dst)++ = lc; - *((short*)dst)++ = (short) lc; - *(char*)dst = (char) lc; - break; - } - } - - return return_dst; /* destination pointer. */ -} /* memset() */ diff --git a/trunk/arch/cris/arch-v32/lib/nand_init.S b/trunk/arch/cris/arch-v32/lib/nand_init.S deleted file mode 100644 index aba5c751c282..000000000000 --- a/trunk/arch/cris/arch-v32/lib/nand_init.S +++ /dev/null @@ -1,179 +0,0 @@ -##============================================================================= -## -## nand_init.S -## -## The bootrom copies data from the NAND flash to the internal RAM but -## due to a bug/feature we can only trust the 256 first bytes. So this -## code copies more data from NAND flash to internal RAM. Obvioulsy this -## code must fit in the first 256 bytes so alter with care. -## -## Some notes about the bug/feature for future reference: -## The bootrom copies the first 127 KB from NAND flash to internal -## memory. The problem is that it does a bytewise copy. NAND flashes -## does autoincrement on the address so for a 16-bite device each -## read/write increases the address by two. So the copy loop in the -## bootrom will discard every second byte. This is solved by inserting -## zeroes in every second byte in the first erase block. -## -## The bootrom also incorrectly assumes that it can read the flash -## linear with only one read command but the flash will actually -## switch between normal area and spare area if you do that so we -## can't trust more than the first 256 bytes. -## -##============================================================================= - -#include -#include -#include -#include -#include -#include - -;; There are 8-bit NAND flashes and 16-bit NAND flashes. -;; We need to treat them slightly different. -#if CONFIG_ETRAX_FLASH_BUSWIDTH==2 -#define PAGE_SIZE 256 -#else -#error 2 -#define PAGE_SIZE 512 -#endif -#define ERASE_BLOCK 16384 - -;; GPIO pins connected to NAND flash -#define CE 4 -#define CLE 5 -#define ALE 6 -#define BY 7 - -;; Address space for NAND flash -#define NAND_RD_ADDR 0x90000000 -#define NAND_WR_ADDR 0x94000000 - -#define READ_CMD 0x00 - -;; Readability macros -#define CSP_MASK \ - REG_MASK(bif_core, rw_grp3_cfg, gated_csp0) | \ - REG_MASK(bif_core, rw_grp3_cfg, gated_csp1) -#define CSP_VAL \ - REG_STATE(bif_core, rw_grp3_cfg, gated_csp0, rd) | \ - REG_STATE(bif_core, rw_grp3_cfg, gated_csp1, wr) - -;;---------------------------------------------------------------------------- -;; Macros to set/clear GPIO bits - -.macro SET x - or.b (1<<\x),$r9 - move.d $r9, [$r2] -.endm - -.macro CLR x - and.b ~(1<<\x),$r9 - move.d $r9, [$r2] -.endm - -;;---------------------------------------------------------------------------- - -nand_boot: - ;; Check if nand boot was selected - move.d REG_ADDR(config, regi_config, r_bootsel), $r0 - move.d [$r0], $r0 - and.d REG_MASK(config, r_bootsel, boot_mode), $r0 - cmp.d REG_STATE(config, r_bootsel, boot_mode, nand), $r0 - bne normal_boot ; No NAND boot - nop - -copy_nand_to_ram: - ;; copy_nand_to_ram - ;; Arguments - ;; r10 - destination - ;; r11 - source offset - ;; r12 - size - ;; r13 - Address to jump to after completion - ;; Note : r10-r12 are clobbered on return - ;; Registers used: - ;; r0 - NAND_RD_ADDR - ;; r1 - NAND_WR_ADDR - ;; r2 - reg_gio_rw_pa_dout - ;; r3 - reg_gio_r_pa_din - ;; r4 - tmp - ;; r5 - byte counter within a page - ;; r6 - reg_pinmux_rw_pa - ;; r7 - reg_gio_rw_pa_oe - ;; r8 - reg_bif_core_rw_grp3_cfg - ;; r9 - reg_gio_rw_pa_dout shadow - move.d 0x90000000, $r0 - move.d 0x94000000, $r1 - move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r2 - move.d REG_ADDR(gio, regi_gio, r_pa_din), $r3 - move.d REG_ADDR(pinmux, regi_pinmux, rw_pa), $r6 - move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r7 - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r8 - -#if CONFIG_ETRAX_FLASH_BUSWIDTH==2 - lsrq 1, $r11 -#endif - ;; Set up GPIO - move.d [$r2], $r9 - move.d [$r7], $r4 - or.b (1< - -void *memcpy(void *pdst, - const void *psrc, - size_t pn) -{ - /* Ok. Now we want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - If gcc was allright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register void *return_dst __asm__ ("r10") = pdst; - register char *dst __asm__ ("r13") = pdst; - register const char *src __asm__ ("r11") = psrc; - register int n __asm__ ("r12") = pn; - - - /* When src is aligned but not dst, this makes a few extra needless - cycles. I believe it would take as many to check that the - re-alignment was unnecessary. */ - if (((unsigned long) dst & 3) != 0 - /* Don't align if we wouldn't copy more than a few bytes; so we - don't have to check further for overflows. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - n--; - *(char*)dst = *(char*)src; - src++; - dst++; - } - - if ((unsigned long) dst & 2) - { - n -= 2; - *(short*)dst = *(short*)src; - src += 2; - dst += 2; - } - } - - /* Decide which copying method to use. Movem is dirt cheap, so the - overheap is low enough to always use the minimum block size as the - threshold. */ - if (n >= 44) - { - /* For large copies we use 'movem' */ - - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. */ - __asm__ volatile (" \n\ - ;; Check that the register asm declaration got right. \n\ - ;; The GCC manual explicitly says TRT will happen. \n\ - .ifnc %0-%1-%2,$r13-$r11-$r12 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll use in the movem process \n\ - \n\ - ;; on the stack. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - ;; Now we've got this: \n\ - ;; r11 - src \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 44,$r12 \n\ -0: \n\ - movem [$r11+],$r10 \n\ - subq 44,$r12 \n\ - bge 0b \n\ - movem $r10,[$r13+] \n\ - \n\ - addq 44,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10" - - /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n) - /* Inputs */ : "0" (dst), "1" (src), "2" (n)); - - } - - /* Either we directly starts copying, using dword copying - in a loop, or we copy as much as possible with 'movem' - and then the last block (<44 bytes) is copied here. - This will work since 'movem' will have updated src,dst,n. */ - - while ( n >= 16 ) - { - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - n -= 16; - } - - /* A switch() is definitely the fastest although it takes a LOT of code. - * Particularly if you inline code this. - */ - switch (n) - { - case 0: - break; - case 1: - *(char*)dst = *(char*)src; - break; - case 2: - *(short*)dst = *(short*)src; - break; - case 3: - *((short*)dst)++ = *((short*)src)++; - *(char*)dst = *(char*)src; - break; - case 4: - *((long*)dst)++ = *((long*)src)++; - break; - case 5: - *((long*)dst)++ = *((long*)src)++; - *(char*)dst = *(char*)src; - break; - case 6: - *((long*)dst)++ = *((long*)src)++; - *(short*)dst = *(short*)src; - break; - case 7: - *((long*)dst)++ = *((long*)src)++; - *((short*)dst)++ = *((short*)src)++; - *(char*)dst = *(char*)src; - break; - case 8: - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - break; - case 9: - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *(char*)dst = *(char*)src; - break; - case 10: - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *(short*)dst = *(short*)src; - break; - case 11: - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *((short*)dst)++ = *((short*)src)++; - *(char*)dst = *(char*)src; - break; - case 12: - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - break; - case 13: - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *(char*)dst = *(char*)src; - break; - case 14: - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *(short*)dst = *(short*)src; - break; - case 15: - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *((long*)dst)++ = *((long*)src)++; - *((short*)dst)++ = *((short*)src)++; - *(char*)dst = *(char*)src; - break; - } - - return return_dst; /* destination pointer. */ -} /* memcpy() */ diff --git a/trunk/arch/cris/arch-v32/lib/usercopy.c b/trunk/arch/cris/arch-v32/lib/usercopy.c deleted file mode 100644 index f0b08460c1be..000000000000 --- a/trunk/arch/cris/arch-v32/lib/usercopy.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * User address space access functions. - * The non-inlined parts of asm-cris/uaccess.h are here. - * - * Copyright (C) 2000, 2003 Axis Communications AB. - * - * Written by Hans-Peter Nilsson. - * Pieces used from memcpy, originally by Kenny Ranerup long time ago. - */ - -#include - -/* Asm:s have been tweaked (within the domain of correctness) to give - satisfactory results for "gcc version 3.2.1 Axis release R53/1.53-v32". - - Check regularly... - - Note that for CRISv32, the PC saved at a bus-fault is the address - *at* the faulting instruction, with a special case for instructions - in delay slots: then it's the address of the branch. Note also that - in contrast to v10, a postincrement in the instruction is *not* - performed at a bus-fault; the register is seen having the original - value in fault handlers. */ - - -/* Copy to userspace. This is based on the memcpy used for - kernel-to-kernel copying; see "string.c". */ - -unsigned long -__copy_user (void __user *pdst, const void *psrc, unsigned long pn) -{ - /* We want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - FIXME: Comment for old gcc version. Check. - If gcc was allright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register char *dst __asm__ ("r13") = pdst; - register const char *src __asm__ ("r11") = psrc; - register int n __asm__ ("r12") = pn; - register int retn __asm__ ("r10") = 0; - - - /* When src is aligned but not dst, this makes a few extra needless - cycles. I believe it would take as many to check that the - re-alignment was unnecessary. */ - if (((unsigned long) dst & 3) != 0 - /* Don't align if we wouldn't copy more than a few bytes; so we - don't have to check further for overflows. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - __asm_copy_to_user_1 (dst, src, retn); - n--; - } - - if ((unsigned long) dst & 2) - { - __asm_copy_to_user_2 (dst, src, retn); - n -= 2; - } - } - - /* Movem is dirt cheap. The overheap is low enough to always use the - minimum possible block size as the threshold. */ - if (n >= 44) - { - /* For large copies we use 'movem'. */ - - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. */ - __asm__ volatile ("\ - ;; Check that the register asm declaration got right. \n\ - ;; The GCC manual explicitly says TRT will happen. \n\ - .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll use in the movem process \n\ - ;; on the stack. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - ;; Now we've got this: \n\ - ;; r11 - src \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 44,$r12 \n\ -0: \n\ - movem [$r11+],$r10 \n\ - subq 44,$r12 \n\ -1: bge 0b \n\ - movem $r10,[$r13+] \n\ -3: \n\ - addq 44,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10 \n\ -2: \n\ - .section .fixup,\"ax\" \n\ -4: \n\ -; When failing on any of the 1..44 bytes in a chunk, we adjust back the \n\ -; source pointer and just drop through to the by-16 and by-4 loops to \n\ -; get the correct number of failing bytes. This necessarily means a \n\ -; few extra exceptions, but invalid user pointers shouldn't happen in \n\ -; time-critical code anyway. \n\ - jump 3b \n\ - subq 44,$r11 \n\ - \n\ - .previous \n\ - .section __ex_table,\"a\" \n\ - .dword 1b,4b \n\ - .previous" - - /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) - /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); - - } - - while (n >= 16) - { - __asm_copy_to_user_16 (dst, src, retn); - n -= 16; - } - - /* Having a separate by-four loops cuts down on cache footprint. - FIXME: Test with and without; increasing switch to be 0..15. */ - while (n >= 4) - { - __asm_copy_to_user_4 (dst, src, retn); - n -= 4; - } - - switch (n) - { - case 0: - break; - case 1: - __asm_copy_to_user_1 (dst, src, retn); - break; - case 2: - __asm_copy_to_user_2 (dst, src, retn); - break; - case 3: - __asm_copy_to_user_3 (dst, src, retn); - break; - } - - return retn; -} - -/* Copy from user to kernel, zeroing the bytes that were inaccessible in - userland. The return-value is the number of bytes that were - inaccessible. */ - -unsigned long -__copy_user_zeroing (void __user *pdst, const void *psrc, unsigned long pn) -{ - /* We want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - FIXME: Comment for old gcc version. Check. - If gcc was allright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register char *dst __asm__ ("r13") = pdst; - register const char *src __asm__ ("r11") = psrc; - register int n __asm__ ("r12") = pn; - register int retn __asm__ ("r10") = 0; - - /* The best reason to align src is that we then know that a read-fault - was for aligned bytes; there's no 1..3 remaining good bytes to - pickle. */ - if (((unsigned long) src & 3) != 0) - { - if (((unsigned long) src & 1) && n != 0) - { - __asm_copy_from_user_1 (dst, src, retn); - n--; - } - - if (((unsigned long) src & 2) && n >= 2) - { - __asm_copy_from_user_2 (dst, src, retn); - n -= 2; - } - - /* We only need one check after the unalignment-adjustments, because - if both adjustments were done, either both or neither reference - had an exception. */ - if (retn != 0) - goto copy_exception_bytes; - } - - /* Movem is dirt cheap. The overheap is low enough to always use the - minimum possible block size as the threshold. */ - if (n >= 44) - { - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. */ - __asm__ volatile ("\ - .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll use in the movem process \n\ - ;; on the stack. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - ;; Now we've got this: \n\ - ;; r11 - src \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 44,$r12 \n\ -0: \n\ - movem [$r11+],$r10 \n\ - \n\ - subq 44,$r12 \n\ - bge 0b \n\ - movem $r10,[$r13+] \n\ - \n\ -4: \n\ - addq 44,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10 \n\ - .section .fixup,\"ax\" \n\ - \n\ -;; Do not jump back into the loop if we fail. For some uses, we get a \n\ -;; page fault somewhere on the line. Without checking for page limits, \n\ -;; we don't know where, but we need to copy accurately and keep an \n\ -;; accurate count; not just clear the whole line. To do that, we fall \n\ -;; down in the code below, proceeding with smaller amounts. It should \n\ -;; be kept in mind that we have to cater to code like what at one time \n\ -;; was in fs/super.c: \n\ -;; i = size - copy_from_user((void *)page, data, size); \n\ -;; which would cause repeated faults while clearing the remainder of \n\ -;; the SIZE bytes at PAGE after the first fault. \n\ -;; A caveat here is that we must not fall through from a failing page \n\ -;; to a valid page. \n\ - \n\ -3: \n\ - jump 4b ;; Fall through, pretending the fault didn't happen. \n\ - nop \n\ - \n\ - .previous \n\ - .section __ex_table,\"a\" \n\ - .dword 0b,3b \n\ - .previous" - - /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) - /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); - } - - /* Either we directly start copying here, using dword copying in a loop, - or we copy as much as possible with 'movem' and then the last block - (<44 bytes) is copied here. This will work since 'movem' will have - updated src, dst and n. (Except with failing src.) - - Since we want to keep src accurate, we can't use - __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and - retn, but not src (by design; it's value is ignored elsewhere). */ - - while (n >= 4) - { - __asm_copy_from_user_4 (dst, src, retn); - n -= 4; - - if (retn) - goto copy_exception_bytes; - } - - /* If we get here, there were no memory read faults. */ - switch (n) - { - /* These copies are at least "naturally aligned" (so we don't have - to check each byte), due to the src alignment code before the - movem loop. The *_3 case *will* get the correct count for retn. */ - case 0: - /* This case deliberately left in (if you have doubts check the - generated assembly code). */ - break; - case 1: - __asm_copy_from_user_1 (dst, src, retn); - break; - case 2: - __asm_copy_from_user_2 (dst, src, retn); - break; - case 3: - __asm_copy_from_user_3 (dst, src, retn); - break; - } - - /* If we get here, retn correctly reflects the number of failing - bytes. */ - return retn; - -copy_exception_bytes: - /* We already have "retn" bytes cleared, and need to clear the - remaining "n" bytes. A non-optimized simple byte-for-byte in-line - memset is preferred here, since this isn't speed-critical code and - we'd rather have this a leaf-function than calling memset. */ - { - char *endp; - for (endp = dst + n; dst < endp; dst++) - *dst = 0; - } - - return retn + n; -} - -/* Zero userspace. */ - -unsigned long -__do_clear_user (void __user *pto, unsigned long pn) -{ - /* We want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - FIXME: Comment for old gcc version. Check. - If gcc was allright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register char *dst __asm__ ("r13") = pto; - register int n __asm__ ("r12") = pn; - register int retn __asm__ ("r10") = 0; - - - if (((unsigned long) dst & 3) != 0 - /* Don't align if we wouldn't copy more than a few bytes. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - __asm_clear_1 (dst, retn); - n--; - } - - if ((unsigned long) dst & 2) - { - __asm_clear_2 (dst, retn); - n -= 2; - } - } - - /* Decide which copying method to use. - FIXME: This number is from the "ordinary" kernel memset. */ - if (n >= 48) - { - /* For large clears we use 'movem' */ - - /* It is not optimal to tell the compiler about clobbering any - call-saved registers; that will move the saving/restoring of - those registers to the function prologue/epilogue, and make - non-movem sizes suboptimal. - - This method is not foolproof; it assumes that the "asm reg" - declarations at the beginning of the function really are used - here (beware: they may be moved to temporary registers). - This way, we do not have to save/move the registers around into - temporaries; we can safely use them straight away. - - If you want to check that the allocation was right; then - check the equalities in the first comment. It should say - something like "r13=r13, r11=r11, r12=r12". */ - __asm__ volatile ("\ - .ifnc %0%1%2,$r13$r12$r10 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll clobber in the movem process \n\ - ;; on the stack. Don't mention them to gcc, it will only be \n\ - ;; upset. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - clear.d $r0 \n\ - clear.d $r1 \n\ - clear.d $r2 \n\ - clear.d $r3 \n\ - clear.d $r4 \n\ - clear.d $r5 \n\ - clear.d $r6 \n\ - clear.d $r7 \n\ - clear.d $r8 \n\ - clear.d $r9 \n\ - clear.d $r10 \n\ - clear.d $r11 \n\ - \n\ - ;; Now we've got this: \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 12*4,$r12 \n\ -0: \n\ - subq 12*4,$r12 \n\ -1: \n\ - bge 0b \n\ - movem $r11,[$r13+] \n\ - \n\ - addq 12*4,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10 \n\ -2: \n\ - .section .fixup,\"ax\" \n\ -3: \n\ - movem [$sp],$r10 \n\ - addq 12*4,$r10 \n\ - addq 12*4,$r13 \n\ - movem $r10,[$sp] \n\ - jump 0b \n\ - clear.d $r10 \n\ - \n\ - .previous \n\ - .section __ex_table,\"a\" \n\ - .dword 1b,3b \n\ - .previous" - - /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn) - /* Inputs */ : "0" (dst), "1" (n), "2" (retn) - /* Clobber */ : "r11"); - } - - while (n >= 16) - { - __asm_clear_16 (dst, retn); - n -= 16; - } - - /* Having a separate by-four loops cuts down on cache footprint. - FIXME: Test with and without; increasing switch to be 0..15. */ - while (n >= 4) - { - __asm_clear_4 (dst, retn); - n -= 4; - } - - switch (n) - { - case 0: - break; - case 1: - __asm_clear_1 (dst, retn); - break; - case 2: - __asm_clear_2 (dst, retn); - break; - case 3: - __asm_clear_3 (dst, retn); - break; - } - - return retn; -} diff --git a/trunk/arch/cris/arch-v32/mm/Makefile b/trunk/arch/cris/arch-v32/mm/Makefile deleted file mode 100644 index 9146f88484b1..000000000000 --- a/trunk/arch/cris/arch-v32/mm/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# Makefile for the Linux/cris parts of the memory manager. - -obj-y := mmu.o init.o tlb.o intmem.o diff --git a/trunk/arch/cris/arch-v32/mm/init.c b/trunk/arch/cris/arch-v32/mm/init.c deleted file mode 100644 index f2fba27d822c..000000000000 --- a/trunk/arch/cris/arch-v32/mm/init.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Set up paging and the MMU. - * - * Copyright (C) 2000-2003, Axis Communications AB. - * - * Authors: Bjorn Wesen - * Tobias Anderberg , CRISv32 port. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void tlb_init(void); - -/* - * The kernel is already mapped with linear mapping at kseg_c so there's no - * need to map it with a page table. However, head.S also temporarily mapped it - * at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various - * other paging stuff. - */ -void __init -cris_mmu_init(void) -{ - unsigned long mmu_config; - unsigned long mmu_kbase_hi; - unsigned long mmu_kbase_lo; - unsigned short mmu_page_id; - - /* - * Make sure the current pgd table points to something sane, even if it - * is most probably not used until the next switch_mm. - */ - per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd; - -#ifdef CONFIG_SMP - { - pgd_t **pgd; - pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id()); - SUPP_BANK_SEL(1); - SUPP_REG_WR(RW_MM_TLB_PGD, pgd); - SUPP_BANK_SEL(2); - SUPP_REG_WR(RW_MM_TLB_PGD, pgd); - } -#endif - - /* Initialise the TLB. Function found in tlb.c. */ - tlb_init(); - - /* Enable exceptions and initialize the kernel segments. */ - mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on) | - REG_STATE(mmu, rw_mm_cfg, acc, on) | - REG_STATE(mmu, rw_mm_cfg, ex, on) | - REG_STATE(mmu, rw_mm_cfg, inv, on) | - REG_STATE(mmu, rw_mm_cfg, seg_f, linear) | - REG_STATE(mmu, rw_mm_cfg, seg_e, linear) | - REG_STATE(mmu, rw_mm_cfg, seg_d, page) | - REG_STATE(mmu, rw_mm_cfg, seg_c, linear) | - REG_STATE(mmu, rw_mm_cfg, seg_b, linear) | -#ifndef CONFIG_ETRAXFS_SIM - REG_STATE(mmu, rw_mm_cfg, seg_a, page) | -#else - REG_STATE(mmu, rw_mm_cfg, seg_a, linear) | -#endif - REG_STATE(mmu, rw_mm_cfg, seg_9, page) | - REG_STATE(mmu, rw_mm_cfg, seg_8, page) | - REG_STATE(mmu, rw_mm_cfg, seg_7, page) | - REG_STATE(mmu, rw_mm_cfg, seg_6, page) | - REG_STATE(mmu, rw_mm_cfg, seg_5, page) | - REG_STATE(mmu, rw_mm_cfg, seg_4, page) | - REG_STATE(mmu, rw_mm_cfg, seg_3, page) | - REG_STATE(mmu, rw_mm_cfg, seg_2, page) | - REG_STATE(mmu, rw_mm_cfg, seg_1, page) | - REG_STATE(mmu, rw_mm_cfg, seg_0, page)); - - mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) | - REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) | -#ifndef CONFIG_ETRAXFS_SIM - REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) | -#else - REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x0) | -#endif - REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) | -#ifndef CONFIG_ETRAXFS_SIM - REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) | -#else - REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa) | -#endif - REG_FIELD(mmu, rw_mm_kbase_hi, base_9, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_hi, base_8, 0x0)); - - mmu_kbase_lo = ( REG_FIELD(mmu, rw_mm_kbase_lo, base_7, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_6, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_5, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_3, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_2, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_1, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0x0)); - - mmu_page_id = REG_FIELD(mmu, rw_mm_tlb_hi, pid, 0); - - /* Update the instruction MMU. */ - SUPP_BANK_SEL(BANK_IM); - SUPP_REG_WR(RW_MM_CFG, mmu_config); - SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi); - SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo); - SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id); - - /* Update the data MMU. */ - SUPP_BANK_SEL(BANK_DM); - SUPP_REG_WR(RW_MM_CFG, mmu_config); - SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi); - SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo); - SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id); - - SPEC_REG_WR(SPEC_REG_PID, 0); - - /* - * The MMU has been enabled ever since head.S but just to make it - * totally obvious enable it here as well. - */ - SUPP_BANK_SEL(BANK_GC); - SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */ -} - -void __init -paging_init(void) -{ - int i; - unsigned long zones_size[MAX_NR_ZONES]; - - printk("Setting up paging and the MMU.\n"); - - /* Clear out the init_mm.pgd that will contain the kernel's mappings. */ - for(i = 0; i < PTRS_PER_PGD; i++) - swapper_pg_dir[i] = __pgd(0); - - cris_mmu_init(); - - /* - * Initialize the bad page table and bad page to point to a couple of - * allocated pages. - */ - empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); - memset((void *) empty_zero_page, 0, PAGE_SIZE); - - /* All pages are DMA'able in Etrax, so put all in the DMA'able zone. */ - zones_size[0] = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT; - - for (i = 1; i < MAX_NR_ZONES; i++) - zones_size[i] = 0; - - /* - * Use free_area_init_node instead of free_area_init, because it is - * designed for systems where the DRAM starts at an address - * substantially higher than 0, like us (we start at PAGE_OFFSET). This - * saves space in the mem_map page array. - */ - free_area_init_node(0, &contig_page_data, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0); - - mem_map = contig_page_data.node_mem_map; -} diff --git a/trunk/arch/cris/arch-v32/mm/intmem.c b/trunk/arch/cris/arch-v32/mm/intmem.c deleted file mode 100644 index 41ee7f7997fd..000000000000 --- a/trunk/arch/cris/arch-v32/mm/intmem.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Simple allocator for internal RAM in ETRAX FS - * - * Copyright (c) 2004 Axis Communications AB. - */ - -#include -#include -#include -#include - -#define STATUS_FREE 0 -#define STATUS_ALLOCATED 1 - -struct intmem_allocation { - struct list_head entry; - unsigned int size; - unsigned offset; - char status; -}; - - -static struct list_head intmem_allocations; -static void* intmem_virtual; - -static void crisv32_intmem_init(void) -{ - static int initiated = 0; - if (!initiated) { - struct intmem_allocation* alloc = - (struct intmem_allocation*)kmalloc(sizeof *alloc, GFP_KERNEL); - INIT_LIST_HEAD(&intmem_allocations); - intmem_virtual = ioremap(MEM_INTMEM_START, MEM_INTMEM_SIZE); - initiated = 1; - alloc->size = MEM_INTMEM_SIZE; - alloc->offset = 0; - alloc->status = STATUS_FREE; - list_add_tail(&alloc->entry, &intmem_allocations); - } -} - -void* crisv32_intmem_alloc(unsigned size, unsigned align) -{ - struct intmem_allocation* allocation; - struct intmem_allocation* tmp; - void* ret = NULL; - - preempt_disable(); - crisv32_intmem_init(); - - list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) { - int alignment = allocation->offset % align; - alignment = alignment ? align - alignment : alignment; - - if (allocation->status == STATUS_FREE && - allocation->size >= size + alignment) { - if (allocation->size > size + alignment) { - struct intmem_allocation* alloc = - (struct intmem_allocation*) - kmalloc(sizeof *alloc, GFP_ATOMIC); - alloc->status = STATUS_FREE; - alloc->size = allocation->size - size - alignment; - alloc->offset = allocation->offset + size; - list_add(&alloc->entry, &allocation->entry); - - if (alignment) { - struct intmem_allocation* tmp; - tmp = (struct intmem_allocation*) - kmalloc(sizeof *tmp, GFP_ATOMIC); - tmp->offset = allocation->offset; - tmp->size = alignment; - tmp->status = STATUS_FREE; - allocation->offset += alignment; - list_add_tail(&tmp->entry, &allocation->entry); - } - } - allocation->status = STATUS_ALLOCATED; - allocation->size = size; - ret = (void*)((int)intmem_virtual + allocation->offset); - } - } - preempt_enable(); - return ret; -} - -void crisv32_intmem_free(void* addr) -{ - struct intmem_allocation* allocation; - struct intmem_allocation* tmp; - - if (addr == NULL) - return; - - preempt_disable(); - crisv32_intmem_init(); - - list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) { - if (allocation->offset == (int)(addr - intmem_virtual)) { - struct intmem_allocation* prev = - list_entry(allocation->entry.prev, - struct intmem_allocation, entry); - struct intmem_allocation* next = - list_entry(allocation->entry.next, - struct intmem_allocation, entry); - - allocation->status = STATUS_FREE; - /* Join with prev and/or next if also free */ - if (prev->status == STATUS_FREE) { - prev->size += allocation->size; - list_del(&allocation->entry); - kfree(allocation); - allocation = prev; - } - if (next->status == STATUS_FREE) { - allocation->size += next->size; - list_del(&next->entry); - kfree(next); - } - preempt_enable(); - return; - } - } - preempt_enable(); -} - -void* crisv32_intmem_phys_to_virt(unsigned long addr) -{ - return (void*)(addr - MEM_INTMEM_START+ - (unsigned long)intmem_virtual); -} - -unsigned long crisv32_intmem_virt_to_phys(void* addr) -{ - return (unsigned long)((unsigned long )addr - - (unsigned long)intmem_virtual + MEM_INTMEM_START); -} - - - diff --git a/trunk/arch/cris/arch-v32/mm/mmu.S b/trunk/arch/cris/arch-v32/mm/mmu.S deleted file mode 100644 index 27b70e5006af..000000000000 --- a/trunk/arch/cris/arch-v32/mm/mmu.S +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (C) 2003 Axis Communications AB - * - * Authors: Mikael Starvik (starvik@axis.com) - * - * Code for the fault low-level handling routines. - * - */ - -#include -#include - -; Save all register. Must save in same order as struct pt_regs. -.macro SAVE_ALL - subq 12, $sp - move $erp, [$sp] - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $ccs, [$sp] - subq 4, $sp - move $spc, [$sp] - subq 4, $sp - move $mof, [$sp] - subq 4, $sp - move $srs, [$sp] - subq 4, $sp - move.d $acr, [$sp] - subq 14*4, $sp - movem $r13, [$sp] - subq 4, $sp - move.d $r10, [$sp] -.endm - -; Bus fault handler. Extracts relevant information and calls mm subsystem -; to handle the fault. -.macro MMU_BUS_FAULT_HANDLER handler, mmu, we, ex - .globl \handler -\handler: - SAVE_ALL - move \mmu, $srs ; Select MMU support register bank - move.d $sp, $r11 ; regs - moveq 1, $r12 ; protection fault - moveq \we, $r13 ; write exception? - orq \ex << 1, $r13 ; execute? - move $s3, $r10 ; rw_mm_cause - and.d ~8191, $r10 ; Get faulting page start address - - jsr do_page_fault - nop - ba ret_from_intr - nop -.endm - -; Refill handler. Three cases may occur: -; 1. PMD and PTE exists in mm subsystem but not in TLB -; 2. PMD exists but not PTE -; 3. PMD doesn't exist -; The code below handles case 1 and calls the mm subsystem for case 2 and 3. -; Do not touch this code without very good reasons and extensive testing. -; Note that the code is optimized to minimize stalls (makes the code harder -; to read). -; -; Each page is 8 KB. Each PMD holds 8192/4 PTEs (each PTE is 4 bytes) so each -; PMD holds 16 MB of virtual memory. -; Bits 0-12 : Offset within a page -; Bits 13-23 : PTE offset within a PMD -; Bits 24-31 : PMD offset within the PGD - -.macro MMU_REFILL_HANDLER handler, mmu - .globl \handler -\handler: - subq 4, $sp -; (The pipeline stalls for one cycle; $sp used as address in the next cycle.) - move $srs, [$sp] - subq 4, $sp - move \mmu, $srs ; Select MMU support register bank - move.d $acr, [$sp] - subq 4, $sp - move.d $r0, [$sp] -#ifdef CONFIG_SMP - move $s7, $acr ; PGD -#else - move.d per_cpu__current_pgd, $acr ; PGD -#endif - ; Look up PMD in PGD - move $s3, $r0 ; rw_mm_cause - lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31) - move.d [$acr], $acr ; PGD for the current process - addi $r0.d, $acr, $acr - move $s3, $r0 ; rw_mm_cause - move.d [$acr], $acr ; Get PMD - beq 1f - ; Look up PTE in PMD - lsrq PAGE_SHIFT, $r0 - and.w PAGE_MASK, $acr ; Remove PMD flags - and.d 0x7ff, $r0 ; Get PTE index into PMD (bit 13-23) - addi $r0.d, $acr, $acr - move.d [$acr], $acr ; Get PTE - beq 2f - move.d [$sp+], $r0 ; Pop r0 in delayslot - ; Store in TLB - move $acr, $s5 - ; Return - move.d [$sp+], $acr - move [$sp], $srs - addq 4, $sp - rete - rfe -1: ; PMD missing, let the mm subsystem fix it up. - move.d [$sp+], $r0 ; Pop r0 -2: ; PTE missing, let the mm subsystem fix it up. - move.d [$sp+], $acr - move [$sp], $srs - addq 4, $sp - SAVE_ALL - move \mmu, $srs - move.d $sp, $r11 ; regs - clear.d $r12 ; Not a protection fault - move.w PAGE_MASK, $acr - move $s3, $r10 ; rw_mm_cause - btstq 9, $r10 ; Check if write access - smi $r13 - and.w PAGE_MASK, $r10 ; Get VPN (virtual address) - jsr do_page_fault - and.w $acr, $r10 - ; Return - ba ret_from_intr - nop -.endm - - ; This is the MMU bus fault handlers. - -MMU_REFILL_HANDLER i_mmu_refill, 1 -MMU_BUS_FAULT_HANDLER i_mmu_invalid, 1, 0, 0 -MMU_BUS_FAULT_HANDLER i_mmu_access, 1, 0, 0 -MMU_BUS_FAULT_HANDLER i_mmu_execute, 1, 0, 1 -MMU_REFILL_HANDLER d_mmu_refill, 2 -MMU_BUS_FAULT_HANDLER d_mmu_invalid, 2, 0, 0 -MMU_BUS_FAULT_HANDLER d_mmu_access, 2, 0, 0 -MMU_BUS_FAULT_HANDLER d_mmu_write, 2, 1, 0 diff --git a/trunk/arch/cris/arch-v32/mm/tlb.c b/trunk/arch/cris/arch-v32/mm/tlb.c deleted file mode 100644 index 8233406798d3..000000000000 --- a/trunk/arch/cris/arch-v32/mm/tlb.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Low level TLB handling. - * - * Copyright (C) 2000-2003, Axis Communications AB. - * - * Authors: Bjorn Wesen - * Tobias Anderberg , CRISv32 port. - */ - -#include -#include -#include -#include - -#define UPDATE_TLB_SEL_IDX(val) \ -do { \ - unsigned long tlb_sel; \ - \ - tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, val); \ - SUPP_REG_WR(RW_MM_TLB_SEL, tlb_sel); \ -} while(0) - -#define UPDATE_TLB_HILO(tlb_hi, tlb_lo) \ -do { \ - SUPP_REG_WR(RW_MM_TLB_HI, tlb_hi); \ - SUPP_REG_WR(RW_MM_TLB_LO, tlb_lo); \ -} while(0) - -/* - * The TLB can host up to 256 different mm contexts at the same time. The running - * context is found in the PID register. Each TLB entry contains a page_id that - * has to match the PID register to give a hit. page_id_map keeps track of which - * mm's is assigned to which page_id's, making sure it's known when to - * invalidate TLB entries. - * - * The last page_id is never running, it is used as an invalid page_id so that - * it's possible to make TLB entries that will nerver match. - * - * Note; the flushes needs to be atomic otherwise an interrupt hander that uses - * vmalloc'ed memory might cause a TLB load in the middle of a flush. - */ - -/* Flush all TLB entries. */ -void -__flush_tlb_all(void) -{ - int i; - int mmu; - unsigned long flags; - unsigned long mmu_tlb_hi; - unsigned long mmu_tlb_sel; - - /* - * Mask with 0xf so similar TLB entries aren't written in the same 4-way - * entry group. - */ - local_save_flags(flags); - local_irq_disable(); - - for (mmu = 1; mmu <= 2; mmu++) { - SUPP_BANK_SEL(mmu); /* Select the MMU */ - for (i = 0; i < NUM_TLB_ENTRIES; i++) { - /* Store invalid entry */ - mmu_tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, i); - - mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, INVALID_PAGEID) - | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, i & 0xf)); - - SUPP_REG_WR(RW_MM_TLB_SEL, mmu_tlb_sel); - SUPP_REG_WR(RW_MM_TLB_HI, mmu_tlb_hi); - SUPP_REG_WR(RW_MM_TLB_LO, 0); - } - } - - local_irq_restore(flags); -} - -/* Flush an entire user address space. */ -void -__flush_tlb_mm(struct mm_struct *mm) -{ - int i; - int mmu; - unsigned long flags; - unsigned long page_id; - unsigned long tlb_hi; - unsigned long mmu_tlb_hi; - - page_id = mm->context.page_id; - - if (page_id == NO_CONTEXT) - return; - - /* Mark the TLB entries that match the page_id as invalid. */ - local_save_flags(flags); - local_irq_disable(); - - for (mmu = 1; mmu <= 2; mmu++) { - SUPP_BANK_SEL(mmu); - for (i = 0; i < NUM_TLB_ENTRIES; i++) { - UPDATE_TLB_SEL_IDX(i); - - /* Get the page_id */ - SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi); - - /* Check if the page_id match. */ - if ((tlb_hi & 0xff) == page_id) { - mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, - INVALID_PAGEID) - | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, - i & 0xf)); - - UPDATE_TLB_HILO(mmu_tlb_hi, 0); - } - } - } - - local_irq_restore(flags); -} - -/* Invalidate a single page. */ -void -__flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) -{ - int i; - int mmu; - unsigned long page_id; - unsigned long flags; - unsigned long tlb_hi; - unsigned long mmu_tlb_hi; - - page_id = vma->vm_mm->context.page_id; - - if (page_id == NO_CONTEXT) - return; - - addr &= PAGE_MASK; - - /* - * Invalidate those TLB entries that match both the mm context and the - * requested virtual address. - */ - local_save_flags(flags); - local_irq_disable(); - - for (mmu = 1; mmu <= 2; mmu++) { - SUPP_BANK_SEL(mmu); - for (i = 0; i < NUM_TLB_ENTRIES; i++) { - UPDATE_TLB_SEL_IDX(i); - SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi); - - /* Check if page_id and address matches */ - if (((tlb_hi & 0xff) == page_id) && - ((tlb_hi & PAGE_MASK) == addr)) { - mmu_tlb_hi = REG_FIELD(mmu, rw_mm_tlb_hi, pid, - INVALID_PAGEID) | addr; - - UPDATE_TLB_HILO(mmu_tlb_hi, 0); - } - } - } - - local_irq_restore(flags); -} - -/* - * Initialize the context related info for a new mm_struct - * instance. - */ - -int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - mm->context.page_id = NO_CONTEXT; - return 0; -} - -/* Called in schedule() just before actually doing the switch_to. */ -void -switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - int cpu = smp_processor_id(); - - /* Make sure there is a MMU context. */ - spin_lock(&next->page_table_lock); - get_mmu_context(next); - cpu_set(cpu, next->cpu_vm_mask); - spin_unlock(&next->page_table_lock); - - /* - * Remember the pgd for the fault handlers. Keep a seperate copy of it - * because current and active_mm might be invalid at points where - * there's still a need to derefer the pgd. - */ - per_cpu(current_pgd, cpu) = next->pgd; - - /* Switch context in the MMU. */ - if (tsk && tsk->thread_info) - { - SPEC_REG_WR(SPEC_REG_PID, next->context.page_id | tsk->thread_info->tls); - } - else - { - SPEC_REG_WR(SPEC_REG_PID, next->context.page_id); - } -} - diff --git a/trunk/arch/cris/arch-v32/output_arch.ld b/trunk/arch/cris/arch-v32/output_arch.ld deleted file mode 100644 index d60a57db0ec2..000000000000 --- a/trunk/arch/cris/arch-v32/output_arch.ld +++ /dev/null @@ -1,2 +0,0 @@ -/* At the time of this writing, there's no equivalent ld option. */ -OUTPUT_ARCH (crisv32) diff --git a/trunk/arch/cris/arch-v32/vmlinux.lds.S b/trunk/arch/cris/arch-v32/vmlinux.lds.S deleted file mode 100644 index adb94605d92a..000000000000 --- a/trunk/arch/cris/arch-v32/vmlinux.lds.S +++ /dev/null @@ -1,134 +0,0 @@ -/* ld script to make the Linux/CRIS kernel - * Authors: Bjorn Wesen (bjornw@axis.com) - * - * It is VERY DANGEROUS to fiddle around with the symbols in this - * script. It is for example quite vital that all generated sections - * that are used are actually named here, otherwise the linker will - * put them at the end, where the init stuff is which is FREED after - * the kernel has booted. - */ - -#include -#include - -jiffies = jiffies_64; -SECTIONS -{ - . = DRAM_VIRTUAL_BASE; - dram_start = .; - ebp_start = .; - - /* The boot section is only necessary until the VCS top level testbench */ - /* includes both flash and DRAM. */ - .boot : { *(.boot) } - - . = DRAM_VIRTUAL_BASE + 0x4000; /* See head.S and pages reserved at the start. */ - - _text = .; /* Text and read-only data. */ - text_start = .; /* Lots of aliases. */ - _stext = .; - __stext = .; - .text : { - *(.text) - SCHED_TEXT - LOCK_TEXT - *(.fixup) - *(.text.__*) - } - - _etext = . ; /* End of text section. */ - __etext = .; - - . = ALIGN(4); /* Exception table. */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - RODATA - - . = ALIGN (4); - ___data_start = . ; - __Sdata = . ; - .data : { /* Data */ - *(.data) - } - __edata = . ; /* End of data section. */ - _edata = . ; - - . = ALIGN(8192); /* init_task and stack, must be aligned. */ - .data.init_task : { *(.data.init_task) } - - . = ALIGN(8192); /* Init code and data. */ - __init_begin = .; - .init.text : { - _sinittext = .; - *(.init.text) - _einittext = .; - } - .init.data : { *(.init.data) } - . = ALIGN(16); - __setup_start = .; - .init.setup : { *(.init.setup) } - __setup_end = .; - __start___param = .; - __param : { *(__param) } - __stop___param = .; - .initcall.init : { - __initcall_start = .; - *(.initcall1.init); - *(.initcall2.init); - *(.initcall3.init); - *(.initcall4.init); - *(.initcall5.init); - *(.initcall6.init); - *(.initcall7.init); - __initcall_end = .; - } - - .con_initcall.init : { - __con_initcall_start = .; - *(.con_initcall.init) - __con_initcall_end = .; - } - SECURITY_INIT - - __per_cpu_start = .; - .data.percpu : { *(.data.percpu) } - __per_cpu_end = .; - - .init.ramfs : { - __initramfs_start = .; - *(.init.ramfs) - __initramfs_end = .; - /* - * We fill to the next page, so we can discard all init - * pages without needing to consider what payload might be - * appended to the kernel image. - */ - FILL (0); - . = ALIGN (8192); - } - - __vmlinux_end = .; /* Last address of the physical file. */ - __init_end = .; - - __data_end = . ; /* Move to _edata? */ - __bss_start = .; /* BSS. */ - .bss : { - *(COMMON) - *(.bss) - } - - . = ALIGN (0x20); - _end = .; - __end = .; - - /* Sections to be discarded */ - /DISCARD/ : { - *(.text.exit) - *(.data.exit) - *(.exitcall.exit) - } - - dram_end = dram_start + CONFIG_ETRAX_DRAM_SIZE*1024*1024; -} diff --git a/trunk/arch/cris/defconfig b/trunk/arch/cris/defconfig index 142a10818af3..32c9c987dbaa 100644 --- a/trunk/arch/cris/defconfig +++ b/trunk/arch/cris/defconfig @@ -1,27 +1,22 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11 -# Mon Jun 20 13:42:02 2005 # CONFIG_MMU=y CONFIG_UID16=y CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_CRIS=y # # Code maturity level options # CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y +CONFIG_STANDALONE=y CONFIG_BROKEN_ON_SMP=y # # General setup # -CONFIG_LOCALVERSION="" -# CONFIG_SWAP is not set +CONFIG_SWAP=y # CONFIG_SYSVIPC is not set # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set @@ -29,19 +24,16 @@ CONFIG_SYSCTL=y # CONFIG_AUDIT is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y # CONFIG_KALLSYMS is not set CONFIG_FUTEX=y CONFIG_EPOLL=y +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set # # Loadable module support @@ -53,28 +45,23 @@ CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_GENERIC_HARDIRQS=y -# CONFIG_SMP is not set CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc" -# CONFIG_ETRAX_WATCHDOG is not set +CONFIG_ETRAX_WATCHDOG=y +CONFIG_ETRAX_WATCHDOG_NICE_DOGGY=y CONFIG_ETRAX_FAST_TIMER=y # CONFIG_PREEMPT is not set -# CONFIG_OOM_REBOOT is not set # # Hardware setup # -# CONFIG_ETRAX100LX is not set -CONFIG_ETRAX100LX_V2=y +CONFIG_ETRAX100LX=y +# CONFIG_ETRAX100LX_V2 is not set # CONFIG_SVINTO_SIM is not set -# CONFIG_ETRAXFS is not set -# CONFIG_ETRAXFS_SIM is not set CONFIG_ETRAX_ARCH_V10=y -# CONFIG_ETRAX_ARCH_V32 is not set -CONFIG_ETRAX_DRAM_SIZE=32 +CONFIG_ETRAX_DRAM_SIZE=16 CONFIG_ETRAX_FLASH_BUSWIDTH=2 -CONFIG_ETRAX_FLASH1_SIZE=4 -CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000 +CONFIG_CRIS_LOW_MAP=y +CONFIG_ETRAX_DRAM_VIRTUAL_BASE=60000000 CONFIG_ETRAX_PA_LEDS=y # CONFIG_ETRAX_PB_LEDS is not set # CONFIG_ETRAX_CSP0_LEDS is not set @@ -94,13 +81,13 @@ CONFIG_ETRAX_RESCUE_SER0=y # CONFIG_ETRAX_RESCUE_SER1 is not set # CONFIG_ETRAX_RESCUE_SER2 is not set # CONFIG_ETRAX_RESCUE_SER3 is not set -CONFIG_ETRAX_DEF_R_WAITSTATES=0x95a6 -CONFIG_ETRAX_DEF_R_BUS_CONFIG=0x4 +CONFIG_ETRAX_DEF_R_WAITSTATES=0x95f8 +CONFIG_ETRAX_DEF_R_BUS_CONFIG=0x104 CONFIG_ETRAX_SDRAM=y -CONFIG_ETRAX_DEF_R_SDRAM_CONFIG=0x09e05757 +CONFIG_ETRAX_DEF_R_SDRAM_CONFIG=0x00e03636 CONFIG_ETRAX_DEF_R_SDRAM_TIMING=0x80008002 CONFIG_ETRAX_DEF_R_PORT_PA_DIR=0x1d -CONFIG_ETRAX_DEF_R_PORT_PA_DATA=0x00 +CONFIG_ETRAX_DEF_R_PORT_PA_DATA=0xf0 CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG=0x00 CONFIG_ETRAX_DEF_R_PORT_PB_DIR=0x1e CONFIG_ETRAX_DEF_R_PORT_PB_DATA=0xf3 @@ -110,17 +97,16 @@ CONFIG_ETRAX_DEF_R_PORT_PB_DATA=0xf3 # Drivers for built-in interfaces # CONFIG_ETRAX_ETHERNET=y +CONFIG_NET_ETHERNET=y # CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y CONFIG_ETRAX_SERIAL=y -# CONFIG_ETRAX_SERIAL_FAST_TIMER is not set -# CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST is not set -CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS=5 +CONFIG_ETRAX_SERIAL_FAST_TIMER=y CONFIG_ETRAX_SERIAL_PORT0=y -# CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_OUT is not set -CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT=y -# CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_IN is not set -CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN=y +# CONFIG_CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_OUT is not set +CONFIG_CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT=y +# CONFIG_CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_IN is not set +CONFIG_CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN=y CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE=y # CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA is not set # CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB is not set @@ -135,10 +121,10 @@ CONFIG_ETRAX_SER0_DSR_ON_PB_BIT=-1 CONFIG_ETRAX_SER0_CD_ON_PB_BIT=-1 # CONFIG_ETRAX_SERIAL_PORT1 is not set CONFIG_ETRAX_SERIAL_PORT2=y -# CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_OUT is not set -CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT=y -# CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_IN is not set -CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN=y +# CONFIG_CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_OUT is not set +CONFIG_CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT=y +# CONFIG_CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_IN is not set +CONFIG_CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN=y CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE=y # CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA is not set # CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB is not set @@ -152,51 +138,44 @@ CONFIG_ETRAX_SER2_RI_ON_PB_BIT=-1 CONFIG_ETRAX_SER2_DSR_ON_PB_BIT=-1 CONFIG_ETRAX_SER2_CD_ON_PB_BIT=-1 # CONFIG_ETRAX_SERIAL_PORT3 is not set -CONFIG_ETRAX_RS485=y -# CONFIG_ETRAX_RS485_ON_PA is not set -# CONFIG_ETRAX_RS485_DISABLE_RECEIVER is not set -CONFIG_ETRAX_IDE=y -CONFIG_ETRAX_IDE_DELAY=15 -CONFIG_ETRAX_IDE_PB7_RESET=y -# CONFIG_ETRAX_IDE_G27_RESET is not set -CONFIG_ETRAX_USB_HOST=y -CONFIG_ETRAX_USB_HOST_PORT1=y -CONFIG_ETRAX_USB_HOST_PORT2=y +# CONFIG_ETRAX_RS485 is not set +# CONFIG_ETRAX_IDE is not set +# CONFIG_IDE is not set +# CONFIG_ETRAX_USB_HOST is not set CONFIG_ETRAX_AXISFLASHMAP=y CONFIG_ETRAX_PTABLE_SECTOR=65536 +CONFIG_MTD=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_OBSOLETE_CHIPS=y +CONFIG_MTD_AMDSTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CONCAT=y # CONFIG_ETRAX_I2C is not set -# CONFIG_ETRAX_GPIO is not set -CONFIG_ETRAX_RTC=y -CONFIG_ETRAX_DS1302=y -# CONFIG_ETRAX_PCF8563 is not set -CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT=y -CONFIG_ETRAX_DS1302_RSTBIT=0 -CONFIG_ETRAX_DS1302_SCLBIT=1 -CONFIG_ETRAX_DS1302_SDABIT=0 -CONFIG_ETRAX_DS1302_TRICKLE_CHARGE=0 +CONFIG_ETRAX_GPIO=y +CONFIG_ETRAX_PA_BUTTON_BITMASK=0x02 +CONFIG_ETRAX_PA_CHANGEABLE_DIR=0x00 +CONFIG_ETRAX_PA_CHANGEABLE_BITS=0xFF +CONFIG_ETRAX_PB_CHANGEABLE_DIR=0x00 +CONFIG_ETRAX_PB_CHANGEABLE_BITS=0xFF +# CONFIG_ETRAX_RTC is not set # # Generic Driver Options # -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set # # Memory Technology Devices (MTD) # -CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CONCAT=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set # # User Modules And Translation Layers # -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set @@ -204,30 +183,14 @@ CONFIG_MTD_BLOCK=y # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=y # CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_GEN_PROBE=y # CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set # CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_AMDSTD_RETRY=0 # CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -CONFIG_MTD_OBSOLETE_CHIPS=y -CONFIG_MTD_AMDSTD=y # CONFIG_MTD_SHARP is not set # CONFIG_MTD_JEDEC is not set @@ -241,13 +204,11 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y # Self-contained MTD device drivers # # CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set CONFIG_MTD_MTDRAM=y CONFIG_MTDRAM_TOTAL_SIZE=0 CONFIG_MTDRAM_ERASE_SIZE=64 CONFIG_MTDRAM_ABS_POS=0x0 # CONFIG_MTD_BLKMTD is not set -# CONFIG_MTD_BLOCK2MTD is not set # # Disk-On-Chip Device Drivers @@ -274,25 +235,11 @@ CONFIG_MTDRAM_ABS_POS=0x0 # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_INITRD is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set # # Multi-device support (RAID and LVM) @@ -302,28 +249,6 @@ CONFIG_IOSCHED_CFQ=y # # ATA/ATAPI/MFM/RLL support # -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_IDE_GENERIC is not set -# CONFIG_IDE_ARM is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support @@ -333,6 +258,7 @@ CONFIG_BLK_DEV_IDEDMA=y # # IEEE 1394 (FireWire) support # +# CONFIG_IEEE1394 is not set # # I2O device support @@ -362,9 +288,6 @@ CONFIG_INET=y # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set # # IP: Virtual Server Configuration @@ -378,10 +301,11 @@ CONFIG_NETFILTER=y # IP: Netfilter Configuration # # CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_CONNTRACK_MARK is not set # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set # # SCTP Configuration (EXPERIMENTAL) @@ -399,12 +323,12 @@ CONFIG_NETFILTER=y # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set +# CONFIG_NET_HW_FLOWCONTROL is not set # # QoS and/or fair queueing # # CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set # # Network testing @@ -414,26 +338,7 @@ CONFIG_NETFILTER=y # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -# CONFIG_BT_SCO is not set -CONFIG_BT_RFCOMM=y -# CONFIG_BT_RFCOMM_TTY is not set -CONFIG_BT_BNEP=y -# CONFIG_BT_BNEP_MC_FILTER is not set -# CONFIG_BT_BNEP_PROTO_FILTER is not set -# CONFIG_BT_HIDP is not set - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIUSB=y -# CONFIG_BT_HCIUSB_SCO is not set -# CONFIG_BT_HCIUART is not set -# CONFIG_BT_HCIBCM203X is not set -# CONFIG_BT_HCIBPA10X is not set -# CONFIG_BT_HCIBFUSB is not set -# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set @@ -443,7 +348,6 @@ CONFIG_NETDEVICES=y # # Ethernet (10 or 100Mbit) # -CONFIG_NET_ETHERNET=y # CONFIG_MII is not set # @@ -485,19 +389,11 @@ CONFIG_NET_ETHERNET=y # # Input device support # -CONFIG_INPUT=y +# CONFIG_INPUT is not set # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set # # Input I/O drivers @@ -508,25 +404,10 @@ CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set # CONFIG_SERIO_SERPORT is not set # CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set # # Input Device Drivers # -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set # # Character devices @@ -545,6 +426,7 @@ CONFIG_MOUSE_PS2=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_QIC02_TAPE is not set # # IPMI @@ -559,10 +441,13 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set # # Ftape, the floppy tape device driver # +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set # CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set @@ -584,15 +469,10 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set - -# -# XFS support -# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set @@ -605,8 +485,7 @@ CONFIG_DNOTIFY=y # # DOS/FAT/NT Filesystems # -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set +# CONFIG_FAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -618,7 +497,6 @@ CONFIG_SYSFS=y # CONFIG_DEVFS_FS is not set # CONFIG_DEVPTS_FS_XATTR is not set CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y @@ -634,15 +512,7 @@ CONFIG_RAMFS=y # CONFIG_EFS_FS is not set CONFIG_JFFS_FS=y CONFIG_JFFS_FS_VERBOSE=0 -# CONFIG_JFFS_PROC_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFFS2_FS_NAND is not set -# CONFIG_JFFS2_FS_NOR_ECC is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -660,13 +530,14 @@ CONFIG_NFS_V3=y # CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set # CONFIG_AFS_FS is not set # @@ -685,121 +556,9 @@ CONFIG_MSDOS_PARTITION=y # # CONFIG_SOUND is not set -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PC-card bridges -# - # # USB support # -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_BANDWIDTH is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_SL811_HCD is not set - -# -# USB Device Class drivers -# - -# -# USB Bluetooth TTY can only be used with disabled Bluetooth subsystem -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# -# CONFIG_USB_STORAGE is not set - -# -# USB Input Devices -# -# CONFIG_USB_HID is not set - -# -# USB HID Boot Protocol drivers -# -# CONFIG_USB_KBD is not set -# CONFIG_USB_MOUSE is not set -# CONFIG_USB_AIPTEK is not set -# CONFIG_USB_WACOM is not set -# CONFIG_USB_KBTAB is not set -# CONFIG_USB_POWERMATE is not set -# CONFIG_USB_MTOUCH is not set -# CONFIG_USB_EGALAX is not set -# CONFIG_USB_XPAD is not set -# CONFIG_USB_ATI_REMOTE is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set - -# -# USB Multimedia devices -# -# CONFIG_USB_DABUSB is not set - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -CONFIG_USB_RTL8150=y -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGETKIT is not set -# CONFIG_USB_PHIDGETSERVO is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_TEST is not set - -# -# USB ATM/DSL drivers -# # # USB Gadget Support @@ -809,17 +568,14 @@ CONFIG_USB_RTL8150=y # # Kernel hacking # -# CONFIG_PROFILING is not set -# CONFIG_SYSTEM_PROFILER is not set +# CONFIG_PROFILE is not set # CONFIG_ETRAX_KGDB is not set # CONFIG_DEBUG_INFO is not set # CONFIG_FRAME_POINTER is not set -# CONFIG_DEBUG_NMI_OOPS is not set # # Security options # -# CONFIG_KEYS is not set # CONFIG_SECURITY is not set # @@ -827,15 +583,9 @@ CONFIG_USB_RTL8150=y # # CONFIG_CRYPTO is not set -# -# Hardware crypto devices -# - # # Library routines # -# CONFIG_CRC_CCITT is not set -CONFIG_CRC32=y +# CONFIG_CRC32 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y diff --git a/trunk/arch/cris/kernel/Makefile b/trunk/arch/cris/kernel/Makefile index c8e8ea570989..1546a0e74047 100644 --- a/trunk/arch/cris/kernel/Makefile +++ b/trunk/arch/cris/kernel/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile,v 1.12 2004/10/19 13:07:43 starvik Exp $ +# $Id: Makefile,v 1.10 2004/05/14 10:18:12 starvik Exp $ # # Makefile for the linux kernel. # @@ -10,7 +10,6 @@ obj-y := process.o traps.o irq.o ptrace.o setup.o \ obj-$(CONFIG_MODULES) += crisksyms.o obj-$(CONFIG_MODULES) += module.o -obj-$(CONFIG_SYSTEM_PROFILER) += profile.o clean: diff --git a/trunk/arch/cris/kernel/crisksyms.c b/trunk/arch/cris/kernel/crisksyms.c index 85833d704ebb..7141bbecd7e4 100644 --- a/trunk/arch/cris/kernel/crisksyms.c +++ b/trunk/arch/cris/kernel/crisksyms.c @@ -27,13 +27,13 @@ extern void __Udiv(void); extern void __Umod(void); extern void __Div(void); extern void __Mod(void); -extern void __ashldi3(void); extern void __ashrdi3(void); -extern void __lshrdi3(void); -extern void iounmap(volatile void * __iomem); +extern void iounmap(void *addr); /* Platform dependent support */ EXPORT_SYMBOL(dump_thread); +EXPORT_SYMBOL(enable_irq); +EXPORT_SYMBOL(disable_irq); EXPORT_SYMBOL(kernel_thread); EXPORT_SYMBOL(get_cmos_time); EXPORT_SYMBOL(loops_per_usec); @@ -57,9 +57,7 @@ EXPORT_SYMBOL(__Udiv); EXPORT_SYMBOL(__Umod); EXPORT_SYMBOL(__Div); EXPORT_SYMBOL(__Mod); -EXPORT_SYMBOL(__ashldi3); EXPORT_SYMBOL(__ashrdi3); -EXPORT_SYMBOL(__lshrdi3); /* Memory functions */ EXPORT_SYMBOL(__ioremap); @@ -71,10 +69,23 @@ EXPORT_SYMBOL(__down); EXPORT_SYMBOL(__down_interruptible); EXPORT_SYMBOL(__down_trylock); +/* Export shadow registers for the CPU I/O pins */ +EXPORT_SYMBOL(genconfig_shadow); +EXPORT_SYMBOL(port_pa_data_shadow); +EXPORT_SYMBOL(port_pa_dir_shadow); +EXPORT_SYMBOL(port_pb_data_shadow); +EXPORT_SYMBOL(port_pb_dir_shadow); +EXPORT_SYMBOL(port_pb_config_shadow); +EXPORT_SYMBOL(port_g_data_shadow); + /* Userspace access functions */ EXPORT_SYMBOL(__copy_user_zeroing); EXPORT_SYMBOL(__copy_user); +/* Cache flush functions */ +EXPORT_SYMBOL(flush_etrax_cache); +EXPORT_SYMBOL(prepare_rx_descriptor); + #undef memcpy #undef memset extern void * memset(void *, int, __kernel_size_t); diff --git a/trunk/arch/cris/kernel/irq.c b/trunk/arch/cris/kernel/irq.c index 30deaf1b728a..d848b9407457 100644 --- a/trunk/arch/cris/kernel/irq.c +++ b/trunk/arch/cris/kernel/irq.c @@ -12,6 +12,8 @@ * shouldn't result in any weird surprises, and installing new handlers * should be easier. * + * Notice Linux/CRIS: these routines do not care about SMP + * */ /* @@ -22,7 +24,6 @@ #include #include #include -#include #include #include @@ -35,56 +36,84 @@ #include #include #include -#include +#include #include -void ack_bad_irq(unsigned int irq) +/* Defined in arch specific irq.c */ +extern void arch_setup_irq(int irq); +extern void arch_free_irq(int irq); + +void +disable_irq(unsigned int irq_nr) +{ + unsigned long flags; + + local_save_flags(flags); + local_irq_disable(); + mask_irq(irq_nr); + local_irq_restore(flags); +} + +void +enable_irq(unsigned int irq_nr) { - printk("unexpected IRQ trap at vector %02x\n", irq); + unsigned long flags; + local_save_flags(flags); + local_irq_disable(); + unmask_irq(irq_nr); + local_irq_restore(flags); } +unsigned long +probe_irq_on() +{ + return 0; +} + +EXPORT_SYMBOL(probe_irq_on); + +int +probe_irq_off(unsigned long x) +{ + return 0; +} + +EXPORT_SYMBOL(probe_irq_off); + +/* + * Initial irq handlers. + */ + +static struct irqaction *irq_action[NR_IRQS]; + int show_interrupts(struct seq_file *p, void *v) { - int i = *(loff_t *) v, j; + int i = *(loff_t *) v; struct irqaction * action; unsigned long flags; - if (i == 0) { - seq_printf(p, " "); - for (j=0; jtypename); - seq_printf(p, " %s", action->name); - - for (action=action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - + seq_printf(p, "%2d: %10u %c %s", + i, kstat_this_cpu.irqs[i], + (action->flags & SA_INTERRUPT) ? '+' : ' ', + action->name); + for (action = action->next; action; action = action->next) { + seq_printf(p, ",%s %s", + (action->flags & SA_INTERRUPT) ? " +" : "", + action->name); + } seq_putc(p, '\n'); skip: - spin_unlock_irqrestore(&irq_desc[i].lock, flags); + local_irq_restore(flags); } return 0; } - /* called by the assembler IRQ entry functions defined in irq.h * to dispatch the interrupts to registred handlers * interrupts are disabled upon entry - depending on if the @@ -94,17 +123,164 @@ int show_interrupts(struct seq_file *p, void *v) asmlinkage void do_IRQ(int irq, struct pt_regs * regs) { - unsigned long sp; - irq_enter(); - sp = rdsp(); - if (unlikely((sp & (PAGE_SIZE - 1)) < (PAGE_SIZE/8))) { - printk("do_IRQ: stack overflow: %lX\n", sp); - show_stack(NULL, (unsigned long *)sp); - } - __do_IRQ(irq, regs); + struct irqaction *action; + int do_random, cpu; + int ret, retval = 0; + + cpu = smp_processor_id(); + irq_enter(); + kstat_cpu(cpu).irqs[irq - FIRST_IRQ]++; + action = irq_action[irq - FIRST_IRQ]; + + if (action) { + if (!(action->flags & SA_INTERRUPT)) + local_irq_enable(); + do_random = 0; + do { + ret = action->handler(irq, action->dev_id, regs); + if (ret == IRQ_HANDLED) + do_random |= action->flags; + retval |= ret; + action = action->next; + } while (action); + + if (retval != 1) { + if (retval) { + printk("irq event %d: bogus retval mask %x\n", + irq, retval); + } else { + printk("irq %d: nobody cared\n", irq); + } + } + + if (do_random & SA_SAMPLE_RANDOM) + add_interrupt_randomness(irq); + local_irq_disable(); + } irq_exit(); } +/* this function links in a handler into the chain of handlers for the + given irq, and if the irq has never been registred, the appropriate + handler is entered into the interrupt vector +*/ + +int setup_irq(int irq, struct irqaction * new) +{ + int shared = 0; + struct irqaction *old, **p; + unsigned long flags; + + p = irq_action + irq - FIRST_IRQ; + if ((old = *p) != NULL) { + /* Can't share interrupts unless both agree to */ + if (!(old->flags & new->flags & SA_SHIRQ)) + return -EBUSY; + + /* Can't share interrupts unless both are same type */ + if ((old->flags ^ new->flags) & SA_INTERRUPT) + return -EBUSY; + + /* add new interrupt at end of irq queue */ + do { + p = &old->next; + old = *p; + } while (old); + shared = 1; + } + + if (new->flags & SA_SAMPLE_RANDOM) + rand_initialize_irq(irq); + + local_save_flags(flags); + local_irq_disable(); + *p = new; + + if (!shared) { + /* if the irq wasn't registred before, enter it into the vector table + and unmask it physically + */ + arch_setup_irq(irq); + unmask_irq(irq); + } + + local_irq_restore(flags); + return 0; +} + +/* this function is called by a driver to register an irq handler + Valid flags: + SA_INTERRUPT -> it's a fast interrupt, handler called with irq disabled and + no signal checking etc is performed upon exit + SA_SHIRQ -> the interrupt can be shared between different handlers, the handler + is required to check if the irq was "aimed" at it explicitely + SA_RANDOM -> the interrupt will add to the random generators entropy +*/ + +int request_irq(unsigned int irq, + irqreturn_t (*handler)(int, void *, struct pt_regs *), + unsigned long irqflags, + const char * devname, + void *dev_id) +{ + int retval; + struct irqaction * action; + + if(!handler) + return -EINVAL; + + /* allocate and fill in a handler structure and setup the irq */ + + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL); + if (!action) + return -ENOMEM; + + action->handler = handler; + action->flags = irqflags; + cpus_clear(action->mask); + action->name = devname; + action->next = NULL; + action->dev_id = dev_id; + + retval = setup_irq(irq, action); + + if (retval) + kfree(action); + return retval; +} + +EXPORT_SYMBOL(request_irq); + +void free_irq(unsigned int irq, void *dev_id) +{ + struct irqaction * action, **p; + unsigned long flags; + + if (irq >= NR_IRQS) { + printk("Trying to free IRQ%d\n",irq); + return; + } + for (p = irq - FIRST_IRQ + irq_action; (action = *p) != NULL; p = &action->next) { + if (action->dev_id != dev_id) + continue; + + /* Found it - now free it */ + local_save_flags(flags); + local_irq_disable(); + *p = action->next; + if (!irq_action[irq - FIRST_IRQ]) { + mask_irq(irq); + arch_free_irq(irq); + } + local_irq_restore(flags); + kfree(action); + return; + } + printk("Trying to free free IRQ%d\n",irq); +} + +EXPORT_SYMBOL(free_irq); + void weird_irq(void) { local_irq_disable(); @@ -112,3 +288,10 @@ void weird_irq(void) while(1); } +#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL) +/* Used by other archs to show/control IRQ steering during SMP */ +void __init +init_irq_proc(void) +{ +} +#endif diff --git a/trunk/arch/cris/kernel/module.c b/trunk/arch/cris/kernel/module.c index 11b867df8617..f1d3e784f30c 100644 --- a/trunk/arch/cris/kernel/module.c +++ b/trunk/arch/cris/kernel/module.c @@ -32,7 +32,7 @@ void *module_alloc(unsigned long size) { if (size == 0) return NULL; - return vmalloc_exec(size); + return vmalloc(size); } @@ -59,8 +59,26 @@ int apply_relocate(Elf32_Shdr *sechdrs, unsigned int relsec, struct module *me) { - printk(KERN_ERR "module %s: REL relocation unsupported\n", me->name); - return -ENOEXEC; + unsigned int i; + Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr; + Elf32_Sym *sym; + uint32_t *location; + + DEBUGP("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_offset + + rel[i].r_offset; + /* This is the symbol it is referring to. Note that all + undefined symbols have been resolved. */ + sym = (Elf32_Sym *)sechdrs[symindex].sh_addr + + ELF32_R_SYM(rel[i].r_info); + + /* We add the value into the location given */ + *location += sym->st_value; + } + return 0; } int apply_relocate_add(Elf32_Shdr *sechdrs, @@ -72,7 +90,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, unsigned int i; Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr; - DEBUGP ("Applying add relocate section %u to %u\n", relsec, + DEBUGP ("Applying relocate section %u to %u\n", relsec, sechdrs[relsec].sh_info); for (i = 0; i < sechdrs[relsec].sh_size / sizeof (*rela); i++) { @@ -85,18 +103,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, Elf32_Sym *sym = ((Elf32_Sym *)sechdrs[symindex].sh_addr + ELF32_R_SYM (rela[i].r_info)); - switch (ELF32_R_TYPE(rela[i].r_info)) { - case R_CRIS_32: - *loc = sym->st_value + rela[i].r_addend; - break; - case R_CRIS_32_PCREL: - *loc = sym->st_value - (unsigned)loc + rela[i].r_addend - 4; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rela[i].r_info)); - return -ENOEXEC; - } + *loc = sym->st_value + rela[i].r_addend; } return 0; diff --git a/trunk/arch/cris/kernel/process.c b/trunk/arch/cris/kernel/process.c index 949a0e40e03c..a5ad2b675853 100644 --- a/trunk/arch/cris/kernel/process.c +++ b/trunk/arch/cris/kernel/process.c @@ -1,4 +1,4 @@ -/* $Id: process.c,v 1.21 2005/03/04 08:16:17 starvik Exp $ +/* $Id: process.c,v 1.17 2004/04/05 13:53:48 starvik Exp $ * * linux/arch/cris/kernel/process.c * @@ -8,18 +8,6 @@ * Authors: Bjorn Wesen (bjornw@axis.com) * * $Log: process.c,v $ - * Revision 1.21 2005/03/04 08:16:17 starvik - * Merge of Linux 2.6.11. - * - * Revision 1.20 2005/01/18 05:57:22 starvik - * Renamed hlt_counter to cris_hlt_counter and made it global. - * - * Revision 1.19 2004/10/19 13:07:43 starvik - * Merge of Linux 2.6.9 - * - * Revision 1.18 2004/08/16 12:37:23 starvik - * Merge of Linux 2.6.8 - * * Revision 1.17 2004/04/05 13:53:48 starvik * Merge of Linux 2.6.5 * @@ -173,18 +161,18 @@ EXPORT_SYMBOL(init_task); * region by enable_hlt/disable_hlt. */ -int cris_hlt_counter=0; +static int hlt_counter=0; void disable_hlt(void) { - cris_hlt_counter++; + hlt_counter++; } EXPORT_SYMBOL(disable_hlt); void enable_hlt(void) { - cris_hlt_counter--; + hlt_counter--; } EXPORT_SYMBOL(enable_hlt); @@ -207,19 +195,16 @@ void cpu_idle (void) /* endless idle loop with no priority at all */ while (1) { while (!need_resched()) { - void (*idle)(void); - /* - * Mark this as an RCU critical section so that - * synchronize_kernel() in the unload path waits - * for our completion. - */ - idle = pm_idle; + void (*idle)(void) = pm_idle; + if (!idle) idle = default_idle; + idle(); } schedule(); } + } void hard_reset_now (void); diff --git a/trunk/arch/cris/kernel/profile.c b/trunk/arch/cris/kernel/profile.c deleted file mode 100644 index 69c52189f044..000000000000 --- a/trunk/arch/cris/kernel/profile.c +++ /dev/null @@ -1,73 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include - -#define SAMPLE_BUFFER_SIZE 8192 - -static char* sample_buffer; -static char* sample_buffer_pos; -static int prof_running = 0; - -void -cris_profile_sample(struct pt_regs* regs) -{ - if (!prof_running) - return; - if (user_mode(regs)) - *(unsigned int*)sample_buffer_pos = current->pid; - else - *(unsigned int*)sample_buffer_pos = 0; - *(unsigned int*)(sample_buffer_pos + 4) = instruction_pointer(regs); - sample_buffer_pos += 8; - if (sample_buffer_pos == sample_buffer + SAMPLE_BUFFER_SIZE) - sample_buffer_pos = sample_buffer; -} - -static ssize_t -read_cris_profile(struct file *file, char __user *buf, size_t count, loff_t *ppos) -{ - unsigned long p = *ppos; - if (p > SAMPLE_BUFFER_SIZE) - return 0; - if (p + count > SAMPLE_BUFFER_SIZE) - count = SAMPLE_BUFFER_SIZE - p; - if (copy_to_user(buf, sample_buffer + p,count)) - return -EFAULT; - memset(sample_buffer + p, 0, count); - *ppos += count; - return count; -} - -static ssize_t -write_cris_profile(struct file *file, const char __user *buf, - size_t count, loff_t *ppos) -{ - sample_buffer_pos = sample_buffer; - memset(sample_buffer, 0, SAMPLE_BUFFER_SIZE); -} - -static struct file_operations cris_proc_profile_operations = { - .read = read_cris_profile, - .write = write_cris_profile, -}; - -static int -__init init_cris_profile(void) -{ - struct proc_dir_entry *entry; - sample_buffer = (char*)kmalloc(SAMPLE_BUFFER_SIZE, GFP_KERNEL); - sample_buffer_pos = sample_buffer; - entry = create_proc_entry("system_profile", S_IWUSR | S_IRUGO, NULL); - if (entry) { - entry->proc_fops = &cris_proc_profile_operations; - entry->size = SAMPLE_BUFFER_SIZE; - } - prof_running = 1; - return 0; -} - -__initcall(init_cris_profile); diff --git a/trunk/arch/cris/kernel/ptrace.c b/trunk/arch/cris/kernel/ptrace.c index 2b6363cbe985..e85a2fdd9acf 100644 --- a/trunk/arch/cris/kernel/ptrace.c +++ b/trunk/arch/cris/kernel/ptrace.c @@ -8,12 +8,6 @@ * Authors: Bjorn Wesen * * $Log: ptrace.c,v $ - * Revision 1.10 2004/09/22 11:50:01 orjanf - * * Moved get_reg/put_reg to arch-specific files. - * * Added functions to access debug registers (CRISv32). - * * Added support for PTRACE_SINGLESTEP (CRISv32). - * * Added S flag to CCS_MASK (CRISv32). - * * Revision 1.9 2003/07/04 12:56:11 tobiasa * Moved arch-specific code to arch-specific files. * @@ -78,6 +72,37 @@ #include #include +/* + * Get contents of register REGNO in task TASK. + */ +inline long get_reg(struct task_struct *task, unsigned int regno) +{ + /* USP is a special case, it's not in the pt_regs struct but + * in the tasks thread struct + */ + + if (regno == PT_USP) + return task->thread.usp; + else if (regno < PT_MAX) + return ((unsigned long *)user_regs(task->thread_info))[regno]; + else + return 0; +} + +/* + * Write contents of register REGNO in task TASK. + */ +inline int put_reg(struct task_struct *task, unsigned int regno, + unsigned long data) +{ + if (regno == PT_USP) + task->thread.usp = data; + else if (regno < PT_MAX) + ((unsigned long *)user_regs(task->thread_info))[regno] = data; + else + return -1; + return 0; +} /* notification of userspace execution resumption * - triggered by current->work.notify_resume diff --git a/trunk/arch/cris/kernel/setup.c b/trunk/arch/cris/kernel/setup.c index d11206e467ab..6ec2671078bf 100644 --- a/trunk/arch/cris/kernel/setup.c +++ b/trunk/arch/cris/kernel/setup.c @@ -17,7 +17,6 @@ #include #include #include -#include #include @@ -30,7 +29,7 @@ struct screen_info screen_info; extern int root_mountflags; extern char _etext, _edata, _end; -char cris_command_line[COMMAND_LINE_SIZE] = { 0, }; +static char command_line[COMMAND_LINE_SIZE] = { 0, }; extern const unsigned long text_start, edata; /* set by the linker script */ extern unsigned long dram_start, dram_end; @@ -148,35 +147,34 @@ setup_arch(char **cmdline_p) paging_init(); - *cmdline_p = cris_command_line; + /* We don't use a command line yet, so just re-initialize it without + saving anything that might be there. */ + + *cmdline_p = command_line; #ifdef CONFIG_ETRAX_CMDLINE - if (!strcmp(cris_command_line, "")) { - strlcpy(cris_command_line, CONFIG_ETRAX_CMDLINE, COMMAND_LINE_SIZE); - cris_command_line[COMMAND_LINE_SIZE - 1] = '\0'; - } -#endif + strlcpy(command_line, CONFIG_ETRAX_CMDLINE, COMMAND_LINE_SIZE); + command_line[COMMAND_LINE_SIZE - 1] = '\0'; /* Save command line for future references. */ - memcpy(saved_command_line, cris_command_line, COMMAND_LINE_SIZE); + memcpy(saved_command_line, command_line, COMMAND_LINE_SIZE); saved_command_line[COMMAND_LINE_SIZE - 1] = '\0'; +#endif /* give credit for the CRIS port */ show_etrax_copyright(); - - /* Setup utsname */ - strcpy(system_utsname.machine, cris_machine_name); } static void *c_start(struct seq_file *m, loff_t *pos) { - return *pos < NR_CPUS ? (void *)(int)(*pos + 1): NULL; + /* We only got one CPU... */ + return *pos < 1 ? (void *)1 : NULL; } static void *c_next(struct seq_file *m, void *v, loff_t *pos) { ++*pos; - return c_start(m, pos); + return NULL; } static void c_stop(struct seq_file *m, void *v) diff --git a/trunk/arch/cris/kernel/time.c b/trunk/arch/cris/kernel/time.c index fa2d4323da25..6c28b0e7f7b4 100644 --- a/trunk/arch/cris/kernel/time.c +++ b/trunk/arch/cris/kernel/time.c @@ -1,4 +1,4 @@ -/* $Id: time.c,v 1.18 2005/03/04 08:16:17 starvik Exp $ +/* $Id: time.c,v 1.14 2004/06/01 05:38:11 starvik Exp $ * * linux/arch/cris/kernel/time.c * @@ -30,7 +30,6 @@ #include #include #include -#include u64 jiffies_64 = INITIAL_JIFFIES; @@ -215,21 +214,6 @@ update_xtime_from_cmos(void) } } -extern void cris_profile_sample(struct pt_regs* regs); - -void -cris_do_profile(struct pt_regs* regs) -{ - -#if CONFIG_SYSTEM_PROFILER - cris_profile_sample(regs); -#endif - -#if CONFIG_PROFILING - profile_tick(CPU_PROFILING, regs); -#endif -} - /* * Scheduler clock - returns current time in nanosec units. */ diff --git a/trunk/arch/cris/kernel/traps.c b/trunk/arch/cris/kernel/traps.c index 520d92205fed..d4dfa050e3a5 100644 --- a/trunk/arch/cris/kernel/traps.c +++ b/trunk/arch/cris/kernel/traps.c @@ -1,4 +1,4 @@ -/* $Id: traps.c,v 1.11 2005/01/24 16:03:19 orjanf Exp $ +/* $Id: traps.c,v 1.9 2004/05/11 12:28:26 starvik Exp $ * * linux/arch/cris/traps.c * @@ -20,15 +20,13 @@ static int kstack_depth_to_print = 24; -extern int raw_printk(const char *fmt, ...); - void show_trace(unsigned long * stack) { unsigned long addr, module_start, module_end; extern char _stext, _etext; int i; - raw_printk("\nCall Trace: "); + printk("\nCall Trace: "); i = 1; module_start = VMALLOC_START; @@ -39,7 +37,7 @@ void show_trace(unsigned long * stack) /* This message matches "failing address" marked s390 in ksymoops, so lines containing it will not be filtered out by ksymoops. */ - raw_printk ("Failing address 0x%lx\n", (unsigned long)stack); + printk ("Failing address 0x%lx\n", (unsigned long)stack); break; } stack++; @@ -56,8 +54,8 @@ void show_trace(unsigned long * stack) (addr <= (unsigned long) &_etext)) || ((addr >= module_start) && (addr <= module_end))) { if (i && ((i % 8) == 0)) - raw_printk("\n "); - raw_printk("[<%08lx>] ", addr); + printk("\n "); + printk("[<%08lx>] ", addr); i++; } } @@ -98,59 +96,25 @@ show_stack(struct task_struct *task, unsigned long *sp) stack = sp; - raw_printk("\nStack from %08lx:\n ", (unsigned long)stack); + printk("\nStack from %08lx:\n ", (unsigned long)stack); for(i = 0; i < kstack_depth_to_print; i++) { if (((long) stack & (THREAD_SIZE-1)) == 0) break; if (i && ((i % 8) == 0)) - raw_printk("\n "); + printk("\n "); if (__get_user (addr, stack)) { /* This message matches "failing address" marked s390 in ksymoops, so lines containing it will not be filtered out by ksymoops. */ - raw_printk ("Failing address 0x%lx\n", (unsigned long)stack); + printk ("Failing address 0x%lx\n", (unsigned long)stack); break; } stack++; - raw_printk("%08lx ", addr); + printk("%08lx ", addr); } show_trace(sp); } -static void (*nmi_handler)(struct pt_regs*); -extern void arch_enable_nmi(void); - -void set_nmi_handler(void (*handler)(struct pt_regs*)) -{ - nmi_handler = handler; - arch_enable_nmi(); -} - -void handle_nmi(struct pt_regs* regs) -{ - if (nmi_handler) - nmi_handler(regs); -} - -#ifdef CONFIG_DEBUG_NMI_OOPS -void oops_nmi_handler(struct pt_regs* regs) -{ - stop_watchdog(); - raw_printk("NMI!\n"); - show_registers(regs); -} - -static int -__init oops_nmi_register(void) -{ - set_nmi_handler(oops_nmi_handler); - return 0; -} - -__initcall(oops_nmi_register); - -#endif - #if 0 /* displays a short stack trace */ @@ -159,9 +123,9 @@ show_stack() { unsigned long *sp = (unsigned long *)rdusp(); int i; - raw_printk("Stack dump [0x%08lx]:\n", (unsigned long)sp); + printk("Stack dump [0x%08lx]:\n", (unsigned long)sp); for(i = 0; i < 16; i++) - raw_printk("sp + %d: 0x%08lx\n", i*4, sp[i]); + printk("sp + %d: 0x%08lx\n", i*4, sp[i]); return 0; } #endif @@ -178,9 +142,3 @@ trap_init(void) { /* Nothing needs to be done */ } - -void spinning_cpu(void* addr) -{ - raw_printk("CPU %d spinning on %X\n", smp_processor_id(), addr); - dump_stack(); -} diff --git a/trunk/arch/cris/mm/fault.c b/trunk/arch/cris/mm/fault.c index fe1cc36b5aca..03254b9eded1 100644 --- a/trunk/arch/cris/mm/fault.c +++ b/trunk/arch/cris/mm/fault.c @@ -6,38 +6,6 @@ * Authors: Bjorn Wesen * * $Log: fault.c,v $ - * Revision 1.20 2005/03/04 08:16:18 starvik - * Merge of Linux 2.6.11. - * - * Revision 1.19 2005/01/14 10:07:59 starvik - * Fixed warning. - * - * Revision 1.18 2005/01/12 08:10:14 starvik - * Readded the change of frametype when handling kernel page fault fixup - * for v10. This is necessary to avoid that the CPU remakes the faulting - * access. - * - * Revision 1.17 2005/01/11 13:53:05 starvik - * Use raw_printk. - * - * Revision 1.16 2004/12/17 11:39:41 starvik - * SMP support. - * - * Revision 1.15 2004/11/23 18:36:18 starvik - * Stack is now non-executable. - * Signal handler trampolines are placed in a reserved page mapped into all - * processes. - * - * Revision 1.14 2004/11/23 07:10:21 starvik - * Moved find_fixup_code to generic code. - * - * Revision 1.13 2004/11/23 07:00:54 starvik - * Actually use the execute permission bit in the MMU. This makes it possible - * to prevent e.g. attacks where executable code is put on the stack. - * - * Revision 1.12 2004/09/29 06:16:04 starvik - * Use instruction_pointer - * * Revision 1.11 2004/05/14 07:58:05 starvik * Merge of changes from 2.4 * @@ -135,7 +103,6 @@ extern int find_fixup_code(struct pt_regs *); extern void die_if_kernel(const char *, struct pt_regs *, long); -extern int raw_printk(const char *fmt, ...); /* debug of low-level TLB reload */ #undef DEBUG @@ -151,8 +118,7 @@ extern int raw_printk(const char *fmt, ...); /* current active page directory */ -volatile DEFINE_PER_CPU(pgd_t *,current_pgd); -unsigned long cris_signal_return_page; +volatile pgd_t *current_pgd; /* * This routine handles page faults. It determines the address, @@ -180,9 +146,8 @@ do_page_fault(unsigned long address, struct pt_regs *regs, struct vm_area_struct * vma; siginfo_t info; - D(printk("Page fault for %lX on %X at %lX, prot %d write %d\n", - address, smp_processor_id(), instruction_pointer(regs), - protection, writeaccess)); + D(printk("Page fault for %X at %X, prot %d write %d\n", + address, regs->erp, protection, writeaccess)); tsk = current; @@ -210,19 +175,8 @@ do_page_fault(unsigned long address, struct pt_regs *regs, !user_mode(regs)) goto vmalloc_fault; - /* When stack execution is not allowed we store the signal - * trampolines in the reserved cris_signal_return_page. - * Handle this in the exact same way as vmalloc (we know - * that the mapping is there and is valid so no need to - * call handle_mm_fault). - */ - if (cris_signal_return_page && - address == cris_signal_return_page && - !protection && user_mode(regs)) - goto vmalloc_fault; - /* we can and should enable interrupts at this point */ - local_irq_enable(); + sti(); mm = tsk->mm; info.si_code = SEGV_MAPERR; @@ -266,10 +220,7 @@ do_page_fault(unsigned long address, struct pt_regs *regs, /* first do some preliminary protection checks */ - if (writeaccess == 2){ - if (!(vma->vm_flags & VM_EXEC)) - goto bad_area; - } else if (writeaccess == 1) { + if (writeaccess) { if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { @@ -283,7 +234,7 @@ do_page_fault(unsigned long address, struct pt_regs *regs, * the fault. */ - switch (handle_mm_fault(mm, vma, address, writeaccess & 1)) { + switch (handle_mm_fault(mm, vma, address, writeaccess)) { case 1: tsk->min_flt++; break; @@ -341,10 +292,10 @@ do_page_fault(unsigned long address, struct pt_regs *regs, */ if ((unsigned long) (address) < PAGE_SIZE) - raw_printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference"); + printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference"); else - raw_printk(KERN_ALERT "Unable to handle kernel access"); - raw_printk(" at virtual address %08lx\n",address); + printk(KERN_ALERT "Unable to handle kernel access"); + printk(" at virtual address %08lx\n",address); die_if_kernel("Oops", regs, (writeaccess << 1) | protection); @@ -395,11 +346,10 @@ do_page_fault(unsigned long address, struct pt_regs *regs, int offset = pgd_index(address); pgd_t *pgd, *pgd_k; - pud_t *pud, *pud_k; pmd_t *pmd, *pmd_k; pte_t *pte_k; - pgd = (pgd_t *)per_cpu(current_pgd, smp_processor_id()) + offset; + pgd = (pgd_t *)current_pgd + offset; pgd_k = init_mm.pgd + offset; /* Since we're two-level, we don't need to do both @@ -414,13 +364,8 @@ do_page_fault(unsigned long address, struct pt_regs *regs, * it exists. */ - pud = pud_offset(pgd, address); - pud_k = pud_offset(pgd_k, address); - if (!pud_present(*pud_k)) - goto no_context; - - pmd = pmd_offset(pud, address); - pmd_k = pmd_offset(pud_k, address); + pmd = pmd_offset(pgd, address); + pmd_k = pmd_offset(pgd_k, address); if (!pmd_present(*pmd_k)) goto bad_area_nosemaphore; @@ -440,19 +385,3 @@ do_page_fault(unsigned long address, struct pt_regs *regs, return; } } - -/* Find fixup code. */ -int -find_fixup_code(struct pt_regs *regs) -{ - const struct exception_table_entry *fixup; - - if ((fixup = search_exception_tables(instruction_pointer(regs))) != 0) { - /* Adjust the instruction pointer in the stackframe. */ - instruction_pointer(regs) = fixup->fixup; - arch_fixup(regs); - return 1; - } - - return 0; -} diff --git a/trunk/arch/cris/mm/ioremap.c b/trunk/arch/cris/mm/ioremap.c index ebba11e270fa..6b9130bfb6c1 100644 --- a/trunk/arch/cris/mm/ioremap.c +++ b/trunk/arch/cris/mm/ioremap.c @@ -14,10 +14,9 @@ #include #include #include -#include extern inline void remap_area_pte(pte_t * pte, unsigned long address, unsigned long size, - unsigned long phys_addr, pgprot_t prot) + unsigned long phys_addr, unsigned long flags) { unsigned long end; @@ -32,7 +31,9 @@ extern inline void remap_area_pte(pte_t * pte, unsigned long address, unsigned l printk("remap_area_pte: page already exists\n"); BUG(); } - set_pte(pte, mk_pte_phys(phys_addr, prot)); + set_pte(pte, mk_pte_phys(phys_addr, __pgprot(_PAGE_PRESENT | __READABLE | + __WRITEABLE | _PAGE_GLOBAL | + _PAGE_KERNEL | flags))); address += PAGE_SIZE; phys_addr += PAGE_SIZE; pte++; @@ -40,7 +41,7 @@ extern inline void remap_area_pte(pte_t * pte, unsigned long address, unsigned l } static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size, - unsigned long phys_addr, pgprot_t prot) + unsigned long phys_addr, unsigned long flags) { unsigned long end; @@ -55,7 +56,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned lo pte_t * pte = pte_alloc_kernel(&init_mm, pmd, address); if (!pte) return -ENOMEM; - remap_area_pte(pte, address, end - address, address + phys_addr, prot); + remap_area_pte(pte, address, end - address, address + phys_addr, flags); address = (address + PMD_SIZE) & PMD_MASK; pmd++; } while (address && (address < end)); @@ -63,7 +64,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned lo } static int remap_area_pages(unsigned long address, unsigned long phys_addr, - unsigned long size, pgprot_t prot) + unsigned long size, unsigned long flags) { int error; pgd_t * dir; @@ -76,19 +77,13 @@ static int remap_area_pages(unsigned long address, unsigned long phys_addr, BUG(); spin_lock(&init_mm.page_table_lock); do { - pud_t *pud; pmd_t *pmd; - + pmd = pmd_alloc(&init_mm, dir, address); error = -ENOMEM; - pud = pud_alloc(&init_mm, dir, address); - if (!pud) - break; - pmd = pmd_alloc(&init_mm, pud, address); - if (!pmd) break; if (remap_area_pmd(pmd, address, end - address, - phys_addr + address, prot)) + phys_addr + address, flags)) break; error = 0; address = (address + PGDIR_SIZE) & PGDIR_MASK; @@ -112,9 +107,9 @@ static int remap_area_pages(unsigned long address, unsigned long phys_addr, * have to convert them into an offset in a page-aligned mapping, but the * caller shouldn't need to know that small detail. */ -void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot) +void * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags) { - void __iomem * addr; + void * addr; struct vm_struct * area; unsigned long offset, last_addr; @@ -136,36 +131,15 @@ void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgpro area = get_vm_area(size, VM_IOREMAP); if (!area) return NULL; - addr = (void __iomem *)area->addr; - if (remap_area_pages((unsigned long) addr, phys_addr, size, prot)) { - vfree((void __force *)addr); + addr = area->addr; + if (remap_area_pages((unsigned long) addr, phys_addr, size, flags)) { + vfree(addr); return NULL; } - return (void __iomem *) (offset + (char __iomem *)addr); -} - -void __iomem * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags) -{ - return __ioremap_prot(phys_addr, size, - __pgprot(_PAGE_PRESENT | __READABLE | - __WRITEABLE | _PAGE_GLOBAL | - _PAGE_KERNEL | flags)); -} - -/** - * ioremap_nocache - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - * - * Must be freed with iounmap. - */ - -void __iomem *ioremap_nocache (unsigned long phys_addr, unsigned long size) -{ - return __ioremap(phys_addr | MEM_NON_CACHEABLE, size, 0); + return (void *) (offset + (char *)addr); } -void iounmap(volatile void __iomem *addr) +void iounmap(void *addr) { if (addr > high_memory) return vfree((void *) (PAGE_MASK & (unsigned long) addr)); diff --git a/trunk/arch/cris/mm/tlb.c b/trunk/arch/cris/mm/tlb.c index 0df390a656cd..23eca5ad7389 100644 --- a/trunk/arch/cris/mm/tlb.c +++ b/trunk/arch/cris/mm/tlb.c @@ -29,6 +29,18 @@ struct mm_struct *page_id_map[NUM_PAGEID]; static int map_replace_ptr = 1; /* which page_id_map entry to replace next */ +/* + * Initialize the context related info for a new mm_struct + * instance. + */ + +int +init_new_context(struct task_struct *tsk, struct mm_struct *mm) +{ + mm->context = NO_CONTEXT; + return 0; +} + /* the following functions are similar to those used in the PPC port */ static inline void @@ -48,12 +60,12 @@ alloc_context(struct mm_struct *mm) */ flush_tlb_mm(old_mm); - old_mm->context.page_id = NO_CONTEXT; + old_mm->context = NO_CONTEXT; } /* insert it into the page_id_map */ - mm->context.page_id = map_replace_ptr; + mm->context = map_replace_ptr; page_id_map[map_replace_ptr] = mm; map_replace_ptr++; @@ -69,7 +81,7 @@ alloc_context(struct mm_struct *mm) void get_mmu_context(struct mm_struct *mm) { - if(mm->context.page_id == NO_CONTEXT) + if(mm->context == NO_CONTEXT) alloc_context(mm); } @@ -84,10 +96,11 @@ get_mmu_context(struct mm_struct *mm) void destroy_context(struct mm_struct *mm) { - if(mm->context.page_id != NO_CONTEXT) { - D(printk("destroy_context %d (%p)\n", mm->context.page_id, mm)); + if(mm->context != NO_CONTEXT) { + D(printk("destroy_context %d (%p)\n", mm->context, mm)); flush_tlb_mm(mm); /* TODO this might be redundant ? */ - page_id_map[mm->context.page_id] = NULL; + page_id_map[mm->context] = NULL; + /* mm->context = NO_CONTEXT; redundant.. mm will be freed */ } } diff --git a/trunk/arch/i386/Kconfig.debug b/trunk/arch/i386/Kconfig.debug index 5228c40a6fb2..bfb2064f7104 100644 --- a/trunk/arch/i386/Kconfig.debug +++ b/trunk/arch/i386/Kconfig.debug @@ -18,9 +18,6 @@ config EARLY_PRINTK config DEBUG_STACKOVERFLOW bool "Check for stack overflows" depends on DEBUG_KERNEL - help - This option will cause messages to be printed if free stack space - drops below a certain limit. config KPROBES bool "Kprobes" diff --git a/trunk/arch/i386/kernel/cpu/cpufreq/powernow-k8.c b/trunk/arch/i386/kernel/cpu/cpufreq/powernow-k8.c index 31f65c8a4c24..10cc096c0ade 100644 --- a/trunk/arch/i386/kernel/cpu/cpufreq/powernow-k8.c +++ b/trunk/arch/i386/kernel/cpu/cpufreq/powernow-k8.c @@ -110,13 +110,14 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data) u32 lo, hi; u32 i = 0; - do { + lo = MSR_S_LO_CHANGE_PENDING; + while (lo & MSR_S_LO_CHANGE_PENDING) { if (i++ > 0x1000000) { printk(KERN_ERR PFX "detected change pending stuck\n"); return 1; } rdmsr(MSR_FIDVID_STATUS, lo, hi); - } while (lo & MSR_S_LO_CHANGE_PENDING); + } data->currvid = hi & MSR_S_HI_CURRENT_VID; data->currfid = lo & MSR_S_LO_CURRENT_FID; diff --git a/trunk/arch/i386/kernel/process.c b/trunk/arch/i386/kernel/process.c index e3f362e8af5b..d9492058aaf3 100644 --- a/trunk/arch/i386/kernel/process.c +++ b/trunk/arch/i386/kernel/process.c @@ -917,8 +917,6 @@ asmlinkage int sys_get_thread_area(struct user_desc __user *u_info) if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX) return -EINVAL; - memset(&info, 0, sizeof(info)); - desc = current->thread.tls_array + idx - GDT_ENTRY_TLS_MIN; info.entry_number = idx; diff --git a/trunk/arch/ia64/kernel/entry.S b/trunk/arch/ia64/kernel/entry.S index 66946f3fdac7..bb9a506deb78 100644 --- a/trunk/arch/ia64/kernel/entry.S +++ b/trunk/arch/ia64/kernel/entry.S @@ -1574,8 +1574,8 @@ sys_call_table: data8 sys_ioprio_set data8 sys_ioprio_get // 1275 data8 sys_set_zone_reclaim - data8 sys_inotify_init - data8 sys_inotify_add_watch - data8 sys_inotify_rm_watch + data8 sys_ni_syscall + data8 sys_ni_syscall + data8 sys_ni_syscall .org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls diff --git a/trunk/arch/ia64/kernel/unwind.c b/trunk/arch/ia64/kernel/unwind.c index 3288be47bc75..2776a074c6f1 100644 --- a/trunk/arch/ia64/kernel/unwind.c +++ b/trunk/arch/ia64/kernel/unwind.c @@ -362,7 +362,7 @@ unw_access_gr (struct unw_frame_info *info, int regnum, unsigned long *val, char if (info->pri_unat_loc) nat_addr = info->pri_unat_loc; else - nat_addr = &info->sw->caller_unat; + nat_addr = &info->sw->ar_unat; nat_mask = (1UL << ((long) addr & 0x1f8)/8); } } else { @@ -524,7 +524,7 @@ unw_access_ar (struct unw_frame_info *info, int regnum, unsigned long *val, int case UNW_AR_UNAT: addr = info->unat_loc; if (!addr) - addr = &info->sw->caller_unat; + addr = &info->sw->ar_unat; break; case UNW_AR_LC: @@ -1775,7 +1775,7 @@ run_script (struct unw_script *script, struct unw_frame_info *state) case UNW_INSN_SETNAT_MEMSTK: if (!state->pri_unat_loc) - state->pri_unat_loc = &state->sw->caller_unat; + state->pri_unat_loc = &state->sw->ar_unat; /* register off. is a multiple of 8, so the least 3 bits (type) are 0 */ s[dst+1] = ((unsigned long) state->pri_unat_loc - s[dst]) | UNW_NAT_MEMSTK; break; @@ -2243,11 +2243,11 @@ unw_init (void) if (8*sizeof(unw_hash_index_t) < UNW_LOG_HASH_SIZE) unw_hash_index_t_is_too_narrow(); - unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(CALLER_UNAT); + unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(AR_UNAT); unw.sw_off[unw.preg_index[UNW_REG_BSPSTORE]] = SW(AR_BSPSTORE); - unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_PFS); + unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_UNAT); unw.sw_off[unw.preg_index[UNW_REG_RP]] = SW(B0); - unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(CALLER_UNAT); + unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(AR_UNAT); unw.sw_off[unw.preg_index[UNW_REG_PR]] = SW(PR); unw.sw_off[unw.preg_index[UNW_REG_LC]] = SW(AR_LC); unw.sw_off[unw.preg_index[UNW_REG_FPSR]] = SW(AR_FPSR); diff --git a/trunk/arch/m32r/Kconfig.debug b/trunk/arch/m32r/Kconfig.debug index 31039723804f..36788c2c310d 100644 --- a/trunk/arch/m32r/Kconfig.debug +++ b/trunk/arch/m32r/Kconfig.debug @@ -5,9 +5,6 @@ source "lib/Kconfig.debug" config DEBUG_STACKOVERFLOW bool "Check for stack overflows" depends on DEBUG_KERNEL - help - This option will cause messages to be printed if free stack space - drops below a certain limit. config DEBUG_STACK_USAGE bool "Stack utilization instrumentation" diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig index 898de2df1fc7..b578239146b5 100644 --- a/trunk/arch/mips/Kconfig +++ b/trunk/arch/mips/Kconfig @@ -1088,6 +1088,41 @@ config ARC32 depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32 default y +config FB + bool + depends on MIPS_MAGNUM_4000 || OLIVETTI_M700 + default y + ---help--- + The frame buffer device provides an abstraction for the graphics + hardware. It represents the frame buffer of some video hardware and + allows application software to access the graphics hardware through + a well-defined interface, so the software doesn't need to know + anything about the low-level (hardware register) stuff. + + Frame buffer devices work identically across the different + architectures supported by Linux and make the implementation of + application programs easier and more portable; at this point, an X + server exists which uses the frame buffer device exclusively. + On several non-X86 architectures, the frame buffer device is the + only way to use the graphics hardware. + + The device is accessed through special device nodes, usually located + in the /dev directory, i.e. /dev/fb*. + + You need an utility program called fbset to make full use of frame + buffer devices. Please read + and the Framebuffer-HOWTO at + for more information. + + Say Y here and to the driver for your graphics board below if you + are compiling a kernel for a non-x86 architecture. + + If you are compiling for the x86 architecture, you can say Y if you + want to play with it, but it is not essential. Please note that + running graphical applications that directly touch the hardware + (e.g. an accelerated X server) and that are not frame buffer + device-aware may cause unexpected results. If unsure, say N. + config HAVE_STD_PC_SERIAL_PORT bool diff --git a/trunk/arch/mips/kernel/irixsig.c b/trunk/arch/mips/kernel/irixsig.c index 40244782a8e5..3f956f809fa4 100644 --- a/trunk/arch/mips/kernel/irixsig.c +++ b/trunk/arch/mips/kernel/irixsig.c @@ -178,7 +178,7 @@ asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs) if (!user_mode(regs)) return 1; - if (try_to_freeze()) + if (try_to_freeze(0)) goto no_signal; if (!oldset) diff --git a/trunk/arch/mips/kernel/signal32.c b/trunk/arch/mips/kernel/signal32.c index c1a69cf232f9..1f3b19124c01 100644 --- a/trunk/arch/mips/kernel/signal32.c +++ b/trunk/arch/mips/kernel/signal32.c @@ -774,7 +774,7 @@ int do_signal32(sigset_t *oldset, struct pt_regs *regs) if (!user_mode(regs)) return 1; - if (try_to_freeze()) + if (try_to_freeze(0)) goto no_signal; if (!oldset) diff --git a/trunk/arch/mips/vr41xx/common/Makefile b/trunk/arch/mips/vr41xx/common/Makefile index fa98ef3855bc..92c11e9bbb3f 100644 --- a/trunk/arch/mips/vr41xx/common/Makefile +++ b/trunk/arch/mips/vr41xx/common/Makefile @@ -2,7 +2,7 @@ # Makefile for common code of the NEC VR4100 series. # -obj-y += bcu.o cmu.o icu.o init.o int-handler.o pmu.o +obj-y += bcu.o cmu.o giu.o icu.o init.o int-handler.o pmu.o obj-$(CONFIG_VRC4173) += vrc4173.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/trunk/arch/mips/vr41xx/common/giu.c b/trunk/arch/mips/vr41xx/common/giu.c new file mode 100644 index 000000000000..9c6b21a79e8f --- /dev/null +++ b/trunk/arch/mips/vr41xx/common/giu.c @@ -0,0 +1,455 @@ +/* + * giu.c, General-purpose I/O Unit Interrupt routines for NEC VR4100 series. + * + * Copyright (C) 2002 MontaVista Software Inc. + * Author: Yoichi Yuasa + * Copyright (C) 2003-2004 Yoichi Yuasa + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* + * Changes: + * MontaVista Software Inc. or + * - New creation, NEC VR4111, VR4121, VR4122 and VR4131 are supported. + * + * Yoichi Yuasa + * - Added support for NEC VR4133. + * - Removed board_irq_init. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define GIUIOSELL_TYPE1 KSEG1ADDR(0x0b000100) +#define GIUIOSELL_TYPE2 KSEG1ADDR(0x0f000140) + +#define GIUIOSELL 0x00 +#define GIUIOSELH 0x02 +#define GIUINTSTATL 0x08 +#define GIUINTSTATH 0x0a +#define GIUINTENL 0x0c +#define GIUINTENH 0x0e +#define GIUINTTYPL 0x10 +#define GIUINTTYPH 0x12 +#define GIUINTALSELL 0x14 +#define GIUINTALSELH 0x16 +#define GIUINTHTSELL 0x18 +#define GIUINTHTSELH 0x1a +#define GIUFEDGEINHL 0x20 +#define GIUFEDGEINHH 0x22 +#define GIUREDGEINHL 0x24 +#define GIUREDGEINHH 0x26 + +static uint32_t giu_base; + +static struct irqaction giu_cascade = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", +}; + +#define read_giuint(offset) readw(giu_base + (offset)) +#define write_giuint(val, offset) writew((val), giu_base + (offset)) + +#define GIUINT_HIGH_OFFSET 16 + +static inline uint16_t set_giuint(uint8_t offset, uint16_t set) +{ + uint16_t res; + + res = read_giuint(offset); + res |= set; + write_giuint(res, offset); + + return res; +} + +static inline uint16_t clear_giuint(uint8_t offset, uint16_t clear) +{ + uint16_t res; + + res = read_giuint(offset); + res &= ~clear; + write_giuint(res, offset); + + return res; +} + +static unsigned int startup_giuint_low_irq(unsigned int irq) +{ + unsigned int pin; + + pin = GIU_IRQ_TO_PIN(irq); + write_giuint((uint16_t)1 << pin, GIUINTSTATL); + set_giuint(GIUINTENL, (uint16_t)1 << pin); + + return 0; +} + +static void shutdown_giuint_low_irq(unsigned int irq) +{ + clear_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq)); +} + +static void enable_giuint_low_irq(unsigned int irq) +{ + set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq)); +} + +#define disable_giuint_low_irq shutdown_giuint_low_irq + +static void ack_giuint_low_irq(unsigned int irq) +{ + unsigned int pin; + + pin = GIU_IRQ_TO_PIN(irq); + clear_giuint(GIUINTENL, (uint16_t)1 << pin); + write_giuint((uint16_t)1 << pin, GIUINTSTATL); +} + +static void end_giuint_low_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq)); +} + +static struct hw_interrupt_type giuint_low_irq_type = { + .typename = "GIUINTL", + .startup = startup_giuint_low_irq, + .shutdown = shutdown_giuint_low_irq, + .enable = enable_giuint_low_irq, + .disable = disable_giuint_low_irq, + .ack = ack_giuint_low_irq, + .end = end_giuint_low_irq, +}; + +static unsigned int startup_giuint_high_irq(unsigned int irq) +{ + unsigned int pin; + + pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET); + write_giuint((uint16_t)1 << pin, GIUINTSTATH); + set_giuint(GIUINTENH, (uint16_t)1 << pin); + + return 0; +} + +static void shutdown_giuint_high_irq(unsigned int irq) +{ + clear_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET)); +} + +static void enable_giuint_high_irq(unsigned int irq) +{ + set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET)); +} + +#define disable_giuint_high_irq shutdown_giuint_high_irq + +static void ack_giuint_high_irq(unsigned int irq) +{ + unsigned int pin; + + pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET); + clear_giuint(GIUINTENH, (uint16_t)1 << pin); + write_giuint((uint16_t)1 << pin, GIUINTSTATH); +} + +static void end_giuint_high_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET)); +} + +static struct hw_interrupt_type giuint_high_irq_type = { + .typename = "GIUINTH", + .startup = startup_giuint_high_irq, + .shutdown = shutdown_giuint_high_irq, + .enable = enable_giuint_high_irq, + .disable = disable_giuint_high_irq, + .ack = ack_giuint_high_irq, + .end = end_giuint_high_irq, +}; + +void __init init_vr41xx_giuint_irq(void) +{ + int i; + + for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) { + if (i < (GIU_IRQ_BASE + GIUINT_HIGH_OFFSET)) + irq_desc[i].handler = &giuint_low_irq_type; + else + irq_desc[i].handler = &giuint_high_irq_type; + } + + setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade); +} + +void vr41xx_set_irq_trigger(int pin, int trigger, int hold) +{ + uint16_t mask; + + if (pin < GIUINT_HIGH_OFFSET) { + mask = (uint16_t)1 << pin; + if (trigger != TRIGGER_LEVEL) { + set_giuint(GIUINTTYPL, mask); + if (hold == SIGNAL_HOLD) + set_giuint(GIUINTHTSELL, mask); + else + clear_giuint(GIUINTHTSELL, mask); + if (current_cpu_data.cputype == CPU_VR4133) { + switch (trigger) { + case TRIGGER_EDGE_FALLING: + set_giuint(GIUFEDGEINHL, mask); + clear_giuint(GIUREDGEINHL, mask); + break; + case TRIGGER_EDGE_RISING: + clear_giuint(GIUFEDGEINHL, mask); + set_giuint(GIUREDGEINHL, mask); + break; + default: + set_giuint(GIUFEDGEINHL, mask); + set_giuint(GIUREDGEINHL, mask); + break; + } + } + } else { + clear_giuint(GIUINTTYPL, mask); + clear_giuint(GIUINTHTSELL, mask); + } + write_giuint(mask, GIUINTSTATL); + } else { + mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET); + if (trigger != TRIGGER_LEVEL) { + set_giuint(GIUINTTYPH, mask); + if (hold == SIGNAL_HOLD) + set_giuint(GIUINTHTSELH, mask); + else + clear_giuint(GIUINTHTSELH, mask); + if (current_cpu_data.cputype == CPU_VR4133) { + switch (trigger) { + case TRIGGER_EDGE_FALLING: + set_giuint(GIUFEDGEINHH, mask); + clear_giuint(GIUREDGEINHH, mask); + break; + case TRIGGER_EDGE_RISING: + clear_giuint(GIUFEDGEINHH, mask); + set_giuint(GIUREDGEINHH, mask); + break; + default: + set_giuint(GIUFEDGEINHH, mask); + set_giuint(GIUREDGEINHH, mask); + break; + } + } + } else { + clear_giuint(GIUINTTYPH, mask); + clear_giuint(GIUINTHTSELH, mask); + } + write_giuint(mask, GIUINTSTATH); + } +} + +EXPORT_SYMBOL(vr41xx_set_irq_trigger); + +void vr41xx_set_irq_level(int pin, int level) +{ + uint16_t mask; + + if (pin < GIUINT_HIGH_OFFSET) { + mask = (uint16_t)1 << pin; + if (level == LEVEL_HIGH) + set_giuint(GIUINTALSELL, mask); + else + clear_giuint(GIUINTALSELL, mask); + write_giuint(mask, GIUINTSTATL); + } else { + mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET); + if (level == LEVEL_HIGH) + set_giuint(GIUINTALSELH, mask); + else + clear_giuint(GIUINTALSELH, mask); + write_giuint(mask, GIUINTSTATH); + } +} + +EXPORT_SYMBOL(vr41xx_set_irq_level); + +#define GIUINT_NR_IRQS 32 + +enum { + GIUINT_NO_CASCADE, + GIUINT_CASCADE +}; + +struct vr41xx_giuint_cascade { + unsigned int flag; + int (*get_irq_number)(int irq); +}; + +static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS]; + +static int no_irq_number(int irq) +{ + return -EINVAL; +} + +int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)) +{ + unsigned int pin; + int retval; + + if (irq < GIU_IRQ(0) || irq > GIU_IRQ(31)) + return -EINVAL; + + if(!get_irq_number) + return -EINVAL; + + pin = GIU_IRQ_TO_PIN(irq); + giuint_cascade[pin].flag = GIUINT_CASCADE; + giuint_cascade[pin].get_irq_number = get_irq_number; + + retval = setup_irq(irq, &giu_cascade); + if (retval != 0) { + giuint_cascade[pin].flag = GIUINT_NO_CASCADE; + giuint_cascade[pin].get_irq_number = no_irq_number; + } + + return retval; +} + +EXPORT_SYMBOL(vr41xx_cascade_irq); + +static inline int get_irq_pin_number(void) +{ + uint16_t pendl, pendh, maskl, maskh; + int i; + + pendl = read_giuint(GIUINTSTATL); + pendh = read_giuint(GIUINTSTATH); + maskl = read_giuint(GIUINTENL); + maskh = read_giuint(GIUINTENH); + + maskl &= pendl; + maskh &= pendh; + + if (maskl) { + for (i = 0; i < 16; i++) { + if (maskl & ((uint16_t)1 << i)) + return i; + } + } else if (maskh) { + for (i = 0; i < 16; i++) { + if (maskh & ((uint16_t)1 << i)) + return i + GIUINT_HIGH_OFFSET; + } + } + + printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n", + maskl, pendl, maskh, pendh); + + atomic_inc(&irq_err_count); + + return -1; +} + +static inline void ack_giuint_irq(int pin) +{ + if (pin < GIUINT_HIGH_OFFSET) { + clear_giuint(GIUINTENL, (uint16_t)1 << pin); + write_giuint((uint16_t)1 << pin, GIUINTSTATL); + } else { + pin -= GIUINT_HIGH_OFFSET; + clear_giuint(GIUINTENH, (uint16_t)1 << pin); + write_giuint((uint16_t)1 << pin, GIUINTSTATH); + } +} + +static inline void end_giuint_irq(int pin) +{ + if (pin < GIUINT_HIGH_OFFSET) + set_giuint(GIUINTENL, (uint16_t)1 << pin); + else + set_giuint(GIUINTENH, (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET)); +} + +void giuint_irq_dispatch(struct pt_regs *regs) +{ + struct vr41xx_giuint_cascade *cascade; + unsigned int giuint_irq; + int pin; + + pin = get_irq_pin_number(); + if (pin < 0) + return; + + disable_irq(GIUINT_CASCADE_IRQ); + + cascade = &giuint_cascade[pin]; + giuint_irq = GIU_IRQ(pin); + if (cascade->flag == GIUINT_CASCADE) { + int irq = cascade->get_irq_number(giuint_irq); + ack_giuint_irq(pin); + if (irq >= 0) + do_IRQ(irq, regs); + end_giuint_irq(pin); + } else { + do_IRQ(giuint_irq, regs); + } + + enable_irq(GIUINT_CASCADE_IRQ); +} + +static int __init vr41xx_giu_init(void) +{ + int i; + + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: + giu_base = GIUIOSELL_TYPE1; + break; + case CPU_VR4122: + case CPU_VR4131: + case CPU_VR4133: + giu_base = GIUIOSELL_TYPE2; + break; + default: + printk(KERN_ERR "GIU: Unexpected CPU of NEC VR4100 series\n"); + return -EINVAL; + } + + for (i = 0; i < GIUINT_NR_IRQS; i++) { + if (i < GIUINT_HIGH_OFFSET) + clear_giuint(GIUINTENL, (uint16_t)1 << i); + else + clear_giuint(GIUINTENH, (uint16_t)1 << (i - GIUINT_HIGH_OFFSET)); + giuint_cascade[i].flag = GIUINT_NO_CASCADE; + giuint_cascade[i].get_irq_number = no_irq_number; + } + + return 0; +} + +early_initcall(vr41xx_giu_init); diff --git a/trunk/arch/parisc/kernel/pci.c b/trunk/arch/parisc/kernel/pci.c index e6a891a0cad0..3cb08a4a513a 100644 --- a/trunk/arch/parisc/kernel/pci.c +++ b/trunk/arch/parisc/kernel/pci.c @@ -255,26 +255,8 @@ void __devinit pcibios_resource_to_bus(struct pci_dev *dev, pcibios_link_hba_resources(&hba->lmmio_space, bus->resource[1]); } -void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, - struct pci_bus_region *region) -{ - struct pci_bus *bus = dev->bus; - struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data); - - if (res->flags & IORESOURCE_MEM) { - res->start = PCI_HOST_ADDR(hba, region->start); - res->end = PCI_HOST_ADDR(hba, region->end); - } - - if (res->flags & IORESOURCE_IO) { - res->start = region->start; - res->end = region->end; - } -} - #ifdef CONFIG_HOTPLUG EXPORT_SYMBOL(pcibios_resource_to_bus); -EXPORT_SYMBOL(pcibios_bus_to_resource); #endif /* diff --git a/trunk/arch/ppc/Kconfig b/trunk/arch/ppc/Kconfig index 2c2da9b43b7a..b833cbcd77f0 100644 --- a/trunk/arch/ppc/Kconfig +++ b/trunk/arch/ppc/Kconfig @@ -85,6 +85,7 @@ config POWER4 bool "POWER4 and 970 (G5)" config 8xx + depends on BROKEN bool "8xx" config E200 @@ -877,13 +878,6 @@ config MPC10X_STORE_GATHERING bool "Enable MPC10x store gathering" depends on MPC10X_BRIDGE -config SANDPOINT_ENABLE_UART1 - bool "Enable DUART mode on Sandpoint" - depends on SANDPOINT - help - If this option is enabled then the MPC824x processor will run - in DUART mode instead of UART mode. - config CPC710_DATA_GATHERING bool "Enable CPC710 data gathering" depends on K2 @@ -941,11 +935,19 @@ config NR_CPUS depends on SMP default "4" +config PREEMPT + bool "Preemptible Kernel" + help + This option reduces the latency of the kernel when reacting to + real-time or interactive events by allowing a low priority process to + be preempted even if it is in kernel mode executing a system call. + + Say Y here if you are building a kernel for a desktop, embedded + or real-time system. Say N if you are unsure. + config HIGHMEM bool "High memory support" -source kernel/Kconfig.hz -source kernel/Kconfig.preempt source "mm/Kconfig" source "fs/Kconfig.binfmt" diff --git a/trunk/arch/ppc/configs/common_defconfig b/trunk/arch/ppc/configs/common_defconfig index 4d33bee23a89..95ead3f1b1cf 100644 --- a/trunk/arch/ppc/configs/common_defconfig +++ b/trunk/arch/ppc/configs/common_defconfig @@ -1,17 +1,15 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc3 -# Wed Jul 13 13:34:24 2005 +# Linux kernel version: 2.6.10-rc2 +# Thu Nov 18 08:22:35 2004 # CONFIG_MMU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_PPC=y CONFIG_PPC32=y CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # # Code maturity level options @@ -19,7 +17,6 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -31,33 +28,30 @@ CONFIG_POSIX_MQUEUE=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y # CONFIG_EMBEDDED is not set CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SHMEM=y CONFIG_CC_ALIGN_FUNCTIONS=0 CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 # # Loadable module support # CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_OBSOLETE_MODPARM=y CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set @@ -72,27 +66,22 @@ CONFIG_6xx=y # CONFIG_POWER3 is not set # CONFIG_POWER4 is not set # CONFIG_8xx is not set -# CONFIG_E200 is not set # CONFIG_E500 is not set -CONFIG_PPC_FPU=y CONFIG_ALTIVEC=y CONFIG_TAU=y # CONFIG_TAU_INT is not set # CONFIG_TAU_AVERAGE is not set -# CONFIG_KEXEC is not set CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y # CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=m -CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_PROC_INTF=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=m -CONFIG_CPU_FREQ_GOV_ONDEMAND=m -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set CONFIG_CPU_FREQ_PMAC=y +CONFIG_CPU_FREQ_TABLE=y CONFIG_PPC601_SYNC_FIX=y CONFIG_PM=y CONFIG_PPC_STD_MMU=y @@ -102,15 +91,11 @@ CONFIG_PPC_STD_MMU=y # CONFIG_PPC_MULTIPLATFORM=y # CONFIG_APUS is not set -# CONFIG_KATANA is not set # CONFIG_WILLOW is not set -# CONFIG_CPCI690 is not set # CONFIG_PCORE is not set # CONFIG_POWERPMC250 is not set -# CONFIG_CHESTNUT is not set -# CONFIG_SPRUCE is not set -# CONFIG_HDPU is not set # CONFIG_EV64260 is not set +# CONFIG_SPRUCE is not set # CONFIG_LOPEC is not set # CONFIG_MCPN765 is not set # CONFIG_MVME5100 is not set @@ -118,7 +103,6 @@ CONFIG_PPC_MULTIPLATFORM=y # CONFIG_PRPMC750 is not set # CONFIG_PRPMC800 is not set # CONFIG_SANDPOINT is not set -# CONFIG_RADSTONE_PPC7D is not set # CONFIG_ADIR is not set # CONFIG_K2 is not set # CONFIG_PAL4 is not set @@ -129,40 +113,22 @@ CONFIG_PPC_MULTIPLATFORM=y # CONFIG_RPX8260 is not set # CONFIG_TQM8260 is not set # CONFIG_ADS8272 is not set -# CONFIG_PQ2FADS is not set # CONFIG_LITE5200 is not set -# CONFIG_MPC834x_SYS is not set CONFIG_PPC_CHRP=y CONFIG_PPC_PMAC=y CONFIG_PPC_PREP=y CONFIG_PPC_OF=y CONFIG_PPCBUG_NVRAM=y # CONFIG_SMP is not set -# CONFIG_HIGHMEM is not set -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_HIGHMEM is not set CONFIG_BINFMT_ELF=y CONFIG_BINFMT_MISC=m CONFIG_PROC_DEVICETREE=y CONFIG_PREP_RESIDUAL=y CONFIG_PROC_PREPRESIDUAL=y -# CONFIG_CMDLINE_BOOL is not set -# CONFIG_PM_DEBUG is not set -CONFIG_SOFTWARE_SUSPEND=y -CONFIG_PM_STD_PARTITION="" -# CONFIG_SECCOMP is not set -CONFIG_ISA_DMA_API=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,9600 console=tty0 root=/dev/sda2" # # Bus options @@ -171,24 +137,18 @@ CONFIG_ISA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set -# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y # # PCCARD (PCMCIA/CardBus) support # -CONFIG_PCCARD=m -# CONFIG_PCMCIA_DEBUG is not set -# CONFIG_PCMCIA is not set -CONFIG_CARDBUS=y +# CONFIG_PCCARD is not set # # PC-card bridges # -CONFIG_YENTA=m CONFIG_PCMCIA_PROBE=y -CONFIG_PCCARD_NONSTATIC=m # # Advanced setup @@ -204,143 +164,6 @@ CONFIG_KERNEL_START=0xc0000000 CONFIG_TASK_SIZE=0x80000000 CONFIG_BOOT_LOAD=0x00800000 -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -# CONFIG_IP_NF_CT_ACCT is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_CT_PROTO_SCTP is not set -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_MAC=m -CONFIG_IP_NF_MATCH_PKTTYPE=m -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_DSCP=m -CONFIG_IP_NF_MATCH_AH_ESP=m -CONFIG_IP_NF_MATCH_LENGTH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_TCPMSS=m -CONFIG_IP_NF_MATCH_HELPER=m -CONFIG_IP_NF_MATCH_STATE=m -CONFIG_IP_NF_MATCH_CONNTRACK=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_REALM=m -CONFIG_IP_NF_MATCH_SCTP=m -CONFIG_IP_NF_MATCH_COMMENT=m -CONFIG_IP_NF_MATCH_CONNMARK=m -CONFIG_IP_NF_MATCH_HASHLIMIT=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_TARGET_TCPMSS=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_IP_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_FTP=m -CONFIG_IP_NF_NAT_TFTP=m -CONFIG_IP_NF_NAT_AMANDA=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_DSCP=m -CONFIG_IP_NF_TARGET_MARK=m -CONFIG_IP_NF_TARGET_CLASSIFY=m -CONFIG_IP_NF_TARGET_CONNMARK=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_TARGET_NOTRACK=m -CONFIG_IP_NF_ARPTABLES=m -# CONFIG_IP_NF_ARPFILTER is not set -# CONFIG_IP_NF_ARP_MANGLE is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETPOLL=y -# CONFIG_NETPOLL_RX is not set -# CONFIG_NETPOLL_TRAP is not set -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set - # # Device Drivers # @@ -350,8 +173,7 @@ CONFIG_NET_POLL_CONTROLLER=y # # CONFIG_STANDALONE is not set CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -# CONFIG_DEBUG_DRIVER is not set +# CONFIG_FW_LOADER is not set # # Memory Technology Devices (MTD) @@ -361,13 +183,7 @@ CONFIG_FW_LOADER=m # # Parallel port support # -CONFIG_PARPORT=m -CONFIG_PARPORT_PC=m -CONFIG_PARPORT_SERIAL=m -CONFIG_PARPORT_PC_FIFO=y -CONFIG_PARPORT_PC_SUPERIO=y -# CONFIG_PARPORT_GSC is not set -CONFIG_PARPORT_1284=y +# CONFIG_PARPORT is not set # # Plug and Play support @@ -378,21 +194,18 @@ CONFIG_PARPORT_1284=y # Block devices # CONFIG_BLK_DEV_FD=m -CONFIG_MAC_FLOPPY=m +# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" @@ -406,7 +219,6 @@ CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set # # ATA/ATAPI/MFM/RLL support @@ -435,7 +247,7 @@ CONFIG_IDEPCI_SHARE_IRQ=y # CONFIG_BLK_DEV_OFFBOARD is not set CONFIG_BLK_DEV_GENERIC=y # CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_SL82C105 is not set +CONFIG_BLK_DEV_SL82C105=y CONFIG_BLK_DEV_IDEDMA_PCI=y # CONFIG_BLK_DEV_IDEDMA_FORCED is not set CONFIG_IDEDMA_PCI_AUTO=y @@ -452,7 +264,6 @@ CONFIG_BLK_DEV_CMD64X=y # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set CONFIG_BLK_DEV_PDC202XX_NEW=y @@ -488,21 +299,19 @@ CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # # CONFIG_SCSI_MULTI_LUN is not set CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_LOGGING is not set # # SCSI Transport Attributes # CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set # # SCSI low-level drivers @@ -531,6 +340,7 @@ CONFIG_SCSI_AIC7XXX_OLD=m # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_DTC3280 is not set # CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_GENERIC_NCR5380 is not set @@ -538,8 +348,6 @@ CONFIG_SCSI_AIC7XXX_OLD=m # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_PPA is not set -# CONFIG_SCSI_IMM is not set # CONFIG_SCSI_NCR53C406A is not set CONFIG_SCSI_SYM53C8XX_2=y CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 @@ -550,15 +358,17 @@ CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 # CONFIG_SCSI_PAS16 is not set # CONFIG_SCSI_PSI240I is not set # CONFIG_SCSI_QLOGIC_FAS is not set +# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLOGIC_1280_1040 is not set CONFIG_SCSI_QLA2XXX=y # CONFIG_SCSI_QLA21XX is not set # CONFIG_SCSI_QLA22XX is not set # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_QLA6322 is not set # CONFIG_SCSI_SYM53C416 is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set @@ -585,40 +395,11 @@ CONFIG_SCSI_MAC53C94=y # Fusion MPT device support # # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support # -CONFIG_IEEE1394=m - -# -# Subsystem Options -# -# CONFIG_IEEE1394_VERBOSEDEBUG is not set -CONFIG_IEEE1394_OUI_DB=y -CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y -CONFIG_IEEE1394_CONFIG_ROM_IP1394=y -# CONFIG_IEEE1394_EXPORT_FULL_API is not set - -# -# Device Drivers -# -# CONFIG_IEEE1394_PCILYNX is not set -CONFIG_IEEE1394_OHCI1394=m - -# -# Protocol Drivers -# -CONFIG_IEEE1394_VIDEO1394=m -CONFIG_IEEE1394_SBP2=m -# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set -CONFIG_IEEE1394_ETH1394=m -CONFIG_IEEE1394_DV1394=m -CONFIG_IEEE1394_RAWIO=m -CONFIG_IEEE1394_CMP=m -CONFIG_IEEE1394_AMDTP=m +# CONFIG_IEEE1394 is not set # # I2O device support @@ -631,8 +412,8 @@ CONFIG_IEEE1394_AMDTP=m CONFIG_ADB=y CONFIG_ADB_CUDA=y CONFIG_ADB_PMU=y +CONFIG_PMAC_PBOOK=y CONFIG_PMAC_APM_EMU=y -CONFIG_PMAC_MEDIABAY=y CONFIG_PMAC_BACKLIGHT=y CONFIG_ADB_MACIO=y CONFIG_INPUT_ADBHID=y @@ -642,13 +423,138 @@ CONFIG_THERM_ADT746X=m # CONFIG_ANSLCD is not set # -# Network device support +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_IP_TCPDIAG=y +# CONFIG_IP_TCPDIAG_IPV6 is not set + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# IP: Netfilter Configuration # +CONFIG_IP_NF_CONNTRACK=m +# CONFIG_IP_NF_CT_ACCT is not set +# CONFIG_IP_NF_CONNTRACK_MARK is not set +# CONFIG_IP_NF_CT_PROTO_SCTP is not set +CONFIG_IP_NF_FTP=m +CONFIG_IP_NF_IRC=m +CONFIG_IP_NF_TFTP=m +CONFIG_IP_NF_AMANDA=m +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_LIMIT=m +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_MAC=m +CONFIG_IP_NF_MATCH_PKTTYPE=m +CONFIG_IP_NF_MATCH_MARK=m +CONFIG_IP_NF_MATCH_MULTIPORT=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_DSCP=m +CONFIG_IP_NF_MATCH_AH_ESP=m +CONFIG_IP_NF_MATCH_LENGTH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_TCPMSS=m +CONFIG_IP_NF_MATCH_HELPER=m +CONFIG_IP_NF_MATCH_STATE=m +CONFIG_IP_NF_MATCH_CONNTRACK=m +CONFIG_IP_NF_MATCH_OWNER=m +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_REALM is not set +# CONFIG_IP_NF_MATCH_SCTP is not set +# CONFIG_IP_NF_MATCH_COMMENT is not set +# CONFIG_IP_NF_MATCH_HASHLIMIT is not set +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +# CONFIG_IP_NF_TARGET_LOG is not set +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_TARGET_TCPMSS=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_SAME=m +CONFIG_IP_NF_NAT_SNMP_BASIC=m +CONFIG_IP_NF_NAT_IRC=m +CONFIG_IP_NF_NAT_FTP=m +CONFIG_IP_NF_NAT_TFTP=m +CONFIG_IP_NF_NAT_AMANDA=m +# CONFIG_IP_NF_MANGLE is not set +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_TARGET_NOTRACK=m +# CONFIG_IP_NF_ARPTABLES is not set +CONFIG_IP_NF_COMPAT_IPCHAINS=m +# CONFIG_IP_NF_COMPAT_IPFWADM is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set -CONFIG_TUN=m +# CONFIG_TUN is not set # # ARCnet devices @@ -682,8 +588,6 @@ CONFIG_TULIP_MMIO=y CONFIG_DE4X5=m # CONFIG_WINBOND_840 is not set # CONFIG_DM9102 is not set -# CONFIG_PCMCIA_XIRCOM is not set -# CONFIG_PCMCIA_XIRTULIP is not set # CONFIG_AT1700 is not set # CONFIG_DEPCA is not set # CONFIG_HP100 is not set @@ -722,12 +626,9 @@ CONFIG_PCNET32=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set -# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_MV643XX_ETH is not set # # Ethernet (10000 Mbit) @@ -775,19 +676,18 @@ CONFIG_NET_WIRELESS=y # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set -# CONFIG_PLIP is not set CONFIG_PPP=y CONFIG_PPP_MULTILINK=y CONFIG_PPP_FILTER=y CONFIG_PPP_ASYNC=y # CONFIG_PPP_SYNC_TTY is not set CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=m -CONFIG_PPPOE=m +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPPOE is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set -CONFIG_NETCONSOLE=m +# CONFIG_NETCONSOLE is not set # # ISDN subsystem @@ -808,7 +708,7 @@ CONFIG_INPUT=y # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set @@ -816,6 +716,18 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_RAW is not set + # # Input Device Drivers # @@ -838,18 +750,6 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_PCSPKR is not set CONFIG_INPUT_UINPUT=m -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_PARKBD is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - # # Character devices # @@ -861,8 +761,7 @@ CONFIG_HW_CONSOLE=y # # Serial drivers # -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250=m CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set @@ -870,16 +769,11 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # Non-8250 serial port support # CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_PMACZILOG=y -CONFIG_SERIAL_PMACZILOG_CONSOLE=y -# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_PMACZILOG_CONSOLE is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_PRINTER is not set -# CONFIG_PPDEV is not set -# CONFIG_TIPAR is not set # # IPMI @@ -900,22 +794,10 @@ CONFIG_GEN_RTC=y # # Ftape, the floppy tape device driver # -CONFIG_AGP=m -CONFIG_AGP_UNINORTH=m -CONFIG_DRM=m -# CONFIG_DRM_TDFX is not set -CONFIG_DRM_R128=m -CONFIG_DRM_RADEON=m -# CONFIG_DRM_MGA is not set -# CONFIG_DRM_SIS is not set -# CONFIG_DRM_VIA is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - # # I2C support # @@ -941,13 +823,11 @@ CONFIG_I2C_ALGOBIT=y CONFIG_I2C_HYDRA=y # CONFIG_I2C_I801 is not set # CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_ISA is not set CONFIG_I2C_KEYWEST=m -# CONFIG_I2C_MPC is not set # CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_PROSAVAGE is not set # CONFIG_I2C_SAVAGE4 is not set # CONFIG_SCx200_ACB is not set @@ -959,20 +839,43 @@ CONFIG_I2C_KEYWEST=m # CONFIG_I2C_VIAPRO is not set # CONFIG_I2C_VOODOO3 is not set # CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_SENSOR is not set # -# Miscellaneous I2C Chip support +# Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set + +# +# Other I2C Chip support # -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_RTC8564 is not set -# CONFIG_SENSORS_M41T00 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -983,11 +886,6 @@ CONFIG_I2C_KEYWEST=m # # CONFIG_W1 is not set -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set - # # Misc devices # @@ -1006,13 +904,8 @@ CONFIG_I2C_KEYWEST=m # Graphics support # CONFIG_FB=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SOFT_CURSOR=y -CONFIG_FB_MACMODES=y CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y +# CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set @@ -1024,16 +917,13 @@ CONFIG_FB_CT65550=y # CONFIG_FB_ASILIANT is not set CONFIG_FB_IMSTT=y # CONFIG_FB_VGA16 is not set -# CONFIG_FB_NVIDIA is not set -CONFIG_FB_RIVA=y -CONFIG_FB_RIVA_I2C=y -# CONFIG_FB_RIVA_DEBUG is not set +# CONFIG_FB_RIVA is not set CONFIG_FB_MATROX=y CONFIG_FB_MATROX_MILLENIUM=y CONFIG_FB_MATROX_MYSTIQUE=y -CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_G450 is not set +# CONFIG_FB_MATROX_G100A is not set CONFIG_FB_MATROX_I2C=y -CONFIG_FB_MATROX_MAVEN=m # CONFIG_FB_MATROX_MULTIHEAD is not set # CONFIG_FB_RADEON_OLD is not set CONFIG_FB_RADEON=y @@ -1042,8 +932,8 @@ CONFIG_FB_RADEON_I2C=y CONFIG_FB_ATY128=y CONFIG_FB_ATY=y CONFIG_FB_ATY_CT=y -CONFIG_FB_ATY_GENERIC_LCD=y -CONFIG_FB_ATY_XL_INIT=y +# CONFIG_FB_ATY_GENERIC_LCD is not set +# CONFIG_FB_ATY_XL_INIT is not set CONFIG_FB_ATY_GX=y # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set @@ -1053,7 +943,6 @@ CONFIG_FB_3DFX=y # CONFIG_FB_3DFX_ACCEL is not set # CONFIG_FB_VOODOO1 is not set # CONFIG_FB_TRIDENT is not set -# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # @@ -1071,10 +960,9 @@ CONFIG_FONT_8x16=y # Logo configuration # CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -1099,7 +987,6 @@ CONFIG_SND_PCM_OSS=m CONFIG_SND_SEQUENCER_OSS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set -CONFIG_SND_GENERIC_PM=y # # Generic devices @@ -1115,7 +1002,6 @@ CONFIG_SND_OPL3_LIB=m # # ISA devices # -CONFIG_SND_CS4231_LIB=m # CONFIG_SND_AD1848 is not set # CONFIG_SND_CS4231 is not set CONFIG_SND_CS4232=m @@ -1153,8 +1039,6 @@ CONFIG_SND_CS4232=m # CONFIG_SND_CS46XX is not set # CONFIG_SND_CS4281 is not set # CONFIG_SND_EMU10K1 is not set -# CONFIG_SND_EMU10K1X is not set -# CONFIG_SND_CA0106 is not set # CONFIG_SND_KORG1212 is not set # CONFIG_SND_MIXART is not set # CONFIG_SND_NM256 is not set @@ -1162,7 +1046,6 @@ CONFIG_SND_CS4232=m # CONFIG_SND_RME96 is not set # CONFIG_SND_RME9652 is not set # CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set # CONFIG_SND_TRIDENT is not set # CONFIG_SND_YMFPCI is not set # CONFIG_SND_ALS4000 is not set @@ -1179,9 +1062,7 @@ CONFIG_SND_CS4232=m # CONFIG_SND_INTEL8X0M is not set # CONFIG_SND_SONICVIBES is not set # CONFIG_SND_VIA82XX is not set -# CONFIG_SND_VIA82XX_MODEM is not set # CONFIG_SND_VX222 is not set -# CONFIG_SND_HDA_INTEL is not set # # ALSA PowerMac devices @@ -1202,8 +1083,6 @@ CONFIG_SND_USB_AUDIO=m # # USB support # -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set @@ -1215,19 +1094,15 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_SUSPEND is not set # CONFIG_USB_OTG is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y # # USB Host Controller Drivers # -CONFIG_USB_EHCI_HCD=m -CONFIG_USB_EHCI_SPLIT_ISO=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_EHCI_HCD is not set CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_BIG_ENDIAN is not set -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_UHCI_HCD=m -# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_UHCI_HCD is not set # # USB Device Class drivers @@ -1237,20 +1112,17 @@ CONFIG_USB_UHCI_HCD=m # CONFIG_USB_MIDI is not set CONFIG_USB_ACM=m CONFIG_USB_PRINTER=m - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set -CONFIG_USB_STORAGE_DATAFAB=y +# CONFIG_USB_STORAGE_RW_DETECT is not set +# CONFIG_USB_STORAGE_DATAFAB is not set CONFIG_USB_STORAGE_FREECOM=y -CONFIG_USB_STORAGE_ISD200=y +# CONFIG_USB_STORAGE_ISD200 is not set CONFIG_USB_STORAGE_DPCM=y -CONFIG_USB_STORAGE_USBAT=y -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_HP8200e is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set # # USB Input Devices @@ -1258,24 +1130,22 @@ CONFIG_USB_STORAGE_JUMPSHOT=y CONFIG_USB_HID=y CONFIG_USB_HIDINPUT=y # CONFIG_HID_FF is not set -CONFIG_USB_HIDDEV=y +# CONFIG_USB_HIDDEV is not set # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set -# CONFIG_USB_ACECAD is not set # CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set # CONFIG_USB_MTOUCH is not set -# CONFIG_USB_ITMTOUCH is not set # CONFIG_USB_EGALAX is not set # CONFIG_USB_XPAD is not set # CONFIG_USB_ATI_REMOTE is not set -# CONFIG_USB_KEYSPAN_REMOTE is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set +# CONFIG_USB_HPUSBSCSI is not set # # USB Multimedia devices @@ -1291,27 +1161,22 @@ CONFIG_USB_HIDDEV=y # # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set -CONFIG_USB_PEGASUS=m +# CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_MON is not set # # USB port drivers # -# CONFIG_USB_USS720 is not set # # USB Serial Converter support # CONFIG_USB_SERIAL=m # CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_AIRPRIME is not set # CONFIG_USB_SERIAL_BELKIN is not set # CONFIG_USB_SERIAL_WHITEHEAT is not set # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP2101 is not set # CONFIG_USB_SERIAL_CYPRESS_M8 is not set # CONFIG_USB_SERIAL_EMPEG is not set # CONFIG_USB_SERIAL_FTDI_SIO is not set @@ -1320,32 +1185,28 @@ CONFIG_USB_SERIAL_VISOR=m # CONFIG_USB_SERIAL_IR is not set # CONFIG_USB_SERIAL_EDGEPORT is not set # CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set # CONFIG_USB_SERIAL_IPW is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y +# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set CONFIG_USB_SERIAL_KEYSPAN_USA28=y CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set CONFIG_USB_SERIAL_KEYSPAN_USA19=y CONFIG_USB_SERIAL_KEYSPAN_USA18X=y CONFIG_USB_SERIAL_KEYSPAN_USA19W=y CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y +# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set # CONFIG_USB_SERIAL_KLSI is not set # CONFIG_USB_SERIAL_KOBIL_SCT is not set # CONFIG_USB_SERIAL_MCT_U232 is not set # CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_HP4X is not set # CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set CONFIG_USB_EZUSB=y @@ -1354,6 +1215,7 @@ CONFIG_USB_EZUSB=y # # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set +# CONFIG_USB_TIGL is not set # CONFIG_USB_AUERSWALD is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set @@ -1362,13 +1224,10 @@ CONFIG_USB_EZUSB=y # CONFIG_USB_CYTHERM is not set # CONFIG_USB_PHIDGETKIT is not set # CONFIG_USB_PHIDGETSERVO is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set # CONFIG_USB_TEST is not set # -# USB DSL modem support +# USB ATM/DSL drivers # # @@ -1376,64 +1235,22 @@ CONFIG_USB_EZUSB=y # # CONFIG_USB_GADGET is not set -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# SN Devices -# - # # File systems # CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=y -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y - -# -# XFS support -# -CONFIG_XFS_FS=m -CONFIG_XFS_EXPORT=y -# CONFIG_XFS_RT is not set -# CONFIG_XFS_QUOTA is not set -CONFIG_XFS_SECURITY=y -CONFIG_XFS_POSIX_ACL=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=m +# CONFIG_AUTOFS4_FS is not set # # CD-ROM/DVD Filesystems @@ -1441,8 +1258,7 @@ CONFIG_AUTOFS4_FS=m CONFIG_ISO9660_FS=y # CONFIG_JOLIET is not set # CONFIG_ZISOFS is not set -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y +# CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems @@ -1460,11 +1276,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y +CONFIG_DEVFS_FS=y +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS_XATTR is not set CONFIG_TMPFS=y -CONFIG_TMPFS_XATTR=y -CONFIG_TMPFS_SECURITY=y +# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y @@ -1478,33 +1295,27 @@ CONFIG_HFSPLUS_FS=m # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_CRAMFS=m +# CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_FS is not set # # Network File Systems # CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y -CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y # CONFIG_NFSD_V4 is not set CONFIG_NFSD_TCP=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -1537,46 +1348,46 @@ CONFIG_MSDOS_PARTITION=y # # Native Language Support # -CONFIG_NLS=m +CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set # # Library routines @@ -1595,19 +1406,7 @@ CONFIG_ZLIB_DEFLATE=y # # Kernel hacking # -# CONFIG_PRINTK_TIME is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_XMON is not set -# CONFIG_BDI_SWITCH is not set +# CONFIG_DEBUG_KERNEL is not set CONFIG_BOOTX_TEXT=y # @@ -1620,7 +1419,3 @@ CONFIG_BOOTX_TEXT=y # Cryptographic options # # CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# diff --git a/trunk/arch/ppc/configs/pmac_defconfig b/trunk/arch/ppc/configs/pmac_defconfig index a2db8b541c9b..8eebb0455766 100644 --- a/trunk/arch/ppc/configs/pmac_defconfig +++ b/trunk/arch/ppc/configs/pmac_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc3 -# Wed Jul 13 14:13:13 2005 +# Linux kernel version: 2.6.11-rc4 +# Sun Feb 13 14:56:58 2005 # CONFIG_MMU=y CONFIG_GENERIC_HARDIRQS=y @@ -11,7 +11,6 @@ CONFIG_HAVE_DEC_LOCK=y CONFIG_PPC=y CONFIG_PPC32=y CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # # Code maturity level options @@ -19,7 +18,6 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -30,7 +28,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set +CONFIG_LOG_BUF_SHIFT=16 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y @@ -39,18 +37,15 @@ CONFIG_IKCONFIG_PROC=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SHMEM=y CONFIG_CC_ALIGN_FUNCTIONS=0 CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 # # Loadable module support @@ -72,16 +67,12 @@ CONFIG_6xx=y # CONFIG_POWER3 is not set # CONFIG_POWER4 is not set # CONFIG_8xx is not set -# CONFIG_E200 is not set # CONFIG_E500 is not set -CONFIG_PPC_FPU=y CONFIG_ALTIVEC=y CONFIG_TAU=y # CONFIG_TAU_INT is not set # CONFIG_TAU_AVERAGE is not set -# CONFIG_KEXEC is not set CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y # CONFIG_CPU_FREQ_DEBUG is not set CONFIG_CPU_FREQ_STAT=m CONFIG_CPU_FREQ_STAT_DETAILS=y @@ -91,8 +82,8 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=m CONFIG_CPU_FREQ_GOV_USERSPACE=m CONFIG_CPU_FREQ_GOV_ONDEMAND=m -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_CPU_FREQ_PMAC=y +CONFIG_CPU_FREQ_TABLE=y CONFIG_PPC601_SYNC_FIX=y CONFIG_PM=y CONFIG_PPC_STD_MMU=y @@ -109,7 +100,6 @@ CONFIG_PPC_MULTIPLATFORM=y # CONFIG_POWERPMC250 is not set # CONFIG_CHESTNUT is not set # CONFIG_SPRUCE is not set -# CONFIG_HDPU is not set # CONFIG_EV64260 is not set # CONFIG_LOPEC is not set # CONFIG_MCPN765 is not set @@ -118,7 +108,6 @@ CONFIG_PPC_MULTIPLATFORM=y # CONFIG_PRPMC750 is not set # CONFIG_PRPMC800 is not set # CONFIG_SANDPOINT is not set -# CONFIG_RADSTONE_PPC7D is not set # CONFIG_ADIR is not set # CONFIG_K2 is not set # CONFIG_PAL4 is not set @@ -131,37 +120,19 @@ CONFIG_PPC_MULTIPLATFORM=y # CONFIG_ADS8272 is not set # CONFIG_PQ2FADS is not set # CONFIG_LITE5200 is not set -# CONFIG_MPC834x_SYS is not set CONFIG_PPC_CHRP=y CONFIG_PPC_PMAC=y CONFIG_PPC_PREP=y CONFIG_PPC_OF=y CONFIG_PPCBUG_NVRAM=y # CONFIG_SMP is not set -# CONFIG_HIGHMEM is not set -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_HIGHMEM is not set CONFIG_BINFMT_ELF=y CONFIG_BINFMT_MISC=m CONFIG_PROC_DEVICETREE=y # CONFIG_PREP_RESIDUAL is not set # CONFIG_CMDLINE_BOOL is not set -# CONFIG_PM_DEBUG is not set -CONFIG_SOFTWARE_SUSPEND=y -CONFIG_PM_STD_PARTITION="" -# CONFIG_SECCOMP is not set -CONFIG_ISA_DMA_API=y # # Bus options @@ -172,7 +143,6 @@ CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_LEGACY_PROC=y CONFIG_PCI_NAMES=y -# CONFIG_PCI_DEBUG is not set # # PCCARD (PCMCIA/CardBus) support @@ -180,8 +150,6 @@ CONFIG_PCI_NAMES=y CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m -# CONFIG_PCMCIA_LOAD_CIS is not set -# CONFIG_PCMCIA_IOCTL is not set CONFIG_CARDBUS=y # @@ -206,194 +174,6 @@ CONFIG_TASK_SIZE_BOOL=y CONFIG_TASK_SIZE=0xc0000000 CONFIG_BOOT_LOAD=0x00800000 -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -CONFIG_IP_NF_CT_ACCT=y -CONFIG_IP_NF_CONNTRACK_MARK=y -CONFIG_IP_NF_CT_PROTO_SCTP=m -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_MAC=m -CONFIG_IP_NF_MATCH_PKTTYPE=m -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_DSCP=m -CONFIG_IP_NF_MATCH_AH_ESP=m -CONFIG_IP_NF_MATCH_LENGTH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_TCPMSS=m -CONFIG_IP_NF_MATCH_HELPER=m -CONFIG_IP_NF_MATCH_STATE=m -CONFIG_IP_NF_MATCH_CONNTRACK=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_REALM=m -CONFIG_IP_NF_MATCH_SCTP=m -CONFIG_IP_NF_MATCH_COMMENT=m -CONFIG_IP_NF_MATCH_CONNMARK=m -CONFIG_IP_NF_MATCH_HASHLIMIT=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_TARGET_TCPMSS=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_IP_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_FTP=m -CONFIG_IP_NF_NAT_TFTP=m -CONFIG_IP_NF_NAT_AMANDA=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_DSCP=m -CONFIG_IP_NF_TARGET_MARK=m -CONFIG_IP_NF_TARGET_CLASSIFY=m -CONFIG_IP_NF_TARGET_CONNMARK=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_TARGET_NOTRACK=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETPOLL=y -# CONFIG_NETPOLL_RX is not set -# CONFIG_NETPOLL_TRAP is not set -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_HAMRADIO is not set -CONFIG_IRDA=m - -# -# IrDA protocols -# -CONFIG_IRLAN=m -CONFIG_IRNET=m -CONFIG_IRCOMM=m -# CONFIG_IRDA_ULTRA is not set - -# -# IrDA options -# -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRDA_FAST_RR=y -# CONFIG_IRDA_DEBUG is not set - -# -# Infrared-port device drivers -# - -# -# SIR device drivers -# -CONFIG_IRTTY_SIR=m - -# -# Dongle support -# -# CONFIG_DONGLE is not set - -# -# Old SIR device drivers -# -# CONFIG_IRPORT_SIR is not set - -# -# Old Serial dongle support -# - -# -# FIR device drivers -# -# CONFIG_USB_IRDA is not set -# CONFIG_SIGMATEL_FIR is not set -# CONFIG_NSC_FIR is not set -# CONFIG_WINBOND_FIR is not set -# CONFIG_TOSHIBA_FIR is not set -# CONFIG_SMC_IRCC_FIR is not set -# CONFIG_ALI_FIR is not set -# CONFIG_VLSI_FIR is not set -# CONFIG_VIA_FIR is not set -# CONFIG_BT is not set - # # Device Drivers # @@ -403,7 +183,7 @@ CONFIG_IRTTY_SIR=m # # CONFIG_STANDALONE is not set CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m +# CONFIG_FW_LOADER is not set # CONFIG_DEBUG_DRIVER is not set # @@ -499,7 +279,6 @@ CONFIG_BLK_DEV_CMD64X=y # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set CONFIG_BLK_DEV_PDC202XX_NEW=y @@ -534,7 +313,6 @@ CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -572,6 +350,7 @@ CONFIG_SCSI_AIC7XXX_OLD=m # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set @@ -583,6 +362,7 @@ CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 # CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set # CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=y @@ -591,7 +371,6 @@ CONFIG_SCSI_QLA2XXX=y # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set @@ -619,8 +398,6 @@ CONFIG_SCSI_MAC53C94=y # Fusion MPT device support # # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support @@ -634,7 +411,6 @@ CONFIG_IEEE1394=m # CONFIG_IEEE1394_OUI_DB is not set CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y CONFIG_IEEE1394_CONFIG_ROM_IP1394=y -# CONFIG_IEEE1394_EXPORT_FULL_API is not set # # Device Drivers @@ -665,8 +441,8 @@ CONFIG_IEEE1394_AMDTP=m CONFIG_ADB=y CONFIG_ADB_CUDA=y CONFIG_ADB_PMU=y +CONFIG_PMAC_PBOOK=y CONFIG_PMAC_APM_EMU=y -CONFIG_PMAC_MEDIABAY=y CONFIG_PMAC_BACKLIGHT=y CONFIG_ADB_MACIO=y CONFIG_INPUT_ADBHID=y @@ -676,13 +452,192 @@ CONFIG_THERM_ADT746X=m # CONFIG_ANSLCD is not set # -# Network device support +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_IP_TCPDIAG=y +# CONFIG_IP_TCPDIAG_IPV6 is not set + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_CONNTRACK=m +CONFIG_IP_NF_CT_ACCT=y +CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CT_PROTO_SCTP=m +CONFIG_IP_NF_FTP=m +CONFIG_IP_NF_IRC=m +CONFIG_IP_NF_TFTP=m +CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_LIMIT=m +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_MAC=m +CONFIG_IP_NF_MATCH_PKTTYPE=m +CONFIG_IP_NF_MATCH_MARK=m +CONFIG_IP_NF_MATCH_MULTIPORT=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_DSCP=m +CONFIG_IP_NF_MATCH_AH_ESP=m +CONFIG_IP_NF_MATCH_LENGTH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_TCPMSS=m +CONFIG_IP_NF_MATCH_HELPER=m +CONFIG_IP_NF_MATCH_STATE=m +CONFIG_IP_NF_MATCH_CONNTRACK=m +CONFIG_IP_NF_MATCH_OWNER=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_REALM=m +CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_COMMENT=m +CONFIG_IP_NF_MATCH_CONNMARK=m +CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_TARGET_TCPMSS=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_SAME=m +CONFIG_IP_NF_NAT_SNMP_BASIC=m +CONFIG_IP_NF_NAT_IRC=m +CONFIG_IP_NF_NAT_FTP=m +CONFIG_IP_NF_NAT_TFTP=m +CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_DSCP=m +CONFIG_IP_NF_TARGET_MARK=m +CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_CONNMARK=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_TARGET_NOTRACK=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +CONFIG_NET_CLS_ROUTE=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRDA_FAST_RR=y +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +CONFIG_IRTTY_SIR=m + +# +# Dongle support +# +# CONFIG_DONGLE is not set + +# +# Old SIR device drivers +# +# CONFIG_IRPORT_SIR is not set + +# +# Old Serial dongle support +# + +# +# FIR device drivers # +# CONFIG_USB_IRDA is not set +# CONFIG_SIGMATEL_FIR is not set +# CONFIG_TOSHIBA_FIR is not set +# CONFIG_VLSI_FIR is not set +# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set -CONFIG_TUN=m +# CONFIG_TUN is not set # # ARCnet devices @@ -736,12 +691,9 @@ CONFIG_PCNET32=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set -# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_MV643XX_ETH is not set # # Ethernet (10000 Mbit) @@ -816,7 +768,7 @@ CONFIG_PPPOE=m # CONFIG_SLIP is not set # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set -CONFIG_NETCONSOLE=m +# CONFIG_NETCONSOLE is not set # # ISDN subsystem @@ -845,6 +797,14 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set +# CONFIG_SERIO_I8042 is not set + # # Input Device Drivers # @@ -862,12 +822,6 @@ CONFIG_INPUT_MOUSE=y # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - # # Character devices # @@ -891,7 +845,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_PMACZILOG=y CONFIG_SERIAL_PMACZILOG_CONSOLE=y -# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -923,7 +876,6 @@ CONFIG_DRM_R128=m CONFIG_DRM_RADEON=m # CONFIG_DRM_MGA is not set # CONFIG_DRM_SIS is not set -# CONFIG_DRM_VIA is not set # # PCMCIA character devices @@ -931,11 +883,6 @@ CONFIG_DRM_RADEON=m # CONFIG_SYNCLINK_CS is not set # CONFIG_RAW_DRIVER is not set -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - # # I2C support # @@ -960,12 +907,12 @@ CONFIG_I2C_ALGOBIT=y # CONFIG_I2C_HYDRA is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_ISA is not set CONFIG_I2C_KEYWEST=m # CONFIG_I2C_MPC is not set # CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_PROSAVAGE is not set # CONFIG_I2C_SAVAGE4 is not set # CONFIG_SCx200_ACB is not set @@ -977,20 +924,45 @@ CONFIG_I2C_KEYWEST=m # CONFIG_I2C_VIAPRO is not set # CONFIG_I2C_VOODOO3 is not set # CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_SENSOR is not set # -# Miscellaneous I2C Chip support +# Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set + +# +# Other I2C Chip support # -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_RTC8564 is not set -# CONFIG_SENSORS_M41T00 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -1001,11 +973,6 @@ CONFIG_I2C_KEYWEST=m # # CONFIG_W1 is not set -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set - # # Misc devices # @@ -1024,11 +991,6 @@ CONFIG_I2C_KEYWEST=m # Graphics support # CONFIG_FB=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SOFT_CURSOR=y -CONFIG_FB_MACMODES=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # CONFIG_FB_CIRRUS is not set @@ -1042,7 +1004,6 @@ CONFIG_FB_CT65550=y # CONFIG_FB_ASILIANT is not set CONFIG_FB_IMSTT=y # CONFIG_FB_VGA16 is not set -# CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set CONFIG_FB_MATROX=y CONFIG_FB_MATROX_MILLENIUM=y @@ -1068,7 +1029,6 @@ CONFIG_FB_3DFX=y CONFIG_FB_3DFX_ACCEL=y # CONFIG_FB_VOODOO1 is not set # CONFIG_FB_TRIDENT is not set -# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # @@ -1150,7 +1110,6 @@ CONFIG_SND_DUMMY=m # CONFIG_SND_RME96 is not set # CONFIG_SND_RME9652 is not set # CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set # CONFIG_SND_TRIDENT is not set # CONFIG_SND_YMFPCI is not set # CONFIG_SND_ALS4000 is not set @@ -1169,7 +1128,6 @@ CONFIG_SND_DUMMY=m # CONFIG_SND_VIA82XX is not set # CONFIG_SND_VIA82XX_MODEM is not set # CONFIG_SND_VX222 is not set -# CONFIG_SND_HDA_INTEL is not set # # ALSA PowerMac devices @@ -1194,8 +1152,6 @@ CONFIG_SND_USB_USX2Y=m # # USB support # -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set @@ -1207,15 +1163,14 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_SUSPEND=y # CONFIG_USB_OTG is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y # # USB Host Controller Drivers # # CONFIG_USB_EHCI_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_BIG_ENDIAN is not set -CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set @@ -1242,15 +1197,12 @@ CONFIG_USB_HIDINPUT=y CONFIG_USB_HIDDEV=y # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set -# CONFIG_USB_ACECAD is not set # CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set # CONFIG_USB_MTOUCH is not set -# CONFIG_USB_ITMTOUCH is not set # CONFIG_USB_EGALAX is not set # CONFIG_USB_XPAD is not set # CONFIG_USB_ATI_REMOTE is not set -# CONFIG_USB_KEYSPAN_REMOTE is not set # # USB Imaging devices @@ -1275,8 +1227,6 @@ CONFIG_USB_HIDDEV=y CONFIG_USB_PEGASUS=m # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_MON is not set # # USB port drivers @@ -1287,11 +1237,9 @@ CONFIG_USB_PEGASUS=m # CONFIG_USB_SERIAL=m # CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_AIRPRIME is not set # CONFIG_USB_SERIAL_BELKIN is not set # CONFIG_USB_SERIAL_WHITEHEAT is not set # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP2101 is not set # CONFIG_USB_SERIAL_CYPRESS_M8 is not set # CONFIG_USB_SERIAL_EMPEG is not set # CONFIG_USB_SERIAL_FTDI_SIO is not set @@ -1320,12 +1268,10 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y # CONFIG_USB_SERIAL_KOBIL_SCT is not set # CONFIG_USB_SERIAL_MCT_U232 is not set # CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_HP4X is not set # CONFIG_USB_SERIAL_SAFE is not set # CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set CONFIG_USB_EZUSB=y @@ -1343,11 +1289,10 @@ CONFIG_USB_EZUSB=y # CONFIG_USB_PHIDGETKIT is not set # CONFIG_USB_PHIDGETSERVO is not set # CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_LD is not set # CONFIG_USB_TEST is not set # -# USB DSL modem support +# USB ATM/DSL drivers # # @@ -1365,10 +1310,6 @@ CONFIG_USB_EZUSB=y # # CONFIG_INFINIBAND is not set -# -# SN Devices -# - # # File systems # @@ -1376,7 +1317,6 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y # CONFIG_EXT2_FS_POSIX_ACL is not set # CONFIG_EXT2_FS_SECURITY is not set -# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set @@ -1386,7 +1326,6 @@ CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y # # XFS support @@ -1394,7 +1333,6 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set @@ -1425,6 +1363,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y +# CONFIG_DEVFS_FS is not set CONFIG_DEVPTS_FS_XATTR=y CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y @@ -1455,20 +1394,15 @@ CONFIG_CRAMFS=m # CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y -CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y # CONFIG_NFSD_V4 is not set CONFIG_NFSD_TCP=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -1560,10 +1494,8 @@ CONFIG_ZLIB_DEFLATE=y # # Kernel hacking # -# CONFIG_PRINTK_TIME is not set CONFIG_DEBUG_KERNEL=y CONFIG_MAGIC_SYSRQ=y -CONFIG_LOG_BUF_SHIFT=16 # CONFIG_SCHEDSTATS is not set # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set diff --git a/trunk/arch/ppc/configs/radstone_ppc7d_defconfig b/trunk/arch/ppc/configs/radstone_ppc7d_defconfig index ca4d1fd0ca05..7f6467e77949 100644 --- a/trunk/arch/ppc/configs/radstone_ppc7d_defconfig +++ b/trunk/arch/ppc/configs/radstone_ppc7d_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc3 -# Tue Jul 26 00:02:09 2005 +# Linux kernel version: 2.6.11 +# Tue Mar 15 14:31:19 2005 # CONFIG_MMU=y CONFIG_GENERIC_HARDIRQS=y @@ -11,7 +11,6 @@ CONFIG_HAVE_DEC_LOCK=y CONFIG_PPC=y CONFIG_PPC32=y CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # # Code maturity level options @@ -19,7 +18,6 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -37,8 +35,6 @@ CONFIG_KOBJECT_UEVENT=y CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_PRINTK=y -CONFIG_BUG=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y @@ -71,12 +67,9 @@ CONFIG_6xx=y # CONFIG_POWER3 is not set # CONFIG_POWER4 is not set # CONFIG_8xx is not set -# CONFIG_E200 is not set # CONFIG_E500 is not set -CONFIG_PPC_FPU=y CONFIG_ALTIVEC=y # CONFIG_TAU is not set -# CONFIG_KEXEC is not set # CONFIG_CPU_FREQ is not set CONFIG_PPC_GEN550=y # CONFIG_PM is not set @@ -91,18 +84,21 @@ CONFIG_PPC_STD_MMU=y # CONFIG_KATANA is not set # CONFIG_WILLOW is not set # CONFIG_CPCI690 is not set +# CONFIG_PCORE is not set # CONFIG_POWERPMC250 is not set # CONFIG_CHESTNUT is not set # CONFIG_SPRUCE is not set -# CONFIG_HDPU is not set # CONFIG_EV64260 is not set # CONFIG_LOPEC is not set +# CONFIG_MCPN765 is not set # CONFIG_MVME5100 is not set # CONFIG_PPLUS is not set # CONFIG_PRPMC750 is not set # CONFIG_PRPMC800 is not set # CONFIG_SANDPOINT is not set CONFIG_RADSTONE_PPC7D=y +# CONFIG_ADIR is not set +# CONFIG_K2 is not set # CONFIG_PAL4 is not set # CONFIG_GEMINI is not set # CONFIG_EST8260 is not set @@ -125,18 +121,10 @@ CONFIG_MV64X60_NEW_BASE=0xfef00000 # CONFIG_SMP is not set # CONFIG_PREEMPT is not set # CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_BINFMT_ELF=y CONFIG_BINFMT_MISC=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyS0,9600" -CONFIG_SECCOMP=y -CONFIG_ISA_DMA_API=y # # Bus options @@ -166,69 +154,6 @@ CONFIG_TASK_SIZE=0x80000000 # CONFIG_BOOT_LOAD_BOOL is not set CONFIG_BOOT_LOAD=0x00800000 -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -CONFIG_BRIDGE=y -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set - # # Device Drivers # @@ -278,7 +203,6 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set @@ -286,13 +210,13 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_XIP is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers @@ -375,7 +299,6 @@ CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -408,6 +331,7 @@ CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set @@ -419,6 +343,7 @@ CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 # CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set # CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=y @@ -427,7 +352,6 @@ CONFIG_SCSI_QLA2XXX=y # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set @@ -442,8 +366,6 @@ CONFIG_SCSI_QLA2XXX=y # Fusion MPT device support # # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support @@ -460,8 +382,71 @@ CONFIG_SCSI_QLA2XXX=y # # -# Network device support +# Networking support # +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_IP_TCPDIAG=y +# CONFIG_IP_TCPDIAG_IPV6 is not set +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set @@ -526,11 +511,9 @@ CONFIG_E100=y # CONFIG_YELLOWFIN is not set CONFIG_R8169=y CONFIG_R8169_NAPI=y -# CONFIG_SKGE is not set CONFIG_SK98LIN=y # CONFIG_VIA_VELOCITY is not set CONFIG_TIGON3=y -# CONFIG_BNX2 is not set CONFIG_MV643XX_ETH=y CONFIG_MV643XX_ETH_0=y CONFIG_MV643XX_ETH_1=y @@ -563,8 +546,6 @@ CONFIG_MV643XX_ETH_1=y # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -617,6 +598,7 @@ CONFIG_SERIO_SERPORT=y CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y # # Character devices @@ -641,7 +623,6 @@ CONFIG_SERIAL_MPSC=y # CONFIG_SERIAL_MPSC_CONSOLE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -709,11 +690,11 @@ CONFIG_I2C_CHARDEV=y # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_ISA is not set # CONFIG_I2C_MPC is not set # CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_PROSAVAGE is not set # CONFIG_I2C_SAVAGE4 is not set # CONFIG_SCx200_ACB is not set @@ -726,41 +707,16 @@ CONFIG_I2C_CHARDEV=y # CONFIG_I2C_VOODOO3 is not set # CONFIG_I2C_PCA_ISA is not set CONFIG_I2C_MV64XXX=y -CONFIG_I2C_SENSOR=y # -# Miscellaneous I2C Chip support +# Hardware Sensors Chip support # -CONFIG_SENSORS_DS1337=y -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_RTC8564 is not set -# CONFIG_SENSORS_M41T00 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -CONFIG_HWMON=y +CONFIG_I2C_SENSOR=y # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_FSCHER is not set # CONFIG_SENSORS_FSCPOS is not set @@ -776,18 +732,33 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM85 is not set # CONFIG_SENSORS_LM87 is not set CONFIG_SENSORS_LM90=y -# CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Other I2C Chip support +# +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_RTC8564 is not set +# CONFIG_SENSORS_M41T00 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set # # Misc devices @@ -841,21 +812,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y # # CONFIG_INFINIBAND is not set -# -# SN Devices -# - # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set # # XFS support @@ -863,7 +828,6 @@ CONFIG_EXT2_FS=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set @@ -890,6 +854,7 @@ CONFIG_ISO9660_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y +# CONFIG_DEVFS_FS is not set # CONFIG_DEVPTS_FS_XATTR is not set CONFIG_TMPFS=y # CONFIG_TMPFS_XATTR is not set @@ -909,7 +874,8 @@ CONFIG_RAMFS=y # CONFIG_JFFS_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_NAND is not set +# CONFIG_JFFS2_FS_NOR_ECC is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_RTIME=y @@ -926,14 +892,12 @@ CONFIG_JFFS2_RTIME=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set diff --git a/trunk/arch/ppc/configs/sandpoint_defconfig b/trunk/arch/ppc/configs/sandpoint_defconfig index fb493a67c60d..0f4393a07f82 100644 --- a/trunk/arch/ppc/configs/sandpoint_defconfig +++ b/trunk/arch/ppc/configs/sandpoint_defconfig @@ -437,7 +437,7 @@ CONFIG_SOUND_GAMEPORT=y # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_NR_UARTS=2 # CONFIG_SERIAL_8250_EXTENDED is not set # diff --git a/trunk/arch/ppc/kernel/head_8xx.S b/trunk/arch/ppc/kernel/head_8xx.S index eb18cadb3755..5a7a64e91fc5 100644 --- a/trunk/arch/ppc/kernel/head_8xx.S +++ b/trunk/arch/ppc/kernel/head_8xx.S @@ -288,11 +288,13 @@ SystemCall: * For the MPC8xx, this is a software tablewalk to load the instruction * TLB. It is modelled after the example in the Motorola manual. The task * switch loads the M_TWB register with the pointer to the first level table. - * If we discover there is no second level table (value is zero) or if there - * is an invalid pte, we load that into the TLB, which causes another fault - * into the TLB Error interrupt where we can handle such problems. - * We have to use the MD_xxx registers for the tablewalk because the - * equivalent MI_xxx registers only perform the attribute functions. + * If we discover there is no second level table (the value is zero), the + * plan was to load that into the TLB, which causes another fault into the + * TLB Error interrupt where we can handle such problems. However, that did + * not work, so if we discover there is no second level table, we restore + * registers and branch to the error exception. We have to use the MD_xxx + * registers for the tablewalk because the equivalent MI_xxx registers + * only perform the attribute functions. */ InstructionTLBMiss: #ifdef CONFIG_8xx_CPU6 diff --git a/trunk/arch/ppc/mm/init.c b/trunk/arch/ppc/mm/init.c index 33ada72c7330..6164a2b34733 100644 --- a/trunk/arch/ppc/mm/init.c +++ b/trunk/arch/ppc/mm/init.c @@ -562,9 +562,6 @@ void flush_dcache_icache_page(struct page *page) #ifdef CONFIG_BOOKE __flush_dcache_icache(kmap(page)); kunmap(page); -#elif CONFIG_8xx - /* On 8xx there is no need to kmap since highmem is not supported */ - __flush_dcache_icache(page_address(page)); #else __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT); #endif diff --git a/trunk/arch/ppc/platforms/4xx/ibm440sp.c b/trunk/arch/ppc/platforms/4xx/ibm440sp.c index fa3e003a0db9..a203efb47aba 100644 --- a/trunk/arch/ppc/platforms/4xx/ibm440sp.c +++ b/trunk/arch/ppc/platforms/4xx/ibm440sp.c @@ -36,8 +36,8 @@ static struct ocp_func_emac_data ibm440sp_emac0_def = { OCP_SYSFS_EMAC_DATA() static struct ocp_func_mal_data ibm440sp_mal0_def = { - .num_tx_chans = 1, /* Number of TX channels */ - .num_rx_chans = 1, /* Number of RX channels */ + .num_tx_chans = 4, /* Number of TX channels */ + .num_rx_chans = 4, /* Number of RX channels */ .txeob_irq = 38, /* TX End Of Buffer IRQ */ .rxeob_irq = 39, /* RX End Of Buffer IRQ */ .txde_irq = 34, /* TX Descriptor Error IRQ */ diff --git a/trunk/arch/ppc/platforms/85xx/mpc8560_ads.c b/trunk/arch/ppc/platforms/85xx/mpc8560_ads.c index f2748c88665a..e18380258b68 100644 --- a/trunk/arch/ppc/platforms/85xx/mpc8560_ads.c +++ b/trunk/arch/ppc/platforms/85xx/mpc8560_ads.c @@ -56,6 +56,7 @@ #include #include +extern void cpm2_reset(void); /* ************************************************************************ * diff --git a/trunk/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/trunk/arch/ppc/platforms/85xx/mpc85xx_cds_common.c index 6267b294f704..b52c4317fefd 100644 --- a/trunk/arch/ppc/platforms/85xx/mpc85xx_cds_common.c +++ b/trunk/arch/ppc/platforms/85xx/mpc85xx_cds_common.c @@ -49,7 +49,7 @@ #include #include #include -#include +#include #include #include diff --git a/trunk/arch/ppc/platforms/85xx/stx_gp3.c b/trunk/arch/ppc/platforms/85xx/stx_gp3.c index c99b365d6110..bb41265cfc85 100644 --- a/trunk/arch/ppc/platforms/85xx/stx_gp3.c +++ b/trunk/arch/ppc/platforms/85xx/stx_gp3.c @@ -52,13 +52,14 @@ #include #include #include -#include +#include #include #include #include #include +extern void cpm2_reset(void); unsigned char __res[sizeof(bd_t)]; diff --git a/trunk/arch/ppc/platforms/pmac_setup.c b/trunk/arch/ppc/platforms/pmac_setup.c index b392b9a15987..4d324b630f4f 100644 --- a/trunk/arch/ppc/platforms/pmac_setup.c +++ b/trunk/arch/ppc/platforms/pmac_setup.c @@ -113,7 +113,7 @@ extern int pmac_newworld; extern void zs_kgdb_hook(int tty_num); static void ohare_init(void); #ifdef CONFIG_BOOTX_TEXT -static void pmac_progress(char *s, unsigned short hex); +void pmac_progress(char *s, unsigned short hex); #endif sys_ctrler_t sys_ctrler = SYS_CTRLER_UNKNOWN; @@ -123,7 +123,7 @@ extern struct smp_ops_t psurge_smp_ops; extern struct smp_ops_t core99_smp_ops; #endif /* CONFIG_SMP */ -static int __pmac +int __pmac pmac_show_cpuinfo(struct seq_file *m) { struct device_node *np; @@ -227,7 +227,7 @@ pmac_show_cpuinfo(struct seq_file *m) return 0; } -static int __openfirmware +int __openfirmware pmac_show_percpuinfo(struct seq_file *m, int i) { #ifdef CONFIG_CPU_FREQ_PMAC @@ -415,7 +415,7 @@ find_ide_boot(void) } #endif /* CONFIG_BLK_DEV_IDE && CONFIG_BLK_DEV_IDE_PMAC */ -static void __init +void __init find_boot_device(void) { #if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC) @@ -512,7 +512,7 @@ note_bootable_part(dev_t dev, int part, int goodness) } } -static void __pmac +void __pmac pmac_restart(char *cmd) { #ifdef CONFIG_ADB_CUDA @@ -537,7 +537,7 @@ pmac_restart(char *cmd) } } -static void __pmac +void __pmac pmac_power_off(void) { #ifdef CONFIG_ADB_CUDA @@ -562,7 +562,7 @@ pmac_power_off(void) } } -static void __pmac +void __pmac pmac_halt(void) { pmac_power_off(); @@ -700,7 +700,7 @@ pmac_init(unsigned long r3, unsigned long r4, unsigned long r5, } #ifdef CONFIG_BOOTX_TEXT -static void __init +void __init pmac_progress(char *s, unsigned short hex) { if (boot_text_mapped) { diff --git a/trunk/arch/ppc/platforms/prpmc750.c b/trunk/arch/ppc/platforms/prpmc750.c index 24ae1caafc61..c894e1ab5934 100644 --- a/trunk/arch/ppc/platforms/prpmc750.c +++ b/trunk/arch/ppc/platforms/prpmc750.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include diff --git a/trunk/arch/ppc/platforms/sandpoint.c b/trunk/arch/ppc/platforms/sandpoint.c index 21e31346b12b..8b149c2fc54f 100644 --- a/trunk/arch/ppc/platforms/sandpoint.c +++ b/trunk/arch/ppc/platforms/sandpoint.c @@ -311,22 +311,19 @@ sandpoint_setup_arch(void) { bd_t *bp = (bd_t *)__res; struct plat_serial8250_port *pdata; + pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_DUART); - pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0); if (pdata) { pdata[0].uartclk = bp->bi_busfreq; - } + pdata[0].membase = ioremap(pdata[0].mapbase, 0x100); -#ifdef CONFIG_SANDPOINT_ENABLE_UART1 - pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1); - if (pdata) - { - pdata[0].uartclk = bp->bi_busfreq; + /* this disables the 2nd serial port on the DUART + * since the sandpoint does not have it connected */ + pdata[1].uartclk = 0; + pdata[1].irq = 0; + pdata[1].mapbase = 0; } -#else - ppc_sys_device_remove(MPC10X_UART1); -#endif } printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n"); diff --git a/trunk/arch/ppc/platforms/tqm8260_setup.c b/trunk/arch/ppc/platforms/tqm8260_setup.c index 3409139330b1..a8880bfc034b 100644 --- a/trunk/arch/ppc/platforms/tqm8260_setup.c +++ b/trunk/arch/ppc/platforms/tqm8260_setup.c @@ -16,8 +16,8 @@ #include +#include #include -#include #include static int diff --git a/trunk/arch/ppc/syslib/cpm2_common.c b/trunk/arch/ppc/syslib/cpm2_common.c index cbac44b1620c..4c19a4ac7163 100644 --- a/trunk/arch/ppc/syslib/cpm2_common.c +++ b/trunk/arch/ppc/syslib/cpm2_common.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/ppc/syslib/m8260_setup.c b/trunk/arch/ppc/syslib/m8260_setup.c index 8f80a42dfdb7..fda75d79050c 100644 --- a/trunk/arch/ppc/syslib/m8260_setup.c +++ b/trunk/arch/ppc/syslib/m8260_setup.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include @@ -33,6 +33,7 @@ unsigned char __res[sizeof(bd_t)]; +extern void cpm2_reset(void); extern void pq2_find_bridges(void); extern void pq2pci_init_irq(void); extern void idma_pci9_init(void); diff --git a/trunk/arch/ppc/syslib/m82xx_pci.c b/trunk/arch/ppc/syslib/m82xx_pci.c index 9db58c587b46..5e7a7edcea74 100644 --- a/trunk/arch/ppc/syslib/m82xx_pci.c +++ b/trunk/arch/ppc/syslib/m82xx_pci.c @@ -238,9 +238,9 @@ pq2ads_setup_pci(struct pci_controller *hose) * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), * and local bus for PCI (SIUMCR [LBPC]). */ - immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr & - ~(SIUMCR_L2CPC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) | - SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10); + immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr & + ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) | + SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10; #endif /* Enable PCI */ immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN); diff --git a/trunk/arch/ppc/syslib/mpc10x_common.c b/trunk/arch/ppc/syslib/mpc10x_common.c index 87065e2e4c5f..8fc5f4154521 100644 --- a/trunk/arch/ppc/syslib/mpc10x_common.c +++ b/trunk/arch/ppc/syslib/mpc10x_common.c @@ -45,29 +45,24 @@ #define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS) #define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS) #define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS) -#define MPC10X_UART1_IRQ (EPIC_IRQ_BASE + 5 + NUM_8259_INTERRUPTS) #else #define MPC10X_I2C_IRQ -1 #define MPC10X_DMA0_IRQ -1 #define MPC10X_DMA1_IRQ -1 #define MPC10X_UART0_IRQ -1 -#define MPC10X_UART1_IRQ -1 #endif static struct fsl_i2c_platform_data mpc10x_i2c_pdata = { .device_flags = 0, }; -static struct plat_serial8250_port serial_plat_uart0[] = { +static struct plat_serial8250_port serial_platform_data[] = { [0] = { .mapbase = 0x4500, .iotype = UPIO_MEM, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, }, - { }, -}; -static struct plat_serial8250_port serial_plat_uart1[] = { - [0] = { + [1] = { .mapbase = 0x4600, .iotype = UPIO_MEM, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, @@ -138,17 +133,11 @@ struct platform_device ppc_sys_platform_devices[] = { }, }, }, - [MPC10X_UART0] = { + [MPC10X_DUART] = { .name = "serial8250", .id = 0, - .dev.platform_data = serial_plat_uart0, + .dev.platform_data = serial_platform_data, }, - [MPC10X_UART1] = { - .name = "serial8250", - .id = 1, - .dev.platform_data = serial_plat_uart1, - }, - }; /* We use the PCI ID to match on */ @@ -158,10 +147,10 @@ struct ppc_sys_spec ppc_sys_specs[] = { .ppc_sys_name = "8245", .mask = 0xFFFFFFFF, .value = MPC10X_BRIDGE_8245, - .num_devices = 5, + .num_devices = 4, .device_list = (enum ppc_sys_devices[]) { - MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_UART0, MPC10X_UART1, + MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_DUART, }, }, { @@ -191,25 +180,6 @@ struct ppc_sys_spec ppc_sys_specs[] = { }, }; -/* - * mach_mpc10x_fixup: This function enables DUART mode if it detects - * if it detects two UARTS in the platform device entries. - */ -static int __init mach_mpc10x_fixup(struct platform_device *pdev) -{ - if (strncmp (pdev->name, "serial8250", 10) == 0 && pdev->id == 1) - writeb(readb(serial_plat_uart1[0].membase + 0x11) | 0x1, - serial_plat_uart1[0].membase + 0x11); - return 0; -} - -static int __init mach_mpc10x_init(void) -{ - ppc_sys_device_fixup = mach_mpc10x_fixup; - return 0; -} -postcore_initcall(mach_mpc10x_init); - /* Set resources to match bridge memory map */ void __init mpc10x_bridge_set_resources(int map, struct pci_controller *hose) @@ -249,7 +219,6 @@ mpc10x_bridge_set_resources(int map, struct pci_controller *hose) ppc_md.progress("mpc10x:exit1", 0x100); } } - /* * Do some initialization and put the EUMB registers at the specified address * (also map the EPIC registers into virtual space--OpenPIC_Addr will be set). @@ -442,13 +411,11 @@ mpc10x_bridge_init(struct pci_controller *hose, ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ; ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ; - serial_plat_uart0[0].mapbase += phys_eumb_base; - serial_plat_uart0[0].irq = MPC10X_UART0_IRQ; - serial_plat_uart0[0].membase = ioremap(serial_plat_uart0[0].mapbase, 0x100); + serial_platform_data[0].mapbase += phys_eumb_base; + serial_platform_data[0].irq = MPC10X_UART0_IRQ; - serial_plat_uart1[0].mapbase += phys_eumb_base; - serial_plat_uart1[0].irq = MPC10X_UART1_IRQ; - serial_plat_uart1[0].membase = ioremap(serial_plat_uart1[0].mapbase, 0x100); + serial_platform_data[1].mapbase += phys_eumb_base; + serial_platform_data[1].irq = MPC10X_UART0_IRQ + 1; /* * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative diff --git a/trunk/arch/ppc/syslib/ppc85xx_setup.c b/trunk/arch/ppc/syslib/ppc85xx_setup.c index b7242f1bd931..ca95d79a704e 100644 --- a/trunk/arch/ppc/syslib/ppc85xx_setup.c +++ b/trunk/arch/ppc/syslib/ppc85xx_setup.c @@ -233,14 +233,14 @@ mpc85xx_setup_pci2(struct pci_controller *hose) pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff; /* Enable, Mem R/W */ pci->powar1 = 0x80044000 | - (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1); + (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1); /* Setup outboud IO windows @ MPC85XX_PCI2_IO_BASE */ pci->potar2 = 0x00000000; pci->potear2 = 0x00000000; pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff; /* Enable, IO R/W */ - pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1); + pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1); /* Setup 2G inbound Memory Window @ 0 */ pci->pitar1 = 0x00000000; diff --git a/trunk/arch/ppc64/Kconfig b/trunk/arch/ppc64/Kconfig index 2ce87836c671..fdd8afba7152 100644 --- a/trunk/arch/ppc64/Kconfig +++ b/trunk/arch/ppc64/Kconfig @@ -288,7 +288,6 @@ config SCHED_SMT overhead in some places. If unsure say N here. source "kernel/Kconfig.preempt" -source kernel/Kconfig.hz config EEH bool "PCI Extended Error Handling (EEH)" if EMBEDDED diff --git a/trunk/arch/ppc64/configs/g5_defconfig b/trunk/arch/ppc64/configs/g5_defconfig index 9e0abe8392fc..1eb33398648e 100644 --- a/trunk/arch/ppc64/configs/g5_defconfig +++ b/trunk/arch/ppc64/configs/g5_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc3 -# Wed Jul 13 14:40:34 2005 +# Linux kernel version: 2.6.12-rc6 +# Tue Jun 14 16:59:20 2005 # CONFIG_64BIT=y CONFIG_MMU=y @@ -73,15 +73,12 @@ CONFIG_SYSVIPC_COMPAT=y # CONFIG_PPC_ISERIES is not set CONFIG_PPC_MULTIPLATFORM=y # CONFIG_PPC_PSERIES is not set -# CONFIG_PPC_BPA is not set CONFIG_PPC_PMAC=y # CONFIG_PPC_MAPLE is not set CONFIG_PPC=y CONFIG_PPC64=y CONFIG_PPC_OF=y -CONFIG_MPIC=y CONFIG_ALTIVEC=y -CONFIG_KEXEC=y CONFIG_U3_DART=y CONFIG_PPC_PMAC64=y CONFIG_BOOTX_TEXT=y @@ -89,24 +86,8 @@ CONFIG_POWER4_ONLY=y CONFIG_IOMMU_VMERGE=y CONFIG_SMP=y CONFIG_NR_CPUS=2 -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_NUMA is not set # CONFIG_SCHED_SMT is not set -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_PREEMPT_BKL is not set -CONFIG_HZ_100=y -# CONFIG_HZ_250 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=100 CONFIG_GENERIC_HARDIRQS=y CONFIG_SECCOMP=y CONFIG_ISA_DMA_API=y @@ -135,144 +116,6 @@ CONFIG_PCI_NAMES=y CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=m -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -CONFIG_NET_IPIP=y -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -CONFIG_IP_NF_CT_ACCT=y -CONFIG_IP_NF_CONNTRACK_MARK=y -CONFIG_IP_NF_CT_PROTO_SCTP=m -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_MAC=m -CONFIG_IP_NF_MATCH_PKTTYPE=m -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_DSCP=m -CONFIG_IP_NF_MATCH_AH_ESP=m -CONFIG_IP_NF_MATCH_LENGTH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_TCPMSS=m -CONFIG_IP_NF_MATCH_HELPER=m -CONFIG_IP_NF_MATCH_STATE=m -CONFIG_IP_NF_MATCH_CONNTRACK=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_REALM=m -CONFIG_IP_NF_MATCH_SCTP=m -CONFIG_IP_NF_MATCH_COMMENT=m -CONFIG_IP_NF_MATCH_CONNMARK=m -CONFIG_IP_NF_MATCH_HASHLIMIT=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_TARGET_TCPMSS=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_IP_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_FTP=m -CONFIG_IP_NF_NAT_TFTP=m -CONFIG_IP_NF_NAT_AMANDA=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_DSCP=m -CONFIG_IP_NF_TARGET_MARK=m -CONFIG_IP_NF_TARGET_CLASSIFY=m -CONFIG_IP_NF_TARGET_CONNMARK=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_TARGET_NOTRACK=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set - # # Device Drivers # @@ -375,7 +218,6 @@ CONFIG_IDEDMA_PCI_AUTO=y # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set @@ -409,7 +251,6 @@ CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -497,8 +338,6 @@ CONFIG_DM_ZERO=m # Fusion MPT device support # # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support @@ -512,7 +351,6 @@ CONFIG_IEEE1394=y CONFIG_IEEE1394_OUI_DB=y CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y CONFIG_IEEE1394_CONFIG_ROM_IP1394=y -# CONFIG_IEEE1394_EXPORT_FULL_API is not set # # Device Drivers @@ -542,13 +380,149 @@ CONFIG_IEEE1394_RAWIO=y CONFIG_ADB=y CONFIG_ADB_PMU=y CONFIG_PMAC_SMU=y +# CONFIG_PMAC_PBOOK is not set # CONFIG_PMAC_BACKLIGHT is not set # CONFIG_INPUT_ADBHID is not set CONFIG_THERM_PM72=y # -# Network device support +# Networking support +# +CONFIG_NET=y + +# +# Networking options # +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_TUNNEL=y +CONFIG_IP_TCPDIAG=m +# CONFIG_IP_TCPDIAG_IPV6 is not set + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_CONNTRACK=m +CONFIG_IP_NF_CT_ACCT=y +CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CT_PROTO_SCTP=m +CONFIG_IP_NF_FTP=m +CONFIG_IP_NF_IRC=m +CONFIG_IP_NF_TFTP=m +CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_LIMIT=m +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_MAC=m +CONFIG_IP_NF_MATCH_PKTTYPE=m +CONFIG_IP_NF_MATCH_MARK=m +CONFIG_IP_NF_MATCH_MULTIPORT=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_DSCP=m +CONFIG_IP_NF_MATCH_AH_ESP=m +CONFIG_IP_NF_MATCH_LENGTH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_TCPMSS=m +CONFIG_IP_NF_MATCH_HELPER=m +CONFIG_IP_NF_MATCH_STATE=m +CONFIG_IP_NF_MATCH_CONNTRACK=m +CONFIG_IP_NF_MATCH_OWNER=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_REALM=m +CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_COMMENT=m +CONFIG_IP_NF_MATCH_CONNMARK=m +CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_TARGET_TCPMSS=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_SAME=m +CONFIG_IP_NF_NAT_SNMP_BASIC=m +CONFIG_IP_NF_NAT_IRC=m +CONFIG_IP_NF_NAT_FTP=m +CONFIG_IP_NF_NAT_TFTP=m +CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_DSCP=m +CONFIG_IP_NF_TARGET_MARK=m +CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_CONNMARK=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_TARGET_NOTRACK=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_XFRM=y +CONFIG_XFRM_USER=m + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +CONFIG_NET_CLS_ROUTE=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m @@ -588,7 +562,6 @@ CONFIG_E1000=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set -# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set CONFIG_TIGON3=m # CONFIG_BNX2 is not set @@ -777,19 +750,50 @@ CONFIG_I2C_KEYWEST=y # CONFIG_I2C_VIAPRO is not set # CONFIG_I2C_VOODOO3 is not set # CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_SENSOR is not set # -# Miscellaneous I2C Chip support +# Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set + +# +# Other I2C Chip support # # CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_RTC8564 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -800,11 +804,6 @@ CONFIG_I2C_KEYWEST=y # # CONFIG_W1 is not set -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set - # # Misc devices # @@ -912,7 +911,6 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_SPLIT_ISO is not set # CONFIG_USB_EHCI_ROOT_HUB_TT is not set -# CONFIG_USB_ISP116X_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y @@ -952,15 +950,12 @@ CONFIG_THRUSTMASTER_FF=y CONFIG_USB_HIDDEV=y # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set -# CONFIG_USB_ACECAD is not set # CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set # CONFIG_USB_MTOUCH is not set -# CONFIG_USB_ITMTOUCH is not set # CONFIG_USB_EGALAX is not set # CONFIG_USB_XPAD is not set # CONFIG_USB_ATI_REMOTE is not set -# CONFIG_USB_KEYSPAN_REMOTE is not set # # USB Imaging devices @@ -1076,11 +1071,10 @@ CONFIG_USB_EZUSB=y # CONFIG_USB_PHIDGETSERVO is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set # CONFIG_USB_TEST is not set # -# USB DSL modem support +# USB ATM/DSL drivers # # @@ -1098,10 +1092,6 @@ CONFIG_USB_EZUSB=y # # CONFIG_INFINIBAND is not set -# -# SN Devices -# - # # File systems # @@ -1109,8 +1099,6 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -1138,7 +1126,6 @@ CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m @@ -1170,6 +1157,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y +# CONFIG_DEVFS_FS is not set CONFIG_DEVPTS_FS_XATTR=y # CONFIG_DEVPTS_FS_SECURITY is not set CONFIG_TMPFS=y @@ -1201,20 +1189,15 @@ CONFIG_CRAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y -CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_TCP=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y diff --git a/trunk/arch/ppc64/configs/iSeries_defconfig b/trunk/arch/ppc64/configs/iSeries_defconfig index dbd54d188c2b..f6a2b99afd63 100644 --- a/trunk/arch/ppc64/configs/iSeries_defconfig +++ b/trunk/arch/ppc64/configs/iSeries_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc3 -# Wed Jul 13 14:43:39 2005 +# Linux kernel version: 2.6.12-rc6 +# Tue Jun 14 17:01:28 2005 # CONFIG_64BIT=y CONFIG_MMU=y @@ -80,24 +80,8 @@ CONFIG_IBMVIO=y CONFIG_IOMMU_VMERGE=y CONFIG_SMP=y CONFIG_NR_CPUS=32 -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_NUMA is not set # CONFIG_SCHED_SMT is not set -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_PREEMPT_BKL is not set -CONFIG_HZ_100=y -# CONFIG_HZ_250 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=100 CONFIG_GENERIC_HARDIRQS=y CONFIG_MSCHUNKS=y CONFIG_LPARCFG=y @@ -125,146 +109,6 @@ CONFIG_PCI_NAMES=y # # CONFIG_HOTPLUG_PCI is not set -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=m -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -CONFIG_NET_IPIP=y -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -CONFIG_IP_NF_CT_ACCT=y -CONFIG_IP_NF_CONNTRACK_MARK=y -CONFIG_IP_NF_CT_PROTO_SCTP=m -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_MAC=m -CONFIG_IP_NF_MATCH_PKTTYPE=m -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_DSCP=m -CONFIG_IP_NF_MATCH_AH_ESP=m -CONFIG_IP_NF_MATCH_LENGTH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_TCPMSS=m -CONFIG_IP_NF_MATCH_HELPER=m -CONFIG_IP_NF_MATCH_STATE=m -CONFIG_IP_NF_MATCH_CONNTRACK=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_REALM=m -CONFIG_IP_NF_MATCH_SCTP=m -CONFIG_IP_NF_MATCH_COMMENT=m -CONFIG_IP_NF_MATCH_CONNMARK=m -CONFIG_IP_NF_MATCH_HASHLIMIT=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_TARGET_TCPMSS=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_IP_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_FTP=m -CONFIG_IP_NF_NAT_TFTP=m -CONFIG_IP_NF_NAT_AMANDA=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_DSCP=m -CONFIG_IP_NF_TARGET_MARK=m -CONFIG_IP_NF_TARGET_CLASSIFY=m -CONFIG_IP_NF_TARGET_CONNMARK=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_TARGET_NOTRACK=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETPOLL=y -CONFIG_NETPOLL_RX=y -CONFIG_NETPOLL_TRAP=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set - # # Device Drivers # @@ -340,7 +184,6 @@ CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -417,8 +260,6 @@ CONFIG_DM_ZERO=m # Fusion MPT device support # # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support @@ -435,8 +276,145 @@ CONFIG_DM_ZERO=m # # -# Network device support +# Networking support +# +CONFIG_NET=y + +# +# Networking options # +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_TUNNEL=y +CONFIG_IP_TCPDIAG=m +# CONFIG_IP_TCPDIAG_IPV6 is not set + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_CONNTRACK=m +CONFIG_IP_NF_CT_ACCT=y +CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CT_PROTO_SCTP=m +CONFIG_IP_NF_FTP=m +CONFIG_IP_NF_IRC=m +CONFIG_IP_NF_TFTP=m +CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_LIMIT=m +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_MAC=m +CONFIG_IP_NF_MATCH_PKTTYPE=m +CONFIG_IP_NF_MATCH_MARK=m +CONFIG_IP_NF_MATCH_MULTIPORT=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_DSCP=m +CONFIG_IP_NF_MATCH_AH_ESP=m +CONFIG_IP_NF_MATCH_LENGTH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_TCPMSS=m +CONFIG_IP_NF_MATCH_HELPER=m +CONFIG_IP_NF_MATCH_STATE=m +CONFIG_IP_NF_MATCH_CONNTRACK=m +CONFIG_IP_NF_MATCH_OWNER=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_REALM=m +CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_COMMENT=m +CONFIG_IP_NF_MATCH_CONNMARK=m +CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_TARGET_TCPMSS=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_SAME=m +CONFIG_IP_NF_NAT_SNMP_BASIC=m +CONFIG_IP_NF_NAT_IRC=m +CONFIG_IP_NF_NAT_FTP=m +CONFIG_IP_NF_NAT_TFTP=m +CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_DSCP=m +CONFIG_IP_NF_TARGET_MARK=m +CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_CONNMARK=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_TARGET_NOTRACK=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_XFRM=y +CONFIG_XFRM_USER=m + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +CONFIG_NET_CLS_ROUTE=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_RX=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m @@ -493,7 +471,6 @@ CONFIG_E1000=m # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set -# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set @@ -633,18 +610,12 @@ CONFIG_MAX_RAW_DEVS=256 # I2C support # # CONFIG_I2C is not set -# CONFIG_I2C_SENSOR is not set # # Dallas's 1-wire bus # # CONFIG_W1 is not set -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set - # # Misc devices # @@ -691,10 +662,6 @@ CONFIG_USB_ARCH_HAS_OHCI=y # # CONFIG_INFINIBAND is not set -# -# SN Devices -# - # # File systems # @@ -702,8 +669,6 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -735,7 +700,6 @@ CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m @@ -767,6 +731,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y +# CONFIG_DEVFS_FS is not set CONFIG_DEVPTS_FS_XATTR=y CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y @@ -798,20 +763,15 @@ CONFIG_CRAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_TCP=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y diff --git a/trunk/arch/ppc64/configs/maple_defconfig b/trunk/arch/ppc64/configs/maple_defconfig index cda8e8cb6d1d..8051b0f47b6f 100644 --- a/trunk/arch/ppc64/configs/maple_defconfig +++ b/trunk/arch/ppc64/configs/maple_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc3 -# Wed Jul 13 14:46:18 2005 +# Linux kernel version: 2.6.12-rc6 +# Tue Jun 14 17:12:48 2005 # CONFIG_64BIT=y CONFIG_MMU=y @@ -73,15 +73,12 @@ CONFIG_SYSVIPC_COMPAT=y # CONFIG_PPC_ISERIES is not set CONFIG_PPC_MULTIPLATFORM=y # CONFIG_PPC_PSERIES is not set -# CONFIG_PPC_BPA is not set # CONFIG_PPC_PMAC is not set CONFIG_PPC_MAPLE=y CONFIG_PPC=y CONFIG_PPC64=y CONFIG_PPC_OF=y -CONFIG_MPIC=y # CONFIG_ALTIVEC is not set -CONFIG_KEXEC=y CONFIG_U3_DART=y CONFIG_MPIC_BROKEN_U3=y CONFIG_BOOTX_TEXT=y @@ -89,24 +86,8 @@ CONFIG_POWER4_ONLY=y CONFIG_IOMMU_VMERGE=y CONFIG_SMP=y CONFIG_NR_CPUS=2 -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_NUMA is not set # CONFIG_SCHED_SMT is not set -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_PREEMPT_BKL is not set -CONFIG_HZ_100=y -# CONFIG_HZ_250 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=100 CONFIG_GENERIC_HARDIRQS=y CONFIG_SECCOMP=y CONFIG_ISA_DMA_API=y @@ -134,71 +115,6 @@ CONFIG_PCI_NAMES=y CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set - # # Device Drivers # @@ -297,7 +213,6 @@ CONFIG_BLK_DEV_AMD74XX=y # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set @@ -325,7 +240,6 @@ CONFIG_IDEDMA_AUTO=y # # Fusion MPT device support # -# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -342,8 +256,70 @@ CONFIG_IDEDMA_AUTO=y # # -# Network device support +# Networking support +# +CONFIG_NET=y + +# +# Networking options # +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_IP_TCPDIAG=y +# CONFIG_IP_TCPDIAG_IPV6 is not set +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set @@ -400,7 +376,6 @@ CONFIG_E1000=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set -# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set @@ -568,19 +543,50 @@ CONFIG_I2C_AMD8111=y # CONFIG_I2C_VIAPRO is not set # CONFIG_I2C_VOODOO3 is not set # CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_SENSOR is not set # -# Miscellaneous I2C Chip support +# Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set + +# +# Other I2C Chip support # # CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_RTC8564 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -591,11 +597,6 @@ CONFIG_I2C_AMD8111=y # # CONFIG_W1 is not set -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set - # # Misc devices # @@ -648,7 +649,6 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_SPLIT_ISO=y CONFIG_USB_EHCI_ROOT_HUB_TT=y -# CONFIG_USB_ISP116X_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y @@ -676,15 +676,12 @@ CONFIG_USB_HIDINPUT=y # CONFIG_USB_HIDDEV is not set # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set -# CONFIG_USB_ACECAD is not set # CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set # CONFIG_USB_MTOUCH is not set -# CONFIG_USB_ITMTOUCH is not set # CONFIG_USB_EGALAX is not set # CONFIG_USB_XPAD is not set # CONFIG_USB_ATI_REMOTE is not set -# CONFIG_USB_KEYSPAN_REMOTE is not set # # USB Imaging devices @@ -775,11 +772,10 @@ CONFIG_USB_EZUSB=y # CONFIG_USB_PHIDGETSERVO is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set # CONFIG_USB_TEST is not set # -# USB DSL modem support +# USB ATM/DSL drivers # # @@ -797,24 +793,17 @@ CONFIG_USB_EZUSB=y # # CONFIG_INFINIBAND is not set -# -# SN Devices -# - # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y # # XFS support @@ -822,7 +811,6 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set @@ -850,6 +838,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y +# CONFIG_DEVFS_FS is not set CONFIG_DEVPTS_FS_XATTR=y # CONFIG_DEVPTS_FS_SECURITY is not set CONFIG_TMPFS=y @@ -881,15 +870,12 @@ CONFIG_CRAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y # CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y diff --git a/trunk/arch/ppc64/configs/pSeries_defconfig b/trunk/arch/ppc64/configs/pSeries_defconfig index 5112edf18181..d0db8b5966c0 100644 --- a/trunk/arch/ppc64/configs/pSeries_defconfig +++ b/trunk/arch/ppc64/configs/pSeries_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc3 -# Wed Jul 13 14:47:54 2005 +# Linux kernel version: 2.6.12-rc6 +# Tue Jun 14 17:13:47 2005 # CONFIG_64BIT=y CONFIG_MMU=y @@ -74,17 +74,13 @@ CONFIG_SYSVIPC_COMPAT=y # CONFIG_PPC_ISERIES is not set CONFIG_PPC_MULTIPLATFORM=y CONFIG_PPC_PSERIES=y -# CONFIG_PPC_BPA is not set # CONFIG_PPC_PMAC is not set # CONFIG_PPC_MAPLE is not set CONFIG_PPC=y CONFIG_PPC64=y CONFIG_PPC_OF=y -CONFIG_XICS=y -CONFIG_MPIC=y CONFIG_ALTIVEC=y CONFIG_PPC_SPLPAR=y -CONFIG_KEXEC=y CONFIG_IBMVIO=y # CONFIG_U3_DART is not set # CONFIG_BOOTX_TEXT is not set @@ -92,30 +88,10 @@ CONFIG_IBMVIO=y CONFIG_IOMMU_VMERGE=y CONFIG_SMP=y CONFIG_NR_CPUS=128 -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_DISCONTIGMEM_ENABLE=y -CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_DISCONTIGMEM_MANUAL=y -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_DISCONTIGMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y -CONFIG_NODES_SPAN_OTHER_NODES=y CONFIG_NUMA=y CONFIG_SCHED_SMT=y -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_PREEMPT_BKL is not set -CONFIG_HZ_100=y -# CONFIG_HZ_250 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=100 CONFIG_EEH=y CONFIG_GENERIC_HARDIRQS=y CONFIG_PPC_RTAS=y @@ -155,146 +131,6 @@ CONFIG_HOTPLUG_PCI_RPA_DLPAR=m CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=m -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -CONFIG_NET_IPIP=y -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -CONFIG_IP_NF_CT_ACCT=y -CONFIG_IP_NF_CONNTRACK_MARK=y -CONFIG_IP_NF_CT_PROTO_SCTP=m -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_MAC=m -CONFIG_IP_NF_MATCH_PKTTYPE=m -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_DSCP=m -CONFIG_IP_NF_MATCH_AH_ESP=m -CONFIG_IP_NF_MATCH_LENGTH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_TCPMSS=m -CONFIG_IP_NF_MATCH_HELPER=m -CONFIG_IP_NF_MATCH_STATE=m -CONFIG_IP_NF_MATCH_CONNTRACK=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_REALM=m -CONFIG_IP_NF_MATCH_SCTP=m -CONFIG_IP_NF_MATCH_COMMENT=m -CONFIG_IP_NF_MATCH_CONNMARK=m -CONFIG_IP_NF_MATCH_HASHLIMIT=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_TARGET_TCPMSS=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_IP_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_FTP=m -CONFIG_IP_NF_NAT_TFTP=m -CONFIG_IP_NF_NAT_AMANDA=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_DSCP=m -CONFIG_IP_NF_TARGET_MARK=m -CONFIG_IP_NF_TARGET_CLASSIFY=m -CONFIG_IP_NF_TARGET_CONNMARK=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_TARGET_NOTRACK=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETPOLL=y -CONFIG_NETPOLL_RX=y -CONFIG_NETPOLL_TRAP=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set - # # Device Drivers # @@ -402,7 +238,6 @@ CONFIG_BLK_DEV_AMD74XX=y # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set @@ -432,7 +267,6 @@ CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -518,8 +352,6 @@ CONFIG_DM_MULTIPATH_EMC=m # Fusion MPT device support # # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support @@ -536,8 +368,145 @@ CONFIG_DM_MULTIPATH_EMC=m # # -# Network device support +# Networking support +# +CONFIG_NET=y + +# +# Networking options # +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_TUNNEL=y +CONFIG_IP_TCPDIAG=m +# CONFIG_IP_TCPDIAG_IPV6 is not set + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_CONNTRACK=m +CONFIG_IP_NF_CT_ACCT=y +CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CT_PROTO_SCTP=m +CONFIG_IP_NF_FTP=m +CONFIG_IP_NF_IRC=m +CONFIG_IP_NF_TFTP=m +CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_LIMIT=m +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_MAC=m +CONFIG_IP_NF_MATCH_PKTTYPE=m +CONFIG_IP_NF_MATCH_MARK=m +CONFIG_IP_NF_MATCH_MULTIPORT=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_DSCP=m +CONFIG_IP_NF_MATCH_AH_ESP=m +CONFIG_IP_NF_MATCH_LENGTH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_TCPMSS=m +CONFIG_IP_NF_MATCH_HELPER=m +CONFIG_IP_NF_MATCH_STATE=m +CONFIG_IP_NF_MATCH_CONNTRACK=m +CONFIG_IP_NF_MATCH_OWNER=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_REALM=m +CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_COMMENT=m +CONFIG_IP_NF_MATCH_CONNMARK=m +CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_TARGET_TCPMSS=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_SAME=m +CONFIG_IP_NF_NAT_SNMP_BASIC=m +CONFIG_IP_NF_NAT_IRC=m +CONFIG_IP_NF_NAT_FTP=m +CONFIG_IP_NF_NAT_TFTP=m +CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_DSCP=m +CONFIG_IP_NF_TARGET_MARK=m +CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_CONNMARK=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_TARGET_NOTRACK=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_XFRM=y +CONFIG_XFRM_USER=m + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +CONFIG_NET_CLS_ROUTE=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_RX=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m @@ -597,7 +566,6 @@ CONFIG_E1000=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set -# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set CONFIG_TIGON3=y @@ -804,19 +772,50 @@ CONFIG_I2C_ALGOBIT=y # CONFIG_I2C_VIAPRO is not set # CONFIG_I2C_VOODOO3 is not set # CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_SENSOR is not set # -# Miscellaneous I2C Chip support +# Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set + +# +# Other I2C Chip support # # CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_RTC8564 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -827,11 +826,6 @@ CONFIG_I2C_ALGOBIT=y # # CONFIG_W1 is not set -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set - # # Misc devices # @@ -939,7 +933,6 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_SPLIT_ISO is not set # CONFIG_USB_EHCI_ROOT_HUB_TT is not set -# CONFIG_USB_ISP116X_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y @@ -976,15 +969,12 @@ CONFIG_USB_HIDINPUT=y CONFIG_USB_HIDDEV=y # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set -# CONFIG_USB_ACECAD is not set # CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set # CONFIG_USB_MTOUCH is not set -# CONFIG_USB_ITMTOUCH is not set # CONFIG_USB_EGALAX is not set # CONFIG_USB_XPAD is not set # CONFIG_USB_ATI_REMOTE is not set -# CONFIG_USB_KEYSPAN_REMOTE is not set # # USB Imaging devices @@ -1036,11 +1026,10 @@ CONFIG_USB_MON=y # CONFIG_USB_PHIDGETSERVO is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set # CONFIG_USB_TEST is not set # -# USB DSL modem support +# USB ATM/DSL drivers # # @@ -1057,16 +1046,11 @@ CONFIG_USB_MON=y # InfiniBand support # CONFIG_INFINIBAND=m -CONFIG_INFINIBAND_USER_VERBS=m CONFIG_INFINIBAND_MTHCA=m # CONFIG_INFINIBAND_MTHCA_DEBUG is not set CONFIG_INFINIBAND_IPOIB=m # CONFIG_INFINIBAND_IPOIB_DEBUG is not set -# -# SN Devices -# - # # File systems # @@ -1074,8 +1058,6 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -1107,7 +1089,6 @@ CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m @@ -1139,6 +1120,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y +# CONFIG_DEVFS_FS is not set CONFIG_DEVPTS_FS_XATTR=y CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y @@ -1170,20 +1152,15 @@ CONFIG_CRAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y -CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_TCP=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y diff --git a/trunk/arch/ppc64/defconfig b/trunk/arch/ppc64/defconfig index fbf1f427ad35..b8e2066dde77 100644 --- a/trunk/arch/ppc64/defconfig +++ b/trunk/arch/ppc64/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc3 -# Wed Jul 13 14:37:07 2005 +# Linux kernel version: 2.6.12-rc5-git9 +# Sun Jun 5 09:26:47 2005 # CONFIG_64BIT=y CONFIG_MMU=y @@ -73,18 +73,13 @@ CONFIG_SYSVIPC_COMPAT=y # CONFIG_PPC_ISERIES is not set CONFIG_PPC_MULTIPLATFORM=y CONFIG_PPC_PSERIES=y -CONFIG_PPC_BPA=y CONFIG_PPC_PMAC=y CONFIG_PPC_MAPLE=y CONFIG_PPC=y CONFIG_PPC64=y CONFIG_PPC_OF=y -CONFIG_XICS=y -CONFIG_MPIC=y -CONFIG_BPA_IIC=y CONFIG_ALTIVEC=y CONFIG_PPC_SPLPAR=y -CONFIG_KEXEC=y CONFIG_IBMVIO=y CONFIG_U3_DART=y CONFIG_MPIC_BROKEN_U3=y @@ -94,30 +89,10 @@ CONFIG_BOOTX_TEXT=y CONFIG_IOMMU_VMERGE=y CONFIG_SMP=y CONFIG_NR_CPUS=32 -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_DISCONTIGMEM_ENABLE=y -CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_DISCONTIGMEM_MANUAL=y -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_DISCONTIGMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y -CONFIG_NODES_SPAN_OTHER_NODES=y # CONFIG_NUMA is not set # CONFIG_SCHED_SMT is not set -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_PREEMPT_BKL is not set -CONFIG_HZ_100=y -# CONFIG_HZ_250 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=100 CONFIG_EEH=y CONFIG_GENERIC_HARDIRQS=y CONFIG_PPC_RTAS=y @@ -157,146 +132,6 @@ CONFIG_HOTPLUG_PCI_RPA_DLPAR=m CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=m -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -CONFIG_NET_IPIP=y -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_TUNNEL=y -# CONFIG_IP_TCPDIAG is not set -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -CONFIG_IP_NF_CT_ACCT=y -CONFIG_IP_NF_CONNTRACK_MARK=y -CONFIG_IP_NF_CT_PROTO_SCTP=m -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_MAC=m -CONFIG_IP_NF_MATCH_PKTTYPE=m -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_DSCP=m -CONFIG_IP_NF_MATCH_AH_ESP=m -CONFIG_IP_NF_MATCH_LENGTH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_TCPMSS=m -CONFIG_IP_NF_MATCH_HELPER=m -CONFIG_IP_NF_MATCH_STATE=m -CONFIG_IP_NF_MATCH_CONNTRACK=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_REALM=m -CONFIG_IP_NF_MATCH_SCTP=m -CONFIG_IP_NF_MATCH_COMMENT=m -CONFIG_IP_NF_MATCH_CONNMARK=m -CONFIG_IP_NF_MATCH_HASHLIMIT=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_TARGET_TCPMSS=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_IP_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_FTP=m -CONFIG_IP_NF_NAT_TFTP=m -CONFIG_IP_NF_NAT_AMANDA=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_DSCP=m -CONFIG_IP_NF_TARGET_MARK=m -CONFIG_IP_NF_TARGET_CLASSIFY=m -CONFIG_IP_NF_TARGET_CONNMARK=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_TARGET_NOTRACK=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETPOLL=y -CONFIG_NETPOLL_RX=y -CONFIG_NETPOLL_TRAP=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set - # # Device Drivers # @@ -404,7 +239,6 @@ CONFIG_BLK_DEV_AMD74XX=y # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set @@ -438,7 +272,6 @@ CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs @@ -536,8 +369,6 @@ CONFIG_DM_MULTIPATH_EMC=m # Fusion MPT device support # # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set # # IEEE 1394 (FireWire) support @@ -551,7 +382,6 @@ CONFIG_IEEE1394=y # CONFIG_IEEE1394_OUI_DB is not set CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y CONFIG_IEEE1394_CONFIG_ROM_IP1394=y -# CONFIG_IEEE1394_EXPORT_FULL_API is not set # # Device Drivers @@ -582,13 +412,151 @@ CONFIG_IEEE1394_AMDTP=m CONFIG_ADB=y CONFIG_ADB_PMU=y CONFIG_PMAC_SMU=y +# CONFIG_PMAC_PBOOK is not set # CONFIG_PMAC_BACKLIGHT is not set # CONFIG_INPUT_ADBHID is not set CONFIG_THERM_PM72=y # -# Network device support +# Networking support +# +CONFIG_NET=y + +# +# Networking options # +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_TUNNEL=y +# CONFIG_IP_TCPDIAG is not set +# CONFIG_IP_TCPDIAG_IPV6 is not set + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_CONNTRACK=m +CONFIG_IP_NF_CT_ACCT=y +CONFIG_IP_NF_CONNTRACK_MARK=y +CONFIG_IP_NF_CT_PROTO_SCTP=m +CONFIG_IP_NF_FTP=m +CONFIG_IP_NF_IRC=m +CONFIG_IP_NF_TFTP=m +CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_LIMIT=m +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_MAC=m +CONFIG_IP_NF_MATCH_PKTTYPE=m +CONFIG_IP_NF_MATCH_MARK=m +CONFIG_IP_NF_MATCH_MULTIPORT=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_DSCP=m +CONFIG_IP_NF_MATCH_AH_ESP=m +CONFIG_IP_NF_MATCH_LENGTH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_TCPMSS=m +CONFIG_IP_NF_MATCH_HELPER=m +CONFIG_IP_NF_MATCH_STATE=m +CONFIG_IP_NF_MATCH_CONNTRACK=m +CONFIG_IP_NF_MATCH_OWNER=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_REALM=m +CONFIG_IP_NF_MATCH_SCTP=m +CONFIG_IP_NF_MATCH_COMMENT=m +CONFIG_IP_NF_MATCH_CONNMARK=m +CONFIG_IP_NF_MATCH_HASHLIMIT=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_TARGET_TCPMSS=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_SAME=m +CONFIG_IP_NF_NAT_SNMP_BASIC=m +CONFIG_IP_NF_NAT_IRC=m +CONFIG_IP_NF_NAT_FTP=m +CONFIG_IP_NF_NAT_TFTP=m +CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_DSCP=m +CONFIG_IP_NF_TARGET_MARK=m +CONFIG_IP_NF_TARGET_CLASSIFY=m +CONFIG_IP_NF_TARGET_CONNMARK=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_TARGET_NOTRACK=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_XFRM=y +CONFIG_XFRM_USER=m + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +CONFIG_NET_CLS_ROUTE=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_RX=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_BONDING=m @@ -648,7 +616,6 @@ CONFIG_E1000=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set -# CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set CONFIG_TIGON3=y @@ -856,19 +823,50 @@ CONFIG_I2C_KEYWEST=y # CONFIG_I2C_VIAPRO is not set # CONFIG_I2C_VOODOO3 is not set # CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_SENSOR is not set # -# Miscellaneous I2C Chip support +# Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set + +# +# Other I2C Chip support # # CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_RTC8564 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -879,11 +877,6 @@ CONFIG_I2C_KEYWEST=y # # CONFIG_W1 is not set -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set - # # Misc devices # @@ -995,7 +988,6 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_SPLIT_ISO is not set # CONFIG_USB_EHCI_ROOT_HUB_TT is not set -# CONFIG_USB_ISP116X_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y @@ -1032,15 +1024,12 @@ CONFIG_USB_HIDINPUT=y CONFIG_USB_HIDDEV=y # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set -# CONFIG_USB_ACECAD is not set # CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set # CONFIG_USB_MTOUCH is not set -# CONFIG_USB_ITMTOUCH is not set # CONFIG_USB_EGALAX is not set # CONFIG_USB_XPAD is not set # CONFIG_USB_ATI_REMOTE is not set -# CONFIG_USB_KEYSPAN_REMOTE is not set # # USB Imaging devices @@ -1092,11 +1081,10 @@ CONFIG_USB_PEGASUS=y # CONFIG_USB_PHIDGETSERVO is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set # CONFIG_USB_TEST is not set # -# USB DSL modem support +# USB ATM/DSL drivers # # @@ -1113,16 +1101,11 @@ CONFIG_USB_PEGASUS=y # InfiniBand support # CONFIG_INFINIBAND=m -CONFIG_INFINIBAND_USER_VERBS=m CONFIG_INFINIBAND_MTHCA=m # CONFIG_INFINIBAND_MTHCA_DEBUG is not set CONFIG_INFINIBAND_IPOIB=m # CONFIG_INFINIBAND_IPOIB_DEBUG is not set -# -# SN Devices -# - # # File systems # @@ -1130,8 +1113,6 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -1163,7 +1144,6 @@ CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y @@ -1194,6 +1174,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y +# CONFIG_DEVFS_FS is not set CONFIG_DEVPTS_FS_XATTR=y CONFIG_DEVPTS_FS_SECURITY=y CONFIG_TMPFS=y @@ -1225,20 +1206,15 @@ CONFIG_CRAMFS=y # CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_TCP=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y diff --git a/trunk/arch/ppc64/kernel/LparData.c b/trunk/arch/ppc64/kernel/LparData.c index 76cfd1449d52..6ffcf67dd507 100644 --- a/trunk/arch/ppc64/kernel/LparData.c +++ b/trunk/arch/ppc64/kernel/LparData.c @@ -33,36 +33,17 @@ * the hypervisor and Linux. */ -/* - * WARNING - magic here - * - * Ok, this is a horrid hack below, but marginally better than the - * alternatives. What we really want is just to initialize - * hvReleaseData in C as in the #if 0 section here. However, gcc - * refuses to believe that (u32)&x is a constant expression, so will - * not allow the xMsNucDataOffset field to be properly initialized. - * So, we declare hvReleaseData in inline asm instead. We use inline - * asm, rather than a .S file, because the assembler won't generate - * the necessary relocation for the LparMap either, unless that symbol - * is declared in the same source file. Finally, we put the asm in a - * dummy, attribute-used function, instead of at file scope, because - * file scope asms don't allow contraints. We want to use the "i" - * constraints to put sizeof() and offsetof() expressions in there, - * because including asm/offsets.h in C code then stringifying causes - * all manner of warnings. - */ -#if 0 struct HvReleaseData hvReleaseData = { .xDesc = 0xc8a5d9c4, /* "HvRD" ebcdic */ .xSize = sizeof(struct HvReleaseData), .xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas), .xSlicNacaAddr = &naca, /* 64-bit Naca address */ - .xMsNucDataOffset = (u32)((unsigned long)&xLparMap - KERNELBASE), - .xFlags = HVREL_TAGSINACTIVE /* tags inactive */ - /* 64 bit */ - /* shared processors */ - /* HMT allowed */ - | 6, /* TEMP: This allows non-GA driver */ + .xMsNucDataOffset = 0x4800, /* offset of LparMap within loadarea (see head.S) */ + .xTagsMode = 1, /* tags inactive */ + .xAddressSize = 0, /* 64 bit */ + .xNoSharedProcs = 0, /* shared processors */ + .xNoHMT = 0, /* HMT allowed */ + .xRsvd2 = 6, /* TEMP: This allows non-GA driver */ .xVrmIndex = 4, /* We are v5r2m0 */ .xMinSupportedPlicVrmIndex = 3, /* v5r1m0 */ .xMinCompatablePlicVrmIndex = 3, /* v5r1m0 */ @@ -70,63 +51,6 @@ struct HvReleaseData hvReleaseData = { 0xa7, 0x40, 0xf2, 0x4b, 0xf4, 0x4b, 0xf6, 0xf4 }, }; -#endif - - -extern struct HvReleaseData hvReleaseData; - -static void __attribute_used__ hvReleaseData_wrapper(void) -{ - /* This doesn't appear to need any alignment (even 4 byte) */ - asm volatile ( - " lparMapPhys = xLparMap - %3\n" - " .data\n" - " .globl hvReleaseData\n" - "hvReleaseData:\n" - " .long 0xc8a5d9c4\n" /* xDesc */ - /* "HvRD" in ebcdic */ - " .short %0\n" /* xSize */ - " .short %1\n" /* xVpdAreasPtrOffset */ - " .llong naca\n" /* xSlicNacaAddr */ - " .long lparMapPhys\n" /* xMsNucDataOffset */ - " .long 0\n" /* xRsvd1 */ - " .short %2\n" /* xFlags */ - " .short 4\n" /* xVrmIndex - v5r2m0 */ - " .short 3\n" /* xMinSupportedPlicVrmIndex - v5r1m0 */ - " .short 3\n" /* xMinCompatablePlicVrmIndex - v5r1m0 */ - " .long 0xd38995a4\n" /* xVrmName */ - " .long 0xa740f24b\n" /* "Linux 2.4.64" ebcdic */ - " .long 0xf44bf6f4\n" - " . = hvReleaseData + %0\n" - " .previous\n" - : : "i"(sizeof(hvReleaseData)), - "i"(offsetof(struct naca_struct, xItVpdAreas)), - "i"(HVREL_TAGSINACTIVE /* tags inactive, 64 bit, */ - /* shared processors, HMT allowed */ - | 6), /* TEMP: This allows non-GA drivers */ - "i"(KERNELBASE) - ); -} - -struct LparMap __attribute__((aligned (16))) xLparMap = { - .xNumberEsids = HvEsidsToMap, - .xNumberRanges = HvRangesToMap, - .xSegmentTableOffs = STAB0_PAGE, - - .xEsids = { - { .xKernelEsid = GET_ESID(KERNELBASE), - .xKernelVsid = KERNEL_VSID(KERNELBASE), }, - { .xKernelEsid = GET_ESID(VMALLOCBASE), - .xKernelVsid = KERNEL_VSID(VMALLOCBASE), }, - }, - - .xRanges = { - { .xPages = HvPagesToMap, - .xOffset = 0, - .xVPN = KERNEL_VSID(KERNELBASE) << (SID_SHIFT - PAGE_SHIFT), - }, - }, -}; extern void system_reset_iSeries(void); extern void machine_check_iSeries(void); diff --git a/trunk/arch/ppc64/kernel/head.S b/trunk/arch/ppc64/kernel/head.S index 74fc3bc68604..93ebcac0d5a2 100644 --- a/trunk/arch/ppc64/kernel/head.S +++ b/trunk/arch/ppc64/kernel/head.S @@ -522,9 +522,36 @@ __end_interrupts: #ifdef CONFIG_PPC_ISERIES .globl naca naca: - .llong itVpdAreas - .llong 0 /* xRamDisk */ - .llong 0 /* xRamDiskSize */ + .llong itVpdAreas + + /* + * The iSeries LPAR map is at this fixed address + * so that the HvReleaseData structure can address + * it with a 32-bit offset. + * + * The VSID values below are dependent on the + * VSID generation algorithm. See include/asm/mmu_context.h. + */ + + . = 0x4800 + + .llong 2 /* # ESIDs to be mapped by hypervisor */ + .llong 1 /* # memory ranges to be mapped by hypervisor */ + .llong STAB0_PAGE /* Page # of segment table within load area */ + .llong 0 /* Reserved */ + .llong 0 /* Reserved */ + .llong 0 /* Reserved */ + .llong 0 /* Reserved */ + .llong 0 /* Reserved */ + .llong (KERNELBASE>>SID_SHIFT) + .llong 0x408f92c94 /* KERNELBASE VSID */ + /* We have to list the bolted VMALLOC segment here, too, so that it + * will be restored on shared processor switch */ + .llong (VMALLOCBASE>>SID_SHIFT) + .llong 0xf09b89af5 /* VMALLOCBASE VSID */ + .llong 8192 /* # pages to map (32 MB) */ + .llong 0 /* Offset from start of loadarea to start of map */ + .llong 0x408f92c940000 /* VPN of first page to map */ . = 0x6100 @@ -2104,6 +2131,13 @@ empty_zero_page: swapper_pg_dir: .space 4096 +#ifdef CONFIG_SMP +/* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */ + .globl stab_array +stab_array: + .space 4096 * 48 +#endif + /* * This space gets a copy of optional info passed to us by the bootstrap * Used to pass parameters into the kernel like root=/dev/sda1, etc. diff --git a/trunk/arch/ppc64/kernel/pmac_setup.c b/trunk/arch/ppc64/kernel/pmac_setup.c index e40877fa67cd..3013cdb5f933 100644 --- a/trunk/arch/ppc64/kernel/pmac_setup.c +++ b/trunk/arch/ppc64/kernel/pmac_setup.c @@ -97,7 +97,7 @@ EXPORT_SYMBOL(smu_cmdbuf_abs); extern void udbg_init_scc(struct device_node *np); -static void __pmac pmac_show_cpuinfo(struct seq_file *m) +void __pmac pmac_show_cpuinfo(struct seq_file *m) { struct device_node *np; char *pp; @@ -144,7 +144,7 @@ static void __pmac pmac_show_cpuinfo(struct seq_file *m) } -static void __init pmac_setup_arch(void) +void __init pmac_setup_arch(void) { /* init to some ~sane value until calibrate_delay() runs */ loops_per_jiffy = 50000000; @@ -230,7 +230,7 @@ void __pmac note_bootable_part(dev_t dev, int part, int goodness) } } -static void __pmac pmac_restart(char *cmd) +void __pmac pmac_restart(char *cmd) { switch(sys_ctrler) { #ifdef CONFIG_ADB_PMU @@ -249,7 +249,7 @@ static void __pmac pmac_restart(char *cmd) } } -static void __pmac pmac_power_off(void) +void __pmac pmac_power_off(void) { switch(sys_ctrler) { #ifdef CONFIG_ADB_PMU @@ -267,7 +267,7 @@ static void __pmac pmac_power_off(void) } } -static void __pmac pmac_halt(void) +void __pmac pmac_halt(void) { pmac_power_off(); } @@ -327,7 +327,7 @@ static void __init init_boot_display(void) /* * Early initialization. */ -static void __init pmac_init_early(void) +void __init pmac_init_early(void) { DBG(" -> pmac_init_early\n"); diff --git a/trunk/arch/ppc64/kernel/setup.c b/trunk/arch/ppc64/kernel/setup.c index 687e85595208..e80f10c89824 100644 --- a/trunk/arch/ppc64/kernel/setup.c +++ b/trunk/arch/ppc64/kernel/setup.c @@ -1068,8 +1068,6 @@ void __init setup_arch(char **cmdline_p) irqstack_early_init(); emergency_stack_init(); - stabs_alloc(); - /* set up the bootmem stuff with available memory */ do_init_bootmem(); sparse_init(); diff --git a/trunk/arch/ppc64/kernel/smp.c b/trunk/arch/ppc64/kernel/smp.c index 793b562da653..2fcddfcb594d 100644 --- a/trunk/arch/ppc64/kernel/smp.c +++ b/trunk/arch/ppc64/kernel/smp.c @@ -65,6 +65,8 @@ struct smp_ops_t *smp_ops; static volatile unsigned int cpu_callin_map[NR_CPUS]; +extern unsigned char stab_array[]; + void smp_call_function_interrupt(void); int smt_enabled_at_boot = 1; @@ -490,6 +492,19 @@ int __devinit __cpu_up(unsigned int cpu) paca[cpu].default_decr = tb_ticks_per_jiffy; + if (!cpu_has_feature(CPU_FTR_SLB)) { + void *tmp; + + /* maximum of 48 CPUs on machines with a segment table */ + if (cpu >= 48) + BUG(); + + tmp = &stab_array[PAGE_SIZE * cpu]; + memset(tmp, 0, PAGE_SIZE); + paca[cpu].stab_addr = (unsigned long)tmp; + paca[cpu].stab_real = virt_to_abs(tmp); + } + /* Make sure callin-map entry is 0 (can be leftover a CPU * hotplug */ diff --git a/trunk/arch/ppc64/kernel/udbg.c b/trunk/arch/ppc64/kernel/udbg.c index c0da45540f0f..d4ccd6f1ef47 100644 --- a/trunk/arch/ppc64/kernel/udbg.c +++ b/trunk/arch/ppc64/kernel/udbg.c @@ -141,7 +141,7 @@ void udbg_init_scc(struct device_node *np) #endif /* CONFIG_PPC_PMAC */ -#ifdef CONFIG_PPC_PMAC +#if CONFIG_PPC_PMAC static void udbg_real_putc(unsigned char c) { while ((real_readb(sccc) & SCC_TXRDY) == 0) diff --git a/trunk/arch/ppc64/mm/stab.c b/trunk/arch/ppc64/mm/stab.c index 1b83f002bf27..df4bbe14153c 100644 --- a/trunk/arch/ppc64/mm/stab.c +++ b/trunk/arch/ppc64/mm/stab.c @@ -18,8 +18,6 @@ #include #include #include -#include -#include struct stab_entry { unsigned long esid_data; @@ -225,39 +223,6 @@ void switch_stab(struct task_struct *tsk, struct mm_struct *mm) extern void slb_initialize(void); -/* - * Allocate segment tables for secondary CPUs. These must all go in - * the first (bolted) segment, so that do_stab_bolted won't get a - * recursive segment miss on the segment table itself. - */ -void stabs_alloc(void) -{ - int cpu; - - if (cpu_has_feature(CPU_FTR_SLB)) - return; - - for_each_cpu(cpu) { - unsigned long newstab; - - if (cpu == 0) - continue; /* stab for CPU 0 is statically allocated */ - - newstab = lmb_alloc_base(PAGE_SIZE, PAGE_SIZE, 1< skip cleanup critical tm __LC_MCK_OLD_PSW+1,0x01 # interrupting from user ? diff --git a/trunk/arch/s390/kernel/entry64.S b/trunk/arch/s390/kernel/entry64.S index d9f22915008c..57ca75d0ad7f 100644 --- a/trunk/arch/s390/kernel/entry64.S +++ b/trunk/arch/s390/kernel/entry64.S @@ -727,9 +727,9 @@ mcck_int_handler: jo 0f spt __LC_LAST_UPDATE_TIMER #ifdef CONFIG_VIRT_CPU_ACCOUNTING - mvc __LC_ASYNC_ENTER_TIMER(8),__LC_LAST_UPDATE_TIMER - mvc __LC_SYNC_ENTER_TIMER(8),__LC_LAST_UPDATE_TIMER - mvc __LC_EXIT_TIMER(8),__LC_LAST_UPDATE_TIMER + mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER + mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER + mvc __LC_LAST_UPDATE_TIMER(8),__LC_EXIT_TIMER 0: tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid? jno mcck_no_vtime # no -> no timer update tm __LC_MCK_OLD_PSW+1,0x01 # interrupting from user ? diff --git a/trunk/arch/s390/kernel/head.S b/trunk/arch/s390/kernel/head.S index d12cff11b4bc..fc8bf5e285f6 100644 --- a/trunk/arch/s390/kernel/head.S +++ b/trunk/arch/s390/kernel/head.S @@ -535,13 +535,8 @@ startup:basr %r13,0 # get base lhi %r1,0 icm %r1,3,.Lscpincr1-PARMAREA(%r4) # use this one if != 0 jnz .Lscnd - lhi %r1,0x800 # otherwise report 2GB + l %r1,.Lscpincr2-PARMAREA+4(%r4) # otherwise use this one .Lscnd: - lhi %r3,0x800 # limit reported memory size to 2GB - cr %r1,%r3 - jl .Lno2gb - lr %r1,%r3 -.Lno2gb: xr %r3,%r3 # same logic ic %r3,.Lscpa1-PARMAREA(%r4) chi %r3,0x00 @@ -770,7 +765,7 @@ _stext: basr %r13,0 # get base # check control registers stctl %c0,%c15,0(%r15) - oi 2(%r15),0x40 # enable sigp emergency signal + oi 2(%r15),0x20 # enable sigp external interrupts oi 0(%r15),0x10 # switch on low address protection lctl %c0,%c15,0(%r15) diff --git a/trunk/arch/s390/kernel/head64.S b/trunk/arch/s390/kernel/head64.S index 10bc592c3637..f525c0c21250 100644 --- a/trunk/arch/s390/kernel/head64.S +++ b/trunk/arch/s390/kernel/head64.S @@ -658,8 +658,10 @@ startup:basr %r13,0 # get base # la %r1,0f-.LPG1(%r13) # set program check address stg %r1,__LC_PGM_NEW_PSW+8 + mvc __LC_DIAG44_OPCODE(8),.Lnop-.LPG1(%r13) diag 0,0,0x44 # test diag 0x44 oi 7(%r12),32 # set diag44 flag + mvc __LC_DIAG44_OPCODE(8),.Ldiag44-.LPG1(%r13) 0: # @@ -700,6 +702,7 @@ startup:basr %r13,0 # get base .L4malign:.quad 0xffffffffffc00000 .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8 .Lnop: .long 0x07000700 +.Ldiag44:.long 0x83000044 .org PARMAREA-64 .Lduct: .long 0,0,0,0,0,0,0,0 @@ -762,7 +765,7 @@ _stext: basr %r13,0 # get base # check control registers stctg %c0,%c15,0(%r15) - oi 6(%r15),0x40 # enable sigp emergency signal + oi 6(%r15),0x20 # enable sigp external interrupts oi 4(%r15),0x10 # switch on low address proctection lctlg %c0,%c15,0(%r15) diff --git a/trunk/arch/s390/kernel/s390_ext.c b/trunk/arch/s390/kernel/s390_ext.c index 207bc511a6e3..3bdd38ec71da 100644 --- a/trunk/arch/s390/kernel/s390_ext.c +++ b/trunk/arch/s390/kernel/s390_ext.c @@ -19,6 +19,7 @@ #include /* + * Simple hash strategy: index = code & 0xff; * ext_int_hash[index] is the start of the list for all external interrupts * that hash to this index. With the current set of external interrupts * (0x1202 external call, 0x1004 cpu timer, 0x2401 hwc console, 0x4000 @@ -26,11 +27,6 @@ */ ext_int_info_t *ext_int_hash[256] = { 0, }; -static inline int ext_hash(__u16 code) -{ - return (code + (code >> 9)) & 0xff; -} - int register_external_interrupt(__u16 code, ext_int_handler_t handler) { ext_int_info_t *p; @@ -41,7 +37,7 @@ int register_external_interrupt(__u16 code, ext_int_handler_t handler) return -ENOMEM; p->code = code; p->handler = handler; - index = ext_hash(code); + index = code & 0xff; p->next = ext_int_hash[index]; ext_int_hash[index] = p; return 0; @@ -56,7 +52,7 @@ int register_early_external_interrupt(__u16 code, ext_int_handler_t handler, return -EINVAL; p->code = code; p->handler = handler; - index = ext_hash(code); + index = code & 0xff; p->next = ext_int_hash[index]; ext_int_hash[index] = p; return 0; @@ -67,7 +63,7 @@ int unregister_external_interrupt(__u16 code, ext_int_handler_t handler) ext_int_info_t *p, *q; int index; - index = ext_hash(code); + index = code & 0xff; q = NULL; p = ext_int_hash[index]; while (p != NULL) { @@ -94,7 +90,7 @@ int unregister_early_external_interrupt(__u16 code, ext_int_handler_t handler, if (p == NULL || p->code != code || p->handler != handler) return -EINVAL; - index = ext_hash(code); + index = code & 0xff; q = ext_int_hash[index]; if (p != q) { while (q != NULL) { @@ -124,7 +120,7 @@ void do_extint(struct pt_regs *regs, unsigned short code) */ account_ticks(regs); kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++; - index = ext_hash(code); + index = code & 0xff; for (p = ext_int_hash[index]; p; p = p->next) { if (likely(p->code == code)) { if (likely(p->handler)) diff --git a/trunk/arch/s390/kernel/setup.c b/trunk/arch/s390/kernel/setup.c index 5ba5a5485da9..a12183989a79 100644 --- a/trunk/arch/s390/kernel/setup.c +++ b/trunk/arch/s390/kernel/setup.c @@ -431,6 +431,12 @@ setup_lowcore(void) ctl_set_bit(14, 29); } #endif +#ifdef CONFIG_ARCH_S390X + if (MACHINE_HAS_DIAG44) + lc->diag44_opcode = 0x83000044; + else + lc->diag44_opcode = 0x07000700; +#endif /* CONFIG_ARCH_S390X */ set_prefix((u32)(unsigned long) lc); } diff --git a/trunk/arch/s390/kernel/smp.c b/trunk/arch/s390/kernel/smp.c index da77f001af8d..642572a8e334 100644 --- a/trunk/arch/s390/kernel/smp.c +++ b/trunk/arch/s390/kernel/smp.c @@ -375,7 +375,7 @@ static void smp_ext_bitcall(int cpu, ec_bit_sig sig) * Set signaling bit in lowcore of target cpu and kick it */ set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast); - while(signal_processor(cpu, sigp_emergency_signal) == sigp_busy) + while(signal_processor(cpu, sigp_external_call) == sigp_busy) udelay(10); } @@ -394,7 +394,7 @@ static void smp_ext_bitcall_others(ec_bit_sig sig) * Set signaling bit in lowcore of target cpu and kick it */ set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast); - while (signal_processor(cpu, sigp_emergency_signal) == sigp_busy) + while (signal_processor(cpu, sigp_external_call) == sigp_busy) udelay(10); } } @@ -751,9 +751,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) unsigned int cpu; int i; - /* request the 0x1201 emergency signal external interrupt */ - if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) - panic("Couldn't request external interrupt 0x1201"); + /* request the 0x1202 external interrupt */ + if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0) + panic("Couldn't request external interrupt 0x1202"); smp_check_cpus(max_cpus); memset(lowcore_ptr,0,sizeof(lowcore_ptr)); /* diff --git a/trunk/arch/s390/lib/Makefile b/trunk/arch/s390/lib/Makefile index b701efa1f00e..a8758b1d20a9 100644 --- a/trunk/arch/s390/lib/Makefile +++ b/trunk/arch/s390/lib/Makefile @@ -5,5 +5,5 @@ EXTRA_AFLAGS := -traditional lib-y += delay.o string.o -lib-$(CONFIG_ARCH_S390_31) += uaccess.o spinlock.o -lib-$(CONFIG_ARCH_S390X) += uaccess64.o spinlock.o +lib-$(CONFIG_ARCH_S390_31) += uaccess.o +lib-$(CONFIG_ARCH_S390X) += uaccess64.o diff --git a/trunk/arch/s390/lib/spinlock.c b/trunk/arch/s390/lib/spinlock.c deleted file mode 100644 index 888b5596c195..000000000000 --- a/trunk/arch/s390/lib/spinlock.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * arch/s390/lib/spinlock.c - * Out of line spinlock code. - * - * S390 version - * Copyright (C) 2004 IBM Deutschland Entwicklung GmbH, IBM Corporation - * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com) - */ - -#include -#include -#include -#include -#include - -atomic_t spin_retry_counter; -int spin_retry = 1000; - -/** - * spin_retry= parameter - */ -static int __init spin_retry_setup(char *str) -{ - spin_retry = simple_strtoul(str, &str, 0); - return 1; -} -__setup("spin_retry=", spin_retry_setup); - -static inline void -_diag44(void) -{ -#ifdef __s390x__ - if (MACHINE_HAS_DIAG44) -#endif - asm volatile("diag 0,0,0x44"); -} - -void -_raw_spin_lock_wait(spinlock_t *lp, unsigned int pc) -{ - int count = spin_retry; - - while (1) { - if (count-- <= 0) { - _diag44(); - count = spin_retry; - } - atomic_inc(&spin_retry_counter); - if (_raw_compare_and_swap(&lp->lock, 0, pc) == 0) - return; - } -} -EXPORT_SYMBOL(_raw_spin_lock_wait); - -int -_raw_spin_trylock_retry(spinlock_t *lp, unsigned int pc) -{ - int count = spin_retry; - - while (count-- > 0) { - atomic_inc(&spin_retry_counter); - if (_raw_compare_and_swap(&lp->lock, 0, pc) == 0) - return 1; - } - return 0; -} -EXPORT_SYMBOL(_raw_spin_trylock_retry); - -void -_raw_read_lock_wait(rwlock_t *rw) -{ - unsigned int old; - int count = spin_retry; - - while (1) { - if (count-- <= 0) { - _diag44(); - count = spin_retry; - } - atomic_inc(&spin_retry_counter); - old = rw->lock & 0x7fffffffU; - if (_raw_compare_and_swap(&rw->lock, old, old + 1) == old) - return; - } -} -EXPORT_SYMBOL(_raw_read_lock_wait); - -int -_raw_read_trylock_retry(rwlock_t *rw) -{ - unsigned int old; - int count = spin_retry; - - while (count-- > 0) { - atomic_inc(&spin_retry_counter); - old = rw->lock & 0x7fffffffU; - if (_raw_compare_and_swap(&rw->lock, old, old + 1) == old) - return 1; - } - return 0; -} -EXPORT_SYMBOL(_raw_read_trylock_retry); - -void -_raw_write_lock_wait(rwlock_t *rw) -{ - int count = spin_retry; - - while (1) { - if (count-- <= 0) { - _diag44(); - count = spin_retry; - } - atomic_inc(&spin_retry_counter); - if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0) - return; - } -} -EXPORT_SYMBOL(_raw_write_lock_wait); - -int -_raw_write_trylock_retry(rwlock_t *rw) -{ - int count = spin_retry; - - while (count-- > 0) { - atomic_inc(&spin_retry_counter); - if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0) - return 1; - } - return 0; -} -EXPORT_SYMBOL(_raw_write_trylock_retry); diff --git a/trunk/arch/sh/kernel/signal.c b/trunk/arch/sh/kernel/signal.c index 8022243f0178..06f1b47eded9 100644 --- a/trunk/arch/sh/kernel/signal.c +++ b/trunk/arch/sh/kernel/signal.c @@ -579,7 +579,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset) if (!user_mode(regs)) return 1; - if (try_to_freeze()) + if (try_to_freeze(0)) goto no_signal; if (!oldset) diff --git a/trunk/arch/sh64/kernel/signal.c b/trunk/arch/sh64/kernel/signal.c index c6a14a87c59b..45ad1026dde7 100644 --- a/trunk/arch/sh64/kernel/signal.c +++ b/trunk/arch/sh64/kernel/signal.c @@ -697,7 +697,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset) if (!user_mode(regs)) return 1; - if (try_to_freeze()) + if (try_to_freeze(0)) goto no_signal; if (!oldset) diff --git a/trunk/arch/sparc/kernel/systbls.S b/trunk/arch/sparc/kernel/systbls.S index 025f4516e651..e457a40838fc 100644 --- a/trunk/arch/sparc/kernel/systbls.S +++ b/trunk/arch/sparc/kernel/systbls.S @@ -48,8 +48,8 @@ sys_call_table: /*135*/ .long sys_nis_syscall, sys_mkdir, sys_rmdir, sys_utimes, sys_stat64 /*140*/ .long sys_sendfile64, sys_nis_syscall, sys_futex, sys_gettid, sys_getrlimit /*145*/ .long sys_setrlimit, sys_pivot_root, sys_prctl, sys_pciconfig_read, sys_pciconfig_write -/*150*/ .long sys_nis_syscall, sys_nis_syscall, sys_nis_syscall, sys_poll, sys_getdents64 -/*155*/ .long sys_fcntl64, sys_ni_syscall, sys_statfs, sys_fstatfs, sys_oldumount +/*150*/ .long sys_nis_syscall, sys_inotify_init, sys_inotify_add_watch, sys_poll, sys_getdents64 +/*155*/ .long sys_fcntl64, sys_inotify_rm_watch, sys_statfs, sys_fstatfs, sys_oldumount /*160*/ .long sys_sched_setaffinity, sys_sched_getaffinity, sys_getdomainname, sys_setdomainname, sys_nis_syscall /*165*/ .long sys_quotactl, sys_set_tid_address, sys_mount, sys_ustat, sys_setxattr /*170*/ .long sys_lsetxattr, sys_fsetxattr, sys_getxattr, sys_lgetxattr, sys_getdents diff --git a/trunk/arch/sparc64/kernel/systbls.S b/trunk/arch/sparc64/kernel/systbls.S index bceb91a8a2bd..53eaf2345fe9 100644 --- a/trunk/arch/sparc64/kernel/systbls.S +++ b/trunk/arch/sparc64/kernel/systbls.S @@ -50,8 +50,8 @@ sys_call_table32: .word sys_nis_syscall, sys32_mkdir, sys_rmdir, sys32_utimes, compat_sys_stat64 /*140*/ .word sys32_sendfile64, sys_nis_syscall, sys32_futex, sys_gettid, compat_sys_getrlimit .word compat_sys_setrlimit, sys_pivot_root, sys32_prctl, sys_pciconfig_read, sys_pciconfig_write -/*150*/ .word sys_nis_syscall, sys_nis_syscall, sys_nis_syscall, sys_poll, sys_getdents64 - .word compat_sys_fcntl64, sys_ni_syscall, compat_sys_statfs, compat_sys_fstatfs, sys_oldumount +/*150*/ .word sys_nis_syscall, sys_inotify_init, sys_inotify_add_watch, sys_poll, sys_getdents64 + .word compat_sys_fcntl64, sys_inotify_rm_watch, compat_sys_statfs, compat_sys_fstatfs, sys_oldumount /*160*/ .word compat_sys_sched_setaffinity, compat_sys_sched_getaffinity, sys32_getdomainname, sys32_setdomainname, sys_nis_syscall .word sys_quotactl, sys_set_tid_address, compat_sys_mount, sys_ustat, sys32_setxattr /*170*/ .word sys32_lsetxattr, sys32_fsetxattr, sys_getxattr, sys_lgetxattr, compat_sys_getdents @@ -116,8 +116,8 @@ sys_call_table: .word sys_socketpair, sys_mkdir, sys_rmdir, sys_utimes, sys_stat64 /*140*/ .word sys_sendfile64, sys_getpeername, sys_futex, sys_gettid, sys_getrlimit .word sys_setrlimit, sys_pivot_root, sys_prctl, sys_pciconfig_read, sys_pciconfig_write -/*150*/ .word sys_getsockname, sys_nis_syscall, sys_nis_syscall, sys_poll, sys_getdents64 - .word sys_nis_syscall, sys_ni_syscall, sys_statfs, sys_fstatfs, sys_oldumount +/*150*/ .word sys_getsockname, sys_inotify_init, sys_inotify_add_watch, sys_poll, sys_getdents64 + .word sys_nis_syscall, sys_inotify_rm_watch, sys_statfs, sys_fstatfs, sys_oldumount /*160*/ .word sys_sched_setaffinity, sys_sched_getaffinity, sys_getdomainname, sys_setdomainname, sys_utrap_install .word sys_quotactl, sys_set_tid_address, sys_mount, sys_ustat, sys_setxattr /*170*/ .word sys_lsetxattr, sys_fsetxattr, sys_getxattr, sys_lgetxattr, sys_getdents diff --git a/trunk/arch/um/Makefile b/trunk/arch/um/Makefile index f5a83a72aa75..eb4ac403bd93 100644 --- a/trunk/arch/um/Makefile +++ b/trunk/arch/um/Makefile @@ -245,7 +245,7 @@ $(ARCH_DIR)/util: scripts_basic $(SYS_DIR)/sc.h $(ARCH_DIR)/kernel-offsets.h FOR $(ARCH_DIR)/kernel/skas/util: scripts_basic $(ARCH_DIR)/user-offsets.h FORCE $(Q)$(MAKE) $(build)=$@ -$(ARCH_DIR)/os-$(OS)/util: scripts_basic $(ARCH_DIR)/user-offsets.h FORCE +$(ARCH_DIR)/os-$(OS)/util: scripts_basic FORCE $(Q)$(MAKE) $(build)=$@ export SUBARCH USER_CFLAGS OS diff --git a/trunk/arch/um/Makefile-i386 b/trunk/arch/um/Makefile-i386 index a777e57dbf89..93d0818fa816 100644 --- a/trunk/arch/um/Makefile-i386 +++ b/trunk/arch/um/Makefile-i386 @@ -33,7 +33,6 @@ ifneq ($(CONFIG_GPROF),y) ARCH_CFLAGS += -DUM_FASTCALL endif -SYS_UTIL_DIR := $(ARCH_DIR)/sys-i386/util SYS_HEADERS := $(SYS_DIR)/sc.h $(SYS_DIR)/thread.h prepare: $(SYS_HEADERS) diff --git a/trunk/arch/um/drivers/cow.h b/trunk/arch/um/drivers/cow.h index 4fcf3a8d13f4..4fcbe8b1b77e 100644 --- a/trunk/arch/um/drivers/cow.h +++ b/trunk/arch/um/drivers/cow.h @@ -3,10 +3,10 @@ #include -#if defined(__BIG_ENDIAN) +#if __BYTE_ORDER == __BIG_ENDIAN # define ntohll(x) (x) # define htonll(x) (x) -#elif defined(__LITTLE_ENDIAN) +#elif __BYTE_ORDER == __LITTLE_ENDIAN # define ntohll(x) bswap_64(x) # define htonll(x) bswap_64(x) #else diff --git a/trunk/arch/um/drivers/hostaudio_kern.c b/trunk/arch/um/drivers/hostaudio_kern.c index 59602b81b240..d5742783e19d 100644 --- a/trunk/arch/um/drivers/hostaudio_kern.c +++ b/trunk/arch/um/drivers/hostaudio_kern.c @@ -57,10 +57,10 @@ __uml_setup("mixer=", set_mixer, "mixer=\n" MIXER_HELP); #else /*MODULE*/ -module_param(dsp, charp, 0644); +MODULE_PARM(dsp, "s"); MODULE_PARM_DESC(dsp, DSP_HELP); -module_param(mixer, charp, 0644); +MODULE_PARM(mixer, "s"); MODULE_PARM_DESC(mixer, MIXER_HELP); #endif diff --git a/trunk/arch/um/kernel/helper.c b/trunk/arch/um/kernel/helper.c index f83e1e8e2392..13b1f5c2f7ee 100644 --- a/trunk/arch/um/kernel/helper.c +++ b/trunk/arch/um/kernel/helper.c @@ -13,7 +13,6 @@ #include "user.h" #include "kern_util.h" #include "user_util.h" -#include "helper.h" #include "os.h" struct helper_data { @@ -150,7 +149,7 @@ int run_helper_thread(int (*proc)(void *), void *arg, unsigned int flags, return(pid); } -int helper_wait(int pid) +int helper_wait(int pid, int block) { int ret; @@ -161,3 +160,14 @@ int helper_wait(int pid) } return(ret); } + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * Emacs will notice this stuff at the end of the file and automatically + * adjust the settings for this buffer only. This must remain at the end + * of the file. + * --------------------------------------------------------------------------- + * Local variables: + * c-file-style: "linux" + * End: + */ diff --git a/trunk/arch/um/kernel/process.c b/trunk/arch/um/kernel/process.c index 8b01a5584e80..c45a60e9c92d 100644 --- a/trunk/arch/um/kernel/process.c +++ b/trunk/arch/um/kernel/process.c @@ -212,26 +212,12 @@ static int stop_ptraced_child(int pid, int exitcode, int mustexit) static int force_sysemu_disabled = 0; -int ptrace_faultinfo = 1; -int proc_mm = 1; - -static int __init skas0_cmd_param(char *str, int* add) -{ - ptrace_faultinfo = proc_mm = 0; - return 0; -} - static int __init nosysemu_cmd_param(char *str, int* add) { force_sysemu_disabled = 1; return 0; } -__uml_setup("skas0", skas0_cmd_param, - "skas0\n" - " Disables SKAS3 usage, so that SKAS0 is used, unless you \n" - " specify mode=tt.\n\n"); - __uml_setup("nosysemu", nosysemu_cmd_param, "nosysemu\n" " Turns off syscall emulation patch for ptrace (SYSEMU) on.\n" @@ -373,10 +359,12 @@ void forward_pending_sigio(int target) kill(target, SIGIO); } +int ptrace_faultinfo = 0; +int proc_mm = 1; + extern void *__syscall_stub_start, __syscall_stub_end; #ifdef UML_CONFIG_MODE_SKAS - static inline void check_skas3_ptrace_support(void) { struct ptrace_faultinfo fi; @@ -387,7 +375,6 @@ static inline void check_skas3_ptrace_support(void) n = ptrace(PTRACE_FAULTINFO, pid, 0, &fi); if (n < 0) { - ptrace_faultinfo = 0; if(errno == EIO) printf("not found\n"); else { @@ -395,10 +382,8 @@ static inline void check_skas3_ptrace_support(void) } } else { - if (!ptrace_faultinfo) - printf("found but disabled on command line\n"); - else - printf("found\n"); + ptrace_faultinfo = 1; + printf("found\n"); } init_registers(pid); @@ -411,13 +396,13 @@ int can_do_skas(void) if (os_access("/proc/mm", OS_ACC_W_OK) < 0) { proc_mm = 0; printf("not found\n"); - } else { - if (!proc_mm) - printf("found but disabled on command line\n"); - else - printf("found\n"); + goto out; + } + else { + printf("found\n"); } +out: check_skas3_ptrace_support(); return 1; } diff --git a/trunk/arch/um/kernel/skas/syscall_user.c b/trunk/arch/um/kernel/skas/syscall_user.c index 6b0664970147..2828e6e37721 100644 --- a/trunk/arch/um/kernel/skas/syscall_user.c +++ b/trunk/arch/um/kernel/skas/syscall_user.c @@ -15,7 +15,7 @@ void handle_syscall(union uml_pt_regs *regs) { long result; -#ifdef UML_CONFIG_SYSCALL_DEBUG +#if UML_CONFIG_SYSCALL_DEBUG int index; index = record_syscall_start(UPT_SYSCALL_NR(regs)); @@ -27,7 +27,7 @@ void handle_syscall(union uml_pt_regs *regs) REGS_SET_SYSCALL_RETURN(regs->skas.regs, result); syscall_trace(regs, 1); -#ifdef UML_CONFIG_SYSCALL_DEBUG +#if UML_CONFIG_SYSCALL_DEBUG record_syscall_end(index, result); #endif } diff --git a/trunk/arch/um/kernel/um_arch.c b/trunk/arch/um/kernel/um_arch.c index ca2bb6f09a7d..8736d098f0ee 100644 --- a/trunk/arch/um/kernel/um_arch.c +++ b/trunk/arch/um/kernel/um_arch.c @@ -38,9 +38,6 @@ #include "choose-mode.h" #include "mode_kern.h" #include "mode.h" -#ifdef UML_CONFIG_MODE_SKAS -#include "skas.h" -#endif #define DEFAULT_COMMAND_LINE "root=98:0" @@ -321,7 +318,6 @@ int linux_main(int argc, char **argv) unsigned long avail, diff; unsigned long virtmem_size, max_physmem; unsigned int i, add; - char * mode; for (i = 1; i < argc; i++){ if((i == 1) && (argv[i][0] == ' ')) continue; @@ -342,21 +338,6 @@ int linux_main(int argc, char **argv) exit(1); } #endif - -#ifndef CONFIG_MODE_SKAS - mode = "TT"; -#else - /* Show to the user the result of selection */ - if (mode_tt) - mode = "TT"; - else if (proc_mm && ptrace_faultinfo) - mode = "SKAS3"; - else - mode = "SKAS0"; -#endif - - printf("UML running in %s mode\n", mode); - uml_start = CHOOSE_MODE_PROC(set_task_sizes_tt, set_task_sizes_skas, 0, &host_task_size, &task_size); diff --git a/trunk/arch/um/os-Linux/elf_aux.c b/trunk/arch/um/os-Linux/elf_aux.c index 5423b1ca17c4..f0d6060e3e57 100644 --- a/trunk/arch/um/os-Linux/elf_aux.c +++ b/trunk/arch/um/os-Linux/elf_aux.c @@ -11,7 +11,6 @@ #include #include "init.h" #include "elf_user.h" -#include #if ELF_CLASS == ELFCLASS32 typedef Elf32_auxv_t elf_auxv_t; diff --git a/trunk/arch/v850/Makefile b/trunk/arch/v850/Makefile index bf38ca0ad781..6edaed4a310e 100644 --- a/trunk/arch/v850/Makefile +++ b/trunk/arch/v850/Makefile @@ -1,8 +1,8 @@ # # arch/v850/Makefile # -# Copyright (C) 2001,02,03,05 NEC Corporation -# Copyright (C) 2001,02,03,05 Miles Bader +# Copyright (C) 2001,02,03 NEC Corporation +# Copyright (C) 2001,02,03 Miles Bader # # This file is included by the global makefile so that you can add your own # architecture-specific flags and dependencies. Remember to do have actions @@ -22,9 +22,6 @@ CFLAGS += -ffixed-r16 -mno-prolog-function CFLAGS += -fno-builtin CFLAGS += -D__linux__ -DUTS_SYSNAME=\"uClinux\" -# By default, build a kernel that runs on the gdb v850 simulator. -KBUILD_DEFCONFIG := sim_defconfig - # This prevents the linker from consolidating the .gnu.linkonce.this_module # section into .text (which the v850 default linker script for -r does for # some reason) diff --git a/trunk/arch/v850/README b/trunk/arch/v850/README index 12f7f7a665e0..01b98e290d4a 100644 --- a/trunk/arch/v850/README +++ b/trunk/arch/v850/README @@ -1,43 +1,31 @@ This port to the NEC V850E processor supports the following platforms: - "sim" - The gdb v850e simulator (CONFIG_V850E_SIM). - - "rte-ma1-cb" - The Midas labs RTE-V850E/MA1-CB and RTE-V850E/NB85E-CB evaluation - boards (CONFIG_RTE_CB_MA1 and CONFIG_RTE_CB_NB85E). This support - has only been tested when running with the Multi-debugger monitor - ROM (for the Green Hills Multi debugger). The optional NEC - Solution Gear RTE-MOTHER-A motherboard is also supported, which - allows PCI boards to be used (CONFIG_RTE_MB_A_PCI). - - "rte-me2-cb" - The Midas labs RTE-V850E/ME2-CB evaluation board (CONFIG_RTE_CB_ME2). - This has only been tested using a kernel downloaded via an ICE - connection using the Multi debugger. Support for the RTE-MOTHER-A is - present, but hasn't been tested (unlike the other Midas labs cpu - boards, the RTE-V850E/ME2-CB includes an ethernet adaptor). - - "as85ep1" - The NEC AS85EP1 V850E evaluation chip/board (CONFIG_V850E_AS85EP1). - - "anna" - The NEC `Anna' (board/chip) implementation of the V850E2 processor - (CONFIG_V850E2_ANNA). - - "sim85e2c", "sim85e2s" - The sim85e2c and sim85e2s simulators, which are verilog simulations - of the V850E2 NA85E2C/NA85E2S cpu cores (CONFIG_V850E2_SIM85E2C and - CONFIG_V850E2_SIM85E2S). - - "fpga85e2c" - A FPGA implementation of the V850E2 NA85E2C cpu core - (CONFIG_V850E2_FPGA85E2C). - -To get a default kernel configuration for a particular platform, you can -use a _defconfig make target (e.g., "make rte-me2-cb_defconfig"); -to see which default configurations are possible, look in the directory -"arch/v850/configs". + + The gdb v850e simulator (CONFIG_V850E_SIM). + + + The Midas labs RTE-V850E/MA1-CB and RTE-V850E/NB85E-CB evaluation boards + (CONFIG_RTE_CB_MA1 and CONFIG_RTE_CB_NB85E). This support has only been + tested when running with the Multi-debugger monitor ROM (for the Green + Hills Multi debugger). The optional NEC Solution Gear RTE-MOTHER-A + motherboard is also supported, which allows PCI boards to be used + (CONFIG_RTE_MB_A_PCI). + + + The Midas labs RTE-V850E/ME2-CB evaluation board (CONFIG_RTE_CB_ME2). + This has only been tested using a kernel downloaded via an ICE connection + using the Multi debugger. Support for the RTE-MOTHER-A is present, but + hasn't been tested (unlike the other Midas labs cpu boards, the + RTE-V850E/ME2-CB includes an ethernet adaptor). + + + The NEC AS85EP1 V850E evaluation chip/board (CONFIG_V850E_AS85EP1). + + + The NEC `Anna' (board/chip) implementation of the V850E2 processor + (CONFIG_V850E2_ANNA). + + + The sim85e2c and sim85e2s simulators, which are verilog simulations of + the V850E2 NA85E2C/NA85E2S cpu cores (CONFIG_V850E2_SIM85E2C and + CONFIG_V850E2_SIM85E2S). + + + A FPGA implementation of the V850E2 NA85E2C cpu core + (CONFIG_V850E2_FPGA85E2C). Porting to anything with a V850E/MA1 or MA2 processor should be simple. See the file and the files it includes for an example of diff --git a/trunk/arch/v850/configs/rte-ma1-cb_defconfig b/trunk/arch/v850/configs/rte-ma1-cb_defconfig deleted file mode 100644 index 1b5ca3c3a658..000000000000 --- a/trunk/arch/v850/configs/rte-ma1-cb_defconfig +++ /dev/null @@ -1,605 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.12-uc0 -# Thu Jul 21 11:08:27 2005 -# -# CONFIG_MMU is not set -# CONFIG_UID16 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_GENERIC_CALIBRATE_DELAY=y -# CONFIG_ISA is not set -# CONFIG_ISAPNP is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -CONFIG_V850=y - -# -# Processor type and features -# -# CONFIG_V850E_SIM is not set -CONFIG_RTE_CB_MA1=y -# CONFIG_RTE_CB_NB85E is not set -# CONFIG_RTE_CB_ME2 is not set -# CONFIG_V850E_AS85EP1 is not set -# CONFIG_V850E2_SIM85E2C is not set -# CONFIG_V850E2_SIM85E2S is not set -# CONFIG_V850E2_FPGA85E2C is not set -# CONFIG_V850E2_ANNA is not set -CONFIG_V850E=y -CONFIG_V850E_MA1=y -CONFIG_RTE_CB=y -CONFIG_RTE_CB_MULTI=y -CONFIG_RTE_CB_MULTI_DBTRAP=y -# CONFIG_RTE_CB_MA1_KSRAM is not set -CONFIG_RTE_MB_A_PCI=y -CONFIG_RTE_GBUS_INT=y -CONFIG_PCI=y -CONFIG_V850E_INTC=y -CONFIG_V850E_TIMER_D=y -# CONFIG_V850E_CACHE is not set -# CONFIG_V850E2_CACHE is not set -CONFIG_NO_CACHE=y -CONFIG_ZERO_BSS=y -# CONFIG_V850E_HIGHRES_TIMER is not set -# CONFIG_RESET_GUARD is not set -CONFIG_LARGE_ALLOCS=y - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -# CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_BASE_FULL is not set -# CONFIG_FUTEX is not set -# CONFIG_EPOLL is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -CONFIG_BASE_SMALL=1 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Bus options (PCI, PCMCIA, EISA, MCA, ISA) -# -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set -# CONFIG_PCI_DEBUG is not set - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_FLAT=y -# CONFIG_BINFMT_ZFLAT is not set -# CONFIG_BINFMT_SHARED_FLAT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_PARTITIONS is not set - -# -# User Modules And Translation Layers -# -# CONFIG_MTD_CHAR is not set -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -CONFIG_MTD_SLRAM=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -# CONFIG_ATA_OVER_ETH is not set - -# -# Disk device support -# - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_UNIX is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_IP_TCPDIAG is not set -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_SMC is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NE2000 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_DGRS is not set -CONFIG_EEPRO100=y -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_V850E_UART=y -CONFIG_V850E_UART_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -# CONFIG_UNIX98_PTYS is not set -# CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -CONFIG_ROMFS_FS=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_HFSPLUS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_SUNRPC=y -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_MAGIC_SYSRQ is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_FS is not set -# CONFIG_NO_KERNEL_MSG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set diff --git a/trunk/arch/v850/configs/rte-me2-cb_defconfig b/trunk/arch/v850/configs/rte-me2-cb_defconfig deleted file mode 100644 index 44becc065404..000000000000 --- a/trunk/arch/v850/configs/rte-me2-cb_defconfig +++ /dev/null @@ -1,453 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.12-uc0 -# Thu Jul 21 11:30:08 2005 -# -# CONFIG_MMU is not set -# CONFIG_UID16 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_GENERIC_CALIBRATE_DELAY=y -# CONFIG_ISA is not set -# CONFIG_ISAPNP is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -CONFIG_V850=y - -# -# Processor type and features -# -# CONFIG_V850E_SIM is not set -# CONFIG_RTE_CB_MA1 is not set -# CONFIG_RTE_CB_NB85E is not set -CONFIG_RTE_CB_ME2=y -# CONFIG_V850E_AS85EP1 is not set -# CONFIG_V850E2_SIM85E2C is not set -# CONFIG_V850E2_SIM85E2S is not set -# CONFIG_V850E2_FPGA85E2C is not set -# CONFIG_V850E2_ANNA is not set -CONFIG_V850E=y -CONFIG_V850E_ME2=y -CONFIG_RTE_CB=y -# CONFIG_RTE_MB_A_PCI is not set -# CONFIG_PCI is not set -CONFIG_V850E_INTC=y -CONFIG_V850E_TIMER_D=y -CONFIG_V850E_CACHE=y -# CONFIG_V850E2_CACHE is not set -# CONFIG_NO_CACHE is not set -# CONFIG_ROM_KERNEL is not set -CONFIG_ZERO_BSS=y -# CONFIG_V850E_HIGHRES_TIMER is not set -# CONFIG_RESET_GUARD is not set -CONFIG_LARGE_ALLOCS=y - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -# CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_BASE_FULL is not set -# CONFIG_FUTEX is not set -# CONFIG_EPOLL is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -CONFIG_BASE_SMALL=1 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Bus options (PCI, PCMCIA, EISA, MCA, ISA) -# - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_FLAT=y -# CONFIG_BINFMT_ZFLAT is not set -# CONFIG_BINFMT_SHARED_FLAT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_PARTITIONS is not set - -# -# User Modules And Translation Layers -# -# CONFIG_MTD_CHAR is not set -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set - -# -# Self-contained MTD device drivers -# -CONFIG_MTD_SLRAM=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set - -# -# Disk device support -# - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support -# -# CONFIG_NET is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -# CONFIG_V850E_UART is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_UNIX98_PTYS is not set -# CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -CONFIG_ROMFS_FS=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_HFSPLUS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_MAGIC_SYSRQ is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_FS is not set -# CONFIG_NO_KERNEL_MSG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set diff --git a/trunk/arch/v850/configs/sim_defconfig b/trunk/arch/v850/configs/sim_defconfig deleted file mode 100644 index d73f5f9d8383..000000000000 --- a/trunk/arch/v850/configs/sim_defconfig +++ /dev/null @@ -1,442 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.12-uc0 -# Thu Jul 21 11:29:27 2005 -# -# CONFIG_MMU is not set -# CONFIG_UID16 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_GENERIC_CALIBRATE_DELAY=y -# CONFIG_ISA is not set -# CONFIG_ISAPNP is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -CONFIG_V850=y - -# -# Processor type and features -# -CONFIG_V850E_SIM=y -# CONFIG_RTE_CB_MA1 is not set -# CONFIG_RTE_CB_NB85E is not set -# CONFIG_RTE_CB_ME2 is not set -# CONFIG_V850E_AS85EP1 is not set -# CONFIG_V850E2_SIM85E2C is not set -# CONFIG_V850E2_SIM85E2S is not set -# CONFIG_V850E2_FPGA85E2C is not set -# CONFIG_V850E2_ANNA is not set -CONFIG_V850E=y -# CONFIG_PCI is not set -# CONFIG_V850E_INTC is not set -# CONFIG_V850E_TIMER_D is not set -# CONFIG_V850E_CACHE is not set -# CONFIG_V850E2_CACHE is not set -CONFIG_NO_CACHE=y -CONFIG_ZERO_BSS=y -# CONFIG_RESET_GUARD is not set -CONFIG_LARGE_ALLOCS=y - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -# CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_BASE_FULL is not set -# CONFIG_FUTEX is not set -# CONFIG_EPOLL is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -CONFIG_BASE_SMALL=1 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Bus options (PCI, PCMCIA, EISA, MCA, ISA) -# - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_FLAT=y -# CONFIG_BINFMT_ZFLAT is not set -# CONFIG_BINFMT_SHARED_FLAT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_PARTITIONS is not set - -# -# User Modules And Translation Layers -# -# CONFIG_MTD_CHAR is not set -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set - -# -# Self-contained MTD device drivers -# -CONFIG_MTD_SLRAM=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set - -# -# Disk device support -# - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support -# -# CONFIG_NET is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_UNIX98_PTYS is not set -# CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -CONFIG_ROMFS_FS=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_HFSPLUS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_MAGIC_SYSRQ is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_FS is not set -# CONFIG_NO_KERNEL_MSG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set diff --git a/trunk/arch/v850/kernel/rte_mb_a_pci.c b/trunk/arch/v850/kernel/rte_mb_a_pci.c index ffbb6d073bf2..074b50abc89d 100644 --- a/trunk/arch/v850/kernel/rte_mb_a_pci.c +++ b/trunk/arch/v850/kernel/rte_mb_a_pci.c @@ -1,8 +1,8 @@ /* * arch/v850/kernel/mb_a_pci.c -- PCI support for Midas lab RTE-MOTHER-A board * - * Copyright (C) 2001,02,03,05 NEC Electronics Corporation - * Copyright (C) 2001,02,03,05 Miles Bader + * Copyright (C) 2001,02,03 NEC Electronics Corporation + * Copyright (C) 2001,02,03 Miles Bader * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -743,17 +743,15 @@ pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len,int dir) for a scatter-gather list, same rules and usage. */ void -pci_dma_sync_sg_for_cpu (struct pci_dev *dev, - struct scatterlist *sg, int sg_len, - int dir) +pci_dma_sync_sg_for_cpu (struct pci_dev *dev, struct scatterlist *sg, int sg_len, + int dir) { BUG (); } void -pci_dma_sync_sg_for_device (struct pci_dev *dev, - struct scatterlist *sg, int sg_len, - int dir) +pci_dma_sync_sg_for_device (struct pci_dev *dev, struct scatterlist *sg, int sg_len, + int dir) { BUG (); } @@ -787,27 +785,6 @@ pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr, free_mb_sram (mb_sram_mem, size); } - -/* iomap/iomap */ - -void __iomem *pci_iomap (struct pci_dev *dev, int bar, unsigned long max) -{ - unsigned long start = pci_resource_start (dev, bar); - unsigned long len = pci_resource_len (dev, bar); - - if (!start || len == 0) - return 0; - - /* None of the ioremap functions actually do anything, other than - re-casting their argument, so don't bother differentiating them. */ - return ioremap (start, len); -} - -void pci_iounmap (struct pci_dev *dev, void __iomem *addr) -{ - /* nothing */ -} - /* symbol exports (for modules) */ @@ -817,5 +794,3 @@ EXPORT_SYMBOL (pci_alloc_consistent); EXPORT_SYMBOL (pci_free_consistent); EXPORT_SYMBOL (pci_dma_sync_single_for_cpu); EXPORT_SYMBOL (pci_dma_sync_single_for_device); -EXPORT_SYMBOL (pci_iomap); -EXPORT_SYMBOL (pci_iounmap); diff --git a/trunk/arch/v850/kernel/vmlinux.lds.S b/trunk/arch/v850/kernel/vmlinux.lds.S index 5be05f47109e..c366a8b326ee 100644 --- a/trunk/arch/v850/kernel/vmlinux.lds.S +++ b/trunk/arch/v850/kernel/vmlinux.lds.S @@ -12,7 +12,6 @@ */ #include - #define VMLINUX_SYMBOL(_sym_) _##_sym_ #include @@ -43,19 +42,6 @@ *(.rodata) *(.rodata.*) \ *(__vermagic) /* Kernel version magic */ \ *(.rodata1) \ - /* PCI quirks */ \ - ___start_pci_fixups_early = . ; \ - *(.pci_fixup_early) \ - ___end_pci_fixups_early = . ; \ - ___start_pci_fixups_header = . ; \ - *(.pci_fixup_header) \ - ___end_pci_fixups_header = . ; \ - ___start_pci_fixups_final = . ; \ - *(.pci_fixup_final) \ - ___end_pci_fixups_final = . ; \ - ___start_pci_fixups_enable = . ; \ - *(.pci_fixup_enable) \ - ___end_pci_fixups_enable = . ; \ /* Kernel symbol table: Normal symbols */ \ ___start___ksymtab = .; \ *(__ksymtab) \ diff --git a/trunk/arch/x86_64/ia32/ia32_aout.c b/trunk/arch/x86_64/ia32/ia32_aout.c index 3e6780fa0186..c12edf5d97f0 100644 --- a/trunk/arch/x86_64/ia32/ia32_aout.c +++ b/trunk/arch/x86_64/ia32/ia32_aout.c @@ -42,7 +42,7 @@ extern int ia32_setup_arg_pages(struct linux_binprm *bprm, static int load_aout_binary(struct linux_binprm *, struct pt_regs * regs); static int load_aout_library(struct file*); -#ifdef CORE_DUMP +#if CORE_DUMP static int aout_core_dump(long signr, struct pt_regs * regs, struct file *file); /* @@ -103,7 +103,7 @@ static struct linux_binfmt aout_format = { .module = THIS_MODULE, .load_binary = load_aout_binary, .load_shlib = load_aout_library, -#ifdef CORE_DUMP +#if CORE_DUMP .core_dump = aout_core_dump, #endif .min_coredump = PAGE_SIZE @@ -120,7 +120,7 @@ static void set_brk(unsigned long start, unsigned long end) up_write(¤t->mm->mmap_sem); } -#ifdef CORE_DUMP +#if CORE_DUMP /* * These are the only things you should do on a core-file: use only these * macros to write out all the necessary info. diff --git a/trunk/arch/x86_64/ia32/sys_ia32.c b/trunk/arch/x86_64/ia32/sys_ia32.c index be996d1b691e..70caf89d4c21 100644 --- a/trunk/arch/x86_64/ia32/sys_ia32.c +++ b/trunk/arch/x86_64/ia32/sys_ia32.c @@ -61,7 +61,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/trunk/arch/x86_64/kernel/smpboot.c b/trunk/arch/x86_64/kernel/smpboot.c index e773a794ec45..b969ee128728 100644 --- a/trunk/arch/x86_64/kernel/smpboot.c +++ b/trunk/arch/x86_64/kernel/smpboot.c @@ -229,7 +229,7 @@ static __cpuinit void sync_master(void *arg) { unsigned long flags, i; - if (smp_processor_id() != 0) + if (smp_processor_id() != boot_cpu_id) return; go[MASTER] = 0; @@ -285,7 +285,7 @@ static __cpuinit void sync_tsc(void) int i, done = 0; long delta, adj, adjust_latency = 0; unsigned long flags, rt, master_time_stamp, bound; -#ifdef DEBUG_TSC_SYNC +#if DEBUG_TSC_SYNC static struct syncdebug { long rt; /* roundtrip time */ long master; /* master's timestamp */ @@ -321,7 +321,7 @@ static __cpuinit void sync_tsc(void) rdtscll(t); wrmsrl(MSR_IA32_TSC, t + adj); } -#ifdef DEBUG_TSC_SYNC +#if DEBUG_TSC_SYNC t[i].rt = rt; t[i].master = master_time_stamp; t[i].diff = delta; @@ -331,7 +331,7 @@ static __cpuinit void sync_tsc(void) } spin_unlock_irqrestore(&tsc_sync_lock, flags); -#ifdef DEBUG_TSC_SYNC +#if DEBUG_TSC_SYNC for (i = 0; i < NUM_ROUNDS; ++i) printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", t[i].rt, t[i].master, t[i].diff, t[i].lat); @@ -537,7 +537,7 @@ void __cpuinit start_secondary(void) extern volatile unsigned long init_rsp; extern void (*initial_code)(void); -#ifdef APIC_DEBUG +#if APIC_DEBUG static void inquire_remote_apic(int apicid) { unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; @@ -841,7 +841,7 @@ static int __cpuinit do_boot_cpu(int cpu, int apicid) else /* trampoline code not run */ printk("Not responding.\n"); -#ifdef APIC_DEBUG +#if APIC_DEBUG inquire_remote_apic(apicid); #endif } diff --git a/trunk/crypto/aes.c b/trunk/crypto/aes.c index 5df92888ef5a..d0dd7c3c5278 100644 --- a/trunk/crypto/aes.c +++ b/trunk/crypto/aes.c @@ -67,7 +67,7 @@ /* * #define byte(x, nr) ((unsigned char)((x) >> (nr*8))) */ -static inline u8 +inline static u8 byte(const u32 x, const unsigned n) { return x >> (n << 3); diff --git a/trunk/drivers/block/as-iosched.c b/trunk/drivers/block/as-iosched.c index 95c0a3690b0f..91aeb678135d 100644 --- a/trunk/drivers/block/as-iosched.c +++ b/trunk/drivers/block/as-iosched.c @@ -1935,15 +1935,23 @@ struct as_fs_entry { static ssize_t as_var_show(unsigned int var, char *page) { + var = (var * 1000) / HZ; return sprintf(page, "%d\n", var); } static ssize_t as_var_store(unsigned long *var, const char *page, size_t count) { + unsigned long tmp; char *p = (char *) page; - *var = simple_strtoul(p, &p, 10); + tmp = simple_strtoul(p, &p, 10); + if (tmp != 0) { + tmp = (tmp * HZ) / 1000; + if (tmp == 0) + tmp = 1; + } + *var = tmp; return count; } diff --git a/trunk/drivers/block/sx8.c b/trunk/drivers/block/sx8.c index d57007b92f77..9db0a9e3e59c 100644 --- a/trunk/drivers/block/sx8.c +++ b/trunk/drivers/block/sx8.c @@ -1582,7 +1582,7 @@ static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) if (rc) goto err_out; -#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ +#if IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ rc = pci_set_dma_mask(pdev, DMA_64BIT_MASK); if (!rc) { rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); @@ -1601,7 +1601,7 @@ static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) goto err_out_regions; } pci_dac = 0; -#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ +#if IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ } #endif diff --git a/trunk/drivers/block/ub.c b/trunk/drivers/block/ub.c index a026567f5d18..685f061e69b2 100644 --- a/trunk/drivers/block/ub.c +++ b/trunk/drivers/block/ub.c @@ -23,7 +23,6 @@ * -- Exterminate P3 printks * -- Resove XXX's * -- Redo "benh's retries", perhaps have spin-up code to handle them. V:D=? - * -- CLEAR, CLR2STS, CLRRS seem to be ripe for refactoring. */ #include #include @@ -38,73 +37,6 @@ #define UB_MAJOR 180 -/* - * The command state machine is the key model for understanding of this driver. - * - * The general rule is that all transitions are done towards the bottom - * of the diagram, thus preventing any loops. - * - * An exception to that is how the STAT state is handled. A counter allows it - * to be re-entered along the path marked with [C]. - * - * +--------+ - * ! INIT ! - * +--------+ - * ! - * ub_scsi_cmd_start fails ->--------------------------------------\ - * ! ! - * V ! - * +--------+ ! - * ! CMD ! ! - * +--------+ ! - * ! +--------+ ! - * was -EPIPE -->-------------------------------->! CLEAR ! ! - * ! +--------+ ! - * ! ! ! - * was error -->------------------------------------- ! --------->\ - * ! ! ! - * /--<-- cmd->dir == NONE ? ! ! - * ! ! ! ! - * ! V ! ! - * ! +--------+ ! ! - * ! ! DATA ! ! ! - * ! +--------+ ! ! - * ! ! +---------+ ! ! - * ! was -EPIPE -->--------------->! CLR2STS ! ! ! - * ! ! +---------+ ! ! - * ! ! ! ! ! - * ! ! was error -->---- ! --------->\ - * ! was error -->--------------------- ! ------------- ! --------->\ - * ! ! ! ! ! - * ! V ! ! ! - * \--->+--------+ ! ! ! - * ! STAT !<--------------------------/ ! ! - * /--->+--------+ ! ! - * ! ! ! ! - * [C] was -EPIPE -->-----------\ ! ! - * ! ! ! ! ! - * +<---- len == 0 ! ! ! - * ! ! ! ! ! - * ! was error -->--------------------------------------!---------->\ - * ! ! ! ! ! - * +<---- bad CSW ! ! ! - * +<---- bad tag ! ! ! - * ! ! V ! ! - * ! ! +--------+ ! ! - * ! ! ! CLRRS ! ! ! - * ! ! +--------+ ! ! - * ! ! ! ! ! - * \------- ! --------------------[C]--------\ ! ! - * ! ! ! ! - * cmd->error---\ +--------+ ! ! - * ! +--------------->! SENSE !<----------/ ! - * STAT_FAIL----/ +--------+ ! - * ! ! V - * ! V +--------+ - * \--------------------------------\--------------------->! DONE ! - * +--------+ - */ - /* * Definitions which have to be scattered once we understand the layout better. */ @@ -159,6 +91,8 @@ struct bulk_cs_wrap { #define US_BULK_CS_WRAP_LEN 13 #define US_BULK_CS_SIGN 0x53425355 /* spells out 'USBS' */ +/* This is for Olympus Camedia digital cameras */ +#define US_BULK_CS_OLYMPUS_SIGN 0x55425355 /* spells out 'USBU' */ #define US_BULK_STAT_OK 0 #define US_BULK_STAT_FAIL 1 #define US_BULK_STAT_PHASE 2 @@ -201,7 +135,6 @@ enum ub_scsi_cmd_state { UB_CMDST_CLR2STS, /* Clearing before requesting status */ UB_CMDST_STAT, /* Status phase */ UB_CMDST_CLEAR, /* Clearing a stall (halt, actually) */ - UB_CMDST_CLRRS, /* Clearing before retrying status */ UB_CMDST_SENSE, /* Sending Request Sense */ UB_CMDST_DONE /* Final state */ }; @@ -213,7 +146,6 @@ static char *ub_scsi_cmd_stname[] = { "c2s", "sts", "clr", - "crs", "Sen", "fin" }; @@ -384,7 +316,6 @@ struct ub_dev { struct urb work_urb; struct timer_list work_timer; int last_pipe; /* What might need clearing */ - __le32 signature; /* Learned signature */ struct bulk_cb_wrap work_bcb; struct bulk_cs_wrap work_bcs; struct usb_ctrlrequest work_cr; @@ -408,9 +339,8 @@ static void ub_scsi_action(unsigned long _dev); static void ub_scsi_dispatch(struct ub_dev *sc); static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd); static void ub_state_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd, int rc); -static int __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd); +static void __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd); static void ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd); -static void ub_state_stat_counted(struct ub_dev *sc, struct ub_scsi_cmd *cmd); static void ub_state_sense(struct ub_dev *sc, struct ub_scsi_cmd *cmd); static int ub_submit_clear_stall(struct ub_dev *sc, struct ub_scsi_cmd *cmd, int stalled_pipe); @@ -1155,28 +1085,6 @@ static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd) ub_state_stat(sc, cmd); - } else if (cmd->state == UB_CMDST_CLRRS) { - if (urb->status == -EPIPE) { - /* - * STALL while clearning STALL. - * The control pipe clears itself - nothing to do. - * XXX Might try to reset the device here and retry. - */ - printk(KERN_NOTICE "%s: stall on control pipe\n", - sc->name); - goto Bad_End; - } - - /* - * We ignore the result for the halt clear. - */ - - /* reset the endpoint toggle */ - usb_settoggle(sc->dev, usb_pipeendpoint(sc->last_pipe), - usb_pipeout(sc->last_pipe), 0); - - ub_state_stat_counted(sc, cmd); - } else if (cmd->state == UB_CMDST_CMD) { if (urb->status == -EPIPE) { rc = ub_submit_clear_stall(sc, cmd, sc->last_pipe); @@ -1282,57 +1190,52 @@ static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd) */ goto Bad_End; } - - /* - * Having a stall when getting CSW is an error, so - * make sure uppper levels are not oblivious to it. - */ - cmd->error = -EIO; /* A cheap trick... */ - - cmd->state = UB_CMDST_CLRRS; + cmd->state = UB_CMDST_CLEAR; ub_cmdtr_state(sc, cmd); return; } - if (urb->status == -EOVERFLOW) { - /* - * XXX We are screwed here. Retrying is pointless, - * because the pipelined data will not get in until - * we read with a big enough buffer. We must reset XXX. - */ - goto Bad_End; - } if (urb->status != 0) goto Bad_End; if (urb->actual_length == 0) { - ub_state_stat_counted(sc, cmd); + /* + * Some broken devices add unnecessary zero-length + * packets to the end of their data transfers. + * Such packets show up as 0-length CSWs. If we + * encounter such a thing, try to read the CSW again. + */ + if (++cmd->stat_count >= 4) { + printk(KERN_NOTICE "%s: unable to get CSW\n", + sc->name); + goto Bad_End; + } + __ub_state_stat(sc, cmd); return; } /* * Check the returned Bulk protocol status. - * The status block has to be validated first. */ bcs = &sc->work_bcs; - - if (sc->signature == cpu_to_le32(0)) { + rc = le32_to_cpu(bcs->Residue); + if (rc != cmd->len - cmd->act_len) { /* - * This is the first reply, so do not perform the check. - * Instead, remember the signature the device uses - * for future checks. But do not allow a nul. + * It is all right to transfer less, the caller has + * to check. But it's not all right if the device + * counts disagree with our counts. */ - sc->signature = bcs->Signature; - if (sc->signature == cpu_to_le32(0)) { - ub_state_stat_counted(sc, cmd); - return; - } - } else { - if (bcs->Signature != sc->signature) { - ub_state_stat_counted(sc, cmd); - return; - } + /* P3 */ printk("%s: resid %d len %d act %d\n", + sc->name, rc, cmd->len, cmd->act_len); + goto Bad_End; + } + +#if 0 + if (bcs->Signature != cpu_to_le32(US_BULK_CS_SIGN) && + bcs->Signature != cpu_to_le32(US_BULK_CS_OLYMPUS_SIGN)) { + /* Windows ignores signatures, so do we. */ } +#endif if (bcs->Tag != cmd->tag) { /* @@ -1342,22 +1245,16 @@ static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd) * commands and reply at commands we timed out before. * Without flushing these replies we loop forever. */ - ub_state_stat_counted(sc, cmd); + if (++cmd->stat_count >= 4) { + printk(KERN_NOTICE "%s: " + "tag mismatch orig 0x%x reply 0x%x\n", + sc->name, cmd->tag, bcs->Tag); + goto Bad_End; + } + __ub_state_stat(sc, cmd); return; } - rc = le32_to_cpu(bcs->Residue); - if (rc != cmd->len - cmd->act_len) { - /* - * It is all right to transfer less, the caller has - * to check. But it's not all right if the device - * counts disagree with our counts. - */ - /* P3 */ printk("%s: resid %d len %d act %d\n", - sc->name, rc, cmd->len, cmd->act_len); - goto Bad_End; - } - switch (bcs->Status) { case US_BULK_STAT_OK: break; @@ -1375,10 +1272,6 @@ static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd) } /* Not zeroing error to preserve a babble indicator */ - if (cmd->error != 0) { - ub_state_sense(sc, cmd); - return; - } cmd->state = UB_CMDST_DONE; ub_cmdtr_state(sc, cmd); ub_cmdq_pop(sc); @@ -1417,7 +1310,7 @@ static void ub_state_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd, int rc) * Factorization helper for the command state machine: * Submit a CSW read. */ -static int __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd) +static void __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd) { int rc; @@ -1435,12 +1328,11 @@ static int __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd) /* XXX Clear stalls */ ub_complete(&sc->work_done); ub_state_done(sc, cmd, rc); - return -1; + return; } sc->work_timer.expires = jiffies + UB_STAT_TIMEOUT; add_timer(&sc->work_timer); - return 0; } /* @@ -1449,34 +1341,13 @@ static int __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd) */ static void ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd) { - - if (__ub_state_stat(sc, cmd) != 0) - return; + __ub_state_stat(sc, cmd); cmd->stat_count = 0; cmd->state = UB_CMDST_STAT; ub_cmdtr_state(sc, cmd); } -/* - * Factorization helper for the command state machine: - * Submit a CSW read and go to STAT state with counter (along [C] path). - */ -static void ub_state_stat_counted(struct ub_dev *sc, struct ub_scsi_cmd *cmd) -{ - - if (++cmd->stat_count >= 4) { - ub_state_sense(sc, cmd); - return; - } - - if (__ub_state_stat(sc, cmd) != 0) - return; - - cmd->state = UB_CMDST_STAT; - ub_cmdtr_state(sc, cmd); -} - /* * Factorization helper for the command state machine: * Submit a REQUEST SENSE and go to SENSE state. diff --git a/trunk/drivers/cdrom/isp16.c b/trunk/drivers/cdrom/isp16.c index db0fd9a240e3..8e68d858ce64 100644 --- a/trunk/drivers/cdrom/isp16.c +++ b/trunk/drivers/cdrom/isp16.c @@ -18,7 +18,7 @@ * * 19 June 2004 -- check_region() converted to request_region() * and return statement cleanups. - * - Jesper Juhl + * Jesper Juhl * * Detect cdrom interface on ISP16 sound card. * Configure cdrom interface. diff --git a/trunk/drivers/cdrom/mcdx.c b/trunk/drivers/cdrom/mcdx.c index b89420e6d704..07bbd24e3c18 100644 --- a/trunk/drivers/cdrom/mcdx.c +++ b/trunk/drivers/cdrom/mcdx.c @@ -51,7 +51,7 @@ */ -#ifdef RCS +#if RCS static const char *mcdx_c_version = "$Id: mcdx.c,v 1.21 1997/01/26 07:12:59 davem Exp $"; #endif @@ -706,7 +706,7 @@ static int mcdx_open(struct cdrom_device_info *cdi, int purpose) xtrace(OPENCLOSE, "open() init irq generation\n"); if (-1 == mcdx_config(stuffp, 1)) return -EIO; -#ifdef FALLBACK +#if FALLBACK /* Set the read speed */ xwarn("AAA %x AAA\n", stuffp->readcmd); if (stuffp->readerrs) @@ -1216,7 +1216,7 @@ static int __init mcdx_init_drive(int drive) } -#ifdef WE_KNOW_WHY +#if WE_KNOW_WHY /* irq 11 -> channel register */ outb(0x50, stuffp->wreg_chn); #endif @@ -1294,7 +1294,7 @@ static int mcdx_transfer(struct s_drive_stuff *stuffp, ans = mcdx_xfer(stuffp, p, sector, nr_sectors); return ans; -#ifdef FALLBACK +#if FALLBACK if (-1 == ans) stuffp->readerrs++; else diff --git a/trunk/drivers/cdrom/optcd.c b/trunk/drivers/cdrom/optcd.c index 351a01dd503a..7e69c54568bf 100644 --- a/trunk/drivers/cdrom/optcd.c +++ b/trunk/drivers/cdrom/optcd.c @@ -245,7 +245,7 @@ module_param(optcd_port, short, 0); /* Busy wait until FLAG goes low. Return 0 on timeout. */ -static inline int flag_low(int flag, unsigned long timeout) +inline static int flag_low(int flag, unsigned long timeout) { int flag_high; unsigned long count = 0; @@ -381,7 +381,7 @@ static int send_seek_params(struct cdrom_msf *params) /* Wait for command execution status. Choice between busy waiting and sleeping. Return value <0 indicates timeout. */ -static inline int get_exec_status(int busy_waiting) +inline static int get_exec_status(int busy_waiting) { unsigned char exec_status; @@ -398,7 +398,7 @@ static inline int get_exec_status(int busy_waiting) /* Wait busy for extra byte of data that a command returns. Return value <0 indicates timeout. */ -static inline int get_data(int short_timeout) +inline static int get_data(int short_timeout) { unsigned char data; @@ -441,14 +441,14 @@ static int reset_drive(void) /* Facilities for asynchronous operation */ /* Read status/data availability flags FL_STEN and FL_DTEN */ -static inline int stdt_flags(void) +inline static int stdt_flags(void) { return inb(STATUS_PORT) & FL_STDT; } /* Fetch status that has previously been waited for. <0 means not available */ -static inline int fetch_status(void) +inline static int fetch_status(void) { unsigned char status; @@ -462,7 +462,7 @@ static inline int fetch_status(void) /* Fetch data that has previously been waited for. */ -static inline void fetch_data(char *buf, int n) +inline static void fetch_data(char *buf, int n) { insb(DATA_PORT, buf, n); DEBUG((DEBUG_DRIVE_IF, "fetched 0x%x bytes", n)); @@ -470,7 +470,7 @@ static inline void fetch_data(char *buf, int n) /* Flush status and data fifos */ -static inline void flush_data(void) +inline static void flush_data(void) { while ((inb(STATUS_PORT) & FL_STDT) != FL_STDT) inb(DATA_PORT); @@ -482,7 +482,7 @@ static inline void flush_data(void) /* Send a simple command and wait for response. Command codes < COMFETCH are quick response commands */ -static inline int exec_cmd(int cmd) +inline static int exec_cmd(int cmd) { int ack = send_cmd(cmd); if (ack < 0) @@ -493,7 +493,7 @@ static inline int exec_cmd(int cmd) /* Send a command with parameters. Don't wait for the response, * which consists of data blocks read from the CD. */ -static inline int exec_read_cmd(int cmd, struct cdrom_msf *params) +inline static int exec_read_cmd(int cmd, struct cdrom_msf *params) { int ack = send_cmd(cmd); if (ack < 0) @@ -503,7 +503,7 @@ static inline int exec_read_cmd(int cmd, struct cdrom_msf *params) /* Send a seek command with parameters and wait for response */ -static inline int exec_seek_cmd(int cmd, struct cdrom_msf *params) +inline static int exec_seek_cmd(int cmd, struct cdrom_msf *params) { int ack = send_cmd(cmd); if (ack < 0) @@ -516,7 +516,7 @@ static inline int exec_seek_cmd(int cmd, struct cdrom_msf *params) /* Send a command with parameters and wait for response */ -static inline int exec_long_cmd(int cmd, struct cdrom_msf *params) +inline static int exec_long_cmd(int cmd, struct cdrom_msf *params) { int ack = exec_read_cmd(cmd, params); if (ack < 0) @@ -528,7 +528,7 @@ static inline int exec_long_cmd(int cmd, struct cdrom_msf *params) /* Binary to BCD (2 digits) */ -static inline void single_bin2bcd(u_char *p) +inline static void single_bin2bcd(u_char *p) { DEBUG((DEBUG_CONV, "bin2bcd %02d", *p)); *p = (*p % 10) | ((*p / 10) << 4); @@ -565,7 +565,7 @@ static void lba2msf(int lba, struct cdrom_msf *msf) /* Two BCD digits to binary */ -static inline u_char bcd2bin(u_char bcd) +inline static u_char bcd2bin(u_char bcd) { DEBUG((DEBUG_CONV, "bcd2bin %x%02x", bcd)); return (bcd >> 4) * 10 + (bcd & 0x0f); @@ -988,7 +988,7 @@ static char buf[CD_FRAMESIZE * N_BUFS]; static volatile int buf_bn[N_BUFS], next_bn; static volatile int buf_in = 0, buf_out = NOBUF; -static inline void opt_invalidate_buffers(void) +inline static void opt_invalidate_buffers(void) { int i; diff --git a/trunk/drivers/char/Kconfig b/trunk/drivers/char/Kconfig index 4f27e5519296..43d0cb19ef6a 100644 --- a/trunk/drivers/char/Kconfig +++ b/trunk/drivers/char/Kconfig @@ -735,7 +735,7 @@ config SGI_IP27_RTC config GEN_RTC tristate "Generic /dev/rtc emulation" - depends on RTC!=y && !IA64 && !ARM && !PPC64 + depends on RTC!=y && !IA64 && !ARM ---help--- If you say Y here and create a character special file /dev/rtc with major number 10 and minor number 135 using mknod ("man mknod"), you diff --git a/trunk/drivers/char/drm/via_dma.c b/trunk/drivers/char/drm/via_dma.c index 4f60f7f4193d..82f839451622 100644 --- a/trunk/drivers/char/drm/via_dma.c +++ b/trunk/drivers/char/drm/via_dma.c @@ -231,7 +231,7 @@ int via_dma_init(DRM_IOCTL_ARGS) drm_via_dma_init_t init; int retcode = 0; - DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data, + DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t *) data, sizeof(init)); switch (init.func) { @@ -343,7 +343,7 @@ int via_cmdbuffer(DRM_IOCTL_ARGS) LOCK_TEST_WITH_RETURN( dev, filp ); - DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, + DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data, sizeof(cmdbuf)); DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size); @@ -386,7 +386,7 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS) LOCK_TEST_WITH_RETURN( dev, filp ); - DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, + DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data, sizeof(cmdbuf)); DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf, @@ -701,7 +701,7 @@ via_cmdbuf_size(DRM_IOCTL_ARGS) return DRM_ERR(EFAULT); } - DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data, + DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t *) data, sizeof(d_siz)); @@ -735,7 +735,7 @@ via_cmdbuf_size(DRM_IOCTL_ARGS) } d_siz.size = tmp_size; - DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz, + DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t *) data, d_siz, sizeof(d_siz)); return ret; } diff --git a/trunk/drivers/char/drm/via_drm.h b/trunk/drivers/char/drm/via_drm.h index be346bb0a26a..4588c9bd1816 100644 --- a/trunk/drivers/char/drm/via_drm.h +++ b/trunk/drivers/char/drm/via_drm.h @@ -158,7 +158,7 @@ typedef struct _drm_via_dma_init { } drm_via_dma_init_t; typedef struct _drm_via_cmdbuffer { - char __user *buf; + char *buf; unsigned long size; } drm_via_cmdbuffer_t; diff --git a/trunk/drivers/char/drm/via_ds.c b/trunk/drivers/char/drm/via_ds.c index 5c71e089246c..daf3df75a20e 100644 --- a/trunk/drivers/char/drm/via_ds.c +++ b/trunk/drivers/char/drm/via_ds.c @@ -133,7 +133,7 @@ memHeap_t *via_mmInit(int ofs, int size) PMemBlock blocks; if (size <= 0) - return NULL; + return 0; blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); @@ -143,7 +143,7 @@ memHeap_t *via_mmInit(int ofs, int size) blocks->free = 1; return (memHeap_t *) blocks; } else - return NULL; + return 0; } static TMemBlock *SliceBlock(TMemBlock * p, diff --git a/trunk/drivers/char/drm/via_ds.h b/trunk/drivers/char/drm/via_ds.h index d2bb9f37ca38..be9c7f9f1aee 100644 --- a/trunk/drivers/char/drm/via_ds.h +++ b/trunk/drivers/char/drm/via_ds.h @@ -61,8 +61,8 @@ struct mem_block_t { struct mem_block_t *heap; int ofs, size; int align; - unsigned int free:1; - unsigned int reserved:1; + int free:1; + int reserved:1; }; typedef struct mem_block_t TMemBlock; typedef struct mem_block_t *PMemBlock; diff --git a/trunk/drivers/char/drm/via_map.c b/trunk/drivers/char/drm/via_map.c index bb171139e737..0be829b6ec65 100644 --- a/trunk/drivers/char/drm/via_map.c +++ b/trunk/drivers/char/drm/via_map.c @@ -95,8 +95,7 @@ int via_map_init(DRM_IOCTL_ARGS) DRM_DEBUG("%s\n", __FUNCTION__); - DRM_COPY_FROM_USER_IOCTL(init, (drm_via_init_t __user *) data, - sizeof(init)); + DRM_COPY_FROM_USER_IOCTL(init, (drm_via_init_t *) data, sizeof(init)); switch (init.func) { case VIA_INIT_MAP: diff --git a/trunk/drivers/char/drm/via_mm.c b/trunk/drivers/char/drm/via_mm.c index 13921f3c0ec2..c22712f44d42 100644 --- a/trunk/drivers/char/drm/via_mm.c +++ b/trunk/drivers/char/drm/via_mm.c @@ -76,8 +76,7 @@ int via_agp_init(DRM_IOCTL_ARGS) { drm_via_agp_t agp; - DRM_COPY_FROM_USER_IOCTL(agp, (drm_via_agp_t __user *) data, - sizeof(agp)); + DRM_COPY_FROM_USER_IOCTL(agp, (drm_via_agp_t *) data, sizeof(agp)); AgpHeap = via_mmInit(agp.offset, agp.size); @@ -93,7 +92,7 @@ int via_fb_init(DRM_IOCTL_ARGS) { drm_via_fb_t fb; - DRM_COPY_FROM_USER_IOCTL(fb, (drm_via_fb_t __user *) data, sizeof(fb)); + DRM_COPY_FROM_USER_IOCTL(fb, (drm_via_fb_t *) data, sizeof(fb)); FBHeap = via_mmInit(fb.offset, fb.size); @@ -194,20 +193,19 @@ int via_mem_alloc(DRM_IOCTL_ARGS) { drm_via_mem_t mem; - DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t __user *) data, - sizeof(mem)); + DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *) data, sizeof(mem)); switch (mem.type) { case VIDEO: if (via_fb_alloc(&mem) < 0) return -EFAULT; - DRM_COPY_TO_USER_IOCTL((drm_via_mem_t __user *) data, mem, + DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *) data, mem, sizeof(mem)); return 0; case AGP: if (via_agp_alloc(&mem) < 0) return -EFAULT; - DRM_COPY_TO_USER_IOCTL((drm_via_mem_t __user *) data, mem, + DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *) data, mem, sizeof(mem)); return 0; } @@ -291,8 +289,7 @@ int via_mem_free(DRM_IOCTL_ARGS) { drm_via_mem_t mem; - DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t __user *) data, - sizeof(mem)); + DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *) data, sizeof(mem)); switch (mem.type) { diff --git a/trunk/drivers/char/drm/via_video.c b/trunk/drivers/char/drm/via_video.c index 1e2d444587bf..37a61c67b292 100644 --- a/trunk/drivers/char/drm/via_video.c +++ b/trunk/drivers/char/drm/via_video.c @@ -76,8 +76,7 @@ via_decoder_futex(DRM_IOCTL_ARGS) DRM_DEBUG("%s\n", __FUNCTION__); - DRM_COPY_FROM_USER_IOCTL(fx, (drm_via_futex_t __user *) data, - sizeof(fx)); + DRM_COPY_FROM_USER_IOCTL(fx, (drm_via_futex_t *) data, sizeof(fx)); if (fx.lock > VIA_NR_XVMC_LOCKS) return -EFAULT; diff --git a/trunk/drivers/char/ipmi/ipmi_si_intf.c b/trunk/drivers/char/ipmi/ipmi_si_intf.c index a44b97304e95..298574e16061 100644 --- a/trunk/drivers/char/ipmi/ipmi_si_intf.c +++ b/trunk/drivers/char/ipmi/ipmi_si_intf.c @@ -1726,7 +1726,7 @@ static int dmi_table(u32 base, int len, int num) return status; } -static inline int dmi_checksum(u8 *buf) +inline static int dmi_checksum(u8 *buf) { u8 sum=0; int a; diff --git a/trunk/drivers/char/ipmi/ipmi_watchdog.c b/trunk/drivers/char/ipmi/ipmi_watchdog.c index d35a953961cb..fcd1c02a32cb 100644 --- a/trunk/drivers/char/ipmi/ipmi_watchdog.c +++ b/trunk/drivers/char/ipmi/ipmi_watchdog.c @@ -131,7 +131,11 @@ #define WDIOC_GET_PRETIMEOUT _IOW(WATCHDOG_IOCTL_BASE, 22, int) #endif -static int nowayout = WATCHDOG_NOWAYOUT; +#ifdef CONFIG_WATCHDOG_NOWAYOUT +static int nowayout = 1; +#else +static int nowayout; +#endif static ipmi_user_t watchdog_user = NULL; diff --git a/trunk/drivers/char/rio/rioboot.c b/trunk/drivers/char/rio/rioboot.c index 34cbb13aad4b..a8be11dfcba3 100644 --- a/trunk/drivers/char/rio/rioboot.c +++ b/trunk/drivers/char/rio/rioboot.c @@ -902,7 +902,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st (HostP->Mapping[entry].RtaUniqueNum==RtaUniq)) { HostP->Mapping[entry].Flags |= RTA_BOOTED|RTA_NEWBOOT; -#ifdef NEED_TO_FIX +#if NEED_TO_FIX RIO_SV_BROADCAST(HostP->svFlags[entry]); #endif if ( (sysport=HostP->Mapping[entry].SysPort) != NO_PORT ) @@ -918,7 +918,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st { entry2 = HostP->Mapping[entry].ID2 - 1; HostP->Mapping[entry2].Flags |= RTA_BOOTED|RTA_NEWBOOT; -#ifdef NEED_TO_FIX +#if NEED_TO_FIX RIO_SV_BROADCAST(HostP->svFlags[entry2]); #endif sysport = HostP->Mapping[entry2].SysPort; @@ -1143,7 +1143,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st CCOPY( MapP->Name, HostP->Mapping[entry].Name, MAX_NAME_LEN ); HostP->Mapping[entry].Flags = SLOT_IN_USE | RTA_BOOTED | RTA_NEWBOOT; -#ifdef NEED_TO_FIX +#if NEED_TO_FIX RIO_SV_BROADCAST(HostP->svFlags[entry]); #endif RIOReMapPorts( p, HostP, &HostP->Mapping[entry] ); @@ -1159,7 +1159,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st "This RTA has a tentative entry on another host - delete that entry (1)\n"); HostP->Mapping[entry].Flags = SLOT_TENTATIVE | RTA_BOOTED | RTA_NEWBOOT; -#ifdef NEED_TO_FIX +#if NEED_TO_FIX RIO_SV_BROADCAST(HostP->svFlags[entry]); #endif } @@ -1169,7 +1169,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st { HostP->Mapping[entry2].Flags = SLOT_IN_USE | RTA_BOOTED | RTA_NEWBOOT | RTA16_SECOND_SLOT; -#ifdef NEED_TO_FIX +#if NEED_TO_FIX RIO_SV_BROADCAST(HostP->svFlags[entry2]); #endif HostP->Mapping[entry2].SysPort = MapP2->SysPort; @@ -1188,7 +1188,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st else HostP->Mapping[entry2].Flags = SLOT_TENTATIVE | RTA_BOOTED | RTA_NEWBOOT | RTA16_SECOND_SLOT; -#ifdef NEED_TO_FIX +#if NEED_TO_FIX RIO_SV_BROADCAST(HostP->svFlags[entry2]); #endif bzero( (caddr_t)MapP2, sizeof(struct Map) ); diff --git a/trunk/drivers/char/rio/rioroute.c b/trunk/drivers/char/rio/rioroute.c index e9564c9fb37c..106b31f48a21 100644 --- a/trunk/drivers/char/rio/rioroute.c +++ b/trunk/drivers/char/rio/rioroute.c @@ -1023,7 +1023,7 @@ RIOFreeDisconnected(struct rio_info *p, struct Host *HostP, int unit) if (link < LINKS_PER_UNIT) return 1; -#ifdef NEED_TO_FIX_THIS +#if NEED_TO_FIX_THIS /* Ok so all the links are disconnected. But we may have only just ** made this slot tentative and not yet received a topology update. ** Lets check how long ago we made it tentative. diff --git a/trunk/drivers/char/rio/riotable.c b/trunk/drivers/char/rio/riotable.c index e45bc275907a..8fb26ad2aa12 100644 --- a/trunk/drivers/char/rio/riotable.c +++ b/trunk/drivers/char/rio/riotable.c @@ -771,7 +771,7 @@ int RIOAssignRta( struct rio_info *p, struct Map *MapP ) if ((MapP->Flags & RTA16_SECOND_SLOT) == 0) CCOPY( MapP->Name, HostMapP->Name, MAX_NAME_LEN ); HostMapP->Flags = SLOT_IN_USE | RTA_BOOTED; -#ifdef NEED_TO_FIX +#if NEED_TO_FIX RIO_SV_BROADCAST(p->RIOHosts[host].svFlags[MapP->ID-1]); #endif if (MapP->Flags & RTA16_SECOND_SLOT) diff --git a/trunk/drivers/char/tpm/Kconfig b/trunk/drivers/char/tpm/Kconfig index 94a3b3e20bf9..7a969778915a 100644 --- a/trunk/drivers/char/tpm/Kconfig +++ b/trunk/drivers/char/tpm/Kconfig @@ -35,16 +35,5 @@ config TCG_ATMEL will be accessible from within Linux. To compile this driver as a module, choose M here; the module will be called tpm_atmel. -config TCG_INFINEON - tristate "Infineon Technologies SLD 9630 TPM Interface" - depends on TCG_TPM - ---help--- - If you have a TPM security chip from Infineon Technologies - say Yes and it will be accessible from within Linux. To - compile this driver as a module, choose M here; the module - will be called tpm_infineon. - Further information on this driver and the supported hardware - can be found at http://www.prosec.rub.de/tpm - endmenu diff --git a/trunk/drivers/char/tpm/Makefile b/trunk/drivers/char/tpm/Makefile index 2392e404e8d1..736d3df266f5 100644 --- a/trunk/drivers/char/tpm/Makefile +++ b/trunk/drivers/char/tpm/Makefile @@ -4,4 +4,4 @@ obj-$(CONFIG_TCG_TPM) += tpm.o obj-$(CONFIG_TCG_NSC) += tpm_nsc.o obj-$(CONFIG_TCG_ATMEL) += tpm_atmel.o -obj-$(CONFIG_TCG_INFINEON) += tpm_infineon.o + diff --git a/trunk/drivers/char/tpm/tpm_infineon.c b/trunk/drivers/char/tpm/tpm_infineon.c deleted file mode 100644 index 0e3241645c19..000000000000 --- a/trunk/drivers/char/tpm/tpm_infineon.c +++ /dev/null @@ -1,467 +0,0 @@ -/* - * Description: - * Device Driver for the Infineon Technologies - * SLD 9630 TT Trusted Platform Module - * Specifications at www.trustedcomputinggroup.org - * - * Copyright (C) 2005, Marcel Selhorst - * Applied Data Security Group, Ruhr-University Bochum, Germany - * Project-Homepage: http://www.prosec.rub.de/tpm - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation, version 2 of the - * License. - * - */ - -#include "tpm.h" - -/* Infineon specific definitions */ -/* maximum number of WTX-packages */ -#define TPM_MAX_WTX_PACKAGES 50 -/* msleep-Time for WTX-packages */ -#define TPM_WTX_MSLEEP_TIME 20 -/* msleep-Time --> Interval to check status register */ -#define TPM_MSLEEP_TIME 3 -/* gives number of max. msleep()-calls before throwing timeout */ -#define TPM_MAX_TRIES 5000 -#define TCPA_INFINEON_DEV_VEN_VALUE 0x15D1 -#define TPM_DATA (TPM_ADDR + 1) & 0xff - -/* TPM header definitions */ -enum infineon_tpm_header { - TPM_VL_VER = 0x01, - TPM_VL_CHANNEL_CONTROL = 0x07, - TPM_VL_CHANNEL_PERSONALISATION = 0x0A, - TPM_VL_CHANNEL_TPM = 0x0B, - TPM_VL_CONTROL = 0x00, - TPM_INF_NAK = 0x15, - TPM_CTRL_WTX = 0x10, - TPM_CTRL_WTX_ABORT = 0x18, - TPM_CTRL_WTX_ABORT_ACK = 0x18, - TPM_CTRL_ERROR = 0x20, - TPM_CTRL_CHAININGACK = 0x40, - TPM_CTRL_CHAINING = 0x80, - TPM_CTRL_DATA = 0x04, - TPM_CTRL_DATA_CHA = 0x84, - TPM_CTRL_DATA_CHA_ACK = 0xC4 -}; - -enum infineon_tpm_register { - WRFIFO = 0x00, - RDFIFO = 0x01, - STAT = 0x02, - CMD = 0x03 -}; - -enum infineon_tpm_command_bits { - CMD_DIS = 0x00, - CMD_LP = 0x01, - CMD_RES = 0x02, - CMD_IRQC = 0x06 -}; - -enum infineon_tpm_status_bits { - STAT_XFE = 0x00, - STAT_LPA = 0x01, - STAT_FOK = 0x02, - STAT_TOK = 0x03, - STAT_IRQA = 0x06, - STAT_RDA = 0x07 -}; - -/* some outgoing values */ -enum infineon_tpm_values { - CHIP_ID1 = 0x20, - CHIP_ID2 = 0x21, - TPM_DAR = 0x30, - RESET_LP_IRQC_DISABLE = 0x41, - ENABLE_REGISTER_PAIR = 0x55, - IOLIMH = 0x60, - IOLIML = 0x61, - DISABLE_REGISTER_PAIR = 0xAA, - IDVENL = 0xF1, - IDVENH = 0xF2, - IDPDL = 0xF3, - IDPDH = 0xF4 -}; - -static int number_of_wtx; - -static int empty_fifo(struct tpm_chip *chip, int clear_wrfifo) -{ - int status; - int check = 0; - int i; - - if (clear_wrfifo) { - for (i = 0; i < 4096; i++) { - status = inb(chip->vendor->base + WRFIFO); - if (status == 0xff) { - if (check == 5) - break; - else - check++; - } - } - } - /* Note: The values which are currently in the FIFO of the TPM - are thrown away since there is no usage for them. Usually, - this has nothing to say, since the TPM will give its answer - immediately or will be aborted anyway, so the data here is - usually garbage and useless. - We have to clean this, because the next communication with - the TPM would be rubbish, if there is still some old data - in the Read FIFO. - */ - i = 0; - do { - status = inb(chip->vendor->base + RDFIFO); - status = inb(chip->vendor->base + STAT); - i++; - if (i == TPM_MAX_TRIES) - return -EIO; - } while ((status & (1 << STAT_RDA)) != 0); - return 0; -} - -static int wait(struct tpm_chip *chip, int wait_for_bit) -{ - int status; - int i; - for (i = 0; i < TPM_MAX_TRIES; i++) { - status = inb(chip->vendor->base + STAT); - /* check the status-register if wait_for_bit is set */ - if (status & 1 << wait_for_bit) - break; - msleep(TPM_MSLEEP_TIME); - } - if (i == TPM_MAX_TRIES) { /* timeout occurs */ - if (wait_for_bit == STAT_XFE) - dev_err(&chip->pci_dev->dev, - "Timeout in wait(STAT_XFE)\n"); - if (wait_for_bit == STAT_RDA) - dev_err(&chip->pci_dev->dev, - "Timeout in wait(STAT_RDA)\n"); - return -EIO; - } - return 0; -}; - -static void wait_and_send(struct tpm_chip *chip, u8 sendbyte) -{ - wait(chip, STAT_XFE); - outb(sendbyte, chip->vendor->base + WRFIFO); -} - - /* Note: WTX means Waiting-Time-Extension. Whenever the TPM needs more - calculation time, it sends a WTX-package, which has to be acknowledged - or aborted. This usually occurs if you are hammering the TPM with key - creation. Set the maximum number of WTX-packages in the definitions - above, if the number is reached, the waiting-time will be denied - and the TPM command has to be resend. - */ - -static void tpm_wtx(struct tpm_chip *chip) -{ - number_of_wtx++; - dev_info(&chip->pci_dev->dev, "Granting WTX (%02d / %02d)\n", - number_of_wtx, TPM_MAX_WTX_PACKAGES); - wait_and_send(chip, TPM_VL_VER); - wait_and_send(chip, TPM_CTRL_WTX); - wait_and_send(chip, 0x00); - wait_and_send(chip, 0x00); - msleep(TPM_WTX_MSLEEP_TIME); -} - -static void tpm_wtx_abort(struct tpm_chip *chip) -{ - dev_info(&chip->pci_dev->dev, "Aborting WTX\n"); - wait_and_send(chip, TPM_VL_VER); - wait_and_send(chip, TPM_CTRL_WTX_ABORT); - wait_and_send(chip, 0x00); - wait_and_send(chip, 0x00); - number_of_wtx = 0; - msleep(TPM_WTX_MSLEEP_TIME); -} - -static int tpm_inf_recv(struct tpm_chip *chip, u8 * buf, size_t count) -{ - int i; - int ret; - u32 size = 0; - -recv_begin: - /* start receiving header */ - for (i = 0; i < 4; i++) { - ret = wait(chip, STAT_RDA); - if (ret) - return -EIO; - buf[i] = inb(chip->vendor->base + RDFIFO); - } - - if (buf[0] != TPM_VL_VER) { - dev_err(&chip->pci_dev->dev, - "Wrong transport protocol implementation!\n"); - return -EIO; - } - - if (buf[1] == TPM_CTRL_DATA) { - /* size of the data received */ - size = ((buf[2] << 8) | buf[3]); - - for (i = 0; i < size; i++) { - wait(chip, STAT_RDA); - buf[i] = inb(chip->vendor->base + RDFIFO); - } - - if ((size == 0x6D00) && (buf[1] == 0x80)) { - dev_err(&chip->pci_dev->dev, - "Error handling on vendor layer!\n"); - return -EIO; - } - - for (i = 0; i < size; i++) - buf[i] = buf[i + 6]; - - size = size - 6; - return size; - } - - if (buf[1] == TPM_CTRL_WTX) { - dev_info(&chip->pci_dev->dev, "WTX-package received\n"); - if (number_of_wtx < TPM_MAX_WTX_PACKAGES) { - tpm_wtx(chip); - goto recv_begin; - } else { - tpm_wtx_abort(chip); - goto recv_begin; - } - } - - if (buf[1] == TPM_CTRL_WTX_ABORT_ACK) { - dev_info(&chip->pci_dev->dev, "WTX-abort acknowledged\n"); - return size; - } - - if (buf[1] == TPM_CTRL_ERROR) { - dev_err(&chip->pci_dev->dev, "ERROR-package received:\n"); - if (buf[4] == TPM_INF_NAK) - dev_err(&chip->pci_dev->dev, - "-> Negative acknowledgement" - " - retransmit command!\n"); - return -EIO; - } - return -EIO; -} - -static int tpm_inf_send(struct tpm_chip *chip, u8 * buf, size_t count) -{ - int i; - int ret; - u8 count_high, count_low, count_4, count_3, count_2, count_1; - - /* Disabling Reset, LP and IRQC */ - outb(RESET_LP_IRQC_DISABLE, chip->vendor->base + CMD); - - ret = empty_fifo(chip, 1); - if (ret) { - dev_err(&chip->pci_dev->dev, "Timeout while clearing FIFO\n"); - return -EIO; - } - - ret = wait(chip, STAT_XFE); - if (ret) - return -EIO; - - count_4 = (count & 0xff000000) >> 24; - count_3 = (count & 0x00ff0000) >> 16; - count_2 = (count & 0x0000ff00) >> 8; - count_1 = (count & 0x000000ff); - count_high = ((count + 6) & 0xffffff00) >> 8; - count_low = ((count + 6) & 0x000000ff); - - /* Sending Header */ - wait_and_send(chip, TPM_VL_VER); - wait_and_send(chip, TPM_CTRL_DATA); - wait_and_send(chip, count_high); - wait_and_send(chip, count_low); - - /* Sending Data Header */ - wait_and_send(chip, TPM_VL_VER); - wait_and_send(chip, TPM_VL_CHANNEL_TPM); - wait_and_send(chip, count_4); - wait_and_send(chip, count_3); - wait_and_send(chip, count_2); - wait_and_send(chip, count_1); - - /* Sending Data */ - for (i = 0; i < count; i++) { - wait_and_send(chip, buf[i]); - } - return count; -} - -static void tpm_inf_cancel(struct tpm_chip *chip) -{ - /* Nothing yet! - This has something to do with the internal functions - of the TPM. Abort isn't really necessary... - */ -} - -static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL); -static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL); -static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL); -static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel); - -static struct attribute *inf_attrs[] = { - &dev_attr_pubek.attr, - &dev_attr_pcrs.attr, - &dev_attr_caps.attr, - &dev_attr_cancel.attr, - NULL, -}; - -static struct attribute_group inf_attr_grp = {.attrs = inf_attrs }; - -static struct file_operations inf_ops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .open = tpm_open, - .read = tpm_read, - .write = tpm_write, - .release = tpm_release, -}; - -static struct tpm_vendor_specific tpm_inf = { - .recv = tpm_inf_recv, - .send = tpm_inf_send, - .cancel = tpm_inf_cancel, - .req_complete_mask = 0, - .req_complete_val = 0, - .attr_group = &inf_attr_grp, - .miscdev = {.fops = &inf_ops,}, -}; - -static int __devinit tpm_inf_probe(struct pci_dev *pci_dev, - const struct pci_device_id *pci_id) -{ - int rc = 0; - u8 iol, ioh; - int vendorid[2]; - int version[2]; - int productid[2]; - - if (pci_enable_device(pci_dev)) - return -EIO; - - dev_info(&pci_dev->dev, "LPC-bus found at 0x%x\n", pci_id->device); - - /* query chip for its vendor, its version number a.s.o. */ - outb(ENABLE_REGISTER_PAIR, TPM_ADDR); - outb(IDVENL, TPM_ADDR); - vendorid[1] = inb(TPM_DATA); - outb(IDVENH, TPM_ADDR); - vendorid[0] = inb(TPM_DATA); - outb(IDPDL, TPM_ADDR); - productid[1] = inb(TPM_DATA); - outb(IDPDH, TPM_ADDR); - productid[0] = inb(TPM_DATA); - outb(CHIP_ID1, TPM_ADDR); - version[1] = inb(TPM_DATA); - outb(CHIP_ID2, TPM_ADDR); - version[0] = inb(TPM_DATA); - - if ((vendorid[0] << 8 | vendorid[1]) == (TCPA_INFINEON_DEV_VEN_VALUE)) { - - /* read IO-ports from TPM */ - outb(IOLIMH, TPM_ADDR); - ioh = inb(TPM_DATA); - outb(IOLIML, TPM_ADDR); - iol = inb(TPM_DATA); - tpm_inf.base = (ioh << 8) | iol; - - if (tpm_inf.base == 0) { - dev_err(&pci_dev->dev, "No IO-ports set!\n"); - pci_disable_device(pci_dev); - return -ENODEV; - } - - /* activate register */ - outb(TPM_DAR, TPM_ADDR); - outb(0x01, TPM_DATA); - outb(DISABLE_REGISTER_PAIR, TPM_ADDR); - - /* disable RESET, LP and IRQC */ - outb(RESET_LP_IRQC_DISABLE, tpm_inf.base + CMD); - - /* Finally, we're done, print some infos */ - dev_info(&pci_dev->dev, "TPM found: " - "io base 0x%x, " - "chip version %02x%02x, " - "vendor id %x%x (Infineon), " - "product id %02x%02x" - "%s\n", - tpm_inf.base, - version[0], version[1], - vendorid[0], vendorid[1], - productid[0], productid[1], ((productid[0] == 0) - && (productid[1] == - 6)) ? - " (SLD 9630 TT 1.1)" : ""); - - rc = tpm_register_hardware(pci_dev, &tpm_inf); - if (rc < 0) { - pci_disable_device(pci_dev); - return -ENODEV; - } - return 0; - } else { - dev_info(&pci_dev->dev, "No Infineon TPM found!\n"); - pci_disable_device(pci_dev); - return -ENODEV; - } -} - -static struct pci_device_id tpm_pci_tbl[] __devinitdata = { - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0)}, - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12)}, - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0)}, - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12)}, - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0)}, - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0)}, - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1)}, - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_2)}, - {0,} -}; - -MODULE_DEVICE_TABLE(pci, tpm_pci_tbl); - -static struct pci_driver inf_pci_driver = { - .name = "tpm_inf", - .id_table = tpm_pci_tbl, - .probe = tpm_inf_probe, - .remove = __devexit_p(tpm_remove), - .suspend = tpm_pm_suspend, - .resume = tpm_pm_resume, -}; - -static int __init init_inf(void) -{ - return pci_register_driver(&inf_pci_driver); -} - -static void __exit cleanup_inf(void) -{ - pci_unregister_driver(&inf_pci_driver); -} - -module_init(init_inf); -module_exit(cleanup_inf); - -MODULE_AUTHOR("Marcel Selhorst "); -MODULE_DESCRIPTION("Driver for Infineon TPM SLD 9630 TT"); -MODULE_VERSION("1.4"); -MODULE_LICENSE("GPL"); diff --git a/trunk/drivers/char/watchdog/acquirewdt.c b/trunk/drivers/char/watchdog/acquirewdt.c index 7289f4af93d0..8f302121741b 100644 --- a/trunk/drivers/char/watchdog/acquirewdt.c +++ b/trunk/drivers/char/watchdog/acquirewdt.c @@ -82,7 +82,12 @@ static int wdt_start = 0x443; module_param(wdt_start, int, 0); MODULE_PARM_DESC(wdt_start, "Acquire WDT 'start' io port (default 0x443)"); -static int nowayout = WATCHDOG_NOWAYOUT; +#ifdef CONFIG_WATCHDOG_NOWAYOUT +static int nowayout = 1; +#else +static int nowayout = 0; +#endif + module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)"); diff --git a/trunk/drivers/char/watchdog/advantechwdt.c b/trunk/drivers/char/watchdog/advantechwdt.c index 194a3fd36b91..ea73c8379bdd 100644 --- a/trunk/drivers/char/watchdog/advantechwdt.c +++ b/trunk/drivers/char/watchdog/advantechwdt.c @@ -73,7 +73,12 @@ static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ module_param(timeout, int, 0); MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=63, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) "."); -static int nowayout = WATCHDOG_NOWAYOUT; +#ifdef CONFIG_WATCHDOG_NOWAYOUT +static int nowayout = 1; +#else +static int nowayout = 0; +#endif + module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)"); diff --git a/trunk/drivers/char/watchdog/alim1535_wdt.c b/trunk/drivers/char/watchdog/alim1535_wdt.c index 8338ca300e2e..35dcbf8be7d1 100644 --- a/trunk/drivers/char/watchdog/alim1535_wdt.c +++ b/trunk/drivers/char/watchdog/alim1535_wdt.c @@ -38,7 +38,12 @@ static int timeout = WATCHDOG_TIMEOUT; module_param(timeout, int, 0); MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (0 #include -static int nowayout = WATCHDOG_NOWAYOUT; +#ifdef CONFIG_WATCHDOG_NOWAYOUT +static int nowayout = 1; +#else +static int nowayout = 0; +#endif static unsigned int heartbeat = 60; /* (secs) Default is 1 minute */ static unsigned long wdt_status; diff --git a/trunk/drivers/char/watchdog/ixp4xx_wdt.c b/trunk/drivers/char/watchdog/ixp4xx_wdt.c index 8d916afbf4fa..83df369113a4 100644 --- a/trunk/drivers/char/watchdog/ixp4xx_wdt.c +++ b/trunk/drivers/char/watchdog/ixp4xx_wdt.c @@ -27,7 +27,11 @@ #include #include -static int nowayout = WATCHDOG_NOWAYOUT; +#ifdef CONFIG_WATCHDOG_NOWAYOUT +static int nowayout = 1; +#else +static int nowayout = 0; +#endif static int heartbeat = 60; /* (secs) Default is 1 minute */ static unsigned long wdt_status; static unsigned long boot_status; diff --git a/trunk/drivers/char/watchdog/machzwd.c b/trunk/drivers/char/watchdog/machzwd.c index a9a20aad61e7..9da395fa7794 100644 --- a/trunk/drivers/char/watchdog/machzwd.c +++ b/trunk/drivers/char/watchdog/machzwd.c @@ -94,7 +94,12 @@ MODULE_DESCRIPTION("MachZ ZF-Logic Watchdog driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -static int nowayout = WATCHDOG_NOWAYOUT; +#ifdef CONFIG_WATCHDOG_NOWAYOUT +static int nowayout = 1; +#else +static int nowayout = 0; +#endif + module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)"); diff --git a/trunk/drivers/char/watchdog/mixcomwd.c b/trunk/drivers/char/watchdog/mixcomwd.c index c9b301dccec3..3143e4a07535 100644 --- a/trunk/drivers/char/watchdog/mixcomwd.c +++ b/trunk/drivers/char/watchdog/mixcomwd.c @@ -62,7 +62,12 @@ static int mixcomwd_timer_alive; static struct timer_list mixcomwd_timer = TIMER_INITIALIZER(NULL, 0, 0); static char expect_close; -static int nowayout = WATCHDOG_NOWAYOUT; +#ifdef CONFIG_WATCHDOG_NOWAYOUT +static int nowayout = 1; +#else +static int nowayout = 0; +#endif + module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)"); diff --git a/trunk/drivers/char/watchdog/pcwd.c b/trunk/drivers/char/watchdog/pcwd.c index 427ad51b7a35..6ebce3f2ef9c 100644 --- a/trunk/drivers/char/watchdog/pcwd.c +++ b/trunk/drivers/char/watchdog/pcwd.c @@ -146,7 +146,12 @@ static int heartbeat = WATCHDOG_HEARTBEAT; module_param(heartbeat, int, 0); MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<=heartbeat<=7200, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); -static int nowayout = WATCHDOG_NOWAYOUT; +#ifdef CONFIG_WATCHDOG_NOWAYOUT +static int nowayout = 1; +#else +static int nowayout = 0; +#endif + module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)"); diff --git a/trunk/drivers/char/watchdog/pcwd_pci.c b/trunk/drivers/char/watchdog/pcwd_pci.c index 2b13afb09c5d..8ce066627326 100644 --- a/trunk/drivers/char/watchdog/pcwd_pci.c +++ b/trunk/drivers/char/watchdog/pcwd_pci.c @@ -103,7 +103,12 @@ static int heartbeat = WATCHDOG_HEARTBEAT; module_param(heartbeat, int, 0); MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (0dev.platform_data; - - if (!(i2c = kmalloc(sizeof(*i2c), GFP_KERNEL))) { - return -ENOMEM; - } - memset(i2c, 0, sizeof(*i2c)); - - i2c->irq = platform_get_irq(pdev, 0); - i2c->flags = pdata->device_flags; - init_waitqueue_head(&i2c->queue); - - i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION); - - if (!i2c->base) { - printk(KERN_ERR "i2c-mpc - failed to map controller\n"); - result = -ENOMEM; - goto fail_map; - } - - if (i2c->irq != 0) - if ((result = request_irq(i2c->irq, mpc_i2c_isr, - SA_SHIRQ, "i2c-mpc", i2c)) < 0) { - printk(KERN_ERR - "i2c-mpc - failed to attach interrupt\n"); - goto fail_irq; - } - - mpc_i2c_setclock(i2c); - dev_set_drvdata(device, i2c); - - i2c->adap = mpc_ops; - i2c_set_adapdata(&i2c->adap, i2c); - i2c->adap.dev.parent = &pdev->dev; - if ((result = i2c_add_adapter(&i2c->adap)) < 0) { - printk(KERN_ERR "i2c-mpc - failed to add adapter\n"); - goto fail_add; - } - - return result; - - fail_add: - if (i2c->irq != 0) - free_irq(i2c->irq, NULL); - fail_irq: - iounmap(i2c->base); - fail_map: - kfree(i2c); - return result; -}; - -static int fsl_i2c_remove(struct device *device) -{ - struct mpc_i2c *i2c = dev_get_drvdata(device); - - i2c_del_adapter(&i2c->adap); - dev_set_drvdata(device, NULL); - - if (i2c->irq != 0) - free_irq(i2c->irq, i2c); - - iounmap(i2c->base); - kfree(i2c); - return 0; -}; - -/* Structure for a device driver */ -static struct device_driver fsl_i2c_driver = { - .name = "fsl-i2c", - .bus = &platform_bus_type, - .probe = fsl_i2c_probe, - .remove = fsl_i2c_remove, -}; - -static int __init fsl_i2c_init(void) -{ - return driver_register(&fsl_i2c_driver); -} - -static void __exit fsl_i2c_exit(void) -{ - driver_unregister(&fsl_i2c_driver); -} - -module_init(fsl_i2c_init); -module_exit(fsl_i2c_exit); - MODULE_AUTHOR("Adrian Cox "); MODULE_DESCRIPTION ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors"); diff --git a/trunk/drivers/ide/cris/Makefile b/trunk/drivers/ide/cris/Makefile index 6176e8d6b2e6..fdc294325d00 100644 --- a/trunk/drivers/ide/cris/Makefile +++ b/trunk/drivers/ide/cris/Makefile @@ -1,3 +1,3 @@ EXTRA_CFLAGS += -Idrivers/ide -obj-y += ide-cris.o +obj-$(CONFIG_ETRAX_ARCH_V10) += ide-v10.o diff --git a/trunk/drivers/ide/cris/ide-cris.c b/trunk/drivers/ide/cris/ide-cris.c deleted file mode 100644 index cd15e6260510..000000000000 --- a/trunk/drivers/ide/cris/ide-cris.c +++ /dev/null @@ -1,1107 +0,0 @@ -/* $Id: cris-ide-driver.patch,v 1.1 2005/06/29 21:39:07 akpm Exp $ - * - * Etrax specific IDE functions, like init and PIO-mode setting etc. - * Almost the entire ide.c is used for the rest of the Etrax ATA driver. - * Copyright (c) 2000-2005 Axis Communications AB - * - * Authors: Bjorn Wesen (initial version) - * Mikael Starvik (crisv32 port) - */ - -/* Regarding DMA: - * - * There are two forms of DMA - "DMA handshaking" between the interface and the drive, - * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's - * something built-in in the Etrax. However only some drives support the DMA-mode handshaking - * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the - * device can't do DMA handshaking for some stupid reason. We don't need to do that. - */ - -#undef REALLY_SLOW_IO /* most systems can safely undef this */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/* number of DMA descriptors */ -#define MAX_DMA_DESCRS 64 - -/* number of times to retry busy-flags when reading/writing IDE-registers - * this can't be too high because a hung harddisk might cause the watchdog - * to trigger (sometimes INB and OUTB are called with irq's disabled) - */ - -#define IDE_REGISTER_TIMEOUT 300 - -#define LOWDB(x) -#define D(x) - -enum /* Transfer types */ -{ - TYPE_PIO, - TYPE_DMA, - TYPE_UDMA -}; - -/* CRISv32 specifics */ -#ifdef CONFIG_ETRAX_ARCH_V32 -#include -#include -#include -#include - -#define ATA_UDMA2_CYC 2 -#define ATA_UDMA2_DVS 3 -#define ATA_UDMA1_CYC 2 -#define ATA_UDMA1_DVS 4 -#define ATA_UDMA0_CYC 4 -#define ATA_UDMA0_DVS 6 -#define ATA_DMA2_STROBE 7 -#define ATA_DMA2_HOLD 1 -#define ATA_DMA1_STROBE 8 -#define ATA_DMA1_HOLD 3 -#define ATA_DMA0_STROBE 25 -#define ATA_DMA0_HOLD 19 -#define ATA_PIO4_SETUP 3 -#define ATA_PIO4_STROBE 7 -#define ATA_PIO4_HOLD 1 -#define ATA_PIO3_SETUP 3 -#define ATA_PIO3_STROBE 9 -#define ATA_PIO3_HOLD 3 -#define ATA_PIO2_SETUP 3 -#define ATA_PIO2_STROBE 13 -#define ATA_PIO2_HOLD 5 -#define ATA_PIO1_SETUP 5 -#define ATA_PIO1_STROBE 23 -#define ATA_PIO1_HOLD 9 -#define ATA_PIO0_SETUP 9 -#define ATA_PIO0_STROBE 39 -#define ATA_PIO0_HOLD 9 - -int -cris_ide_ack_intr(ide_hwif_t* hwif) -{ - reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, - int, hwif->io_ports[0]); - REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel); - return 1; -} - -static inline int -cris_ide_busy(void) -{ - reg_ata_rs_stat_data stat_data; - stat_data = REG_RD(ata, regi_ata, rs_stat_data); - return stat_data.busy; -} - -static inline int -cris_ide_ready(void) -{ - return !cris_ide_busy(); -} - -static inline int -cris_ide_data_available(unsigned short* data) -{ - reg_ata_rs_stat_data stat_data; - stat_data = REG_RD(ata, regi_ata, rs_stat_data); - *data = stat_data.data; - return stat_data.dav; -} - -static void -cris_ide_write_command(unsigned long command) -{ - REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */ -} - -static void -cris_ide_set_speed(int type, int setup, int strobe, int hold) -{ - reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); - reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); - - if (type == TYPE_PIO) { - ctrl0.pio_setup = setup; - ctrl0.pio_strb = strobe; - ctrl0.pio_hold = hold; - } else if (type == TYPE_DMA) { - ctrl0.dma_strb = strobe; - ctrl0.dma_hold = hold; - } else if (type == TYPE_UDMA) { - ctrl1.udma_tcyc = setup; - ctrl1.udma_tdvs = strobe; - } - REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); - REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); -} - -static unsigned long -cris_ide_base_address(int bus) -{ - reg_ata_rw_ctrl2 ctrl2 = {0}; - ctrl2.sel = bus; - return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2); -} - -static unsigned long -cris_ide_reg_addr(unsigned long addr, int cs0, int cs1) -{ - reg_ata_rw_ctrl2 ctrl2 = {0}; - ctrl2.addr = addr; - ctrl2.cs1 = cs1; - ctrl2.cs0 = cs0; - return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2); -} - -static __init void -cris_ide_reset(unsigned val) -{ - reg_ata_rw_ctrl0 ctrl0 = {0}; - ctrl0.rst = val ? regk_ata_active : regk_ata_inactive; - REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); -} - -static __init void -cris_ide_init(void) -{ - reg_ata_rw_ctrl0 ctrl0 = {0}; - reg_ata_rw_intr_mask intr_mask = {0}; - - ctrl0.en = regk_ata_yes; - REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); - - intr_mask.bus0 = regk_ata_yes; - intr_mask.bus1 = regk_ata_yes; - intr_mask.bus2 = regk_ata_yes; - intr_mask.bus3 = regk_ata_yes; - - REG_WR(ata, regi_ata, rw_intr_mask, intr_mask); - - crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata); - crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata); - - crisv32_pinmux_alloc_fixed(pinmux_ata); - crisv32_pinmux_alloc_fixed(pinmux_ata0); - crisv32_pinmux_alloc_fixed(pinmux_ata1); - crisv32_pinmux_alloc_fixed(pinmux_ata2); - crisv32_pinmux_alloc_fixed(pinmux_ata3); - - DMA_RESET(regi_dma2); - DMA_ENABLE(regi_dma2); - DMA_RESET(regi_dma3); - DMA_ENABLE(regi_dma3); - - DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2); - DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2); -} - -static dma_descr_context mycontext __attribute__ ((__aligned__(32))); - -#define cris_dma_descr_type dma_descr_data -#define cris_pio_read regk_ata_rd -#define cris_ultra_mask 0x7 -#define MAX_DESCR_SIZE 0xffffffffUL - -static unsigned long -cris_ide_get_reg(unsigned long reg) -{ - return (reg & 0x0e000000) >> 25; -} - -static void -cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last) -{ - d->buf = (char*)virt_to_phys(buf); - d->after = d->buf + len; - d->eol = last; -} - -static void -cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len) -{ - reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); - reg_ata_rw_trf_cnt trf_cnt = {0}; - - mycontext.saved_data = (dma_descr_data*)virt_to_phys(d); - mycontext.saved_data_buf = d->buf; - /* start the dma channel */ - DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext)); - - /* initiate a multi word dma read using PIO handshaking */ - trf_cnt.cnt = len >> 1; - /* Due to a "feature" the transfer count has to be one extra word for UDMA. */ - if (type == TYPE_UDMA) - trf_cnt.cnt++; - REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt); - - ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr; - ctrl2.trf_mode = regk_ata_dma; - ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio : - type == TYPE_DMA ? regk_ata_dma : regk_ata_udma; - ctrl2.multi = regk_ata_yes; - ctrl2.dma_size = regk_ata_word; - REG_WR(ata, regi_ata, rw_ctrl2, ctrl2); -} - -static void -cris_ide_wait_dma(int dir) -{ - reg_dma_rw_stat status; - do - { - status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat); - } while(status.list_state != regk_dma_data_at_eol); -} - -static int cris_dma_test_irq(ide_drive_t *drive) -{ - int intr = REG_RD_INT(ata, regi_ata, r_intr); - reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); - return intr & (1 << ctrl2.sel) ? 1 : 0; -} - -static void cris_ide_initialize_dma(int dir) -{ -} - -#else -/* CRISv10 specifics */ -#include -#include - -/* PIO timing (in R_ATA_CONFIG) - * - * _____________________________ - * ADDRESS : ________/ - * - * _______________ - * DIOR : ____________/ \__________ - * - * _______________ - * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX - * - * - * DIOR is unbuffered while address and data is buffered. - * This creates two problems: - * 1. The DIOR pulse is to early (because it is unbuffered) - * 2. The rise time of DIOR is long - * - * There are at least three different plausible solutions - * 1. Use a pad capable of larger currents in Etrax - * 2. Use an external buffer - * 3. Make the strobe pulse longer - * - * Some of the strobe timings below are modified to compensate - * for this. This implies a slight performance decrease. - * - * THIS SHOULD NEVER BE CHANGED! - * - * TODO: Is this true for the latest LX boards still ? - */ - -#define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */ -#define ATA_UDMA2_DVS 0 -#define ATA_UDMA1_CYC 0 -#define ATA_UDMA1_DVS 0 -#define ATA_UDMA0_CYC 0 -#define ATA_UDMA0_DVS 0 -#define ATA_DMA2_STROBE 4 -#define ATA_DMA2_HOLD 0 -#define ATA_DMA1_STROBE 4 -#define ATA_DMA1_HOLD 1 -#define ATA_DMA0_STROBE 12 -#define ATA_DMA0_HOLD 9 -#define ATA_PIO4_SETUP 1 -#define ATA_PIO4_STROBE 5 -#define ATA_PIO4_HOLD 0 -#define ATA_PIO3_SETUP 1 -#define ATA_PIO3_STROBE 5 -#define ATA_PIO3_HOLD 1 -#define ATA_PIO2_SETUP 1 -#define ATA_PIO2_STROBE 6 -#define ATA_PIO2_HOLD 2 -#define ATA_PIO1_SETUP 2 -#define ATA_PIO1_STROBE 11 -#define ATA_PIO1_HOLD 4 -#define ATA_PIO0_SETUP 4 -#define ATA_PIO0_STROBE 19 -#define ATA_PIO0_HOLD 4 - -int -cris_ide_ack_intr(ide_hwif_t* hwif) -{ - return 1; -} - -static inline int -cris_ide_busy(void) -{ - return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ; -} - -static inline int -cris_ide_ready(void) -{ - return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ; -} - -static inline int -cris_ide_data_available(unsigned short* data) -{ - unsigned long status = *R_ATA_STATUS_DATA; - *data = (unsigned short)status; - return status & IO_MASK(R_ATA_STATUS_DATA, dav); -} - -static void -cris_ide_write_command(unsigned long command) -{ - *R_ATA_CTRL_DATA = command; -} - -static void -cris_ide_set_speed(int type, int setup, int strobe, int hold) -{ - static int pio_setup = ATA_PIO4_SETUP; - static int pio_strobe = ATA_PIO4_STROBE; - static int pio_hold = ATA_PIO4_HOLD; - static int dma_strobe = ATA_DMA2_STROBE; - static int dma_hold = ATA_DMA2_HOLD; - - if (type == TYPE_PIO) { - pio_setup = setup; - pio_strobe = strobe; - pio_hold = hold; - } else if (type == TYPE_DMA) { - dma_strobe = strobe; - dma_hold = hold; - } - *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | - IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) | - IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) | - IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) | - IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) | - IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) ); -} - -static unsigned long -cris_ide_base_address(int bus) -{ - return IO_FIELD(R_ATA_CTRL_DATA, sel, bus); -} - -static unsigned long -cris_ide_reg_addr(unsigned long addr, int cs0, int cs1) -{ - return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) | - IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) | - IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1); -} - -static __init void -cris_ide_reset(unsigned val) -{ -#ifdef CONFIG_ETRAX_IDE_G27_RESET - REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val); -#endif -#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET - REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, val); -#endif -#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, val); -#endif -#ifdef CONFIG_ETRAX_IDE_PB7_RESET - port_pb_dir_shadow = port_pb_dir_shadow | - IO_STATE(R_PORT_PB_DIR, dir7, output); - *R_PORT_PB_DIR = port_pb_dir_shadow; - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val); -#endif -} - -static __init void -cris_ide_init(void) -{ - volatile unsigned int dummy; - - *R_ATA_CTRL_DATA = 0; - *R_ATA_TRANSFER_CNT = 0; - *R_ATA_CONFIG = 0; - - if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) { - printk(KERN_CRIT "ide: Failed to get IO interface\n"); - return; - } else if (cris_request_dma(ATA_TX_DMA_NBR, - "ETRAX100LX IDE TX", - DMA_VERBOSE_ON_ERROR, - dma_ata)) { - cris_free_io_interface(if_ata); - printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n"); - return; - } else if (cris_request_dma(ATA_RX_DMA_NBR, - "ETRAX100LX IDE RX", - DMA_VERBOSE_ON_ERROR, - dma_ata)) { - cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx"); - cris_free_io_interface(if_ata); - printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n"); - return; - } - - /* make a dummy read to set the ata controller in a proper state */ - dummy = *R_ATA_STATUS_DATA; - - *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 )); - *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) | - IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) ); - - while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/ - - *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) | - IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) | - IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) | - IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) ); - - /* reset the dma channels we will use */ - - RESET_DMA(ATA_TX_DMA_NBR); - RESET_DMA(ATA_RX_DMA_NBR); - WAIT_DMA(ATA_TX_DMA_NBR); - WAIT_DMA(ATA_RX_DMA_NBR); -} - -#define cris_dma_descr_type etrax_dma_descr -#define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read) -#define cris_ultra_mask 0x0 -#define MAX_DESCR_SIZE 0x10000UL - -static unsigned long -cris_ide_get_reg(unsigned long reg) -{ - return (reg & 0x0e000000) >> 25; -} - -static void -cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last) -{ - d->buf = virt_to_phys(buf); - d->sw_len = len == MAX_DESCR_SIZE ? 0 : len; - if (last) - d->ctrl |= d_eol; -} - -static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len) -{ - unsigned long cmd; - - if (dir) { - /* need to do this before RX DMA due to a chip bug - * it is enough to just flush the part of the cache that - * corresponds to the buffers we start, but since HD transfers - * usually are more than 8 kB, it is easier to optimize for the - * normal case and just flush the entire cache. its the only - * way to be sure! (OB movie quote) - */ - flush_etrax_cache(); - *R_DMA_CH3_FIRST = virt_to_phys(d); - *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start); - - } else { - *R_DMA_CH2_FIRST = virt_to_phys(d); - *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start); - } - - /* initiate a multi word dma read using DMA handshaking */ - - *R_ATA_TRANSFER_CNT = - IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1); - - cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write); - cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) : - IO_STATE(R_ATA_CTRL_DATA, handsh, dma); - *R_ATA_CTRL_DATA = - cmd | - IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) | - IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | - IO_STATE(R_ATA_CTRL_DATA, multi, on) | - IO_STATE(R_ATA_CTRL_DATA, dma_size, word); -} - -static void -cris_ide_wait_dma(int dir) -{ - if (dir) - WAIT_DMA(ATA_RX_DMA_NBR); - else - WAIT_DMA(ATA_TX_DMA_NBR); -} - -static int cris_dma_test_irq(ide_drive_t *drive) -{ - int intr = *R_IRQ_MASK0_RD; - int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, IDE_DATA_REG); - return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0; -} - - -static void cris_ide_initialize_dma(int dir) -{ - if (dir) - { - RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */ - WAIT_DMA(ATA_RX_DMA_NBR); - } - else - { - RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */ - WAIT_DMA(ATA_TX_DMA_NBR); - } -} - -#endif - -void -cris_ide_outw(unsigned short data, unsigned long reg) { - int timeleft; - - LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg)); - - /* note the lack of handling any timeouts. we stop waiting, but we don't - * really notify anybody. - */ - - timeleft = IDE_REGISTER_TIMEOUT; - /* wait for busy flag */ - do { - timeleft--; - } while(timeleft && cris_ide_busy()); - - /* - * Fall through at a timeout, so the ongoing command will be - * aborted by the write below, which is expected to be a dummy - * command to the command register. This happens when a faulty - * drive times out on a command. See comment on timeout in - * INB. - */ - if(!timeleft) - printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data); - - cris_ide_write_command(reg|data); /* write data to the drive's register */ - - timeleft = IDE_REGISTER_TIMEOUT; - /* wait for transmitter ready */ - do { - timeleft--; - } while(timeleft && !cris_ide_ready()); -} - -void -cris_ide_outb(unsigned char data, unsigned long reg) -{ - cris_ide_outw(data, reg); -} - -void -cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port) -{ - cris_ide_outw(addr, port); -} - -unsigned short -cris_ide_inw(unsigned long reg) { - int timeleft; - unsigned short val; - - timeleft = IDE_REGISTER_TIMEOUT; - /* wait for busy flag */ - do { - timeleft--; - } while(timeleft && cris_ide_busy()); - - if(!timeleft) { - /* - * If we're asked to read the status register, like for - * example when a command does not complete for an - * extended time, but the ATA interface is stuck in a - * busy state at the *ETRAX* ATA interface level (as has - * happened repeatedly with at least one bad disk), then - * the best thing to do is to pretend that we read - * "busy" in the status register, so the IDE driver will - * time-out, abort the ongoing command and perform a - * reset sequence. Note that the subsequent OUT_BYTE - * call will also timeout on busy, but as long as the - * write is still performed, everything will be fine. - */ - if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET) - return BUSY_STAT; - else - /* For other rare cases we assume 0 is good enough. */ - return 0; - } - - cris_ide_write_command(reg | cris_pio_read); - - timeleft = IDE_REGISTER_TIMEOUT; - /* wait for available */ - do { - timeleft--; - } while(timeleft && !cris_ide_data_available(&val)); - - if(!timeleft) - return 0; - - LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg)); - - return val; -} - -unsigned char -cris_ide_inb(unsigned long reg) -{ - return (unsigned char)cris_ide_inw(reg); -} - -static int cris_dma_check (ide_drive_t *drive); -static int cris_dma_end (ide_drive_t *drive); -static int cris_dma_setup (ide_drive_t *drive); -static void cris_dma_exec_cmd (ide_drive_t *drive, u8 command); -static int cris_dma_test_irq(ide_drive_t *drive); -static void cris_dma_start(ide_drive_t *drive); -static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int); -static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int); -static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int); -static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int); -static int cris_dma_off (ide_drive_t *drive); -static int cris_dma_on (ide_drive_t *drive); - -static void tune_cris_ide(ide_drive_t *drive, u8 pio) -{ - int setup, strobe, hold; - - switch(pio) - { - case 0: - setup = ATA_PIO0_SETUP; - strobe = ATA_PIO0_STROBE; - hold = ATA_PIO0_HOLD; - break; - case 1: - setup = ATA_PIO1_SETUP; - strobe = ATA_PIO1_STROBE; - hold = ATA_PIO1_HOLD; - break; - case 2: - setup = ATA_PIO2_SETUP; - strobe = ATA_PIO2_STROBE; - hold = ATA_PIO2_HOLD; - break; - case 3: - setup = ATA_PIO3_SETUP; - strobe = ATA_PIO3_STROBE; - hold = ATA_PIO3_HOLD; - break; - case 4: - setup = ATA_PIO4_SETUP; - strobe = ATA_PIO4_STROBE; - hold = ATA_PIO4_HOLD; - break; - default: - return; - } - - cris_ide_set_speed(TYPE_PIO, setup, strobe, hold); -} - -static int speed_cris_ide(ide_drive_t *drive, u8 speed) -{ - int cyc = 0, dvs = 0, strobe = 0, hold = 0; - - if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) { - tune_cris_ide(drive, speed - XFER_PIO_0); - return 0; - } - - switch(speed) - { - case XFER_UDMA_0: - cyc = ATA_UDMA0_CYC; - dvs = ATA_UDMA0_DVS; - break; - case XFER_UDMA_1: - cyc = ATA_UDMA1_CYC; - dvs = ATA_UDMA1_DVS; - break; - case XFER_UDMA_2: - cyc = ATA_UDMA2_CYC; - dvs = ATA_UDMA2_DVS; - break; - case XFER_MW_DMA_0: - strobe = ATA_DMA0_STROBE; - hold = ATA_DMA0_HOLD; - break; - case XFER_MW_DMA_1: - strobe = ATA_DMA1_STROBE; - hold = ATA_DMA1_HOLD; - break; - case XFER_MW_DMA_2: - strobe = ATA_DMA2_STROBE; - hold = ATA_DMA2_HOLD; - break; - default: - return 0; - } - - if (speed >= XFER_UDMA_0) - cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0); - else - cris_ide_set_speed(TYPE_DMA, 0, strobe, hold); - - return 0; -} - -void __init -init_e100_ide (void) -{ - hw_regs_t hw; - int ide_offsets[IDE_NR_PORTS]; - int h; - int i; - - printk("ide: ETRAX FS built-in ATA DMA controller\n"); - - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) - ide_offsets[i] = cris_ide_reg_addr(i, 0, 1); - - /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */ - ide_offsets[IDE_CONTROL_OFFSET] = cris_ide_reg_addr(6, 1, 0); - - /* first fill in some stuff in the ide_hwifs fields */ - - for(h = 0; h < MAX_HWIFS; h++) { - ide_hwif_t *hwif = &ide_hwifs[h]; - ide_setup_ports(&hw, cris_ide_base_address(h), - ide_offsets, - 0, 0, cris_ide_ack_intr, - ide_default_irq(0)); - ide_register_hw(&hw, &hwif); - hwif->mmio = 2; - hwif->chipset = ide_etrax100; - hwif->tuneproc = &tune_cris_ide; - hwif->speedproc = &speed_cris_ide; - hwif->ata_input_data = &cris_ide_input_data; - hwif->ata_output_data = &cris_ide_output_data; - hwif->atapi_input_bytes = &cris_atapi_input_bytes; - hwif->atapi_output_bytes = &cris_atapi_output_bytes; - hwif->ide_dma_check = &cris_dma_check; - hwif->ide_dma_end = &cris_dma_end; - hwif->dma_setup = &cris_dma_setup; - hwif->dma_exec_cmd = &cris_dma_exec_cmd; - hwif->ide_dma_test_irq = &cris_dma_test_irq; - hwif->dma_start = &cris_dma_start; - hwif->OUTB = &cris_ide_outb; - hwif->OUTW = &cris_ide_outw; - hwif->OUTBSYNC = &cris_ide_outbsync; - hwif->INB = &cris_ide_inb; - hwif->INW = &cris_ide_inw; - hwif->ide_dma_host_off = &cris_dma_off; - hwif->ide_dma_host_on = &cris_dma_on; - hwif->ide_dma_off_quietly = &cris_dma_off; - hwif->udma_four = 0; - hwif->ultra_mask = cris_ultra_mask; - hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */ - hwif->swdma_mask = 0x07; /* Singleword DMA 0-2 */ - } - - /* Reset pulse */ - cris_ide_reset(0); - udelay(25); - cris_ide_reset(1); - - cris_ide_init(); - - cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD); - cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD); - cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0); -} - -static int cris_dma_off (ide_drive_t *drive) -{ - return 0; -} - -static int cris_dma_on (ide_drive_t *drive) -{ - return 0; -} - - -static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16))); - -/* - * The following routines are mainly used by the ATAPI drivers. - * - * These routines will round up any request for an odd number of bytes, - * so if an odd bytecount is specified, be sure that there's at least one - * extra byte allocated for the buffer. - */ -static void -cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) -{ - D(printk("atapi_input_bytes, buffer 0x%x, count %d\n", - buffer, bytecount)); - - if(bytecount & 1) { - printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount); - bytecount++; /* to round off */ - } - - /* setup DMA and start transfer */ - - cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1); - cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount); - - /* wait for completion */ - LED_DISK_READ(1); - cris_ide_wait_dma(1); - LED_DISK_READ(0); -} - -static void -cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) -{ - D(printk("atapi_output_bytes, buffer 0x%x, count %d\n", - buffer, bytecount)); - - if(bytecount & 1) { - printk("odd bytecount %d in atapi_out_bytes!\n", bytecount); - bytecount++; - } - - cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1); - cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount); - - /* wait for completion */ - - LED_DISK_WRITE(1); - LED_DISK_READ(1); - cris_ide_wait_dma(0); - LED_DISK_WRITE(0); -} - -/* - * This is used for most PIO data transfers *from* the IDE interface - */ -static void -cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount) -{ - cris_atapi_input_bytes(drive, buffer, wcount << 2); -} - -/* - * This is used for most PIO data transfers *to* the IDE interface - */ -static void -cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount) -{ - cris_atapi_output_bytes(drive, buffer, wcount << 2); -} - -/* we only have one DMA channel on the chip for ATA, so we can keep these statically */ -static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16))); -static unsigned int ata_tot_size; - -/* - * cris_ide_build_dmatable() prepares a dma request. - * Returns 0 if all went okay, returns 1 otherwise. - */ -static int cris_ide_build_dmatable (ide_drive_t *drive) -{ - ide_hwif_t *hwif = drive->hwif; - struct scatterlist* sg; - struct request *rq = drive->hwif->hwgroup->rq; - unsigned long size, addr; - unsigned int count = 0; - int i = 0; - - sg = hwif->sg_table; - - ata_tot_size = 0; - - ide_map_sg(drive, rq); - i = hwif->sg_nents; - - while(i) { - /* - * Determine addr and size of next buffer area. We assume that - * individual virtual buffers are always composed linearly in - * physical memory. For example, we assume that any 8kB buffer - * is always composed of two adjacent physical 4kB pages rather - * than two possibly non-adjacent physical 4kB pages. - */ - /* group sequential buffers into one large buffer */ - addr = page_to_phys(sg->page) + sg->offset; - size = sg_dma_len(sg); - while (sg++, --i) { - if ((addr + size) != page_to_phys(sg->page) + sg->offset) - break; - size += sg_dma_len(sg); - } - - /* did we run out of descriptors? */ - - if(count >= MAX_DMA_DESCRS) { - printk("%s: too few DMA descriptors\n", drive->name); - return 1; - } - - /* however, this case is more difficult - rw_trf_cnt cannot be more - than 65536 words per transfer, so in that case we need to either - 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with - the descriptors, or - 2) simply do the request here, and get dma_intr to only ide_end_request on - those blocks that were actually set-up for transfer. - */ - - if(ata_tot_size + size > 131072) { - printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size); - return 1; - } - - /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we - don't handle size > 131072 only one split is necessary */ - - if(size > MAX_DESCR_SIZE) { - cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0); - count++; - ata_tot_size += MAX_DESCR_SIZE; - size -= MAX_DESCR_SIZE; - addr += MAX_DESCR_SIZE; - } - - cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1); - count++; - ata_tot_size += size; - } - - if (count) { - /* return and say all is ok */ - return 0; - } - - printk("%s: empty DMA table?\n", drive->name); - return 1; /* let the PIO routines handle this weirdness */ -} - -static int cris_config_drive_for_dma (ide_drive_t *drive) -{ - u8 speed = ide_dma_speed(drive, 1); - - if (!speed) - return 0; - - speed_cris_ide(drive, speed); - ide_config_drive_speed(drive, speed); - - return ide_dma_enable(drive); -} - -/* - * cris_dma_intr() is the handler for disk read/write DMA interrupts - */ -static ide_startstop_t cris_dma_intr (ide_drive_t *drive) -{ - LED_DISK_READ(0); - LED_DISK_WRITE(0); - - return ide_dma_intr(drive); -} - -/* - * Functions below initiates/aborts DMA read/write operations on a drive. - * - * The caller is assumed to have selected the drive and programmed the drive's - * sector address using CHS or LBA. All that remains is to prepare for DMA - * and then issue the actual read/write DMA/PIO command to the drive. - * - * For ATAPI devices, we just prepare for DMA and return. The caller should - * then issue the packet command to the drive and call us again with - * cris_dma_start afterwards. - * - * Returns 0 if all went well. - * Returns 1 if DMA read/write could not be started, in which case - * the caller should revert to PIO for the current request. - */ - -static int cris_dma_check(ide_drive_t *drive) -{ - ide_hwif_t *hwif = drive->hwif; - struct hd_driveid* id = drive->id; - - if (id && (id->capability & 1)) { - if (ide_use_dma(drive)) { - if (cris_config_drive_for_dma(drive)) - return hwif->ide_dma_on(drive); - } - } - - return hwif->ide_dma_off_quietly(drive); -} - -static int cris_dma_end(ide_drive_t *drive) -{ - drive->waiting_for_dma = 0; - return 0; -} - -static int cris_dma_setup(ide_drive_t *drive) -{ - struct request *rq = drive->hwif->hwgroup->rq; - - cris_ide_initialize_dma(!rq_data_dir(rq)); - if (cris_ide_build_dmatable (drive)) { - ide_map_sg(drive, rq); - return 1; - } - - drive->waiting_for_dma = 1; - return 0; -} - -static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command) -{ - /* set the irq handler which will finish the request when DMA is done */ - ide_set_handler(drive, &cris_dma_intr, WAIT_CMD, NULL); - - /* issue cmd to drive */ - cris_ide_outb(command, IDE_COMMAND_REG); -} - -static void cris_dma_start(ide_drive_t *drive) -{ - struct request *rq = drive->hwif->hwgroup->rq; - int writing = rq_data_dir(rq); - int type = TYPE_DMA; - - if (drive->current_speed >= XFER_UDMA_0) - type = TYPE_UDMA; - - cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size); - - if (writing) { - LED_DISK_WRITE(1); - } else { - LED_DISK_READ(1); - } -} diff --git a/trunk/drivers/ide/cris/ide-v10.c b/trunk/drivers/ide/cris/ide-v10.c new file mode 100644 index 000000000000..5b40220d3ddc --- /dev/null +++ b/trunk/drivers/ide/cris/ide-v10.c @@ -0,0 +1,842 @@ +/* $Id: ide.c,v 1.4 2004/10/12 07:55:48 starvik Exp $ + * + * Etrax specific IDE functions, like init and PIO-mode setting etc. + * Almost the entire ide.c is used for the rest of the Etrax ATA driver. + * Copyright (c) 2000-2004 Axis Communications AB + * + * Authors: Bjorn Wesen (initial version) + * Mikael Starvik (pio setup stuff, Linux 2.6 port) + */ + +/* Regarding DMA: + * + * There are two forms of DMA - "DMA handshaking" between the interface and the drive, + * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's + * something built-in in the Etrax. However only some drives support the DMA-mode handshaking + * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the + * device can't do DMA handshaking for some stupid reason. We don't need to do that. + */ + +#undef REALLY_SLOW_IO /* most systems can safely undef this */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* number of Etrax DMA descriptors */ +#define MAX_DMA_DESCRS 64 + +/* number of times to retry busy-flags when reading/writing IDE-registers + * this can't be too high because a hung harddisk might cause the watchdog + * to trigger (sometimes INB and OUTB are called with irq's disabled) + */ + +#define IDE_REGISTER_TIMEOUT 300 + +static int e100_read_command = 0; + +#define LOWDB(x) +#define D(x) + +static int e100_ide_build_dmatable (ide_drive_t *drive); +static ide_startstop_t etrax_dma_intr (ide_drive_t *drive); + +void +etrax100_ide_outw(unsigned short data, unsigned long reg) { + int timeleft; + LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg)); + + /* note the lack of handling any timeouts. we stop waiting, but we don't + * really notify anybody. + */ + + timeleft = IDE_REGISTER_TIMEOUT; + /* wait for busy flag */ + while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy))) + timeleft--; + + /* + * Fall through at a timeout, so the ongoing command will be + * aborted by the write below, which is expected to be a dummy + * command to the command register. This happens when a faulty + * drive times out on a command. See comment on timeout in + * INB. + */ + if(!timeleft) + printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data); + + *R_ATA_CTRL_DATA = reg | data; /* write data to the drive's register */ + + timeleft = IDE_REGISTER_TIMEOUT; + /* wait for transmitter ready */ + while(timeleft && !(*R_ATA_STATUS_DATA & + IO_MASK(R_ATA_STATUS_DATA, tr_rdy))) + timeleft--; +} + +void +etrax100_ide_outb(unsigned char data, unsigned long reg) +{ + etrax100_ide_outw(data, reg); +} + +void +etrax100_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port) +{ + etrax100_ide_outw(addr, port); +} + +unsigned short +etrax100_ide_inw(unsigned long reg) { + int status; + int timeleft; + + timeleft = IDE_REGISTER_TIMEOUT; + /* wait for busy flag */ + while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy))) + timeleft--; + + if(!timeleft) { + /* + * If we're asked to read the status register, like for + * example when a command does not complete for an + * extended time, but the ATA interface is stuck in a + * busy state at the *ETRAX* ATA interface level (as has + * happened repeatedly with at least one bad disk), then + * the best thing to do is to pretend that we read + * "busy" in the status register, so the IDE driver will + * time-out, abort the ongoing command and perform a + * reset sequence. Note that the subsequent OUT_BYTE + * call will also timeout on busy, but as long as the + * write is still performed, everything will be fine. + */ + if ((reg & IO_MASK (R_ATA_CTRL_DATA, addr)) + == IO_FIELD (R_ATA_CTRL_DATA, addr, IDE_STATUS_OFFSET)) + return BUSY_STAT; + else + /* For other rare cases we assume 0 is good enough. */ + return 0; + } + + *R_ATA_CTRL_DATA = reg | IO_STATE(R_ATA_CTRL_DATA, rw, read); /* read data */ + + timeleft = IDE_REGISTER_TIMEOUT; + /* wait for available */ + while(timeleft && !((status = *R_ATA_STATUS_DATA) & + IO_MASK(R_ATA_STATUS_DATA, dav))) + timeleft--; + + if(!timeleft) + return 0; + + LOWDB(printk("inb: 0x%x from reg 0x%x\n", status & 0xff, reg)); + + return (unsigned short)status; +} + +unsigned char +etrax100_ide_inb(unsigned long reg) +{ + return (unsigned char)etrax100_ide_inw(reg); +} + +/* PIO timing (in R_ATA_CONFIG) + * + * _____________________________ + * ADDRESS : ________/ + * + * _______________ + * DIOR : ____________/ \__________ + * + * _______________ + * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX + * + * + * DIOR is unbuffered while address and data is buffered. + * This creates two problems: + * 1. The DIOR pulse is to early (because it is unbuffered) + * 2. The rise time of DIOR is long + * + * There are at least three different plausible solutions + * 1. Use a pad capable of larger currents in Etrax + * 2. Use an external buffer + * 3. Make the strobe pulse longer + * + * Some of the strobe timings below are modified to compensate + * for this. This implies a slight performance decrease. + * + * THIS SHOULD NEVER BE CHANGED! + * + * TODO: Is this true for the latest LX boards still ? + */ + +#define ATA_DMA2_STROBE 4 +#define ATA_DMA2_HOLD 0 +#define ATA_DMA1_STROBE 4 +#define ATA_DMA1_HOLD 1 +#define ATA_DMA0_STROBE 12 +#define ATA_DMA0_HOLD 9 +#define ATA_PIO4_SETUP 1 +#define ATA_PIO4_STROBE 5 +#define ATA_PIO4_HOLD 0 +#define ATA_PIO3_SETUP 1 +#define ATA_PIO3_STROBE 5 +#define ATA_PIO3_HOLD 1 +#define ATA_PIO2_SETUP 1 +#define ATA_PIO2_STROBE 6 +#define ATA_PIO2_HOLD 2 +#define ATA_PIO1_SETUP 2 +#define ATA_PIO1_STROBE 11 +#define ATA_PIO1_HOLD 4 +#define ATA_PIO0_SETUP 4 +#define ATA_PIO0_STROBE 19 +#define ATA_PIO0_HOLD 4 + +static int e100_dma_check (ide_drive_t *drive); +static void e100_dma_start(ide_drive_t *drive); +static int e100_dma_end (ide_drive_t *drive); +static void e100_ide_input_data (ide_drive_t *drive, void *, unsigned int); +static void e100_ide_output_data (ide_drive_t *drive, void *, unsigned int); +static void e100_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int); +static void e100_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int); +static int e100_dma_off (ide_drive_t *drive); + + +/* + * good_dma_drives() lists the model names (from "hdparm -i") + * of drives which do not support mword2 DMA but which are + * known to work fine with this interface under Linux. + */ + +const char *good_dma_drives[] = {"Micropolis 2112A", + "CONNER CTMA 4000", + "CONNER CTT8000-A", + NULL}; + +static void tune_e100_ide(ide_drive_t *drive, byte pio) +{ + pio = 4; + /* pio = ide_get_best_pio_mode(drive, pio, 4, NULL); */ + + /* set pio mode! */ + + switch(pio) { + case 0: + *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | + IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | + IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | + IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO0_SETUP ) | + IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO0_STROBE ) | + IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO0_HOLD ) ); + break; + case 1: + *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | + IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | + IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | + IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO1_SETUP ) | + IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO1_STROBE ) | + IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO1_HOLD ) ); + break; + case 2: + *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | + IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | + IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | + IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO2_SETUP ) | + IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO2_STROBE ) | + IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO2_HOLD ) ); + break; + case 3: + *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | + IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | + IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | + IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO3_SETUP ) | + IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO3_STROBE ) | + IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO3_HOLD ) ); + break; + case 4: + *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | + IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | + IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | + IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) | + IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) | + IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) ); + break; + } +} + +static int e100_dma_setup(ide_drive_t *drive) +{ + struct request *rq = drive->hwif->hwgroup->rq; + + if (rq_data_dir(rq)) { + e100_read_command = 0; + + RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */ + WAIT_DMA(ATA_TX_DMA_NBR); + } else { + e100_read_command = 1; + + RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */ + WAIT_DMA(ATA_RX_DMA_NBR); + } + + /* set up the Etrax DMA descriptors */ + if (e100_ide_build_dmatable(drive)) { + ide_map_sg(drive, rq); + return 1; + } + + return 0; +} + +static void e100_dma_exec_cmd(ide_drive_t *drive, u8 command) +{ + /* set the irq handler which will finish the request when DMA is done */ + ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL); + + /* issue cmd to drive */ + etrax100_ide_outb(command, IDE_COMMAND_REG); +} + +void __init +init_e100_ide (void) +{ + volatile unsigned int dummy; + int h; + + printk("ide: ETRAX 100LX built-in ATA DMA controller\n"); + + /* first fill in some stuff in the ide_hwifs fields */ + + for(h = 0; h < MAX_HWIFS; h++) { + ide_hwif_t *hwif = &ide_hwifs[h]; + hwif->mmio = 2; + hwif->chipset = ide_etrax100; + hwif->tuneproc = &tune_e100_ide; + hwif->ata_input_data = &e100_ide_input_data; + hwif->ata_output_data = &e100_ide_output_data; + hwif->atapi_input_bytes = &e100_atapi_input_bytes; + hwif->atapi_output_bytes = &e100_atapi_output_bytes; + hwif->ide_dma_check = &e100_dma_check; + hwif->ide_dma_end = &e100_dma_end; + hwif->dma_setup = &e100_dma_setup; + hwif->dma_exec_cmd = &e100_dma_exec_cmd; + hwif->dma_start = &e100_dma_start; + hwif->OUTB = &etrax100_ide_outb; + hwif->OUTW = &etrax100_ide_outw; + hwif->OUTBSYNC = &etrax100_ide_outbsync; + hwif->INB = &etrax100_ide_inb; + hwif->INW = &etrax100_ide_inw; + hwif->ide_dma_off_quietly = &e100_dma_off; + } + + /* actually reset and configure the etrax100 ide/ata interface */ + + *R_ATA_CTRL_DATA = 0; + *R_ATA_TRANSFER_CNT = 0; + *R_ATA_CONFIG = 0; + + genconfig_shadow = (genconfig_shadow & + ~IO_MASK(R_GEN_CONFIG, dma2) & + ~IO_MASK(R_GEN_CONFIG, dma3) & + ~IO_MASK(R_GEN_CONFIG, ata)) | + ( IO_STATE( R_GEN_CONFIG, dma3, ata ) | + IO_STATE( R_GEN_CONFIG, dma2, ata ) | + IO_STATE( R_GEN_CONFIG, ata, select ) ); + + *R_GEN_CONFIG = genconfig_shadow; + + /* pull the chosen /reset-line low */ + +#ifdef CONFIG_ETRAX_IDE_G27_RESET + REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 0); +#endif +#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET + REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 0); +#endif +#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 0); +#endif +#ifdef CONFIG_ETRAX_IDE_PB7_RESET + port_pb_dir_shadow = port_pb_dir_shadow | + IO_STATE(R_PORT_PB_DIR, dir7, output); + *R_PORT_PB_DIR = port_pb_dir_shadow; + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, 1); +#endif + + /* wait some */ + + udelay(25); + + /* de-assert bus-reset */ + +#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET + REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 1); +#endif +#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 1); +#endif +#ifdef CONFIG_ETRAX_IDE_G27_RESET + REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 1); +#endif + + /* make a dummy read to set the ata controller in a proper state */ + dummy = *R_ATA_STATUS_DATA; + + *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | + IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | + IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | + IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) | + IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) | + IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) ); + + *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) | + IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) ); + + while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/ + + *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) | + IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) | + IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) | + IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) ); + + printk("ide: waiting %d seconds for drives to regain consciousness\n", + CONFIG_ETRAX_IDE_DELAY); + + h = jiffies + (CONFIG_ETRAX_IDE_DELAY * HZ); + while(time_before(jiffies, h)) /* nothing */ ; + + /* reset the dma channels we will use */ + + RESET_DMA(ATA_TX_DMA_NBR); + RESET_DMA(ATA_RX_DMA_NBR); + WAIT_DMA(ATA_TX_DMA_NBR); + WAIT_DMA(ATA_RX_DMA_NBR); + +} + +static int e100_dma_off (ide_drive_t *drive) +{ + return 0; +} + +static etrax_dma_descr mydescr; + +/* + * The following routines are mainly used by the ATAPI drivers. + * + * These routines will round up any request for an odd number of bytes, + * so if an odd bytecount is specified, be sure that there's at least one + * extra byte allocated for the buffer. + */ +static void +e100_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) +{ + unsigned long data_reg = IDE_DATA_REG; + + D(printk("atapi_input_bytes, dreg 0x%x, buffer 0x%x, count %d\n", + data_reg, buffer, bytecount)); + + if(bytecount & 1) { + printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount); + bytecount++; /* to round off */ + } + + /* make sure the DMA channel is available */ + RESET_DMA(ATA_RX_DMA_NBR); + WAIT_DMA(ATA_RX_DMA_NBR); + + /* setup DMA descriptor */ + + mydescr.sw_len = bytecount; + mydescr.ctrl = d_eol; + mydescr.buf = virt_to_phys(buffer); + + /* start the dma channel */ + + *R_DMA_CH3_FIRST = virt_to_phys(&mydescr); + *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start); + + /* initiate a multi word dma read using PIO handshaking */ + + *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1); + + *R_ATA_CTRL_DATA = data_reg | + IO_STATE(R_ATA_CTRL_DATA, rw, read) | + IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | + IO_STATE(R_ATA_CTRL_DATA, handsh, pio) | + IO_STATE(R_ATA_CTRL_DATA, multi, on) | + IO_STATE(R_ATA_CTRL_DATA, dma_size, word); + + /* wait for completion */ + + LED_DISK_READ(1); + WAIT_DMA(ATA_RX_DMA_NBR); + LED_DISK_READ(0); + +#if 0 + /* old polled transfer code + * this should be moved into a new function that can do polled + * transfers if DMA is not available + */ + + /* initiate a multi word read */ + + *R_ATA_TRANSFER_CNT = wcount << 1; + + *R_ATA_CTRL_DATA = data_reg | + IO_STATE(R_ATA_CTRL_DATA, rw, read) | + IO_STATE(R_ATA_CTRL_DATA, src_dst, register) | + IO_STATE(R_ATA_CTRL_DATA, handsh, pio) | + IO_STATE(R_ATA_CTRL_DATA, multi, on) | + IO_STATE(R_ATA_CTRL_DATA, dma_size, word); + + /* svinto has a latency until the busy bit actually is set */ + + nop(); nop(); + nop(); nop(); + nop(); nop(); + nop(); nop(); + nop(); nop(); + + /* unit should be busy during multi transfer */ + while((status = *R_ATA_STATUS_DATA) & IO_MASK(R_ATA_STATUS_DATA, busy)) { + while(!(status & IO_MASK(R_ATA_STATUS_DATA, dav))) + status = *R_ATA_STATUS_DATA; + *ptr++ = (unsigned short)(status & 0xffff); + } +#endif +} + +static void +e100_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) +{ + unsigned long data_reg = IDE_DATA_REG; + + D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n", + data_reg, buffer, bytecount)); + + if(bytecount & 1) { + printk("odd bytecount %d in atapi_out_bytes!\n", bytecount); + bytecount++; + } + + /* make sure the DMA channel is available */ + RESET_DMA(ATA_TX_DMA_NBR); + WAIT_DMA(ATA_TX_DMA_NBR); + + /* setup DMA descriptor */ + + mydescr.sw_len = bytecount; + mydescr.ctrl = d_eol; + mydescr.buf = virt_to_phys(buffer); + + /* start the dma channel */ + + *R_DMA_CH2_FIRST = virt_to_phys(&mydescr); + *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start); + + /* initiate a multi word dma write using PIO handshaking */ + + *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1); + + *R_ATA_CTRL_DATA = data_reg | + IO_STATE(R_ATA_CTRL_DATA, rw, write) | + IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | + IO_STATE(R_ATA_CTRL_DATA, handsh, pio) | + IO_STATE(R_ATA_CTRL_DATA, multi, on) | + IO_STATE(R_ATA_CTRL_DATA, dma_size, word); + + /* wait for completion */ + + LED_DISK_WRITE(1); + WAIT_DMA(ATA_TX_DMA_NBR); + LED_DISK_WRITE(0); + +#if 0 + /* old polled write code - see comment in input_bytes */ + + /* wait for busy flag */ + while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); + + /* initiate a multi word write */ + + *R_ATA_TRANSFER_CNT = bytecount >> 1; + + ctrl = data_reg | + IO_STATE(R_ATA_CTRL_DATA, rw, write) | + IO_STATE(R_ATA_CTRL_DATA, src_dst, register) | + IO_STATE(R_ATA_CTRL_DATA, handsh, pio) | + IO_STATE(R_ATA_CTRL_DATA, multi, on) | + IO_STATE(R_ATA_CTRL_DATA, dma_size, word); + + LED_DISK_WRITE(1); + + /* Etrax will set busy = 1 until the multi pio transfer has finished + * and tr_rdy = 1 after each successful word transfer. + * When the last byte has been transferred Etrax will first set tr_tdy = 1 + * and then busy = 0 (not in the same cycle). If we read busy before it + * has been set to 0 we will think that we should transfer more bytes + * and then tr_rdy would be 0 forever. This is solved by checking busy + * in the inner loop. + */ + + do { + *R_ATA_CTRL_DATA = ctrl | *ptr++; + while(!(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy)) && + (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy))); + } while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); + + LED_DISK_WRITE(0); +#endif + +} + +/* + * This is used for most PIO data transfers *from* the IDE interface + */ +static void +e100_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount) +{ + e100_atapi_input_bytes(drive, buffer, wcount << 2); +} + +/* + * This is used for most PIO data transfers *to* the IDE interface + */ +static void +e100_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount) +{ + e100_atapi_output_bytes(drive, buffer, wcount << 2); +} + +/* we only have one DMA channel on the chip for ATA, so we can keep these statically */ +static etrax_dma_descr ata_descrs[MAX_DMA_DESCRS]; +static unsigned int ata_tot_size; + +/* + * e100_ide_build_dmatable() prepares a dma request. + * Returns 0 if all went okay, returns 1 otherwise. + */ +static int e100_ide_build_dmatable (ide_drive_t *drive) +{ + ide_hwif_t *hwif = HWIF(drive); + struct scatterlist* sg; + struct request *rq = HWGROUP(drive)->rq; + unsigned long size, addr; + unsigned int count = 0; + int i = 0; + + sg = hwif->sg_table; + + ata_tot_size = 0; + + ide_map_sg(drive, rq); + + i = hwif->sg_nents; + + while(i) { + /* + * Determine addr and size of next buffer area. We assume that + * individual virtual buffers are always composed linearly in + * physical memory. For example, we assume that any 8kB buffer + * is always composed of two adjacent physical 4kB pages rather + * than two possibly non-adjacent physical 4kB pages. + */ + /* group sequential buffers into one large buffer */ + addr = page_to_phys(sg->page) + sg->offset; + size = sg_dma_len(sg); + while (sg++, --i) { + if ((addr + size) != page_to_phys(sg->page) + sg->offset) + break; + size += sg_dma_len(sg); + } + + /* did we run out of descriptors? */ + + if(count >= MAX_DMA_DESCRS) { + printk("%s: too few DMA descriptors\n", drive->name); + return 1; + } + + /* however, this case is more difficult - R_ATA_TRANSFER_CNT cannot be more + than 65536 words per transfer, so in that case we need to either + 1) use a DMA interrupt to re-trigger R_ATA_TRANSFER_CNT and continue with + the descriptors, or + 2) simply do the request here, and get dma_intr to only ide_end_request on + those blocks that were actually set-up for transfer. + */ + + if(ata_tot_size + size > 131072) { + printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size); + return 1; + } + + /* If size > 65536 it has to be splitted into new descriptors. Since we don't handle + size > 131072 only one split is necessary */ + + if(size > 65536) { + /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */ + ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */ + ata_descrs[count].ctrl = 0; + ata_descrs[count].buf = addr; + ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]); + count++; + ata_tot_size += 65536; + /* size and addr should refere to not handled data */ + size -= 65536; + addr += 65536; + } + /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */ + if(size == 65536) { + ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */ + } else { + ata_descrs[count].sw_len = size; + } + ata_descrs[count].ctrl = 0; + ata_descrs[count].buf = addr; + ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]); + count++; + ata_tot_size += size; + } + + if (count) { + /* set the end-of-list flag on the last descriptor */ + ata_descrs[count - 1].ctrl |= d_eol; + /* return and say all is ok */ + return 0; + } + + printk("%s: empty DMA table?\n", drive->name); + return 1; /* let the PIO routines handle this weirdness */ +} + +static int config_drive_for_dma (ide_drive_t *drive) +{ + const char **list; + struct hd_driveid *id = drive->id; + + if (id && (id->capability & 1)) { + /* Enable DMA on any drive that supports mword2 DMA */ + if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) { + drive->using_dma = 1; + return 0; /* DMA enabled */ + } + + /* Consult the list of known "good" drives */ + list = good_dma_drives; + while (*list) { + if (!strcmp(*list++,id->model)) { + drive->using_dma = 1; + return 0; /* DMA enabled */ + } + } + } + return 1; /* DMA not enabled */ +} + +/* + * etrax_dma_intr() is the handler for disk read/write DMA interrupts + */ +static ide_startstop_t etrax_dma_intr (ide_drive_t *drive) +{ + LED_DISK_READ(0); + LED_DISK_WRITE(0); + + return ide_dma_intr(drive); +} + +/* + * Functions below initiates/aborts DMA read/write operations on a drive. + * + * The caller is assumed to have selected the drive and programmed the drive's + * sector address using CHS or LBA. All that remains is to prepare for DMA + * and then issue the actual read/write DMA/PIO command to the drive. + * + * Returns 0 if all went well. + * Returns 1 if DMA read/write could not be started, in which case + * the caller should revert to PIO for the current request. + */ + +static int e100_dma_check(ide_drive_t *drive) +{ + return config_drive_for_dma (drive); +} + +static int e100_dma_end(ide_drive_t *drive) +{ + /* TODO: check if something went wrong with the DMA */ + return 0; +} + +static void e100_dma_start(ide_drive_t *drive) +{ + if (e100_read_command) { + /* begin DMA */ + + /* need to do this before RX DMA due to a chip bug + * it is enough to just flush the part of the cache that + * corresponds to the buffers we start, but since HD transfers + * usually are more than 8 kB, it is easier to optimize for the + * normal case and just flush the entire cache. its the only + * way to be sure! (OB movie quote) + */ + flush_etrax_cache(); + *R_DMA_CH3_FIRST = virt_to_phys(ata_descrs); + *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start); + + /* initiate a multi word dma read using DMA handshaking */ + + *R_ATA_TRANSFER_CNT = + IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1); + + *R_ATA_CTRL_DATA = + IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) | + IO_STATE(R_ATA_CTRL_DATA, rw, read) | + IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | + IO_STATE(R_ATA_CTRL_DATA, handsh, dma) | + IO_STATE(R_ATA_CTRL_DATA, multi, on) | + IO_STATE(R_ATA_CTRL_DATA, dma_size, word); + + LED_DISK_READ(1); + + D(printk("dma read of %d bytes.\n", ata_tot_size)); + + } else { + /* writing */ + /* begin DMA */ + + *R_DMA_CH2_FIRST = virt_to_phys(ata_descrs); + *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start); + + /* initiate a multi word dma write using DMA handshaking */ + + *R_ATA_TRANSFER_CNT = + IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1); + + *R_ATA_CTRL_DATA = + IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) | + IO_STATE(R_ATA_CTRL_DATA, rw, write) | + IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | + IO_STATE(R_ATA_CTRL_DATA, handsh, dma) | + IO_STATE(R_ATA_CTRL_DATA, multi, on) | + IO_STATE(R_ATA_CTRL_DATA, dma_size, word); + + LED_DISK_WRITE(1); + + D(printk("dma write of %d bytes.\n", ata_tot_size)); + } +} diff --git a/trunk/drivers/ide/pci/cmd640.c b/trunk/drivers/ide/pci/cmd640.c index 11d035f1983d..92a2b7caed58 100644 --- a/trunk/drivers/ide/pci/cmd640.c +++ b/trunk/drivers/ide/pci/cmd640.c @@ -487,7 +487,7 @@ static void display_clocks (unsigned int index) * Pack active and recovery counts into single byte representation * used by controller */ -static inline u8 pack_nibbles (u8 upper, u8 lower) +inline static u8 pack_nibbles (u8 upper, u8 lower) { return ((upper & 0x0f) << 4) | (lower & 0x0f); } diff --git a/trunk/drivers/ide/pci/trm290.c b/trunk/drivers/ide/pci/trm290.c index c26c8ca90dd4..8b5eea5405ef 100644 --- a/trunk/drivers/ide/pci/trm290.c +++ b/trunk/drivers/ide/pci/trm290.c @@ -5,7 +5,7 @@ * May be copied or modified under the terms of the GNU General Public License * * June 22, 2004 - get rid of check_region - * - Jesper Juhl + * Jesper Juhl * */ diff --git a/trunk/drivers/ieee1394/sbp2.c b/trunk/drivers/ieee1394/sbp2.c index 627af507643a..fe3e1703fa61 100644 --- a/trunk/drivers/ieee1394/sbp2.c +++ b/trunk/drivers/ieee1394/sbp2.c @@ -169,7 +169,6 @@ MODULE_DEVICE_TABLE(ieee1394, sbp2_id_table); * Debug levels, configured via kernel config, or enable here. */ -#define CONFIG_IEEE1394_SBP2_DEBUG 0 /* #define CONFIG_IEEE1394_SBP2_DEBUG_ORBS */ /* #define CONFIG_IEEE1394_SBP2_DEBUG_DMA */ /* #define CONFIG_IEEE1394_SBP2_DEBUG 1 */ diff --git a/trunk/drivers/infiniband/core/Makefile b/trunk/drivers/infiniband/core/Makefile index 10be36731ed7..e1a7cf3e8636 100644 --- a/trunk/drivers/infiniband/core/Makefile +++ b/trunk/drivers/infiniband/core/Makefile @@ -1,20 +1,15 @@ EXTRA_CFLAGS += -Idrivers/infiniband/include -obj-$(CONFIG_INFINIBAND) += ib_core.o ib_mad.o ib_sa.o \ - ib_cm.o ib_umad.o ib_ucm.o +obj-$(CONFIG_INFINIBAND) += ib_core.o ib_mad.o ib_sa.o ib_umad.o obj-$(CONFIG_INFINIBAND_USER_VERBS) += ib_uverbs.o ib_core-y := packer.o ud_header.o verbs.o sysfs.o \ device.o fmr_pool.o cache.o -ib_mad-y := mad.o smi.o agent.o mad_rmpp.o +ib_mad-y := mad.o smi.o agent.o ib_sa-y := sa_query.o -ib_cm-y := cm.o - ib_umad-y := user_mad.o -ib_ucm-y := ucm.o - ib_uverbs-y := uverbs_main.o uverbs_cmd.o uverbs_mem.o diff --git a/trunk/drivers/infiniband/core/agent.c b/trunk/drivers/infiniband/core/agent.c index 729f0b0d983a..23d1957c4b29 100644 --- a/trunk/drivers/infiniband/core/agent.c +++ b/trunk/drivers/infiniband/core/agent.c @@ -134,7 +134,7 @@ static int agent_mad_send(struct ib_mad_agent *mad_agent, sizeof(mad_priv->mad), DMA_TO_DEVICE); gather_list.length = sizeof(mad_priv->mad); - gather_list.lkey = mad_agent->mr->lkey; + gather_list.lkey = (*port_priv->mr).lkey; send_wr.next = NULL; send_wr.opcode = IB_WR_SEND; @@ -156,10 +156,10 @@ static int agent_mad_send(struct ib_mad_agent *mad_agent, /* Should sgid be looked up ? */ ah_attr.grh.sgid_index = 0; ah_attr.grh.hop_limit = grh->hop_limit; - ah_attr.grh.flow_label = be32_to_cpu( - grh->version_tclass_flow) & 0xfffff; - ah_attr.grh.traffic_class = (be32_to_cpu( - grh->version_tclass_flow) >> 20) & 0xff; + ah_attr.grh.flow_label = be32_to_cpup( + &grh->version_tclass_flow) & 0xfffff; + ah_attr.grh.traffic_class = (be32_to_cpup( + &grh->version_tclass_flow) >> 20) & 0xff; memcpy(ah_attr.grh.dgid.raw, grh->sgid.raw, sizeof(ah_attr.grh.dgid)); @@ -322,12 +322,22 @@ int ib_agent_port_open(struct ib_device *device, int port_num) goto error3; } + port_priv->mr = ib_get_dma_mr(port_priv->smp_agent->qp->pd, + IB_ACCESS_LOCAL_WRITE); + if (IS_ERR(port_priv->mr)) { + printk(KERN_ERR SPFX "Couldn't get DMA MR\n"); + ret = PTR_ERR(port_priv->mr); + goto error4; + } + spin_lock_irqsave(&ib_agent_port_list_lock, flags); list_add_tail(&port_priv->port_list, &ib_agent_port_list); spin_unlock_irqrestore(&ib_agent_port_list_lock, flags); return 0; +error4: + ib_unregister_mad_agent(port_priv->perf_mgmt_agent); error3: ib_unregister_mad_agent(port_priv->smp_agent); error2: @@ -351,6 +361,8 @@ int ib_agent_port_close(struct ib_device *device, int port_num) list_del(&port_priv->port_list); spin_unlock_irqrestore(&ib_agent_port_list_lock, flags); + ib_dereg_mr(port_priv->mr); + ib_unregister_mad_agent(port_priv->perf_mgmt_agent); ib_unregister_mad_agent(port_priv->smp_agent); kfree(port_priv); diff --git a/trunk/drivers/infiniband/core/agent_priv.h b/trunk/drivers/infiniband/core/agent_priv.h index 17435af1e914..17a0cce5813c 100644 --- a/trunk/drivers/infiniband/core/agent_priv.h +++ b/trunk/drivers/infiniband/core/agent_priv.h @@ -33,7 +33,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: agent_priv.h 1640 2005-01-24 22:39:02Z halr $ + * $Id: agent_priv.h 1389 2004-12-27 22:56:47Z roland $ */ #ifndef __IB_AGENT_PRIV_H__ @@ -57,6 +57,7 @@ struct ib_agent_port_private { int port_num; struct ib_mad_agent *smp_agent; /* SM class */ struct ib_mad_agent *perf_mgmt_agent; /* PerfMgmt class */ + struct ib_mr *mr; }; #endif /* __IB_AGENT_PRIV_H__ */ diff --git a/trunk/drivers/infiniband/core/cm.c b/trunk/drivers/infiniband/core/cm.c deleted file mode 100644 index 403ed125d8f4..000000000000 --- a/trunk/drivers/infiniband/core/cm.c +++ /dev/null @@ -1,3324 +0,0 @@ -/* - * Copyright (c) 2004, 2005 Intel Corporation. All rights reserved. - * Copyright (c) 2004 Topspin Corporation. All rights reserved. - * Copyright (c) 2004, 2005 Voltaire Corporation. All rights reserved. - * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * $Id: cm.c 2821 2005-07-08 17:07:28Z sean.hefty $ - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "cm_msgs.h" - -MODULE_AUTHOR("Sean Hefty"); -MODULE_DESCRIPTION("InfiniBand CM"); -MODULE_LICENSE("Dual BSD/GPL"); - -static void cm_add_one(struct ib_device *device); -static void cm_remove_one(struct ib_device *device); - -static struct ib_client cm_client = { - .name = "cm", - .add = cm_add_one, - .remove = cm_remove_one -}; - -static struct ib_cm { - spinlock_t lock; - struct list_head device_list; - rwlock_t device_lock; - struct rb_root listen_service_table; - u64 listen_service_id; - /* struct rb_root peer_service_table; todo: fix peer to peer */ - struct rb_root remote_qp_table; - struct rb_root remote_id_table; - struct rb_root remote_sidr_table; - struct idr local_id_table; - struct workqueue_struct *wq; -} cm; - -struct cm_port { - struct cm_device *cm_dev; - struct ib_mad_agent *mad_agent; - u8 port_num; -}; - -struct cm_device { - struct list_head list; - struct ib_device *device; - u64 ca_guid; - struct cm_port port[0]; -}; - -struct cm_av { - struct cm_port *port; - union ib_gid dgid; - struct ib_ah_attr ah_attr; - u16 pkey_index; - u8 packet_life_time; -}; - -struct cm_work { - struct work_struct work; - struct list_head list; - struct cm_port *port; - struct ib_mad_recv_wc *mad_recv_wc; /* Received MADs */ - u32 local_id; /* Established / timewait */ - u32 remote_id; - struct ib_cm_event cm_event; - struct ib_sa_path_rec path[0]; -}; - -struct cm_timewait_info { - struct cm_work work; /* Must be first. */ - struct rb_node remote_qp_node; - struct rb_node remote_id_node; - u64 remote_ca_guid; - u32 remote_qpn; - u8 inserted_remote_qp; - u8 inserted_remote_id; -}; - -struct cm_id_private { - struct ib_cm_id id; - - struct rb_node service_node; - struct rb_node sidr_id_node; - spinlock_t lock; - wait_queue_head_t wait; - atomic_t refcount; - - struct ib_mad_send_buf *msg; - struct cm_timewait_info *timewait_info; - /* todo: use alternate port on send failure */ - struct cm_av av; - struct cm_av alt_av; - - void *private_data; - u64 tid; - u32 local_qpn; - u32 remote_qpn; - u32 sq_psn; - u32 rq_psn; - int timeout_ms; - enum ib_mtu path_mtu; - u8 private_data_len; - u8 max_cm_retries; - u8 peer_to_peer; - u8 responder_resources; - u8 initiator_depth; - u8 local_ack_timeout; - u8 retry_count; - u8 rnr_retry_count; - u8 service_timeout; - - struct list_head work_list; - atomic_t work_count; -}; - -static void cm_work_handler(void *data); - -static inline void cm_deref_id(struct cm_id_private *cm_id_priv) -{ - if (atomic_dec_and_test(&cm_id_priv->refcount)) - wake_up(&cm_id_priv->wait); -} - -static int cm_alloc_msg(struct cm_id_private *cm_id_priv, - struct ib_mad_send_buf **msg) -{ - struct ib_mad_agent *mad_agent; - struct ib_mad_send_buf *m; - struct ib_ah *ah; - - mad_agent = cm_id_priv->av.port->mad_agent; - ah = ib_create_ah(mad_agent->qp->pd, &cm_id_priv->av.ah_attr); - if (IS_ERR(ah)) - return PTR_ERR(ah); - - m = ib_create_send_mad(mad_agent, 1, cm_id_priv->av.pkey_index, - ah, 0, sizeof(struct ib_mad_hdr), - sizeof(struct ib_mad)-sizeof(struct ib_mad_hdr), - GFP_ATOMIC); - if (IS_ERR(m)) { - ib_destroy_ah(ah); - return PTR_ERR(m); - } - - /* Timeout set by caller if response is expected. */ - m->send_wr.wr.ud.retries = cm_id_priv->max_cm_retries; - - atomic_inc(&cm_id_priv->refcount); - m->context[0] = cm_id_priv; - *msg = m; - return 0; -} - -static int cm_alloc_response_msg(struct cm_port *port, - struct ib_mad_recv_wc *mad_recv_wc, - struct ib_mad_send_buf **msg) -{ - struct ib_mad_send_buf *m; - struct ib_ah *ah; - - ah = ib_create_ah_from_wc(port->mad_agent->qp->pd, mad_recv_wc->wc, - mad_recv_wc->recv_buf.grh, port->port_num); - if (IS_ERR(ah)) - return PTR_ERR(ah); - - m = ib_create_send_mad(port->mad_agent, 1, mad_recv_wc->wc->pkey_index, - ah, 0, sizeof(struct ib_mad_hdr), - sizeof(struct ib_mad)-sizeof(struct ib_mad_hdr), - GFP_ATOMIC); - if (IS_ERR(m)) { - ib_destroy_ah(ah); - return PTR_ERR(m); - } - *msg = m; - return 0; -} - -static void cm_free_msg(struct ib_mad_send_buf *msg) -{ - ib_destroy_ah(msg->send_wr.wr.ud.ah); - if (msg->context[0]) - cm_deref_id(msg->context[0]); - ib_free_send_mad(msg); -} - -static void * cm_copy_private_data(const void *private_data, - u8 private_data_len) -{ - void *data; - - if (!private_data || !private_data_len) - return NULL; - - data = kmalloc(private_data_len, GFP_KERNEL); - if (!data) - return ERR_PTR(-ENOMEM); - - memcpy(data, private_data, private_data_len); - return data; -} - -static void cm_set_private_data(struct cm_id_private *cm_id_priv, - void *private_data, u8 private_data_len) -{ - if (cm_id_priv->private_data && cm_id_priv->private_data_len) - kfree(cm_id_priv->private_data); - - cm_id_priv->private_data = private_data; - cm_id_priv->private_data_len = private_data_len; -} - -static void cm_set_ah_attr(struct ib_ah_attr *ah_attr, u8 port_num, - u16 dlid, u8 sl, u16 src_path_bits) -{ - memset(ah_attr, 0, sizeof ah_attr); - ah_attr->dlid = be16_to_cpu(dlid); - ah_attr->sl = sl; - ah_attr->src_path_bits = src_path_bits; - ah_attr->port_num = port_num; -} - -static void cm_init_av_for_response(struct cm_port *port, - struct ib_wc *wc, struct cm_av *av) -{ - av->port = port; - av->pkey_index = wc->pkey_index; - cm_set_ah_attr(&av->ah_attr, port->port_num, cpu_to_be16(wc->slid), - wc->sl, wc->dlid_path_bits); -} - -static int cm_init_av_by_path(struct ib_sa_path_rec *path, struct cm_av *av) -{ - struct cm_device *cm_dev; - struct cm_port *port = NULL; - unsigned long flags; - int ret; - u8 p; - - read_lock_irqsave(&cm.device_lock, flags); - list_for_each_entry(cm_dev, &cm.device_list, list) { - if (!ib_find_cached_gid(cm_dev->device, &path->sgid, - &p, NULL)) { - port = &cm_dev->port[p-1]; - break; - } - } - read_unlock_irqrestore(&cm.device_lock, flags); - - if (!port) - return -EINVAL; - - ret = ib_find_cached_pkey(cm_dev->device, port->port_num, - be16_to_cpu(path->pkey), &av->pkey_index); - if (ret) - return ret; - - av->port = port; - cm_set_ah_attr(&av->ah_attr, av->port->port_num, path->dlid, - path->sl, path->slid & 0x7F); - av->packet_life_time = path->packet_life_time; - return 0; -} - -static int cm_alloc_id(struct cm_id_private *cm_id_priv) -{ - unsigned long flags; - int ret; - - do { - spin_lock_irqsave(&cm.lock, flags); - ret = idr_get_new_above(&cm.local_id_table, cm_id_priv, 1, - (int *) &cm_id_priv->id.local_id); - spin_unlock_irqrestore(&cm.lock, flags); - } while( (ret == -EAGAIN) && idr_pre_get(&cm.local_id_table, GFP_KERNEL) ); - return ret; -} - -static void cm_free_id(u32 local_id) -{ - unsigned long flags; - - spin_lock_irqsave(&cm.lock, flags); - idr_remove(&cm.local_id_table, (int) local_id); - spin_unlock_irqrestore(&cm.lock, flags); -} - -static struct cm_id_private * cm_get_id(u32 local_id, u32 remote_id) -{ - struct cm_id_private *cm_id_priv; - - cm_id_priv = idr_find(&cm.local_id_table, (int) local_id); - if (cm_id_priv) { - if (cm_id_priv->id.remote_id == remote_id) - atomic_inc(&cm_id_priv->refcount); - else - cm_id_priv = NULL; - } - - return cm_id_priv; -} - -static struct cm_id_private * cm_acquire_id(u32 local_id, u32 remote_id) -{ - struct cm_id_private *cm_id_priv; - unsigned long flags; - - spin_lock_irqsave(&cm.lock, flags); - cm_id_priv = cm_get_id(local_id, remote_id); - spin_unlock_irqrestore(&cm.lock, flags); - - return cm_id_priv; -} - -static struct cm_id_private * cm_insert_listen(struct cm_id_private *cm_id_priv) -{ - struct rb_node **link = &cm.listen_service_table.rb_node; - struct rb_node *parent = NULL; - struct cm_id_private *cur_cm_id_priv; - u64 service_id = cm_id_priv->id.service_id; - u64 service_mask = cm_id_priv->id.service_mask; - - while (*link) { - parent = *link; - cur_cm_id_priv = rb_entry(parent, struct cm_id_private, - service_node); - if ((cur_cm_id_priv->id.service_mask & service_id) == - (service_mask & cur_cm_id_priv->id.service_id)) - return cm_id_priv; - if (service_id < cur_cm_id_priv->id.service_id) - link = &(*link)->rb_left; - else - link = &(*link)->rb_right; - } - rb_link_node(&cm_id_priv->service_node, parent, link); - rb_insert_color(&cm_id_priv->service_node, &cm.listen_service_table); - return NULL; -} - -static struct cm_id_private * cm_find_listen(u64 service_id) -{ - struct rb_node *node = cm.listen_service_table.rb_node; - struct cm_id_private *cm_id_priv; - - while (node) { - cm_id_priv = rb_entry(node, struct cm_id_private, service_node); - if ((cm_id_priv->id.service_mask & service_id) == - (cm_id_priv->id.service_mask & cm_id_priv->id.service_id)) - return cm_id_priv; - if (service_id < cm_id_priv->id.service_id) - node = node->rb_left; - else - node = node->rb_right; - } - return NULL; -} - -static struct cm_timewait_info * cm_insert_remote_id(struct cm_timewait_info - *timewait_info) -{ - struct rb_node **link = &cm.remote_id_table.rb_node; - struct rb_node *parent = NULL; - struct cm_timewait_info *cur_timewait_info; - u64 remote_ca_guid = timewait_info->remote_ca_guid; - u32 remote_id = timewait_info->work.remote_id; - - while (*link) { - parent = *link; - cur_timewait_info = rb_entry(parent, struct cm_timewait_info, - remote_id_node); - if (remote_id < cur_timewait_info->work.remote_id) - link = &(*link)->rb_left; - else if (remote_id > cur_timewait_info->work.remote_id) - link = &(*link)->rb_right; - else if (remote_ca_guid < cur_timewait_info->remote_ca_guid) - link = &(*link)->rb_left; - else if (remote_ca_guid > cur_timewait_info->remote_ca_guid) - link = &(*link)->rb_right; - else - return cur_timewait_info; - } - timewait_info->inserted_remote_id = 1; - rb_link_node(&timewait_info->remote_id_node, parent, link); - rb_insert_color(&timewait_info->remote_id_node, &cm.remote_id_table); - return NULL; -} - -static struct cm_timewait_info * cm_find_remote_id(u64 remote_ca_guid, - u32 remote_id) -{ - struct rb_node *node = cm.remote_id_table.rb_node; - struct cm_timewait_info *timewait_info; - - while (node) { - timewait_info = rb_entry(node, struct cm_timewait_info, - remote_id_node); - if (remote_id < timewait_info->work.remote_id) - node = node->rb_left; - else if (remote_id > timewait_info->work.remote_id) - node = node->rb_right; - else if (remote_ca_guid < timewait_info->remote_ca_guid) - node = node->rb_left; - else if (remote_ca_guid > timewait_info->remote_ca_guid) - node = node->rb_right; - else - return timewait_info; - } - return NULL; -} - -static struct cm_timewait_info * cm_insert_remote_qpn(struct cm_timewait_info - *timewait_info) -{ - struct rb_node **link = &cm.remote_qp_table.rb_node; - struct rb_node *parent = NULL; - struct cm_timewait_info *cur_timewait_info; - u64 remote_ca_guid = timewait_info->remote_ca_guid; - u32 remote_qpn = timewait_info->remote_qpn; - - while (*link) { - parent = *link; - cur_timewait_info = rb_entry(parent, struct cm_timewait_info, - remote_qp_node); - if (remote_qpn < cur_timewait_info->remote_qpn) - link = &(*link)->rb_left; - else if (remote_qpn > cur_timewait_info->remote_qpn) - link = &(*link)->rb_right; - else if (remote_ca_guid < cur_timewait_info->remote_ca_guid) - link = &(*link)->rb_left; - else if (remote_ca_guid > cur_timewait_info->remote_ca_guid) - link = &(*link)->rb_right; - else - return cur_timewait_info; - } - timewait_info->inserted_remote_qp = 1; - rb_link_node(&timewait_info->remote_qp_node, parent, link); - rb_insert_color(&timewait_info->remote_qp_node, &cm.remote_qp_table); - return NULL; -} - -static struct cm_id_private * cm_insert_remote_sidr(struct cm_id_private - *cm_id_priv) -{ - struct rb_node **link = &cm.remote_sidr_table.rb_node; - struct rb_node *parent = NULL; - struct cm_id_private *cur_cm_id_priv; - union ib_gid *port_gid = &cm_id_priv->av.dgid; - u32 remote_id = cm_id_priv->id.remote_id; - - while (*link) { - parent = *link; - cur_cm_id_priv = rb_entry(parent, struct cm_id_private, - sidr_id_node); - if (remote_id < cur_cm_id_priv->id.remote_id) - link = &(*link)->rb_left; - else if (remote_id > cur_cm_id_priv->id.remote_id) - link = &(*link)->rb_right; - else { - int cmp; - cmp = memcmp(port_gid, &cur_cm_id_priv->av.dgid, - sizeof *port_gid); - if (cmp < 0) - link = &(*link)->rb_left; - else if (cmp > 0) - link = &(*link)->rb_right; - else - return cur_cm_id_priv; - } - } - rb_link_node(&cm_id_priv->sidr_id_node, parent, link); - rb_insert_color(&cm_id_priv->sidr_id_node, &cm.remote_sidr_table); - return NULL; -} - -static void cm_reject_sidr_req(struct cm_id_private *cm_id_priv, - enum ib_cm_sidr_status status) -{ - struct ib_cm_sidr_rep_param param; - - memset(¶m, 0, sizeof param); - param.status = status; - ib_send_cm_sidr_rep(&cm_id_priv->id, ¶m); -} - -struct ib_cm_id *ib_create_cm_id(ib_cm_handler cm_handler, - void *context) -{ - struct cm_id_private *cm_id_priv; - int ret; - - cm_id_priv = kmalloc(sizeof *cm_id_priv, GFP_KERNEL); - if (!cm_id_priv) - return ERR_PTR(-ENOMEM); - - memset(cm_id_priv, 0, sizeof *cm_id_priv); - cm_id_priv->id.state = IB_CM_IDLE; - cm_id_priv->id.cm_handler = cm_handler; - cm_id_priv->id.context = context; - ret = cm_alloc_id(cm_id_priv); - if (ret) - goto error; - - spin_lock_init(&cm_id_priv->lock); - init_waitqueue_head(&cm_id_priv->wait); - INIT_LIST_HEAD(&cm_id_priv->work_list); - atomic_set(&cm_id_priv->work_count, -1); - atomic_set(&cm_id_priv->refcount, 1); - return &cm_id_priv->id; - -error: - kfree(cm_id_priv); - return ERR_PTR(-ENOMEM); -} -EXPORT_SYMBOL(ib_create_cm_id); - -static struct cm_work * cm_dequeue_work(struct cm_id_private *cm_id_priv) -{ - struct cm_work *work; - - if (list_empty(&cm_id_priv->work_list)) - return NULL; - - work = list_entry(cm_id_priv->work_list.next, struct cm_work, list); - list_del(&work->list); - return work; -} - -static void cm_free_work(struct cm_work *work) -{ - if (work->mad_recv_wc) - ib_free_recv_mad(work->mad_recv_wc); - kfree(work); -} - -static inline int cm_convert_to_ms(int iba_time) -{ - /* approximate conversion to ms from 4.096us x 2^iba_time */ - return 1 << max(iba_time - 8, 0); -} - -static void cm_cleanup_timewait(struct cm_timewait_info *timewait_info) -{ - unsigned long flags; - - if (!timewait_info->inserted_remote_id && - !timewait_info->inserted_remote_qp) - return; - - spin_lock_irqsave(&cm.lock, flags); - if (timewait_info->inserted_remote_id) { - rb_erase(&timewait_info->remote_id_node, &cm.remote_id_table); - timewait_info->inserted_remote_id = 0; - } - - if (timewait_info->inserted_remote_qp) { - rb_erase(&timewait_info->remote_qp_node, &cm.remote_qp_table); - timewait_info->inserted_remote_qp = 0; - } - spin_unlock_irqrestore(&cm.lock, flags); -} - -static struct cm_timewait_info * cm_create_timewait_info(u32 local_id) -{ - struct cm_timewait_info *timewait_info; - - timewait_info = kmalloc(sizeof *timewait_info, GFP_KERNEL); - if (!timewait_info) - return ERR_PTR(-ENOMEM); - memset(timewait_info, 0, sizeof *timewait_info); - - timewait_info->work.local_id = local_id; - INIT_WORK(&timewait_info->work.work, cm_work_handler, - &timewait_info->work); - timewait_info->work.cm_event.event = IB_CM_TIMEWAIT_EXIT; - return timewait_info; -} - -static void cm_enter_timewait(struct cm_id_private *cm_id_priv) -{ - int wait_time; - - /* - * The cm_id could be destroyed by the user before we exit timewait. - * To protect against this, we search for the cm_id after exiting - * timewait before notifying the user that we've exited timewait. - */ - cm_id_priv->id.state = IB_CM_TIMEWAIT; - wait_time = cm_convert_to_ms(cm_id_priv->local_ack_timeout); - queue_delayed_work(cm.wq, &cm_id_priv->timewait_info->work.work, - msecs_to_jiffies(wait_time)); - cm_id_priv->timewait_info = NULL; -} - -static void cm_reset_to_idle(struct cm_id_private *cm_id_priv) -{ - cm_id_priv->id.state = IB_CM_IDLE; - if (cm_id_priv->timewait_info) { - cm_cleanup_timewait(cm_id_priv->timewait_info); - kfree(cm_id_priv->timewait_info); - cm_id_priv->timewait_info = NULL; - } -} - -void ib_destroy_cm_id(struct ib_cm_id *cm_id) -{ - struct cm_id_private *cm_id_priv; - struct cm_work *work; - unsigned long flags; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); -retest: - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id->state) { - case IB_CM_LISTEN: - cm_id->state = IB_CM_IDLE; - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - spin_lock_irqsave(&cm.lock, flags); - rb_erase(&cm_id_priv->service_node, &cm.listen_service_table); - spin_unlock_irqrestore(&cm.lock, flags); - break; - case IB_CM_SIDR_REQ_SENT: - cm_id->state = IB_CM_IDLE; - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - break; - case IB_CM_SIDR_REQ_RCVD: - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_reject_sidr_req(cm_id_priv, IB_SIDR_REJECT); - break; - case IB_CM_REQ_SENT: - case IB_CM_MRA_REQ_RCVD: - case IB_CM_REP_SENT: - case IB_CM_MRA_REP_RCVD: - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - /* Fall through */ - case IB_CM_REQ_RCVD: - case IB_CM_MRA_REQ_SENT: - case IB_CM_REP_RCVD: - case IB_CM_MRA_REP_SENT: - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - ib_send_cm_rej(cm_id, IB_CM_REJ_TIMEOUT, - &cm_id_priv->av.port->cm_dev->ca_guid, - sizeof cm_id_priv->av.port->cm_dev->ca_guid, - NULL, 0); - break; - case IB_CM_ESTABLISHED: - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - ib_send_cm_dreq(cm_id, NULL, 0); - goto retest; - case IB_CM_DREQ_SENT: - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - cm_enter_timewait(cm_id_priv); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - break; - case IB_CM_DREQ_RCVD: - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - ib_send_cm_drep(cm_id, NULL, 0); - break; - default: - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - break; - } - - cm_free_id(cm_id->local_id); - atomic_dec(&cm_id_priv->refcount); - wait_event(cm_id_priv->wait, !atomic_read(&cm_id_priv->refcount)); - while ((work = cm_dequeue_work(cm_id_priv)) != NULL) - cm_free_work(work); - if (cm_id_priv->private_data && cm_id_priv->private_data_len) - kfree(cm_id_priv->private_data); - kfree(cm_id_priv); -} -EXPORT_SYMBOL(ib_destroy_cm_id); - -int ib_cm_listen(struct ib_cm_id *cm_id, - u64 service_id, - u64 service_mask) -{ - struct cm_id_private *cm_id_priv, *cur_cm_id_priv; - unsigned long flags; - int ret = 0; - - service_mask = service_mask ? service_mask : ~0ULL; - service_id &= service_mask; - if ((service_id & IB_SERVICE_ID_AGN_MASK) == IB_CM_ASSIGN_SERVICE_ID && - (service_id != IB_CM_ASSIGN_SERVICE_ID)) - return -EINVAL; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - BUG_ON(cm_id->state != IB_CM_IDLE); - - cm_id->state = IB_CM_LISTEN; - - spin_lock_irqsave(&cm.lock, flags); - if (service_id == IB_CM_ASSIGN_SERVICE_ID) { - cm_id->service_id = __cpu_to_be64(cm.listen_service_id++); - cm_id->service_mask = ~0ULL; - } else { - cm_id->service_id = service_id; - cm_id->service_mask = service_mask; - } - cur_cm_id_priv = cm_insert_listen(cm_id_priv); - spin_unlock_irqrestore(&cm.lock, flags); - - if (cur_cm_id_priv) { - cm_id->state = IB_CM_IDLE; - ret = -EBUSY; - } - return ret; -} -EXPORT_SYMBOL(ib_cm_listen); - -static u64 cm_form_tid(struct cm_id_private *cm_id_priv, - enum cm_msg_sequence msg_seq) -{ - u64 hi_tid, low_tid; - - hi_tid = ((u64) cm_id_priv->av.port->mad_agent->hi_tid) << 32; - low_tid = (u64) (cm_id_priv->id.local_id | (msg_seq << 30)); - return cpu_to_be64(hi_tid | low_tid); -} - -static void cm_format_mad_hdr(struct ib_mad_hdr *hdr, - enum cm_msg_attr_id attr_id, u64 tid) -{ - hdr->base_version = IB_MGMT_BASE_VERSION; - hdr->mgmt_class = IB_MGMT_CLASS_CM; - hdr->class_version = IB_CM_CLASS_VERSION; - hdr->method = IB_MGMT_METHOD_SEND; - hdr->attr_id = attr_id; - hdr->tid = tid; -} - -static void cm_format_req(struct cm_req_msg *req_msg, - struct cm_id_private *cm_id_priv, - struct ib_cm_req_param *param) -{ - cm_format_mad_hdr(&req_msg->hdr, CM_REQ_ATTR_ID, - cm_form_tid(cm_id_priv, CM_MSG_SEQUENCE_REQ)); - - req_msg->local_comm_id = cm_id_priv->id.local_id; - req_msg->service_id = param->service_id; - req_msg->local_ca_guid = cm_id_priv->av.port->cm_dev->ca_guid; - cm_req_set_local_qpn(req_msg, cpu_to_be32(param->qp_num)); - cm_req_set_resp_res(req_msg, param->responder_resources); - cm_req_set_init_depth(req_msg, param->initiator_depth); - cm_req_set_remote_resp_timeout(req_msg, - param->remote_cm_response_timeout); - cm_req_set_qp_type(req_msg, param->qp_type); - cm_req_set_flow_ctrl(req_msg, param->flow_control); - cm_req_set_starting_psn(req_msg, cpu_to_be32(param->starting_psn)); - cm_req_set_local_resp_timeout(req_msg, - param->local_cm_response_timeout); - cm_req_set_retry_count(req_msg, param->retry_count); - req_msg->pkey = param->primary_path->pkey; - cm_req_set_path_mtu(req_msg, param->primary_path->mtu); - cm_req_set_rnr_retry_count(req_msg, param->rnr_retry_count); - cm_req_set_max_cm_retries(req_msg, param->max_cm_retries); - cm_req_set_srq(req_msg, param->srq); - - req_msg->primary_local_lid = param->primary_path->slid; - req_msg->primary_remote_lid = param->primary_path->dlid; - req_msg->primary_local_gid = param->primary_path->sgid; - req_msg->primary_remote_gid = param->primary_path->dgid; - cm_req_set_primary_flow_label(req_msg, param->primary_path->flow_label); - cm_req_set_primary_packet_rate(req_msg, param->primary_path->rate); - req_msg->primary_traffic_class = param->primary_path->traffic_class; - req_msg->primary_hop_limit = param->primary_path->hop_limit; - cm_req_set_primary_sl(req_msg, param->primary_path->sl); - cm_req_set_primary_subnet_local(req_msg, 1); /* local only... */ - cm_req_set_primary_local_ack_timeout(req_msg, - min(31, param->primary_path->packet_life_time + 1)); - - if (param->alternate_path) { - req_msg->alt_local_lid = param->alternate_path->slid; - req_msg->alt_remote_lid = param->alternate_path->dlid; - req_msg->alt_local_gid = param->alternate_path->sgid; - req_msg->alt_remote_gid = param->alternate_path->dgid; - cm_req_set_alt_flow_label(req_msg, - param->alternate_path->flow_label); - cm_req_set_alt_packet_rate(req_msg, param->alternate_path->rate); - req_msg->alt_traffic_class = param->alternate_path->traffic_class; - req_msg->alt_hop_limit = param->alternate_path->hop_limit; - cm_req_set_alt_sl(req_msg, param->alternate_path->sl); - cm_req_set_alt_subnet_local(req_msg, 1); /* local only... */ - cm_req_set_alt_local_ack_timeout(req_msg, - min(31, param->alternate_path->packet_life_time + 1)); - } - - if (param->private_data && param->private_data_len) - memcpy(req_msg->private_data, param->private_data, - param->private_data_len); -} - -static inline int cm_validate_req_param(struct ib_cm_req_param *param) -{ - /* peer-to-peer not supported */ - if (param->peer_to_peer) - return -EINVAL; - - if (!param->primary_path) - return -EINVAL; - - if (param->qp_type != IB_QPT_RC && param->qp_type != IB_QPT_UC) - return -EINVAL; - - if (param->private_data && - param->private_data_len > IB_CM_REQ_PRIVATE_DATA_SIZE) - return -EINVAL; - - if (param->alternate_path && - (param->alternate_path->pkey != param->primary_path->pkey || - param->alternate_path->mtu != param->primary_path->mtu)) - return -EINVAL; - - return 0; -} - -int ib_send_cm_req(struct ib_cm_id *cm_id, - struct ib_cm_req_param *param) -{ - struct cm_id_private *cm_id_priv; - struct ib_send_wr *bad_send_wr; - struct cm_req_msg *req_msg; - unsigned long flags; - int ret; - - ret = cm_validate_req_param(param); - if (ret) - return ret; - - /* Verify that we're not in timewait. */ - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id->state != IB_CM_IDLE) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - ret = -EINVAL; - goto out; - } - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - cm_id_priv->timewait_info = cm_create_timewait_info(cm_id_priv-> - id.local_id); - if (IS_ERR(cm_id_priv->timewait_info)) - goto out; - - ret = cm_init_av_by_path(param->primary_path, &cm_id_priv->av); - if (ret) - goto error1; - if (param->alternate_path) { - ret = cm_init_av_by_path(param->alternate_path, - &cm_id_priv->alt_av); - if (ret) - goto error1; - } - cm_id->service_id = param->service_id; - cm_id->service_mask = ~0ULL; - cm_id_priv->timeout_ms = cm_convert_to_ms( - param->primary_path->packet_life_time) * 2 + - cm_convert_to_ms( - param->remote_cm_response_timeout); - cm_id_priv->max_cm_retries = param->max_cm_retries; - cm_id_priv->initiator_depth = param->initiator_depth; - cm_id_priv->responder_resources = param->responder_resources; - cm_id_priv->retry_count = param->retry_count; - cm_id_priv->path_mtu = param->primary_path->mtu; - - ret = cm_alloc_msg(cm_id_priv, &cm_id_priv->msg); - if (ret) - goto error1; - - req_msg = (struct cm_req_msg *) cm_id_priv->msg->mad; - cm_format_req(req_msg, cm_id_priv, param); - cm_id_priv->tid = req_msg->hdr.tid; - cm_id_priv->msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms; - cm_id_priv->msg->context[1] = (void *) (unsigned long) IB_CM_REQ_SENT; - - cm_id_priv->local_qpn = cm_req_get_local_qpn(req_msg); - cm_id_priv->rq_psn = cm_req_get_starting_psn(req_msg); - cm_id_priv->local_ack_timeout = - cm_req_get_primary_local_ack_timeout(req_msg); - - spin_lock_irqsave(&cm_id_priv->lock, flags); - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &cm_id_priv->msg->send_wr, &bad_send_wr); - if (ret) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - goto error2; - } - BUG_ON(cm_id->state != IB_CM_IDLE); - cm_id->state = IB_CM_REQ_SENT; - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return 0; - -error2: cm_free_msg(cm_id_priv->msg); -error1: kfree(cm_id_priv->timewait_info); -out: return ret; -} -EXPORT_SYMBOL(ib_send_cm_req); - -static int cm_issue_rej(struct cm_port *port, - struct ib_mad_recv_wc *mad_recv_wc, - enum ib_cm_rej_reason reason, - enum cm_msg_response msg_rejected, - void *ari, u8 ari_length) -{ - struct ib_mad_send_buf *msg = NULL; - struct ib_send_wr *bad_send_wr; - struct cm_rej_msg *rej_msg, *rcv_msg; - int ret; - - ret = cm_alloc_response_msg(port, mad_recv_wc, &msg); - if (ret) - return ret; - - /* We just need common CM header information. Cast to any message. */ - rcv_msg = (struct cm_rej_msg *) mad_recv_wc->recv_buf.mad; - rej_msg = (struct cm_rej_msg *) msg->mad; - - cm_format_mad_hdr(&rej_msg->hdr, CM_REJ_ATTR_ID, rcv_msg->hdr.tid); - rej_msg->remote_comm_id = rcv_msg->local_comm_id; - rej_msg->local_comm_id = rcv_msg->remote_comm_id; - cm_rej_set_msg_rejected(rej_msg, msg_rejected); - rej_msg->reason = reason; - - if (ari && ari_length) { - cm_rej_set_reject_info_len(rej_msg, ari_length); - memcpy(rej_msg->ari, ari, ari_length); - } - - ret = ib_post_send_mad(port->mad_agent, &msg->send_wr, &bad_send_wr); - if (ret) - cm_free_msg(msg); - - return ret; -} - -static inline int cm_is_active_peer(u64 local_ca_guid, u64 remote_ca_guid, - u32 local_qpn, u32 remote_qpn) -{ - return (be64_to_cpu(local_ca_guid) > be64_to_cpu(remote_ca_guid) || - ((local_ca_guid == remote_ca_guid) && - (be32_to_cpu(local_qpn) > be32_to_cpu(remote_qpn)))); -} - -static inline void cm_format_paths_from_req(struct cm_req_msg *req_msg, - struct ib_sa_path_rec *primary_path, - struct ib_sa_path_rec *alt_path) -{ - memset(primary_path, 0, sizeof *primary_path); - primary_path->dgid = req_msg->primary_local_gid; - primary_path->sgid = req_msg->primary_remote_gid; - primary_path->dlid = req_msg->primary_local_lid; - primary_path->slid = req_msg->primary_remote_lid; - primary_path->flow_label = cm_req_get_primary_flow_label(req_msg); - primary_path->hop_limit = req_msg->primary_hop_limit; - primary_path->traffic_class = req_msg->primary_traffic_class; - primary_path->reversible = 1; - primary_path->pkey = req_msg->pkey; - primary_path->sl = cm_req_get_primary_sl(req_msg); - primary_path->mtu_selector = IB_SA_EQ; - primary_path->mtu = cm_req_get_path_mtu(req_msg); - primary_path->rate_selector = IB_SA_EQ; - primary_path->rate = cm_req_get_primary_packet_rate(req_msg); - primary_path->packet_life_time_selector = IB_SA_EQ; - primary_path->packet_life_time = - cm_req_get_primary_local_ack_timeout(req_msg); - primary_path->packet_life_time -= (primary_path->packet_life_time > 0); - - if (req_msg->alt_local_lid) { - memset(alt_path, 0, sizeof *alt_path); - alt_path->dgid = req_msg->alt_local_gid; - alt_path->sgid = req_msg->alt_remote_gid; - alt_path->dlid = req_msg->alt_local_lid; - alt_path->slid = req_msg->alt_remote_lid; - alt_path->flow_label = cm_req_get_alt_flow_label(req_msg); - alt_path->hop_limit = req_msg->alt_hop_limit; - alt_path->traffic_class = req_msg->alt_traffic_class; - alt_path->reversible = 1; - alt_path->pkey = req_msg->pkey; - alt_path->sl = cm_req_get_alt_sl(req_msg); - alt_path->mtu_selector = IB_SA_EQ; - alt_path->mtu = cm_req_get_path_mtu(req_msg); - alt_path->rate_selector = IB_SA_EQ; - alt_path->rate = cm_req_get_alt_packet_rate(req_msg); - alt_path->packet_life_time_selector = IB_SA_EQ; - alt_path->packet_life_time = - cm_req_get_alt_local_ack_timeout(req_msg); - alt_path->packet_life_time -= (alt_path->packet_life_time > 0); - } -} - -static void cm_format_req_event(struct cm_work *work, - struct cm_id_private *cm_id_priv, - struct ib_cm_id *listen_id) -{ - struct cm_req_msg *req_msg; - struct ib_cm_req_event_param *param; - - req_msg = (struct cm_req_msg *)work->mad_recv_wc->recv_buf.mad; - param = &work->cm_event.param.req_rcvd; - param->listen_id = listen_id; - param->device = cm_id_priv->av.port->mad_agent->device; - param->port = cm_id_priv->av.port->port_num; - param->primary_path = &work->path[0]; - if (req_msg->alt_local_lid) - param->alternate_path = &work->path[1]; - else - param->alternate_path = NULL; - param->remote_ca_guid = req_msg->local_ca_guid; - param->remote_qkey = be32_to_cpu(req_msg->local_qkey); - param->remote_qpn = be32_to_cpu(cm_req_get_local_qpn(req_msg)); - param->qp_type = cm_req_get_qp_type(req_msg); - param->starting_psn = be32_to_cpu(cm_req_get_starting_psn(req_msg)); - param->responder_resources = cm_req_get_init_depth(req_msg); - param->initiator_depth = cm_req_get_resp_res(req_msg); - param->local_cm_response_timeout = - cm_req_get_remote_resp_timeout(req_msg); - param->flow_control = cm_req_get_flow_ctrl(req_msg); - param->remote_cm_response_timeout = - cm_req_get_local_resp_timeout(req_msg); - param->retry_count = cm_req_get_retry_count(req_msg); - param->rnr_retry_count = cm_req_get_rnr_retry_count(req_msg); - param->srq = cm_req_get_srq(req_msg); - work->cm_event.private_data = &req_msg->private_data; -} - -static void cm_process_work(struct cm_id_private *cm_id_priv, - struct cm_work *work) -{ - unsigned long flags; - int ret; - - /* We will typically only have the current event to report. */ - ret = cm_id_priv->id.cm_handler(&cm_id_priv->id, &work->cm_event); - cm_free_work(work); - - while (!ret && !atomic_add_negative(-1, &cm_id_priv->work_count)) { - spin_lock_irqsave(&cm_id_priv->lock, flags); - work = cm_dequeue_work(cm_id_priv); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - BUG_ON(!work); - ret = cm_id_priv->id.cm_handler(&cm_id_priv->id, - &work->cm_event); - cm_free_work(work); - } - cm_deref_id(cm_id_priv); - if (ret) - ib_destroy_cm_id(&cm_id_priv->id); -} - -static void cm_format_mra(struct cm_mra_msg *mra_msg, - struct cm_id_private *cm_id_priv, - enum cm_msg_response msg_mraed, u8 service_timeout, - const void *private_data, u8 private_data_len) -{ - cm_format_mad_hdr(&mra_msg->hdr, CM_MRA_ATTR_ID, cm_id_priv->tid); - cm_mra_set_msg_mraed(mra_msg, msg_mraed); - mra_msg->local_comm_id = cm_id_priv->id.local_id; - mra_msg->remote_comm_id = cm_id_priv->id.remote_id; - cm_mra_set_service_timeout(mra_msg, service_timeout); - - if (private_data && private_data_len) - memcpy(mra_msg->private_data, private_data, private_data_len); -} - -static void cm_format_rej(struct cm_rej_msg *rej_msg, - struct cm_id_private *cm_id_priv, - enum ib_cm_rej_reason reason, - void *ari, - u8 ari_length, - const void *private_data, - u8 private_data_len) -{ - cm_format_mad_hdr(&rej_msg->hdr, CM_REJ_ATTR_ID, cm_id_priv->tid); - rej_msg->remote_comm_id = cm_id_priv->id.remote_id; - - switch(cm_id_priv->id.state) { - case IB_CM_REQ_RCVD: - rej_msg->local_comm_id = 0; - cm_rej_set_msg_rejected(rej_msg, CM_MSG_RESPONSE_REQ); - break; - case IB_CM_MRA_REQ_SENT: - rej_msg->local_comm_id = cm_id_priv->id.local_id; - cm_rej_set_msg_rejected(rej_msg, CM_MSG_RESPONSE_REQ); - break; - case IB_CM_REP_RCVD: - case IB_CM_MRA_REP_SENT: - rej_msg->local_comm_id = cm_id_priv->id.local_id; - cm_rej_set_msg_rejected(rej_msg, CM_MSG_RESPONSE_REP); - break; - default: - rej_msg->local_comm_id = cm_id_priv->id.local_id; - cm_rej_set_msg_rejected(rej_msg, CM_MSG_RESPONSE_OTHER); - break; - } - - rej_msg->reason = reason; - if (ari && ari_length) { - cm_rej_set_reject_info_len(rej_msg, ari_length); - memcpy(rej_msg->ari, ari, ari_length); - } - - if (private_data && private_data_len) - memcpy(rej_msg->private_data, private_data, private_data_len); -} - -static void cm_dup_req_handler(struct cm_work *work, - struct cm_id_private *cm_id_priv) -{ - struct ib_mad_send_buf *msg = NULL; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - /* Quick state check to discard duplicate REQs. */ - if (cm_id_priv->id.state == IB_CM_REQ_RCVD) - return; - - ret = cm_alloc_response_msg(work->port, work->mad_recv_wc, &msg); - if (ret) - return; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id_priv->id.state) { - case IB_CM_MRA_REQ_SENT: - cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv, - CM_MSG_RESPONSE_REQ, cm_id_priv->service_timeout, - cm_id_priv->private_data, - cm_id_priv->private_data_len); - break; - case IB_CM_TIMEWAIT: - cm_format_rej((struct cm_rej_msg *) msg->mad, cm_id_priv, - IB_CM_REJ_STALE_CONN, NULL, 0, NULL, 0); - break; - default: - goto unlock; - } - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, &msg->send_wr, - &bad_send_wr); - if (ret) - goto free; - return; - -unlock: spin_unlock_irqrestore(&cm_id_priv->lock, flags); -free: cm_free_msg(msg); -} - -static struct cm_id_private * cm_match_req(struct cm_work *work, - struct cm_id_private *cm_id_priv) -{ - struct cm_id_private *listen_cm_id_priv, *cur_cm_id_priv; - struct cm_timewait_info *timewait_info; - struct cm_req_msg *req_msg; - unsigned long flags; - - req_msg = (struct cm_req_msg *)work->mad_recv_wc->recv_buf.mad; - - /* Check for duplicate REQ and stale connections. */ - spin_lock_irqsave(&cm.lock, flags); - timewait_info = cm_insert_remote_id(cm_id_priv->timewait_info); - if (!timewait_info) - timewait_info = cm_insert_remote_qpn(cm_id_priv->timewait_info); - - if (timewait_info) { - cur_cm_id_priv = cm_get_id(timewait_info->work.local_id, - timewait_info->work.remote_id); - spin_unlock_irqrestore(&cm.lock, flags); - if (cur_cm_id_priv) { - cm_dup_req_handler(work, cur_cm_id_priv); - cm_deref_id(cur_cm_id_priv); - } else - cm_issue_rej(work->port, work->mad_recv_wc, - IB_CM_REJ_STALE_CONN, CM_MSG_RESPONSE_REQ, - NULL, 0); - goto error; - } - - /* Find matching listen request. */ - listen_cm_id_priv = cm_find_listen(req_msg->service_id); - if (!listen_cm_id_priv) { - spin_unlock_irqrestore(&cm.lock, flags); - cm_issue_rej(work->port, work->mad_recv_wc, - IB_CM_REJ_INVALID_SERVICE_ID, CM_MSG_RESPONSE_REQ, - NULL, 0); - goto error; - } - atomic_inc(&listen_cm_id_priv->refcount); - atomic_inc(&cm_id_priv->refcount); - cm_id_priv->id.state = IB_CM_REQ_RCVD; - atomic_inc(&cm_id_priv->work_count); - spin_unlock_irqrestore(&cm.lock, flags); - return listen_cm_id_priv; - -error: cm_cleanup_timewait(cm_id_priv->timewait_info); - return NULL; -} - -static int cm_req_handler(struct cm_work *work) -{ - struct ib_cm_id *cm_id; - struct cm_id_private *cm_id_priv, *listen_cm_id_priv; - struct cm_req_msg *req_msg; - int ret; - - req_msg = (struct cm_req_msg *)work->mad_recv_wc->recv_buf.mad; - - cm_id = ib_create_cm_id(NULL, NULL); - if (IS_ERR(cm_id)) - return PTR_ERR(cm_id); - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - cm_id_priv->id.remote_id = req_msg->local_comm_id; - cm_init_av_for_response(work->port, work->mad_recv_wc->wc, - &cm_id_priv->av); - cm_id_priv->timewait_info = cm_create_timewait_info(cm_id_priv-> - id.local_id); - if (IS_ERR(cm_id_priv->timewait_info)) { - ret = PTR_ERR(cm_id_priv->timewait_info); - goto error1; - } - cm_id_priv->timewait_info->work.remote_id = req_msg->local_comm_id; - cm_id_priv->timewait_info->remote_ca_guid = req_msg->local_ca_guid; - cm_id_priv->timewait_info->remote_qpn = cm_req_get_local_qpn(req_msg); - - listen_cm_id_priv = cm_match_req(work, cm_id_priv); - if (!listen_cm_id_priv) { - ret = -EINVAL; - goto error2; - } - - cm_id_priv->id.cm_handler = listen_cm_id_priv->id.cm_handler; - cm_id_priv->id.context = listen_cm_id_priv->id.context; - cm_id_priv->id.service_id = req_msg->service_id; - cm_id_priv->id.service_mask = ~0ULL; - - cm_format_paths_from_req(req_msg, &work->path[0], &work->path[1]); - ret = cm_init_av_by_path(&work->path[0], &cm_id_priv->av); - if (ret) - goto error3; - if (req_msg->alt_local_lid) { - ret = cm_init_av_by_path(&work->path[1], &cm_id_priv->alt_av); - if (ret) - goto error3; - } - cm_id_priv->tid = req_msg->hdr.tid; - cm_id_priv->timeout_ms = cm_convert_to_ms( - cm_req_get_local_resp_timeout(req_msg)); - cm_id_priv->max_cm_retries = cm_req_get_max_cm_retries(req_msg); - cm_id_priv->remote_qpn = cm_req_get_local_qpn(req_msg); - cm_id_priv->initiator_depth = cm_req_get_resp_res(req_msg); - cm_id_priv->responder_resources = cm_req_get_init_depth(req_msg); - cm_id_priv->path_mtu = cm_req_get_path_mtu(req_msg); - cm_id_priv->sq_psn = cm_req_get_starting_psn(req_msg); - cm_id_priv->local_ack_timeout = - cm_req_get_primary_local_ack_timeout(req_msg); - cm_id_priv->retry_count = cm_req_get_retry_count(req_msg); - cm_id_priv->rnr_retry_count = cm_req_get_rnr_retry_count(req_msg); - - cm_format_req_event(work, cm_id_priv, &listen_cm_id_priv->id); - cm_process_work(cm_id_priv, work); - cm_deref_id(listen_cm_id_priv); - return 0; - -error3: atomic_dec(&cm_id_priv->refcount); - cm_deref_id(listen_cm_id_priv); - cm_cleanup_timewait(cm_id_priv->timewait_info); -error2: kfree(cm_id_priv->timewait_info); -error1: ib_destroy_cm_id(&cm_id_priv->id); - return ret; -} - -static void cm_format_rep(struct cm_rep_msg *rep_msg, - struct cm_id_private *cm_id_priv, - struct ib_cm_rep_param *param) -{ - cm_format_mad_hdr(&rep_msg->hdr, CM_REP_ATTR_ID, cm_id_priv->tid); - rep_msg->local_comm_id = cm_id_priv->id.local_id; - rep_msg->remote_comm_id = cm_id_priv->id.remote_id; - cm_rep_set_local_qpn(rep_msg, cpu_to_be32(param->qp_num)); - cm_rep_set_starting_psn(rep_msg, cpu_to_be32(param->starting_psn)); - rep_msg->resp_resources = param->responder_resources; - rep_msg->initiator_depth = param->initiator_depth; - cm_rep_set_target_ack_delay(rep_msg, param->target_ack_delay); - cm_rep_set_failover(rep_msg, param->failover_accepted); - cm_rep_set_flow_ctrl(rep_msg, param->flow_control); - cm_rep_set_rnr_retry_count(rep_msg, param->rnr_retry_count); - cm_rep_set_srq(rep_msg, param->srq); - rep_msg->local_ca_guid = cm_id_priv->av.port->cm_dev->ca_guid; - - if (param->private_data && param->private_data_len) - memcpy(rep_msg->private_data, param->private_data, - param->private_data_len); -} - -int ib_send_cm_rep(struct ib_cm_id *cm_id, - struct ib_cm_rep_param *param) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct cm_rep_msg *rep_msg; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - if (param->private_data && - param->private_data_len > IB_CM_REP_PRIVATE_DATA_SIZE) - return -EINVAL; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id->state != IB_CM_REQ_RCVD && - cm_id->state != IB_CM_MRA_REQ_SENT) { - ret = -EINVAL; - goto out; - } - - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto out; - - rep_msg = (struct cm_rep_msg *) msg->mad; - cm_format_rep(rep_msg, cm_id_priv, param); - msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms; - msg->context[1] = (void *) (unsigned long) IB_CM_REP_SENT; - - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_free_msg(msg); - return ret; - } - - cm_id->state = IB_CM_REP_SENT; - cm_id_priv->msg = msg; - cm_id_priv->initiator_depth = param->initiator_depth; - cm_id_priv->responder_resources = param->responder_resources; - cm_id_priv->rq_psn = cm_rep_get_starting_psn(rep_msg); - cm_id_priv->local_qpn = cm_rep_get_local_qpn(rep_msg); - -out: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} -EXPORT_SYMBOL(ib_send_cm_rep); - -static void cm_format_rtu(struct cm_rtu_msg *rtu_msg, - struct cm_id_private *cm_id_priv, - const void *private_data, - u8 private_data_len) -{ - cm_format_mad_hdr(&rtu_msg->hdr, CM_RTU_ATTR_ID, cm_id_priv->tid); - rtu_msg->local_comm_id = cm_id_priv->id.local_id; - rtu_msg->remote_comm_id = cm_id_priv->id.remote_id; - - if (private_data && private_data_len) - memcpy(rtu_msg->private_data, private_data, private_data_len); -} - -int ib_send_cm_rtu(struct ib_cm_id *cm_id, - const void *private_data, - u8 private_data_len) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - void *data; - int ret; - - if (private_data && private_data_len > IB_CM_RTU_PRIVATE_DATA_SIZE) - return -EINVAL; - - data = cm_copy_private_data(private_data, private_data_len); - if (IS_ERR(data)) - return PTR_ERR(data); - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id->state != IB_CM_REP_RCVD && - cm_id->state != IB_CM_MRA_REP_SENT) { - ret = -EINVAL; - goto error; - } - - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto error; - - cm_format_rtu((struct cm_rtu_msg *) msg->mad, cm_id_priv, - private_data, private_data_len); - - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_free_msg(msg); - kfree(data); - return ret; - } - - cm_id->state = IB_CM_ESTABLISHED; - cm_set_private_data(cm_id_priv, data, private_data_len); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return 0; - -error: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - kfree(data); - return ret; -} -EXPORT_SYMBOL(ib_send_cm_rtu); - -static void cm_format_rep_event(struct cm_work *work) -{ - struct cm_rep_msg *rep_msg; - struct ib_cm_rep_event_param *param; - - rep_msg = (struct cm_rep_msg *)work->mad_recv_wc->recv_buf.mad; - param = &work->cm_event.param.rep_rcvd; - param->remote_ca_guid = rep_msg->local_ca_guid; - param->remote_qkey = be32_to_cpu(rep_msg->local_qkey); - param->remote_qpn = be32_to_cpu(cm_rep_get_local_qpn(rep_msg)); - param->starting_psn = be32_to_cpu(cm_rep_get_starting_psn(rep_msg)); - param->responder_resources = rep_msg->initiator_depth; - param->initiator_depth = rep_msg->resp_resources; - param->target_ack_delay = cm_rep_get_target_ack_delay(rep_msg); - param->failover_accepted = cm_rep_get_failover(rep_msg); - param->flow_control = cm_rep_get_flow_ctrl(rep_msg); - param->rnr_retry_count = cm_rep_get_rnr_retry_count(rep_msg); - param->srq = cm_rep_get_srq(rep_msg); - work->cm_event.private_data = &rep_msg->private_data; -} - -static void cm_dup_rep_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - struct cm_rep_msg *rep_msg; - struct ib_mad_send_buf *msg = NULL; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - rep_msg = (struct cm_rep_msg *) work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_id(rep_msg->remote_comm_id, - rep_msg->local_comm_id); - if (!cm_id_priv) - return; - - ret = cm_alloc_response_msg(work->port, work->mad_recv_wc, &msg); - if (ret) - goto deref; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id_priv->id.state == IB_CM_ESTABLISHED) - cm_format_rtu((struct cm_rtu_msg *) msg->mad, cm_id_priv, - cm_id_priv->private_data, - cm_id_priv->private_data_len); - else if (cm_id_priv->id.state == IB_CM_MRA_REP_SENT) - cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv, - CM_MSG_RESPONSE_REP, cm_id_priv->service_timeout, - cm_id_priv->private_data, - cm_id_priv->private_data_len); - else - goto unlock; - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, &msg->send_wr, - &bad_send_wr); - if (ret) - goto free; - goto deref; - -unlock: spin_unlock_irqrestore(&cm_id_priv->lock, flags); -free: cm_free_msg(msg); -deref: cm_deref_id(cm_id_priv); -} - -static int cm_rep_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - struct cm_rep_msg *rep_msg; - unsigned long flags; - int ret; - - rep_msg = (struct cm_rep_msg *)work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_id(rep_msg->remote_comm_id, 0); - if (!cm_id_priv) { - cm_dup_rep_handler(work); - return -EINVAL; - } - - cm_id_priv->timewait_info->work.remote_id = rep_msg->local_comm_id; - cm_id_priv->timewait_info->remote_ca_guid = rep_msg->local_ca_guid; - cm_id_priv->timewait_info->remote_qpn = cm_rep_get_local_qpn(rep_msg); - - spin_lock_irqsave(&cm.lock, flags); - /* Check for duplicate REP. */ - if (cm_insert_remote_id(cm_id_priv->timewait_info)) { - spin_unlock_irqrestore(&cm.lock, flags); - ret = -EINVAL; - goto error; - } - /* Check for a stale connection. */ - if (cm_insert_remote_qpn(cm_id_priv->timewait_info)) { - spin_unlock_irqrestore(&cm.lock, flags); - cm_issue_rej(work->port, work->mad_recv_wc, - IB_CM_REJ_STALE_CONN, CM_MSG_RESPONSE_REP, - NULL, 0); - ret = -EINVAL; - goto error; - } - spin_unlock_irqrestore(&cm.lock, flags); - - cm_format_rep_event(work); - - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id_priv->id.state) { - case IB_CM_REQ_SENT: - case IB_CM_MRA_REQ_RCVD: - break; - default: - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - ret = -EINVAL; - goto error; - } - cm_id_priv->id.state = IB_CM_REP_RCVD; - cm_id_priv->id.remote_id = rep_msg->local_comm_id; - cm_id_priv->remote_qpn = cm_rep_get_local_qpn(rep_msg); - cm_id_priv->initiator_depth = rep_msg->resp_resources; - cm_id_priv->responder_resources = rep_msg->initiator_depth; - cm_id_priv->sq_psn = cm_rep_get_starting_psn(rep_msg); - cm_id_priv->rnr_retry_count = cm_rep_get_rnr_retry_count(rep_msg); - - /* todo: handle peer_to_peer */ - - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; - -error: cm_cleanup_timewait(cm_id_priv->timewait_info); - cm_deref_id(cm_id_priv); - return ret; -} - -static int cm_establish_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - unsigned long flags; - int ret; - - /* See comment in ib_cm_establish about lookup. */ - cm_id_priv = cm_acquire_id(work->local_id, work->remote_id); - if (!cm_id_priv) - return -EINVAL; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id_priv->id.state != IB_CM_ESTABLISHED) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - goto out; - } - - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; -out: - cm_deref_id(cm_id_priv); - return -EINVAL; -} - -static int cm_rtu_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - struct cm_rtu_msg *rtu_msg; - unsigned long flags; - int ret; - - rtu_msg = (struct cm_rtu_msg *)work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_id(rtu_msg->remote_comm_id, - rtu_msg->local_comm_id); - if (!cm_id_priv) - return -EINVAL; - - work->cm_event.private_data = &rtu_msg->private_data; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id_priv->id.state != IB_CM_REP_SENT && - cm_id_priv->id.state != IB_CM_MRA_REP_RCVD) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - goto out; - } - cm_id_priv->id.state = IB_CM_ESTABLISHED; - - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; -out: - cm_deref_id(cm_id_priv); - return -EINVAL; -} - -static void cm_format_dreq(struct cm_dreq_msg *dreq_msg, - struct cm_id_private *cm_id_priv, - const void *private_data, - u8 private_data_len) -{ - cm_format_mad_hdr(&dreq_msg->hdr, CM_DREQ_ATTR_ID, - cm_form_tid(cm_id_priv, CM_MSG_SEQUENCE_DREQ)); - dreq_msg->local_comm_id = cm_id_priv->id.local_id; - dreq_msg->remote_comm_id = cm_id_priv->id.remote_id; - cm_dreq_set_remote_qpn(dreq_msg, cm_id_priv->remote_qpn); - - if (private_data && private_data_len) - memcpy(dreq_msg->private_data, private_data, private_data_len); -} - -int ib_send_cm_dreq(struct ib_cm_id *cm_id, - const void *private_data, - u8 private_data_len) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - if (private_data && private_data_len > IB_CM_DREQ_PRIVATE_DATA_SIZE) - return -EINVAL; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id->state != IB_CM_ESTABLISHED) { - ret = -EINVAL; - goto out; - } - - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) { - cm_enter_timewait(cm_id_priv); - goto out; - } - - cm_format_dreq((struct cm_dreq_msg *) msg->mad, cm_id_priv, - private_data, private_data_len); - msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms; - msg->context[1] = (void *) (unsigned long) IB_CM_DREQ_SENT; - - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) { - cm_enter_timewait(cm_id_priv); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_free_msg(msg); - return ret; - } - - cm_id->state = IB_CM_DREQ_SENT; - cm_id_priv->msg = msg; -out: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} -EXPORT_SYMBOL(ib_send_cm_dreq); - -static void cm_format_drep(struct cm_drep_msg *drep_msg, - struct cm_id_private *cm_id_priv, - const void *private_data, - u8 private_data_len) -{ - cm_format_mad_hdr(&drep_msg->hdr, CM_DREP_ATTR_ID, cm_id_priv->tid); - drep_msg->local_comm_id = cm_id_priv->id.local_id; - drep_msg->remote_comm_id = cm_id_priv->id.remote_id; - - if (private_data && private_data_len) - memcpy(drep_msg->private_data, private_data, private_data_len); -} - -int ib_send_cm_drep(struct ib_cm_id *cm_id, - const void *private_data, - u8 private_data_len) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - void *data; - int ret; - - if (private_data && private_data_len > IB_CM_DREP_PRIVATE_DATA_SIZE) - return -EINVAL; - - data = cm_copy_private_data(private_data, private_data_len); - if (IS_ERR(data)) - return PTR_ERR(data); - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id->state != IB_CM_DREQ_RCVD) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - kfree(data); - return -EINVAL; - } - - cm_set_private_data(cm_id_priv, data, private_data_len); - cm_enter_timewait(cm_id_priv); - - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto out; - - cm_format_drep((struct cm_drep_msg *) msg->mad, cm_id_priv, - private_data, private_data_len); - - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, &msg->send_wr, - &bad_send_wr); - if (ret) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_free_msg(msg); - return ret; - } - -out: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} -EXPORT_SYMBOL(ib_send_cm_drep); - -static int cm_dreq_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - struct cm_dreq_msg *dreq_msg; - struct ib_mad_send_buf *msg = NULL; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - dreq_msg = (struct cm_dreq_msg *)work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_id(dreq_msg->remote_comm_id, - dreq_msg->local_comm_id); - if (!cm_id_priv) - return -EINVAL; - - work->cm_event.private_data = &dreq_msg->private_data; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id_priv->local_qpn != cm_dreq_get_remote_qpn(dreq_msg)) - goto unlock; - - switch (cm_id_priv->id.state) { - case IB_CM_REP_SENT: - case IB_CM_DREQ_SENT: - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - break; - case IB_CM_ESTABLISHED: - case IB_CM_MRA_REP_RCVD: - break; - case IB_CM_TIMEWAIT: - if (cm_alloc_response_msg(work->port, work->mad_recv_wc, &msg)) - goto unlock; - - cm_format_drep((struct cm_drep_msg *) msg->mad, cm_id_priv, - cm_id_priv->private_data, - cm_id_priv->private_data_len); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr)) - cm_free_msg(msg); - goto deref; - default: - goto unlock; - } - cm_id_priv->id.state = IB_CM_DREQ_RCVD; - cm_id_priv->tid = dreq_msg->hdr.tid; - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; - -unlock: spin_unlock_irqrestore(&cm_id_priv->lock, flags); -deref: cm_deref_id(cm_id_priv); - return -EINVAL; -} - -static int cm_drep_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - struct cm_drep_msg *drep_msg; - unsigned long flags; - int ret; - - drep_msg = (struct cm_drep_msg *)work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_id(drep_msg->remote_comm_id, - drep_msg->local_comm_id); - if (!cm_id_priv) - return -EINVAL; - - work->cm_event.private_data = &drep_msg->private_data; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id_priv->id.state != IB_CM_DREQ_SENT && - cm_id_priv->id.state != IB_CM_DREQ_RCVD) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - goto out; - } - cm_enter_timewait(cm_id_priv); - - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; -out: - cm_deref_id(cm_id_priv); - return -EINVAL; -} - -int ib_send_cm_rej(struct ib_cm_id *cm_id, - enum ib_cm_rej_reason reason, - void *ari, - u8 ari_length, - const void *private_data, - u8 private_data_len) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - if ((private_data && private_data_len > IB_CM_REJ_PRIVATE_DATA_SIZE) || - (ari && ari_length > IB_CM_REJ_ARI_LENGTH)) - return -EINVAL; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id->state) { - case IB_CM_REQ_SENT: - case IB_CM_MRA_REQ_RCVD: - case IB_CM_REQ_RCVD: - case IB_CM_MRA_REQ_SENT: - case IB_CM_REP_RCVD: - case IB_CM_MRA_REP_SENT: - ret = cm_alloc_msg(cm_id_priv, &msg); - if (!ret) - cm_format_rej((struct cm_rej_msg *) msg->mad, - cm_id_priv, reason, ari, ari_length, - private_data, private_data_len); - - cm_reset_to_idle(cm_id_priv); - break; - case IB_CM_REP_SENT: - case IB_CM_MRA_REP_RCVD: - ret = cm_alloc_msg(cm_id_priv, &msg); - if (!ret) - cm_format_rej((struct cm_rej_msg *) msg->mad, - cm_id_priv, reason, ari, ari_length, - private_data, private_data_len); - - cm_enter_timewait(cm_id_priv); - break; - default: - ret = -EINVAL; - goto out; - } - - if (ret) - goto out; - - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) - cm_free_msg(msg); - -out: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} -EXPORT_SYMBOL(ib_send_cm_rej); - -static void cm_format_rej_event(struct cm_work *work) -{ - struct cm_rej_msg *rej_msg; - struct ib_cm_rej_event_param *param; - - rej_msg = (struct cm_rej_msg *)work->mad_recv_wc->recv_buf.mad; - param = &work->cm_event.param.rej_rcvd; - param->ari = rej_msg->ari; - param->ari_length = cm_rej_get_reject_info_len(rej_msg); - param->reason = rej_msg->reason; - work->cm_event.private_data = &rej_msg->private_data; -} - -static struct cm_id_private * cm_acquire_rejected_id(struct cm_rej_msg *rej_msg) -{ - struct cm_timewait_info *timewait_info; - struct cm_id_private *cm_id_priv; - unsigned long flags; - u32 remote_id; - - remote_id = rej_msg->local_comm_id; - - if (rej_msg->reason == IB_CM_REJ_TIMEOUT) { - spin_lock_irqsave(&cm.lock, flags); - timewait_info = cm_find_remote_id( *((u64 *) rej_msg->ari), - remote_id); - if (!timewait_info) { - spin_unlock_irqrestore(&cm.lock, flags); - return NULL; - } - cm_id_priv = idr_find(&cm.local_id_table, - (int) timewait_info->work.local_id); - if (cm_id_priv) { - if (cm_id_priv->id.remote_id == remote_id) - atomic_inc(&cm_id_priv->refcount); - else - cm_id_priv = NULL; - } - spin_unlock_irqrestore(&cm.lock, flags); - } else if (cm_rej_get_msg_rejected(rej_msg) == CM_MSG_RESPONSE_REQ) - cm_id_priv = cm_acquire_id(rej_msg->remote_comm_id, 0); - else - cm_id_priv = cm_acquire_id(rej_msg->remote_comm_id, remote_id); - - return cm_id_priv; -} - -static int cm_rej_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - struct cm_rej_msg *rej_msg; - unsigned long flags; - int ret; - - rej_msg = (struct cm_rej_msg *)work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_rejected_id(rej_msg); - if (!cm_id_priv) - return -EINVAL; - - cm_format_rej_event(work); - - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id_priv->id.state) { - case IB_CM_REQ_SENT: - case IB_CM_MRA_REQ_RCVD: - case IB_CM_REP_SENT: - case IB_CM_MRA_REP_RCVD: - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - /* fall through */ - case IB_CM_REQ_RCVD: - case IB_CM_MRA_REQ_SENT: - if (rej_msg->reason == IB_CM_REJ_STALE_CONN) - cm_enter_timewait(cm_id_priv); - else - cm_reset_to_idle(cm_id_priv); - break; - case IB_CM_DREQ_SENT: - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - /* fall through */ - case IB_CM_REP_RCVD: - case IB_CM_MRA_REP_SENT: - case IB_CM_ESTABLISHED: - cm_enter_timewait(cm_id_priv); - break; - default: - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - ret = -EINVAL; - goto out; - } - - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; -out: - cm_deref_id(cm_id_priv); - return -EINVAL; -} - -int ib_send_cm_mra(struct ib_cm_id *cm_id, - u8 service_timeout, - const void *private_data, - u8 private_data_len) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - void *data; - unsigned long flags; - int ret; - - if (private_data && private_data_len > IB_CM_MRA_PRIVATE_DATA_SIZE) - return -EINVAL; - - data = cm_copy_private_data(private_data, private_data_len); - if (IS_ERR(data)) - return PTR_ERR(data); - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch(cm_id_priv->id.state) { - case IB_CM_REQ_RCVD: - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto error1; - - cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv, - CM_MSG_RESPONSE_REQ, service_timeout, - private_data, private_data_len); - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) - goto error2; - cm_id->state = IB_CM_MRA_REQ_SENT; - break; - case IB_CM_REP_RCVD: - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto error1; - - cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv, - CM_MSG_RESPONSE_REP, service_timeout, - private_data, private_data_len); - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) - goto error2; - cm_id->state = IB_CM_MRA_REP_SENT; - break; - case IB_CM_ESTABLISHED: - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto error1; - - cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv, - CM_MSG_RESPONSE_OTHER, service_timeout, - private_data, private_data_len); - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) - goto error2; - cm_id->lap_state = IB_CM_MRA_LAP_SENT; - break; - default: - ret = -EINVAL; - goto error1; - } - cm_id_priv->service_timeout = service_timeout; - cm_set_private_data(cm_id_priv, data, private_data_len); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return 0; - -error1: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - kfree(data); - return ret; - -error2: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - kfree(data); - cm_free_msg(msg); - return ret; -} -EXPORT_SYMBOL(ib_send_cm_mra); - -static struct cm_id_private * cm_acquire_mraed_id(struct cm_mra_msg *mra_msg) -{ - switch (cm_mra_get_msg_mraed(mra_msg)) { - case CM_MSG_RESPONSE_REQ: - return cm_acquire_id(mra_msg->remote_comm_id, 0); - case CM_MSG_RESPONSE_REP: - case CM_MSG_RESPONSE_OTHER: - return cm_acquire_id(mra_msg->remote_comm_id, - mra_msg->local_comm_id); - default: - return NULL; - } -} - -static int cm_mra_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - struct cm_mra_msg *mra_msg; - unsigned long flags; - int timeout, ret; - - mra_msg = (struct cm_mra_msg *)work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_mraed_id(mra_msg); - if (!cm_id_priv) - return -EINVAL; - - work->cm_event.private_data = &mra_msg->private_data; - work->cm_event.param.mra_rcvd.service_timeout = - cm_mra_get_service_timeout(mra_msg); - timeout = cm_convert_to_ms(cm_mra_get_service_timeout(mra_msg)) + - cm_convert_to_ms(cm_id_priv->av.packet_life_time); - - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id_priv->id.state) { - case IB_CM_REQ_SENT: - if (cm_mra_get_msg_mraed(mra_msg) != CM_MSG_RESPONSE_REQ || - ib_modify_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg, timeout)) - goto out; - cm_id_priv->id.state = IB_CM_MRA_REQ_RCVD; - break; - case IB_CM_REP_SENT: - if (cm_mra_get_msg_mraed(mra_msg) != CM_MSG_RESPONSE_REP || - ib_modify_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg, timeout)) - goto out; - cm_id_priv->id.state = IB_CM_MRA_REP_RCVD; - break; - case IB_CM_ESTABLISHED: - if (cm_mra_get_msg_mraed(mra_msg) != CM_MSG_RESPONSE_OTHER || - cm_id_priv->id.lap_state != IB_CM_LAP_SENT || - ib_modify_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg, timeout)) - goto out; - cm_id_priv->id.lap_state = IB_CM_MRA_LAP_RCVD; - break; - default: - goto out; - } - - cm_id_priv->msg->context[1] = (void *) (unsigned long) - cm_id_priv->id.state; - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; -out: - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_deref_id(cm_id_priv); - return -EINVAL; -} - -static void cm_format_lap(struct cm_lap_msg *lap_msg, - struct cm_id_private *cm_id_priv, - struct ib_sa_path_rec *alternate_path, - const void *private_data, - u8 private_data_len) -{ - cm_format_mad_hdr(&lap_msg->hdr, CM_LAP_ATTR_ID, - cm_form_tid(cm_id_priv, CM_MSG_SEQUENCE_LAP)); - lap_msg->local_comm_id = cm_id_priv->id.local_id; - lap_msg->remote_comm_id = cm_id_priv->id.remote_id; - cm_lap_set_remote_qpn(lap_msg, cm_id_priv->remote_qpn); - /* todo: need remote CM response timeout */ - cm_lap_set_remote_resp_timeout(lap_msg, 0x1F); - lap_msg->alt_local_lid = alternate_path->slid; - lap_msg->alt_remote_lid = alternate_path->dlid; - lap_msg->alt_local_gid = alternate_path->sgid; - lap_msg->alt_remote_gid = alternate_path->dgid; - cm_lap_set_flow_label(lap_msg, alternate_path->flow_label); - cm_lap_set_traffic_class(lap_msg, alternate_path->traffic_class); - lap_msg->alt_hop_limit = alternate_path->hop_limit; - cm_lap_set_packet_rate(lap_msg, alternate_path->rate); - cm_lap_set_sl(lap_msg, alternate_path->sl); - cm_lap_set_subnet_local(lap_msg, 1); /* local only... */ - cm_lap_set_local_ack_timeout(lap_msg, - min(31, alternate_path->packet_life_time + 1)); - - if (private_data && private_data_len) - memcpy(lap_msg->private_data, private_data, private_data_len); -} - -int ib_send_cm_lap(struct ib_cm_id *cm_id, - struct ib_sa_path_rec *alternate_path, - const void *private_data, - u8 private_data_len) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - if (private_data && private_data_len > IB_CM_LAP_PRIVATE_DATA_SIZE) - return -EINVAL; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id->state != IB_CM_ESTABLISHED || - cm_id->lap_state != IB_CM_LAP_IDLE) { - ret = -EINVAL; - goto out; - } - - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto out; - - cm_format_lap((struct cm_lap_msg *) msg->mad, cm_id_priv, - alternate_path, private_data, private_data_len); - msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms; - msg->context[1] = (void *) (unsigned long) IB_CM_ESTABLISHED; - - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_free_msg(msg); - return ret; - } - - cm_id->lap_state = IB_CM_LAP_SENT; - cm_id_priv->msg = msg; - -out: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} -EXPORT_SYMBOL(ib_send_cm_lap); - -static void cm_format_path_from_lap(struct ib_sa_path_rec *path, - struct cm_lap_msg *lap_msg) -{ - memset(path, 0, sizeof *path); - path->dgid = lap_msg->alt_local_gid; - path->sgid = lap_msg->alt_remote_gid; - path->dlid = lap_msg->alt_local_lid; - path->slid = lap_msg->alt_remote_lid; - path->flow_label = cm_lap_get_flow_label(lap_msg); - path->hop_limit = lap_msg->alt_hop_limit; - path->traffic_class = cm_lap_get_traffic_class(lap_msg); - path->reversible = 1; - /* pkey is same as in REQ */ - path->sl = cm_lap_get_sl(lap_msg); - path->mtu_selector = IB_SA_EQ; - /* mtu is same as in REQ */ - path->rate_selector = IB_SA_EQ; - path->rate = cm_lap_get_packet_rate(lap_msg); - path->packet_life_time_selector = IB_SA_EQ; - path->packet_life_time = cm_lap_get_local_ack_timeout(lap_msg); - path->packet_life_time -= (path->packet_life_time > 0); -} - -static int cm_lap_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - struct cm_lap_msg *lap_msg; - struct ib_cm_lap_event_param *param; - struct ib_mad_send_buf *msg = NULL; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - /* todo: verify LAP request and send reject APR if invalid. */ - lap_msg = (struct cm_lap_msg *)work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_id(lap_msg->remote_comm_id, - lap_msg->local_comm_id); - if (!cm_id_priv) - return -EINVAL; - - param = &work->cm_event.param.lap_rcvd; - param->alternate_path = &work->path[0]; - cm_format_path_from_lap(param->alternate_path, lap_msg); - work->cm_event.private_data = &lap_msg->private_data; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id_priv->id.state != IB_CM_ESTABLISHED) - goto unlock; - - switch (cm_id_priv->id.lap_state) { - case IB_CM_LAP_IDLE: - break; - case IB_CM_MRA_LAP_SENT: - if (cm_alloc_response_msg(work->port, work->mad_recv_wc, &msg)) - goto unlock; - - cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv, - CM_MSG_RESPONSE_OTHER, - cm_id_priv->service_timeout, - cm_id_priv->private_data, - cm_id_priv->private_data_len); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr)) - cm_free_msg(msg); - goto deref; - default: - goto unlock; - } - - cm_id_priv->id.lap_state = IB_CM_LAP_RCVD; - cm_id_priv->tid = lap_msg->hdr.tid; - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; - -unlock: spin_unlock_irqrestore(&cm_id_priv->lock, flags); -deref: cm_deref_id(cm_id_priv); - return -EINVAL; -} - -static void cm_format_apr(struct cm_apr_msg *apr_msg, - struct cm_id_private *cm_id_priv, - enum ib_cm_apr_status status, - void *info, - u8 info_length, - const void *private_data, - u8 private_data_len) -{ - cm_format_mad_hdr(&apr_msg->hdr, CM_APR_ATTR_ID, cm_id_priv->tid); - apr_msg->local_comm_id = cm_id_priv->id.local_id; - apr_msg->remote_comm_id = cm_id_priv->id.remote_id; - apr_msg->ap_status = (u8) status; - - if (info && info_length) { - apr_msg->info_length = info_length; - memcpy(apr_msg->info, info, info_length); - } - - if (private_data && private_data_len) - memcpy(apr_msg->private_data, private_data, private_data_len); -} - -int ib_send_cm_apr(struct ib_cm_id *cm_id, - enum ib_cm_apr_status status, - void *info, - u8 info_length, - const void *private_data, - u8 private_data_len) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - if ((private_data && private_data_len > IB_CM_APR_PRIVATE_DATA_SIZE) || - (info && info_length > IB_CM_APR_INFO_LENGTH)) - return -EINVAL; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id->state != IB_CM_ESTABLISHED || - (cm_id->lap_state != IB_CM_LAP_RCVD && - cm_id->lap_state != IB_CM_MRA_LAP_SENT)) { - ret = -EINVAL; - goto out; - } - - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto out; - - cm_format_apr((struct cm_apr_msg *) msg->mad, cm_id_priv, status, - info, info_length, private_data, private_data_len); - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_free_msg(msg); - return ret; - } - - cm_id->lap_state = IB_CM_LAP_IDLE; -out: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} -EXPORT_SYMBOL(ib_send_cm_apr); - -static int cm_apr_handler(struct cm_work *work) -{ - struct cm_id_private *cm_id_priv; - struct cm_apr_msg *apr_msg; - unsigned long flags; - int ret; - - apr_msg = (struct cm_apr_msg *)work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_id(apr_msg->remote_comm_id, - apr_msg->local_comm_id); - if (!cm_id_priv) - return -EINVAL; /* Unmatched reply. */ - - work->cm_event.param.apr_rcvd.ap_status = apr_msg->ap_status; - work->cm_event.param.apr_rcvd.apr_info = &apr_msg->info; - work->cm_event.param.apr_rcvd.info_len = apr_msg->info_length; - work->cm_event.private_data = &apr_msg->private_data; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id_priv->id.state != IB_CM_ESTABLISHED || - (cm_id_priv->id.lap_state != IB_CM_LAP_SENT && - cm_id_priv->id.lap_state != IB_CM_MRA_LAP_RCVD)) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - goto out; - } - cm_id_priv->id.lap_state = IB_CM_LAP_IDLE; - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - cm_id_priv->msg = NULL; - - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; -out: - cm_deref_id(cm_id_priv); - return -EINVAL; -} - -static int cm_timewait_handler(struct cm_work *work) -{ - struct cm_timewait_info *timewait_info; - struct cm_id_private *cm_id_priv; - unsigned long flags; - int ret; - - timewait_info = (struct cm_timewait_info *)work; - cm_cleanup_timewait(timewait_info); - - cm_id_priv = cm_acquire_id(timewait_info->work.local_id, - timewait_info->work.remote_id); - if (!cm_id_priv) - return -EINVAL; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id_priv->id.state != IB_CM_TIMEWAIT || - cm_id_priv->remote_qpn != timewait_info->remote_qpn) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - goto out; - } - cm_id_priv->id.state = IB_CM_IDLE; - ret = atomic_inc_and_test(&cm_id_priv->work_count); - if (!ret) - list_add_tail(&work->list, &cm_id_priv->work_list); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) - cm_process_work(cm_id_priv, work); - else - cm_deref_id(cm_id_priv); - return 0; -out: - cm_deref_id(cm_id_priv); - return -EINVAL; -} - -static void cm_format_sidr_req(struct cm_sidr_req_msg *sidr_req_msg, - struct cm_id_private *cm_id_priv, - struct ib_cm_sidr_req_param *param) -{ - cm_format_mad_hdr(&sidr_req_msg->hdr, CM_SIDR_REQ_ATTR_ID, - cm_form_tid(cm_id_priv, CM_MSG_SEQUENCE_SIDR)); - sidr_req_msg->request_id = cm_id_priv->id.local_id; - sidr_req_msg->pkey = param->pkey; - sidr_req_msg->service_id = param->service_id; - - if (param->private_data && param->private_data_len) - memcpy(sidr_req_msg->private_data, param->private_data, - param->private_data_len); -} - -int ib_send_cm_sidr_req(struct ib_cm_id *cm_id, - struct ib_cm_sidr_req_param *param) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - if (!param->path || (param->private_data && - param->private_data_len > IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE)) - return -EINVAL; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - ret = cm_init_av_by_path(param->path, &cm_id_priv->av); - if (ret) - goto out; - - cm_id->service_id = param->service_id; - cm_id->service_mask = ~0ULL; - cm_id_priv->timeout_ms = param->timeout_ms; - cm_id_priv->max_cm_retries = param->max_cm_retries; - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto out; - - cm_format_sidr_req((struct cm_sidr_req_msg *) msg->mad, cm_id_priv, - param); - msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms; - msg->context[1] = (void *) (unsigned long) IB_CM_SIDR_REQ_SENT; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id->state == IB_CM_IDLE) - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - else - ret = -EINVAL; - - if (ret) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_free_msg(msg); - goto out; - } - cm_id->state = IB_CM_SIDR_REQ_SENT; - cm_id_priv->msg = msg; - spin_unlock_irqrestore(&cm_id_priv->lock, flags); -out: - return ret; -} -EXPORT_SYMBOL(ib_send_cm_sidr_req); - -static void cm_format_sidr_req_event(struct cm_work *work, - struct ib_cm_id *listen_id) -{ - struct cm_sidr_req_msg *sidr_req_msg; - struct ib_cm_sidr_req_event_param *param; - - sidr_req_msg = (struct cm_sidr_req_msg *) - work->mad_recv_wc->recv_buf.mad; - param = &work->cm_event.param.sidr_req_rcvd; - param->pkey = sidr_req_msg->pkey; - param->listen_id = listen_id; - param->device = work->port->mad_agent->device; - param->port = work->port->port_num; - work->cm_event.private_data = &sidr_req_msg->private_data; -} - -static int cm_sidr_req_handler(struct cm_work *work) -{ - struct ib_cm_id *cm_id; - struct cm_id_private *cm_id_priv, *cur_cm_id_priv; - struct cm_sidr_req_msg *sidr_req_msg; - struct ib_wc *wc; - unsigned long flags; - - cm_id = ib_create_cm_id(NULL, NULL); - if (IS_ERR(cm_id)) - return PTR_ERR(cm_id); - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - - /* Record SGID/SLID and request ID for lookup. */ - sidr_req_msg = (struct cm_sidr_req_msg *) - work->mad_recv_wc->recv_buf.mad; - wc = work->mad_recv_wc->wc; - cm_id_priv->av.dgid.global.subnet_prefix = wc->slid; - cm_id_priv->av.dgid.global.interface_id = 0; - cm_init_av_for_response(work->port, work->mad_recv_wc->wc, - &cm_id_priv->av); - cm_id_priv->id.remote_id = sidr_req_msg->request_id; - cm_id_priv->id.state = IB_CM_SIDR_REQ_RCVD; - cm_id_priv->tid = sidr_req_msg->hdr.tid; - atomic_inc(&cm_id_priv->work_count); - - spin_lock_irqsave(&cm.lock, flags); - cur_cm_id_priv = cm_insert_remote_sidr(cm_id_priv); - if (cur_cm_id_priv) { - spin_unlock_irqrestore(&cm.lock, flags); - goto out; /* Duplicate message. */ - } - cur_cm_id_priv = cm_find_listen(sidr_req_msg->service_id); - if (!cur_cm_id_priv) { - rb_erase(&cm_id_priv->sidr_id_node, &cm.remote_sidr_table); - spin_unlock_irqrestore(&cm.lock, flags); - /* todo: reply with no match */ - goto out; /* No match. */ - } - atomic_inc(&cur_cm_id_priv->refcount); - spin_unlock_irqrestore(&cm.lock, flags); - - cm_id_priv->id.cm_handler = cur_cm_id_priv->id.cm_handler; - cm_id_priv->id.context = cur_cm_id_priv->id.context; - cm_id_priv->id.service_id = sidr_req_msg->service_id; - cm_id_priv->id.service_mask = ~0ULL; - - cm_format_sidr_req_event(work, &cur_cm_id_priv->id); - cm_process_work(cm_id_priv, work); - cm_deref_id(cur_cm_id_priv); - return 0; -out: - ib_destroy_cm_id(&cm_id_priv->id); - return -EINVAL; -} - -static void cm_format_sidr_rep(struct cm_sidr_rep_msg *sidr_rep_msg, - struct cm_id_private *cm_id_priv, - struct ib_cm_sidr_rep_param *param) -{ - cm_format_mad_hdr(&sidr_rep_msg->hdr, CM_SIDR_REP_ATTR_ID, - cm_id_priv->tid); - sidr_rep_msg->request_id = cm_id_priv->id.remote_id; - sidr_rep_msg->status = param->status; - cm_sidr_rep_set_qpn(sidr_rep_msg, cpu_to_be32(param->qp_num)); - sidr_rep_msg->service_id = cm_id_priv->id.service_id; - sidr_rep_msg->qkey = cpu_to_be32(param->qkey); - - if (param->info && param->info_length) - memcpy(sidr_rep_msg->info, param->info, param->info_length); - - if (param->private_data && param->private_data_len) - memcpy(sidr_rep_msg->private_data, param->private_data, - param->private_data_len); -} - -int ib_send_cm_sidr_rep(struct ib_cm_id *cm_id, - struct ib_cm_sidr_rep_param *param) -{ - struct cm_id_private *cm_id_priv; - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - unsigned long flags; - int ret; - - if ((param->info && param->info_length > IB_CM_SIDR_REP_INFO_LENGTH) || - (param->private_data && - param->private_data_len > IB_CM_SIDR_REP_PRIVATE_DATA_SIZE)) - return -EINVAL; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id->state != IB_CM_SIDR_REQ_RCVD) { - ret = -EINVAL; - goto error; - } - - ret = cm_alloc_msg(cm_id_priv, &msg); - if (ret) - goto error; - - cm_format_sidr_rep((struct cm_sidr_rep_msg *) msg->mad, cm_id_priv, - param); - ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, - &msg->send_wr, &bad_send_wr); - if (ret) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_free_msg(msg); - return ret; - } - cm_id->state = IB_CM_IDLE; - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - spin_lock_irqsave(&cm.lock, flags); - rb_erase(&cm_id_priv->sidr_id_node, &cm.remote_sidr_table); - spin_unlock_irqrestore(&cm.lock, flags); - return 0; - -error: spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} -EXPORT_SYMBOL(ib_send_cm_sidr_rep); - -static void cm_format_sidr_rep_event(struct cm_work *work) -{ - struct cm_sidr_rep_msg *sidr_rep_msg; - struct ib_cm_sidr_rep_event_param *param; - - sidr_rep_msg = (struct cm_sidr_rep_msg *) - work->mad_recv_wc->recv_buf.mad; - param = &work->cm_event.param.sidr_rep_rcvd; - param->status = sidr_rep_msg->status; - param->qkey = be32_to_cpu(sidr_rep_msg->qkey); - param->qpn = be32_to_cpu(cm_sidr_rep_get_qpn(sidr_rep_msg)); - param->info = &sidr_rep_msg->info; - param->info_len = sidr_rep_msg->info_length; - work->cm_event.private_data = &sidr_rep_msg->private_data; -} - -static int cm_sidr_rep_handler(struct cm_work *work) -{ - struct cm_sidr_rep_msg *sidr_rep_msg; - struct cm_id_private *cm_id_priv; - unsigned long flags; - - sidr_rep_msg = (struct cm_sidr_rep_msg *) - work->mad_recv_wc->recv_buf.mad; - cm_id_priv = cm_acquire_id(sidr_rep_msg->request_id, 0); - if (!cm_id_priv) - return -EINVAL; /* Unmatched reply. */ - - spin_lock_irqsave(&cm_id_priv->lock, flags); - if (cm_id_priv->id.state != IB_CM_SIDR_REQ_SENT) { - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - goto out; - } - cm_id_priv->id.state = IB_CM_IDLE; - ib_cancel_mad(cm_id_priv->av.port->mad_agent, - (unsigned long) cm_id_priv->msg); - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - cm_format_sidr_rep_event(work); - cm_process_work(cm_id_priv, work); - return 0; -out: - cm_deref_id(cm_id_priv); - return -EINVAL; -} - -static void cm_process_send_error(struct ib_mad_send_buf *msg, - enum ib_wc_status wc_status) -{ - struct cm_id_private *cm_id_priv; - struct ib_cm_event cm_event; - enum ib_cm_state state; - unsigned long flags; - int ret; - - memset(&cm_event, 0, sizeof cm_event); - cm_id_priv = msg->context[0]; - - /* Discard old sends or ones without a response. */ - spin_lock_irqsave(&cm_id_priv->lock, flags); - state = (enum ib_cm_state) (unsigned long) msg->context[1]; - if (msg != cm_id_priv->msg || state != cm_id_priv->id.state) - goto discard; - - switch (state) { - case IB_CM_REQ_SENT: - case IB_CM_MRA_REQ_RCVD: - cm_reset_to_idle(cm_id_priv); - cm_event.event = IB_CM_REQ_ERROR; - break; - case IB_CM_REP_SENT: - case IB_CM_MRA_REP_RCVD: - cm_reset_to_idle(cm_id_priv); - cm_event.event = IB_CM_REP_ERROR; - break; - case IB_CM_DREQ_SENT: - cm_enter_timewait(cm_id_priv); - cm_event.event = IB_CM_DREQ_ERROR; - break; - case IB_CM_SIDR_REQ_SENT: - cm_id_priv->id.state = IB_CM_IDLE; - cm_event.event = IB_CM_SIDR_REQ_ERROR; - break; - default: - goto discard; - } - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_event.param.send_status = wc_status; - - /* No other events can occur on the cm_id at this point. */ - ret = cm_id_priv->id.cm_handler(&cm_id_priv->id, &cm_event); - cm_free_msg(msg); - if (ret) - ib_destroy_cm_id(&cm_id_priv->id); - return; -discard: - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - cm_free_msg(msg); -} - -static void cm_send_handler(struct ib_mad_agent *mad_agent, - struct ib_mad_send_wc *mad_send_wc) -{ - struct ib_mad_send_buf *msg; - - msg = (struct ib_mad_send_buf *)(unsigned long)mad_send_wc->wr_id; - - switch (mad_send_wc->status) { - case IB_WC_SUCCESS: - case IB_WC_WR_FLUSH_ERR: - cm_free_msg(msg); - break; - default: - if (msg->context[0] && msg->context[1]) - cm_process_send_error(msg, mad_send_wc->status); - else - cm_free_msg(msg); - break; - } -} - -static void cm_work_handler(void *data) -{ - struct cm_work *work = data; - int ret; - - switch (work->cm_event.event) { - case IB_CM_REQ_RECEIVED: - ret = cm_req_handler(work); - break; - case IB_CM_MRA_RECEIVED: - ret = cm_mra_handler(work); - break; - case IB_CM_REJ_RECEIVED: - ret = cm_rej_handler(work); - break; - case IB_CM_REP_RECEIVED: - ret = cm_rep_handler(work); - break; - case IB_CM_RTU_RECEIVED: - ret = cm_rtu_handler(work); - break; - case IB_CM_USER_ESTABLISHED: - ret = cm_establish_handler(work); - break; - case IB_CM_DREQ_RECEIVED: - ret = cm_dreq_handler(work); - break; - case IB_CM_DREP_RECEIVED: - ret = cm_drep_handler(work); - break; - case IB_CM_SIDR_REQ_RECEIVED: - ret = cm_sidr_req_handler(work); - break; - case IB_CM_SIDR_REP_RECEIVED: - ret = cm_sidr_rep_handler(work); - break; - case IB_CM_LAP_RECEIVED: - ret = cm_lap_handler(work); - break; - case IB_CM_APR_RECEIVED: - ret = cm_apr_handler(work); - break; - case IB_CM_TIMEWAIT_EXIT: - ret = cm_timewait_handler(work); - break; - default: - ret = -EINVAL; - break; - } - if (ret) - cm_free_work(work); -} - -int ib_cm_establish(struct ib_cm_id *cm_id) -{ - struct cm_id_private *cm_id_priv; - struct cm_work *work; - unsigned long flags; - int ret = 0; - - work = kmalloc(sizeof *work, GFP_ATOMIC); - if (!work) - return -ENOMEM; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id->state) - { - case IB_CM_REP_SENT: - case IB_CM_MRA_REP_RCVD: - cm_id->state = IB_CM_ESTABLISHED; - break; - case IB_CM_ESTABLISHED: - ret = -EISCONN; - break; - default: - ret = -EINVAL; - break; - } - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - - if (ret) { - kfree(work); - goto out; - } - - /* - * The CM worker thread may try to destroy the cm_id before it - * can execute this work item. To prevent potential deadlock, - * we need to find the cm_id once we're in the context of the - * worker thread, rather than holding a reference on it. - */ - INIT_WORK(&work->work, cm_work_handler, work); - work->local_id = cm_id->local_id; - work->remote_id = cm_id->remote_id; - work->mad_recv_wc = NULL; - work->cm_event.event = IB_CM_USER_ESTABLISHED; - queue_work(cm.wq, &work->work); -out: - return ret; -} -EXPORT_SYMBOL(ib_cm_establish); - -static void cm_recv_handler(struct ib_mad_agent *mad_agent, - struct ib_mad_recv_wc *mad_recv_wc) -{ - struct cm_work *work; - enum ib_cm_event_type event; - int paths = 0; - - switch (mad_recv_wc->recv_buf.mad->mad_hdr.attr_id) { - case CM_REQ_ATTR_ID: - paths = 1 + (((struct cm_req_msg *) mad_recv_wc->recv_buf.mad)-> - alt_local_lid != 0); - event = IB_CM_REQ_RECEIVED; - break; - case CM_MRA_ATTR_ID: - event = IB_CM_MRA_RECEIVED; - break; - case CM_REJ_ATTR_ID: - event = IB_CM_REJ_RECEIVED; - break; - case CM_REP_ATTR_ID: - event = IB_CM_REP_RECEIVED; - break; - case CM_RTU_ATTR_ID: - event = IB_CM_RTU_RECEIVED; - break; - case CM_DREQ_ATTR_ID: - event = IB_CM_DREQ_RECEIVED; - break; - case CM_DREP_ATTR_ID: - event = IB_CM_DREP_RECEIVED; - break; - case CM_SIDR_REQ_ATTR_ID: - event = IB_CM_SIDR_REQ_RECEIVED; - break; - case CM_SIDR_REP_ATTR_ID: - event = IB_CM_SIDR_REP_RECEIVED; - break; - case CM_LAP_ATTR_ID: - paths = 1; - event = IB_CM_LAP_RECEIVED; - break; - case CM_APR_ATTR_ID: - event = IB_CM_APR_RECEIVED; - break; - default: - ib_free_recv_mad(mad_recv_wc); - return; - } - - work = kmalloc(sizeof *work + sizeof(struct ib_sa_path_rec) * paths, - GFP_KERNEL); - if (!work) { - ib_free_recv_mad(mad_recv_wc); - return; - } - - INIT_WORK(&work->work, cm_work_handler, work); - work->cm_event.event = event; - work->mad_recv_wc = mad_recv_wc; - work->port = (struct cm_port *)mad_agent->context; - queue_work(cm.wq, &work->work); -} - -static int cm_init_qp_init_attr(struct cm_id_private *cm_id_priv, - struct ib_qp_attr *qp_attr, - int *qp_attr_mask) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id_priv->id.state) { - case IB_CM_REQ_SENT: - case IB_CM_MRA_REQ_RCVD: - case IB_CM_REQ_RCVD: - case IB_CM_MRA_REQ_SENT: - case IB_CM_REP_RCVD: - case IB_CM_MRA_REP_SENT: - case IB_CM_REP_SENT: - case IB_CM_MRA_REP_RCVD: - case IB_CM_ESTABLISHED: - *qp_attr_mask = IB_QP_STATE | IB_QP_ACCESS_FLAGS | - IB_QP_PKEY_INDEX | IB_QP_PORT; - qp_attr->qp_access_flags = IB_ACCESS_LOCAL_WRITE; - if (cm_id_priv->responder_resources) - qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE | - IB_ACCESS_REMOTE_READ; - qp_attr->pkey_index = cm_id_priv->av.pkey_index; - qp_attr->port_num = cm_id_priv->av.port->port_num; - ret = 0; - break; - default: - ret = -EINVAL; - break; - } - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} - -static int cm_init_qp_rtr_attr(struct cm_id_private *cm_id_priv, - struct ib_qp_attr *qp_attr, - int *qp_attr_mask) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id_priv->id.state) { - case IB_CM_REQ_RCVD: - case IB_CM_MRA_REQ_SENT: - case IB_CM_REP_RCVD: - case IB_CM_MRA_REP_SENT: - case IB_CM_REP_SENT: - case IB_CM_MRA_REP_RCVD: - case IB_CM_ESTABLISHED: - *qp_attr_mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | - IB_QP_DEST_QPN | IB_QP_RQ_PSN | - IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; - qp_attr->ah_attr = cm_id_priv->av.ah_attr; - qp_attr->path_mtu = cm_id_priv->path_mtu; - qp_attr->dest_qp_num = be32_to_cpu(cm_id_priv->remote_qpn); - qp_attr->rq_psn = be32_to_cpu(cm_id_priv->rq_psn); - qp_attr->max_dest_rd_atomic = cm_id_priv->responder_resources; - qp_attr->min_rnr_timer = 0; - if (cm_id_priv->alt_av.ah_attr.dlid) { - *qp_attr_mask |= IB_QP_ALT_PATH; - qp_attr->alt_ah_attr = cm_id_priv->alt_av.ah_attr; - } - ret = 0; - break; - default: - ret = -EINVAL; - break; - } - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} - -static int cm_init_qp_rts_attr(struct cm_id_private *cm_id_priv, - struct ib_qp_attr *qp_attr, - int *qp_attr_mask) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&cm_id_priv->lock, flags); - switch (cm_id_priv->id.state) { - case IB_CM_REP_RCVD: - case IB_CM_MRA_REP_SENT: - case IB_CM_REP_SENT: - case IB_CM_MRA_REP_RCVD: - case IB_CM_ESTABLISHED: - *qp_attr_mask = IB_QP_STATE | IB_QP_TIMEOUT | IB_QP_RETRY_CNT | - IB_QP_RNR_RETRY | IB_QP_SQ_PSN | - IB_QP_MAX_QP_RD_ATOMIC; - qp_attr->timeout = cm_id_priv->local_ack_timeout; - qp_attr->retry_cnt = cm_id_priv->retry_count; - qp_attr->rnr_retry = cm_id_priv->rnr_retry_count; - qp_attr->sq_psn = be32_to_cpu(cm_id_priv->sq_psn); - qp_attr->max_rd_atomic = cm_id_priv->initiator_depth; - if (cm_id_priv->alt_av.ah_attr.dlid) { - *qp_attr_mask |= IB_QP_PATH_MIG_STATE; - qp_attr->path_mig_state = IB_MIG_REARM; - } - ret = 0; - break; - default: - ret = -EINVAL; - break; - } - spin_unlock_irqrestore(&cm_id_priv->lock, flags); - return ret; -} - -int ib_cm_init_qp_attr(struct ib_cm_id *cm_id, - struct ib_qp_attr *qp_attr, - int *qp_attr_mask) -{ - struct cm_id_private *cm_id_priv; - int ret; - - cm_id_priv = container_of(cm_id, struct cm_id_private, id); - switch (qp_attr->qp_state) { - case IB_QPS_INIT: - ret = cm_init_qp_init_attr(cm_id_priv, qp_attr, qp_attr_mask); - break; - case IB_QPS_RTR: - ret = cm_init_qp_rtr_attr(cm_id_priv, qp_attr, qp_attr_mask); - break; - case IB_QPS_RTS: - ret = cm_init_qp_rts_attr(cm_id_priv, qp_attr, qp_attr_mask); - break; - default: - ret = -EINVAL; - break; - } - return ret; -} -EXPORT_SYMBOL(ib_cm_init_qp_attr); - -static u64 cm_get_ca_guid(struct ib_device *device) -{ - struct ib_device_attr *device_attr; - u64 guid; - int ret; - - device_attr = kmalloc(sizeof *device_attr, GFP_KERNEL); - if (!device_attr) - return 0; - - ret = ib_query_device(device, device_attr); - guid = ret ? 0 : device_attr->node_guid; - kfree(device_attr); - return guid; -} - -static void cm_add_one(struct ib_device *device) -{ - struct cm_device *cm_dev; - struct cm_port *port; - struct ib_mad_reg_req reg_req = { - .mgmt_class = IB_MGMT_CLASS_CM, - .mgmt_class_version = IB_CM_CLASS_VERSION - }; - struct ib_port_modify port_modify = { - .set_port_cap_mask = IB_PORT_CM_SUP - }; - unsigned long flags; - int ret; - u8 i; - - cm_dev = kmalloc(sizeof(*cm_dev) + sizeof(*port) * - device->phys_port_cnt, GFP_KERNEL); - if (!cm_dev) - return; - - cm_dev->device = device; - cm_dev->ca_guid = cm_get_ca_guid(device); - if (!cm_dev->ca_guid) - goto error1; - - set_bit(IB_MGMT_METHOD_SEND, reg_req.method_mask); - for (i = 1; i <= device->phys_port_cnt; i++) { - port = &cm_dev->port[i-1]; - port->cm_dev = cm_dev; - port->port_num = i; - port->mad_agent = ib_register_mad_agent(device, i, - IB_QPT_GSI, - ®_req, - 0, - cm_send_handler, - cm_recv_handler, - port); - if (IS_ERR(port->mad_agent)) - goto error2; - - ret = ib_modify_port(device, i, 0, &port_modify); - if (ret) - goto error3; - } - ib_set_client_data(device, &cm_client, cm_dev); - - write_lock_irqsave(&cm.device_lock, flags); - list_add_tail(&cm_dev->list, &cm.device_list); - write_unlock_irqrestore(&cm.device_lock, flags); - return; - -error3: - ib_unregister_mad_agent(port->mad_agent); -error2: - port_modify.set_port_cap_mask = 0; - port_modify.clr_port_cap_mask = IB_PORT_CM_SUP; - while (--i) { - port = &cm_dev->port[i-1]; - ib_modify_port(device, port->port_num, 0, &port_modify); - ib_unregister_mad_agent(port->mad_agent); - } -error1: - kfree(cm_dev); -} - -static void cm_remove_one(struct ib_device *device) -{ - struct cm_device *cm_dev; - struct cm_port *port; - struct ib_port_modify port_modify = { - .clr_port_cap_mask = IB_PORT_CM_SUP - }; - unsigned long flags; - int i; - - cm_dev = ib_get_client_data(device, &cm_client); - if (!cm_dev) - return; - - write_lock_irqsave(&cm.device_lock, flags); - list_del(&cm_dev->list); - write_unlock_irqrestore(&cm.device_lock, flags); - - for (i = 1; i <= device->phys_port_cnt; i++) { - port = &cm_dev->port[i-1]; - ib_modify_port(device, port->port_num, 0, &port_modify); - ib_unregister_mad_agent(port->mad_agent); - } - kfree(cm_dev); -} - -static int __init ib_cm_init(void) -{ - int ret; - - memset(&cm, 0, sizeof cm); - INIT_LIST_HEAD(&cm.device_list); - rwlock_init(&cm.device_lock); - spin_lock_init(&cm.lock); - cm.listen_service_table = RB_ROOT; - cm.listen_service_id = __constant_be64_to_cpu(IB_CM_ASSIGN_SERVICE_ID); - cm.remote_id_table = RB_ROOT; - cm.remote_qp_table = RB_ROOT; - cm.remote_sidr_table = RB_ROOT; - idr_init(&cm.local_id_table); - idr_pre_get(&cm.local_id_table, GFP_KERNEL); - - cm.wq = create_workqueue("ib_cm"); - if (!cm.wq) - return -ENOMEM; - - ret = ib_register_client(&cm_client); - if (ret) - goto error; - - return 0; -error: - destroy_workqueue(cm.wq); - return ret; -} - -static void __exit ib_cm_cleanup(void) -{ - flush_workqueue(cm.wq); - destroy_workqueue(cm.wq); - ib_unregister_client(&cm_client); -} - -module_init(ib_cm_init); -module_exit(ib_cm_cleanup); - diff --git a/trunk/drivers/infiniband/core/cm_msgs.h b/trunk/drivers/infiniband/core/cm_msgs.h deleted file mode 100644 index 15a309a77b2b..000000000000 --- a/trunk/drivers/infiniband/core/cm_msgs.h +++ /dev/null @@ -1,819 +0,0 @@ -/* - * Copyright (c) 2004 Intel Corporation. All rights reserved. - * Copyright (c) 2004 Topspin Corporation. All rights reserved. - * Copyright (c) 2004 Voltaire Corporation. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING the madirectory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use source and binary forms, with or - * withmodification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retathe above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHWARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS THE - * SOFTWARE. - */ -#if !defined(CM_MSGS_H) -#define CM_MSGS_H - -#include - -/* - * Parameters to routines below should be in network-byte order, and values - * are returned in network-byte order. - */ - -#define IB_CM_CLASS_VERSION 2 /* IB specification 1.2 */ - -enum cm_msg_attr_id { - CM_REQ_ATTR_ID = __constant_htons(0x0010), - CM_MRA_ATTR_ID = __constant_htons(0x0011), - CM_REJ_ATTR_ID = __constant_htons(0x0012), - CM_REP_ATTR_ID = __constant_htons(0x0013), - CM_RTU_ATTR_ID = __constant_htons(0x0014), - CM_DREQ_ATTR_ID = __constant_htons(0x0015), - CM_DREP_ATTR_ID = __constant_htons(0x0016), - CM_SIDR_REQ_ATTR_ID = __constant_htons(0x0017), - CM_SIDR_REP_ATTR_ID = __constant_htons(0x0018), - CM_LAP_ATTR_ID = __constant_htons(0x0019), - CM_APR_ATTR_ID = __constant_htons(0x001A) -}; - -enum cm_msg_sequence { - CM_MSG_SEQUENCE_REQ, - CM_MSG_SEQUENCE_LAP, - CM_MSG_SEQUENCE_DREQ, - CM_MSG_SEQUENCE_SIDR -}; - -struct cm_req_msg { - struct ib_mad_hdr hdr; - - u32 local_comm_id; - u32 rsvd4; - u64 service_id; - u64 local_ca_guid; - u32 rsvd24; - u32 local_qkey; - /* local QPN:24, responder resources:8 */ - u32 offset32; - /* local EECN:24, initiator depth:8 */ - u32 offset36; - /* - * remote EECN:24, remote CM response timeout:5, - * transport service type:2, end-to-end flow control:1 - */ - u32 offset40; - /* starting PSN:24, local CM response timeout:5, retry count:3 */ - u32 offset44; - u16 pkey; - /* path MTU:4, RDC exists:1, RNR retry count:3. */ - u8 offset50; - /* max CM Retries:4, SRQ:1, rsvd:3 */ - u8 offset51; - - u16 primary_local_lid; - u16 primary_remote_lid; - union ib_gid primary_local_gid; - union ib_gid primary_remote_gid; - /* flow label:20, rsvd:6, packet rate:6 */ - u32 primary_offset88; - u8 primary_traffic_class; - u8 primary_hop_limit; - /* SL:4, subnet local:1, rsvd:3 */ - u8 primary_offset94; - /* local ACK timeout:5, rsvd:3 */ - u8 primary_offset95; - - u16 alt_local_lid; - u16 alt_remote_lid; - union ib_gid alt_local_gid; - union ib_gid alt_remote_gid; - /* flow label:20, rsvd:6, packet rate:6 */ - u32 alt_offset132; - u8 alt_traffic_class; - u8 alt_hop_limit; - /* SL:4, subnet local:1, rsvd:3 */ - u8 alt_offset138; - /* local ACK timeout:5, rsvd:3 */ - u8 alt_offset139; - - u8 private_data[IB_CM_REQ_PRIVATE_DATA_SIZE]; - -} __attribute__ ((packed)); - -static inline u32 cm_req_get_local_qpn(struct cm_req_msg *req_msg) -{ - return cpu_to_be32(be32_to_cpu(req_msg->offset32) >> 8); -} - -static inline void cm_req_set_local_qpn(struct cm_req_msg *req_msg, u32 qpn) -{ - req_msg->offset32 = cpu_to_be32((be32_to_cpu(qpn) << 8) | - (be32_to_cpu(req_msg->offset32) & - 0x000000FF)); -} - -static inline u8 cm_req_get_resp_res(struct cm_req_msg *req_msg) -{ - return (u8) be32_to_cpu(req_msg->offset32); -} - -static inline void cm_req_set_resp_res(struct cm_req_msg *req_msg, u8 resp_res) -{ - req_msg->offset32 = cpu_to_be32(resp_res | - (be32_to_cpu(req_msg->offset32) & - 0xFFFFFF00)); -} - -static inline u8 cm_req_get_init_depth(struct cm_req_msg *req_msg) -{ - return (u8) be32_to_cpu(req_msg->offset36); -} - -static inline void cm_req_set_init_depth(struct cm_req_msg *req_msg, - u8 init_depth) -{ - req_msg->offset36 = cpu_to_be32(init_depth | - (be32_to_cpu(req_msg->offset36) & - 0xFFFFFF00)); -} - -static inline u8 cm_req_get_remote_resp_timeout(struct cm_req_msg *req_msg) -{ - return (u8) ((be32_to_cpu(req_msg->offset40) & 0xF8) >> 3); -} - -static inline void cm_req_set_remote_resp_timeout(struct cm_req_msg *req_msg, - u8 resp_timeout) -{ - req_msg->offset40 = cpu_to_be32((resp_timeout << 3) | - (be32_to_cpu(req_msg->offset40) & - 0xFFFFFF07)); -} - -static inline enum ib_qp_type cm_req_get_qp_type(struct cm_req_msg *req_msg) -{ - u8 transport_type = (u8) (be32_to_cpu(req_msg->offset40) & 0x06) >> 1; - switch(transport_type) { - case 0: return IB_QPT_RC; - case 1: return IB_QPT_UC; - default: return 0; - } -} - -static inline void cm_req_set_qp_type(struct cm_req_msg *req_msg, - enum ib_qp_type qp_type) -{ - switch(qp_type) { - case IB_QPT_UC: - req_msg->offset40 = cpu_to_be32((be32_to_cpu( - req_msg->offset40) & - 0xFFFFFFF9) | 0x2); - default: - req_msg->offset40 = cpu_to_be32(be32_to_cpu( - req_msg->offset40) & - 0xFFFFFFF9); - } -} - -static inline u8 cm_req_get_flow_ctrl(struct cm_req_msg *req_msg) -{ - return be32_to_cpu(req_msg->offset40) & 0x1; -} - -static inline void cm_req_set_flow_ctrl(struct cm_req_msg *req_msg, - u8 flow_ctrl) -{ - req_msg->offset40 = cpu_to_be32((flow_ctrl & 0x1) | - (be32_to_cpu(req_msg->offset40) & - 0xFFFFFFFE)); -} - -static inline u32 cm_req_get_starting_psn(struct cm_req_msg *req_msg) -{ - return cpu_to_be32(be32_to_cpu(req_msg->offset44) >> 8); -} - -static inline void cm_req_set_starting_psn(struct cm_req_msg *req_msg, - u32 starting_psn) -{ - req_msg->offset44 = cpu_to_be32((be32_to_cpu(starting_psn) << 8) | - (be32_to_cpu(req_msg->offset44) & 0x000000FF)); -} - -static inline u8 cm_req_get_local_resp_timeout(struct cm_req_msg *req_msg) -{ - return (u8) ((be32_to_cpu(req_msg->offset44) & 0xF8) >> 3); -} - -static inline void cm_req_set_local_resp_timeout(struct cm_req_msg *req_msg, - u8 resp_timeout) -{ - req_msg->offset44 = cpu_to_be32((resp_timeout << 3) | - (be32_to_cpu(req_msg->offset44) & 0xFFFFFF07)); -} - -static inline u8 cm_req_get_retry_count(struct cm_req_msg *req_msg) -{ - return (u8) (be32_to_cpu(req_msg->offset44) & 0x7); -} - -static inline void cm_req_set_retry_count(struct cm_req_msg *req_msg, - u8 retry_count) -{ - req_msg->offset44 = cpu_to_be32((retry_count & 0x7) | - (be32_to_cpu(req_msg->offset44) & 0xFFFFFFF8)); -} - -static inline u8 cm_req_get_path_mtu(struct cm_req_msg *req_msg) -{ - return req_msg->offset50 >> 4; -} - -static inline void cm_req_set_path_mtu(struct cm_req_msg *req_msg, u8 path_mtu) -{ - req_msg->offset50 = (u8) ((req_msg->offset50 & 0xF) | (path_mtu << 4)); -} - -static inline u8 cm_req_get_rnr_retry_count(struct cm_req_msg *req_msg) -{ - return req_msg->offset50 & 0x7; -} - -static inline void cm_req_set_rnr_retry_count(struct cm_req_msg *req_msg, - u8 rnr_retry_count) -{ - req_msg->offset50 = (u8) ((req_msg->offset50 & 0xF8) | - (rnr_retry_count & 0x7)); -} - -static inline u8 cm_req_get_max_cm_retries(struct cm_req_msg *req_msg) -{ - return req_msg->offset51 >> 4; -} - -static inline void cm_req_set_max_cm_retries(struct cm_req_msg *req_msg, - u8 retries) -{ - req_msg->offset51 = (u8) ((req_msg->offset51 & 0xF) | (retries << 4)); -} - -static inline u8 cm_req_get_srq(struct cm_req_msg *req_msg) -{ - return (req_msg->offset51 & 0x8) >> 3; -} - -static inline void cm_req_set_srq(struct cm_req_msg *req_msg, u8 srq) -{ - req_msg->offset51 = (u8) ((req_msg->offset51 & 0xF7) | - ((srq & 0x1) << 3)); -} - -static inline u32 cm_req_get_primary_flow_label(struct cm_req_msg *req_msg) -{ - return cpu_to_be32((be32_to_cpu(req_msg->primary_offset88) >> 12)); -} - -static inline void cm_req_set_primary_flow_label(struct cm_req_msg *req_msg, - u32 flow_label) -{ - req_msg->primary_offset88 = cpu_to_be32( - (be32_to_cpu(req_msg->primary_offset88) & - 0x00000FFF) | - (be32_to_cpu(flow_label) << 12)); -} - -static inline u8 cm_req_get_primary_packet_rate(struct cm_req_msg *req_msg) -{ - return (u8) (be32_to_cpu(req_msg->primary_offset88) & 0x3F); -} - -static inline void cm_req_set_primary_packet_rate(struct cm_req_msg *req_msg, - u8 rate) -{ - req_msg->primary_offset88 = cpu_to_be32( - (be32_to_cpu(req_msg->primary_offset88) & - 0xFFFFFFC0) | (rate & 0x3F)); -} - -static inline u8 cm_req_get_primary_sl(struct cm_req_msg *req_msg) -{ - return (u8) (req_msg->primary_offset94 >> 4); -} - -static inline void cm_req_set_primary_sl(struct cm_req_msg *req_msg, u8 sl) -{ - req_msg->primary_offset94 = (u8) ((req_msg->primary_offset94 & 0x0F) | - (sl << 4)); -} - -static inline u8 cm_req_get_primary_subnet_local(struct cm_req_msg *req_msg) -{ - return (u8) ((req_msg->primary_offset94 & 0x08) >> 3); -} - -static inline void cm_req_set_primary_subnet_local(struct cm_req_msg *req_msg, - u8 subnet_local) -{ - req_msg->primary_offset94 = (u8) ((req_msg->primary_offset94 & 0xF7) | - ((subnet_local & 0x1) << 3)); -} - -static inline u8 cm_req_get_primary_local_ack_timeout(struct cm_req_msg *req_msg) -{ - return (u8) (req_msg->primary_offset95 >> 3); -} - -static inline void cm_req_set_primary_local_ack_timeout(struct cm_req_msg *req_msg, - u8 local_ack_timeout) -{ - req_msg->primary_offset95 = (u8) ((req_msg->primary_offset95 & 0x07) | - (local_ack_timeout << 3)); -} - -static inline u32 cm_req_get_alt_flow_label(struct cm_req_msg *req_msg) -{ - return cpu_to_be32((be32_to_cpu(req_msg->alt_offset132) >> 12)); -} - -static inline void cm_req_set_alt_flow_label(struct cm_req_msg *req_msg, - u32 flow_label) -{ - req_msg->alt_offset132 = cpu_to_be32( - (be32_to_cpu(req_msg->alt_offset132) & - 0x00000FFF) | - (be32_to_cpu(flow_label) << 12)); -} - -static inline u8 cm_req_get_alt_packet_rate(struct cm_req_msg *req_msg) -{ - return (u8) (be32_to_cpu(req_msg->alt_offset132) & 0x3F); -} - -static inline void cm_req_set_alt_packet_rate(struct cm_req_msg *req_msg, - u8 rate) -{ - req_msg->alt_offset132 = cpu_to_be32( - (be32_to_cpu(req_msg->alt_offset132) & - 0xFFFFFFC0) | (rate & 0x3F)); -} - -static inline u8 cm_req_get_alt_sl(struct cm_req_msg *req_msg) -{ - return (u8) (req_msg->alt_offset138 >> 4); -} - -static inline void cm_req_set_alt_sl(struct cm_req_msg *req_msg, u8 sl) -{ - req_msg->alt_offset138 = (u8) ((req_msg->alt_offset138 & 0x0F) | - (sl << 4)); -} - -static inline u8 cm_req_get_alt_subnet_local(struct cm_req_msg *req_msg) -{ - return (u8) ((req_msg->alt_offset138 & 0x08) >> 3); -} - -static inline void cm_req_set_alt_subnet_local(struct cm_req_msg *req_msg, - u8 subnet_local) -{ - req_msg->alt_offset138 = (u8) ((req_msg->alt_offset138 & 0xF7) | - ((subnet_local & 0x1) << 3)); -} - -static inline u8 cm_req_get_alt_local_ack_timeout(struct cm_req_msg *req_msg) -{ - return (u8) (req_msg->alt_offset139 >> 3); -} - -static inline void cm_req_set_alt_local_ack_timeout(struct cm_req_msg *req_msg, - u8 local_ack_timeout) -{ - req_msg->alt_offset139 = (u8) ((req_msg->alt_offset139 & 0x07) | - (local_ack_timeout << 3)); -} - -/* Message REJected or MRAed */ -enum cm_msg_response { - CM_MSG_RESPONSE_REQ = 0x0, - CM_MSG_RESPONSE_REP = 0x1, - CM_MSG_RESPONSE_OTHER = 0x2 -}; - - struct cm_mra_msg { - struct ib_mad_hdr hdr; - - u32 local_comm_id; - u32 remote_comm_id; - /* message MRAed:2, rsvd:6 */ - u8 offset8; - /* service timeout:5, rsvd:3 */ - u8 offset9; - - u8 private_data[IB_CM_MRA_PRIVATE_DATA_SIZE]; - -} __attribute__ ((packed)); - -static inline u8 cm_mra_get_msg_mraed(struct cm_mra_msg *mra_msg) -{ - return (u8) (mra_msg->offset8 >> 6); -} - -static inline void cm_mra_set_msg_mraed(struct cm_mra_msg *mra_msg, u8 msg) -{ - mra_msg->offset8 = (u8) ((mra_msg->offset8 & 0x3F) | (msg << 6)); -} - -static inline u8 cm_mra_get_service_timeout(struct cm_mra_msg *mra_msg) -{ - return (u8) (mra_msg->offset9 >> 3); -} - -static inline void cm_mra_set_service_timeout(struct cm_mra_msg *mra_msg, - u8 service_timeout) -{ - mra_msg->offset9 = (u8) ((mra_msg->offset9 & 0x07) | - (service_timeout << 3)); -} - -struct cm_rej_msg { - struct ib_mad_hdr hdr; - - u32 local_comm_id; - u32 remote_comm_id; - /* message REJected:2, rsvd:6 */ - u8 offset8; - /* reject info length:7, rsvd:1. */ - u8 offset9; - u16 reason; - u8 ari[IB_CM_REJ_ARI_LENGTH]; - - u8 private_data[IB_CM_REJ_PRIVATE_DATA_SIZE]; - -} __attribute__ ((packed)); - -static inline u8 cm_rej_get_msg_rejected(struct cm_rej_msg *rej_msg) -{ - return (u8) (rej_msg->offset8 >> 6); -} - -static inline void cm_rej_set_msg_rejected(struct cm_rej_msg *rej_msg, u8 msg) -{ - rej_msg->offset8 = (u8) ((rej_msg->offset8 & 0x3F) | (msg << 6)); -} - -static inline u8 cm_rej_get_reject_info_len(struct cm_rej_msg *rej_msg) -{ - return (u8) (rej_msg->offset9 >> 1); -} - -static inline void cm_rej_set_reject_info_len(struct cm_rej_msg *rej_msg, - u8 len) -{ - rej_msg->offset9 = (u8) ((rej_msg->offset9 & 0x1) | (len << 1)); -} - -struct cm_rep_msg { - struct ib_mad_hdr hdr; - - u32 local_comm_id; - u32 remote_comm_id; - u32 local_qkey; - /* local QPN:24, rsvd:8 */ - u32 offset12; - /* local EECN:24, rsvd:8 */ - u32 offset16; - /* starting PSN:24 rsvd:8 */ - u32 offset20; - u8 resp_resources; - u8 initiator_depth; - /* target ACK delay:5, failover accepted:2, end-to-end flow control:1 */ - u8 offset26; - /* RNR retry count:3, SRQ:1, rsvd:5 */ - u8 offset27; - u64 local_ca_guid; - - u8 private_data[IB_CM_REP_PRIVATE_DATA_SIZE]; - -} __attribute__ ((packed)); - -static inline u32 cm_rep_get_local_qpn(struct cm_rep_msg *rep_msg) -{ - return cpu_to_be32(be32_to_cpu(rep_msg->offset12) >> 8); -} - -static inline void cm_rep_set_local_qpn(struct cm_rep_msg *rep_msg, u32 qpn) -{ - rep_msg->offset12 = cpu_to_be32((be32_to_cpu(qpn) << 8) | - (be32_to_cpu(rep_msg->offset12) & 0x000000FF)); -} - -static inline u32 cm_rep_get_starting_psn(struct cm_rep_msg *rep_msg) -{ - return cpu_to_be32(be32_to_cpu(rep_msg->offset20) >> 8); -} - -static inline void cm_rep_set_starting_psn(struct cm_rep_msg *rep_msg, - u32 starting_psn) -{ - rep_msg->offset20 = cpu_to_be32((be32_to_cpu(starting_psn) << 8) | - (be32_to_cpu(rep_msg->offset20) & 0x000000FF)); -} - -static inline u8 cm_rep_get_target_ack_delay(struct cm_rep_msg *rep_msg) -{ - return (u8) (rep_msg->offset26 >> 3); -} - -static inline void cm_rep_set_target_ack_delay(struct cm_rep_msg *rep_msg, - u8 target_ack_delay) -{ - rep_msg->offset26 = (u8) ((rep_msg->offset26 & 0x07) | - (target_ack_delay << 3)); -} - -static inline u8 cm_rep_get_failover(struct cm_rep_msg *rep_msg) -{ - return (u8) ((rep_msg->offset26 & 0x06) >> 1); -} - -static inline void cm_rep_set_failover(struct cm_rep_msg *rep_msg, u8 failover) -{ - rep_msg->offset26 = (u8) ((rep_msg->offset26 & 0xF9) | - ((failover & 0x3) << 1)); -} - -static inline u8 cm_rep_get_flow_ctrl(struct cm_rep_msg *rep_msg) -{ - return (u8) (rep_msg->offset26 & 0x01); -} - -static inline void cm_rep_set_flow_ctrl(struct cm_rep_msg *rep_msg, - u8 flow_ctrl) -{ - rep_msg->offset26 = (u8) ((rep_msg->offset26 & 0xFE) | - (flow_ctrl & 0x1)); -} - -static inline u8 cm_rep_get_rnr_retry_count(struct cm_rep_msg *rep_msg) -{ - return (u8) (rep_msg->offset27 >> 5); -} - -static inline void cm_rep_set_rnr_retry_count(struct cm_rep_msg *rep_msg, - u8 rnr_retry_count) -{ - rep_msg->offset27 = (u8) ((rep_msg->offset27 & 0x1F) | - (rnr_retry_count << 5)); -} - -static inline u8 cm_rep_get_srq(struct cm_rep_msg *rep_msg) -{ - return (u8) ((rep_msg->offset27 >> 4) & 0x1); -} - -static inline void cm_rep_set_srq(struct cm_rep_msg *rep_msg, u8 srq) -{ - rep_msg->offset27 = (u8) ((rep_msg->offset27 & 0xEF) | - ((srq & 0x1) << 4)); -} - -struct cm_rtu_msg { - struct ib_mad_hdr hdr; - - u32 local_comm_id; - u32 remote_comm_id; - - u8 private_data[IB_CM_RTU_PRIVATE_DATA_SIZE]; - -} __attribute__ ((packed)); - -struct cm_dreq_msg { - struct ib_mad_hdr hdr; - - u32 local_comm_id; - u32 remote_comm_id; - /* remote QPN/EECN:24, rsvd:8 */ - u32 offset8; - - u8 private_data[IB_CM_DREQ_PRIVATE_DATA_SIZE]; - -} __attribute__ ((packed)); - -static inline u32 cm_dreq_get_remote_qpn(struct cm_dreq_msg *dreq_msg) -{ - return cpu_to_be32(be32_to_cpu(dreq_msg->offset8) >> 8); -} - -static inline void cm_dreq_set_remote_qpn(struct cm_dreq_msg *dreq_msg, u32 qpn) -{ - dreq_msg->offset8 = cpu_to_be32((be32_to_cpu(qpn) << 8) | - (be32_to_cpu(dreq_msg->offset8) & 0x000000FF)); -} - -struct cm_drep_msg { - struct ib_mad_hdr hdr; - - u32 local_comm_id; - u32 remote_comm_id; - - u8 private_data[IB_CM_DREP_PRIVATE_DATA_SIZE]; - -} __attribute__ ((packed)); - -struct cm_lap_msg { - struct ib_mad_hdr hdr; - - u32 local_comm_id; - u32 remote_comm_id; - - u32 rsvd8; - /* remote QPN/EECN:24, remote CM response timeout:5, rsvd:3 */ - u32 offset12; - u32 rsvd16; - - u16 alt_local_lid; - u16 alt_remote_lid; - union ib_gid alt_local_gid; - union ib_gid alt_remote_gid; - /* flow label:20, rsvd:4, traffic class:8 */ - u32 offset56; - u8 alt_hop_limit; - /* rsvd:2, packet rate:6 */ - uint8_t offset61; - /* SL:4, subnet local:1, rsvd:3 */ - uint8_t offset62; - /* local ACK timeout:5, rsvd:3 */ - uint8_t offset63; - - u8 private_data[IB_CM_LAP_PRIVATE_DATA_SIZE]; -} __attribute__ ((packed)); - -static inline u32 cm_lap_get_remote_qpn(struct cm_lap_msg *lap_msg) -{ - return cpu_to_be32(be32_to_cpu(lap_msg->offset12) >> 8); -} - -static inline void cm_lap_set_remote_qpn(struct cm_lap_msg *lap_msg, u32 qpn) -{ - lap_msg->offset12 = cpu_to_be32((be32_to_cpu(qpn) << 8) | - (be32_to_cpu(lap_msg->offset12) & - 0x000000FF)); -} - -static inline u8 cm_lap_get_remote_resp_timeout(struct cm_lap_msg *lap_msg) -{ - return (u8) ((be32_to_cpu(lap_msg->offset12) & 0xF8) >> 3); -} - -static inline void cm_lap_set_remote_resp_timeout(struct cm_lap_msg *lap_msg, - u8 resp_timeout) -{ - lap_msg->offset12 = cpu_to_be32((resp_timeout << 3) | - (be32_to_cpu(lap_msg->offset12) & - 0xFFFFFF07)); -} - -static inline u32 cm_lap_get_flow_label(struct cm_lap_msg *lap_msg) -{ - return be32_to_cpu(lap_msg->offset56) >> 12; -} - -static inline void cm_lap_set_flow_label(struct cm_lap_msg *lap_msg, - u32 flow_label) -{ - lap_msg->offset56 = cpu_to_be32((flow_label << 12) | - (be32_to_cpu(lap_msg->offset56) & - 0x00000FFF)); -} - -static inline u8 cm_lap_get_traffic_class(struct cm_lap_msg *lap_msg) -{ - return (u8) be32_to_cpu(lap_msg->offset56); -} - -static inline void cm_lap_set_traffic_class(struct cm_lap_msg *lap_msg, - u8 traffic_class) -{ - lap_msg->offset56 = cpu_to_be32(traffic_class | - (be32_to_cpu(lap_msg->offset56) & - 0xFFFFFF00)); -} - -static inline u8 cm_lap_get_packet_rate(struct cm_lap_msg *lap_msg) -{ - return lap_msg->offset61 & 0x3F; -} - -static inline void cm_lap_set_packet_rate(struct cm_lap_msg *lap_msg, - u8 packet_rate) -{ - lap_msg->offset61 = (packet_rate & 0x3F) | (lap_msg->offset61 & 0xC0); -} - -static inline u8 cm_lap_get_sl(struct cm_lap_msg *lap_msg) -{ - return lap_msg->offset62 >> 4; -} - -static inline void cm_lap_set_sl(struct cm_lap_msg *lap_msg, u8 sl) -{ - lap_msg->offset62 = (sl << 4) | (lap_msg->offset62 & 0x0F); -} - -static inline u8 cm_lap_get_subnet_local(struct cm_lap_msg *lap_msg) -{ - return (lap_msg->offset62 >> 3) & 0x1; -} - -static inline void cm_lap_set_subnet_local(struct cm_lap_msg *lap_msg, - u8 subnet_local) -{ - lap_msg->offset62 = ((subnet_local & 0x1) << 3) | - (lap_msg->offset61 & 0xF7); -} -static inline u8 cm_lap_get_local_ack_timeout(struct cm_lap_msg *lap_msg) -{ - return lap_msg->offset63 >> 3; -} - -static inline void cm_lap_set_local_ack_timeout(struct cm_lap_msg *lap_msg, - u8 local_ack_timeout) -{ - lap_msg->offset63 = (local_ack_timeout << 3) | - (lap_msg->offset63 & 0x07); -} - -struct cm_apr_msg { - struct ib_mad_hdr hdr; - - u32 local_comm_id; - u32 remote_comm_id; - - u8 info_length; - u8 ap_status; - u8 info[IB_CM_APR_INFO_LENGTH]; - - u8 private_data[IB_CM_APR_PRIVATE_DATA_SIZE]; -} __attribute__ ((packed)); - -struct cm_sidr_req_msg { - struct ib_mad_hdr hdr; - - u32 request_id; - u16 pkey; - u16 rsvd; - u64 service_id; - - u8 private_data[IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE]; -} __attribute__ ((packed)); - -struct cm_sidr_rep_msg { - struct ib_mad_hdr hdr; - - u32 request_id; - u8 status; - u8 info_length; - u16 rsvd; - /* QPN:24, rsvd:8 */ - u32 offset8; - u64 service_id; - u32 qkey; - u8 info[IB_CM_SIDR_REP_INFO_LENGTH]; - - u8 private_data[IB_CM_SIDR_REP_PRIVATE_DATA_SIZE]; -} __attribute__ ((packed)); - -static inline u32 cm_sidr_rep_get_qpn(struct cm_sidr_rep_msg *sidr_rep_msg) -{ - return cpu_to_be32(be32_to_cpu(sidr_rep_msg->offset8) >> 8); -} - -static inline void cm_sidr_rep_set_qpn(struct cm_sidr_rep_msg *sidr_rep_msg, - u32 qpn) -{ - sidr_rep_msg->offset8 = cpu_to_be32((be32_to_cpu(qpn) << 8) | - (be32_to_cpu(sidr_rep_msg->offset8) & - 0x000000FF)); -} - -#endif /* CM_MSGS_H */ diff --git a/trunk/drivers/infiniband/core/fmr_pool.c b/trunk/drivers/infiniband/core/fmr_pool.c index 7763b31abba7..328feae2a5be 100644 --- a/trunk/drivers/infiniband/core/fmr_pool.c +++ b/trunk/drivers/infiniband/core/fmr_pool.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2004 Topspin Communications. All rights reserved. - * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU @@ -30,7 +29,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: fmr_pool.c 2730 2005-06-28 16:43:03Z sean.hefty $ + * $Id: fmr_pool.c 1349 2004-12-16 21:09:43Z roland $ */ #include @@ -330,7 +329,7 @@ EXPORT_SYMBOL(ib_create_fmr_pool); * * Destroy an FMR pool and free all associated resources. */ -void ib_destroy_fmr_pool(struct ib_fmr_pool *pool) +int ib_destroy_fmr_pool(struct ib_fmr_pool *pool) { struct ib_pool_fmr *fmr; struct ib_pool_fmr *tmp; @@ -353,6 +352,8 @@ void ib_destroy_fmr_pool(struct ib_fmr_pool *pool) kfree(pool->cache_bucket); kfree(pool); + + return 0; } EXPORT_SYMBOL(ib_destroy_fmr_pool); diff --git a/trunk/drivers/infiniband/core/mad.c b/trunk/drivers/infiniband/core/mad.c index b97e210ce9c8..23628c622a50 100644 --- a/trunk/drivers/infiniband/core/mad.c +++ b/trunk/drivers/infiniband/core/mad.c @@ -1,7 +1,5 @@ /* * Copyright (c) 2004, 2005 Voltaire, Inc. All rights reserved. - * Copyright (c) 2005 Intel Corporation. All rights reserved. - * Copyright (c) 2005 Mellanox Technologies Ltd. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU @@ -31,12 +29,12 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: mad.c 2817 2005-07-07 11:29:26Z halr $ + * $Id: mad.c 1389 2004-12-27 22:56:47Z roland $ */ + #include #include "mad_priv.h" -#include "mad_rmpp.h" #include "smi.h" #include "agent.h" @@ -47,7 +45,6 @@ MODULE_AUTHOR("Sean Hefty"); kmem_cache_t *ib_mad_cache; - static struct list_head ib_mad_port_list; static u32 ib_mad_client_id = 0; @@ -61,12 +58,16 @@ static int method_in_use(struct ib_mad_mgmt_method_table **method, static void remove_mad_reg_req(struct ib_mad_agent_private *priv); static struct ib_mad_agent_private *find_mad_agent( struct ib_mad_port_private *port_priv, - struct ib_mad *mad); + struct ib_mad *mad, int solicited); static int ib_mad_post_receive_mads(struct ib_mad_qp_info *qp_info, struct ib_mad_private *mad); static void cancel_mads(struct ib_mad_agent_private *mad_agent_priv); +static void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr, + struct ib_mad_send_wc *mad_send_wc); static void timeout_sends(void *data); +static void cancel_sends(void *data); static void local_completions(void *data); +static int solicited_mad(struct ib_mad *mad); static int add_nonoui_reg_req(struct ib_mad_reg_req *mad_reg_req, struct ib_mad_agent_private *agent_priv, u8 mgmt_class); @@ -196,8 +197,8 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device, if (qpn == -1) goto error1; - if (rmpp_version && rmpp_version != IB_MGMT_RMPP_VERSION) - goto error1; + if (rmpp_version) + goto error1; /* XXX: until RMPP implemented */ /* Validate MAD registration request if supplied */ if (mad_reg_req) { @@ -260,29 +261,22 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device, ret = ERR_PTR(-ENOMEM); goto error1; } - memset(mad_agent_priv, 0, sizeof *mad_agent_priv); - - mad_agent_priv->agent.mr = ib_get_dma_mr(port_priv->qp_info[qpn].qp->pd, - IB_ACCESS_LOCAL_WRITE); - if (IS_ERR(mad_agent_priv->agent.mr)) { - ret = ERR_PTR(-ENOMEM); - goto error2; - } if (mad_reg_req) { reg_req = kmalloc(sizeof *reg_req, GFP_KERNEL); if (!reg_req) { ret = ERR_PTR(-ENOMEM); - goto error3; + goto error2; } /* Make a copy of the MAD registration request */ memcpy(reg_req, mad_reg_req, sizeof *reg_req); } /* Now, fill in the various structures */ + memset(mad_agent_priv, 0, sizeof *mad_agent_priv); mad_agent_priv->qp_info = &port_priv->qp_info[qpn]; mad_agent_priv->reg_req = reg_req; - mad_agent_priv->agent.rmpp_version = rmpp_version; + mad_agent_priv->rmpp_version = rmpp_version; mad_agent_priv->agent.device = device; mad_agent_priv->agent.recv_handler = recv_handler; mad_agent_priv->agent.send_handler = send_handler; @@ -307,7 +301,7 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device, if (method) { if (method_in_use(&method, mad_reg_req)) - goto error4; + goto error3; } } ret2 = add_nonoui_reg_req(mad_reg_req, mad_agent_priv, @@ -323,14 +317,14 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device, if (is_vendor_method_in_use( vendor_class, mad_reg_req)) - goto error4; + goto error3; } } ret2 = add_oui_reg_req(mad_reg_req, mad_agent_priv); } if (ret2) { ret = ERR_PTR(ret2); - goto error4; + goto error3; } } @@ -341,24 +335,22 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device, spin_lock_init(&mad_agent_priv->lock); INIT_LIST_HEAD(&mad_agent_priv->send_list); INIT_LIST_HEAD(&mad_agent_priv->wait_list); - INIT_LIST_HEAD(&mad_agent_priv->done_list); - INIT_LIST_HEAD(&mad_agent_priv->rmpp_list); INIT_WORK(&mad_agent_priv->timed_work, timeout_sends, mad_agent_priv); INIT_LIST_HEAD(&mad_agent_priv->local_list); INIT_WORK(&mad_agent_priv->local_work, local_completions, mad_agent_priv); + INIT_LIST_HEAD(&mad_agent_priv->canceled_list); + INIT_WORK(&mad_agent_priv->canceled_work, cancel_sends, mad_agent_priv); atomic_set(&mad_agent_priv->refcount, 1); init_waitqueue_head(&mad_agent_priv->wait); return &mad_agent_priv->agent; -error4: +error3: spin_unlock_irqrestore(&port_priv->reg_lock, flags); kfree(reg_req); -error3: - kfree(mad_agent_priv); error2: - ib_dereg_mr(mad_agent_priv->agent.mr); + kfree(mad_agent_priv); error1: return ret; } @@ -495,16 +487,18 @@ static void unregister_mad_agent(struct ib_mad_agent_private *mad_agent_priv) * MADs, preventing us from queuing additional work */ cancel_mads(mad_agent_priv); + port_priv = mad_agent_priv->qp_info->port_priv; + cancel_delayed_work(&mad_agent_priv->timed_work); + flush_workqueue(port_priv->wq); spin_lock_irqsave(&port_priv->reg_lock, flags); remove_mad_reg_req(mad_agent_priv); list_del(&mad_agent_priv->agent_list); spin_unlock_irqrestore(&port_priv->reg_lock, flags); - flush_workqueue(port_priv->wq); - ib_cancel_rmpp_recvs(mad_agent_priv); + /* XXX: Cleanup pending RMPP receives for this agent */ atomic_dec(&mad_agent_priv->refcount); wait_event(mad_agent_priv->wait, @@ -512,7 +506,6 @@ static void unregister_mad_agent(struct ib_mad_agent_private *mad_agent_priv) if (mad_agent_priv->reg_req) kfree(mad_agent_priv->reg_req); - ib_dereg_mr(mad_agent_priv->agent.mr); kfree(mad_agent_priv); } @@ -558,13 +551,6 @@ int ib_unregister_mad_agent(struct ib_mad_agent *mad_agent) } EXPORT_SYMBOL(ib_unregister_mad_agent); -static inline int response_mad(struct ib_mad *mad) -{ - /* Trap represses are responses although response bit is reset */ - return ((mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS) || - (mad->mad_hdr.method & IB_MGMT_METHOD_RESP)); -} - static void dequeue_mad(struct ib_mad_list_head *mad_list) { struct ib_mad_queue *mad_queue; @@ -657,7 +643,7 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv, struct ib_smp *smp, struct ib_send_wr *send_wr) { - int ret; + int ret, solicited; unsigned long flags; struct ib_mad_local_private *local; struct ib_mad_private *mad_priv; @@ -703,7 +689,11 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv, switch (ret) { case IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY: - if (response_mad(&mad_priv->mad.mad) && + /* + * See if response is solicited and + * there is a recv handler + */ + if (solicited_mad(&mad_priv->mad.mad) && mad_agent_priv->agent.recv_handler) { local->mad_priv = mad_priv; local->recv_mad_agent = mad_agent_priv; @@ -720,13 +710,15 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv, break; case IB_MAD_RESULT_SUCCESS: /* Treat like an incoming receive MAD */ + solicited = solicited_mad(&mad_priv->mad.mad); port_priv = ib_get_mad_port(mad_agent_priv->agent.device, mad_agent_priv->agent.port_num); if (port_priv) { mad_priv->mad.mad.mad_hdr.tid = ((struct ib_mad *)smp)->mad_hdr.tid; recv_mad_agent = find_mad_agent(port_priv, - &mad_priv->mad.mad); + &mad_priv->mad.mad, + solicited); } if (!port_priv || !recv_mad_agent) { kmem_cache_free(ib_mad_cache, mad_priv); @@ -758,133 +750,43 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv, list_add_tail(&local->completion_list, &mad_agent_priv->local_list); spin_unlock_irqrestore(&mad_agent_priv->lock, flags); queue_work(mad_agent_priv->qp_info->port_priv->wq, - &mad_agent_priv->local_work); + &mad_agent_priv->local_work); ret = 1; out: return ret; } -static int get_buf_length(int hdr_len, int data_len) -{ - int seg_size, pad; - - seg_size = sizeof(struct ib_mad) - hdr_len; - if (data_len && seg_size) { - pad = seg_size - data_len % seg_size; - if (pad == seg_size) - pad = 0; - } else - pad = seg_size; - return hdr_len + data_len + pad; -} - -struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent, - u32 remote_qpn, u16 pkey_index, - struct ib_ah *ah, int rmpp_active, - int hdr_len, int data_len, - unsigned int __nocast gfp_mask) -{ - struct ib_mad_agent_private *mad_agent_priv; - struct ib_mad_send_buf *send_buf; - int buf_size; - void *buf; - - mad_agent_priv = container_of(mad_agent, - struct ib_mad_agent_private, agent); - buf_size = get_buf_length(hdr_len, data_len); - - if ((!mad_agent->rmpp_version && - (rmpp_active || buf_size > sizeof(struct ib_mad))) || - (!rmpp_active && buf_size > sizeof(struct ib_mad))) - return ERR_PTR(-EINVAL); - - buf = kmalloc(sizeof *send_buf + buf_size, gfp_mask); - if (!buf) - return ERR_PTR(-ENOMEM); - memset(buf, 0, sizeof *send_buf + buf_size); - - send_buf = buf + buf_size; - send_buf->mad = buf; - - send_buf->sge.addr = dma_map_single(mad_agent->device->dma_device, - buf, buf_size, DMA_TO_DEVICE); - pci_unmap_addr_set(send_buf, mapping, send_buf->sge.addr); - send_buf->sge.length = buf_size; - send_buf->sge.lkey = mad_agent->mr->lkey; - - send_buf->send_wr.wr_id = (unsigned long) send_buf; - send_buf->send_wr.sg_list = &send_buf->sge; - send_buf->send_wr.num_sge = 1; - send_buf->send_wr.opcode = IB_WR_SEND; - send_buf->send_wr.send_flags = IB_SEND_SIGNALED; - send_buf->send_wr.wr.ud.ah = ah; - send_buf->send_wr.wr.ud.mad_hdr = &send_buf->mad->mad_hdr; - send_buf->send_wr.wr.ud.remote_qpn = remote_qpn; - send_buf->send_wr.wr.ud.remote_qkey = IB_QP_SET_QKEY; - send_buf->send_wr.wr.ud.pkey_index = pkey_index; - - if (rmpp_active) { - struct ib_rmpp_mad *rmpp_mad; - rmpp_mad = (struct ib_rmpp_mad *)send_buf->mad; - rmpp_mad->rmpp_hdr.paylen_newwin = cpu_to_be32(hdr_len - - offsetof(struct ib_rmpp_mad, data) + data_len); - rmpp_mad->rmpp_hdr.rmpp_version = mad_agent->rmpp_version; - rmpp_mad->rmpp_hdr.rmpp_type = IB_MGMT_RMPP_TYPE_DATA; - ib_set_rmpp_flags(&rmpp_mad->rmpp_hdr, - IB_MGMT_RMPP_FLAG_ACTIVE); - } - - send_buf->mad_agent = mad_agent; - atomic_inc(&mad_agent_priv->refcount); - return send_buf; -} -EXPORT_SYMBOL(ib_create_send_mad); - -void ib_free_send_mad(struct ib_mad_send_buf *send_buf) -{ - struct ib_mad_agent_private *mad_agent_priv; - - mad_agent_priv = container_of(send_buf->mad_agent, - struct ib_mad_agent_private, agent); - - dma_unmap_single(send_buf->mad_agent->device->dma_device, - pci_unmap_addr(send_buf, mapping), - send_buf->sge.length, DMA_TO_DEVICE); - kfree(send_buf->mad); - - if (atomic_dec_and_test(&mad_agent_priv->refcount)) - wake_up(&mad_agent_priv->wait); -} -EXPORT_SYMBOL(ib_free_send_mad); - -int ib_send_mad(struct ib_mad_send_wr_private *mad_send_wr) +static int ib_send_mad(struct ib_mad_agent_private *mad_agent_priv, + struct ib_mad_send_wr_private *mad_send_wr) { struct ib_mad_qp_info *qp_info; struct ib_send_wr *bad_send_wr; - struct list_head *list; unsigned long flags; int ret; - /* Set WR ID to find mad_send_wr upon completion */ - qp_info = mad_send_wr->mad_agent_priv->qp_info; + /* Replace user's WR ID with our own to find WR upon completion */ + qp_info = mad_agent_priv->qp_info; + mad_send_wr->wr_id = mad_send_wr->send_wr.wr_id; mad_send_wr->send_wr.wr_id = (unsigned long)&mad_send_wr->mad_list; mad_send_wr->mad_list.mad_queue = &qp_info->send_queue; spin_lock_irqsave(&qp_info->send_queue.lock, flags); - if (qp_info->send_queue.count < qp_info->send_queue.max_active) { - ret = ib_post_send(mad_send_wr->mad_agent_priv->agent.qp, + if (qp_info->send_queue.count++ < qp_info->send_queue.max_active) { + list_add_tail(&mad_send_wr->mad_list.list, + &qp_info->send_queue.list); + spin_unlock_irqrestore(&qp_info->send_queue.lock, flags); + ret = ib_post_send(mad_agent_priv->agent.qp, &mad_send_wr->send_wr, &bad_send_wr); - list = &qp_info->send_queue.list; + if (ret) { + printk(KERN_ERR PFX "ib_post_send failed: %d\n", ret); + dequeue_mad(&mad_send_wr->mad_list); + } } else { + list_add_tail(&mad_send_wr->mad_list.list, + &qp_info->overflow_list); + spin_unlock_irqrestore(&qp_info->send_queue.lock, flags); ret = 0; - list = &qp_info->overflow_list; } - - if (!ret) { - qp_info->send_queue.count++; - list_add_tail(&mad_send_wr->mad_list.list, list); - } - spin_unlock_irqrestore(&qp_info->send_queue.lock, flags); return ret; } @@ -958,19 +860,18 @@ int ib_post_send_mad(struct ib_mad_agent *mad_agent, ret = -ENOMEM; goto error2; } - memset(mad_send_wr, 0, sizeof *mad_send_wr); mad_send_wr->send_wr = *send_wr; mad_send_wr->send_wr.sg_list = mad_send_wr->sg_list; memcpy(mad_send_wr->sg_list, send_wr->sg_list, sizeof *send_wr->sg_list * send_wr->num_sge); - mad_send_wr->wr_id = send_wr->wr_id; + mad_send_wr->send_wr.next = NULL; mad_send_wr->tid = send_wr->wr.ud.mad_hdr->tid; - mad_send_wr->mad_agent_priv = mad_agent_priv; + mad_send_wr->agent = mad_agent; /* Timeout will be updated after send completes */ mad_send_wr->timeout = msecs_to_jiffies(send_wr->wr. ud.timeout_ms); - mad_send_wr->retries = mad_send_wr->send_wr.wr.ud.retries; + mad_send_wr->retry = 0; /* One reference for each work request to QP + response */ mad_send_wr->refcount = 1 + (mad_send_wr->timeout > 0); mad_send_wr->status = IB_WC_SUCCESS; @@ -982,13 +883,8 @@ int ib_post_send_mad(struct ib_mad_agent *mad_agent, &mad_agent_priv->send_list); spin_unlock_irqrestore(&mad_agent_priv->lock, flags); - if (mad_agent_priv->agent.rmpp_version) { - ret = ib_send_rmpp_mad(mad_send_wr); - if (ret >= 0 && ret != IB_RMPP_RESULT_CONSUMED) - ret = ib_send_mad(mad_send_wr); - } else - ret = ib_send_mad(mad_send_wr); - if (ret < 0) { + ret = ib_send_mad(mad_agent_priv, mad_send_wr); + if (ret) { /* Fail send request */ spin_lock_irqsave(&mad_agent_priv->lock, flags); list_del(&mad_send_wr->agent_list); @@ -1014,28 +910,41 @@ EXPORT_SYMBOL(ib_post_send_mad); */ void ib_free_recv_mad(struct ib_mad_recv_wc *mad_recv_wc) { - struct ib_mad_recv_buf *mad_recv_buf, *temp_recv_buf; + struct ib_mad_recv_buf *entry; struct ib_mad_private_header *mad_priv_hdr; struct ib_mad_private *priv; - struct list_head free_list; - INIT_LIST_HEAD(&free_list); - list_splice_init(&mad_recv_wc->rmpp_list, &free_list); + mad_priv_hdr = container_of(mad_recv_wc, + struct ib_mad_private_header, + recv_wc); + priv = container_of(mad_priv_hdr, struct ib_mad_private, header); - list_for_each_entry_safe(mad_recv_buf, temp_recv_buf, - &free_list, list) { - mad_recv_wc = container_of(mad_recv_buf, struct ib_mad_recv_wc, - recv_buf); + /* + * Walk receive buffer list associated with this WC + * No need to remove them from list of receive buffers + */ + list_for_each_entry(entry, &mad_recv_wc->recv_buf.list, list) { + /* Free previous receive buffer */ + kmem_cache_free(ib_mad_cache, priv); mad_priv_hdr = container_of(mad_recv_wc, struct ib_mad_private_header, recv_wc); priv = container_of(mad_priv_hdr, struct ib_mad_private, header); - kmem_cache_free(ib_mad_cache, priv); } + + /* Free last buffer */ + kmem_cache_free(ib_mad_cache, priv); } EXPORT_SYMBOL(ib_free_recv_mad); +void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc, + void *buf) +{ + printk(KERN_ERR PFX "ib_coalesce_recv_mad() not implemented yet\n"); +} +EXPORT_SYMBOL(ib_coalesce_recv_mad); + struct ib_mad_agent *ib_redirect_mad_qp(struct ib_qp *qp, u8 rmpp_version, ib_mad_send_handler send_handler, @@ -1429,15 +1338,42 @@ static void remove_mad_reg_req(struct ib_mad_agent_private *agent_priv) return; } +static int response_mad(struct ib_mad *mad) +{ + /* Trap represses are responses although response bit is reset */ + return ((mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS) || + (mad->mad_hdr.method & IB_MGMT_METHOD_RESP)); +} + +static int solicited_mad(struct ib_mad *mad) +{ + /* CM MADs are never solicited */ + if (mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CM) { + return 0; + } + + /* XXX: Determine whether MAD is using RMPP */ + + /* Not using RMPP */ + /* Is this MAD a response to a previous MAD ? */ + return response_mad(mad); +} + static struct ib_mad_agent_private * find_mad_agent(struct ib_mad_port_private *port_priv, - struct ib_mad *mad) + struct ib_mad *mad, + int solicited) { struct ib_mad_agent_private *mad_agent = NULL; unsigned long flags; spin_lock_irqsave(&port_priv->reg_lock, flags); - if (response_mad(mad)) { + + /* + * Whether MAD was solicited determines type of routing to + * MAD client. + */ + if (solicited) { u32 hi_tid; struct ib_mad_agent_private *entry; @@ -1541,20 +1477,21 @@ static int validate_mad(struct ib_mad *mad, u32 qp_num) return valid; } -static int is_data_mad(struct ib_mad_agent_private *mad_agent_priv, - struct ib_mad_hdr *mad_hdr) +/* + * Return start of fully reassembled MAD, or NULL, if MAD isn't assembled yet + */ +static struct ib_mad_private * +reassemble_recv(struct ib_mad_agent_private *mad_agent_priv, + struct ib_mad_private *recv) { - struct ib_rmpp_mad *rmpp_mad; - - rmpp_mad = (struct ib_rmpp_mad *)mad_hdr; - return !mad_agent_priv->agent.rmpp_version || - !(ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) & - IB_MGMT_RMPP_FLAG_ACTIVE) || - (rmpp_mad->rmpp_hdr.rmpp_type == IB_MGMT_RMPP_TYPE_DATA); + /* Until we have RMPP, all receives are reassembled!... */ + INIT_LIST_HEAD(&recv->header.recv_wc.recv_buf.list); + return recv; } -struct ib_mad_send_wr_private* -ib_find_send_mad(struct ib_mad_agent_private *mad_agent_priv, u64 tid) +static struct ib_mad_send_wr_private* +find_send_req(struct ib_mad_agent_private *mad_agent_priv, + u64 tid) { struct ib_mad_send_wr_private *mad_send_wr; @@ -1570,9 +1507,7 @@ ib_find_send_mad(struct ib_mad_agent_private *mad_agent_priv, u64 tid) */ list_for_each_entry(mad_send_wr, &mad_agent_priv->send_list, agent_list) { - if (is_data_mad(mad_agent_priv, - mad_send_wr->send_wr.wr.ud.mad_hdr) && - mad_send_wr->tid == tid && mad_send_wr->timeout) { + if (mad_send_wr->tid == tid && mad_send_wr->timeout) { /* Verify request has not been canceled */ return (mad_send_wr->status == IB_WC_SUCCESS) ? mad_send_wr : NULL; @@ -1581,55 +1516,43 @@ ib_find_send_mad(struct ib_mad_agent_private *mad_agent_priv, u64 tid) return NULL; } -void ib_mark_mad_done(struct ib_mad_send_wr_private *mad_send_wr) -{ - mad_send_wr->timeout = 0; - if (mad_send_wr->refcount == 1) { - list_del(&mad_send_wr->agent_list); - list_add_tail(&mad_send_wr->agent_list, - &mad_send_wr->mad_agent_priv->done_list); - } -} - static void ib_mad_complete_recv(struct ib_mad_agent_private *mad_agent_priv, - struct ib_mad_recv_wc *mad_recv_wc) + struct ib_mad_private *recv, + int solicited) { struct ib_mad_send_wr_private *mad_send_wr; struct ib_mad_send_wc mad_send_wc; unsigned long flags; - u64 tid; - - INIT_LIST_HEAD(&mad_recv_wc->rmpp_list); - list_add(&mad_recv_wc->recv_buf.list, &mad_recv_wc->rmpp_list); - if (mad_agent_priv->agent.rmpp_version) { - mad_recv_wc = ib_process_rmpp_recv_wc(mad_agent_priv, - mad_recv_wc); - if (!mad_recv_wc) { - if (atomic_dec_and_test(&mad_agent_priv->refcount)) - wake_up(&mad_agent_priv->wait); - return; - } + + /* Fully reassemble receive before processing */ + recv = reassemble_recv(mad_agent_priv, recv); + if (!recv) { + if (atomic_dec_and_test(&mad_agent_priv->refcount)) + wake_up(&mad_agent_priv->wait); + return; } /* Complete corresponding request */ - if (response_mad(mad_recv_wc->recv_buf.mad)) { - tid = mad_recv_wc->recv_buf.mad->mad_hdr.tid; + if (solicited) { spin_lock_irqsave(&mad_agent_priv->lock, flags); - mad_send_wr = ib_find_send_mad(mad_agent_priv, tid); + mad_send_wr = find_send_req(mad_agent_priv, + recv->mad.mad.mad_hdr.tid); if (!mad_send_wr) { spin_unlock_irqrestore(&mad_agent_priv->lock, flags); - ib_free_recv_mad(mad_recv_wc); + ib_free_recv_mad(&recv->header.recv_wc); if (atomic_dec_and_test(&mad_agent_priv->refcount)) wake_up(&mad_agent_priv->wait); return; } - ib_mark_mad_done(mad_send_wr); + /* Timeout = 0 means that we won't wait for a response */ + mad_send_wr->timeout = 0; spin_unlock_irqrestore(&mad_agent_priv->lock, flags); /* Defined behavior is to complete response before request */ - mad_recv_wc->wc->wr_id = mad_send_wr->wr_id; - mad_agent_priv->agent.recv_handler(&mad_agent_priv->agent, - mad_recv_wc); + recv->header.recv_wc.wc->wr_id = mad_send_wr->wr_id; + mad_agent_priv->agent.recv_handler( + &mad_agent_priv->agent, + &recv->header.recv_wc); atomic_dec(&mad_agent_priv->refcount); mad_send_wc.status = IB_WC_SUCCESS; @@ -1637,8 +1560,9 @@ static void ib_mad_complete_recv(struct ib_mad_agent_private *mad_agent_priv, mad_send_wc.wr_id = mad_send_wr->wr_id; ib_mad_complete_send_wr(mad_send_wr, &mad_send_wc); } else { - mad_agent_priv->agent.recv_handler(&mad_agent_priv->agent, - mad_recv_wc); + mad_agent_priv->agent.recv_handler( + &mad_agent_priv->agent, + &recv->header.recv_wc); if (atomic_dec_and_test(&mad_agent_priv->refcount)) wake_up(&mad_agent_priv->wait); } @@ -1652,6 +1576,7 @@ static void ib_mad_recv_done_handler(struct ib_mad_port_private *port_priv, struct ib_mad_private *recv, *response; struct ib_mad_list_head *mad_list; struct ib_mad_agent_private *mad_agent; + int solicited; response = kmem_cache_alloc(ib_mad_cache, GFP_KERNEL); if (!response) @@ -1737,9 +1662,11 @@ static void ib_mad_recv_done_handler(struct ib_mad_port_private *port_priv, } } - mad_agent = find_mad_agent(port_priv, &recv->mad.mad); + /* Determine corresponding MAD agent for incoming receive MAD */ + solicited = solicited_mad(&recv->mad.mad); + mad_agent = find_mad_agent(port_priv, &recv->mad.mad, solicited); if (mad_agent) { - ib_mad_complete_recv(mad_agent, &recv->header.recv_wc); + ib_mad_complete_recv(mad_agent, recv, solicited); /* * recv is freed up in error cases in ib_mad_complete_recv * or via recv_handler in ib_mad_complete_recv() @@ -1783,31 +1710,26 @@ static void adjust_timeout(struct ib_mad_agent_private *mad_agent_priv) } } -static void wait_for_response(struct ib_mad_send_wr_private *mad_send_wr) +static void wait_for_response(struct ib_mad_agent_private *mad_agent_priv, + struct ib_mad_send_wr_private *mad_send_wr ) { - struct ib_mad_agent_private *mad_agent_priv; struct ib_mad_send_wr_private *temp_mad_send_wr; struct list_head *list_item; unsigned long delay; - mad_agent_priv = mad_send_wr->mad_agent_priv; list_del(&mad_send_wr->agent_list); delay = mad_send_wr->timeout; mad_send_wr->timeout += jiffies; - if (delay) { - list_for_each_prev(list_item, &mad_agent_priv->wait_list) { - temp_mad_send_wr = list_entry(list_item, - struct ib_mad_send_wr_private, - agent_list); - if (time_after(mad_send_wr->timeout, - temp_mad_send_wr->timeout)) - break; - } + list_for_each_prev(list_item, &mad_agent_priv->wait_list) { + temp_mad_send_wr = list_entry(list_item, + struct ib_mad_send_wr_private, + agent_list); + if (time_after(mad_send_wr->timeout, + temp_mad_send_wr->timeout)) + break; } - else - list_item = &mad_agent_priv->wait_list; list_add(&mad_send_wr->agent_list, list_item); /* Reschedule a work item if we have a shorter timeout */ @@ -1818,32 +1740,19 @@ static void wait_for_response(struct ib_mad_send_wr_private *mad_send_wr) } } -void ib_reset_mad_timeout(struct ib_mad_send_wr_private *mad_send_wr, - int timeout_ms) -{ - mad_send_wr->timeout = msecs_to_jiffies(timeout_ms); - wait_for_response(mad_send_wr); -} - /* * Process a send work completion */ -void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr, - struct ib_mad_send_wc *mad_send_wc) +static void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr, + struct ib_mad_send_wc *mad_send_wc) { struct ib_mad_agent_private *mad_agent_priv; unsigned long flags; - int ret; - mad_agent_priv = mad_send_wr->mad_agent_priv; - spin_lock_irqsave(&mad_agent_priv->lock, flags); - if (mad_agent_priv->agent.rmpp_version) { - ret = ib_process_rmpp_send_wc(mad_send_wr, mad_send_wc); - if (ret == IB_RMPP_RESULT_CONSUMED) - goto done; - } else - ret = IB_RMPP_RESULT_UNHANDLED; + mad_agent_priv = container_of(mad_send_wr->agent, + struct ib_mad_agent_private, agent); + spin_lock_irqsave(&mad_agent_priv->lock, flags); if (mad_send_wc->status != IB_WC_SUCCESS && mad_send_wr->status == IB_WC_SUCCESS) { mad_send_wr->status = mad_send_wc->status; @@ -1853,9 +1762,10 @@ void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr, if (--mad_send_wr->refcount > 0) { if (mad_send_wr->refcount == 1 && mad_send_wr->timeout && mad_send_wr->status == IB_WC_SUCCESS) { - wait_for_response(mad_send_wr); + wait_for_response(mad_agent_priv, mad_send_wr); } - goto done; + spin_unlock_irqrestore(&mad_agent_priv->lock, flags); + return; } /* Remove send from MAD agent and notify client of completion */ @@ -1865,18 +1775,14 @@ void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr, if (mad_send_wr->status != IB_WC_SUCCESS ) mad_send_wc->status = mad_send_wr->status; - if (ret != IB_RMPP_RESULT_INTERNAL) - mad_agent_priv->agent.send_handler(&mad_agent_priv->agent, - mad_send_wc); + mad_agent_priv->agent.send_handler(&mad_agent_priv->agent, + mad_send_wc); /* Release reference on agent taken when sending */ if (atomic_dec_and_test(&mad_agent_priv->refcount)) wake_up(&mad_agent_priv->wait); kfree(mad_send_wr); - return; -done: - spin_unlock_irqrestore(&mad_agent_priv->lock, flags); } static void ib_mad_send_done_handler(struct ib_mad_port_private *port_priv, @@ -2055,8 +1961,6 @@ static void cancel_mads(struct ib_mad_agent_private *mad_agent_priv) /* Empty wait list to prevent receives from finding a request */ list_splice_init(&mad_agent_priv->wait_list, &cancel_list); - /* Empty local completion list as well */ - list_splice_init(&mad_agent_priv->local_list, &cancel_list); spin_unlock_irqrestore(&mad_agent_priv->lock, flags); /* Report all cancelled requests */ @@ -2076,7 +1980,8 @@ static void cancel_mads(struct ib_mad_agent_private *mad_agent_priv) } static struct ib_mad_send_wr_private* -find_send_by_wr_id(struct ib_mad_agent_private *mad_agent_priv, u64 wr_id) +find_send_by_wr_id(struct ib_mad_agent_private *mad_agent_priv, + u64 wr_id) { struct ib_mad_send_wr_private *mad_send_wr; @@ -2088,50 +1993,79 @@ find_send_by_wr_id(struct ib_mad_agent_private *mad_agent_priv, u64 wr_id) list_for_each_entry(mad_send_wr, &mad_agent_priv->send_list, agent_list) { - if (is_data_mad(mad_agent_priv, - mad_send_wr->send_wr.wr.ud.mad_hdr) && - mad_send_wr->wr_id == wr_id) + if (mad_send_wr->wr_id == wr_id) return mad_send_wr; } return NULL; } -int ib_modify_mad(struct ib_mad_agent *mad_agent, u64 wr_id, u32 timeout_ms) +void cancel_sends(void *data) +{ + struct ib_mad_agent_private *mad_agent_priv; + struct ib_mad_send_wr_private *mad_send_wr; + struct ib_mad_send_wc mad_send_wc; + unsigned long flags; + + mad_agent_priv = data; + + mad_send_wc.status = IB_WC_WR_FLUSH_ERR; + mad_send_wc.vendor_err = 0; + + spin_lock_irqsave(&mad_agent_priv->lock, flags); + while (!list_empty(&mad_agent_priv->canceled_list)) { + mad_send_wr = list_entry(mad_agent_priv->canceled_list.next, + struct ib_mad_send_wr_private, + agent_list); + + list_del(&mad_send_wr->agent_list); + spin_unlock_irqrestore(&mad_agent_priv->lock, flags); + + mad_send_wc.wr_id = mad_send_wr->wr_id; + mad_agent_priv->agent.send_handler(&mad_agent_priv->agent, + &mad_send_wc); + + kfree(mad_send_wr); + if (atomic_dec_and_test(&mad_agent_priv->refcount)) + wake_up(&mad_agent_priv->wait); + spin_lock_irqsave(&mad_agent_priv->lock, flags); + } + spin_unlock_irqrestore(&mad_agent_priv->lock, flags); +} + +void ib_cancel_mad(struct ib_mad_agent *mad_agent, + u64 wr_id) { struct ib_mad_agent_private *mad_agent_priv; struct ib_mad_send_wr_private *mad_send_wr; unsigned long flags; - int active; mad_agent_priv = container_of(mad_agent, struct ib_mad_agent_private, agent); spin_lock_irqsave(&mad_agent_priv->lock, flags); mad_send_wr = find_send_by_wr_id(mad_agent_priv, wr_id); - if (!mad_send_wr || mad_send_wr->status != IB_WC_SUCCESS) { + if (!mad_send_wr) { spin_unlock_irqrestore(&mad_agent_priv->lock, flags); - return -EINVAL; + goto out; } - active = (!mad_send_wr->timeout || mad_send_wr->refcount > 1); - if (!timeout_ms) { - mad_send_wr->status = IB_WC_WR_FLUSH_ERR; + if (mad_send_wr->status == IB_WC_SUCCESS) mad_send_wr->refcount -= (mad_send_wr->timeout > 0); - } - mad_send_wr->send_wr.wr.ud.timeout_ms = timeout_ms; - if (active) - mad_send_wr->timeout = msecs_to_jiffies(timeout_ms); - else - ib_reset_mad_timeout(mad_send_wr, timeout_ms); + if (mad_send_wr->refcount != 0) { + mad_send_wr->status = IB_WC_WR_FLUSH_ERR; + spin_unlock_irqrestore(&mad_agent_priv->lock, flags); + goto out; + } + list_del(&mad_send_wr->agent_list); + list_add_tail(&mad_send_wr->agent_list, &mad_agent_priv->canceled_list); + adjust_timeout(mad_agent_priv); spin_unlock_irqrestore(&mad_agent_priv->lock, flags); - return 0; -} -EXPORT_SYMBOL(ib_modify_mad); -void ib_cancel_mad(struct ib_mad_agent *mad_agent, u64 wr_id) -{ - ib_modify_mad(mad_agent, wr_id, 0); + queue_work(mad_agent_priv->qp_info->port_priv->wq, + &mad_agent_priv->canceled_work); +out: + return; } EXPORT_SYMBOL(ib_cancel_mad); @@ -2141,7 +2075,6 @@ static void local_completions(void *data) struct ib_mad_local_private *local; struct ib_mad_agent_private *recv_mad_agent; unsigned long flags; - int recv = 0; struct ib_wc wc; struct ib_mad_send_wc mad_send_wc; @@ -2157,10 +2090,10 @@ static void local_completions(void *data) recv_mad_agent = local->recv_mad_agent; if (!recv_mad_agent) { printk(KERN_ERR PFX "No receive MAD agent for local completion\n"); + kmem_cache_free(ib_mad_cache, local->mad_priv); goto local_send_completion; } - recv = 1; /* * Defined behavior is to complete response * before request @@ -2172,9 +2105,7 @@ static void local_completions(void *data) local->mad_priv->header.recv_wc.wc = &wc; local->mad_priv->header.recv_wc.mad_len = sizeof(struct ib_mad); - INIT_LIST_HEAD(&local->mad_priv->header.recv_wc.rmpp_list); - list_add(&local->mad_priv->header.recv_wc.recv_buf.list, - &local->mad_priv->header.recv_wc.rmpp_list); + INIT_LIST_HEAD(&local->mad_priv->header.recv_wc.recv_buf.list); local->mad_priv->header.recv_wc.recv_buf.grh = NULL; local->mad_priv->header.recv_wc.recv_buf.mad = &local->mad_priv->mad.mad; @@ -2205,47 +2136,11 @@ static void local_completions(void *data) spin_lock_irqsave(&mad_agent_priv->lock, flags); list_del(&local->completion_list); atomic_dec(&mad_agent_priv->refcount); - if (!recv) - kmem_cache_free(ib_mad_cache, local->mad_priv); kfree(local); } spin_unlock_irqrestore(&mad_agent_priv->lock, flags); } -static int retry_send(struct ib_mad_send_wr_private *mad_send_wr) -{ - int ret; - - if (!mad_send_wr->retries--) - return -ETIMEDOUT; - - mad_send_wr->timeout = msecs_to_jiffies(mad_send_wr->send_wr. - wr.ud.timeout_ms); - - if (mad_send_wr->mad_agent_priv->agent.rmpp_version) { - ret = ib_retry_rmpp(mad_send_wr); - switch (ret) { - case IB_RMPP_RESULT_UNHANDLED: - ret = ib_send_mad(mad_send_wr); - break; - case IB_RMPP_RESULT_CONSUMED: - ret = 0; - break; - default: - ret = -ECOMM; - break; - } - } else - ret = ib_send_mad(mad_send_wr); - - if (!ret) { - mad_send_wr->refcount++; - list_add_tail(&mad_send_wr->agent_list, - &mad_send_wr->mad_agent_priv->send_list); - } - return ret; -} - static void timeout_sends(void *data) { struct ib_mad_agent_private *mad_agent_priv; @@ -2254,6 +2149,8 @@ static void timeout_sends(void *data) unsigned long flags, delay; mad_agent_priv = (struct ib_mad_agent_private *)data; + + mad_send_wc.status = IB_WC_RESP_TIMEOUT_ERR; mad_send_wc.vendor_err = 0; spin_lock_irqsave(&mad_agent_priv->lock, flags); @@ -2273,16 +2170,8 @@ static void timeout_sends(void *data) } list_del(&mad_send_wr->agent_list); - if (mad_send_wr->status == IB_WC_SUCCESS && - !retry_send(mad_send_wr)) - continue; - spin_unlock_irqrestore(&mad_agent_priv->lock, flags); - if (mad_send_wr->status == IB_WC_SUCCESS) - mad_send_wc.status = IB_WC_RESP_TIMEOUT_ERR; - else - mad_send_wc.status = mad_send_wr->status; mad_send_wc.wr_id = mad_send_wr->wr_id; mad_agent_priv->agent.send_handler(&mad_agent_priv->agent, &mad_send_wc); @@ -2558,6 +2447,14 @@ static int ib_mad_port_open(struct ib_device *device, unsigned long flags; char name[sizeof "ib_mad123"]; + /* First, check if port already open at MAD layer */ + port_priv = ib_get_mad_port(device, port_num); + if (port_priv) { + printk(KERN_DEBUG PFX "%s port %d already open\n", + device->name, port_num); + return 0; + } + /* Create new device info */ port_priv = kmalloc(sizeof *port_priv, GFP_KERNEL); if (!port_priv) { @@ -2682,7 +2579,7 @@ static int ib_mad_port_close(struct ib_device *device, int port_num) static void ib_mad_init_device(struct ib_device *device) { - int num_ports, cur_port, i; + int ret, num_ports, cur_port, i, ret2; if (device->node_type == IB_NODE_SWITCH) { num_ports = 1; @@ -2692,37 +2589,47 @@ static void ib_mad_init_device(struct ib_device *device) cur_port = 1; } for (i = 0; i < num_ports; i++, cur_port++) { - if (ib_mad_port_open(device, cur_port)) { + ret = ib_mad_port_open(device, cur_port); + if (ret) { printk(KERN_ERR PFX "Couldn't open %s port %d\n", device->name, cur_port); goto error_device_open; } - if (ib_agent_port_open(device, cur_port)) { + ret = ib_agent_port_open(device, cur_port); + if (ret) { printk(KERN_ERR PFX "Couldn't open %s port %d " "for agents\n", device->name, cur_port); goto error_device_open; } } - return; + + goto error_device_query; error_device_open: while (i > 0) { cur_port--; - if (ib_agent_port_close(device, cur_port)) + ret2 = ib_agent_port_close(device, cur_port); + if (ret2) { printk(KERN_ERR PFX "Couldn't close %s port %d " "for agents\n", device->name, cur_port); - if (ib_mad_port_close(device, cur_port)) + } + ret2 = ib_mad_port_close(device, cur_port); + if (ret2) { printk(KERN_ERR PFX "Couldn't close %s port %d\n", device->name, cur_port); + } i--; } + +error_device_query: + return; } static void ib_mad_remove_device(struct ib_device *device) { - int i, num_ports, cur_port; + int ret = 0, i, num_ports, cur_port, ret2; if (device->node_type == IB_NODE_SWITCH) { num_ports = 1; @@ -2732,13 +2639,21 @@ static void ib_mad_remove_device(struct ib_device *device) cur_port = 1; } for (i = 0; i < num_ports; i++, cur_port++) { - if (ib_agent_port_close(device, cur_port)) + ret2 = ib_agent_port_close(device, cur_port); + if (ret2) { printk(KERN_ERR PFX "Couldn't close %s port %d " "for agents\n", device->name, cur_port); - if (ib_mad_port_close(device, cur_port)) + if (!ret) + ret = ret2; + } + ret2 = ib_mad_port_close(device, cur_port); + if (ret2) { printk(KERN_ERR PFX "Couldn't close %s port %d\n", device->name, cur_port); + if (!ret) + ret = ret2; + } } } @@ -2794,4 +2709,3 @@ static void __exit ib_mad_cleanup_module(void) module_init(ib_mad_init_module); module_exit(ib_mad_cleanup_module); - diff --git a/trunk/drivers/infiniband/core/mad_priv.h b/trunk/drivers/infiniband/core/mad_priv.h index 568da10b05ab..008cbcb94b15 100644 --- a/trunk/drivers/infiniband/core/mad_priv.h +++ b/trunk/drivers/infiniband/core/mad_priv.h @@ -1,7 +1,5 @@ /* * Copyright (c) 2004, 2005, Voltaire, Inc. All rights reserved. - * Copyright (c) 2005 Intel Corporation. All rights reserved. - * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU @@ -31,7 +29,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: mad_priv.h 2730 2005-06-28 16:43:03Z sean.hefty $ + * $Id: mad_priv.h 1389 2004-12-27 22:56:47Z roland $ */ #ifndef __IB_MAD_PRIV_H__ @@ -94,15 +92,16 @@ struct ib_mad_agent_private { spinlock_t lock; struct list_head send_list; struct list_head wait_list; - struct list_head done_list; struct work_struct timed_work; unsigned long timeout; struct list_head local_list; struct work_struct local_work; - struct list_head rmpp_list; + struct list_head canceled_list; + struct work_struct canceled_work; atomic_t refcount; wait_queue_head_t wait; + u8 rmpp_version; }; struct ib_mad_snoop_private { @@ -117,24 +116,15 @@ struct ib_mad_snoop_private { struct ib_mad_send_wr_private { struct ib_mad_list_head mad_list; struct list_head agent_list; - struct ib_mad_agent_private *mad_agent_priv; + struct ib_mad_agent *agent; struct ib_send_wr send_wr; struct ib_sge sg_list[IB_MAD_SEND_REQ_MAX_SG]; u64 wr_id; /* client WR ID */ u64 tid; unsigned long timeout; - int retries; int retry; int refcount; enum ib_wc_status status; - - /* RMPP control */ - int last_ack; - int seg_num; - int newwin; - int total_seg; - int data_offset; - int pad; }; struct ib_mad_local_private { @@ -207,17 +197,4 @@ struct ib_mad_port_private { extern kmem_cache_t *ib_mad_cache; -int ib_send_mad(struct ib_mad_send_wr_private *mad_send_wr); - -struct ib_mad_send_wr_private * -ib_find_send_mad(struct ib_mad_agent_private *mad_agent_priv, u64 tid); - -void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr, - struct ib_mad_send_wc *mad_send_wc); - -void ib_mark_mad_done(struct ib_mad_send_wr_private *mad_send_wr); - -void ib_reset_mad_timeout(struct ib_mad_send_wr_private *mad_send_wr, - int timeout_ms); - #endif /* __IB_MAD_PRIV_H__ */ diff --git a/trunk/drivers/infiniband/core/mad_rmpp.c b/trunk/drivers/infiniband/core/mad_rmpp.c deleted file mode 100644 index 8f1eb80e421f..000000000000 --- a/trunk/drivers/infiniband/core/mad_rmpp.c +++ /dev/null @@ -1,765 +0,0 @@ -/* - * Copyright (c) 2005 Intel Inc. All rights reserved. - * Copyright (c) 2005 Voltaire, Inc. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * $Id: mad_rmpp.c 1921 2005-03-02 22:58:44Z sean.hefty $ - */ - -#include - -#include "mad_priv.h" -#include "mad_rmpp.h" - -enum rmpp_state { - RMPP_STATE_ACTIVE, - RMPP_STATE_TIMEOUT, - RMPP_STATE_COMPLETE -}; - -struct mad_rmpp_recv { - struct ib_mad_agent_private *agent; - struct list_head list; - struct work_struct timeout_work; - struct work_struct cleanup_work; - wait_queue_head_t wait; - enum rmpp_state state; - spinlock_t lock; - atomic_t refcount; - - struct ib_ah *ah; - struct ib_mad_recv_wc *rmpp_wc; - struct ib_mad_recv_buf *cur_seg_buf; - int last_ack; - int seg_num; - int newwin; - - u64 tid; - u32 src_qp; - u16 slid; - u8 mgmt_class; - u8 class_version; - u8 method; -}; - -static void destroy_rmpp_recv(struct mad_rmpp_recv *rmpp_recv) -{ - atomic_dec(&rmpp_recv->refcount); - wait_event(rmpp_recv->wait, !atomic_read(&rmpp_recv->refcount)); - ib_destroy_ah(rmpp_recv->ah); - kfree(rmpp_recv); -} - -void ib_cancel_rmpp_recvs(struct ib_mad_agent_private *agent) -{ - struct mad_rmpp_recv *rmpp_recv, *temp_rmpp_recv; - unsigned long flags; - - spin_lock_irqsave(&agent->lock, flags); - list_for_each_entry(rmpp_recv, &agent->rmpp_list, list) { - cancel_delayed_work(&rmpp_recv->timeout_work); - cancel_delayed_work(&rmpp_recv->cleanup_work); - } - spin_unlock_irqrestore(&agent->lock, flags); - - flush_workqueue(agent->qp_info->port_priv->wq); - - list_for_each_entry_safe(rmpp_recv, temp_rmpp_recv, - &agent->rmpp_list, list) { - list_del(&rmpp_recv->list); - if (rmpp_recv->state != RMPP_STATE_COMPLETE) - ib_free_recv_mad(rmpp_recv->rmpp_wc); - destroy_rmpp_recv(rmpp_recv); - } -} - -static void recv_timeout_handler(void *data) -{ - struct mad_rmpp_recv *rmpp_recv = data; - struct ib_mad_recv_wc *rmpp_wc; - unsigned long flags; - - spin_lock_irqsave(&rmpp_recv->agent->lock, flags); - if (rmpp_recv->state != RMPP_STATE_ACTIVE) { - spin_unlock_irqrestore(&rmpp_recv->agent->lock, flags); - return; - } - rmpp_recv->state = RMPP_STATE_TIMEOUT; - list_del(&rmpp_recv->list); - spin_unlock_irqrestore(&rmpp_recv->agent->lock, flags); - - /* TODO: send abort. */ - rmpp_wc = rmpp_recv->rmpp_wc; - destroy_rmpp_recv(rmpp_recv); - ib_free_recv_mad(rmpp_wc); -} - -static void recv_cleanup_handler(void *data) -{ - struct mad_rmpp_recv *rmpp_recv = data; - unsigned long flags; - - spin_lock_irqsave(&rmpp_recv->agent->lock, flags); - list_del(&rmpp_recv->list); - spin_unlock_irqrestore(&rmpp_recv->agent->lock, flags); - destroy_rmpp_recv(rmpp_recv); -} - -static struct mad_rmpp_recv * -create_rmpp_recv(struct ib_mad_agent_private *agent, - struct ib_mad_recv_wc *mad_recv_wc) -{ - struct mad_rmpp_recv *rmpp_recv; - struct ib_mad_hdr *mad_hdr; - - rmpp_recv = kmalloc(sizeof *rmpp_recv, GFP_KERNEL); - if (!rmpp_recv) - return NULL; - - rmpp_recv->ah = ib_create_ah_from_wc(agent->agent.qp->pd, - mad_recv_wc->wc, - mad_recv_wc->recv_buf.grh, - agent->agent.port_num); - if (IS_ERR(rmpp_recv->ah)) - goto error; - - rmpp_recv->agent = agent; - init_waitqueue_head(&rmpp_recv->wait); - INIT_WORK(&rmpp_recv->timeout_work, recv_timeout_handler, rmpp_recv); - INIT_WORK(&rmpp_recv->cleanup_work, recv_cleanup_handler, rmpp_recv); - spin_lock_init(&rmpp_recv->lock); - rmpp_recv->state = RMPP_STATE_ACTIVE; - atomic_set(&rmpp_recv->refcount, 1); - - rmpp_recv->rmpp_wc = mad_recv_wc; - rmpp_recv->cur_seg_buf = &mad_recv_wc->recv_buf; - rmpp_recv->newwin = 1; - rmpp_recv->seg_num = 1; - rmpp_recv->last_ack = 0; - - mad_hdr = &mad_recv_wc->recv_buf.mad->mad_hdr; - rmpp_recv->tid = mad_hdr->tid; - rmpp_recv->src_qp = mad_recv_wc->wc->src_qp; - rmpp_recv->slid = mad_recv_wc->wc->slid; - rmpp_recv->mgmt_class = mad_hdr->mgmt_class; - rmpp_recv->class_version = mad_hdr->class_version; - rmpp_recv->method = mad_hdr->method; - return rmpp_recv; - -error: kfree(rmpp_recv); - return NULL; -} - -static inline void deref_rmpp_recv(struct mad_rmpp_recv *rmpp_recv) -{ - if (atomic_dec_and_test(&rmpp_recv->refcount)) - wake_up(&rmpp_recv->wait); -} - -static struct mad_rmpp_recv * -find_rmpp_recv(struct ib_mad_agent_private *agent, - struct ib_mad_recv_wc *mad_recv_wc) -{ - struct mad_rmpp_recv *rmpp_recv; - struct ib_mad_hdr *mad_hdr = &mad_recv_wc->recv_buf.mad->mad_hdr; - - list_for_each_entry(rmpp_recv, &agent->rmpp_list, list) { - if (rmpp_recv->tid == mad_hdr->tid && - rmpp_recv->src_qp == mad_recv_wc->wc->src_qp && - rmpp_recv->slid == mad_recv_wc->wc->slid && - rmpp_recv->mgmt_class == mad_hdr->mgmt_class && - rmpp_recv->class_version == mad_hdr->class_version && - rmpp_recv->method == mad_hdr->method) - return rmpp_recv; - } - return NULL; -} - -static struct mad_rmpp_recv * -acquire_rmpp_recv(struct ib_mad_agent_private *agent, - struct ib_mad_recv_wc *mad_recv_wc) -{ - struct mad_rmpp_recv *rmpp_recv; - unsigned long flags; - - spin_lock_irqsave(&agent->lock, flags); - rmpp_recv = find_rmpp_recv(agent, mad_recv_wc); - if (rmpp_recv) - atomic_inc(&rmpp_recv->refcount); - spin_unlock_irqrestore(&agent->lock, flags); - return rmpp_recv; -} - -static struct mad_rmpp_recv * -insert_rmpp_recv(struct ib_mad_agent_private *agent, - struct mad_rmpp_recv *rmpp_recv) -{ - struct mad_rmpp_recv *cur_rmpp_recv; - - cur_rmpp_recv = find_rmpp_recv(agent, rmpp_recv->rmpp_wc); - if (!cur_rmpp_recv) - list_add_tail(&rmpp_recv->list, &agent->rmpp_list); - - return cur_rmpp_recv; -} - -static int data_offset(u8 mgmt_class) -{ - if (mgmt_class == IB_MGMT_CLASS_SUBN_ADM) - return offsetof(struct ib_sa_mad, data); - else if ((mgmt_class >= IB_MGMT_CLASS_VENDOR_RANGE2_START) && - (mgmt_class <= IB_MGMT_CLASS_VENDOR_RANGE2_END)) - return offsetof(struct ib_vendor_mad, data); - else - return offsetof(struct ib_rmpp_mad, data); -} - -static void format_ack(struct ib_rmpp_mad *ack, - struct ib_rmpp_mad *data, - struct mad_rmpp_recv *rmpp_recv) -{ - unsigned long flags; - - memcpy(&ack->mad_hdr, &data->mad_hdr, - data_offset(data->mad_hdr.mgmt_class)); - - ack->mad_hdr.method ^= IB_MGMT_METHOD_RESP; - ack->rmpp_hdr.rmpp_type = IB_MGMT_RMPP_TYPE_ACK; - ib_set_rmpp_flags(&ack->rmpp_hdr, IB_MGMT_RMPP_FLAG_ACTIVE); - - spin_lock_irqsave(&rmpp_recv->lock, flags); - rmpp_recv->last_ack = rmpp_recv->seg_num; - ack->rmpp_hdr.seg_num = cpu_to_be32(rmpp_recv->seg_num); - ack->rmpp_hdr.paylen_newwin = cpu_to_be32(rmpp_recv->newwin); - spin_unlock_irqrestore(&rmpp_recv->lock, flags); -} - -static void ack_recv(struct mad_rmpp_recv *rmpp_recv, - struct ib_mad_recv_wc *recv_wc) -{ - struct ib_mad_send_buf *msg; - struct ib_send_wr *bad_send_wr; - int hdr_len, ret; - - hdr_len = sizeof(struct ib_mad_hdr) + sizeof(struct ib_rmpp_hdr); - msg = ib_create_send_mad(&rmpp_recv->agent->agent, recv_wc->wc->src_qp, - recv_wc->wc->pkey_index, rmpp_recv->ah, 1, - hdr_len, sizeof(struct ib_rmpp_mad) - hdr_len, - GFP_KERNEL); - if (!msg) - return; - - format_ack((struct ib_rmpp_mad *) msg->mad, - (struct ib_rmpp_mad *) recv_wc->recv_buf.mad, rmpp_recv); - ret = ib_post_send_mad(&rmpp_recv->agent->agent, &msg->send_wr, - &bad_send_wr); - if (ret) - ib_free_send_mad(msg); -} - -static inline int get_last_flag(struct ib_mad_recv_buf *seg) -{ - struct ib_rmpp_mad *rmpp_mad; - - rmpp_mad = (struct ib_rmpp_mad *) seg->mad; - return ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) & IB_MGMT_RMPP_FLAG_LAST; -} - -static inline int get_seg_num(struct ib_mad_recv_buf *seg) -{ - struct ib_rmpp_mad *rmpp_mad; - - rmpp_mad = (struct ib_rmpp_mad *) seg->mad; - return be32_to_cpu(rmpp_mad->rmpp_hdr.seg_num); -} - -static inline struct ib_mad_recv_buf * get_next_seg(struct list_head *rmpp_list, - struct ib_mad_recv_buf *seg) -{ - if (seg->list.next == rmpp_list) - return NULL; - - return container_of(seg->list.next, struct ib_mad_recv_buf, list); -} - -static inline int window_size(struct ib_mad_agent_private *agent) -{ - return max(agent->qp_info->recv_queue.max_active >> 3, 1); -} - -static struct ib_mad_recv_buf * find_seg_location(struct list_head *rmpp_list, - int seg_num) -{ - struct ib_mad_recv_buf *seg_buf; - int cur_seg_num; - - list_for_each_entry_reverse(seg_buf, rmpp_list, list) { - cur_seg_num = get_seg_num(seg_buf); - if (seg_num > cur_seg_num) - return seg_buf; - if (seg_num == cur_seg_num) - break; - } - return NULL; -} - -static void update_seg_num(struct mad_rmpp_recv *rmpp_recv, - struct ib_mad_recv_buf *new_buf) -{ - struct list_head *rmpp_list = &rmpp_recv->rmpp_wc->rmpp_list; - - while (new_buf && (get_seg_num(new_buf) == rmpp_recv->seg_num + 1)) { - rmpp_recv->cur_seg_buf = new_buf; - rmpp_recv->seg_num++; - new_buf = get_next_seg(rmpp_list, new_buf); - } -} - -static inline int get_mad_len(struct mad_rmpp_recv *rmpp_recv) -{ - struct ib_rmpp_mad *rmpp_mad; - int hdr_size, data_size, pad; - - rmpp_mad = (struct ib_rmpp_mad *)rmpp_recv->cur_seg_buf->mad; - - hdr_size = data_offset(rmpp_mad->mad_hdr.mgmt_class); - data_size = sizeof(struct ib_rmpp_mad) - hdr_size; - pad = data_size - be32_to_cpu(rmpp_mad->rmpp_hdr.paylen_newwin); - if (pad > data_size || pad < 0) - pad = 0; - - return hdr_size + rmpp_recv->seg_num * data_size - pad; -} - -static struct ib_mad_recv_wc * complete_rmpp(struct mad_rmpp_recv *rmpp_recv) -{ - struct ib_mad_recv_wc *rmpp_wc; - - ack_recv(rmpp_recv, rmpp_recv->rmpp_wc); - if (rmpp_recv->seg_num > 1) - cancel_delayed_work(&rmpp_recv->timeout_work); - - rmpp_wc = rmpp_recv->rmpp_wc; - rmpp_wc->mad_len = get_mad_len(rmpp_recv); - /* 10 seconds until we can find the packet lifetime */ - queue_delayed_work(rmpp_recv->agent->qp_info->port_priv->wq, - &rmpp_recv->cleanup_work, msecs_to_jiffies(10000)); - return rmpp_wc; -} - -void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc, void *buf) -{ - struct ib_mad_recv_buf *seg_buf; - struct ib_rmpp_mad *rmpp_mad; - void *data; - int size, len, offset; - u8 flags; - - len = mad_recv_wc->mad_len; - if (len <= sizeof(struct ib_mad)) { - memcpy(buf, mad_recv_wc->recv_buf.mad, len); - return; - } - - offset = data_offset(mad_recv_wc->recv_buf.mad->mad_hdr.mgmt_class); - - list_for_each_entry(seg_buf, &mad_recv_wc->rmpp_list, list) { - rmpp_mad = (struct ib_rmpp_mad *)seg_buf->mad; - flags = ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr); - - if (flags & IB_MGMT_RMPP_FLAG_FIRST) { - data = rmpp_mad; - size = sizeof(*rmpp_mad); - } else { - data = (void *) rmpp_mad + offset; - if (flags & IB_MGMT_RMPP_FLAG_LAST) - size = len; - else - size = sizeof(*rmpp_mad) - offset; - } - - memcpy(buf, data, size); - len -= size; - buf += size; - } -} -EXPORT_SYMBOL(ib_coalesce_recv_mad); - -static struct ib_mad_recv_wc * -continue_rmpp(struct ib_mad_agent_private *agent, - struct ib_mad_recv_wc *mad_recv_wc) -{ - struct mad_rmpp_recv *rmpp_recv; - struct ib_mad_recv_buf *prev_buf; - struct ib_mad_recv_wc *done_wc; - int seg_num; - unsigned long flags; - - rmpp_recv = acquire_rmpp_recv(agent, mad_recv_wc); - if (!rmpp_recv) - goto drop1; - - seg_num = get_seg_num(&mad_recv_wc->recv_buf); - - spin_lock_irqsave(&rmpp_recv->lock, flags); - if ((rmpp_recv->state == RMPP_STATE_TIMEOUT) || - (seg_num > rmpp_recv->newwin)) - goto drop3; - - if ((seg_num <= rmpp_recv->last_ack) || - (rmpp_recv->state == RMPP_STATE_COMPLETE)) { - spin_unlock_irqrestore(&rmpp_recv->lock, flags); - ack_recv(rmpp_recv, mad_recv_wc); - goto drop2; - } - - prev_buf = find_seg_location(&rmpp_recv->rmpp_wc->rmpp_list, seg_num); - if (!prev_buf) - goto drop3; - - done_wc = NULL; - list_add(&mad_recv_wc->recv_buf.list, &prev_buf->list); - if (rmpp_recv->cur_seg_buf == prev_buf) { - update_seg_num(rmpp_recv, &mad_recv_wc->recv_buf); - if (get_last_flag(rmpp_recv->cur_seg_buf)) { - rmpp_recv->state = RMPP_STATE_COMPLETE; - spin_unlock_irqrestore(&rmpp_recv->lock, flags); - done_wc = complete_rmpp(rmpp_recv); - goto out; - } else if (rmpp_recv->seg_num == rmpp_recv->newwin) { - rmpp_recv->newwin += window_size(agent); - spin_unlock_irqrestore(&rmpp_recv->lock, flags); - ack_recv(rmpp_recv, mad_recv_wc); - goto out; - } - } - spin_unlock_irqrestore(&rmpp_recv->lock, flags); -out: - deref_rmpp_recv(rmpp_recv); - return done_wc; - -drop3: spin_unlock_irqrestore(&rmpp_recv->lock, flags); -drop2: deref_rmpp_recv(rmpp_recv); -drop1: ib_free_recv_mad(mad_recv_wc); - return NULL; -} - -static struct ib_mad_recv_wc * -start_rmpp(struct ib_mad_agent_private *agent, - struct ib_mad_recv_wc *mad_recv_wc) -{ - struct mad_rmpp_recv *rmpp_recv; - unsigned long flags; - - rmpp_recv = create_rmpp_recv(agent, mad_recv_wc); - if (!rmpp_recv) { - ib_free_recv_mad(mad_recv_wc); - return NULL; - } - - spin_lock_irqsave(&agent->lock, flags); - if (insert_rmpp_recv(agent, rmpp_recv)) { - spin_unlock_irqrestore(&agent->lock, flags); - /* duplicate first MAD */ - destroy_rmpp_recv(rmpp_recv); - return continue_rmpp(agent, mad_recv_wc); - } - atomic_inc(&rmpp_recv->refcount); - - if (get_last_flag(&mad_recv_wc->recv_buf)) { - rmpp_recv->state = RMPP_STATE_COMPLETE; - spin_unlock_irqrestore(&agent->lock, flags); - complete_rmpp(rmpp_recv); - } else { - spin_unlock_irqrestore(&agent->lock, flags); - /* 40 seconds until we can find the packet lifetimes */ - queue_delayed_work(agent->qp_info->port_priv->wq, - &rmpp_recv->timeout_work, - msecs_to_jiffies(40000)); - rmpp_recv->newwin += window_size(agent); - ack_recv(rmpp_recv, mad_recv_wc); - mad_recv_wc = NULL; - } - deref_rmpp_recv(rmpp_recv); - return mad_recv_wc; -} - -static inline u64 get_seg_addr(struct ib_mad_send_wr_private *mad_send_wr) -{ - return mad_send_wr->sg_list[0].addr + mad_send_wr->data_offset + - (sizeof(struct ib_rmpp_mad) - mad_send_wr->data_offset) * - (mad_send_wr->seg_num - 1); -} - -static int send_next_seg(struct ib_mad_send_wr_private *mad_send_wr) -{ - struct ib_rmpp_mad *rmpp_mad; - int timeout; - - rmpp_mad = (struct ib_rmpp_mad *)mad_send_wr->send_wr.wr.ud.mad_hdr; - ib_set_rmpp_flags(&rmpp_mad->rmpp_hdr, IB_MGMT_RMPP_FLAG_ACTIVE); - rmpp_mad->rmpp_hdr.seg_num = cpu_to_be32(mad_send_wr->seg_num); - - if (mad_send_wr->seg_num == 1) { - rmpp_mad->rmpp_hdr.rmpp_rtime_flags |= IB_MGMT_RMPP_FLAG_FIRST; - rmpp_mad->rmpp_hdr.paylen_newwin = - cpu_to_be32(mad_send_wr->total_seg * - (sizeof(struct ib_rmpp_mad) - - offsetof(struct ib_rmpp_mad, data))); - mad_send_wr->sg_list[0].length = sizeof(struct ib_rmpp_mad); - } else { - mad_send_wr->send_wr.num_sge = 2; - mad_send_wr->sg_list[0].length = mad_send_wr->data_offset; - mad_send_wr->sg_list[1].addr = get_seg_addr(mad_send_wr); - mad_send_wr->sg_list[1].length = sizeof(struct ib_rmpp_mad) - - mad_send_wr->data_offset; - mad_send_wr->sg_list[1].lkey = mad_send_wr->sg_list[0].lkey; - } - - if (mad_send_wr->seg_num == mad_send_wr->total_seg) { - rmpp_mad->rmpp_hdr.rmpp_rtime_flags |= IB_MGMT_RMPP_FLAG_LAST; - rmpp_mad->rmpp_hdr.paylen_newwin = - cpu_to_be32(sizeof(struct ib_rmpp_mad) - - offsetof(struct ib_rmpp_mad, data) - - mad_send_wr->pad); - } - - /* 2 seconds for an ACK until we can find the packet lifetime */ - timeout = mad_send_wr->send_wr.wr.ud.timeout_ms; - if (!timeout || timeout > 2000) - mad_send_wr->timeout = msecs_to_jiffies(2000); - mad_send_wr->seg_num++; - return ib_send_mad(mad_send_wr); -} - -static void process_rmpp_ack(struct ib_mad_agent_private *agent, - struct ib_mad_recv_wc *mad_recv_wc) -{ - struct ib_mad_send_wr_private *mad_send_wr; - struct ib_rmpp_mad *rmpp_mad; - unsigned long flags; - int seg_num, newwin, ret; - - rmpp_mad = (struct ib_rmpp_mad *)mad_recv_wc->recv_buf.mad; - if (rmpp_mad->rmpp_hdr.rmpp_status) - return; - - seg_num = be32_to_cpu(rmpp_mad->rmpp_hdr.seg_num); - newwin = be32_to_cpu(rmpp_mad->rmpp_hdr.paylen_newwin); - - spin_lock_irqsave(&agent->lock, flags); - mad_send_wr = ib_find_send_mad(agent, rmpp_mad->mad_hdr.tid); - if (!mad_send_wr) - goto out; /* Unmatched ACK */ - - if ((mad_send_wr->last_ack == mad_send_wr->total_seg) || - (!mad_send_wr->timeout) || (mad_send_wr->status != IB_WC_SUCCESS)) - goto out; /* Send is already done */ - - if (seg_num > mad_send_wr->total_seg) - goto out; /* Bad ACK */ - - if (newwin < mad_send_wr->newwin || seg_num < mad_send_wr->last_ack) - goto out; /* Old ACK */ - - if (seg_num > mad_send_wr->last_ack) { - mad_send_wr->last_ack = seg_num; - mad_send_wr->retries = mad_send_wr->send_wr.wr.ud.retries; - } - mad_send_wr->newwin = newwin; - if (mad_send_wr->last_ack == mad_send_wr->total_seg) { - /* If no response is expected, the ACK completes the send */ - if (!mad_send_wr->send_wr.wr.ud.timeout_ms) { - struct ib_mad_send_wc wc; - - ib_mark_mad_done(mad_send_wr); - spin_unlock_irqrestore(&agent->lock, flags); - - wc.status = IB_WC_SUCCESS; - wc.vendor_err = 0; - wc.wr_id = mad_send_wr->wr_id; - ib_mad_complete_send_wr(mad_send_wr, &wc); - return; - } - if (mad_send_wr->refcount == 1) - ib_reset_mad_timeout(mad_send_wr, mad_send_wr-> - send_wr.wr.ud.timeout_ms); - } else if (mad_send_wr->refcount == 1 && - mad_send_wr->seg_num < mad_send_wr->newwin && - mad_send_wr->seg_num <= mad_send_wr->total_seg) { - /* Send failure will just result in a timeout/retry */ - ret = send_next_seg(mad_send_wr); - if (ret) - goto out; - - mad_send_wr->refcount++; - list_del(&mad_send_wr->agent_list); - list_add_tail(&mad_send_wr->agent_list, - &mad_send_wr->mad_agent_priv->send_list); - } -out: - spin_unlock_irqrestore(&agent->lock, flags); -} - -struct ib_mad_recv_wc * -ib_process_rmpp_recv_wc(struct ib_mad_agent_private *agent, - struct ib_mad_recv_wc *mad_recv_wc) -{ - struct ib_rmpp_mad *rmpp_mad; - - rmpp_mad = (struct ib_rmpp_mad *)mad_recv_wc->recv_buf.mad; - if (!(rmpp_mad->rmpp_hdr.rmpp_rtime_flags & IB_MGMT_RMPP_FLAG_ACTIVE)) - return mad_recv_wc; - - if (rmpp_mad->rmpp_hdr.rmpp_version != IB_MGMT_RMPP_VERSION) - goto out; - - switch (rmpp_mad->rmpp_hdr.rmpp_type) { - case IB_MGMT_RMPP_TYPE_DATA: - if (rmpp_mad->rmpp_hdr.seg_num == __constant_htonl(1)) - return start_rmpp(agent, mad_recv_wc); - else - return continue_rmpp(agent, mad_recv_wc); - case IB_MGMT_RMPP_TYPE_ACK: - process_rmpp_ack(agent, mad_recv_wc); - break; - case IB_MGMT_RMPP_TYPE_STOP: - case IB_MGMT_RMPP_TYPE_ABORT: - /* TODO: process_rmpp_nack(agent, mad_recv_wc); */ - break; - default: - break; - } -out: - ib_free_recv_mad(mad_recv_wc); - return NULL; -} - -int ib_send_rmpp_mad(struct ib_mad_send_wr_private *mad_send_wr) -{ - struct ib_rmpp_mad *rmpp_mad; - int i, total_len, ret; - - rmpp_mad = (struct ib_rmpp_mad *)mad_send_wr->send_wr.wr.ud.mad_hdr; - if (!(ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) & - IB_MGMT_RMPP_FLAG_ACTIVE)) - return IB_RMPP_RESULT_UNHANDLED; - - if (rmpp_mad->rmpp_hdr.rmpp_type != IB_MGMT_RMPP_TYPE_DATA) - return IB_RMPP_RESULT_INTERNAL; - - if (mad_send_wr->send_wr.num_sge > 1) - return -EINVAL; /* TODO: support num_sge > 1 */ - - mad_send_wr->seg_num = 1; - mad_send_wr->newwin = 1; - mad_send_wr->data_offset = data_offset(rmpp_mad->mad_hdr.mgmt_class); - - total_len = 0; - for (i = 0; i < mad_send_wr->send_wr.num_sge; i++) - total_len += mad_send_wr->send_wr.sg_list[i].length; - - mad_send_wr->total_seg = (total_len - mad_send_wr->data_offset) / - (sizeof(struct ib_rmpp_mad) - mad_send_wr->data_offset); - mad_send_wr->pad = total_len - offsetof(struct ib_rmpp_mad, data) - - be32_to_cpu(rmpp_mad->rmpp_hdr.paylen_newwin); - - /* We need to wait for the final ACK even if there isn't a response */ - mad_send_wr->refcount += (mad_send_wr->timeout == 0); - ret = send_next_seg(mad_send_wr); - if (!ret) - return IB_RMPP_RESULT_CONSUMED; - return ret; -} - -int ib_process_rmpp_send_wc(struct ib_mad_send_wr_private *mad_send_wr, - struct ib_mad_send_wc *mad_send_wc) -{ - struct ib_rmpp_mad *rmpp_mad; - struct ib_mad_send_buf *msg; - int ret; - - rmpp_mad = (struct ib_rmpp_mad *)mad_send_wr->send_wr.wr.ud.mad_hdr; - if (!(ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) & - IB_MGMT_RMPP_FLAG_ACTIVE)) - return IB_RMPP_RESULT_UNHANDLED; /* RMPP not active */ - - if (rmpp_mad->rmpp_hdr.rmpp_type != IB_MGMT_RMPP_TYPE_DATA) { - msg = (struct ib_mad_send_buf *) (unsigned long) - mad_send_wc->wr_id; - ib_free_send_mad(msg); - return IB_RMPP_RESULT_INTERNAL; /* ACK, STOP, or ABORT */ - } - - if (mad_send_wc->status != IB_WC_SUCCESS || - mad_send_wr->status != IB_WC_SUCCESS) - return IB_RMPP_RESULT_PROCESSED; /* Canceled or send error */ - - if (!mad_send_wr->timeout) - return IB_RMPP_RESULT_PROCESSED; /* Response received */ - - if (mad_send_wr->last_ack == mad_send_wr->total_seg) { - mad_send_wr->timeout = - msecs_to_jiffies(mad_send_wr->send_wr.wr.ud.timeout_ms); - return IB_RMPP_RESULT_PROCESSED; /* Send done */ - } - - if (mad_send_wr->seg_num > mad_send_wr->newwin || - mad_send_wr->seg_num > mad_send_wr->total_seg) - return IB_RMPP_RESULT_PROCESSED; /* Wait for ACK */ - - ret = send_next_seg(mad_send_wr); - if (ret) { - mad_send_wc->status = IB_WC_GENERAL_ERR; - return IB_RMPP_RESULT_PROCESSED; - } - return IB_RMPP_RESULT_CONSUMED; -} - -int ib_retry_rmpp(struct ib_mad_send_wr_private *mad_send_wr) -{ - struct ib_rmpp_mad *rmpp_mad; - int ret; - - rmpp_mad = (struct ib_rmpp_mad *)mad_send_wr->send_wr.wr.ud.mad_hdr; - if (!(ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) & - IB_MGMT_RMPP_FLAG_ACTIVE)) - return IB_RMPP_RESULT_UNHANDLED; /* RMPP not active */ - - if (mad_send_wr->last_ack == mad_send_wr->total_seg) - return IB_RMPP_RESULT_PROCESSED; - - mad_send_wr->seg_num = mad_send_wr->last_ack + 1; - ret = send_next_seg(mad_send_wr); - if (ret) - return IB_RMPP_RESULT_PROCESSED; - - return IB_RMPP_RESULT_CONSUMED; -} diff --git a/trunk/drivers/infiniband/core/mad_rmpp.h b/trunk/drivers/infiniband/core/mad_rmpp.h deleted file mode 100644 index c4924dfb8e75..000000000000 --- a/trunk/drivers/infiniband/core/mad_rmpp.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2005 Intel Inc. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * $Id: mad_rmpp.h 1921 2005-02-25 22:58:44Z sean.hefty $ - */ - -#ifndef __MAD_RMPP_H__ -#define __MAD_RMPP_H__ - -enum { - IB_RMPP_RESULT_PROCESSED, - IB_RMPP_RESULT_CONSUMED, - IB_RMPP_RESULT_INTERNAL, - IB_RMPP_RESULT_UNHANDLED -}; - -int ib_send_rmpp_mad(struct ib_mad_send_wr_private *mad_send_wr); - -struct ib_mad_recv_wc * -ib_process_rmpp_recv_wc(struct ib_mad_agent_private *agent, - struct ib_mad_recv_wc *mad_recv_wc); - -int ib_process_rmpp_send_wc(struct ib_mad_send_wr_private *mad_send_wr, - struct ib_mad_send_wc *mad_send_wc); - -void ib_cancel_rmpp_recvs(struct ib_mad_agent_private *agent); - -int ib_retry_rmpp(struct ib_mad_send_wr_private *mad_send_wr); - -#endif /* __MAD_RMPP_H__ */ diff --git a/trunk/drivers/infiniband/core/sa_query.c b/trunk/drivers/infiniband/core/sa_query.c index 795184931c83..5a08e81fa827 100644 --- a/trunk/drivers/infiniband/core/sa_query.c +++ b/trunk/drivers/infiniband/core/sa_query.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2004 Topspin Communications. All rights reserved. - * Copyright (c) 2005 Voltaire, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU @@ -30,7 +29,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: sa_query.c 2811 2005-07-06 18:11:43Z halr $ + * $Id: sa_query.c 1389 2004-12-27 22:56:47Z roland $ */ #include @@ -51,6 +50,26 @@ MODULE_AUTHOR("Roland Dreier"); MODULE_DESCRIPTION("InfiniBand subnet administration query support"); MODULE_LICENSE("Dual BSD/GPL"); +/* + * These two structures must be packed because they have 64-bit fields + * that are only 32-bit aligned. 64-bit architectures will lay them + * out wrong otherwise. (And unfortunately they are sent on the wire + * so we can't change the layout) + */ +struct ib_sa_hdr { + u64 sm_key; + u16 attr_offset; + u16 reserved; + ib_sa_comp_mask comp_mask; +} __attribute__ ((packed)); + +struct ib_sa_mad { + struct ib_mad_hdr mad_hdr; + struct ib_rmpp_hdr rmpp_hdr; + struct ib_sa_hdr sa_hdr; + u8 data[200]; +} __attribute__ ((packed)); + struct ib_sa_sm_ah { struct ib_ah *ah; struct kref ref; @@ -58,6 +77,7 @@ struct ib_sa_sm_ah { struct ib_sa_port { struct ib_mad_agent *agent; + struct ib_mr *mr; struct ib_sa_sm_ah *sm_ah; struct work_struct update_task; spinlock_t ah_lock; @@ -80,12 +100,6 @@ struct ib_sa_query { int id; }; -struct ib_sa_service_query { - void (*callback)(int, struct ib_sa_service_rec *, void *); - void *context; - struct ib_sa_query sa_query; -}; - struct ib_sa_path_query { void (*callback)(int, struct ib_sa_path_rec *, void *); void *context; @@ -327,54 +341,6 @@ static const struct ib_field mcmember_rec_table[] = { .size_bits = 23 }, }; -#define SERVICE_REC_FIELD(field) \ - .struct_offset_bytes = offsetof(struct ib_sa_service_rec, field), \ - .struct_size_bytes = sizeof ((struct ib_sa_service_rec *) 0)->field, \ - .field_name = "sa_service_rec:" #field - -static const struct ib_field service_rec_table[] = { - { SERVICE_REC_FIELD(id), - .offset_words = 0, - .offset_bits = 0, - .size_bits = 64 }, - { SERVICE_REC_FIELD(gid), - .offset_words = 2, - .offset_bits = 0, - .size_bits = 128 }, - { SERVICE_REC_FIELD(pkey), - .offset_words = 6, - .offset_bits = 0, - .size_bits = 16 }, - { SERVICE_REC_FIELD(lease), - .offset_words = 7, - .offset_bits = 0, - .size_bits = 32 }, - { SERVICE_REC_FIELD(key), - .offset_words = 8, - .offset_bits = 0, - .size_bits = 128 }, - { SERVICE_REC_FIELD(name), - .offset_words = 12, - .offset_bits = 0, - .size_bits = 64*8 }, - { SERVICE_REC_FIELD(data8), - .offset_words = 28, - .offset_bits = 0, - .size_bits = 16*8 }, - { SERVICE_REC_FIELD(data16), - .offset_words = 32, - .offset_bits = 0, - .size_bits = 8*16 }, - { SERVICE_REC_FIELD(data32), - .offset_words = 36, - .offset_bits = 0, - .size_bits = 4*32 }, - { SERVICE_REC_FIELD(data64), - .offset_words = 40, - .offset_bits = 0, - .size_bits = 2*64 }, -}; - static void free_sm_ah(struct kref *kref) { struct ib_sa_sm_ah *sm_ah = container_of(kref, struct ib_sa_sm_ah, ref); @@ -497,7 +463,7 @@ static int send_mad(struct ib_sa_query *query, int timeout_ms) .mad_hdr = &query->mad->mad_hdr, .remote_qpn = 1, .remote_qkey = IB_QP1_QKEY, - .timeout_ms = timeout_ms, + .timeout_ms = timeout_ms } } }; @@ -526,7 +492,7 @@ static int send_mad(struct ib_sa_query *query, int timeout_ms) sizeof (struct ib_sa_mad), DMA_TO_DEVICE); gather_list.length = sizeof (struct ib_sa_mad); - gather_list.lkey = port->agent->mr->lkey; + gather_list.lkey = port->mr->lkey; pci_unmap_addr_set(query, mapping, gather_list.addr); ret = ib_post_send_mad(port->agent, &wr, &bad_wr); @@ -600,7 +566,7 @@ static void ib_sa_path_rec_release(struct ib_sa_query *sa_query) int ib_sa_path_rec_get(struct ib_device *device, u8 port_num, struct ib_sa_path_rec *rec, ib_sa_comp_mask comp_mask, - int timeout_ms, unsigned int __nocast gfp_mask, + int timeout_ms, int gfp_mask, void (*callback)(int status, struct ib_sa_path_rec *resp, void *context), @@ -650,114 +616,6 @@ int ib_sa_path_rec_get(struct ib_device *device, u8 port_num, } EXPORT_SYMBOL(ib_sa_path_rec_get); -static void ib_sa_service_rec_callback(struct ib_sa_query *sa_query, - int status, - struct ib_sa_mad *mad) -{ - struct ib_sa_service_query *query = - container_of(sa_query, struct ib_sa_service_query, sa_query); - - if (mad) { - struct ib_sa_service_rec rec; - - ib_unpack(service_rec_table, ARRAY_SIZE(service_rec_table), - mad->data, &rec); - query->callback(status, &rec, query->context); - } else - query->callback(status, NULL, query->context); -} - -static void ib_sa_service_rec_release(struct ib_sa_query *sa_query) -{ - kfree(sa_query->mad); - kfree(container_of(sa_query, struct ib_sa_service_query, sa_query)); -} - -/** - * ib_sa_service_rec_query - Start Service Record operation - * @device:device to send request on - * @port_num: port number to send request on - * @method:SA method - should be get, set, or delete - * @rec:Service Record to send in request - * @comp_mask:component mask to send in request - * @timeout_ms:time to wait for response - * @gfp_mask:GFP mask to use for internal allocations - * @callback:function called when request completes, times out or is - * canceled - * @context:opaque user context passed to callback - * @sa_query:request context, used to cancel request - * - * Send a Service Record set/get/delete to the SA to register, - * unregister or query a service record. - * The callback function will be called when the request completes (or - * fails); status is 0 for a successful response, -EINTR if the query - * is canceled, -ETIMEDOUT is the query timed out, or -EIO if an error - * occurred sending the query. The resp parameter of the callback is - * only valid if status is 0. - * - * If the return value of ib_sa_service_rec_query() is negative, it is an - * error code. Otherwise it is a request ID that can be used to cancel - * the query. - */ -int ib_sa_service_rec_query(struct ib_device *device, u8 port_num, u8 method, - struct ib_sa_service_rec *rec, - ib_sa_comp_mask comp_mask, - int timeout_ms, unsigned int __nocast gfp_mask, - void (*callback)(int status, - struct ib_sa_service_rec *resp, - void *context), - void *context, - struct ib_sa_query **sa_query) -{ - struct ib_sa_service_query *query; - struct ib_sa_device *sa_dev = ib_get_client_data(device, &sa_client); - struct ib_sa_port *port = &sa_dev->port[port_num - sa_dev->start_port]; - struct ib_mad_agent *agent = port->agent; - int ret; - - if (method != IB_MGMT_METHOD_GET && - method != IB_MGMT_METHOD_SET && - method != IB_SA_METHOD_DELETE) - return -EINVAL; - - query = kmalloc(sizeof *query, gfp_mask); - if (!query) - return -ENOMEM; - query->sa_query.mad = kmalloc(sizeof *query->sa_query.mad, gfp_mask); - if (!query->sa_query.mad) { - kfree(query); - return -ENOMEM; - } - - query->callback = callback; - query->context = context; - - init_mad(query->sa_query.mad, agent); - - query->sa_query.callback = callback ? ib_sa_service_rec_callback : NULL; - query->sa_query.release = ib_sa_service_rec_release; - query->sa_query.port = port; - query->sa_query.mad->mad_hdr.method = method; - query->sa_query.mad->mad_hdr.attr_id = - cpu_to_be16(IB_SA_ATTR_SERVICE_REC); - query->sa_query.mad->sa_hdr.comp_mask = comp_mask; - - ib_pack(service_rec_table, ARRAY_SIZE(service_rec_table), - rec, query->sa_query.mad->data); - - *sa_query = &query->sa_query; - - ret = send_mad(&query->sa_query, timeout_ms); - if (ret < 0) { - *sa_query = NULL; - kfree(query->sa_query.mad); - kfree(query); - } - - return ret; -} -EXPORT_SYMBOL(ib_sa_service_rec_query); - static void ib_sa_mcmember_rec_callback(struct ib_sa_query *sa_query, int status, struct ib_sa_mad *mad) @@ -785,7 +643,7 @@ int ib_sa_mcmember_rec_query(struct ib_device *device, u8 port_num, u8 method, struct ib_sa_mcmember_rec *rec, ib_sa_comp_mask comp_mask, - int timeout_ms, unsigned int __nocast gfp_mask, + int timeout_ms, int gfp_mask, void (*callback)(int status, struct ib_sa_mcmember_rec *resp, void *context), @@ -922,6 +780,7 @@ static void ib_sa_add_one(struct ib_device *device) sa_dev->end_port = e; for (i = 0; i <= e - s; ++i) { + sa_dev->port[i].mr = NULL; sa_dev->port[i].sm_ah = NULL; sa_dev->port[i].port_num = i + s; spin_lock_init(&sa_dev->port[i].ah_lock); @@ -933,6 +792,13 @@ static void ib_sa_add_one(struct ib_device *device) if (IS_ERR(sa_dev->port[i].agent)) goto err; + sa_dev->port[i].mr = ib_get_dma_mr(sa_dev->port[i].agent->qp->pd, + IB_ACCESS_LOCAL_WRITE); + if (IS_ERR(sa_dev->port[i].mr)) { + ib_unregister_mad_agent(sa_dev->port[i].agent); + goto err; + } + INIT_WORK(&sa_dev->port[i].update_task, update_sm_ah, &sa_dev->port[i]); } @@ -956,8 +822,10 @@ static void ib_sa_add_one(struct ib_device *device) return; err: - while (--i >= 0) + while (--i >= 0) { + ib_dereg_mr(sa_dev->port[i].mr); ib_unregister_mad_agent(sa_dev->port[i].agent); + } kfree(sa_dev); diff --git a/trunk/drivers/infiniband/core/ucm.c b/trunk/drivers/infiniband/core/ucm.c deleted file mode 100644 index 546ec61c407f..000000000000 --- a/trunk/drivers/infiniband/core/ucm.c +++ /dev/null @@ -1,1393 +0,0 @@ -/* - * Copyright (c) 2005 Topspin Communications. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * $Id: ucm.c 2594 2005-06-13 19:46:02Z libor $ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "ucm.h" - -MODULE_AUTHOR("Libor Michalek"); -MODULE_DESCRIPTION("InfiniBand userspace Connection Manager access"); -MODULE_LICENSE("Dual BSD/GPL"); - -enum { - IB_UCM_MAJOR = 231, - IB_UCM_MINOR = 255 -}; - -#define IB_UCM_DEV MKDEV(IB_UCM_MAJOR, IB_UCM_MINOR) - -static struct semaphore ctx_id_mutex; -static struct idr ctx_id_table; -static int ctx_id_rover = 0; - -static struct ib_ucm_context *ib_ucm_ctx_get(int id) -{ - struct ib_ucm_context *ctx; - - down(&ctx_id_mutex); - ctx = idr_find(&ctx_id_table, id); - if (ctx) - ctx->ref++; - up(&ctx_id_mutex); - - return ctx; -} - -static void ib_ucm_ctx_put(struct ib_ucm_context *ctx) -{ - struct ib_ucm_event *uevent; - - down(&ctx_id_mutex); - - ctx->ref--; - if (!ctx->ref) - idr_remove(&ctx_id_table, ctx->id); - - up(&ctx_id_mutex); - - if (ctx->ref) - return; - - down(&ctx->file->mutex); - - list_del(&ctx->file_list); - while (!list_empty(&ctx->events)) { - - uevent = list_entry(ctx->events.next, - struct ib_ucm_event, ctx_list); - list_del(&uevent->file_list); - list_del(&uevent->ctx_list); - - /* clear incoming connections. */ - if (uevent->cm_id) - ib_destroy_cm_id(uevent->cm_id); - - kfree(uevent); - } - - up(&ctx->file->mutex); - - printk(KERN_ERR "UCM: Destroyed CM ID <%d>\n", ctx->id); - - ib_destroy_cm_id(ctx->cm_id); - kfree(ctx); -} - -static struct ib_ucm_context *ib_ucm_ctx_alloc(struct ib_ucm_file *file) -{ - struct ib_ucm_context *ctx; - int result; - - ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return NULL; - - ctx->ref = 1; /* user reference */ - ctx->file = file; - - INIT_LIST_HEAD(&ctx->events); - init_MUTEX(&ctx->mutex); - - list_add_tail(&ctx->file_list, &file->ctxs); - - ctx_id_rover = (ctx_id_rover + 1) & INT_MAX; -retry: - result = idr_pre_get(&ctx_id_table, GFP_KERNEL); - if (!result) - goto error; - - down(&ctx_id_mutex); - result = idr_get_new_above(&ctx_id_table, ctx, ctx_id_rover, &ctx->id); - up(&ctx_id_mutex); - - if (result == -EAGAIN) - goto retry; - if (result) - goto error; - - printk(KERN_ERR "UCM: Allocated CM ID <%d>\n", ctx->id); - - return ctx; -error: - list_del(&ctx->file_list); - kfree(ctx); - - return NULL; -} -/* - * Event portion of the API, handle CM events - * and allow event polling. - */ -static void ib_ucm_event_path_get(struct ib_ucm_path_rec *upath, - struct ib_sa_path_rec *kpath) -{ - if (!kpath || !upath) - return; - - memcpy(upath->dgid, kpath->dgid.raw, sizeof(union ib_gid)); - memcpy(upath->sgid, kpath->sgid.raw, sizeof(union ib_gid)); - - upath->dlid = kpath->dlid; - upath->slid = kpath->slid; - upath->raw_traffic = kpath->raw_traffic; - upath->flow_label = kpath->flow_label; - upath->hop_limit = kpath->hop_limit; - upath->traffic_class = kpath->traffic_class; - upath->reversible = kpath->reversible; - upath->numb_path = kpath->numb_path; - upath->pkey = kpath->pkey; - upath->sl = kpath->sl; - upath->mtu_selector = kpath->mtu_selector; - upath->mtu = kpath->mtu; - upath->rate_selector = kpath->rate_selector; - upath->rate = kpath->rate; - upath->packet_life_time = kpath->packet_life_time; - upath->preference = kpath->preference; - - upath->packet_life_time_selector = - kpath->packet_life_time_selector; -} - -static void ib_ucm_event_req_get(struct ib_ucm_req_event_resp *ureq, - struct ib_cm_req_event_param *kreq) -{ - ureq->listen_id = (long)kreq->listen_id->context; - - ureq->remote_ca_guid = kreq->remote_ca_guid; - ureq->remote_qkey = kreq->remote_qkey; - ureq->remote_qpn = kreq->remote_qpn; - ureq->qp_type = kreq->qp_type; - ureq->starting_psn = kreq->starting_psn; - ureq->responder_resources = kreq->responder_resources; - ureq->initiator_depth = kreq->initiator_depth; - ureq->local_cm_response_timeout = kreq->local_cm_response_timeout; - ureq->flow_control = kreq->flow_control; - ureq->remote_cm_response_timeout = kreq->remote_cm_response_timeout; - ureq->retry_count = kreq->retry_count; - ureq->rnr_retry_count = kreq->rnr_retry_count; - ureq->srq = kreq->srq; - - ib_ucm_event_path_get(&ureq->primary_path, kreq->primary_path); - ib_ucm_event_path_get(&ureq->alternate_path, kreq->alternate_path); -} - -static void ib_ucm_event_rep_get(struct ib_ucm_rep_event_resp *urep, - struct ib_cm_rep_event_param *krep) -{ - urep->remote_ca_guid = krep->remote_ca_guid; - urep->remote_qkey = krep->remote_qkey; - urep->remote_qpn = krep->remote_qpn; - urep->starting_psn = krep->starting_psn; - urep->responder_resources = krep->responder_resources; - urep->initiator_depth = krep->initiator_depth; - urep->target_ack_delay = krep->target_ack_delay; - urep->failover_accepted = krep->failover_accepted; - urep->flow_control = krep->flow_control; - urep->rnr_retry_count = krep->rnr_retry_count; - urep->srq = krep->srq; -} - -static void ib_ucm_event_rej_get(struct ib_ucm_rej_event_resp *urej, - struct ib_cm_rej_event_param *krej) -{ - urej->reason = krej->reason; -} - -static void ib_ucm_event_mra_get(struct ib_ucm_mra_event_resp *umra, - struct ib_cm_mra_event_param *kmra) -{ - umra->timeout = kmra->service_timeout; -} - -static void ib_ucm_event_lap_get(struct ib_ucm_lap_event_resp *ulap, - struct ib_cm_lap_event_param *klap) -{ - ib_ucm_event_path_get(&ulap->path, klap->alternate_path); -} - -static void ib_ucm_event_apr_get(struct ib_ucm_apr_event_resp *uapr, - struct ib_cm_apr_event_param *kapr) -{ - uapr->status = kapr->ap_status; -} - -static void ib_ucm_event_sidr_req_get(struct ib_ucm_sidr_req_event_resp *ureq, - struct ib_cm_sidr_req_event_param *kreq) -{ - ureq->listen_id = (long)kreq->listen_id->context; - ureq->pkey = kreq->pkey; -} - -static void ib_ucm_event_sidr_rep_get(struct ib_ucm_sidr_rep_event_resp *urep, - struct ib_cm_sidr_rep_event_param *krep) -{ - urep->status = krep->status; - urep->qkey = krep->qkey; - urep->qpn = krep->qpn; -}; - -static int ib_ucm_event_process(struct ib_cm_event *evt, - struct ib_ucm_event *uvt) -{ - void *info = NULL; - int result; - - switch (evt->event) { - case IB_CM_REQ_RECEIVED: - ib_ucm_event_req_get(&uvt->resp.u.req_resp, - &evt->param.req_rcvd); - uvt->data_len = IB_CM_REQ_PRIVATE_DATA_SIZE; - uvt->resp.present |= (evt->param.req_rcvd.primary_path ? - IB_UCM_PRES_PRIMARY : 0); - uvt->resp.present |= (evt->param.req_rcvd.alternate_path ? - IB_UCM_PRES_ALTERNATE : 0); - break; - case IB_CM_REP_RECEIVED: - ib_ucm_event_rep_get(&uvt->resp.u.rep_resp, - &evt->param.rep_rcvd); - uvt->data_len = IB_CM_REP_PRIVATE_DATA_SIZE; - - break; - case IB_CM_RTU_RECEIVED: - uvt->data_len = IB_CM_RTU_PRIVATE_DATA_SIZE; - uvt->resp.u.send_status = evt->param.send_status; - - break; - case IB_CM_DREQ_RECEIVED: - uvt->data_len = IB_CM_DREQ_PRIVATE_DATA_SIZE; - uvt->resp.u.send_status = evt->param.send_status; - - break; - case IB_CM_DREP_RECEIVED: - uvt->data_len = IB_CM_DREP_PRIVATE_DATA_SIZE; - uvt->resp.u.send_status = evt->param.send_status; - - break; - case IB_CM_MRA_RECEIVED: - ib_ucm_event_mra_get(&uvt->resp.u.mra_resp, - &evt->param.mra_rcvd); - uvt->data_len = IB_CM_MRA_PRIVATE_DATA_SIZE; - - break; - case IB_CM_REJ_RECEIVED: - ib_ucm_event_rej_get(&uvt->resp.u.rej_resp, - &evt->param.rej_rcvd); - uvt->data_len = IB_CM_REJ_PRIVATE_DATA_SIZE; - uvt->info_len = evt->param.rej_rcvd.ari_length; - info = evt->param.rej_rcvd.ari; - - break; - case IB_CM_LAP_RECEIVED: - ib_ucm_event_lap_get(&uvt->resp.u.lap_resp, - &evt->param.lap_rcvd); - uvt->data_len = IB_CM_LAP_PRIVATE_DATA_SIZE; - uvt->resp.present |= (evt->param.lap_rcvd.alternate_path ? - IB_UCM_PRES_ALTERNATE : 0); - break; - case IB_CM_APR_RECEIVED: - ib_ucm_event_apr_get(&uvt->resp.u.apr_resp, - &evt->param.apr_rcvd); - uvt->data_len = IB_CM_APR_PRIVATE_DATA_SIZE; - uvt->info_len = evt->param.apr_rcvd.info_len; - info = evt->param.apr_rcvd.apr_info; - - break; - case IB_CM_SIDR_REQ_RECEIVED: - ib_ucm_event_sidr_req_get(&uvt->resp.u.sidr_req_resp, - &evt->param.sidr_req_rcvd); - uvt->data_len = IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE; - - break; - case IB_CM_SIDR_REP_RECEIVED: - ib_ucm_event_sidr_rep_get(&uvt->resp.u.sidr_rep_resp, - &evt->param.sidr_rep_rcvd); - uvt->data_len = IB_CM_SIDR_REP_PRIVATE_DATA_SIZE; - uvt->info_len = evt->param.sidr_rep_rcvd.info_len; - info = evt->param.sidr_rep_rcvd.info; - - break; - default: - uvt->resp.u.send_status = evt->param.send_status; - - break; - } - - if (uvt->data_len && evt->private_data) { - - uvt->data = kmalloc(uvt->data_len, GFP_KERNEL); - if (!uvt->data) { - result = -ENOMEM; - goto error; - } - - memcpy(uvt->data, evt->private_data, uvt->data_len); - uvt->resp.present |= IB_UCM_PRES_DATA; - } - - if (uvt->info_len && info) { - - uvt->info = kmalloc(uvt->info_len, GFP_KERNEL); - if (!uvt->info) { - result = -ENOMEM; - goto error; - } - - memcpy(uvt->info, info, uvt->info_len); - uvt->resp.present |= IB_UCM_PRES_INFO; - } - - return 0; -error: - if (uvt->info) - kfree(uvt->info); - if (uvt->data) - kfree(uvt->data); - return result; -} - -static int ib_ucm_event_handler(struct ib_cm_id *cm_id, - struct ib_cm_event *event) -{ - struct ib_ucm_event *uevent; - struct ib_ucm_context *ctx; - int result = 0; - int id; - /* - * lookup correct context based on event type. - */ - switch (event->event) { - case IB_CM_REQ_RECEIVED: - id = (long)event->param.req_rcvd.listen_id->context; - break; - case IB_CM_SIDR_REQ_RECEIVED: - id = (long)event->param.sidr_req_rcvd.listen_id->context; - break; - default: - id = (long)cm_id->context; - break; - } - - printk(KERN_ERR "UCM: Event. CM ID <%d> event <%d>\n", - id, event->event); - - ctx = ib_ucm_ctx_get(id); - if (!ctx) - return -ENOENT; - - if (event->event == IB_CM_REQ_RECEIVED || - event->event == IB_CM_SIDR_REQ_RECEIVED) - id = IB_UCM_CM_ID_INVALID; - - uevent = kmalloc(sizeof(*uevent), GFP_KERNEL); - if (!uevent) { - result = -ENOMEM; - goto done; - } - - memset(uevent, 0, sizeof(*uevent)); - - uevent->resp.id = id; - uevent->resp.event = event->event; - - result = ib_ucm_event_process(event, uevent); - if (result) - goto done; - - uevent->ctx = ctx; - uevent->cm_id = ((event->event == IB_CM_REQ_RECEIVED || - event->event == IB_CM_SIDR_REQ_RECEIVED ) ? - cm_id : NULL); - - down(&ctx->file->mutex); - - list_add_tail(&uevent->file_list, &ctx->file->events); - list_add_tail(&uevent->ctx_list, &ctx->events); - - wake_up_interruptible(&ctx->file->poll_wait); - - up(&ctx->file->mutex); -done: - ctx->error = result; - ib_ucm_ctx_put(ctx); /* func reference */ - return result; -} - -static ssize_t ib_ucm_event(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_ucm_context *ctx; - struct ib_ucm_event_get cmd; - struct ib_ucm_event *uevent = NULL; - int result = 0; - DEFINE_WAIT(wait); - - if (out_len < sizeof(struct ib_ucm_event_resp)) - return -ENOSPC; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - /* - * wait - */ - down(&file->mutex); - - while (list_empty(&file->events)) { - - if (file->filp->f_flags & O_NONBLOCK) { - result = -EAGAIN; - break; - } - - if (signal_pending(current)) { - result = -ERESTARTSYS; - break; - } - - prepare_to_wait(&file->poll_wait, &wait, TASK_INTERRUPTIBLE); - - up(&file->mutex); - schedule(); - down(&file->mutex); - - finish_wait(&file->poll_wait, &wait); - } - - if (result) - goto done; - - uevent = list_entry(file->events.next, struct ib_ucm_event, file_list); - - if (!uevent->cm_id) - goto user; - - ctx = ib_ucm_ctx_alloc(file); - if (!ctx) { - result = -ENOMEM; - goto done; - } - - ctx->cm_id = uevent->cm_id; - ctx->cm_id->cm_handler = ib_ucm_event_handler; - ctx->cm_id->context = (void *)(unsigned long)ctx->id; - - uevent->resp.id = ctx->id; - -user: - if (copy_to_user((void __user *)(unsigned long)cmd.response, - &uevent->resp, sizeof(uevent->resp))) { - result = -EFAULT; - goto done; - } - - if (uevent->data) { - - if (cmd.data_len < uevent->data_len) { - result = -ENOMEM; - goto done; - } - - if (copy_to_user((void __user *)(unsigned long)cmd.data, - uevent->data, uevent->data_len)) { - result = -EFAULT; - goto done; - } - } - - if (uevent->info) { - - if (cmd.info_len < uevent->info_len) { - result = -ENOMEM; - goto done; - } - - if (copy_to_user((void __user *)(unsigned long)cmd.info, - uevent->info, uevent->info_len)) { - result = -EFAULT; - goto done; - } - } - - list_del(&uevent->file_list); - list_del(&uevent->ctx_list); - - if (uevent->data) - kfree(uevent->data); - if (uevent->info) - kfree(uevent->info); - kfree(uevent); -done: - up(&file->mutex); - return result; -} - - -static ssize_t ib_ucm_create_id(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_ucm_create_id cmd; - struct ib_ucm_create_id_resp resp; - struct ib_ucm_context *ctx; - int result; - - if (out_len < sizeof(resp)) - return -ENOSPC; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - ctx = ib_ucm_ctx_alloc(file); - if (!ctx) - return -ENOMEM; - - ctx->cm_id = ib_create_cm_id(ib_ucm_event_handler, - (void *)(unsigned long)ctx->id); - if (!ctx->cm_id) { - result = -ENOMEM; - goto err_cm; - } - - resp.id = ctx->id; - if (copy_to_user((void __user *)(unsigned long)cmd.response, - &resp, sizeof(resp))) { - result = -EFAULT; - goto err_ret; - } - - return 0; -err_ret: - ib_destroy_cm_id(ctx->cm_id); -err_cm: - ib_ucm_ctx_put(ctx); /* user reference */ - - return result; -} - -static ssize_t ib_ucm_destroy_id(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_ucm_destroy_id cmd; - struct ib_ucm_context *ctx; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) - return -ENOENT; - - ib_ucm_ctx_put(ctx); /* user reference */ - ib_ucm_ctx_put(ctx); /* func reference */ - - return 0; -} - -static ssize_t ib_ucm_attr_id(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_ucm_attr_id_resp resp; - struct ib_ucm_attr_id cmd; - struct ib_ucm_context *ctx; - int result = 0; - - if (out_len < sizeof(resp)) - return -ENOSPC; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) - return -ENOENT; - - down(&ctx->file->mutex); - if (ctx->file != file) { - result = -EINVAL; - goto done; - } - - resp.service_id = ctx->cm_id->service_id; - resp.service_mask = ctx->cm_id->service_mask; - resp.local_id = ctx->cm_id->local_id; - resp.remote_id = ctx->cm_id->remote_id; - - if (copy_to_user((void __user *)(unsigned long)cmd.response, - &resp, sizeof(resp))) - result = -EFAULT; - -done: - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ - return result; -} - -static ssize_t ib_ucm_listen(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_ucm_listen cmd; - struct ib_ucm_context *ctx; - int result; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) - return -ENOENT; - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = ib_cm_listen(ctx->cm_id, cmd.service_id, - cmd.service_mask); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ - return result; -} - -static ssize_t ib_ucm_establish(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_ucm_establish cmd; - struct ib_ucm_context *ctx; - int result; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) - return -ENOENT; - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = ib_cm_establish(ctx->cm_id); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ - return result; -} - -static int ib_ucm_alloc_data(const void **dest, u64 src, u32 len) -{ - void *data; - - *dest = NULL; - - if (!len) - return 0; - - data = kmalloc(len, GFP_KERNEL); - if (!data) - return -ENOMEM; - - if (copy_from_user(data, (void __user *)(unsigned long)src, len)) { - kfree(data); - return -EFAULT; - } - - *dest = data; - return 0; -} - -static int ib_ucm_path_get(struct ib_sa_path_rec **path, u64 src) -{ - struct ib_ucm_path_rec ucm_path; - struct ib_sa_path_rec *sa_path; - - *path = NULL; - - if (!src) - return 0; - - sa_path = kmalloc(sizeof(*sa_path), GFP_KERNEL); - if (!sa_path) - return -ENOMEM; - - if (copy_from_user(&ucm_path, (void __user *)(unsigned long)src, - sizeof(ucm_path))) { - - kfree(sa_path); - return -EFAULT; - } - - memcpy(sa_path->dgid.raw, ucm_path.dgid, sizeof(union ib_gid)); - memcpy(sa_path->sgid.raw, ucm_path.sgid, sizeof(union ib_gid)); - - sa_path->dlid = ucm_path.dlid; - sa_path->slid = ucm_path.slid; - sa_path->raw_traffic = ucm_path.raw_traffic; - sa_path->flow_label = ucm_path.flow_label; - sa_path->hop_limit = ucm_path.hop_limit; - sa_path->traffic_class = ucm_path.traffic_class; - sa_path->reversible = ucm_path.reversible; - sa_path->numb_path = ucm_path.numb_path; - sa_path->pkey = ucm_path.pkey; - sa_path->sl = ucm_path.sl; - sa_path->mtu_selector = ucm_path.mtu_selector; - sa_path->mtu = ucm_path.mtu; - sa_path->rate_selector = ucm_path.rate_selector; - sa_path->rate = ucm_path.rate; - sa_path->packet_life_time = ucm_path.packet_life_time; - sa_path->preference = ucm_path.preference; - - sa_path->packet_life_time_selector = - ucm_path.packet_life_time_selector; - - *path = sa_path; - return 0; -} - -static ssize_t ib_ucm_send_req(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_cm_req_param param; - struct ib_ucm_context *ctx; - struct ib_ucm_req cmd; - int result; - - param.private_data = NULL; - param.primary_path = NULL; - param.alternate_path = NULL; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - result = ib_ucm_alloc_data(¶m.private_data, cmd.data, cmd.len); - if (result) - goto done; - - result = ib_ucm_path_get(¶m.primary_path, cmd.primary_path); - if (result) - goto done; - - result = ib_ucm_path_get(¶m.alternate_path, cmd.alternate_path); - if (result) - goto done; - - param.private_data_len = cmd.len; - param.service_id = cmd.sid; - param.qp_num = cmd.qpn; - param.qp_type = cmd.qp_type; - param.starting_psn = cmd.psn; - param.peer_to_peer = cmd.peer_to_peer; - param.responder_resources = cmd.responder_resources; - param.initiator_depth = cmd.initiator_depth; - param.remote_cm_response_timeout = cmd.remote_cm_response_timeout; - param.flow_control = cmd.flow_control; - param.local_cm_response_timeout = cmd.local_cm_response_timeout; - param.retry_count = cmd.retry_count; - param.rnr_retry_count = cmd.rnr_retry_count; - param.max_cm_retries = cmd.max_cm_retries; - param.srq = cmd.srq; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) { - result = -ENOENT; - goto done; - } - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = ib_send_cm_req(ctx->cm_id, ¶m); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ -done: - if (param.private_data) - kfree(param.private_data); - if (param.primary_path) - kfree(param.primary_path); - if (param.alternate_path) - kfree(param.alternate_path); - - return result; -} - -static ssize_t ib_ucm_send_rep(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_cm_rep_param param; - struct ib_ucm_context *ctx; - struct ib_ucm_rep cmd; - int result; - - param.private_data = NULL; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - result = ib_ucm_alloc_data(¶m.private_data, cmd.data, cmd.len); - if (result) - return result; - - param.qp_num = cmd.qpn; - param.starting_psn = cmd.psn; - param.private_data_len = cmd.len; - param.responder_resources = cmd.responder_resources; - param.initiator_depth = cmd.initiator_depth; - param.target_ack_delay = cmd.target_ack_delay; - param.failover_accepted = cmd.failover_accepted; - param.flow_control = cmd.flow_control; - param.rnr_retry_count = cmd.rnr_retry_count; - param.srq = cmd.srq; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) { - result = -ENOENT; - goto done; - } - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = ib_send_cm_rep(ctx->cm_id, ¶m); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ -done: - if (param.private_data) - kfree(param.private_data); - - return result; -} - -static ssize_t ib_ucm_send_private_data(struct ib_ucm_file *file, - const char __user *inbuf, int in_len, - int (*func)(struct ib_cm_id *cm_id, - const void *private_data, - u8 private_data_len)) -{ - struct ib_ucm_private_data cmd; - struct ib_ucm_context *ctx; - const void *private_data = NULL; - int result; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - result = ib_ucm_alloc_data(&private_data, cmd.data, cmd.len); - if (result) - return result; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) { - result = -ENOENT; - goto done; - } - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = func(ctx->cm_id, private_data, cmd.len); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ -done: - if (private_data) - kfree(private_data); - - return result; -} - -static ssize_t ib_ucm_send_rtu(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - return ib_ucm_send_private_data(file, inbuf, in_len, ib_send_cm_rtu); -} - -static ssize_t ib_ucm_send_dreq(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - return ib_ucm_send_private_data(file, inbuf, in_len, ib_send_cm_dreq); -} - -static ssize_t ib_ucm_send_drep(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - return ib_ucm_send_private_data(file, inbuf, in_len, ib_send_cm_drep); -} - -static ssize_t ib_ucm_send_info(struct ib_ucm_file *file, - const char __user *inbuf, int in_len, - int (*func)(struct ib_cm_id *cm_id, - int status, - const void *info, - u8 info_len, - const void *data, - u8 data_len)) -{ - struct ib_ucm_context *ctx; - struct ib_ucm_info cmd; - const void *data = NULL; - const void *info = NULL; - int result; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - result = ib_ucm_alloc_data(&data, cmd.data, cmd.data_len); - if (result) - goto done; - - result = ib_ucm_alloc_data(&info, cmd.info, cmd.info_len); - if (result) - goto done; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) { - result = -ENOENT; - goto done; - } - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = func(ctx->cm_id, cmd.status, - info, cmd.info_len, - data, cmd.data_len); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ -done: - if (data) - kfree(data); - if (info) - kfree(info); - - return result; -} - -static ssize_t ib_ucm_send_rej(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - return ib_ucm_send_info(file, inbuf, in_len, (void *)ib_send_cm_rej); -} - -static ssize_t ib_ucm_send_apr(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - return ib_ucm_send_info(file, inbuf, in_len, (void *)ib_send_cm_apr); -} - -static ssize_t ib_ucm_send_mra(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_ucm_context *ctx; - struct ib_ucm_mra cmd; - const void *data = NULL; - int result; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - result = ib_ucm_alloc_data(&data, cmd.data, cmd.len); - if (result) - return result; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) { - result = -ENOENT; - goto done; - } - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = ib_send_cm_mra(ctx->cm_id, cmd.timeout, - data, cmd.len); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ -done: - if (data) - kfree(data); - - return result; -} - -static ssize_t ib_ucm_send_lap(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_ucm_context *ctx; - struct ib_sa_path_rec *path = NULL; - struct ib_ucm_lap cmd; - const void *data = NULL; - int result; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - result = ib_ucm_alloc_data(&data, cmd.data, cmd.len); - if (result) - goto done; - - result = ib_ucm_path_get(&path, cmd.path); - if (result) - goto done; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) { - result = -ENOENT; - goto done; - } - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = ib_send_cm_lap(ctx->cm_id, path, data, cmd.len); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ -done: - if (data) - kfree(data); - if (path) - kfree(path); - - return result; -} - -static ssize_t ib_ucm_send_sidr_req(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_cm_sidr_req_param param; - struct ib_ucm_context *ctx; - struct ib_ucm_sidr_req cmd; - int result; - - param.private_data = NULL; - param.path = NULL; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - result = ib_ucm_alloc_data(¶m.private_data, cmd.data, cmd.len); - if (result) - goto done; - - result = ib_ucm_path_get(¶m.path, cmd.path); - if (result) - goto done; - - param.private_data_len = cmd.len; - param.service_id = cmd.sid; - param.timeout_ms = cmd.timeout; - param.max_cm_retries = cmd.max_cm_retries; - param.pkey = cmd.pkey; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) { - result = -ENOENT; - goto done; - } - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = ib_send_cm_sidr_req(ctx->cm_id, ¶m); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ -done: - if (param.private_data) - kfree(param.private_data); - if (param.path) - kfree(param.path); - - return result; -} - -static ssize_t ib_ucm_send_sidr_rep(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) -{ - struct ib_cm_sidr_rep_param param; - struct ib_ucm_sidr_rep cmd; - struct ib_ucm_context *ctx; - int result; - - param.info = NULL; - - if (copy_from_user(&cmd, inbuf, sizeof(cmd))) - return -EFAULT; - - result = ib_ucm_alloc_data(¶m.private_data, - cmd.data, cmd.data_len); - if (result) - goto done; - - result = ib_ucm_alloc_data(¶m.info, cmd.info, cmd.info_len); - if (result) - goto done; - - param.qp_num = cmd.qpn; - param.qkey = cmd.qkey; - param.status = cmd.status; - param.info_length = cmd.info_len; - param.private_data_len = cmd.data_len; - - ctx = ib_ucm_ctx_get(cmd.id); - if (!ctx) { - result = -ENOENT; - goto done; - } - - down(&ctx->file->mutex); - if (ctx->file != file) - result = -EINVAL; - else - result = ib_send_cm_sidr_rep(ctx->cm_id, ¶m); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* func reference */ -done: - if (param.private_data) - kfree(param.private_data); - if (param.info) - kfree(param.info); - - return result; -} - -static ssize_t (*ucm_cmd_table[])(struct ib_ucm_file *file, - const char __user *inbuf, - int in_len, int out_len) = { - [IB_USER_CM_CMD_CREATE_ID] = ib_ucm_create_id, - [IB_USER_CM_CMD_DESTROY_ID] = ib_ucm_destroy_id, - [IB_USER_CM_CMD_ATTR_ID] = ib_ucm_attr_id, - [IB_USER_CM_CMD_LISTEN] = ib_ucm_listen, - [IB_USER_CM_CMD_ESTABLISH] = ib_ucm_establish, - [IB_USER_CM_CMD_SEND_REQ] = ib_ucm_send_req, - [IB_USER_CM_CMD_SEND_REP] = ib_ucm_send_rep, - [IB_USER_CM_CMD_SEND_RTU] = ib_ucm_send_rtu, - [IB_USER_CM_CMD_SEND_DREQ] = ib_ucm_send_dreq, - [IB_USER_CM_CMD_SEND_DREP] = ib_ucm_send_drep, - [IB_USER_CM_CMD_SEND_REJ] = ib_ucm_send_rej, - [IB_USER_CM_CMD_SEND_MRA] = ib_ucm_send_mra, - [IB_USER_CM_CMD_SEND_LAP] = ib_ucm_send_lap, - [IB_USER_CM_CMD_SEND_APR] = ib_ucm_send_apr, - [IB_USER_CM_CMD_SEND_SIDR_REQ] = ib_ucm_send_sidr_req, - [IB_USER_CM_CMD_SEND_SIDR_REP] = ib_ucm_send_sidr_rep, - [IB_USER_CM_CMD_EVENT] = ib_ucm_event, -}; - -static ssize_t ib_ucm_write(struct file *filp, const char __user *buf, - size_t len, loff_t *pos) -{ - struct ib_ucm_file *file = filp->private_data; - struct ib_ucm_cmd_hdr hdr; - ssize_t result; - - if (len < sizeof(hdr)) - return -EINVAL; - - if (copy_from_user(&hdr, buf, sizeof(hdr))) - return -EFAULT; - - printk(KERN_ERR "UCM: Write. cmd <%d> in <%d> out <%d> len <%Zu>\n", - hdr.cmd, hdr.in, hdr.out, len); - - if (hdr.cmd < 0 || hdr.cmd >= ARRAY_SIZE(ucm_cmd_table)) - return -EINVAL; - - if (hdr.in + sizeof(hdr) > len) - return -EINVAL; - - result = ucm_cmd_table[hdr.cmd](file, buf + sizeof(hdr), - hdr.in, hdr.out); - if (!result) - result = len; - - return result; -} - -static unsigned int ib_ucm_poll(struct file *filp, - struct poll_table_struct *wait) -{ - struct ib_ucm_file *file = filp->private_data; - unsigned int mask = 0; - - poll_wait(filp, &file->poll_wait, wait); - - if (!list_empty(&file->events)) - mask = POLLIN | POLLRDNORM; - - return mask; -} - -static int ib_ucm_open(struct inode *inode, struct file *filp) -{ - struct ib_ucm_file *file; - - file = kmalloc(sizeof(*file), GFP_KERNEL); - if (!file) - return -ENOMEM; - - INIT_LIST_HEAD(&file->events); - INIT_LIST_HEAD(&file->ctxs); - init_waitqueue_head(&file->poll_wait); - - init_MUTEX(&file->mutex); - - filp->private_data = file; - file->filp = filp; - - printk(KERN_ERR "UCM: Created struct\n"); - - return 0; -} - -static int ib_ucm_close(struct inode *inode, struct file *filp) -{ - struct ib_ucm_file *file = filp->private_data; - struct ib_ucm_context *ctx; - - down(&file->mutex); - - while (!list_empty(&file->ctxs)) { - - ctx = list_entry(file->ctxs.next, - struct ib_ucm_context, file_list); - - up(&ctx->file->mutex); - ib_ucm_ctx_put(ctx); /* user reference */ - down(&file->mutex); - } - - up(&file->mutex); - - kfree(file); - - printk(KERN_ERR "UCM: Deleted struct\n"); - return 0; -} - -static struct file_operations ib_ucm_fops = { - .owner = THIS_MODULE, - .open = ib_ucm_open, - .release = ib_ucm_close, - .write = ib_ucm_write, - .poll = ib_ucm_poll, -}; - - -static struct class *ib_ucm_class; -static struct cdev ib_ucm_cdev; - -static int __init ib_ucm_init(void) -{ - int result; - - result = register_chrdev_region(IB_UCM_DEV, 1, "infiniband_cm"); - if (result) { - printk(KERN_ERR "UCM: Error <%d> registering dev\n", result); - goto err_chr; - } - - cdev_init(&ib_ucm_cdev, &ib_ucm_fops); - - result = cdev_add(&ib_ucm_cdev, IB_UCM_DEV, 1); - if (result) { - printk(KERN_ERR "UCM: Error <%d> adding cdev\n", result); - goto err_cdev; - } - - ib_ucm_class = class_create(THIS_MODULE, "infiniband_cm"); - if (IS_ERR(ib_ucm_class)) { - result = PTR_ERR(ib_ucm_class); - printk(KERN_ERR "UCM: Error <%d> creating class\n", result); - goto err_class; - } - - class_device_create(ib_ucm_class, IB_UCM_DEV, NULL, "ucm"); - - idr_init(&ctx_id_table); - init_MUTEX(&ctx_id_mutex); - - return 0; -err_class: - cdev_del(&ib_ucm_cdev); -err_cdev: - unregister_chrdev_region(IB_UCM_DEV, 1); -err_chr: - return result; -} - -static void __exit ib_ucm_cleanup(void) -{ - class_device_destroy(ib_ucm_class, IB_UCM_DEV); - class_destroy(ib_ucm_class); - cdev_del(&ib_ucm_cdev); - unregister_chrdev_region(IB_UCM_DEV, 1); -} - -module_init(ib_ucm_init); -module_exit(ib_ucm_cleanup); diff --git a/trunk/drivers/infiniband/core/ucm.h b/trunk/drivers/infiniband/core/ucm.h deleted file mode 100644 index 6d36606151b2..000000000000 --- a/trunk/drivers/infiniband/core/ucm.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2005 Topspin Communications. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * $Id: ucm.h 2208 2005-04-22 23:24:31Z libor $ - */ - -#ifndef UCM_H -#define UCM_H - -#include -#include -#include -#include - -#include -#include - -#define IB_UCM_CM_ID_INVALID 0xffffffff - -struct ib_ucm_file { - struct semaphore mutex; - struct file *filp; - /* - * list of pending events - */ - struct list_head ctxs; /* list of active connections */ - struct list_head events; /* list of pending events */ - wait_queue_head_t poll_wait; -}; - -struct ib_ucm_context { - int id; - int ref; - int error; - - struct ib_ucm_file *file; - struct ib_cm_id *cm_id; - struct semaphore mutex; - - struct list_head events; /* list of pending events. */ - struct list_head file_list; /* member in file ctx list */ -}; - -struct ib_ucm_event { - struct ib_ucm_context *ctx; - struct list_head file_list; /* member in file event list */ - struct list_head ctx_list; /* member in ctx event list */ - - struct ib_ucm_event_resp resp; - void *data; - void *info; - int data_len; - int info_len; - /* - * new connection identifiers needs to be saved until - * userspace can get a handle on them. - */ - struct ib_cm_id *cm_id; -}; - -#endif /* UCM_H */ diff --git a/trunk/drivers/infiniband/core/user_mad.c b/trunk/drivers/infiniband/core/user_mad.c index 2e38792df533..9d912d6877ff 100644 --- a/trunk/drivers/infiniband/core/user_mad.c +++ b/trunk/drivers/infiniband/core/user_mad.c @@ -1,7 +1,5 @@ /* * Copyright (c) 2004 Topspin Communications. All rights reserved. - * Copyright (c) 2005 Voltaire, Inc. All rights reserved. - * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU @@ -31,7 +29,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: user_mad.c 2814 2005-07-06 19:14:09Z halr $ + * $Id: user_mad.c 1389 2004-12-27 22:56:47Z roland $ */ #include @@ -96,12 +94,10 @@ struct ib_umad_file { }; struct ib_umad_packet { + struct ib_user_mad mad; struct ib_ah *ah; - struct ib_mad_send_buf *msg; struct list_head list; - int length; DECLARE_PCI_UNMAP_ADDR(mapping) - struct ib_user_mad mad; }; static const dev_t base_dev = MKDEV(IB_UMAD_MAJOR, IB_UMAD_MINOR_BASE); @@ -118,10 +114,10 @@ static int queue_packet(struct ib_umad_file *file, int ret = 1; down_read(&file->agent_mutex); - for (packet->mad.hdr.id = 0; - packet->mad.hdr.id < IB_UMAD_MAX_AGENTS; - packet->mad.hdr.id++) - if (agent == file->agent[packet->mad.hdr.id]) { + for (packet->mad.id = 0; + packet->mad.id < IB_UMAD_MAX_AGENTS; + packet->mad.id++) + if (agent == file->agent[packet->mad.id]) { spin_lock_irq(&file->recv_lock); list_add_tail(&packet->list, &file->recv_list); spin_unlock_irq(&file->recv_lock); @@ -139,30 +135,22 @@ static void send_handler(struct ib_mad_agent *agent, struct ib_mad_send_wc *send_wc) { struct ib_umad_file *file = agent->context; - struct ib_umad_packet *timeout, *packet = + struct ib_umad_packet *packet = (void *) (unsigned long) send_wc->wr_id; - ib_destroy_ah(packet->msg->send_wr.wr.ud.ah); - ib_free_send_mad(packet->msg); + dma_unmap_single(agent->device->dma_device, + pci_unmap_addr(packet, mapping), + sizeof packet->mad.data, + DMA_TO_DEVICE); + ib_destroy_ah(packet->ah); if (send_wc->status == IB_WC_RESP_TIMEOUT_ERR) { - timeout = kmalloc(sizeof *timeout + sizeof (struct ib_mad_hdr), - GFP_KERNEL); - if (!timeout) - goto out; - - memset(timeout, 0, sizeof *timeout + sizeof (struct ib_mad_hdr)); + packet->mad.status = ETIMEDOUT; - timeout->length = sizeof (struct ib_mad_hdr); - timeout->mad.hdr.id = packet->mad.hdr.id; - timeout->mad.hdr.status = ETIMEDOUT; - memcpy(timeout->mad.data, packet->mad.data, - sizeof (struct ib_mad_hdr)); - - if (!queue_packet(file, agent, timeout)) - return; + if (!queue_packet(file, agent, packet)) + return; } -out: + kfree(packet); } @@ -171,35 +159,30 @@ static void recv_handler(struct ib_mad_agent *agent, { struct ib_umad_file *file = agent->context; struct ib_umad_packet *packet; - int length; if (mad_recv_wc->wc->status != IB_WC_SUCCESS) goto out; - length = mad_recv_wc->mad_len; - packet = kmalloc(sizeof *packet + length, GFP_KERNEL); + packet = kmalloc(sizeof *packet, GFP_KERNEL); if (!packet) goto out; - memset(packet, 0, sizeof *packet + length); - packet->length = length; - - ib_coalesce_recv_mad(mad_recv_wc, packet->mad.data); + memset(packet, 0, sizeof *packet); - packet->mad.hdr.status = 0; - packet->mad.hdr.length = length + sizeof (struct ib_user_mad); - packet->mad.hdr.qpn = cpu_to_be32(mad_recv_wc->wc->src_qp); - packet->mad.hdr.lid = cpu_to_be16(mad_recv_wc->wc->slid); - packet->mad.hdr.sl = mad_recv_wc->wc->sl; - packet->mad.hdr.path_bits = mad_recv_wc->wc->dlid_path_bits; - packet->mad.hdr.grh_present = !!(mad_recv_wc->wc->wc_flags & IB_WC_GRH); - if (packet->mad.hdr.grh_present) { + memcpy(packet->mad.data, mad_recv_wc->recv_buf.mad, sizeof packet->mad.data); + packet->mad.status = 0; + packet->mad.qpn = cpu_to_be32(mad_recv_wc->wc->src_qp); + packet->mad.lid = cpu_to_be16(mad_recv_wc->wc->slid); + packet->mad.sl = mad_recv_wc->wc->sl; + packet->mad.path_bits = mad_recv_wc->wc->dlid_path_bits; + packet->mad.grh_present = !!(mad_recv_wc->wc->wc_flags & IB_WC_GRH); + if (packet->mad.grh_present) { /* XXX parse GRH */ - packet->mad.hdr.gid_index = 0; - packet->mad.hdr.hop_limit = 0; - packet->mad.hdr.traffic_class = 0; - memset(packet->mad.hdr.gid, 0, 16); - packet->mad.hdr.flow_label = 0; + packet->mad.gid_index = 0; + packet->mad.hop_limit = 0; + packet->mad.traffic_class = 0; + memset(packet->mad.gid, 0, 16); + packet->mad.flow_label = 0; } if (queue_packet(file, agent, packet)) @@ -216,7 +199,7 @@ static ssize_t ib_umad_read(struct file *filp, char __user *buf, struct ib_umad_packet *packet; ssize_t ret; - if (count < sizeof (struct ib_user_mad) + sizeof (struct ib_mad)) + if (count < sizeof (struct ib_user_mad)) return -EINVAL; spin_lock_irq(&file->recv_lock); @@ -239,25 +222,12 @@ static ssize_t ib_umad_read(struct file *filp, char __user *buf, spin_unlock_irq(&file->recv_lock); - if (count < packet->length + sizeof (struct ib_user_mad)) { - /* Return length needed (and first RMPP segment) if too small */ - if (copy_to_user(buf, &packet->mad, - sizeof (struct ib_user_mad) + sizeof (struct ib_mad))) - ret = -EFAULT; - else - ret = -ENOSPC; - } else if (copy_to_user(buf, &packet->mad, - packet->length + sizeof (struct ib_user_mad))) + if (copy_to_user(buf, &packet->mad, sizeof packet->mad)) ret = -EFAULT; else - ret = packet->length + sizeof (struct ib_user_mad); - if (ret < 0) { - /* Requeue packet */ - spin_lock_irq(&file->recv_lock); - list_add(&packet->list, &file->recv_list); - spin_unlock_irq(&file->recv_lock); - } else - kfree(packet); + ret = sizeof packet->mad; + + kfree(packet); return ret; } @@ -268,163 +238,105 @@ static ssize_t ib_umad_write(struct file *filp, const char __user *buf, struct ib_umad_packet *packet; struct ib_mad_agent *agent; struct ib_ah_attr ah_attr; - struct ib_send_wr *bad_wr; - struct ib_rmpp_mad *rmpp_mad; + struct ib_sge gather_list; + struct ib_send_wr *bad_wr, wr = { + .opcode = IB_WR_SEND, + .sg_list = &gather_list, + .num_sge = 1, + .send_flags = IB_SEND_SIGNALED, + }; u8 method; u64 *tid; - int ret, length, hdr_len, data_len, rmpp_hdr_size; - int rmpp_active = 0; + int ret; if (count < sizeof (struct ib_user_mad)) return -EINVAL; - length = count - sizeof (struct ib_user_mad); - packet = kmalloc(sizeof *packet + sizeof(struct ib_mad_hdr) + - sizeof(struct ib_rmpp_hdr), GFP_KERNEL); + packet = kmalloc(sizeof *packet, GFP_KERNEL); if (!packet) return -ENOMEM; - if (copy_from_user(&packet->mad, buf, - sizeof (struct ib_user_mad) + - sizeof(struct ib_mad_hdr) + - sizeof(struct ib_rmpp_hdr))) { - ret = -EFAULT; - goto err; + if (copy_from_user(&packet->mad, buf, sizeof packet->mad)) { + kfree(packet); + return -EFAULT; } - if (packet->mad.hdr.id < 0 || - packet->mad.hdr.id >= IB_UMAD_MAX_AGENTS) { + if (packet->mad.id < 0 || packet->mad.id >= IB_UMAD_MAX_AGENTS) { ret = -EINVAL; goto err; } - packet->length = length; - down_read(&file->agent_mutex); - agent = file->agent[packet->mad.hdr.id]; + agent = file->agent[packet->mad.id]; if (!agent) { ret = -EINVAL; goto err_up; } - memset(&ah_attr, 0, sizeof ah_attr); - ah_attr.dlid = be16_to_cpu(packet->mad.hdr.lid); - ah_attr.sl = packet->mad.hdr.sl; - ah_attr.src_path_bits = packet->mad.hdr.path_bits; - ah_attr.port_num = file->port->port_num; - if (packet->mad.hdr.grh_present) { - ah_attr.ah_flags = IB_AH_GRH; - memcpy(ah_attr.grh.dgid.raw, packet->mad.hdr.gid, 16); - ah_attr.grh.flow_label = packet->mad.hdr.flow_label; - ah_attr.grh.hop_limit = packet->mad.hdr.hop_limit; - ah_attr.grh.traffic_class = packet->mad.hdr.traffic_class; - } - - packet->ah = ib_create_ah(agent->qp->pd, &ah_attr); - if (IS_ERR(packet->ah)) { - ret = PTR_ERR(packet->ah); - goto err_up; - } - - rmpp_mad = (struct ib_rmpp_mad *) packet->mad.data; - if (ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) & IB_MGMT_RMPP_FLAG_ACTIVE) { - /* RMPP active */ - if (!agent->rmpp_version) { - ret = -EINVAL; - goto err_ah; - } - /* Validate that management class can support RMPP */ - if (rmpp_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_ADM) { - hdr_len = offsetof(struct ib_sa_mad, data); - data_len = length; - } else if ((rmpp_mad->mad_hdr.mgmt_class >= IB_MGMT_CLASS_VENDOR_RANGE2_START) && - (rmpp_mad->mad_hdr.mgmt_class <= IB_MGMT_CLASS_VENDOR_RANGE2_END)) { - hdr_len = offsetof(struct ib_vendor_mad, data); - data_len = length - hdr_len; - } else { - ret = -EINVAL; - goto err_ah; - } - rmpp_active = 1; - } else { - if (length > sizeof(struct ib_mad)) { - ret = -EINVAL; - goto err_ah; - } - hdr_len = offsetof(struct ib_mad, data); - data_len = length - hdr_len; - } - - packet->msg = ib_create_send_mad(agent, - be32_to_cpu(packet->mad.hdr.qpn), - 0, packet->ah, rmpp_active, - hdr_len, data_len, - GFP_KERNEL); - if (IS_ERR(packet->msg)) { - ret = PTR_ERR(packet->msg); - goto err_ah; - } - - packet->msg->send_wr.wr.ud.timeout_ms = packet->mad.hdr.timeout_ms; - packet->msg->send_wr.wr.ud.retries = packet->mad.hdr.retries; - - /* Override send WR WRID initialized in ib_create_send_mad */ - packet->msg->send_wr.wr_id = (unsigned long) packet; - - if (!rmpp_active) { - /* Copy message from user into send buffer */ - if (copy_from_user(packet->msg->mad, - buf + sizeof(struct ib_user_mad), length)) { - ret = -EFAULT; - goto err_msg; - } - } else { - rmpp_hdr_size = sizeof(struct ib_mad_hdr) + - sizeof(struct ib_rmpp_hdr); - - /* Only copy MAD headers (RMPP header in place) */ - memcpy(packet->msg->mad, packet->mad.data, - sizeof(struct ib_mad_hdr)); - - /* Now, copy rest of message from user into send buffer */ - if (copy_from_user(((struct ib_rmpp_mad *) packet->msg->mad)->data, - buf + sizeof (struct ib_user_mad) + rmpp_hdr_size, - length - rmpp_hdr_size)) { - ret = -EFAULT; - goto err_msg; - } - } - /* * If userspace is generating a request that will generate a * response, we need to make sure the high-order part of the * transaction ID matches the agent being used to send the * MAD. */ - method = packet->msg->mad->mad_hdr.method; + method = ((struct ib_mad_hdr *) packet->mad.data)->method; if (!(method & IB_MGMT_METHOD_RESP) && method != IB_MGMT_METHOD_TRAP_REPRESS && method != IB_MGMT_METHOD_SEND) { - tid = &packet->msg->mad->mad_hdr.tid; + tid = &((struct ib_mad_hdr *) packet->mad.data)->tid; *tid = cpu_to_be64(((u64) agent->hi_tid) << 32 | (be64_to_cpup(tid) & 0xffffffff)); } - ret = ib_post_send_mad(agent, &packet->msg->send_wr, &bad_wr); - if (ret) - goto err_msg; + memset(&ah_attr, 0, sizeof ah_attr); + ah_attr.dlid = be16_to_cpu(packet->mad.lid); + ah_attr.sl = packet->mad.sl; + ah_attr.src_path_bits = packet->mad.path_bits; + ah_attr.port_num = file->port->port_num; + if (packet->mad.grh_present) { + ah_attr.ah_flags = IB_AH_GRH; + memcpy(ah_attr.grh.dgid.raw, packet->mad.gid, 16); + ah_attr.grh.flow_label = packet->mad.flow_label; + ah_attr.grh.hop_limit = packet->mad.hop_limit; + ah_attr.grh.traffic_class = packet->mad.traffic_class; + } + + packet->ah = ib_create_ah(agent->qp->pd, &ah_attr); + if (IS_ERR(packet->ah)) { + ret = PTR_ERR(packet->ah); + goto err_up; + } + + gather_list.addr = dma_map_single(agent->device->dma_device, + packet->mad.data, + sizeof packet->mad.data, + DMA_TO_DEVICE); + gather_list.length = sizeof packet->mad.data; + gather_list.lkey = file->mr[packet->mad.id]->lkey; + pci_unmap_addr_set(packet, mapping, gather_list.addr); - up_read(&file->agent_mutex); + wr.wr.ud.mad_hdr = (struct ib_mad_hdr *) packet->mad.data; + wr.wr.ud.ah = packet->ah; + wr.wr.ud.remote_qpn = be32_to_cpu(packet->mad.qpn); + wr.wr.ud.remote_qkey = be32_to_cpu(packet->mad.qkey); + wr.wr.ud.timeout_ms = packet->mad.timeout_ms; - return sizeof (struct ib_user_mad_hdr) + packet->length; + wr.wr_id = (unsigned long) packet; + + ret = ib_post_send_mad(agent, &wr, &bad_wr); + if (ret) { + dma_unmap_single(agent->device->dma_device, + pci_unmap_addr(packet, mapping), + sizeof packet->mad.data, + DMA_TO_DEVICE); + goto err_up; + } -err_msg: - ib_free_send_mad(packet->msg); + up_read(&file->agent_mutex); -err_ah: - ib_destroy_ah(packet->ah); + return sizeof packet->mad; err_up: up_read(&file->agent_mutex); @@ -487,8 +399,7 @@ static int ib_umad_reg_agent(struct ib_umad_file *file, unsigned long arg) agent = ib_register_mad_agent(file->port->ib_dev, file->port->port_num, ureq.qpn ? IB_QPT_GSI : IB_QPT_SMI, ureq.mgmt_class ? &req : NULL, - ureq.rmpp_version, - send_handler, recv_handler, file); + 0, send_handler, recv_handler, file); if (IS_ERR(agent)) { ret = PTR_ERR(agent); goto out; @@ -549,8 +460,8 @@ static int ib_umad_unreg_agent(struct ib_umad_file *file, unsigned long arg) return ret; } -static long ib_umad_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg) +static long ib_umad_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg) { switch (cmd) { case IB_USER_MAD_REGISTER_AGENT: @@ -606,14 +517,14 @@ static int ib_umad_close(struct inode *inode, struct file *filp) } static struct file_operations umad_fops = { - .owner = THIS_MODULE, - .read = ib_umad_read, - .write = ib_umad_write, - .poll = ib_umad_poll, + .owner = THIS_MODULE, + .read = ib_umad_read, + .write = ib_umad_write, + .poll = ib_umad_poll, .unlocked_ioctl = ib_umad_ioctl, - .compat_ioctl = ib_umad_ioctl, - .open = ib_umad_open, - .release = ib_umad_close + .compat_ioctl = ib_umad_ioctl, + .open = ib_umad_open, + .release = ib_umad_close }; static int ib_umad_sm_open(struct inode *inode, struct file *filp) diff --git a/trunk/drivers/infiniband/core/verbs.c b/trunk/drivers/infiniband/core/verbs.c index 506fdf1f2a26..2516f9646515 100644 --- a/trunk/drivers/infiniband/core/verbs.c +++ b/trunk/drivers/infiniband/core/verbs.c @@ -41,7 +41,6 @@ #include #include -#include /* Protection domains */ @@ -89,40 +88,6 @@ struct ib_ah *ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr) } EXPORT_SYMBOL(ib_create_ah); -struct ib_ah *ib_create_ah_from_wc(struct ib_pd *pd, struct ib_wc *wc, - struct ib_grh *grh, u8 port_num) -{ - struct ib_ah_attr ah_attr; - u32 flow_class; - u16 gid_index; - int ret; - - memset(&ah_attr, 0, sizeof ah_attr); - ah_attr.dlid = wc->slid; - ah_attr.sl = wc->sl; - ah_attr.src_path_bits = wc->dlid_path_bits; - ah_attr.port_num = port_num; - - if (wc->wc_flags & IB_WC_GRH) { - ah_attr.ah_flags = IB_AH_GRH; - ah_attr.grh.dgid = grh->dgid; - - ret = ib_find_cached_gid(pd->device, &grh->sgid, &port_num, - &gid_index); - if (ret) - return ERR_PTR(ret); - - ah_attr.grh.sgid_index = (u8) gid_index; - flow_class = be32_to_cpu(grh->version_tclass_flow); - ah_attr.grh.flow_label = flow_class & 0xFFFFF; - ah_attr.grh.traffic_class = (flow_class >> 20) & 0xFF; - ah_attr.grh.hop_limit = grh->hop_limit; - } - - return ib_create_ah(pd, &ah_attr); -} -EXPORT_SYMBOL(ib_create_ah_from_wc); - int ib_modify_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr) { return ah->device->modify_ah ? diff --git a/trunk/drivers/infiniband/include/ib_cm.h b/trunk/drivers/infiniband/include/ib_cm.h deleted file mode 100644 index e5d74a730a70..000000000000 --- a/trunk/drivers/infiniband/include/ib_cm.h +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright (c) 2004 Intel Corporation. All rights reserved. - * Copyright (c) 2004 Topspin Corporation. All rights reserved. - * Copyright (c) 2004 Voltaire Corporation. All rights reserved. - * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * $Id: ib_cm.h 2730 2005-06-28 16:43:03Z sean.hefty $ - */ -#if !defined(IB_CM_H) -#define IB_CM_H - -#include -#include - -enum ib_cm_state { - IB_CM_IDLE, - IB_CM_LISTEN, - IB_CM_REQ_SENT, - IB_CM_REQ_RCVD, - IB_CM_MRA_REQ_SENT, - IB_CM_MRA_REQ_RCVD, - IB_CM_REP_SENT, - IB_CM_REP_RCVD, - IB_CM_MRA_REP_SENT, - IB_CM_MRA_REP_RCVD, - IB_CM_ESTABLISHED, - IB_CM_DREQ_SENT, - IB_CM_DREQ_RCVD, - IB_CM_TIMEWAIT, - IB_CM_SIDR_REQ_SENT, - IB_CM_SIDR_REQ_RCVD -}; - -enum ib_cm_lap_state { - IB_CM_LAP_IDLE, - IB_CM_LAP_SENT, - IB_CM_LAP_RCVD, - IB_CM_MRA_LAP_SENT, - IB_CM_MRA_LAP_RCVD, -}; - -enum ib_cm_event_type { - IB_CM_REQ_ERROR, - IB_CM_REQ_RECEIVED, - IB_CM_REP_ERROR, - IB_CM_REP_RECEIVED, - IB_CM_RTU_RECEIVED, - IB_CM_USER_ESTABLISHED, - IB_CM_DREQ_ERROR, - IB_CM_DREQ_RECEIVED, - IB_CM_DREP_RECEIVED, - IB_CM_TIMEWAIT_EXIT, - IB_CM_MRA_RECEIVED, - IB_CM_REJ_RECEIVED, - IB_CM_LAP_ERROR, - IB_CM_LAP_RECEIVED, - IB_CM_APR_RECEIVED, - IB_CM_SIDR_REQ_ERROR, - IB_CM_SIDR_REQ_RECEIVED, - IB_CM_SIDR_REP_RECEIVED -}; - -enum ib_cm_data_size { - IB_CM_REQ_PRIVATE_DATA_SIZE = 92, - IB_CM_MRA_PRIVATE_DATA_SIZE = 222, - IB_CM_REJ_PRIVATE_DATA_SIZE = 148, - IB_CM_REP_PRIVATE_DATA_SIZE = 196, - IB_CM_RTU_PRIVATE_DATA_SIZE = 224, - IB_CM_DREQ_PRIVATE_DATA_SIZE = 220, - IB_CM_DREP_PRIVATE_DATA_SIZE = 224, - IB_CM_REJ_ARI_LENGTH = 72, - IB_CM_LAP_PRIVATE_DATA_SIZE = 168, - IB_CM_APR_PRIVATE_DATA_SIZE = 148, - IB_CM_APR_INFO_LENGTH = 72, - IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE = 216, - IB_CM_SIDR_REP_PRIVATE_DATA_SIZE = 136, - IB_CM_SIDR_REP_INFO_LENGTH = 72 -}; - -struct ib_cm_id; - -struct ib_cm_req_event_param { - struct ib_cm_id *listen_id; - struct ib_device *device; - u8 port; - - struct ib_sa_path_rec *primary_path; - struct ib_sa_path_rec *alternate_path; - - u64 remote_ca_guid; - u32 remote_qkey; - u32 remote_qpn; - enum ib_qp_type qp_type; - - u32 starting_psn; - u8 responder_resources; - u8 initiator_depth; - unsigned int local_cm_response_timeout:5; - unsigned int flow_control:1; - unsigned int remote_cm_response_timeout:5; - unsigned int retry_count:3; - unsigned int rnr_retry_count:3; - unsigned int srq:1; -}; - -struct ib_cm_rep_event_param { - u64 remote_ca_guid; - u32 remote_qkey; - u32 remote_qpn; - u32 starting_psn; - u8 responder_resources; - u8 initiator_depth; - unsigned int target_ack_delay:5; - unsigned int failover_accepted:2; - unsigned int flow_control:1; - unsigned int rnr_retry_count:3; - unsigned int srq:1; -}; - -enum ib_cm_rej_reason { - IB_CM_REJ_NO_QP = __constant_htons(1), - IB_CM_REJ_NO_EEC = __constant_htons(2), - IB_CM_REJ_NO_RESOURCES = __constant_htons(3), - IB_CM_REJ_TIMEOUT = __constant_htons(4), - IB_CM_REJ_UNSUPPORTED = __constant_htons(5), - IB_CM_REJ_INVALID_COMM_ID = __constant_htons(6), - IB_CM_REJ_INVALID_COMM_INSTANCE = __constant_htons(7), - IB_CM_REJ_INVALID_SERVICE_ID = __constant_htons(8), - IB_CM_REJ_INVALID_TRANSPORT_TYPE = __constant_htons(9), - IB_CM_REJ_STALE_CONN = __constant_htons(10), - IB_CM_REJ_RDC_NOT_EXIST = __constant_htons(11), - IB_CM_REJ_INVALID_GID = __constant_htons(12), - IB_CM_REJ_INVALID_LID = __constant_htons(13), - IB_CM_REJ_INVALID_SL = __constant_htons(14), - IB_CM_REJ_INVALID_TRAFFIC_CLASS = __constant_htons(15), - IB_CM_REJ_INVALID_HOP_LIMIT = __constant_htons(16), - IB_CM_REJ_INVALID_PACKET_RATE = __constant_htons(17), - IB_CM_REJ_INVALID_ALT_GID = __constant_htons(18), - IB_CM_REJ_INVALID_ALT_LID = __constant_htons(19), - IB_CM_REJ_INVALID_ALT_SL = __constant_htons(20), - IB_CM_REJ_INVALID_ALT_TRAFFIC_CLASS = __constant_htons(21), - IB_CM_REJ_INVALID_ALT_HOP_LIMIT = __constant_htons(22), - IB_CM_REJ_INVALID_ALT_PACKET_RATE = __constant_htons(23), - IB_CM_REJ_PORT_REDIRECT = __constant_htons(24), - IB_CM_REJ_INVALID_MTU = __constant_htons(26), - IB_CM_REJ_INSUFFICIENT_RESP_RESOURCES = __constant_htons(27), - IB_CM_REJ_CONSUMER_DEFINED = __constant_htons(28), - IB_CM_REJ_INVALID_RNR_RETRY = __constant_htons(29), - IB_CM_REJ_DUPLICATE_LOCAL_COMM_ID = __constant_htons(30), - IB_CM_REJ_INVALID_CLASS_VERSION = __constant_htons(31), - IB_CM_REJ_INVALID_FLOW_LABEL = __constant_htons(32), - IB_CM_REJ_INVALID_ALT_FLOW_LABEL = __constant_htons(33) -}; - -struct ib_cm_rej_event_param { - enum ib_cm_rej_reason reason; - void *ari; - u8 ari_length; -}; - -struct ib_cm_mra_event_param { - u8 service_timeout; -}; - -struct ib_cm_lap_event_param { - struct ib_sa_path_rec *alternate_path; -}; - -enum ib_cm_apr_status { - IB_CM_APR_SUCCESS, - IB_CM_APR_INVALID_COMM_ID, - IB_CM_APR_UNSUPPORTED, - IB_CM_APR_REJECT, - IB_CM_APR_REDIRECT, - IB_CM_APR_IS_CURRENT, - IB_CM_APR_INVALID_QPN_EECN, - IB_CM_APR_INVALID_LID, - IB_CM_APR_INVALID_GID, - IB_CM_APR_INVALID_FLOW_LABEL, - IB_CM_APR_INVALID_TCLASS, - IB_CM_APR_INVALID_HOP_LIMIT, - IB_CM_APR_INVALID_PACKET_RATE, - IB_CM_APR_INVALID_SL -}; - -struct ib_cm_apr_event_param { - enum ib_cm_apr_status ap_status; - void *apr_info; - u8 info_len; -}; - -struct ib_cm_sidr_req_event_param { - struct ib_cm_id *listen_id; - struct ib_device *device; - u8 port; - - u16 pkey; -}; - -enum ib_cm_sidr_status { - IB_SIDR_SUCCESS, - IB_SIDR_UNSUPPORTED, - IB_SIDR_REJECT, - IB_SIDR_NO_QP, - IB_SIDR_REDIRECT, - IB_SIDR_UNSUPPORTED_VERSION -}; - -struct ib_cm_sidr_rep_event_param { - enum ib_cm_sidr_status status; - u32 qkey; - u32 qpn; - void *info; - u8 info_len; - -}; - -struct ib_cm_event { - enum ib_cm_event_type event; - union { - struct ib_cm_req_event_param req_rcvd; - struct ib_cm_rep_event_param rep_rcvd; - /* No data for RTU received events. */ - struct ib_cm_rej_event_param rej_rcvd; - struct ib_cm_mra_event_param mra_rcvd; - struct ib_cm_lap_event_param lap_rcvd; - struct ib_cm_apr_event_param apr_rcvd; - /* No data for DREQ/DREP received events. */ - struct ib_cm_sidr_req_event_param sidr_req_rcvd; - struct ib_cm_sidr_rep_event_param sidr_rep_rcvd; - enum ib_wc_status send_status; - } param; - - void *private_data; -}; - -/** - * ib_cm_handler - User-defined callback to process communication events. - * @cm_id: Communication identifier associated with the reported event. - * @event: Information about the communication event. - * - * IB_CM_REQ_RECEIVED and IB_CM_SIDR_REQ_RECEIVED communication events - * generated as a result of listen requests result in the allocation of a - * new @cm_id. The new @cm_id is returned to the user through this callback. - * Clients are responsible for destroying the new @cm_id. For peer-to-peer - * IB_CM_REQ_RECEIVED and all other events, the returned @cm_id corresponds - * to a user's existing communication identifier. - * - * Users may not call ib_destroy_cm_id while in the context of this callback; - * however, returning a non-zero value instructs the communication manager to - * destroy the @cm_id after the callback completes. - */ -typedef int (*ib_cm_handler)(struct ib_cm_id *cm_id, - struct ib_cm_event *event); - -struct ib_cm_id { - ib_cm_handler cm_handler; - void *context; - u64 service_id; - u64 service_mask; - enum ib_cm_state state; /* internal CM/debug use */ - enum ib_cm_lap_state lap_state; /* internal CM/debug use */ - u32 local_id; - u32 remote_id; -}; - -/** - * ib_create_cm_id - Allocate a communication identifier. - * @cm_handler: Callback invoked to notify the user of CM events. - * @context: User specified context associated with the communication - * identifier. - * - * Communication identifiers are used to track connection states, service - * ID resolution requests, and listen requests. - */ -struct ib_cm_id *ib_create_cm_id(ib_cm_handler cm_handler, - void *context); - -/** - * ib_destroy_cm_id - Destroy a connection identifier. - * @cm_id: Connection identifier to destroy. - * - * This call blocks until the connection identifier is destroyed. - */ -void ib_destroy_cm_id(struct ib_cm_id *cm_id); - -#define IB_SERVICE_ID_AGN_MASK __constant_cpu_to_be64(0xFF00000000000000ULL) -#define IB_CM_ASSIGN_SERVICE_ID __constant_cpu_to_be64(0x0200000000000000ULL) - -/** - * ib_cm_listen - Initiates listening on the specified service ID for - * connection and service ID resolution requests. - * @cm_id: Connection identifier associated with the listen request. - * @service_id: Service identifier matched against incoming connection - * and service ID resolution requests. The service ID should be specified - * network-byte order. If set to IB_CM_ASSIGN_SERVICE_ID, the CM will - * assign a service ID to the caller. - * @service_mask: Mask applied to service ID used to listen across a - * range of service IDs. If set to 0, the service ID is matched - * exactly. This parameter is ignored if %service_id is set to - * IB_CM_ASSIGN_SERVICE_ID. - */ -int ib_cm_listen(struct ib_cm_id *cm_id, - u64 service_id, - u64 service_mask); - -struct ib_cm_req_param { - struct ib_sa_path_rec *primary_path; - struct ib_sa_path_rec *alternate_path; - u64 service_id; - u32 qp_num; - enum ib_qp_type qp_type; - u32 starting_psn; - const void *private_data; - u8 private_data_len; - u8 peer_to_peer; - u8 responder_resources; - u8 initiator_depth; - u8 remote_cm_response_timeout; - u8 flow_control; - u8 local_cm_response_timeout; - u8 retry_count; - u8 rnr_retry_count; - u8 max_cm_retries; - u8 srq; -}; - -/** - * ib_send_cm_req - Sends a connection request to the remote node. - * @cm_id: Connection identifier that will be associated with the - * connection request. - * @param: Connection request information needed to establish the - * connection. - */ -int ib_send_cm_req(struct ib_cm_id *cm_id, - struct ib_cm_req_param *param); - -struct ib_cm_rep_param { - u32 qp_num; - u32 starting_psn; - const void *private_data; - u8 private_data_len; - u8 responder_resources; - u8 initiator_depth; - u8 target_ack_delay; - u8 failover_accepted; - u8 flow_control; - u8 rnr_retry_count; - u8 srq; -}; - -/** - * ib_send_cm_rep - Sends a connection reply in response to a connection - * request. - * @cm_id: Connection identifier that will be associated with the - * connection request. - * @param: Connection reply information needed to establish the - * connection. - */ -int ib_send_cm_rep(struct ib_cm_id *cm_id, - struct ib_cm_rep_param *param); - -/** - * ib_send_cm_rtu - Sends a connection ready to use message in response - * to a connection reply message. - * @cm_id: Connection identifier associated with the connection request. - * @private_data: Optional user-defined private data sent with the - * ready to use message. - * @private_data_len: Size of the private data buffer, in bytes. - */ -int ib_send_cm_rtu(struct ib_cm_id *cm_id, - const void *private_data, - u8 private_data_len); - -/** - * ib_send_cm_dreq - Sends a disconnection request for an existing - * connection. - * @cm_id: Connection identifier associated with the connection being - * released. - * @private_data: Optional user-defined private data sent with the - * disconnection request message. - * @private_data_len: Size of the private data buffer, in bytes. - */ -int ib_send_cm_dreq(struct ib_cm_id *cm_id, - const void *private_data, - u8 private_data_len); - -/** - * ib_send_cm_drep - Sends a disconnection reply to a disconnection request. - * @cm_id: Connection identifier associated with the connection being - * released. - * @private_data: Optional user-defined private data sent with the - * disconnection reply message. - * @private_data_len: Size of the private data buffer, in bytes. - * - * If the cm_id is in the correct state, the CM will transition the connection - * to the timewait state, even if an error occurs sending the DREP message. - */ -int ib_send_cm_drep(struct ib_cm_id *cm_id, - const void *private_data, - u8 private_data_len); - -/** - * ib_cm_establish - Forces a connection state to established. - * @cm_id: Connection identifier to transition to established. - * - * This routine should be invoked by users who receive messages on a - * connected QP before an RTU has been received. - */ -int ib_cm_establish(struct ib_cm_id *cm_id); - -/** - * ib_send_cm_rej - Sends a connection rejection message to the - * remote node. - * @cm_id: Connection identifier associated with the connection being - * rejected. - * @reason: Reason for the connection request rejection. - * @ari: Optional additional rejection information. - * @ari_length: Size of the additional rejection information, in bytes. - * @private_data: Optional user-defined private data sent with the - * rejection message. - * @private_data_len: Size of the private data buffer, in bytes. - */ -int ib_send_cm_rej(struct ib_cm_id *cm_id, - enum ib_cm_rej_reason reason, - void *ari, - u8 ari_length, - const void *private_data, - u8 private_data_len); - -/** - * ib_send_cm_mra - Sends a message receipt acknowledgement to a connection - * message. - * @cm_id: Connection identifier associated with the connection message. - * @service_timeout: The maximum time required for the sender to reply to - * to the connection message. - * @private_data: Optional user-defined private data sent with the - * message receipt acknowledgement. - * @private_data_len: Size of the private data buffer, in bytes. - */ -int ib_send_cm_mra(struct ib_cm_id *cm_id, - u8 service_timeout, - const void *private_data, - u8 private_data_len); - -/** - * ib_send_cm_lap - Sends a load alternate path request. - * @cm_id: Connection identifier associated with the load alternate path - * message. - * @alternate_path: A path record that identifies the alternate path to - * load. - * @private_data: Optional user-defined private data sent with the - * load alternate path message. - * @private_data_len: Size of the private data buffer, in bytes. - */ -int ib_send_cm_lap(struct ib_cm_id *cm_id, - struct ib_sa_path_rec *alternate_path, - const void *private_data, - u8 private_data_len); - -/** - * ib_cm_init_qp_attr - Initializes the QP attributes for use in transitioning - * to a specified QP state. - * @cm_id: Communication identifier associated with the QP attributes to - * initialize. - * @qp_attr: On input, specifies the desired QP state. On output, the - * mandatory and desired optional attributes will be set in order to - * modify the QP to the specified state. - * @qp_attr_mask: The QP attribute mask that may be used to transition the - * QP to the specified state. - * - * Users must set the @qp_attr->qp_state to the desired QP state. This call - * will set all required attributes for the given transition, along with - * known optional attributes. Users may override the attributes returned from - * this call before calling ib_modify_qp. - */ -int ib_cm_init_qp_attr(struct ib_cm_id *cm_id, - struct ib_qp_attr *qp_attr, - int *qp_attr_mask); - -/** - * ib_send_cm_apr - Sends an alternate path response message in response to - * a load alternate path request. - * @cm_id: Connection identifier associated with the alternate path response. - * @status: Reply status sent with the alternate path response. - * @info: Optional additional information sent with the alternate path - * response. - * @info_length: Size of the additional information, in bytes. - * @private_data: Optional user-defined private data sent with the - * alternate path response message. - * @private_data_len: Size of the private data buffer, in bytes. - */ -int ib_send_cm_apr(struct ib_cm_id *cm_id, - enum ib_cm_apr_status status, - void *info, - u8 info_length, - const void *private_data, - u8 private_data_len); - -struct ib_cm_sidr_req_param { - struct ib_sa_path_rec *path; - u64 service_id; - int timeout_ms; - const void *private_data; - u8 private_data_len; - u8 max_cm_retries; - u16 pkey; -}; - -/** - * ib_send_cm_sidr_req - Sends a service ID resolution request to the - * remote node. - * @cm_id: Communication identifier that will be associated with the - * service ID resolution request. - * @param: Service ID resolution request information. - */ -int ib_send_cm_sidr_req(struct ib_cm_id *cm_id, - struct ib_cm_sidr_req_param *param); - -struct ib_cm_sidr_rep_param { - u32 qp_num; - u32 qkey; - enum ib_cm_sidr_status status; - const void *info; - u8 info_length; - const void *private_data; - u8 private_data_len; -}; - -/** - * ib_send_cm_sidr_rep - Sends a service ID resolution request to the - * remote node. - * @cm_id: Communication identifier associated with the received service ID - * resolution request. - * @param: Service ID resolution reply information. - */ -int ib_send_cm_sidr_rep(struct ib_cm_id *cm_id, - struct ib_cm_sidr_rep_param *param); - -#endif /* IB_CM_H */ diff --git a/trunk/drivers/infiniband/include/ib_fmr_pool.h b/trunk/drivers/infiniband/include/ib_fmr_pool.h index 6c9e24d6e144..e8769657cbbb 100644 --- a/trunk/drivers/infiniband/include/ib_fmr_pool.h +++ b/trunk/drivers/infiniband/include/ib_fmr_pool.h @@ -1,6 +1,5 @@ /* * Copyright (c) 2004 Topspin Corporation. All rights reserved. - * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU @@ -30,7 +29,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: ib_fmr_pool.h 2730 2005-06-28 16:43:03Z sean.hefty $ + * $Id: ib_fmr_pool.h 1349 2004-12-16 21:09:43Z roland $ */ #if !defined(IB_FMR_POOL_H) @@ -79,7 +78,7 @@ struct ib_pool_fmr { struct ib_fmr_pool *ib_create_fmr_pool(struct ib_pd *pd, struct ib_fmr_pool_param *params); -void ib_destroy_fmr_pool(struct ib_fmr_pool *pool); +int ib_destroy_fmr_pool(struct ib_fmr_pool *pool); int ib_flush_fmr_pool(struct ib_fmr_pool *pool); diff --git a/trunk/drivers/infiniband/include/ib_mad.h b/trunk/drivers/infiniband/include/ib_mad.h index 491b6f25b3b8..4a6bf6763a97 100644 --- a/trunk/drivers/infiniband/include/ib_mad.h +++ b/trunk/drivers/infiniband/include/ib_mad.h @@ -33,14 +33,12 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: ib_mad.h 2775 2005-07-02 13:42:12Z halr $ + * $Id: ib_mad.h 1389 2004-12-27 22:56:47Z roland $ */ #if !defined( IB_MAD_H ) #define IB_MAD_H -#include - #include /* Management base version */ @@ -58,8 +56,6 @@ #define IB_MGMT_CLASS_VENDOR_RANGE2_START 0x30 #define IB_MGMT_CLASS_VENDOR_RANGE2_END 0x4F -#define IB_OPENIB_OUI (0x001405) - /* Management methods */ #define IB_MGMT_METHOD_GET 0x01 #define IB_MGMT_METHOD_SET 0x02 @@ -74,37 +70,18 @@ #define IB_MGMT_MAX_METHODS 128 -/* RMPP information */ -#define IB_MGMT_RMPP_VERSION 1 - -#define IB_MGMT_RMPP_TYPE_DATA 1 -#define IB_MGMT_RMPP_TYPE_ACK 2 -#define IB_MGMT_RMPP_TYPE_STOP 3 -#define IB_MGMT_RMPP_TYPE_ABORT 4 - -#define IB_MGMT_RMPP_FLAG_ACTIVE 1 -#define IB_MGMT_RMPP_FLAG_FIRST (1<<1) -#define IB_MGMT_RMPP_FLAG_LAST (1<<2) - -#define IB_MGMT_RMPP_NO_RESPTIME 0x1F - -#define IB_MGMT_RMPP_STATUS_SUCCESS 0 -#define IB_MGMT_RMPP_STATUS_RESX 1 -#define IB_MGMT_RMPP_STATUS_T2L 118 -#define IB_MGMT_RMPP_STATUS_BAD_LEN 119 -#define IB_MGMT_RMPP_STATUS_BAD_SEG 120 -#define IB_MGMT_RMPP_STATUS_BADT 121 -#define IB_MGMT_RMPP_STATUS_W2S 122 -#define IB_MGMT_RMPP_STATUS_S2B 123 -#define IB_MGMT_RMPP_STATUS_BAD_STATUS 124 -#define IB_MGMT_RMPP_STATUS_UNV 125 -#define IB_MGMT_RMPP_STATUS_TMR 126 -#define IB_MGMT_RMPP_STATUS_UNSPEC 127 - #define IB_QP0 0 #define IB_QP1 __constant_htonl(1) #define IB_QP1_QKEY 0x80010000 -#define IB_QP_SET_QKEY 0x80000000 + +struct ib_grh { + u32 version_tclass_flow; + u16 paylen; + u8 next_hdr; + u8 hop_limit; + union ib_gid sgid; + union ib_gid dgid; +} __attribute__ ((packed)); struct ib_mad_hdr { u8 base_version; @@ -117,7 +94,7 @@ struct ib_mad_hdr { u16 attr_id; u16 resv; u32 attr_mod; -}; +} __attribute__ ((packed)); struct ib_rmpp_hdr { u8 rmpp_version; @@ -126,41 +103,17 @@ struct ib_rmpp_hdr { u8 rmpp_status; u32 seg_num; u32 paylen_newwin; -}; - -typedef u64 __bitwise ib_sa_comp_mask; - -#define IB_SA_COMP_MASK(n) ((__force ib_sa_comp_mask) cpu_to_be64(1ull << n)) - -/* - * ib_sa_hdr and ib_sa_mad structures must be packed because they have - * 64-bit fields that are only 32-bit aligned. 64-bit architectures will - * lay them out wrong otherwise. (And unfortunately they are sent on - * the wire so we can't change the layout) - */ -struct ib_sa_hdr { - u64 sm_key; - u16 attr_offset; - u16 reserved; - ib_sa_comp_mask comp_mask; } __attribute__ ((packed)); struct ib_mad { struct ib_mad_hdr mad_hdr; u8 data[232]; -}; +} __attribute__ ((packed)); struct ib_rmpp_mad { struct ib_mad_hdr mad_hdr; struct ib_rmpp_hdr rmpp_hdr; u8 data[220]; -}; - -struct ib_sa_mad { - struct ib_mad_hdr mad_hdr; - struct ib_rmpp_hdr rmpp_hdr; - struct ib_sa_hdr sa_hdr; - u8 data[200]; } __attribute__ ((packed)); struct ib_vendor_mad { @@ -169,70 +122,7 @@ struct ib_vendor_mad { u8 reserved; u8 oui[3]; u8 data[216]; -}; - -/** - * ib_mad_send_buf - MAD data buffer and work request for sends. - * @mad: References an allocated MAD data buffer. The size of the data - * buffer is specified in the @send_wr.length field. - * @mapping: DMA mapping information. - * @mad_agent: MAD agent that allocated the buffer. - * @context: User-controlled context fields. - * @send_wr: An initialized work request structure used when sending the MAD. - * The wr_id field of the work request is initialized to reference this - * data structure. - * @sge: A scatter-gather list referenced by the work request. - * - * Users are responsible for initializing the MAD buffer itself, with the - * exception of specifying the payload length field in any RMPP MAD. - */ -struct ib_mad_send_buf { - struct ib_mad *mad; - DECLARE_PCI_UNMAP_ADDR(mapping) - struct ib_mad_agent *mad_agent; - void *context[2]; - struct ib_send_wr send_wr; - struct ib_sge sge; -}; - -/** - * ib_get_rmpp_resptime - Returns the RMPP response time. - * @rmpp_hdr: An RMPP header. - */ -static inline u8 ib_get_rmpp_resptime(struct ib_rmpp_hdr *rmpp_hdr) -{ - return rmpp_hdr->rmpp_rtime_flags >> 3; -} - -/** - * ib_get_rmpp_flags - Returns the RMPP flags. - * @rmpp_hdr: An RMPP header. - */ -static inline u8 ib_get_rmpp_flags(struct ib_rmpp_hdr *rmpp_hdr) -{ - return rmpp_hdr->rmpp_rtime_flags & 0x7; -} - -/** - * ib_set_rmpp_resptime - Sets the response time in an RMPP header. - * @rmpp_hdr: An RMPP header. - * @rtime: The response time to set. - */ -static inline void ib_set_rmpp_resptime(struct ib_rmpp_hdr *rmpp_hdr, u8 rtime) -{ - rmpp_hdr->rmpp_rtime_flags = ib_get_rmpp_flags(rmpp_hdr) | (rtime << 3); -} - -/** - * ib_set_rmpp_flags - Sets the flags in an RMPP header. - * @rmpp_hdr: An RMPP header. - * @flags: The flags to set. - */ -static inline void ib_set_rmpp_flags(struct ib_rmpp_hdr *rmpp_hdr, u8 flags) -{ - rmpp_hdr->rmpp_rtime_flags = (rmpp_hdr->rmpp_rtime_flags & 0xF1) | - (flags & 0x7); -} +} __attribute__ ((packed)); struct ib_mad_agent; struct ib_mad_send_wc; @@ -278,7 +168,6 @@ typedef void (*ib_mad_recv_handler)(struct ib_mad_agent *mad_agent, * ib_mad_agent - Used to track MAD registration with the access layer. * @device: Reference to device registration is on. * @qp: Reference to QP used for sending and receiving MADs. - * @mr: Memory region for system memory usable for DMA. * @recv_handler: Callback handler for a received MAD. * @send_handler: Callback handler for a sent MAD. * @snoop_handler: Callback handler for snooped sent MADs. @@ -287,19 +176,16 @@ typedef void (*ib_mad_recv_handler)(struct ib_mad_agent *mad_agent, * Unsolicited MADs sent by this client will have the upper 32-bits * of their TID set to this value. * @port_num: Port number on which QP is registered - * @rmpp_version: If set, indicates the RMPP version used by this agent. */ struct ib_mad_agent { struct ib_device *device; struct ib_qp *qp; - struct ib_mr *mr; ib_mad_recv_handler recv_handler; ib_mad_send_handler send_handler; ib_mad_snoop_handler snoop_handler; void *context; u32 hi_tid; u8 port_num; - u8 rmpp_version; }; /** @@ -333,7 +219,6 @@ struct ib_mad_recv_buf { * ib_mad_recv_wc - received MAD information. * @wc: Completion information for the received data. * @recv_buf: Specifies the location of the received data buffer(s). - * @rmpp_list: Specifies a list of RMPP reassembled received MAD buffers. * @mad_len: The length of the received MAD, without duplicated headers. * * For received response, the wr_id field of the wc is set to the wr_id @@ -342,7 +227,6 @@ struct ib_mad_recv_buf { struct ib_mad_recv_wc { struct ib_wc *wc; struct ib_mad_recv_buf recv_buf; - struct list_head rmpp_list; int mad_len; }; @@ -438,16 +322,6 @@ int ib_unregister_mad_agent(struct ib_mad_agent *mad_agent); * @bad_send_wr: Specifies the MAD on which an error was encountered. * * Sent MADs are not guaranteed to complete in the order that they were posted. - * - * If the MAD requires RMPP, the data buffer should contain a single copy - * of the common MAD, RMPP, and class specific headers, followed by the class - * defined data. If the class defined data would not divide evenly into - * RMPP segments, then space must be allocated at the end of the referenced - * buffer for any required padding. To indicate the amount of class defined - * data being transferred, the paylen_newwin field in the RMPP header should - * be set to the size of the class specific header plus the amount of class - * defined data being transferred. The paylen_newwin field should be - * specified in network-byte order. */ int ib_post_send_mad(struct ib_mad_agent *mad_agent, struct ib_send_wr *send_wr, @@ -460,13 +334,15 @@ int ib_post_send_mad(struct ib_mad_agent *mad_agent, * referenced buffer should be at least the size of the mad_len specified * by @mad_recv_wc. * - * This call copies a chain of received MAD segments into a single data buffer, + * This call copies a chain of received RMPP MADs into a single data buffer, * removing duplicated headers. */ -void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc, void *buf); +void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc, + void *buf); /** - * ib_free_recv_mad - Returns data buffers used to receive a MAD. + * ib_free_recv_mad - Returns data buffers used to receive a MAD to the + * access layer. * @mad_recv_wc: Work completion information for a received MAD. * * Clients receiving MADs through their ib_mad_recv_handler must call this @@ -482,18 +358,8 @@ void ib_free_recv_mad(struct ib_mad_recv_wc *mad_recv_wc); * MADs will be returned to the user through the corresponding * ib_mad_send_handler. */ -void ib_cancel_mad(struct ib_mad_agent *mad_agent, u64 wr_id); - -/** - * ib_modify_mad - Modifies an outstanding send MAD operation. - * @mad_agent: Specifies the registration associated with sent MAD. - * @wr_id: Indicates the work request identifier of the MAD to modify. - * @timeout_ms: New timeout value for sent MAD. - * - * This call will reset the timeout value for a sent MAD to the specified - * value. - */ -int ib_modify_mad(struct ib_mad_agent *mad_agent, u64 wr_id, u32 timeout_ms); +void ib_cancel_mad(struct ib_mad_agent *mad_agent, + u64 wr_id); /** * ib_redirect_mad_qp - Registers a QP for MAD services. @@ -535,43 +401,4 @@ struct ib_mad_agent *ib_redirect_mad_qp(struct ib_qp *qp, int ib_process_mad_wc(struct ib_mad_agent *mad_agent, struct ib_wc *wc); -/** - * ib_create_send_mad - Allocate and initialize a data buffer and work request - * for sending a MAD. - * @mad_agent: Specifies the registered MAD service to associate with the MAD. - * @remote_qpn: Specifies the QPN of the receiving node. - * @pkey_index: Specifies which PKey the MAD will be sent using. This field - * is valid only if the remote_qpn is QP 1. - * @ah: References the address handle used to transfer to the remote node. - * @rmpp_active: Indicates if the send will enable RMPP. - * @hdr_len: Indicates the size of the data header of the MAD. This length - * should include the common MAD header, RMPP header, plus any class - * specific header. - * @data_len: Indicates the size of any user-transferred data. The call will - * automatically adjust the allocated buffer size to account for any - * additional padding that may be necessary. - * @gfp_mask: GFP mask used for the memory allocation. - * - * This is a helper routine that may be used to allocate a MAD. Users are - * not required to allocate outbound MADs using this call. The returned - * MAD send buffer will reference a data buffer usable for sending a MAD, along - * with an initialized work request structure. Users may modify the returned - * MAD data buffer or work request before posting the send. - * - * The returned data buffer will be cleared. Users are responsible for - * initializing the common MAD and any class specific headers. If @rmpp_active - * is set, the RMPP header will be initialized for sending. - */ -struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent, - u32 remote_qpn, u16 pkey_index, - struct ib_ah *ah, int rmpp_active, - int hdr_len, int data_len, - unsigned int __nocast gfp_mask); - -/** - * ib_free_send_mad - Returns data buffers used to send a MAD. - * @send_buf: Previously allocated send data buffer. - */ -void ib_free_send_mad(struct ib_mad_send_buf *send_buf); - #endif /* IB_MAD_H */ diff --git a/trunk/drivers/infiniband/include/ib_sa.h b/trunk/drivers/infiniband/include/ib_sa.h index 6d999f7b5d93..00222285eb9a 100644 --- a/trunk/drivers/infiniband/include/ib_sa.h +++ b/trunk/drivers/infiniband/include/ib_sa.h @@ -1,6 +1,5 @@ /* * Copyright (c) 2004 Topspin Communications. All rights reserved. - * Copyright (c) 2005 Voltaire, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU @@ -30,7 +29,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: ib_sa.h 2811 2005-07-06 18:11:43Z halr $ + * $Id: ib_sa.h 1389 2004-12-27 22:56:47Z roland $ */ #ifndef IB_SA_H @@ -42,11 +41,9 @@ #include enum { - IB_SA_CLASS_VERSION = 2, /* IB spec version 1.1/1.2 */ + IB_SA_CLASS_VERSION = 2, /* IB spec version 1.1/1.2 */ - IB_SA_METHOD_GET_TABLE = 0x12, - IB_SA_METHOD_GET_TABLE_RESP = 0x92, - IB_SA_METHOD_DELETE = 0x15 + IB_SA_METHOD_DELETE = 0x15 }; enum ib_sa_selector { @@ -90,6 +87,10 @@ static inline int ib_sa_rate_enum_to_int(enum ib_sa_rate rate) } } +typedef u64 __bitwise ib_sa_comp_mask; + +#define IB_SA_COMP_MASK(n) ((__force ib_sa_comp_mask) cpu_to_be64(1ull << n)) + /* * Structures for SA records are named "struct ib_sa_xxx_rec." No * attempt is made to pack structures to match the physical layout of @@ -194,61 +195,6 @@ struct ib_sa_mcmember_rec { int proxy_join; }; -/* Service Record Component Mask Sec 15.2.5.14 Ver 1.1 */ -#define IB_SA_SERVICE_REC_SERVICE_ID IB_SA_COMP_MASK( 0) -#define IB_SA_SERVICE_REC_SERVICE_GID IB_SA_COMP_MASK( 1) -#define IB_SA_SERVICE_REC_SERVICE_PKEY IB_SA_COMP_MASK( 2) -/* reserved: 3 */ -#define IB_SA_SERVICE_REC_SERVICE_LEASE IB_SA_COMP_MASK( 4) -#define IB_SA_SERVICE_REC_SERVICE_KEY IB_SA_COMP_MASK( 5) -#define IB_SA_SERVICE_REC_SERVICE_NAME IB_SA_COMP_MASK( 6) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_0 IB_SA_COMP_MASK( 7) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_1 IB_SA_COMP_MASK( 8) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_2 IB_SA_COMP_MASK( 9) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_3 IB_SA_COMP_MASK(10) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_4 IB_SA_COMP_MASK(11) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_5 IB_SA_COMP_MASK(12) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_6 IB_SA_COMP_MASK(13) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_7 IB_SA_COMP_MASK(14) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_8 IB_SA_COMP_MASK(15) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_9 IB_SA_COMP_MASK(16) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_10 IB_SA_COMP_MASK(17) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_11 IB_SA_COMP_MASK(18) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_12 IB_SA_COMP_MASK(19) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_13 IB_SA_COMP_MASK(20) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_14 IB_SA_COMP_MASK(21) -#define IB_SA_SERVICE_REC_SERVICE_DATA8_15 IB_SA_COMP_MASK(22) -#define IB_SA_SERVICE_REC_SERVICE_DATA16_0 IB_SA_COMP_MASK(23) -#define IB_SA_SERVICE_REC_SERVICE_DATA16_1 IB_SA_COMP_MASK(24) -#define IB_SA_SERVICE_REC_SERVICE_DATA16_2 IB_SA_COMP_MASK(25) -#define IB_SA_SERVICE_REC_SERVICE_DATA16_3 IB_SA_COMP_MASK(26) -#define IB_SA_SERVICE_REC_SERVICE_DATA16_4 IB_SA_COMP_MASK(27) -#define IB_SA_SERVICE_REC_SERVICE_DATA16_5 IB_SA_COMP_MASK(28) -#define IB_SA_SERVICE_REC_SERVICE_DATA16_6 IB_SA_COMP_MASK(29) -#define IB_SA_SERVICE_REC_SERVICE_DATA16_7 IB_SA_COMP_MASK(30) -#define IB_SA_SERVICE_REC_SERVICE_DATA32_0 IB_SA_COMP_MASK(31) -#define IB_SA_SERVICE_REC_SERVICE_DATA32_1 IB_SA_COMP_MASK(32) -#define IB_SA_SERVICE_REC_SERVICE_DATA32_2 IB_SA_COMP_MASK(33) -#define IB_SA_SERVICE_REC_SERVICE_DATA32_3 IB_SA_COMP_MASK(34) -#define IB_SA_SERVICE_REC_SERVICE_DATA64_0 IB_SA_COMP_MASK(35) -#define IB_SA_SERVICE_REC_SERVICE_DATA64_1 IB_SA_COMP_MASK(36) - -#define IB_DEFAULT_SERVICE_LEASE 0xFFFFFFFF - -struct ib_sa_service_rec { - u64 id; - union ib_gid gid; - u16 pkey; - /* reserved */ - u32 lease; - u8 key[16]; - u8 name[64]; - u8 data8[16]; - u16 data16[8]; - u32 data32[4]; - u64 data64[2]; -}; - struct ib_sa_query; void ib_sa_cancel_query(int id, struct ib_sa_query *query); @@ -256,7 +202,7 @@ void ib_sa_cancel_query(int id, struct ib_sa_query *query); int ib_sa_path_rec_get(struct ib_device *device, u8 port_num, struct ib_sa_path_rec *rec, ib_sa_comp_mask comp_mask, - int timeout_ms, unsigned int __nocast gfp_mask, + int timeout_ms, int gfp_mask, void (*callback)(int status, struct ib_sa_path_rec *resp, void *context), @@ -267,24 +213,13 @@ int ib_sa_mcmember_rec_query(struct ib_device *device, u8 port_num, u8 method, struct ib_sa_mcmember_rec *rec, ib_sa_comp_mask comp_mask, - int timeout_ms, unsigned int __nocast gfp_mask, + int timeout_ms, int gfp_mask, void (*callback)(int status, struct ib_sa_mcmember_rec *resp, void *context), void *context, struct ib_sa_query **query); -int ib_sa_service_rec_query(struct ib_device *device, u8 port_num, - u8 method, - struct ib_sa_service_rec *rec, - ib_sa_comp_mask comp_mask, - int timeout_ms, unsigned int __nocast gfp_mask, - void (*callback)(int status, - struct ib_sa_service_rec *resp, - void *context), - void *context, - struct ib_sa_query **sa_query); - /** * ib_sa_mcmember_rec_set - Start an MCMember set query * @device:device to send query on @@ -313,7 +248,7 @@ static inline int ib_sa_mcmember_rec_set(struct ib_device *device, u8 port_num, struct ib_sa_mcmember_rec *rec, ib_sa_comp_mask comp_mask, - int timeout_ms, unsigned int __nocast gfp_mask, + int timeout_ms, int gfp_mask, void (*callback)(int status, struct ib_sa_mcmember_rec *resp, void *context), @@ -355,7 +290,7 @@ static inline int ib_sa_mcmember_rec_delete(struct ib_device *device, u8 port_num, struct ib_sa_mcmember_rec *rec, ib_sa_comp_mask comp_mask, - int timeout_ms, unsigned int __nocast gfp_mask, + int timeout_ms, int gfp_mask, void (*callback)(int status, struct ib_sa_mcmember_rec *resp, void *context), diff --git a/trunk/drivers/infiniband/include/ib_user_cm.h b/trunk/drivers/infiniband/include/ib_user_cm.h deleted file mode 100644 index 500b1af6ff77..000000000000 --- a/trunk/drivers/infiniband/include/ib_user_cm.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright (c) 2005 Topspin Communications. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * $Id: ib_user_cm.h 2576 2005-06-09 17:00:30Z libor $ - */ - -#ifndef IB_USER_CM_H -#define IB_USER_CM_H - -#include - -#define IB_USER_CM_ABI_VERSION 1 - -enum { - IB_USER_CM_CMD_CREATE_ID, - IB_USER_CM_CMD_DESTROY_ID, - IB_USER_CM_CMD_ATTR_ID, - - IB_USER_CM_CMD_LISTEN, - IB_USER_CM_CMD_ESTABLISH, - - IB_USER_CM_CMD_SEND_REQ, - IB_USER_CM_CMD_SEND_REP, - IB_USER_CM_CMD_SEND_RTU, - IB_USER_CM_CMD_SEND_DREQ, - IB_USER_CM_CMD_SEND_DREP, - IB_USER_CM_CMD_SEND_REJ, - IB_USER_CM_CMD_SEND_MRA, - IB_USER_CM_CMD_SEND_LAP, - IB_USER_CM_CMD_SEND_APR, - IB_USER_CM_CMD_SEND_SIDR_REQ, - IB_USER_CM_CMD_SEND_SIDR_REP, - - IB_USER_CM_CMD_EVENT, -}; -/* - * command ABI structures. - */ -struct ib_ucm_cmd_hdr { - __u32 cmd; - __u16 in; - __u16 out; -}; - -struct ib_ucm_create_id { - __u64 response; -}; - -struct ib_ucm_create_id_resp { - __u32 id; -}; - -struct ib_ucm_destroy_id { - __u32 id; -}; - -struct ib_ucm_attr_id { - __u64 response; - __u32 id; -}; - -struct ib_ucm_attr_id_resp { - __u64 service_id; - __u64 service_mask; - __u32 local_id; - __u32 remote_id; -}; - -struct ib_ucm_listen { - __u64 service_id; - __u64 service_mask; - __u32 id; -}; - -struct ib_ucm_establish { - __u32 id; -}; - -struct ib_ucm_private_data { - __u64 data; - __u32 id; - __u8 len; - __u8 reserved[3]; -}; - -struct ib_ucm_path_rec { - __u8 dgid[16]; - __u8 sgid[16]; - __u16 dlid; - __u16 slid; - __u32 raw_traffic; - __u32 flow_label; - __u32 reversible; - __u32 mtu; - __u16 pkey; - __u8 hop_limit; - __u8 traffic_class; - __u8 numb_path; - __u8 sl; - __u8 mtu_selector; - __u8 rate_selector; - __u8 rate; - __u8 packet_life_time_selector; - __u8 packet_life_time; - __u8 preference; -}; - -struct ib_ucm_req { - __u32 id; - __u32 qpn; - __u32 qp_type; - __u32 psn; - __u64 sid; - __u64 data; - __u64 primary_path; - __u64 alternate_path; - __u8 len; - __u8 peer_to_peer; - __u8 responder_resources; - __u8 initiator_depth; - __u8 remote_cm_response_timeout; - __u8 flow_control; - __u8 local_cm_response_timeout; - __u8 retry_count; - __u8 rnr_retry_count; - __u8 max_cm_retries; - __u8 srq; - __u8 reserved[1]; -}; - -struct ib_ucm_rep { - __u64 data; - __u32 id; - __u32 qpn; - __u32 psn; - __u8 len; - __u8 responder_resources; - __u8 initiator_depth; - __u8 target_ack_delay; - __u8 failover_accepted; - __u8 flow_control; - __u8 rnr_retry_count; - __u8 srq; -}; - -struct ib_ucm_info { - __u32 id; - __u32 status; - __u64 info; - __u64 data; - __u8 info_len; - __u8 data_len; - __u8 reserved[2]; -}; - -struct ib_ucm_mra { - __u64 data; - __u32 id; - __u8 len; - __u8 timeout; - __u8 reserved[2]; -}; - -struct ib_ucm_lap { - __u64 path; - __u64 data; - __u32 id; - __u8 len; - __u8 reserved[3]; -}; - -struct ib_ucm_sidr_req { - __u32 id; - __u32 timeout; - __u64 sid; - __u64 data; - __u64 path; - __u16 pkey; - __u8 len; - __u8 max_cm_retries; -}; - -struct ib_ucm_sidr_rep { - __u32 id; - __u32 qpn; - __u32 qkey; - __u32 status; - __u64 info; - __u64 data; - __u8 info_len; - __u8 data_len; - __u8 reserved[2]; -}; -/* - * event notification ABI structures. - */ -struct ib_ucm_event_get { - __u64 response; - __u64 data; - __u64 info; - __u8 data_len; - __u8 info_len; - __u8 reserved[2]; -}; - -struct ib_ucm_req_event_resp { - __u32 listen_id; - /* device */ - /* port */ - struct ib_ucm_path_rec primary_path; - struct ib_ucm_path_rec alternate_path; - __u64 remote_ca_guid; - __u32 remote_qkey; - __u32 remote_qpn; - __u32 qp_type; - __u32 starting_psn; - __u8 responder_resources; - __u8 initiator_depth; - __u8 local_cm_response_timeout; - __u8 flow_control; - __u8 remote_cm_response_timeout; - __u8 retry_count; - __u8 rnr_retry_count; - __u8 srq; -}; - -struct ib_ucm_rep_event_resp { - __u64 remote_ca_guid; - __u32 remote_qkey; - __u32 remote_qpn; - __u32 starting_psn; - __u8 responder_resources; - __u8 initiator_depth; - __u8 target_ack_delay; - __u8 failover_accepted; - __u8 flow_control; - __u8 rnr_retry_count; - __u8 srq; - __u8 reserved[1]; -}; - -struct ib_ucm_rej_event_resp { - __u32 reason; - /* ari in ib_ucm_event_get info field. */ -}; - -struct ib_ucm_mra_event_resp { - __u8 timeout; - __u8 reserved[3]; -}; - -struct ib_ucm_lap_event_resp { - struct ib_ucm_path_rec path; -}; - -struct ib_ucm_apr_event_resp { - __u32 status; - /* apr info in ib_ucm_event_get info field. */ -}; - -struct ib_ucm_sidr_req_event_resp { - __u32 listen_id; - /* device */ - /* port */ - __u16 pkey; - __u8 reserved[2]; -}; - -struct ib_ucm_sidr_rep_event_resp { - __u32 status; - __u32 qkey; - __u32 qpn; - /* info in ib_ucm_event_get info field. */ -}; - -#define IB_UCM_PRES_DATA 0x01 -#define IB_UCM_PRES_INFO 0x02 -#define IB_UCM_PRES_PRIMARY 0x04 -#define IB_UCM_PRES_ALTERNATE 0x08 - -struct ib_ucm_event_resp { - __u32 id; - __u32 event; - __u32 present; - union { - struct ib_ucm_req_event_resp req_resp; - struct ib_ucm_rep_event_resp rep_resp; - struct ib_ucm_rej_event_resp rej_resp; - struct ib_ucm_mra_event_resp mra_resp; - struct ib_ucm_lap_event_resp lap_resp; - struct ib_ucm_apr_event_resp apr_resp; - - struct ib_ucm_sidr_req_event_resp sidr_req_resp; - struct ib_ucm_sidr_rep_event_resp sidr_rep_resp; - - __u32 send_status; - } u; -}; - -#endif /* IB_USER_CM_H */ diff --git a/trunk/drivers/infiniband/include/ib_user_mad.h b/trunk/drivers/infiniband/include/ib_user_mad.h index a9a56b50aacc..06ad4a6075fa 100644 --- a/trunk/drivers/infiniband/include/ib_user_mad.h +++ b/trunk/drivers/infiniband/include/ib_user_mad.h @@ -1,6 +1,5 @@ /* * Copyright (c) 2004 Topspin Communications. All rights reserved. - * Copyright (c) 2005 Voltaire, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU @@ -30,7 +29,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: ib_user_mad.h 2814 2005-07-06 19:14:09Z halr $ + * $Id: ib_user_mad.h 1389 2004-12-27 22:56:47Z roland $ */ #ifndef IB_USER_MAD_H @@ -43,7 +42,7 @@ * Increment this value if any changes that break userspace ABI * compatibility are made. */ -#define IB_USER_MAD_ABI_VERSION 5 +#define IB_USER_MAD_ABI_VERSION 2 /* * Make sure that all structs defined in this file remain laid out so @@ -52,13 +51,13 @@ */ /** - * ib_user_mad_hdr - MAD packet header + * ib_user_mad - MAD packet + * @data - Contents of MAD * @id - ID of agent MAD received with/to be sent with * @status - 0 on successful receive, ETIMEDOUT if no response * received (transaction ID in data[] will be set to TID of original * request) (ignored on send) * @timeout_ms - Milliseconds to wait for response (unset on receive) - * @retries - Number of automatic retries to attempt * @qpn - Remote QP number received from/to be sent to * @qkey - Remote Q_Key to be sent with (unset on receive) * @lid - Remote lid received from/to be sent to @@ -73,12 +72,11 @@ * * All multi-byte quantities are stored in network (big endian) byte order. */ -struct ib_user_mad_hdr { +struct ib_user_mad { + __u8 data[256]; __u32 id; __u32 status; __u32 timeout_ms; - __u32 retries; - __u32 length; __u32 qpn; __u32 qkey; __u16 lid; @@ -92,17 +90,6 @@ struct ib_user_mad_hdr { __u32 flow_label; }; -/** - * ib_user_mad - MAD packet - * @hdr - MAD packet header - * @data - Contents of MAD - * - */ -struct ib_user_mad { - struct ib_user_mad_hdr hdr; - __u8 data[0]; -}; - /** * ib_user_mad_reg_req - MAD registration request * @id - Set by the kernel; used to identify agent in future requests. @@ -116,8 +103,6 @@ struct ib_user_mad { * management class to receive. * @oui: Indicates IEEE OUI when mgmt_class is a vendor class * in the range from 0x30 to 0x4f. Otherwise not used. - * @rmpp_version: If set, indicates the RMPP version used. - * */ struct ib_user_mad_reg_req { __u32 id; @@ -126,7 +111,6 @@ struct ib_user_mad_reg_req { __u8 mgmt_class; __u8 mgmt_class_version; __u8 oui[3]; - __u8 rmpp_version; }; #define IB_IOCTL_MAGIC 0x1b diff --git a/trunk/drivers/infiniband/include/ib_verbs.h b/trunk/drivers/infiniband/include/ib_verbs.h index 5d24edaa66e6..e5bd9a10c201 100644 --- a/trunk/drivers/infiniband/include/ib_verbs.h +++ b/trunk/drivers/infiniband/include/ib_verbs.h @@ -289,15 +289,6 @@ struct ib_global_route { u8 traffic_class; }; -struct ib_grh { - u32 version_tclass_flow; - u16 paylen; - u8 next_hdr; - u8 hop_limit; - union ib_gid sgid; - union ib_gid dgid; -}; - enum { IB_MULTICAST_QPN = 0xffffff }; @@ -575,7 +566,6 @@ struct ib_send_wr { u32 remote_qpn; u32 remote_qkey; int timeout_ms; /* valid for MADs only */ - int retries; /* valid for MADs only */ u16 pkey_index; /* valid for GSI only */ u8 port_num; /* valid for DR SMPs on switch only */ } ud; @@ -999,21 +989,6 @@ int ib_dealloc_pd(struct ib_pd *pd); */ struct ib_ah *ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); -/** - * ib_create_ah_from_wc - Creates an address handle associated with the - * sender of the specified work completion. - * @pd: The protection domain associated with the address handle. - * @wc: Work completion information associated with a received message. - * @grh: References the received global route header. This parameter is - * ignored unless the work completion indicates that the GRH is valid. - * @port_num: The outbound port number to associate with the address. - * - * The address handle is used to reference a local or global destination - * in all UD QP post sends. - */ -struct ib_ah *ib_create_ah_from_wc(struct ib_pd *pd, struct ib_wc *wc, - struct ib_grh *grh, u8 port_num); - /** * ib_modify_ah - Modifies the address vector associated with an address * handle. diff --git a/trunk/drivers/isdn/hisax/avm_a1.c b/trunk/drivers/isdn/hisax/avm_a1.c index 9a8b02557ff9..8f028d42fd2f 100644 --- a/trunk/drivers/isdn/hisax/avm_a1.c +++ b/trunk/drivers/isdn/hisax/avm_a1.c @@ -135,7 +135,7 @@ avm_a1_interrupt(int intno, void *dev_id, struct pt_regs *regs) return IRQ_HANDLED; } -static inline void +inline static void release_ioregs(struct IsdnCardState *cs, int mask) { release_region(cs->hw.avm.cfg_reg, 8); diff --git a/trunk/drivers/isdn/hisax/config.c b/trunk/drivers/isdn/hisax/config.c index fbaab4352902..c542e6fb2bde 100644 --- a/trunk/drivers/isdn/hisax/config.c +++ b/trunk/drivers/isdn/hisax/config.c @@ -1900,7 +1900,6 @@ static struct pci_device_id hisax_pci_tbl[] __initdata = { {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_R685, PCI_ANY_ID, PCI_ANY_ID}, {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_R753, PCI_ANY_ID, PCI_ANY_ID}, {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_DJINN_ITOO, PCI_ANY_ID, PCI_ANY_ID}, - {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_OLITEC, PCI_ANY_ID, PCI_ANY_ID}, #endif #ifdef CONFIG_HISAX_QUADRO {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_ANY_ID, PCI_ANY_ID}, diff --git a/trunk/drivers/isdn/hisax/gazel.c b/trunk/drivers/isdn/hisax/gazel.c index 60b04c6d9e7d..352b45ac5347 100644 --- a/trunk/drivers/isdn/hisax/gazel.c +++ b/trunk/drivers/isdn/hisax/gazel.c @@ -546,9 +546,8 @@ setup_gazelpci(struct IsdnCardState *cs) found = 0; seekcard = PCI_DEVICE_ID_PLX_R685; - for (nbseek = 0; nbseek < 4; nbseek++) { - if ((dev_tel = pci_find_device(PCI_VENDOR_ID_PLX, - seekcard, dev_tel))) { + for (nbseek = 0; nbseek < 3; nbseek++) { + if ((dev_tel = pci_find_device(PCI_VENDOR_ID_PLX, seekcard, dev_tel))) { if (pci_enable_device(dev_tel)) return 1; pci_irq = dev_tel->irq; @@ -566,9 +565,6 @@ setup_gazelpci(struct IsdnCardState *cs) case PCI_DEVICE_ID_PLX_R753: seekcard = PCI_DEVICE_ID_PLX_DJINN_ITOO; break; - case PCI_DEVICE_ID_PLX_DJINN_ITOO: - seekcard = PCI_DEVICE_ID_PLX_OLITEC; - break; } } } @@ -609,7 +605,6 @@ setup_gazelpci(struct IsdnCardState *cs) break; case PCI_DEVICE_ID_PLX_R753: case PCI_DEVICE_ID_PLX_DJINN_ITOO: - case PCI_DEVICE_ID_PLX_OLITEC: printk(KERN_INFO "Gazel: Card PCI R753 found\n"); cs->subtyp = R753; test_and_set_bit(HW_IPAC, &cs->HW_Flags); diff --git a/trunk/drivers/isdn/hisax/isdnl2.c b/trunk/drivers/isdn/hisax/isdnl2.c index 6d0431725555..1615c1a76ab8 100644 --- a/trunk/drivers/isdn/hisax/isdnl2.c +++ b/trunk/drivers/isdn/hisax/isdnl2.c @@ -213,7 +213,7 @@ sethdraddr(struct Layer2 *l2, u_char * header, int rsp) } } -static inline void +inline static void enqueue_super(struct PStack *st, struct sk_buff *skb) { diff --git a/trunk/drivers/isdn/hisax/l3dss1.c b/trunk/drivers/isdn/hisax/l3dss1.c index e96845cdd4f6..a6d2abdb478a 100644 --- a/trunk/drivers/isdn/hisax/l3dss1.c +++ b/trunk/drivers/isdn/hisax/l3dss1.c @@ -353,7 +353,7 @@ l3dss1_parse_facility(struct PStack *st, struct l3_process *pc, { l3dss1_dummy_invoke(st, cr, id, ident, p, nlen); return; } -#ifdef HISAX_DE_AOC +#if HISAX_DE_AOC { #define FOO1(s,a,b) \ @@ -977,7 +977,7 @@ l3dss1_release_cmpl(struct l3_process *pc, u_char pr, void *arg) dss1_release_l3_process(pc); } -#ifdef EXT_BEARER_CAPS +#if EXT_BEARER_CAPS static u_char * EncodeASyncParams(u_char * p, u_char si2) @@ -1369,7 +1369,7 @@ l3dss1_setup_req(struct l3_process *pc, u_char pr, *p++ = *sub++ & 0x7f; } } -#ifdef EXT_BEARER_CAPS +#if EXT_BEARER_CAPS if ((pc->para.setup.si2 >= 160) && (pc->para.setup.si2 <= 175)) { // sync. Bitratenadaption, V.110/X.30 *p++ = IE_LLC; @@ -1609,7 +1609,7 @@ l3dss1_setup(struct l3_process *pc, u_char pr, void *arg) case 0x08: /* Unrestricted digital information */ pc->para.setup.si1 = 7; /* JIM, 05.11.97 I wanna set service indicator 2 */ -#ifdef EXT_BEARER_CAPS +#if EXT_BEARER_CAPS pc->para.setup.si2 = DecodeSI2(skb); #endif break; diff --git a/trunk/drivers/isdn/hisax/teles3.c b/trunk/drivers/isdn/hisax/teles3.c index a3eaf4d65707..adeaad62d35c 100644 --- a/trunk/drivers/isdn/hisax/teles3.c +++ b/trunk/drivers/isdn/hisax/teles3.c @@ -143,7 +143,7 @@ teles3_interrupt(int intno, void *dev_id, struct pt_regs *regs) return IRQ_HANDLED; } -static inline void +inline static void release_ioregs(struct IsdnCardState *cs, int mask) { if (mask & 1) diff --git a/trunk/drivers/macintosh/Kconfig b/trunk/drivers/macintosh/Kconfig index 65ab64c43b3e..91691a6c004e 100644 --- a/trunk/drivers/macintosh/Kconfig +++ b/trunk/drivers/macintosh/Kconfig @@ -4,7 +4,7 @@ menu "Macintosh device drivers" config ADB bool "Apple Desktop Bus (ADB) support" - depends on MAC || (PPC_PMAC && PPC32) + depends on MAC || PPC_PMAC help Apple Desktop Bus (ADB) support is for support of devices which are connected to an ADB port. ADB devices tend to have 4 pins. diff --git a/trunk/drivers/md/bitmap.c b/trunk/drivers/md/bitmap.c index 70bca955e0de..0c2ed99a3832 100644 --- a/trunk/drivers/md/bitmap.c +++ b/trunk/drivers/md/bitmap.c @@ -108,7 +108,7 @@ static unsigned char *bitmap_alloc_page(struct bitmap *bitmap) { unsigned char *page; -#ifdef INJECT_FAULTS_1 +#if INJECT_FAULTS_1 page = NULL; #else page = kmalloc(PAGE_SIZE, GFP_NOIO); @@ -843,7 +843,7 @@ static int bitmap_init_from_disk(struct bitmap *bitmap, int in_sync) BUG_ON(!file && !bitmap->offset); -#ifdef INJECT_FAULTS_3 +#if INJECT_FAULTS_3 outofdate = 1; #else outofdate = bitmap->flags & BITMAP_STALE; @@ -1187,7 +1187,7 @@ static int bitmap_start_daemon(struct bitmap *bitmap, mdk_thread_t **ptr, spin_unlock_irqrestore(&bitmap->lock, flags); -#ifdef INJECT_FATAL_FAULT_2 +#if INJECT_FATAL_FAULT_2 daemon = NULL; #else sprintf(namebuf, "%%s_%s", name); @@ -1552,7 +1552,7 @@ int bitmap_create(mddev_t *mddev) bitmap->syncchunk = ~0UL; -#ifdef INJECT_FATAL_FAULT_1 +#if INJECT_FATAL_FAULT_1 bitmap->bp = NULL; #else bitmap->bp = kmalloc(pages * sizeof(*bitmap->bp), GFP_KERNEL); diff --git a/trunk/drivers/md/md.c b/trunk/drivers/md/md.c index 6580e0fa4a47..4a0c57db2b67 100644 --- a/trunk/drivers/md/md.c +++ b/trunk/drivers/md/md.c @@ -284,7 +284,7 @@ static mdk_rdev_t * find_rdev(mddev_t * mddev, dev_t dev) return NULL; } -static inline sector_t calc_dev_sboffset(struct block_device *bdev) +inline static sector_t calc_dev_sboffset(struct block_device *bdev) { sector_t size = bdev->bd_inode->i_size >> BLOCK_SIZE_BITS; return MD_NEW_SIZE_BLOCKS(size); diff --git a/trunk/drivers/md/raid1.c b/trunk/drivers/md/raid1.c index d3a64a04a6d8..5f253ee536bb 100644 --- a/trunk/drivers/md/raid1.c +++ b/trunk/drivers/md/raid1.c @@ -1468,7 +1468,6 @@ static int raid1_resize(mddev_t *mddev, sector_t sectors) set_bit(MD_RECOVERY_NEEDED, &mddev->recovery); } mddev->size = mddev->array_size; - mddev->resync_max_sectors = sectors; return 0; } diff --git a/trunk/drivers/md/raid5.c b/trunk/drivers/md/raid5.c index 4698d5f79575..93a9726cc2d6 100644 --- a/trunk/drivers/md/raid5.c +++ b/trunk/drivers/md/raid5.c @@ -1931,7 +1931,6 @@ static int raid5_resize(mddev_t *mddev, sector_t sectors) set_bit(MD_RECOVERY_NEEDED, &mddev->recovery); } mddev->size = sectors /2; - mddev->resync_max_sectors = sectors; return 0; } diff --git a/trunk/drivers/md/raid6main.c b/trunk/drivers/md/raid6main.c index f5ee16805111..f62ea1a73d0d 100644 --- a/trunk/drivers/md/raid6main.c +++ b/trunk/drivers/md/raid6main.c @@ -2095,7 +2095,6 @@ static int raid6_resize(mddev_t *mddev, sector_t sectors) set_bit(MD_RECOVERY_NEEDED, &mddev->recovery); } mddev->size = sectors /2; - mddev->resync_max_sectors = sectors; return 0; } diff --git a/trunk/drivers/media/dvb/frontends/Kconfig b/trunk/drivers/media/dvb/frontends/Kconfig index e83256d0fd14..d847c62bd837 100644 --- a/trunk/drivers/media/dvb/frontends/Kconfig +++ b/trunk/drivers/media/dvb/frontends/Kconfig @@ -187,8 +187,8 @@ config DVB_BCM3510 An ATSC 8VSB/16VSB and QAM64/256 tuner module. Say Y when you want to support this frontend. -config DVB_LGDT330X - tristate "LGDT3302 or LGDT3303 based (DViCO FusionHDTV Gold)" +config DVB_LGDT3302 + tristate "LGDT3302 based (DViCO FusionHDTV3 Gold)" depends on DVB_CORE help An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want diff --git a/trunk/drivers/media/dvb/frontends/Makefile b/trunk/drivers/media/dvb/frontends/Makefile index ad8658ffd60a..de5e240cba7f 100644 --- a/trunk/drivers/media/dvb/frontends/Makefile +++ b/trunk/drivers/media/dvb/frontends/Makefile @@ -30,4 +30,4 @@ obj-$(CONFIG_DVB_OR51211) += or51211.o obj-$(CONFIG_DVB_OR51132) += or51132.o obj-$(CONFIG_DVB_BCM3510) += bcm3510.o obj-$(CONFIG_DVB_S5H1420) += s5h1420.o -obj-$(CONFIG_DVB_LGDT330X) += lgdt330x.o +obj-$(CONFIG_DVB_LGDT3302) += lgdt3302.o diff --git a/trunk/drivers/media/dvb/frontends/dvb-pll.c b/trunk/drivers/media/dvb/frontends/dvb-pll.c index 5264310c070e..5afeaa9b43b4 100644 --- a/trunk/drivers/media/dvb/frontends/dvb-pll.c +++ b/trunk/drivers/media/dvb/frontends/dvb-pll.c @@ -82,14 +82,13 @@ struct dvb_pll_desc dvb_pll_lg_z201 = { .name = "LG z201", .min = 174000000, .max = 862000000, - .count = 6, + .count = 5, .entries = { { 0, 36166667, 166666, 0xbc, 0x03 }, - { 157500000, 36166667, 166666, 0xbc, 0x01 }, - { 443250000, 36166667, 166666, 0xbc, 0x02 }, - { 542000000, 36166667, 166666, 0xbc, 0x04 }, - { 830000000, 36166667, 166666, 0xf4, 0x04 }, - { 999999999, 36166667, 166666, 0xfc, 0x04 }, + { 443250000, 36166667, 166666, 0xbc, 0x01 }, + { 542000000, 36166667, 166666, 0xbc, 0x02 }, + { 830000000, 36166667, 166666, 0xf4, 0x02 }, + { 999999999, 36166667, 166666, 0xfc, 0x02 }, }, }; EXPORT_SYMBOL(dvb_pll_lg_z201); diff --git a/trunk/drivers/media/dvb/frontends/lgdt330x.c b/trunk/drivers/media/dvb/frontends/lgdt3302.c similarity index 77% rename from trunk/drivers/media/dvb/frontends/lgdt330x.c rename to trunk/drivers/media/dvb/frontends/lgdt3302.c index e94dee50eecd..c85a2a99df42 100644 --- a/trunk/drivers/media/dvb/frontends/lgdt330x.c +++ b/trunk/drivers/media/dvb/frontends/lgdt3302.c @@ -1,5 +1,5 @@ /* - * Support for LGDT3302 & LGDT3303 (DViCO FusionHDTV Gold) - VSB/QAM + * Support for LGDT3302 (DViCO FustionHDTV 3 Gold) - VSB/QAM * * Copyright (C) 2005 Wilson Michaels * @@ -25,11 +25,10 @@ /* * NOTES ABOUT THIS DRIVER * - * This driver supports DViCO FusionHDTV Gold under Linux. + * This driver supports DViCO FusionHDTV 3 Gold under Linux. * * TODO: * BER and signal strength always return 0. - * Include support for LGDT3303 * */ @@ -42,24 +41,24 @@ #include "dvb_frontend.h" #include "dvb-pll.h" -#include "lgdt330x_priv.h" -#include "lgdt330x.h" +#include "lgdt3302_priv.h" +#include "lgdt3302.h" static int debug = 0; module_param(debug, int, 0644); -MODULE_PARM_DESC(debug,"Turn on/off lgdt330x frontend debugging (default:off)."); +MODULE_PARM_DESC(debug,"Turn on/off lgdt3302 frontend debugging (default:off)."); #define dprintk(args...) \ do { \ -if (debug) printk(KERN_DEBUG "lgdt330x: " args); \ +if (debug) printk(KERN_DEBUG "lgdt3302: " args); \ } while (0) -struct lgdt330x_state +struct lgdt3302_state { struct i2c_adapter* i2c; struct dvb_frontend_ops ops; /* Configuration settings */ - const struct lgdt330x_config* config; + const struct lgdt3302_config* config; struct dvb_frontend frontend; @@ -70,33 +69,45 @@ struct lgdt330x_state u32 current_frequency; }; -static int i2c_writebytes (struct lgdt330x_state* state, +static int i2c_writebytes (struct lgdt3302_state* state, u8 addr, /* demod_address or pll_address */ u8 *buf, /* data bytes to send */ int len /* number of bytes to send */ ) { - u8 tmp[] = { buf[0], buf[1] }; - struct i2c_msg msg = - { .addr = addr, .flags = 0, .buf = tmp, .len = 2 }; - int err; - int i; + if (addr == state->config->pll_address) { + struct i2c_msg msg = + { .addr = addr, .flags = 0, .buf = buf, .len = len }; + int err; - for (i=1; ii2c, &msg, 1)) != 1) { - printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err == %i)\n", __FUNCTION__, addr, buf[0], err); + printk(KERN_WARNING "lgdt3302: %s error (addr %02x <- %02x, err == %i)\n", __FUNCTION__, addr, buf[0], err); if (err < 0) return err; else return -EREMOTEIO; } - tmp[0]++; + } else { + u8 tmp[] = { buf[0], buf[1] }; + struct i2c_msg msg = + { .addr = addr, .flags = 0, .buf = tmp, .len = 2 }; + int err; + int i; + + for (i=1; ii2c, &msg, 1)) != 1) { + printk(KERN_WARNING "lgdt3302: %s error (addr %02x <- %02x, err == %i)\n", __FUNCTION__, addr, buf[0], err); + if (err < 0) + return err; + else + return -EREMOTEIO; + } + tmp[0]++; + } } return 0; } - -#if 0 -static int i2c_readbytes (struct lgdt330x_state* state, +static int i2c_readbytes (struct lgdt3302_state* state, u8 addr, /* demod_address or pll_address */ u8 *buf, /* holds data bytes read */ int len /* number of bytes to read */ ) @@ -106,19 +117,18 @@ static int i2c_readbytes (struct lgdt330x_state* state, int err; if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { - printk(KERN_WARNING "lgdt330x: %s error (addr %02x, err == %i)\n", __FUNCTION__, addr, err); + printk(KERN_WARNING "lgdt3302: %s error (addr %02x, err == %i)\n", __FUNCTION__, addr, err); return -EREMOTEIO; } return 0; } -#endif /* * This routine writes the register (reg) to the demod bus * then reads the data returned for (len) bytes. */ -static u8 i2c_selectreadbytes (struct lgdt330x_state* state, +static u8 i2c_selectreadbytes (struct lgdt3302_state* state, enum I2C_REG reg, u8* buf, int len) { u8 wr [] = { reg }; @@ -131,7 +141,7 @@ static u8 i2c_selectreadbytes (struct lgdt330x_state* state, int ret; ret = i2c_transfer(state->i2c, msg, 2); if (ret != 2) { - printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __FUNCTION__, state->config->demod_address, reg, ret); + printk(KERN_WARNING "lgdt3302: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __FUNCTION__, state->config->demod_address, reg, ret); } else { ret = 0; } @@ -139,7 +149,7 @@ static u8 i2c_selectreadbytes (struct lgdt330x_state* state, } /* Software reset */ -int lgdt330x_SwReset(struct lgdt330x_state* state) +int lgdt3302_SwReset(struct lgdt3302_state* state) { u8 ret; u8 reset[] = { @@ -165,7 +175,7 @@ int lgdt330x_SwReset(struct lgdt330x_state* state) return ret; } -static int lgdt330x_init(struct dvb_frontend* fe) +static int lgdt3302_init(struct dvb_frontend* fe) { /* Hardware reset is done using gpio[0] of cx23880x chip. * I'd like to do it here, but don't know how to find chip address. @@ -174,18 +184,18 @@ static int lgdt330x_init(struct dvb_frontend* fe) * the caller of this function needs to do it. */ dprintk("%s entered\n", __FUNCTION__); - return lgdt330x_SwReset((struct lgdt330x_state*) fe->demodulator_priv); + return lgdt3302_SwReset((struct lgdt3302_state*) fe->demodulator_priv); } -static int lgdt330x_read_ber(struct dvb_frontend* fe, u32* ber) +static int lgdt3302_read_ber(struct dvb_frontend* fe, u32* ber) { *ber = 0; /* Dummy out for now */ return 0; } -static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) +static int lgdt3302_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) { - struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; + struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv; u8 buf[2]; i2c_selectreadbytes(state, PACKET_ERR_COUNTER1, buf, sizeof(buf)); @@ -194,11 +204,12 @@ static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) return 0; } -static int lgdt330x_set_parameters(struct dvb_frontend* fe, +static int lgdt3302_set_parameters(struct dvb_frontend* fe, struct dvb_frontend_parameters *param) { - struct lgdt330x_state* state = - (struct lgdt330x_state*) fe->demodulator_priv; + u8 buf[4]; + struct lgdt3302_state* state = + (struct lgdt3302_state*) fe->demodulator_priv; /* Use 50MHz parameter values from spec sheet since xtal is 50 */ static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 }; @@ -217,10 +228,6 @@ static int lgdt330x_set_parameters(struct dvb_frontend* fe, /* Select VSB mode and serial MPEG interface */ top_ctrl_cfg[1] = 0x07; - - /* Select ANT connector if supported by card */ - if (state->config->pll_rf_set) - state->config->pll_rf_set(fe, 1); break; case QAM_64: @@ -228,10 +235,6 @@ static int lgdt330x_set_parameters(struct dvb_frontend* fe, /* Select QAM_64 mode and serial MPEG interface */ top_ctrl_cfg[1] = 0x04; - - /* Select CABLE connector if supported by card */ - if (state->config->pll_rf_set) - state->config->pll_rf_set(fe, 0); break; case QAM_256: @@ -239,13 +242,9 @@ static int lgdt330x_set_parameters(struct dvb_frontend* fe, /* Select QAM_256 mode and serial MPEG interface */ top_ctrl_cfg[1] = 0x05; - - /* Select CABLE connector if supported by card */ - if (state->config->pll_rf_set) - state->config->pll_rf_set(fe, 0); break; default: - printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __FUNCTION__, param->u.vsb.modulation); + printk(KERN_WARNING "lgdt3302: %s: Modulation type(%d) UNSUPPORTED\n", __FUNCTION__, param->u.vsb.modulation); return -1; } /* Initializations common to all modes */ @@ -291,50 +290,44 @@ static int lgdt330x_set_parameters(struct dvb_frontend* fe, /* Change only if we are actually changing the channel */ if (state->current_frequency != param->frequency) { - u8 buf[5]; - struct i2c_msg msg = { .flags = 0, .buf = &buf[1], .len = 4 }; - int err; - - state->config->pll_set(fe, param, buf); - msg.addr = buf[0]; + dvb_pll_configure(state->config->pll_desc, buf, + param->frequency, 0); + dprintk("%s: tuner bytes: 0x%02x 0x%02x " + "0x%02x 0x%02x\n", __FUNCTION__, buf[0],buf[1],buf[2],buf[3]); + i2c_writebytes(state, state->config->pll_address ,buf, 4); - dprintk("%s: tuner at 0x%02x bytes: 0x%02x 0x%02x " - "0x%02x 0x%02x\n", __FUNCTION__, - buf[0],buf[1],buf[2],buf[3],buf[4]); - if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { - printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __FUNCTION__, buf[0], buf[1], err); - if (err < 0) - return err; - else - return -EREMOTEIO; - } -#if 0 /* Check the status of the tuner pll */ - i2c_readbytes(state, buf[0], &buf[1], 1); - dprintk("%s: tuner status byte = 0x%02x\n", __FUNCTION__, buf[1]); -#endif + i2c_readbytes(state, state->config->pll_address, buf, 1); + dprintk("%s: tuner status byte = 0x%02x\n", __FUNCTION__, buf[0]); + /* Update current frequency */ state->current_frequency = param->frequency; } - lgdt330x_SwReset(state); + lgdt3302_SwReset(state); return 0; } -static int lgdt330x_get_frontend(struct dvb_frontend* fe, +static int lgdt3302_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters* param) { - struct lgdt330x_state *state = fe->demodulator_priv; + struct lgdt3302_state *state = fe->demodulator_priv; param->frequency = state->current_frequency; return 0; } -static int lgdt330x_read_status(struct dvb_frontend* fe, fe_status_t* status) +static int lgdt3302_read_status(struct dvb_frontend* fe, fe_status_t* status) { - struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; + struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv; u8 buf[3]; *status = 0; /* Reset status result */ + /* Check the status of the tuner pll */ + i2c_readbytes(state, state->config->pll_address, buf, 1); + dprintk("%s: tuner status byte = 0x%02x\n", __FUNCTION__, buf[0]); + if ((buf[0] & 0xc0) != 0x40) + return 0; /* Tuner PLL not locked or not powered on */ + /* * You must set the Mask bits to 1 in the IRQ_MASK in order * to see that status bit in the IRQ_STATUS register. @@ -390,19 +383,19 @@ static int lgdt330x_read_status(struct dvb_frontend* fe, fe_status_t* status) *status |= FE_HAS_CARRIER; break; default: - printk("KERN_WARNING lgdt330x: %s: Modulation set to unsupported value\n", __FUNCTION__); + printk("KERN_WARNING lgdt3302: %s: Modulation set to unsupported value\n", __FUNCTION__); } return 0; } -static int lgdt330x_read_signal_strength(struct dvb_frontend* fe, u16* strength) +static int lgdt3302_read_signal_strength(struct dvb_frontend* fe, u16* strength) { /* not directly available. */ return 0; } -static int lgdt330x_read_snr(struct dvb_frontend* fe, u16* snr) +static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr) { #ifdef SNR_IN_DB /* @@ -457,7 +450,7 @@ static int lgdt330x_read_snr(struct dvb_frontend* fe, u16* snr) static u8 buf[5];/* read data buffer */ static u32 noise; /* noise value */ static u32 snr_db; /* index into SNR_EQ[] */ - struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; + struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv; /* read both equalizer and pase tracker noise data */ i2c_selectreadbytes(state, EQPH_ERR0, buf, sizeof(buf)); @@ -493,7 +486,7 @@ static int lgdt330x_read_snr(struct dvb_frontend* fe, u16* snr) /* Return the raw noise value */ static u8 buf[5];/* read data buffer */ static u32 noise; /* noise value */ - struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; + struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv; /* read both equalizer and pase tracker noise data */ i2c_selectreadbytes(state, EQPH_ERR0, buf, sizeof(buf)); @@ -516,7 +509,7 @@ static int lgdt330x_read_snr(struct dvb_frontend* fe, u16* snr) return 0; } -static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings) +static int lgdt3302_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings) { /* I have no idea about this - it may not be needed */ fe_tune_settings->min_delay_ms = 500; @@ -525,22 +518,22 @@ static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_fronte return 0; } -static void lgdt330x_release(struct dvb_frontend* fe) +static void lgdt3302_release(struct dvb_frontend* fe) { - struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; + struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv; kfree(state); } -static struct dvb_frontend_ops lgdt330x_ops; +static struct dvb_frontend_ops lgdt3302_ops; -struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config, +struct dvb_frontend* lgdt3302_attach(const struct lgdt3302_config* config, struct i2c_adapter* i2c) { - struct lgdt330x_state* state = NULL; + struct lgdt3302_state* state = NULL; u8 buf[1]; /* Allocate memory for the internal state */ - state = (struct lgdt330x_state*) kmalloc(sizeof(struct lgdt330x_state), GFP_KERNEL); + state = (struct lgdt3302_state*) kmalloc(sizeof(struct lgdt3302_state), GFP_KERNEL); if (state == NULL) goto error; memset(state,0,sizeof(*state)); @@ -548,7 +541,7 @@ struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config, /* Setup the state */ state->config = config; state->i2c = i2c; - memcpy(&state->ops, &lgdt330x_ops, sizeof(struct dvb_frontend_ops)); + memcpy(&state->ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops)); /* Verify communication with demod chip */ if (i2c_selectreadbytes(state, 2, buf, 1)) goto error; @@ -568,9 +561,9 @@ struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config, return NULL; } -static struct dvb_frontend_ops lgdt330x_ops = { +static struct dvb_frontend_ops lgdt3302_ops = { .info = { - .name= "LG Electronics lgdt330x VSB/QAM Frontend", + .name= "LG Electronics LGDT3302 VSB/QAM Frontend", .type = FE_ATSC, .frequency_min= 54000000, .frequency_max= 858000000, @@ -580,23 +573,23 @@ static struct dvb_frontend_ops lgdt330x_ops = { .symbol_rate_max = 10762000, .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB }, - .init = lgdt330x_init, - .set_frontend = lgdt330x_set_parameters, - .get_frontend = lgdt330x_get_frontend, - .get_tune_settings = lgdt330x_get_tune_settings, - .read_status = lgdt330x_read_status, - .read_ber = lgdt330x_read_ber, - .read_signal_strength = lgdt330x_read_signal_strength, - .read_snr = lgdt330x_read_snr, - .read_ucblocks = lgdt330x_read_ucblocks, - .release = lgdt330x_release, + .init = lgdt3302_init, + .set_frontend = lgdt3302_set_parameters, + .get_frontend = lgdt3302_get_frontend, + .get_tune_settings = lgdt3302_get_tune_settings, + .read_status = lgdt3302_read_status, + .read_ber = lgdt3302_read_ber, + .read_signal_strength = lgdt3302_read_signal_strength, + .read_snr = lgdt3302_read_snr, + .read_ucblocks = lgdt3302_read_ucblocks, + .release = lgdt3302_release, }; -MODULE_DESCRIPTION("lgdt330x [DViCO FusionHDTV 3 Gold] (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver"); +MODULE_DESCRIPTION("LGDT3302 [DViCO FusionHDTV 3 Gold] (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver"); MODULE_AUTHOR("Wilson Michaels"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(lgdt330x_attach); +EXPORT_SYMBOL(lgdt3302_attach); /* * Local variables: diff --git a/trunk/drivers/media/dvb/frontends/lgdt330x.h b/trunk/drivers/media/dvb/frontends/lgdt3302.h similarity index 72% rename from trunk/drivers/media/dvb/frontends/lgdt330x.h rename to trunk/drivers/media/dvb/frontends/lgdt3302.h index 04986f8e7565..81587a40032b 100644 --- a/trunk/drivers/media/dvb/frontends/lgdt330x.h +++ b/trunk/drivers/media/dvb/frontends/lgdt3302.h @@ -1,5 +1,7 @@ /* - * Support for LGDT3302 & LGDT3303 (DViCO FustionHDTV Gold) - VSB/QAM + * $Id: lgdt3302.h,v 1.2 2005/06/28 23:50:48 mkrufky Exp $ + * + * Support for LGDT3302 (DViCO FustionHDTV 3 Gold) - VSB/QAM * * Copyright (C) 2005 Wilson Michaels * @@ -19,28 +21,26 @@ * */ -#ifndef LGDT330X_H -#define LGDT330X_H +#ifndef LGDT3302_H +#define LGDT3302_H #include -struct lgdt330x_config +struct lgdt3302_config { /* The demodulator's i2c address */ u8 demod_address; - - /* PLL interface */ - int (*pll_rf_set) (struct dvb_frontend* fe, int index); - int (*pll_set)(struct dvb_frontend* fe, struct dvb_frontend_parameters* params, u8* pll_address); + u8 pll_address; + struct dvb_pll_desc *pll_desc; /* Need to set device param for start_dma */ int (*set_ts_params)(struct dvb_frontend* fe, int is_punctured); }; -extern struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config, +extern struct dvb_frontend* lgdt3302_attach(const struct lgdt3302_config* config, struct i2c_adapter* i2c); -#endif /* LGDT330X_H */ +#endif /* LGDT3302_H */ /* * Local variables: diff --git a/trunk/drivers/media/dvb/frontends/lgdt330x_priv.h b/trunk/drivers/media/dvb/frontends/lgdt3302_priv.h similarity index 89% rename from trunk/drivers/media/dvb/frontends/lgdt330x_priv.h rename to trunk/drivers/media/dvb/frontends/lgdt3302_priv.h index 4143ce8f1a95..6193fa7a569d 100644 --- a/trunk/drivers/media/dvb/frontends/lgdt330x_priv.h +++ b/trunk/drivers/media/dvb/frontends/lgdt3302_priv.h @@ -1,5 +1,7 @@ /* - * Support for LGDT3302 & LGDT3303 (DViCO FustionHDTV Gold) - VSB/QAM + * $Id: lgdt3302_priv.h,v 1.2 2005/06/28 23:50:48 mkrufky Exp $ + * + * Support for LGDT3302 (DViCO FustionHDTV 3 Gold) - VSB/QAM * * Copyright (C) 2005 Wilson Michaels * @@ -19,8 +21,8 @@ * */ -#ifndef _LGDT330X_PRIV_ -#define _LGDT330X_PRIV_ +#ifndef _LGDT3302_PRIV_ +#define _LGDT3302_PRIV_ /* i2c control register addresses */ enum I2C_REG { @@ -61,7 +63,7 @@ enum I2C_REG { PACKET_ERR_COUNTER2= 0x6b, }; -#endif /* _LGDT330X_PRIV_ */ +#endif /* _LGDT3302_PRIV_ */ /* * Local variables: diff --git a/trunk/drivers/media/radio/radio-maestro.c b/trunk/drivers/media/radio/radio-maestro.c index e5e2021a7312..e62147e4ed1b 100644 --- a/trunk/drivers/media/radio/radio-maestro.c +++ b/trunk/drivers/media/radio/radio-maestro.c @@ -154,7 +154,7 @@ static void radio_bits_set(struct radio_device *dev, __u32 data) msleep(125); } -static inline int radio_function(struct inode *inode, struct file *file, +inline static int radio_function(struct inode *inode, struct file *file, unsigned int cmd, void *arg) { struct video_device *dev = video_devdata(file); @@ -283,7 +283,7 @@ static int __init maestro_radio_init(void) module_init(maestro_radio_init); module_exit(maestro_radio_exit); -static inline __u16 radio_power_on(struct radio_device *dev) +inline static __u16 radio_power_on(struct radio_device *dev) { register __u16 io=dev->io; register __u32 ofreq; diff --git a/trunk/drivers/media/radio/radio-maxiradio.c b/trunk/drivers/media/radio/radio-maxiradio.c index 02d39a50d5ed..5b748a48ce72 100644 --- a/trunk/drivers/media/radio/radio-maxiradio.c +++ b/trunk/drivers/media/radio/radio-maxiradio.c @@ -166,7 +166,7 @@ static int get_tune(__u16 io) } -static inline int radio_function(struct inode *inode, struct file *file, +inline static int radio_function(struct inode *inode, struct file *file, unsigned int cmd, void *arg) { struct video_device *dev = video_devdata(file); diff --git a/trunk/drivers/media/video/Kconfig b/trunk/drivers/media/video/Kconfig index ac81e5e01a9a..f461750c7646 100644 --- a/trunk/drivers/media/video/Kconfig +++ b/trunk/drivers/media/video/Kconfig @@ -236,7 +236,7 @@ config VIDEO_MEYE config VIDEO_SAA7134 tristate "Philips SAA7134 support" - depends on VIDEO_DEV && PCI && I2C && SOUND + depends on VIDEO_DEV && PCI && I2C select VIDEO_BUF select VIDEO_IR select VIDEO_TUNER @@ -331,7 +331,7 @@ config VIDEO_CX88_DVB select DVB_MT352 select DVB_OR51132 select DVB_CX22702 - select DVB_LGDT330X + select DVB_LGDT3302 ---help--- This adds support for DVB/ATSC cards based on the Connexant 2388x chip. diff --git a/trunk/drivers/media/video/bttv-cards.c b/trunk/drivers/media/video/bttv-cards.c index 6c52fd0bb7df..2dbf5ec43abd 100644 --- a/trunk/drivers/media/video/bttv-cards.c +++ b/trunk/drivers/media/video/bttv-cards.c @@ -1,5 +1,5 @@ /* - $Id: bttv-cards.c,v 1.54 2005/07/19 18:26:46 mkrufky Exp $ + $Id: bttv-cards.c,v 1.53 2005/07/05 17:37:35 nsh Exp $ bttv-cards.c @@ -2772,6 +2772,8 @@ void __devinit bttv_init_card2(struct bttv *btv) } btv->pll.pll_current = -1; + bttv_reset_audio(btv); + /* tuner configuration (from card list / autodetect / insmod option) */ if (UNSET != bttv_tvcards[btv->c.type].tuner_type) if(UNSET == btv->tuner_type) diff --git a/trunk/drivers/media/video/cx88/Makefile b/trunk/drivers/media/video/cx88/Makefile index 107e48645e3a..606d0348da2c 100644 --- a/trunk/drivers/media/video/cx88/Makefile +++ b/trunk/drivers/media/video/cx88/Makefile @@ -9,15 +9,3 @@ obj-$(CONFIG_VIDEO_CX88_DVB) += cx88-dvb.o EXTRA_CFLAGS += -I$(src)/.. EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/dvb-core EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/frontends -ifneq ($(CONFIG_DVB_CX22702),n) - EXTRA_CFLAGS += -DHAVE_CX22702=1 -endif -ifneq ($(CONFIG_DVB_OR51132),n) - EXTRA_CFLAGS += -DHAVE_OR51132=1 -endif -ifneq ($(CONFIG_DVB_LGDT330X),n) - EXTRA_CFLAGS += -DHAVE_LGDT330X=1 -endif -ifneq ($(CONFIG_DVB_MT352),n) - EXTRA_CFLAGS += -DHAVE_MT352=1 -endif diff --git a/trunk/drivers/media/video/cx88/cx88-dvb.c b/trunk/drivers/media/video/cx88/cx88-dvb.c index ef0e9a85c359..6ad1458ab652 100644 --- a/trunk/drivers/media/video/cx88/cx88-dvb.c +++ b/trunk/drivers/media/video/cx88/cx88-dvb.c @@ -1,5 +1,5 @@ /* - * $Id: cx88-dvb.c,v 1.54 2005/07/25 05:13:50 mkrufky Exp $ + * $Id: cx88-dvb.c,v 1.42 2005/07/12 15:44:55 mkrufky Exp $ * * device driver for Conexant 2388x based TV cards * MPEG Transport Stream (DVB) routines @@ -29,23 +29,27 @@ #include #include #include -#include + +#define CONFIG_DVB_MT352 1 +#define CONFIG_DVB_CX22702 1 +#define CONFIG_DVB_OR51132 1 +#define CONFIG_DVB_LGDT3302 1 #include "cx88.h" #include "dvb-pll.h" -#ifdef HAVE_MT352 +#if CONFIG_DVB_MT352 # include "mt352.h" # include "mt352_priv.h" #endif -#ifdef HAVE_CX22702 +#if CONFIG_DVB_CX22702 # include "cx22702.h" #endif -#ifdef HAVE_OR51132 +#if CONFIG_DVB_OR51132 # include "or51132.h" #endif -#ifdef HAVE_LGDT330X -# include "lgdt330x.h" +#if CONFIG_DVB_LGDT3302 +# include "lgdt3302.h" #endif MODULE_DESCRIPTION("driver for cx2388x based DVB cards"); @@ -103,7 +107,7 @@ static struct videobuf_queue_ops dvb_qops = { /* ------------------------------------------------------------------ */ -#ifdef HAVE_MT352 +#if CONFIG_DVB_MT352 static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe) { static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 }; @@ -173,7 +177,7 @@ static struct mt352_config dntv_live_dvbt_config = { }; #endif -#ifdef HAVE_CX22702 +#if CONFIG_DVB_CX22702 static struct cx22702_config connexant_refboard_config = { .demod_address = 0x43, .output_mode = CX22702_SERIAL_OUTPUT, @@ -189,7 +193,7 @@ static struct cx22702_config hauppauge_novat_config = { }; #endif -#ifdef HAVE_OR51132 +#if CONFIG_DVB_OR51132 static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured) { @@ -206,33 +210,8 @@ static struct or51132_config pchdtv_hd3000 = { }; #endif -#ifdef HAVE_LGDT330X -static int lgdt330x_pll_set(struct dvb_frontend* fe, - struct dvb_frontend_parameters* params, - u8* pllbuf) -{ - struct cx8802_dev *dev= fe->dvb->priv; - - pllbuf[0] = dev->core->pll_addr; - dvb_pll_configure(dev->core->pll_desc, &pllbuf[1], - params->frequency, 0); - return 0; -} - -static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index) -{ - struct cx8802_dev *dev= fe->dvb->priv; - struct cx88_core *core = dev->core; - - dprintk(1, "%s: index = %d\n", __FUNCTION__, index); - if (index == 0) - cx_clear(MO_GP0_IO, 8); - else - cx_set(MO_GP0_IO, 8); - return 0; -} - -static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured) +#if CONFIG_DVB_LGDT3302 +static int lgdt3302_set_ts_param(struct dvb_frontend* fe, int is_punctured) { struct cx8802_dev *dev= fe->dvb->priv; if (is_punctured) @@ -242,10 +221,18 @@ static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured) return 0; } -static struct lgdt330x_config fusionhdtv_3_gold = { +static struct lgdt3302_config fusionhdtv_3_gold_q = { .demod_address = 0x0e, - .pll_set = lgdt330x_pll_set, - .set_ts_params = lgdt330x_set_ts_param, + .pll_address = 0x61, + .pll_desc = &dvb_pll_microtune_4042, + .set_ts_params = lgdt3302_set_ts_param, +}; + +static struct lgdt3302_config fusionhdtv_3_gold_t = { + .demod_address = 0x0e, + .pll_address = 0x61, + .pll_desc = &dvb_pll_thomson_dtt7611, + .set_ts_params = lgdt3302_set_ts_param, }; #endif @@ -257,7 +244,7 @@ static int dvb_register(struct cx8802_dev *dev) /* init frontend */ switch (dev->core->board) { -#ifdef HAVE_CX22702 +#if CONFIG_DVB_CX22702 case CX88_BOARD_HAUPPAUGE_DVB_T1: dev->dvb.frontend = cx22702_attach(&hauppauge_novat_config, &dev->core->i2c_adap); @@ -268,7 +255,7 @@ static int dvb_register(struct cx8802_dev *dev) &dev->core->i2c_adap); break; #endif -#ifdef HAVE_MT352 +#if CONFIG_DVB_MT352 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1: dev->core->pll_addr = 0x61; dev->core->pll_desc = &dvb_pll_lg_z201; @@ -290,13 +277,13 @@ static int dvb_register(struct cx8802_dev *dev) &dev->core->i2c_adap); break; #endif -#ifdef HAVE_OR51132 +#if CONFIG_DVB_OR51132 case CX88_BOARD_PCHDTV_HD3000: dev->dvb.frontend = or51132_attach(&pchdtv_hd3000, &dev->core->i2c_adap); break; #endif -#ifdef HAVE_LGDT330X +#if CONFIG_DVB_LGDT3302 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q: dev->ts_gen_cntrl = 0x08; { @@ -305,14 +292,9 @@ static int dvb_register(struct cx8802_dev *dev) cx_clear(MO_GP0_IO, 1); mdelay(100); - cx_set(MO_GP0_IO, 1); + cx_set(MO_GP0_IO, 9); // ANT connector too FIXME mdelay(200); - - /* Select RF connector callback */ - fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set; - dev->core->pll_addr = 0x61; - dev->core->pll_desc = &dvb_pll_microtune_4042; - dev->dvb.frontend = lgdt330x_attach(&fusionhdtv_3_gold, + dev->dvb.frontend = lgdt3302_attach(&fusionhdtv_3_gold_q, &dev->core->i2c_adap); } break; @@ -324,11 +306,9 @@ static int dvb_register(struct cx8802_dev *dev) cx_clear(MO_GP0_IO, 1); mdelay(100); - cx_set(MO_GP0_IO, 9); + cx_set(MO_GP0_IO, 9); /* ANT connector too FIXME */ mdelay(200); - dev->core->pll_addr = 0x61; - dev->core->pll_desc = &dvb_pll_thomson_dtt7611; - dev->dvb.frontend = lgdt330x_attach(&fusionhdtv_3_gold, + dev->dvb.frontend = lgdt3302_attach(&fusionhdtv_3_gold_t, &dev->core->i2c_adap); } break; diff --git a/trunk/drivers/media/video/cx88/cx88-i2c.c b/trunk/drivers/media/video/cx88/cx88-i2c.c index a628a55299c6..8403c4e95050 100644 --- a/trunk/drivers/media/video/cx88/cx88-i2c.c +++ b/trunk/drivers/media/video/cx88/cx88-i2c.c @@ -1,5 +1,5 @@ /* - $Id: cx88-i2c.c,v 1.30 2005/07/25 05:10:13 mkrufky Exp $ + $Id: cx88-i2c.c,v 1.28 2005/07/05 17:37:35 nsh Exp $ cx88-i2c.c -- all the i2c code is here @@ -164,7 +164,7 @@ static struct i2c_client cx8800_i2c_client_template = { }; static char *i2c_devs[128] = { - [ 0x1c >> 1 ] = "lgdt330x", + [ 0x1c >> 1 ] = "lgdt3302", [ 0x86 >> 1 ] = "tda9887/cx22702", [ 0xa0 >> 1 ] = "eeprom", [ 0xc0 >> 1 ] = "tuner (analog)", diff --git a/trunk/drivers/media/video/mxb.c b/trunk/drivers/media/video/mxb.c index d04793fb80fc..486234d41b56 100644 --- a/trunk/drivers/media/video/mxb.c +++ b/trunk/drivers/media/video/mxb.c @@ -142,8 +142,8 @@ struct mxb int cur_mode; /* current audio mode (mono, stereo, ...) */ int cur_input; /* current input */ + int cur_freq; /* current frequency the tuner is tuned to */ int cur_mute; /* current mute status */ - struct v4l2_frequency cur_freq; /* current frequency the tuner is tuned to */ }; static struct saa7146_extension extension; @@ -352,15 +352,9 @@ static int mxb_init_done(struct saa7146_dev* dev) /* select a tuner type */ tun_setup.mode_mask = T_ANALOG_TV; tun_setup.addr = ADDR_UNSET; - tun_setup.type = TUNER_PHILIPS_PAL; + tun_setup.type = 5; mxb->tuner->driver->command(mxb->tuner,TUNER_SET_TYPE_ADDR, &tun_setup); - /* tune in some frequency on tuner */ - mxb->cur_freq.tuner = 0; - mxb->cur_freq.type = V4L2_TUNER_ANALOG_TV; - mxb->cur_freq.frequency = freq; - mxb->tuner->driver->command(mxb->tuner, VIDIOC_S_FREQUENCY, - &mxb->cur_freq); - + /* mute audio on tea6420s */ mxb->tea6420_1->driver->command(mxb->tea6420_1,TEA6420_SWITCH, &TEA6420_line[6][0]); mxb->tea6420_2->driver->command(mxb->tea6420_2,TEA6420_SWITCH, &TEA6420_line[6][1]); @@ -377,8 +371,12 @@ static int mxb_init_done(struct saa7146_dev* dev) vm.out = 13; mxb->tea6415c->driver->command(mxb->tea6415c,TEA6415C_SWITCH, &vm); + /* tune in some frequency on tuner */ + mxb->tuner->driver->command(mxb->tuner, VIDIOCSFREQ, &freq); + /* the rest for mxb */ mxb->cur_input = 0; + mxb->cur_freq = freq; mxb->cur_mute = 1; mxb->cur_mode = V4L2_TUNER_MODE_STEREO; @@ -821,14 +819,18 @@ static int mxb_ioctl(struct saa7146_fh *fh, unsigned int cmd, void *arg) return -EINVAL; } - *f = mxb->cur_freq; + memset(f,0,sizeof(*f)); + f->type = V4L2_TUNER_ANALOG_TV; + f->frequency = mxb->cur_freq; - DEB_EE(("VIDIOC_G_FREQ: freq:0x%08x.\n", mxb->cur_freq.frequency)); + DEB_EE(("VIDIOC_G_FREQ: freq:0x%08x.\n", mxb->cur_freq)); return 0; } case VIDIOC_S_FREQUENCY: { struct v4l2_frequency *f = arg; + int t_locked = 0; + int v_byte = 0; if (0 != f->tuner) return -EINVAL; @@ -841,11 +843,20 @@ static int mxb_ioctl(struct saa7146_fh *fh, unsigned int cmd, void *arg) return -EINVAL; } - mxb->cur_freq = *f; - DEB_EE(("VIDIOC_S_FREQUENCY: freq:0x%08x.\n", mxb->cur_freq.frequency)); + DEB_EE(("VIDIOC_S_FREQUENCY: freq:0x%08x.\n",f->frequency)); + + mxb->cur_freq = f->frequency; /* tune in desired frequency */ - mxb->tuner->driver->command(mxb->tuner, VIDIOC_S_FREQUENCY, &mxb->cur_freq); + mxb->tuner->driver->command(mxb->tuner, VIDIOCSFREQ, &mxb->cur_freq); + + /* check if pll of tuner & saa7111a is locked */ +// mxb->tuner->driver->command(mxb->tuner,TUNER_IS_LOCKED, &t_locked); + mxb->saa7111a->driver->command(mxb->saa7111a,DECODER_GET_STATUS, &v_byte); + + /* not locked -- anything to do here ? */ + if( 0 == t_locked || 0 == (v_byte & DECODER_STATUS_GOOD)) { + } /* hack: changing the frequency should invalidate the vbi-counter (=> alevt) */ spin_lock(&dev->slock); diff --git a/trunk/drivers/media/video/saa7134/Makefile b/trunk/drivers/media/video/saa7134/Makefile index b778ffd94e65..e577a06b136b 100644 --- a/trunk/drivers/media/video/saa7134/Makefile +++ b/trunk/drivers/media/video/saa7134/Makefile @@ -9,9 +9,3 @@ obj-$(CONFIG_VIDEO_SAA7134_DVB) += saa7134-dvb.o EXTRA_CFLAGS += -I$(src)/.. EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/dvb-core EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/frontends -ifneq ($(CONFIG_DVB_MT352),n) - EXTRA_CFLAGS += -DHAVE_MT352=1 -endif -ifneq ($(CONFIG_DVB_TDA1004X),n) - EXTRA_CFLAGS += -DHAVE_TDA1004X=1 -endif diff --git a/trunk/drivers/media/video/saa7134/saa7134-dvb.c b/trunk/drivers/media/video/saa7134/saa7134-dvb.c index 8be6a90358c8..334bc1850092 100644 --- a/trunk/drivers/media/video/saa7134/saa7134-dvb.c +++ b/trunk/drivers/media/video/saa7134/saa7134-dvb.c @@ -1,5 +1,5 @@ /* - * $Id: saa7134-dvb.c,v 1.23 2005/07/24 22:12:47 mkrufky Exp $ + * $Id: saa7134-dvb.c,v 1.18 2005/07/04 16:05:50 mkrufky Exp $ * * (c) 2004 Gerd Knorr [SuSE Labs] * @@ -29,17 +29,18 @@ #include #include #include -#include +#define CONFIG_DVB_MT352 1 +#define CONFIG_DVB_TDA1004X 1 #include "saa7134-reg.h" #include "saa7134.h" -#ifdef HAVE_MT352 +#if CONFIG_DVB_MT352 # include "mt352.h" # include "mt352_priv.h" /* FIXME */ #endif -#ifdef HAVE_TDA1004X +#if CONFIG_DVB_TDA1004X # include "tda1004x.h" #endif @@ -53,7 +54,7 @@ MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)"); /* ------------------------------------------------------------------ */ -#ifdef HAVE_MT352 +#if CONFIG_DVB_MT352 static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on) { u32 ok; @@ -152,7 +153,7 @@ static struct mt352_config pinnacle_300i = { /* ------------------------------------------------------------------ */ -#ifdef HAVE_TDA1004X +#if CONFIG_DVB_TDA1004X static int philips_tu1216_pll_init(struct dvb_frontend *fe) { struct saa7134_dev *dev = fe->dvb->priv; @@ -384,7 +385,7 @@ static int philips_fmd1216_pll_set(struct dvb_frontend *fe, struct dvb_frontend_ return 0; } -#ifdef HAVE_TDA1004X + static struct tda1004x_config medion_cardbus = { .demod_address = 0x08, .invert = 1, @@ -397,7 +398,6 @@ static struct tda1004x_config medion_cardbus = { .pll_sleep = philips_fmd1216_analog, .request_firmware = NULL, }; -#endif /* ------------------------------------------------------------------ */ @@ -547,14 +547,14 @@ static int dvb_init(struct saa7134_dev *dev) dev); switch (dev->board) { -#ifdef HAVE_MT352 +#if CONFIG_DVB_MT352 case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL: printk("%s: pinnacle 300i dvb setup\n",dev->name); dev->dvb.frontend = mt352_attach(&pinnacle_300i, &dev->i2c_adap); break; #endif -#ifdef HAVE_TDA1004X +#if CONFIG_DVB_TDA1004X case SAA7134_BOARD_MD7134: dev->dvb.frontend = tda10046_attach(&medion_cardbus, &dev->i2c_adap); diff --git a/trunk/drivers/media/video/tvaudio.c b/trunk/drivers/media/video/tvaudio.c index f42a1efa8fcf..d8b78f1d686b 100644 --- a/trunk/drivers/media/video/tvaudio.c +++ b/trunk/drivers/media/video/tvaudio.c @@ -285,7 +285,6 @@ static int chip_thread(void *data) schedule(); } remove_wait_queue(&chip->wq, &wait); - try_to_freeze(); if (chip->done || signal_pending(current)) break; dprintk("%s: thread wakeup\n", i2c_clientname(&chip->c)); diff --git a/trunk/drivers/media/video/tveeprom.c b/trunk/drivers/media/video/tveeprom.c index 62b03ef091e0..e8d9440977cb 100644 --- a/trunk/drivers/media/video/tveeprom.c +++ b/trunk/drivers/media/video/tveeprom.c @@ -445,7 +445,6 @@ int tveeprom_read(struct i2c_client *c, unsigned char *eedata, int len) } EXPORT_SYMBOL(tveeprom_read); -#if 0 int tveeprom_dump(unsigned char *eedata, int len) { int i; @@ -461,7 +460,6 @@ int tveeprom_dump(unsigned char *eedata, int len) return 0; } EXPORT_SYMBOL(tveeprom_dump); -#endif /* 0 */ /* ----------------------------------------------------------------------- */ /* needed for ivtv.sf.net at the moment. Should go away in the long */ @@ -479,7 +477,7 @@ static unsigned short normal_i2c[] = { I2C_CLIENT_INSMOD; -static struct i2c_driver i2c_driver_tveeprom; +struct i2c_driver i2c_driver_tveeprom; static int tveeprom_command(struct i2c_client *client, @@ -551,7 +549,7 @@ tveeprom_detach_client (struct i2c_client *client) return 0; } -static struct i2c_driver i2c_driver_tveeprom = { +struct i2c_driver i2c_driver_tveeprom = { .owner = THIS_MODULE, .name = "tveeprom", .id = I2C_DRIVERID_TVEEPROM, diff --git a/trunk/drivers/mmc/wbsd.c b/trunk/drivers/mmc/wbsd.c index 8b487ed1069c..0c41d4b41a65 100644 --- a/trunk/drivers/mmc/wbsd.c +++ b/trunk/drivers/mmc/wbsd.c @@ -1053,7 +1053,7 @@ static void wbsd_detect_card(unsigned long data) * Tasklets */ -static inline struct mmc_data* wbsd_get_data(struct wbsd_host* host) +inline static struct mmc_data* wbsd_get_data(struct wbsd_host* host) { WARN_ON(!host->mrq); if (!host->mrq) diff --git a/trunk/drivers/mtd/devices/docecc.c b/trunk/drivers/mtd/devices/docecc.c index 9a087c1fb0b7..933877ff4d88 100644 --- a/trunk/drivers/mtd/devices/docecc.c +++ b/trunk/drivers/mtd/devices/docecc.c @@ -40,7 +40,6 @@ #include #include -#define DEBUG 0 /* need to undef it (from asm/termbits.h) */ #undef B0 diff --git a/trunk/drivers/net/3c505.c b/trunk/drivers/net/3c505.c index 111601ca4ca3..ad17f17e8e7a 100644 --- a/trunk/drivers/net/3c505.c +++ b/trunk/drivers/net/3c505.c @@ -272,7 +272,7 @@ static inline void set_hsf(struct net_device *dev, int hsf) static int start_receive(struct net_device *, pcb_struct *); -static inline void adapter_reset(struct net_device *dev) +inline static void adapter_reset(struct net_device *dev) { unsigned long timeout; elp_device *adapter = dev->priv; diff --git a/trunk/drivers/net/8139too.c b/trunk/drivers/net/8139too.c index 4c2cf7bbd252..5a4a08a7c951 100644 --- a/trunk/drivers/net/8139too.c +++ b/trunk/drivers/net/8139too.c @@ -126,14 +126,14 @@ #define USE_IO_OPS 1 #endif -/* define to 1, 2 or 3 to enable copious debugging info */ -#define RTL8139_DEBUG 0 +/* define to 1 to enable copious debugging info */ +#undef RTL8139_DEBUG /* define to 1 to disable lightweight runtime debugging checks */ #undef RTL8139_NDEBUG -#if RTL8139_DEBUG +#ifdef RTL8139_DEBUG /* note: prints function name for you */ # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args) #else diff --git a/trunk/drivers/net/Kconfig b/trunk/drivers/net/Kconfig index 8a835eb58808..534b598866b3 100644 --- a/trunk/drivers/net/Kconfig +++ b/trunk/drivers/net/Kconfig @@ -23,12 +23,9 @@ config NETDEVICES If unsure, say Y. -# All the following symbols are dependent on NETDEVICES - do not repeat -# that for each of the symbols. -if NETDEVICES - config DUMMY tristate "Dummy net driver support" + depends on NETDEVICES ---help--- This is essentially a bit-bucket device (i.e. traffic you send to this device is consigned into oblivion) with a configurable IP @@ -48,6 +45,7 @@ config DUMMY config BONDING tristate "Bonding driver support" + depends on NETDEVICES depends on INET ---help--- Say 'Y' or 'M' if you wish to be able to 'bond' multiple Ethernet @@ -65,6 +63,7 @@ config BONDING config EQUALIZER tristate "EQL (serial line load balancing) support" + depends on NETDEVICES ---help--- If you have two serial connections to some other computer (this usually requires two modems and two telephone lines) and you use @@ -84,6 +83,7 @@ config EQUALIZER config TUN tristate "Universal TUN/TAP device driver support" + depends on NETDEVICES select CRC32 ---help--- TUN/TAP provides packet reception and transmission for user space @@ -107,7 +107,7 @@ config TUN config NET_SB1000 tristate "General Instruments Surfboard 1000" - depends on PNP + depends on NETDEVICES && PNP ---help--- This is a driver for the General Instrument (also known as NextLevel) SURFboard 1000 internal @@ -129,14 +129,16 @@ config NET_SB1000 If you don't have this card, of course say N. +if NETDEVICES source "drivers/net/arcnet/Kconfig" +endif # # Ethernet # menu "Ethernet (10 or 100Mbit)" - depends on !UML + depends on NETDEVICES && !UML config NET_ETHERNET bool "Ethernet (10 or 100Mbit)" @@ -1135,7 +1137,7 @@ config IBMLANA config IBMVETH tristate "IBM LAN Virtual Ethernet support" - depends on NET_ETHERNET && PPC_PSERIES + depends on NETDEVICES && NET_ETHERNET && PPC_PSERIES ---help--- This driver supports virtual ethernet adapters on newer IBM iSeries and pSeries systems. @@ -1758,7 +1760,7 @@ endmenu # menu "Ethernet (1000 Mbit)" - depends on !UML + depends on NETDEVICES && !UML config ACENIC tristate "Alteon AceNIC/3Com 3C985/NetGear GA620 Gigabit support" @@ -2089,7 +2091,7 @@ endmenu # menu "Ethernet (10000 Mbit)" - depends on !UML + depends on NETDEVICES && !UML config IXGB tristate "Intel(R) PRO/10GbE support" @@ -2184,11 +2186,11 @@ source "drivers/s390/net/Kconfig" config ISERIES_VETH tristate "iSeries Virtual Ethernet driver support" - depends on PPC_ISERIES + depends on NETDEVICES && PPC_ISERIES config FDDI bool "FDDI driver support" - depends on (PCI || EISA) + depends on NETDEVICES && (PCI || EISA) help Fiber Distributed Data Interface is a high speed local area network design; essentially a replacement for high speed Ethernet. FDDI can @@ -2237,7 +2239,7 @@ config SKFP config HIPPI bool "HIPPI driver support (EXPERIMENTAL)" - depends on EXPERIMENTAL && INET && PCI + depends on NETDEVICES && EXPERIMENTAL && INET && PCI help HIgh Performance Parallel Interface (HIPPI) is a 800Mbit/sec and 1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI @@ -2269,7 +2271,7 @@ config ROADRUNNER_LARGE_RINGS config PLIP tristate "PLIP (parallel port) support" - depends on PARPORT + depends on NETDEVICES && PARPORT ---help--- PLIP (Parallel Line Internet Protocol) is used to create a reasonably fast mini network consisting of two (or, rarely, more) @@ -2305,6 +2307,7 @@ config PLIP config PPP tristate "PPP (point-to-point protocol) support" + depends on NETDEVICES ---help--- PPP (Point to Point Protocol) is a newer and better SLIP. It serves the same purpose: sending Internet traffic over telephone (and other @@ -2440,6 +2443,7 @@ config PPPOATM config SLIP tristate "SLIP (serial line) support" + depends on NETDEVICES ---help--- Say Y if you intend to use SLIP or CSLIP (compressed SLIP) to connect to your Internet service provider or to connect to some @@ -2506,7 +2510,7 @@ config SLIP_MODE_SLIP6 config NET_FC bool "Fibre Channel driver support" - depends on SCSI && PCI + depends on NETDEVICES && SCSI && PCI help Fibre Channel is a high speed serial protocol mainly used to connect large storage devices to the computer; it is compatible with and @@ -2519,7 +2523,7 @@ config NET_FC config SHAPER tristate "Traffic Shaper (EXPERIMENTAL)" - depends on EXPERIMENTAL + depends on NETDEVICES && EXPERIMENTAL ---help--- The traffic shaper is a virtual network device that allows you to limit the rate of outgoing data flow over some other network device. @@ -2540,13 +2544,11 @@ config SHAPER config NETCONSOLE tristate "Network console logging support (EXPERIMENTAL)" - depends on EXPERIMENTAL + depends on NETDEVICES && INET && EXPERIMENTAL ---help--- If you want to log kernel messages over the network, enable this. See for details. -endif #NETDEVICES - config NETPOLL def_bool NETCONSOLE diff --git a/trunk/drivers/net/amd8111e.c b/trunk/drivers/net/amd8111e.c index d9ba8be72af8..8618012df06a 100755 --- a/trunk/drivers/net/amd8111e.c +++ b/trunk/drivers/net/amd8111e.c @@ -1290,7 +1290,7 @@ static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *reg writel(intr0, mmio + INT0); /* Check if Receive Interrupt has occurred. */ -#ifdef CONFIG_AMD8111E_NAPI +#if CONFIG_AMD8111E_NAPI if(intr0 & RINT0){ if(netif_rx_schedule_prep(dev)){ /* Disable receive interupts */ diff --git a/trunk/drivers/net/ne.c b/trunk/drivers/net/ne.c index d209a1556b2e..6c57096aa2e1 100644 --- a/trunk/drivers/net/ne.c +++ b/trunk/drivers/net/ne.c @@ -129,9 +129,9 @@ bad_clone_list[] __initdata = { #define NESM_START_PG 0x40 /* First page of TX buffer */ #define NESM_STOP_PG 0x80 /* Last page +1 of RX ring */ -#if defined(CONFIG_PLAT_MAPPI) +#ifdef CONFIG_PLAT_MAPPI # define DCR_VAL 0x4b -#elif defined(CONFIG_PLAT_OAKS32R) +#elif CONFIG_PLAT_OAKS32R # define DCR_VAL 0x48 #else # define DCR_VAL 0x49 diff --git a/trunk/drivers/net/plip.c b/trunk/drivers/net/plip.c index 1bd22cd40c75..21537ee3a6a7 100644 --- a/trunk/drivers/net/plip.c +++ b/trunk/drivers/net/plip.c @@ -160,7 +160,7 @@ static struct net_device_stats *plip_get_stats(struct net_device *dev); static int plip_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); static int plip_preempt(void *handle); static void plip_wakeup(void *handle); - + enum plip_connection_state { PLIP_CN_NONE=0, PLIP_CN_RECEIVE, @@ -231,8 +231,8 @@ struct net_local { atomic_t kill_timer; struct semaphore killed_timer_sem; }; - -static inline void enable_parport_interrupts (struct net_device *dev) + +inline static void enable_parport_interrupts (struct net_device *dev) { if (dev->irq != -1) { @@ -242,7 +242,7 @@ static inline void enable_parport_interrupts (struct net_device *dev) } } -static inline void disable_parport_interrupts (struct net_device *dev) +inline static void disable_parport_interrupts (struct net_device *dev) { if (dev->irq != -1) { @@ -252,7 +252,7 @@ static inline void disable_parport_interrupts (struct net_device *dev) } } -static inline void write_data (struct net_device *dev, unsigned char data) +inline static void write_data (struct net_device *dev, unsigned char data) { struct parport *port = ((struct net_local *)dev->priv)->pardev->port; @@ -260,14 +260,14 @@ static inline void write_data (struct net_device *dev, unsigned char data) port->ops->write_data (port, data); } -static inline unsigned char read_status (struct net_device *dev) +inline static unsigned char read_status (struct net_device *dev) { struct parport *port = ((struct net_local *)dev->priv)->pardev->port; return port->ops->read_status (port); } - + /* Entry point of PLIP driver. Probe the hardware, and register/initialize the driver. @@ -316,7 +316,7 @@ plip_init_netdev(struct net_device *dev) spin_lock_init(&nl->lock); } - + /* Bottom half handler for the delayed request. This routine is kicked by do_timer(). Request `plip_bh' to be invoked. */ @@ -471,7 +471,7 @@ plip_bh_timeout_error(struct net_device *dev, struct net_local *nl, return TIMEOUT; } - + static int plip_none(struct net_device *dev, struct net_local *nl, struct plip_local *snd, struct plip_local *rcv) @@ -481,7 +481,7 @@ plip_none(struct net_device *dev, struct net_local *nl, /* PLIP_RECEIVE --- receive a byte(two nibbles) Returns OK on success, TIMEOUT on timeout */ -static inline int +inline static int plip_receive(unsigned short nibble_timeout, struct net_device *dev, enum plip_nibble_state *ns_p, unsigned char *data_p) { @@ -582,6 +582,7 @@ static __be16 plip_type_trans(struct sk_buff *skb, struct net_device *dev) return htons(ETH_P_802_2); } + /* PLIP_RECEIVE_PACKET --- receive a packet */ static int plip_receive_packet(struct net_device *dev, struct net_local *nl, @@ -701,7 +702,7 @@ plip_receive_packet(struct net_device *dev, struct net_local *nl, /* PLIP_SEND --- send a byte (two nibbles) Returns OK on success, TIMEOUT when timeout */ -static inline int +inline static int plip_send(unsigned short nibble_timeout, struct net_device *dev, enum plip_nibble_state *ns_p, unsigned char data) { @@ -901,7 +902,7 @@ plip_error(struct net_device *dev, struct net_local *nl, return OK; } - + /* Handle the parallel port interrupts. */ static void plip_interrupt(int irq, void *dev_id, struct pt_regs * regs) @@ -956,7 +957,7 @@ plip_interrupt(int irq, void *dev_id, struct pt_regs * regs) spin_unlock_irq(&nl->lock); } - + static int plip_tx_packet(struct sk_buff *skb, struct net_device *dev) { @@ -1237,7 +1238,7 @@ plip_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) } return 0; } - + static int parport[PLIP_MAX] = { [0 ... PLIP_MAX-1] = -1 }; static int timid; diff --git a/trunk/drivers/net/via-velocity.h b/trunk/drivers/net/via-velocity.h index d9a774b91ddc..1b70b7c97580 100644 --- a/trunk/drivers/net/via-velocity.h +++ b/trunk/drivers/net/via-velocity.h @@ -1414,7 +1414,7 @@ static inline void mac_get_cam(struct mac_regs __iomem * regs, int idx, u8 *addr * the rest of the logic from the result of sleep/wakeup */ -static inline void mac_wol_reset(struct mac_regs __iomem * regs) +inline static void mac_wol_reset(struct mac_regs __iomem * regs) { /* Turn off SWPTAG right after leaving power mode */ @@ -1811,7 +1811,7 @@ struct velocity_info { * CHECK ME: locking */ -static inline int velocity_get_ip(struct velocity_info *vptr) +inline static int velocity_get_ip(struct velocity_info *vptr) { struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr; struct in_ifaddr *ifa; diff --git a/trunk/drivers/net/wireless/airo.c b/trunk/drivers/net/wireless/airo.c index df20adcd0730..47f3c5d0203d 100644 --- a/trunk/drivers/net/wireless/airo.c +++ b/trunk/drivers/net/wireless/airo.c @@ -5013,7 +5013,7 @@ static void proc_SSID_on_close( struct inode *inode, struct file *file ) { enable_MAC(ai, &rsp, 1); } -static inline u8 hexVal(char c) { +inline static u8 hexVal(char c) { if (c>='0' && c<='9') return c -= '0'; if (c>='a' && c<='f') return c -= 'a'-10; if (c>='A' && c<='F') return c -= 'A'-10; diff --git a/trunk/drivers/oprofile/cpu_buffer.c b/trunk/drivers/oprofile/cpu_buffer.c index 026f671ea558..e9b1772a3a28 100644 --- a/trunk/drivers/oprofile/cpu_buffer.c +++ b/trunk/drivers/oprofile/cpu_buffer.c @@ -42,7 +42,8 @@ void free_cpu_buffers(void) vfree(cpu_buffer[i].buffer); } } - + + int alloc_cpu_buffers(void) { int i; @@ -73,6 +74,7 @@ int alloc_cpu_buffers(void) free_cpu_buffers(); return -ENOMEM; } + void start_cpu_work(void) { @@ -91,6 +93,7 @@ void start_cpu_work(void) } } + void end_cpu_work(void) { int i; @@ -106,6 +109,7 @@ void end_cpu_work(void) flush_scheduled_work(); } + /* Resets the cpu buffer to a sane state. */ void cpu_buffer_reset(struct oprofile_cpu_buffer * cpu_buf) { @@ -117,6 +121,7 @@ void cpu_buffer_reset(struct oprofile_cpu_buffer * cpu_buf) cpu_buf->last_task = NULL; } + /* compute number of available slots in cpu_buffer queue */ static unsigned long nr_available_slots(struct oprofile_cpu_buffer const * b) { @@ -129,6 +134,7 @@ static unsigned long nr_available_slots(struct oprofile_cpu_buffer const * b) return tail + (b->buffer_size - head) - 1; } + static void increment_head(struct oprofile_cpu_buffer * b) { unsigned long new_head = b->head_pos + 1; @@ -143,7 +149,10 @@ static void increment_head(struct oprofile_cpu_buffer * b) b->head_pos = 0; } -static inline void + + + +inline static void add_sample(struct oprofile_cpu_buffer * cpu_buf, unsigned long pc, unsigned long event) { @@ -153,12 +162,14 @@ add_sample(struct oprofile_cpu_buffer * cpu_buf, increment_head(cpu_buf); } -static inline void + +inline static void add_code(struct oprofile_cpu_buffer * buffer, unsigned long value) { add_sample(buffer, ESCAPE_CODE, value); } + /* This must be safe from any context. It's safe writing here * because of the head/tail separation of the writer and reader * of the CPU buffer. @@ -212,11 +223,13 @@ static int oprofile_begin_trace(struct oprofile_cpu_buffer * cpu_buf) return 1; } + static void oprofile_end_trace(struct oprofile_cpu_buffer * cpu_buf) { cpu_buf->tracing = 0; } + void oprofile_add_sample(struct pt_regs * const regs, unsigned long event) { struct oprofile_cpu_buffer * cpu_buf = &cpu_buffer[smp_processor_id()]; @@ -238,12 +251,14 @@ void oprofile_add_sample(struct pt_regs * const regs, unsigned long event) oprofile_end_trace(cpu_buf); } + void oprofile_add_pc(unsigned long pc, int is_kernel, unsigned long event) { struct oprofile_cpu_buffer * cpu_buf = &cpu_buffer[smp_processor_id()]; log_sample(cpu_buf, pc, is_kernel, event); } + void oprofile_add_trace(unsigned long pc) { struct oprofile_cpu_buffer * cpu_buf = &cpu_buffer[smp_processor_id()]; @@ -268,6 +283,8 @@ void oprofile_add_trace(unsigned long pc) add_sample(cpu_buf, pc, 0); } + + /* * This serves to avoid cpu buffer overflow, and makes sure * the task mortuary progresses diff --git a/trunk/drivers/pnp/pnpbios/rsparser.c b/trunk/drivers/pnp/pnpbios/rsparser.c index e305bb132c24..9001b6f0204d 100644 --- a/trunk/drivers/pnp/pnpbios/rsparser.c +++ b/trunk/drivers/pnp/pnpbios/rsparser.c @@ -11,7 +11,7 @@ #ifdef CONFIG_PCI #include #else -inline void pcibios_penalize_isa_irq(int irq, int active) {} +inline void pcibios_penalize_isa_irq(int irq) {} #endif /* CONFIG_PCI */ #include "pnpbios.h" diff --git a/trunk/drivers/s390/block/dasd.c b/trunk/drivers/s390/block/dasd.c index d5f53980749b..6527ff6f4706 100644 --- a/trunk/drivers/s390/block/dasd.c +++ b/trunk/drivers/s390/block/dasd.c @@ -7,7 +7,7 @@ * Bugreports.to..: * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999-2001 * - * $Revision: 1.165 $ + * $Revision: 1.164 $ */ #include @@ -1740,10 +1740,6 @@ dasd_exit(void) dasd_proc_exit(); #endif dasd_ioctl_exit(); - if (dasd_page_cache != NULL) { - kmem_cache_destroy(dasd_page_cache); - dasd_page_cache = NULL; - } dasd_gendisk_exit(); dasd_devmap_exit(); devfs_remove("dasd"); diff --git a/trunk/drivers/s390/block/dasd_fba.c b/trunk/drivers/s390/block/dasd_fba.c index 28cb4613b7f5..7963ae343eef 100644 --- a/trunk/drivers/s390/block/dasd_fba.c +++ b/trunk/drivers/s390/block/dasd_fba.c @@ -4,7 +4,7 @@ * Bugreports.to..: * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000 * - * $Revision: 1.40 $ + * $Revision: 1.39 $ */ #include @@ -354,8 +354,6 @@ dasd_fba_build_cp(struct dasd_device * device, struct request *req) } cqr->device = device; cqr->expires = 5 * 60 * HZ; /* 5 minutes */ - cqr->retries = 32; - cqr->buildclk = get_clock(); cqr->status = DASD_CQR_FILLED; return cqr; } diff --git a/trunk/drivers/s390/char/tape.h b/trunk/drivers/s390/char/tape.h index 01d865d93791..d04e6c2c3cc1 100644 --- a/trunk/drivers/s390/char/tape.h +++ b/trunk/drivers/s390/char/tape.h @@ -3,11 +3,10 @@ * tape device driver for 3480/3490E/3590 tapes. * * S390 and zSeries version - * Copyright (C) 2001,2005 IBM Deutschland Entwicklung GmbH, IBM Corporation + * Copyright (C) 2001,2002 IBM Deutschland Entwicklung GmbH, IBM Corporation * Author(s): Carsten Otte * Tuan Ngo-Anh * Martin Schwidefsky - * Stefan Bader */ #ifndef _TAPE_H @@ -112,7 +111,6 @@ enum tape_request_status { TAPE_REQUEST_QUEUED, /* request is queued to be processed */ TAPE_REQUEST_IN_IO, /* request is currently in IO */ TAPE_REQUEST_DONE, /* request is completed. */ - TAPE_REQUEST_CANCEL, /* request should be canceled. */ }; /* Tape CCW request */ @@ -239,9 +237,6 @@ struct tape_device { /* Block dev frontend data */ struct tape_blk_data blk_data; #endif - - /* Function to start or stop the next request later. */ - struct work_struct tape_dnr; }; /* Externals from tape_core.c */ diff --git a/trunk/drivers/s390/char/tape_core.c b/trunk/drivers/s390/char/tape_core.c index 6c52e8307dc5..0597aa0e27ee 100644 --- a/trunk/drivers/s390/char/tape_core.c +++ b/trunk/drivers/s390/char/tape_core.c @@ -3,12 +3,11 @@ * basic function of the tape device driver * * S390 and zSeries version - * Copyright (C) 2001,2005 IBM Deutschland Entwicklung GmbH, IBM Corporation + * Copyright (C) 2001,2002 IBM Deutschland Entwicklung GmbH, IBM Corporation * Author(s): Carsten Otte * Michael Holzheu * Tuan Ngo-Anh * Martin Schwidefsky - * Stefan Bader */ #include @@ -29,7 +28,7 @@ #define PRINTK_HEADER "TAPE_CORE: " static void __tape_do_irq (struct ccw_device *, unsigned long, struct irb *); -static void tape_delayed_next_request(void * data); +static void __tape_remove_request(struct tape_device *, struct tape_request *); /* * One list to contain all tape devices of all disciplines, so @@ -258,7 +257,7 @@ tape_med_state_set(struct tape_device *device, enum tape_medium_state newstate) * Stop running ccw. Has to be called with the device lock held. */ static inline int -__tape_cancel_io(struct tape_device *device, struct tape_request *request) +__tape_halt_io(struct tape_device *device, struct tape_request *request) { int retries; int rc; @@ -271,23 +270,20 @@ __tape_cancel_io(struct tape_device *device, struct tape_request *request) for (retries = 0; retries < 5; retries++) { rc = ccw_device_clear(device->cdev, (long) request); - switch (rc) { - case 0: - request->status = TAPE_REQUEST_DONE; - return 0; - case -EBUSY: - request->status = TAPE_REQUEST_CANCEL; - schedule_work(&device->tape_dnr); - return 0; - case -ENODEV: - DBF_EXCEPTION(2, "device gone, retry\n"); - break; - case -EIO: - DBF_EXCEPTION(2, "I/O error, retry\n"); - break; - default: - BUG(); + if (rc == 0) { /* Termination successful */ + request->rc = -EIO; + request->status = TAPE_REQUEST_DONE; + return 0; } + + if (rc == -ENODEV) + DBF_EXCEPTION(2, "device gone, retry\n"); + else if (rc == -EIO) + DBF_EXCEPTION(2, "I/O error, retry\n"); + else if (rc == -EBUSY) + DBF_EXCEPTION(2, "device busy, retry late\n"); + else + BUG(); } return rc; @@ -477,7 +473,6 @@ tape_alloc_device(void) *device->modeset_byte = 0; device->first_minor = -1; atomic_set(&device->ref_count, 1); - INIT_WORK(&device->tape_dnr, tape_delayed_next_request, device); return device; } @@ -713,119 +708,54 @@ tape_free_request (struct tape_request * request) kfree(request); } -static inline int -__tape_start_io(struct tape_device *device, struct tape_request *request) -{ - int rc; - -#ifdef CONFIG_S390_TAPE_BLOCK - if (request->op == TO_BLOCK) - device->discipline->check_locate(device, request); -#endif - rc = ccw_device_start( - device->cdev, - request->cpaddr, - (unsigned long) request, - 0x00, - request->options - ); - if (rc == 0) { - request->status = TAPE_REQUEST_IN_IO; - } else if (rc == -EBUSY) { - /* The common I/O subsystem is currently busy. Retry later. */ - request->status = TAPE_REQUEST_QUEUED; - schedule_work(&device->tape_dnr); - rc = 0; - } else { - /* Start failed. Remove request and indicate failure. */ - DBF_EVENT(1, "tape: start request failed with RC = %i\n", rc); - } - return rc; -} - static inline void -__tape_start_next_request(struct tape_device *device) +__tape_do_io_list(struct tape_device *device) { struct list_head *l, *n; struct tape_request *request; int rc; - DBF_LH(6, "__tape_start_next_request(%p)\n", device); + DBF_LH(6, "__tape_do_io_list(%p)\n", device); /* * Try to start each request on request queue until one is * started successful. */ list_for_each_safe(l, n, &device->req_queue) { request = list_entry(l, struct tape_request, list); - - /* - * Avoid race condition if bottom-half was triggered more than - * once. - */ - if (request->status == TAPE_REQUEST_IN_IO) - return; - - /* - * We wanted to cancel the request but the common I/O layer - * was busy at that time. This can only happen if this - * function is called by delayed_next_request. - * Otherwise we start the next request on the queue. - */ - if (request->status == TAPE_REQUEST_CANCEL) { - rc = __tape_cancel_io(device, request); - } else { - rc = __tape_start_io(device, request); +#ifdef CONFIG_S390_TAPE_BLOCK + if (request->op == TO_BLOCK) + device->discipline->check_locate(device, request); +#endif + rc = ccw_device_start(device->cdev, request->cpaddr, + (unsigned long) request, 0x00, + request->options); + if (rc == 0) { + request->status = TAPE_REQUEST_IN_IO; + break; } - if (rc == 0) - return; + /* Start failed. Remove request and indicate failure. */ + DBF_EVENT(1, "tape: DOIO failed with er = %i\n", rc); - /* Set ending status. */ + /* Set ending status and do callback. */ request->rc = rc; request->status = TAPE_REQUEST_DONE; - - /* Remove from request queue. */ - list_del(&request->list); - - /* Do callback. */ - if (request->callback != NULL) - request->callback(request, request->callback_data); + __tape_remove_request(device, request); } } static void -tape_delayed_next_request(void *data) +__tape_remove_request(struct tape_device *device, struct tape_request *request) { - struct tape_device * device; + /* Remove from request queue. */ + list_del(&request->list); - device = (struct tape_device *) data; - DBF_LH(6, "tape_delayed_next_request(%p)\n", device); - spin_lock_irq(get_ccwdev_lock(device->cdev)); - __tape_start_next_request(device); - spin_unlock_irq(get_ccwdev_lock(device->cdev)); -} - -static inline void -__tape_end_request( - struct tape_device * device, - struct tape_request * request, - int rc) -{ - DBF_LH(6, "__tape_end_request(%p, %p, %i)\n", device, request, rc); - if (request) { - request->rc = rc; - request->status = TAPE_REQUEST_DONE; - - /* Remove from request queue. */ - list_del(&request->list); - - /* Do callback. */ - if (request->callback != NULL) - request->callback(request, request->callback_data); - } + /* Do callback. */ + if (request->callback != NULL) + request->callback(request, request->callback_data); /* Start next request. */ if (!list_empty(&device->req_queue)) - __tape_start_next_request(device); + __tape_do_io_list(device); } /* @@ -882,7 +812,7 @@ tape_dump_sense_dbf(struct tape_device *device, struct tape_request *request, * the device lock held. */ static inline int -__tape_start_request(struct tape_device *device, struct tape_request *request) +__tape_do_io(struct tape_device *device, struct tape_request *request) { int rc; @@ -907,16 +837,24 @@ __tape_start_request(struct tape_device *device, struct tape_request *request) if (list_empty(&device->req_queue)) { /* No other requests are on the queue. Start this one. */ - rc = __tape_start_io(device, request); - if (rc) +#ifdef CONFIG_S390_TAPE_BLOCK + if (request->op == TO_BLOCK) + device->discipline->check_locate(device, request); +#endif + rc = ccw_device_start(device->cdev, request->cpaddr, + (unsigned long) request, 0x00, + request->options); + if (rc) { + DBF_EVENT(1, "tape: DOIO failed with rc = %i\n", rc); return rc; - + } DBF_LH(5, "Request %p added for execution.\n", request); list_add(&request->list, &device->req_queue); + request->status = TAPE_REQUEST_IN_IO; } else { DBF_LH(5, "Request %p add to queue.\n", request); - request->status = TAPE_REQUEST_QUEUED; list_add_tail(&request->list, &device->req_queue); + request->status = TAPE_REQUEST_QUEUED; } return 0; } @@ -934,7 +872,7 @@ tape_do_io_async(struct tape_device *device, struct tape_request *request) spin_lock_irq(get_ccwdev_lock(device->cdev)); /* Add request to request queue and try to start it. */ - rc = __tape_start_request(device, request); + rc = __tape_do_io(device, request); spin_unlock_irq(get_ccwdev_lock(device->cdev)); return rc; } @@ -963,7 +901,7 @@ tape_do_io(struct tape_device *device, struct tape_request *request) request->callback = __tape_wake_up; request->callback_data = &wq; /* Add request to request queue and try to start it. */ - rc = __tape_start_request(device, request); + rc = __tape_do_io(device, request); spin_unlock_irq(get_ccwdev_lock(device->cdev)); if (rc) return rc; @@ -997,7 +935,7 @@ tape_do_io_interruptible(struct tape_device *device, /* Setup callback */ request->callback = __tape_wake_up_interruptible; request->callback_data = &wq; - rc = __tape_start_request(device, request); + rc = __tape_do_io(device, request); spin_unlock_irq(get_ccwdev_lock(device->cdev)); if (rc) return rc; @@ -1006,26 +944,35 @@ tape_do_io_interruptible(struct tape_device *device, if (rc != -ERESTARTSYS) /* Request finished normally. */ return request->rc; - /* Interrupted by a signal. We have to stop the current request. */ spin_lock_irq(get_ccwdev_lock(device->cdev)); - rc = __tape_cancel_io(device, request); - spin_unlock_irq(get_ccwdev_lock(device->cdev)); + rc = __tape_halt_io(device, request); if (rc == 0) { - /* Wait for the interrupt that acknowledges the halt. */ - do { - rc = wait_event_interruptible( - wq, - (request->callback == NULL) - ); - } while (rc != -ERESTARTSYS); - DBF_EVENT(3, "IO stopped on %08x\n", device->cdev_id); rc = -ERESTARTSYS; } + spin_unlock_irq(get_ccwdev_lock(device->cdev)); return rc; } +/* + * Handle requests that return an i/o error in the irb. + */ +static inline void +tape_handle_killed_request( + struct tape_device *device, + struct tape_request *request) +{ + if(request != NULL) { + /* Set ending status. FIXME: Should the request be retried? */ + request->rc = -EIO; + request->status = TAPE_REQUEST_DONE; + __tape_remove_request(device, request); + } else { + __tape_do_io_list(device); + } +} + /* * Tape interrupt routine, called from the ccw_device layer */ @@ -1034,6 +981,7 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb) { struct tape_device *device; struct tape_request *request; + int final; int rc; device = (struct tape_device *) cdev->dev.driver_data; @@ -1048,13 +996,12 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb) /* On special conditions irb is an error pointer */ if (IS_ERR(irb)) { - /* FIXME: What to do with the request? */ switch (PTR_ERR(irb)) { case -ETIMEDOUT: PRINT_WARN("(%s): Request timed out\n", cdev->dev.bus_id); case -EIO: - __tape_end_request(device, request, -EIO); + tape_handle_killed_request(device, request); break; default: PRINT_ERR("(%s): Unexpected i/o error %li\n", @@ -1064,21 +1011,6 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb) return; } - /* - * If the condition code is not zero and the start function bit is - * still set, this is an deferred error and the last start I/O did - * not succeed. Restart the request now. - */ - if (irb->scsw.cc != 0 && (irb->scsw.fctl & SCSW_FCTL_START_FUNC)) { - PRINT_WARN("(%s): deferred cc=%i. restaring\n", - cdev->dev.bus_id, - irb->scsw.cc); - rc = __tape_start_io(device, request); - if (rc) - __tape_end_request(device, request, rc); - return; - } - /* May be an unsolicited irq */ if(request != NULL) request->rescnt = irb->scsw.count; @@ -1110,7 +1042,7 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb) * To detect these request the state will be set to TAPE_REQUEST_DONE. */ if(request != NULL && request->status == TAPE_REQUEST_DONE) { - __tape_end_request(device, request, -EIO); + __tape_remove_request(device, request); return; } @@ -1122,34 +1054,51 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb) * rc == TAPE_IO_RETRY: request finished but needs another go. * rc == TAPE_IO_STOP: request needs to get terminated. */ + final = 0; switch (rc) { - case TAPE_IO_SUCCESS: - /* Upon normal completion the device _is_ online */ - device->tape_generic_status |= GMT_ONLINE(~0); - __tape_end_request(device, request, rc); - break; - case TAPE_IO_PENDING: - break; - case TAPE_IO_RETRY: - rc = __tape_start_io(device, request); - if (rc) - __tape_end_request(device, request, rc); - break; - case TAPE_IO_STOP: - rc = __tape_cancel_io(device, request); - if (rc) - __tape_end_request(device, request, rc); - break; - default: - if (rc > 0) { - DBF_EVENT(6, "xunknownrc\n"); - PRINT_ERR("Invalid return code from discipline " - "interrupt function.\n"); - __tape_end_request(device, request, -EIO); - } else { - __tape_end_request(device, request, rc); - } - break; + case TAPE_IO_SUCCESS: + /* Upon normal completion the device _is_ online */ + device->tape_generic_status |= GMT_ONLINE(~0); + final = 1; + break; + case TAPE_IO_PENDING: + break; + case TAPE_IO_RETRY: +#ifdef CONFIG_S390_TAPE_BLOCK + if (request->op == TO_BLOCK) + device->discipline->check_locate(device, request); +#endif + rc = ccw_device_start(cdev, request->cpaddr, + (unsigned long) request, 0x00, + request->options); + if (rc) { + DBF_EVENT(1, "tape: DOIO failed with er = %i\n", rc); + final = 1; + } + break; + case TAPE_IO_STOP: + __tape_halt_io(device, request); + break; + default: + if (rc > 0) { + DBF_EVENT(6, "xunknownrc\n"); + PRINT_ERR("Invalid return code from discipline " + "interrupt function.\n"); + rc = -EIO; + } + final = 1; + break; + } + if (final) { + /* May be an unsolicited irq */ + if(request != NULL) { + /* Set ending status. */ + request->rc = rc; + request->status = TAPE_REQUEST_DONE; + __tape_remove_request(device, request); + } else { + __tape_do_io_list(device); + } } } @@ -1242,7 +1191,7 @@ tape_init (void) #ifdef DBF_LIKE_HELL debug_set_level(TAPE_DBF_AREA, 6); #endif - DBF_EVENT(3, "tape init: ($Revision: 1.54 $)\n"); + DBF_EVENT(3, "tape init: ($Revision: 1.51 $)\n"); tape_proc_init(); tapechar_init (); tapeblock_init (); @@ -1267,7 +1216,7 @@ tape_exit(void) MODULE_AUTHOR("(C) 2001 IBM Deutschland Entwicklung GmbH by Carsten Otte and " "Michael Holzheu (cotte@de.ibm.com,holzheu@de.ibm.com)"); MODULE_DESCRIPTION("Linux on zSeries channel attached " - "tape device driver ($Revision: 1.54 $)"); + "tape device driver ($Revision: 1.51 $)"); MODULE_LICENSE("GPL"); module_init(tape_init); diff --git a/trunk/drivers/s390/char/vmcp.c b/trunk/drivers/s390/char/vmcp.c index 8990d8076e7d..7f11a608a633 100644 --- a/trunk/drivers/s390/char/vmcp.c +++ b/trunk/drivers/s390/char/vmcp.c @@ -115,9 +115,9 @@ vmcp_write(struct file *file, const char __user * buff, size_t count, return -ENOMEM; } debug_text_event(vmcp_debug, 1, cmd); - session->resp_size = __cpcmd(cmd, session->response, - session->bufsize, - &session->resp_code); + session->resp_size = cpcmd(cmd, session->response, + session->bufsize, + &session->resp_code); up(&session->mutex); kfree(cmd); *ppos = 0; /* reset the file pointer after a command */ diff --git a/trunk/drivers/s390/char/vmwatchdog.c b/trunk/drivers/s390/char/vmwatchdog.c index 5473c23fcb52..22cf4fec8da9 100644 --- a/trunk/drivers/s390/char/vmwatchdog.c +++ b/trunk/drivers/s390/char/vmwatchdog.c @@ -23,7 +23,11 @@ static char vmwdt_cmd[MAX_CMDLEN] = "IPL"; static int vmwdt_conceal; -static int vmwdt_nowayout = WATCHDOG_NOWAYOUT; +#ifdef CONFIG_WATCHDOG_NOWAYOUT +static int vmwdt_nowayout = 1; +#else +static int vmwdt_nowayout = 0; +#endif MODULE_LICENSE("GPL"); MODULE_AUTHOR("Arnd Bergmann "); diff --git a/trunk/drivers/s390/cio/chsc.c b/trunk/drivers/s390/cio/chsc.c index fa3c23b80e3a..b86f94ecd874 100644 --- a/trunk/drivers/s390/cio/chsc.c +++ b/trunk/drivers/s390/cio/chsc.c @@ -1,7 +1,7 @@ /* * drivers/s390/cio/chsc.c * S/390 common I/O routines -- channel subsystem call - * $Revision: 1.120 $ + * $Revision: 1.119 $ * * Copyright (C) 1999-2002 IBM Deutschland Entwicklung GmbH, * IBM Corporation @@ -412,7 +412,11 @@ s390_process_res_acc (u8 chpid, __u16 fla, u32 fla_mask) if (chp_mask == 0) { spin_unlock_irq(&sch->lock); - continue; + + if (fla_mask != 0) + break; + else + continue; } old_lpm = sch->lpm; sch->lpm = ((sch->schib.pmcw.pim & @@ -426,7 +430,7 @@ s390_process_res_acc (u8 chpid, __u16 fla, u32 fla_mask) spin_unlock_irq(&sch->lock); put_device(&sch->dev); - if (fla_mask == 0xffff) + if (fla_mask != 0) break; } return rc; diff --git a/trunk/drivers/s390/cio/device_status.c b/trunk/drivers/s390/cio/device_status.c index 12a24d4331a2..4ab2e0d95009 100644 --- a/trunk/drivers/s390/cio/device_status.c +++ b/trunk/drivers/s390/cio/device_status.c @@ -39,14 +39,15 @@ ccw_device_msg_control_check(struct ccw_device *cdev, struct irb *irb) " ... device %04X on subchannel %04X, dev_stat " ": %02X sch_stat : %02X\n", cdev->private->devno, cdev->private->irq, - irb->scsw.dstat, irb->scsw.cstat); + cdev->private->irb.scsw.dstat, + cdev->private->irb.scsw.cstat); if (irb->scsw.cc != 3) { char dbf_text[15]; sprintf(dbf_text, "chk%x", cdev->private->irq); CIO_TRACE_EVENT(0, dbf_text); - CIO_HEX_EVENT(0, irb, sizeof (struct irb)); + CIO_HEX_EVENT(0, &cdev->private->irb, sizeof (struct irb)); } } diff --git a/trunk/drivers/s390/cio/qdio.c b/trunk/drivers/s390/cio/qdio.c index d36258d6665f..82194c4eadfb 100644 --- a/trunk/drivers/s390/cio/qdio.c +++ b/trunk/drivers/s390/cio/qdio.c @@ -432,7 +432,7 @@ tiqdio_clear_global_summary(void) /************************* OUTBOUND ROUTINES *******************************/ -static inline int +inline static int qdio_get_outbound_buffer_frontier(struct qdio_q *q) { int f,f_mod_no; @@ -510,7 +510,7 @@ qdio_get_outbound_buffer_frontier(struct qdio_q *q) } /* all buffers are processed */ -static inline int +inline static int qdio_is_outbound_q_done(struct qdio_q *q) { int no_used; @@ -532,7 +532,7 @@ qdio_is_outbound_q_done(struct qdio_q *q) return (no_used==0); } -static inline int +inline static int qdio_has_outbound_q_moved(struct qdio_q *q) { int i; @@ -552,7 +552,7 @@ qdio_has_outbound_q_moved(struct qdio_q *q) } } -static inline void +inline static void qdio_kick_outbound_q(struct qdio_q *q) { int result; @@ -641,7 +641,7 @@ qdio_kick_outbound_q(struct qdio_q *q) } } -static inline void +inline static void qdio_kick_outbound_handler(struct qdio_q *q) { int start, end, real_end, count; @@ -740,7 +740,7 @@ qdio_outbound_processing(struct qdio_q *q) /************************* INBOUND ROUTINES *******************************/ -static inline int +inline static int qdio_get_inbound_buffer_frontier(struct qdio_q *q) { int f,f_mod_no; @@ -865,7 +865,7 @@ qdio_get_inbound_buffer_frontier(struct qdio_q *q) return q->first_to_check; } -static inline int +inline static int qdio_has_inbound_q_moved(struct qdio_q *q) { int i; @@ -898,7 +898,7 @@ qdio_has_inbound_q_moved(struct qdio_q *q) } /* means, no more buffers to be filled */ -static inline int +inline static int tiqdio_is_inbound_q_done(struct qdio_q *q) { int no_used; @@ -951,7 +951,7 @@ tiqdio_is_inbound_q_done(struct qdio_q *q) return 0; } -static inline int +inline static int qdio_is_inbound_q_done(struct qdio_q *q) { int no_used; @@ -1010,7 +1010,7 @@ qdio_is_inbound_q_done(struct qdio_q *q) } } -static inline void +inline static void qdio_kick_inbound_handler(struct qdio_q *q) { int count, start, end, real_end, i; diff --git a/trunk/drivers/s390/net/qeth.h b/trunk/drivers/s390/net/qeth.h index 3a0285669adf..008e0a5d2eb3 100644 --- a/trunk/drivers/s390/net/qeth.h +++ b/trunk/drivers/s390/net/qeth.h @@ -824,7 +824,7 @@ extern struct list_head qeth_notify_list; #define QETH_CARD_IFNAME(card) (((card)->dev)? (card)->dev->name : "") -static inline __u8 +inline static __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type) { switch (link_type) { @@ -835,7 +835,7 @@ qeth_get_ipa_adp_type(enum qeth_link_types link_type) } } -static inline int +inline static int qeth_realloc_headroom(struct qeth_card *card, struct sk_buff **skb, int size) { struct sk_buff *new_skb = NULL; @@ -852,7 +852,6 @@ qeth_realloc_headroom(struct qeth_card *card, struct sk_buff **skb, int size) } return 0; } - static inline struct sk_buff * qeth_pskb_unshare(struct sk_buff *skb, int pri) { @@ -864,7 +863,8 @@ qeth_pskb_unshare(struct sk_buff *skb, int pri) return nskb; } -static inline void * + +inline static void * qeth_push_skb(struct qeth_card *card, struct sk_buff **skb, int size) { void *hdr; @@ -887,7 +887,7 @@ qeth_push_skb(struct qeth_card *card, struct sk_buff **skb, int size) } -static inline int +inline static int qeth_get_hlen(__u8 link_type) { #ifdef CONFIG_QETH_IPV6 @@ -911,7 +911,7 @@ qeth_get_hlen(__u8 link_type) #endif /* CONFIG_QETH_IPV6 */ } -static inline unsigned short +inline static unsigned short qeth_get_netdev_flags(struct qeth_card *card) { if (card->options.layer2) @@ -929,7 +929,7 @@ qeth_get_netdev_flags(struct qeth_card *card) } } -static inline int +inline static int qeth_get_initial_mtu_for_card(struct qeth_card * card) { switch (card->info.type) { @@ -950,7 +950,7 @@ qeth_get_initial_mtu_for_card(struct qeth_card * card) } } -static inline int +inline static int qeth_get_max_mtu_for_card(int cardtype) { switch (cardtype) { @@ -965,7 +965,7 @@ qeth_get_max_mtu_for_card(int cardtype) } } -static inline int +inline static int qeth_get_mtu_out_of_mpc(int cardtype) { switch (cardtype) { @@ -976,7 +976,7 @@ qeth_get_mtu_out_of_mpc(int cardtype) } } -static inline int +inline static int qeth_get_mtu_outof_framesize(int framesize) { switch (framesize) { @@ -993,7 +993,7 @@ qeth_get_mtu_outof_framesize(int framesize) } } -static inline int +inline static int qeth_mtu_is_valid(struct qeth_card * card, int mtu) { switch (card->info.type) { @@ -1008,7 +1008,7 @@ qeth_mtu_is_valid(struct qeth_card * card, int mtu) } } -static inline int +inline static int qeth_get_arphdr_type(int cardtype, int linktype) { switch (cardtype) { @@ -1027,7 +1027,7 @@ qeth_get_arphdr_type(int cardtype, int linktype) } #ifdef CONFIG_QETH_PERF_STATS -static inline int +inline static int qeth_get_micros(void) { return (int) (get_clock() >> 12); diff --git a/trunk/drivers/scsi/NCR53c406a.c b/trunk/drivers/scsi/NCR53c406a.c index 79ae73b23680..b2002ba6e2aa 100644 --- a/trunk/drivers/scsi/NCR53c406a.c +++ b/trunk/drivers/scsi/NCR53c406a.c @@ -182,13 +182,13 @@ static int irq_probe(void); static void *bios_base; #endif -#ifdef PORT_BASE +#if PORT_BASE static int port_base = PORT_BASE; #else static int port_base; #endif -#ifdef IRQ_LEV +#if IRQ_LEV static int irq_level = IRQ_LEV; #else static int irq_level = -1; /* 0 is 'no irq', so use -1 for 'uninitialized' */ diff --git a/trunk/drivers/scsi/aic7xxx/aic79xx_osm.c b/trunk/drivers/scsi/aic7xxx/aic79xx_osm.c index 329cb2331339..6466a184a141 100644 --- a/trunk/drivers/scsi/aic7xxx/aic79xx_osm.c +++ b/trunk/drivers/scsi/aic7xxx/aic79xx_osm.c @@ -1505,7 +1505,7 @@ ahd_linux_dev_reset(Scsi_Cmnd *cmd) memset(recovery_cmd, 0, sizeof(struct scsi_cmnd)); recovery_cmd->device = cmd->device; recovery_cmd->scsi_done = ahd_linux_dev_reset_complete; -#ifdef AHD_DEBUG +#if AHD_DEBUG if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) printf("%s:%d:%d:%d: Device reset called for cmd %p\n", ahd_name(ahd), cmd->device->channel, cmd->device->id, diff --git a/trunk/drivers/scsi/aic7xxx/aic79xx_pci.c b/trunk/drivers/scsi/aic7xxx/aic79xx_pci.c index 703f6e44889d..4c3bb7bb8420 100644 --- a/trunk/drivers/scsi/aic7xxx/aic79xx_pci.c +++ b/trunk/drivers/scsi/aic7xxx/aic79xx_pci.c @@ -582,7 +582,7 @@ ahd_check_extport(struct ahd_softc *ahd) } } -#ifdef AHD_DEBUG +#if AHD_DEBUG if (have_seeprom != 0 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { uint16_t *sc_data; diff --git a/trunk/drivers/scsi/dc395x.c b/trunk/drivers/scsi/dc395x.c index 929170dcd3cb..ae13c002f60d 100644 --- a/trunk/drivers/scsi/dc395x.c +++ b/trunk/drivers/scsi/dc395x.c @@ -744,7 +744,7 @@ static void free_tag(struct DeviceCtlBlk *dcb, struct ScsiReqBlk *srb) /* Find cmd in SRB list */ -static inline struct ScsiReqBlk *find_cmd(struct scsi_cmnd *cmd, +inline static struct ScsiReqBlk *find_cmd(struct scsi_cmnd *cmd, struct list_head *head) { struct ScsiReqBlk *i; diff --git a/trunk/drivers/scsi/dpt/dptsig.h b/trunk/drivers/scsi/dpt/dptsig.h index 4bf447792129..95a4cce6c892 100644 --- a/trunk/drivers/scsi/dpt/dptsig.h +++ b/trunk/drivers/scsi/dpt/dptsig.h @@ -76,7 +76,7 @@ typedef unsigned long sigLONG; #endif /* aix */ #endif /* For the Macintosh */ -#ifdef STRUCTALIGNMENTSUPPORTED +#if STRUCTALIGNMENTSUPPORTED #pragma options align=mac68k #endif @@ -332,7 +332,7 @@ typedef struct dpt_sig { #endif /* aix */ #endif /* For the Macintosh */ -#ifdef STRUCTALIGNMENTSUPPORTED +#if STRUCTALIGNMENTSUPPORTED #pragma options align=reset #endif diff --git a/trunk/drivers/scsi/dtc.c b/trunk/drivers/scsi/dtc.c index 897743b23342..ab9de39bb50b 100644 --- a/trunk/drivers/scsi/dtc.c +++ b/trunk/drivers/scsi/dtc.c @@ -92,6 +92,10 @@ #define DTC_PUBLIC_RELEASE 2 +/*#define DTCDEBUG 0x1*/ +#define DTCDEBUG_INIT 0x1 +#define DTCDEBUG_TRANSFER 0x2 + /* * The DTC3180 & 3280 boards are memory mapped. * diff --git a/trunk/drivers/scsi/dtc.h b/trunk/drivers/scsi/dtc.h index 277cd015ee4e..ed73629eb2f9 100644 --- a/trunk/drivers/scsi/dtc.h +++ b/trunk/drivers/scsi/dtc.h @@ -28,10 +28,6 @@ #ifndef DTC3280_H #define DTC3280_H -#define DTCDEBUG 0 -#define DTCDEBUG_INIT 0x1 -#define DTCDEBUG_TRANSFER 0x2 - static int dtc_abort(Scsi_Cmnd *); static int dtc_biosparam(struct scsi_device *, struct block_device *, sector_t, int*); diff --git a/trunk/drivers/scsi/fdomain.c b/trunk/drivers/scsi/fdomain.c index 3b2a5bf5c43e..aecf32dd0bde 100644 --- a/trunk/drivers/scsi/fdomain.c +++ b/trunk/drivers/scsi/fdomain.c @@ -570,7 +570,7 @@ static void do_pause(unsigned amount) /* Pause for amount*10 milliseconds */ mdelay(10*amount); } -static inline void fdomain_make_bus_idle( void ) +inline static void fdomain_make_bus_idle( void ) { outb(0, port_base + SCSI_Cntl); outb(0, port_base + SCSI_Mode_Cntl); diff --git a/trunk/drivers/scsi/initio.c b/trunk/drivers/scsi/initio.c index ea6f3c0e05d9..2094d4811d61 100644 --- a/trunk/drivers/scsi/initio.c +++ b/trunk/drivers/scsi/initio.c @@ -716,7 +716,7 @@ static int init_tulip(HCS * pCurHcb, SCB * scbp, int tul_num_scb, pCurHcb->HCS_SCSI_ID = i91unvramp->NVM_SCSIInfo[0].NVM_ChSCSIID; pCurHcb->HCS_IdMask = ~(1 << pCurHcb->HCS_SCSI_ID); -#ifdef CHK_PARITY +#if CHK_PARITY /* Enable parity error response */ TUL_WR(pCurHcb->HCS_Base + TUL_PCMD, TUL_RD(pCurHcb->HCS_Base, TUL_PCMD) | 0x40); #endif diff --git a/trunk/drivers/scsi/lpfc/lpfc_compat.h b/trunk/drivers/scsi/lpfc/lpfc_compat.h index a11f1ae7b98e..275ba34b3c9d 100644 --- a/trunk/drivers/scsi/lpfc/lpfc_compat.h +++ b/trunk/drivers/scsi/lpfc/lpfc_compat.h @@ -30,9 +30,8 @@ memcpy_toio() and memcpy_fromio() can be used. However on a big-endian host, copy 4 bytes at a time, using writel() and readl(). *******************************************************************/ -#include -#ifdef __BIG_ENDIAN +#if __BIG_ENDIAN static inline void lpfc_memcpy_to_slim(void __iomem *dest, void *src, unsigned int bytes) diff --git a/trunk/drivers/scsi/lpfc/lpfc_scsi.h b/trunk/drivers/scsi/lpfc/lpfc_scsi.h index 0fd9ba14e1b5..d8fd2010ef41 100644 --- a/trunk/drivers/scsi/lpfc/lpfc_scsi.h +++ b/trunk/drivers/scsi/lpfc/lpfc_scsi.h @@ -18,8 +18,6 @@ * included with this package. * *******************************************************************/ -#include - struct lpfc_hba; #define list_remove_head(list, entry, type, member) \ @@ -83,7 +81,7 @@ struct fcp_cmnd { /* # of bits to shift lun id to end up in right * payload word, little endian = 8, big = 16. */ -#ifdef __BIG_ENDIAN +#if __BIG_ENDIAN #define FC_LUN_SHIFT 16 #define FC_ADDR_MODE_SHIFT 24 #else /* __LITTLE_ENDIAN */ diff --git a/trunk/drivers/scsi/pas16.c b/trunk/drivers/scsi/pas16.c index 72bc947e45b6..363e0ebd4a39 100644 --- a/trunk/drivers/scsi/pas16.c +++ b/trunk/drivers/scsi/pas16.c @@ -2,7 +2,6 @@ #define PSEUDO_DMA #define FOO #define UNSAFE /* Not unsafe for PAS16 -- use it */ -#define PDEBUG 0 /* * This driver adapted from Drew Eckhardt's Trantor T128 driver diff --git a/trunk/drivers/scsi/qla2xxx/Kconfig b/trunk/drivers/scsi/qla2xxx/Kconfig index 6c73b84c6e64..fccecf67423e 100644 --- a/trunk/drivers/scsi/qla2xxx/Kconfig +++ b/trunk/drivers/scsi/qla2xxx/Kconfig @@ -2,6 +2,7 @@ config SCSI_QLA2XXX tristate default (SCSI && PCI) depends on SCSI && PCI + select SCSI_FC_ATTRS config SCSI_QLA21XX tristate "QLogic ISP2100 host adapter family support" diff --git a/trunk/drivers/scsi/qla2xxx/Makefile b/trunk/drivers/scsi/qla2xxx/Makefile index 00d2e3c21ef6..982b83604b41 100644 --- a/trunk/drivers/scsi/qla2xxx/Makefile +++ b/trunk/drivers/scsi/qla2xxx/Makefile @@ -1,4 +1,5 @@ EXTRA_CFLAGS += -DUNIQUE_FW_NAME +CONFIG_SCSI_QLA24XX=m EXTRA_CFLAGS += -DCONFIG_SCSI_QLA24XX -DCONFIG_SCSI_QLA24XX_MODULE qla2xxx-y := qla_os.o qla_init.o qla_mbx.o qla_iocb.o qla_isr.o qla_gs.o \ diff --git a/trunk/drivers/scsi/scsi_scan.c b/trunk/drivers/scsi/scsi_scan.c index 2d3c4ac475f2..ad3a5b142468 100644 --- a/trunk/drivers/scsi/scsi_scan.c +++ b/trunk/drivers/scsi/scsi_scan.c @@ -756,8 +756,7 @@ static int scsi_add_lun(struct scsi_device *sdev, char *inq_result, int *bflags) * register it and tell the rest of the kernel * about it. */ - if (scsi_sysfs_add_sdev(sdev) != 0) - return SCSI_SCAN_NO_RESPONSE; + scsi_sysfs_add_sdev(sdev); return SCSI_SCAN_LUN_PRESENT; } diff --git a/trunk/drivers/scsi/sym53c8xx_2/sym_hipd.h b/trunk/drivers/scsi/sym53c8xx_2/sym_hipd.h index 3131a6bf7ab7..c55c7a57afa0 100644 --- a/trunk/drivers/scsi/sym53c8xx_2/sym_hipd.h +++ b/trunk/drivers/scsi/sym53c8xx_2/sym_hipd.h @@ -151,16 +151,6 @@ */ #define SYM_CONF_MIN_ASYNC (40) - -/* - * MEMORY ALLOCATOR. - */ - -#define SYM_MEM_WARN 1 /* Warn on failed operations */ - -#define SYM_MEM_PAGE_ORDER 0 /* 1 PAGE maximum */ -#define SYM_MEM_CLUSTER_SHIFT (PAGE_SHIFT+SYM_MEM_PAGE_ORDER) -#define SYM_MEM_FREE_UNUSED /* Free unused pages immediately */ /* * Shortest memory chunk is (1<rx_nrfifos * pinfo->rx_fifosize) + L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize); if (is_con) { - mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8)); + mem_addr = (u8 *) m8xx_cpm_hostalloc(memsz); dma_addr = 0; } else mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr, diff --git a/trunk/drivers/serial/jsm/jsm.h b/trunk/drivers/serial/jsm/jsm.h index 18753193f59b..5bf3c45521f4 100644 --- a/trunk/drivers/serial/jsm/jsm.h +++ b/trunk/drivers/serial/jsm/jsm.h @@ -89,7 +89,7 @@ enum { #define WRITEBUFLEN ((4096) + 4) #define MYFLIPLEN N_TTY_BUF_SIZE -#define JSM_VERSION "jsm: 1.2-1-INKERNEL" +#define JSM_VERSION "jsm: 1.1-1-INKERNEL" #define JSM_PARTNUM "40002438_A-INKERNEL" struct jsm_board; diff --git a/trunk/drivers/serial/jsm/jsm_driver.c b/trunk/drivers/serial/jsm/jsm_driver.c index 7e56c7824194..cc5d21300ed3 100644 --- a/trunk/drivers/serial/jsm/jsm_driver.c +++ b/trunk/drivers/serial/jsm/jsm_driver.c @@ -22,7 +22,6 @@ * Scott H Kilau * Wendy Xiong * - * ***********************************************************************/ #include #include @@ -43,7 +42,7 @@ struct uart_driver jsm_uart_driver = { .owner = THIS_MODULE, .driver_name = JSM_DRIVER_NAME, .dev_name = "ttyn", - .major = 0, + .major = 253, .minor = JSM_MINOR_START, .nr = NR_PORTS, }; diff --git a/trunk/drivers/serial/jsm/jsm_neo.c b/trunk/drivers/serial/jsm/jsm_neo.c index 6f22b42d9337..3a11a69feb44 100644 --- a/trunk/drivers/serial/jsm/jsm_neo.c +++ b/trunk/drivers/serial/jsm/jsm_neo.c @@ -48,9 +48,8 @@ static inline void neo_pci_posting_flush(struct jsm_board *bd) static void neo_set_cts_flow_control(struct jsm_channel *ch) { - u8 ier, efr; - ier = readb(&ch->ch_neo_uart->ier); - efr = readb(&ch->ch_neo_uart->efr); + u8 ier = readb(&ch->ch_neo_uart->ier); + u8 efr = readb(&ch->ch_neo_uart->efr); jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); @@ -79,9 +78,8 @@ static void neo_set_cts_flow_control(struct jsm_channel *ch) static void neo_set_rts_flow_control(struct jsm_channel *ch) { - u8 ier, efr; - ier = readb(&ch->ch_neo_uart->ier); - efr = readb(&ch->ch_neo_uart->efr); + u8 ier = readb(&ch->ch_neo_uart->ier); + u8 efr = readb(&ch->ch_neo_uart->efr); jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); @@ -119,9 +117,8 @@ static void neo_set_rts_flow_control(struct jsm_channel *ch) static void neo_set_ixon_flow_control(struct jsm_channel *ch) { - u8 ier, efr; - ier = readb(&ch->ch_neo_uart->ier); - efr = readb(&ch->ch_neo_uart->efr); + u8 ier = readb(&ch->ch_neo_uart->ier); + u8 efr = readb(&ch->ch_neo_uart->efr); jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); @@ -156,9 +153,8 @@ static void neo_set_ixon_flow_control(struct jsm_channel *ch) static void neo_set_ixoff_flow_control(struct jsm_channel *ch) { - u8 ier, efr; - ier = readb(&ch->ch_neo_uart->ier); - efr = readb(&ch->ch_neo_uart->efr); + u8 ier = readb(&ch->ch_neo_uart->ier); + u8 efr = readb(&ch->ch_neo_uart->efr); jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); @@ -194,9 +190,8 @@ static void neo_set_ixoff_flow_control(struct jsm_channel *ch) static void neo_set_no_input_flow_control(struct jsm_channel *ch) { - u8 ier, efr; - ier = readb(&ch->ch_neo_uart->ier); - efr = readb(&ch->ch_neo_uart->efr); + u8 ier = readb(&ch->ch_neo_uart->ier); + u8 efr = readb(&ch->ch_neo_uart->efr); jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); @@ -233,9 +228,8 @@ static void neo_set_no_input_flow_control(struct jsm_channel *ch) static void neo_set_no_output_flow_control(struct jsm_channel *ch) { - u8 ier, efr; - ier = readb(&ch->ch_neo_uart->ier); - efr = readb(&ch->ch_neo_uart->efr); + u8 ier = readb(&ch->ch_neo_uart->ier); + u8 efr = readb(&ch->ch_neo_uart->efr); jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); diff --git a/trunk/drivers/usb/image/microtek.c b/trunk/drivers/usb/image/microtek.c index c84e1486054f..7d21a4f5c425 100644 --- a/trunk/drivers/usb/image/microtek.c +++ b/trunk/drivers/usb/image/microtek.c @@ -361,7 +361,8 @@ int mts_scsi_queuecommand (Scsi_Cmnd *srb, mts_scsi_cmnd_callback callback ); static void mts_transfer_cleanup( struct urb *transfer ); static void mts_do_sg(struct urb * transfer, struct pt_regs *regs); -static inline + +inline static void mts_int_submit_urb (struct urb* transfer, int pipe, void* data, diff --git a/trunk/drivers/video/Kconfig b/trunk/drivers/video/Kconfig index cde0ed097af6..04d3120f7236 100644 --- a/trunk/drivers/video/Kconfig +++ b/trunk/drivers/video/Kconfig @@ -1399,8 +1399,8 @@ config FB_TX3912 Say Y here to enable kernel support for the on-board framebuffer. config FB_G364 - bool "G364 frame buffer support" - depends on (FB = y) && (MIPS_MAGNUM_4000 || OLIVETTI_M700) + bool + depends on MIPS_MAGNUM_4000 || OLIVETTI_M700 select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT diff --git a/trunk/drivers/video/aty/radeon_base.c b/trunk/drivers/video/aty/radeon_base.c index e7e8b52014c3..47a6b12bc968 100644 --- a/trunk/drivers/video/aty/radeon_base.c +++ b/trunk/drivers/video/aty/radeon_base.c @@ -2521,11 +2521,6 @@ static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev) radeonfb_pm_exit(rinfo); - if (rinfo->mon1_EDID) - sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); - if (rinfo->mon2_EDID) - sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); - #if 0 /* restore original state * diff --git a/trunk/drivers/video/console/fbcon.c b/trunk/drivers/video/console/fbcon.c index 35c88bd7ba5e..9dd0fbccf994 100644 --- a/trunk/drivers/video/console/fbcon.c +++ b/trunk/drivers/video/console/fbcon.c @@ -275,8 +275,7 @@ static void fb_flashcursor(void *private) if (!vc || !CON_IS_VISIBLE(vc) || fbcon_is_inactive(vc, info) || - registered_fb[con2fb_map[vc->vc_num]] != info || - vc_cons[ops->currcon].d->vc_deccm != 1) + registered_fb[con2fb_map[vc->vc_num]] != info) return; acquire_console_sem(); p = &fb_display[vc->vc_num]; diff --git a/trunk/drivers/video/fbcmap.c b/trunk/drivers/video/fbcmap.c index c32a2a50bfa2..4e5ce8f7d65e 100644 --- a/trunk/drivers/video/fbcmap.c +++ b/trunk/drivers/video/fbcmap.c @@ -212,7 +212,7 @@ int fb_cmap_to_user(struct fb_cmap *from, struct fb_cmap_user *to) int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *info) { - int i, start, rc = 0; + int i, start; u16 *red, *green, *blue, *transp; u_int hred, hgreen, hblue, htransp = 0xffff; @@ -225,51 +225,75 @@ int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *info) if (start < 0 || (!info->fbops->fb_setcolreg && !info->fbops->fb_setcmap)) return -EINVAL; - if (info->fbops->fb_setcmap) { - rc = info->fbops->fb_setcmap(cmap, info); - } else { - for (i = 0; i < cmap->len; i++) { - hred = *red++; - hgreen = *green++; - hblue = *blue++; - if (transp) - htransp = *transp++; - if (info->fbops->fb_setcolreg(start++, - hred, hgreen, hblue, - htransp, info)) - break; - } + if (info->fbops->fb_setcmap) + return info->fbops->fb_setcmap(cmap, info); + for (i = 0; i < cmap->len; i++) { + hred = *red++; + hgreen = *green++; + hblue = *blue++; + if (transp) + htransp = *transp++; + if (info->fbops->fb_setcolreg(start++, + hred, hgreen, hblue, htransp, + info)) + break; } - if (rc == 0) - fb_copy_cmap(cmap, &info->cmap); - - return rc; + return 0; } int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *info) { - int rc, size = cmap->len * sizeof(u16); - struct fb_cmap umap; + int i, start; + u16 __user *red, *green, *blue, *transp; + u_int hred, hgreen, hblue, htransp = 0xffff; + + red = cmap->red; + green = cmap->green; + blue = cmap->blue; + transp = cmap->transp; + start = cmap->start; - if (cmap->start < 0 || (!info->fbops->fb_setcolreg && - !info->fbops->fb_setcmap)) + if (start < 0 || (!info->fbops->fb_setcolreg && + !info->fbops->fb_setcmap)) return -EINVAL; - memset(&umap, 0, sizeof(struct fb_cmap)); - rc = fb_alloc_cmap(&umap, cmap->len, cmap->transp != NULL); - if (rc) - return rc; - if (copy_from_user(umap.red, cmap->red, size) || - copy_from_user(umap.green, cmap->green, size) || - copy_from_user(umap.blue, cmap->blue, size) || - (cmap->transp && copy_from_user(umap.transp, cmap->transp, size))) { + /* If we can batch, do it */ + if (info->fbops->fb_setcmap && cmap->len > 1) { + struct fb_cmap umap; + int size = cmap->len * sizeof(u16); + int rc; + + memset(&umap, 0, sizeof(struct fb_cmap)); + rc = fb_alloc_cmap(&umap, cmap->len, transp != NULL); + if (rc) + return rc; + if (copy_from_user(umap.red, red, size) || + copy_from_user(umap.green, green, size) || + copy_from_user(umap.blue, blue, size) || + (transp && copy_from_user(umap.transp, transp, size))) { + rc = -EFAULT; + } + umap.start = start; + if (rc == 0) + rc = info->fbops->fb_setcmap(&umap, info); fb_dealloc_cmap(&umap); - return -EFAULT; + return rc; } - umap.start = cmap->start; - rc = fb_set_cmap(&umap, info); - fb_dealloc_cmap(&umap); - return rc; + + for (i = 0; i < cmap->len; i++, red++, blue++, green++) { + if (get_user(hred, red) || + get_user(hgreen, green) || + get_user(hblue, blue) || + (transp && get_user(htransp, transp))) + return -EFAULT; + if (info->fbops->fb_setcolreg(start++, + hred, hgreen, hblue, htransp, + info)) + return 0; + if (transp) + transp++; + } + return 0; } /** diff --git a/trunk/drivers/video/fbmem.c b/trunk/drivers/video/fbmem.c index 40784a944d05..2222de6ad844 100644 --- a/trunk/drivers/video/fbmem.c +++ b/trunk/drivers/video/fbmem.c @@ -1164,7 +1164,6 @@ static void __exit fbmem_exit(void) { class_destroy(fb_class); - unregister_chrdev(FB_MAJOR, "fb"); } module_exit(fbmem_exit); diff --git a/trunk/drivers/video/fbmon.c b/trunk/drivers/video/fbmon.c index c2718bb94949..6cd1976548d4 100644 --- a/trunk/drivers/video/fbmon.c +++ b/trunk/drivers/video/fbmon.c @@ -1241,8 +1241,6 @@ int fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info) vtotal *= 2; hfreq = pixclock/htotal; - hfreq = (hfreq + 500) / 1000 * 1000; - vfreq = hfreq/vtotal; return (vfreq < vfmin || vfreq > vfmax || diff --git a/trunk/drivers/video/fbsysfs.c b/trunk/drivers/video/fbsysfs.c index 63b505cce4ec..ddc9443254d9 100644 --- a/trunk/drivers/video/fbsysfs.c +++ b/trunk/drivers/video/fbsysfs.c @@ -242,68 +242,10 @@ static ssize_t show_virtual(struct class_device *class_device, char *buf) fb_info->var.yres_virtual); } -/* Format for cmap is "%02x%c%4x%4x%4x\n" */ -/* %02x entry %c transp %4x red %4x blue %4x green \n */ -/* 255 rows at 16 chars equals 4096 */ -/* PAGE_SIZE can be 4096 or larger */ -static ssize_t store_cmap(struct class_device *class_device, const char *buf, +static ssize_t store_cmap(struct class_device *class_device, const char * buf, size_t count) { - struct fb_info *fb_info = (struct fb_info *)class_get_devdata(class_device); - int rc, i, start, length, transp = 0; - - if ((count > 4096) || ((count % 16) != 0) || (PAGE_SIZE < 4096)) - return -EINVAL; - - if (!fb_info->fbops->fb_setcolreg && !fb_info->fbops->fb_setcmap) - return -EINVAL; - - sscanf(buf, "%02x", &start); - length = count / 16; - - for (i = 0; i < length; i++) - if (buf[i * 16 + 2] != ' ') - transp = 1; - - /* If we can batch, do it */ - if (fb_info->fbops->fb_setcmap && length > 1) { - struct fb_cmap umap; - - memset(&umap, 0, sizeof(umap)); - if ((rc = fb_alloc_cmap(&umap, length, transp))) - return rc; - - umap.start = start; - for (i = 0; i < length; i++) { - sscanf(&buf[i * 16 + 3], "%4hx", &umap.red[i]); - sscanf(&buf[i * 16 + 7], "%4hx", &umap.blue[i]); - sscanf(&buf[i * 16 + 11], "%4hx", &umap.green[i]); - if (transp) - umap.transp[i] = (buf[i * 16 + 2] != ' '); - } - rc = fb_info->fbops->fb_setcmap(&umap, fb_info); - fb_copy_cmap(&umap, &fb_info->cmap); - fb_dealloc_cmap(&umap); - - return rc; - } - for (i = 0; i < length; i++) { - u16 red, blue, green, tsp; - - sscanf(&buf[i * 16 + 3], "%4hx", &red); - sscanf(&buf[i * 16 + 7], "%4hx", &blue); - sscanf(&buf[i * 16 + 11], "%4hx", &green); - tsp = (buf[i * 16 + 2] != ' '); - if ((rc = fb_info->fbops->fb_setcolreg(start++, - red, green, blue, tsp, fb_info))) - return rc; - - fb_info->cmap.red[i] = red; - fb_info->cmap.blue[i] = blue; - fb_info->cmap.green[i] = green; - if (transp) - fb_info->cmap.transp[i] = tsp; - } +// struct fb_info *fb_info = (struct fb_info *)class_get_devdata(class_device); return 0; } @@ -311,24 +253,20 @@ static ssize_t show_cmap(struct class_device *class_device, char *buf) { struct fb_info *fb_info = (struct fb_info *)class_get_devdata(class_device); - unsigned int i; + unsigned int offset = 0, i; if (!fb_info->cmap.red || !fb_info->cmap.blue || - !fb_info->cmap.green) - return -EINVAL; - - if (PAGE_SIZE < 4096) + !fb_info->cmap.green || !fb_info->cmap.transp) return -EINVAL; - /* don't mess with the format, the buffer is PAGE_SIZE */ - /* 255 entries at 16 chars per line equals 4096 = PAGE_SIZE */ for (i = 0; i < fb_info->cmap.len; i++) { - sprintf(&buf[ i * 16], "%02x%c%4x%4x%4x\n", i + fb_info->cmap.start, - ((fb_info->cmap.transp && fb_info->cmap.transp[i]) ? '*' : ' '), - fb_info->cmap.red[i], fb_info->cmap.blue[i], - fb_info->cmap.green[i]); + offset += snprintf(buf, PAGE_SIZE - offset, + "%d,%d,%d,%d,%d\n", i + fb_info->cmap.start, + fb_info->cmap.red[i], fb_info->cmap.blue[i], + fb_info->cmap.green[i], + fb_info->cmap.transp[i]); } - return 4096; + return offset; } static ssize_t store_blank(struct class_device *class_device, const char * buf, diff --git a/trunk/drivers/video/pm2fb.c b/trunk/drivers/video/pm2fb.c index 42c17efa9fb0..5dceddedf507 100644 --- a/trunk/drivers/video/pm2fb.c +++ b/trunk/drivers/video/pm2fb.c @@ -138,27 +138,27 @@ static struct fb_var_screeninfo pm2fb_var __devinitdata = { * Utility functions */ -static inline u32 RD32(unsigned char __iomem *base, s32 off) +inline static u32 RD32(unsigned char __iomem *base, s32 off) { return fb_readl(base + off); } -static inline void WR32(unsigned char __iomem *base, s32 off, u32 v) +inline static void WR32(unsigned char __iomem *base, s32 off, u32 v) { fb_writel(v, base + off); } -static inline u32 pm2_RD(struct pm2fb_par* p, s32 off) +inline static u32 pm2_RD(struct pm2fb_par* p, s32 off) { return RD32(p->v_regs, off); } -static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v) +inline static void pm2_WR(struct pm2fb_par* p, s32 off, u32 v) { WR32(p->v_regs, off, v); } -static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx) +inline static u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx) { int index = PM2R_RD_INDEXED_DATA; switch (p->type) { @@ -174,7 +174,7 @@ static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx) return pm2_RD(p, index); } -static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v) +inline static void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v) { int index = PM2R_RD_INDEXED_DATA; switch (p->type) { @@ -190,7 +190,7 @@ static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v) pm2_WR(p, index, v); } -static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v) +inline static void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v) { pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff); mb(); @@ -200,7 +200,7 @@ static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v) #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT #define WAIT_FIFO(p,a) #else -static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a) +inline static void WAIT_FIFO(struct pm2fb_par* p, u32 a) { while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a ); mb(); diff --git a/trunk/drivers/video/riva/fbdev.c b/trunk/drivers/video/riva/fbdev.c index ae297e222681..6a9e183be41b 100644 --- a/trunk/drivers/video/riva/fbdev.c +++ b/trunk/drivers/video/riva/fbdev.c @@ -1826,7 +1826,7 @@ static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) #ifdef CONFIG_PPC_OF if (!riva_get_EDID_OF(info, pdev)) printk(PFX "could not retrieve EDID from OF\n"); -#elif defined(CONFIG_FB_RIVA_I2C) +#elif CONFIG_FB_RIVA_I2C if (!riva_get_EDID_i2c(info)) printk(PFX "could not retrieve EDID from DDC/I2C\n"); #endif diff --git a/trunk/fs/autofs4/autofs_i.h b/trunk/fs/autofs4/autofs_i.h index fca83e28edcf..9c09641ce907 100644 --- a/trunk/fs/autofs4/autofs_i.h +++ b/trunk/fs/autofs4/autofs_i.h @@ -92,7 +92,6 @@ struct autofs_wait_queue { struct autofs_sb_info { u32 magic; - struct dentry *root; struct file *pipe; pid_t oz_pgrp; int catatonic; diff --git a/trunk/fs/autofs4/inode.c b/trunk/fs/autofs4/inode.c index 0a3c05d10167..4bb14cc68040 100644 --- a/trunk/fs/autofs4/inode.c +++ b/trunk/fs/autofs4/inode.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "autofs_i.h" #include @@ -77,66 +76,6 @@ void autofs4_free_ino(struct autofs_info *ino) kfree(ino); } -/* - * Deal with the infamous "Busy inodes after umount ..." message. - * - * Clean up the dentry tree. This happens with autofs if the user - * space program goes away due to a SIGKILL, SIGSEGV etc. - */ -static void autofs4_force_release(struct autofs_sb_info *sbi) -{ - struct dentry *this_parent = sbi->root; - struct list_head *next; - - spin_lock(&dcache_lock); -repeat: - next = this_parent->d_subdirs.next; -resume: - while (next != &this_parent->d_subdirs) { - struct dentry *dentry = list_entry(next, struct dentry, d_child); - - /* Negative dentry - don`t care */ - if (!simple_positive(dentry)) { - next = next->next; - continue; - } - - if (!list_empty(&dentry->d_subdirs)) { - this_parent = dentry; - goto repeat; - } - - next = next->next; - spin_unlock(&dcache_lock); - - DPRINTK("dentry %p %.*s", - dentry, (int)dentry->d_name.len, dentry->d_name.name); - - dput(dentry); - spin_lock(&dcache_lock); - } - - if (this_parent != sbi->root) { - struct dentry *dentry = this_parent; - - next = this_parent->d_child.next; - this_parent = this_parent->d_parent; - spin_unlock(&dcache_lock); - DPRINTK("parent dentry %p %.*s", - dentry, (int)dentry->d_name.len, dentry->d_name.name); - dput(dentry); - spin_lock(&dcache_lock); - goto resume; - } - spin_unlock(&dcache_lock); - - dput(sbi->root); - sbi->root = NULL; - shrink_dcache_sb(sbi->sb); - - return; -} - static void autofs4_put_super(struct super_block *sb) { struct autofs_sb_info *sbi = autofs4_sbi(sb); @@ -146,10 +85,6 @@ static void autofs4_put_super(struct super_block *sb) if ( !sbi->catatonic ) autofs4_catatonic_mode(sbi); /* Free wait queues, close pipe */ - /* Clean up and release dangling references */ - if (sbi) - autofs4_force_release(sbi); - kfree(sbi); DPRINTK("shutting down"); @@ -264,7 +199,6 @@ int autofs4_fill_super(struct super_block *s, void *data, int silent) s->s_fs_info = sbi; sbi->magic = AUTOFS_SBI_MAGIC; - sbi->root = NULL; sbi->catatonic = 0; sbi->exp_timeout = 0; sbi->oz_pgrp = process_group(current); @@ -332,13 +266,6 @@ int autofs4_fill_super(struct super_block *s, void *data, int silent) goto fail_fput; sbi->pipe = pipe; - /* - * Take a reference to the root dentry so we get a chance to - * clean up the dentry tree on umount. - * See autofs4_force_release. - */ - sbi->root = dget(root); - /* * Success! Install the root dentry now to indicate completion. */ diff --git a/trunk/fs/ext2/ialloc.c b/trunk/fs/ext2/ialloc.c index 161f156d98c8..77e059149212 100644 --- a/trunk/fs/ext2/ialloc.c +++ b/trunk/fs/ext2/ialloc.c @@ -612,7 +612,6 @@ struct inode *ext2_new_inode(struct inode *dir, int mode) err = ext2_init_acl(inode, dir); if (err) { DQUOT_FREE_INODE(inode); - DQUOT_DROP(inode); goto fail2; } mark_inode_dirty(inode); diff --git a/trunk/fs/ext2/xattr.c b/trunk/fs/ext2/xattr.c index 0099462d4271..27982b500e84 100644 --- a/trunk/fs/ext2/xattr.c +++ b/trunk/fs/ext2/xattr.c @@ -823,7 +823,7 @@ ext2_xattr_delete_inode(struct inode *inode) void ext2_xattr_put_super(struct super_block *sb) { - mb_cache_shrink(sb->s_bdev); + mb_cache_shrink(ext2_xattr_cache, sb->s_bdev); } diff --git a/trunk/fs/ext2/xip.c b/trunk/fs/ext2/xip.c index ca7f00312388..0aa5ac159c09 100644 --- a/trunk/fs/ext2/xip.c +++ b/trunk/fs/ext2/xip.c @@ -36,7 +36,7 @@ __ext2_get_sector(struct inode *inode, sector_t offset, int create, *result = tmp.b_blocknr; /* did we get a sparse block (hole in the file)? */ - if (!tmp.b_blocknr && !rc) { + if (!(*result)) { BUG_ON(create); rc = -ENODATA; } diff --git a/trunk/fs/ext3/ialloc.c b/trunk/fs/ext3/ialloc.c index 6981bd014ede..1e6f3ea28713 100644 --- a/trunk/fs/ext3/ialloc.c +++ b/trunk/fs/ext3/ialloc.c @@ -604,14 +604,12 @@ struct inode *ext3_new_inode(handle_t *handle, struct inode * dir, int mode) err = ext3_init_acl(handle, inode, dir); if (err) { DQUOT_FREE_INODE(inode); - DQUOT_DROP(inode); goto fail2; } err = ext3_mark_inode_dirty(handle, inode); if (err) { ext3_std_error(sb, err); DQUOT_FREE_INODE(inode); - DQUOT_DROP(inode); goto fail2; } diff --git a/trunk/fs/ext3/xattr.c b/trunk/fs/ext3/xattr.c index 269c7b92db9a..3f9dfa643b19 100644 --- a/trunk/fs/ext3/xattr.c +++ b/trunk/fs/ext3/xattr.c @@ -1106,7 +1106,7 @@ ext3_xattr_delete_inode(handle_t *handle, struct inode *inode) void ext3_xattr_put_super(struct super_block *sb) { - mb_cache_shrink(sb->s_bdev); + mb_cache_shrink(ext3_xattr_cache, sb->s_bdev); } /* diff --git a/trunk/fs/fcntl.c b/trunk/fs/fcntl.c index 6fbc9d8fcc36..286a9f8f3d49 100644 --- a/trunk/fs/fcntl.c +++ b/trunk/fs/fcntl.c @@ -288,7 +288,7 @@ static long do_fcntl(int fd, unsigned int cmd, unsigned long arg, break; case F_SETLK: case F_SETLKW: - err = fcntl_setlk(fd, filp, cmd, (struct flock __user *) arg); + err = fcntl_setlk(filp, cmd, (struct flock __user *) arg); break; case F_GETOWN: /* @@ -376,8 +376,7 @@ asmlinkage long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg break; case F_SETLK64: case F_SETLKW64: - err = fcntl_setlk64(fd, filp, cmd, - (struct flock64 __user *) arg); + err = fcntl_setlk64(filp, cmd, (struct flock64 __user *) arg); break; default: err = do_fcntl(fd, cmd, arg, filp); diff --git a/trunk/fs/jffs/intrep.c b/trunk/fs/jffs/intrep.c index 456d7e6e29c2..fc589ddd0762 100644 --- a/trunk/fs/jffs/intrep.c +++ b/trunk/fs/jffs/intrep.c @@ -3397,9 +3397,6 @@ jffs_garbage_collect_thread(void *ptr) siginfo_t info; unsigned long signr = 0; - if (try_to_freeze()) - continue; - spin_lock_irq(¤t->sighand->siglock); signr = dequeue_signal(current, ¤t->blocked, &info); spin_unlock_irq(¤t->sighand->siglock); diff --git a/trunk/fs/jfs/jfs_dmap.c b/trunk/fs/jfs/jfs_dmap.c index c739626f5bf1..0732f206ca60 100644 --- a/trunk/fs/jfs/jfs_dmap.c +++ b/trunk/fs/jfs/jfs_dmap.c @@ -75,7 +75,7 @@ static void dbAllocBits(struct bmap * bmp, struct dmap * dp, s64 blkno, int nblocks); static void dbSplit(dmtree_t * tp, int leafno, int splitsz, int newval); static void dbBackSplit(dmtree_t * tp, int leafno); -static int dbJoin(dmtree_t * tp, int leafno, int newval); +static void dbJoin(dmtree_t * tp, int leafno, int newval); static void dbAdjTree(dmtree_t * tp, int leafno, int newval); static int dbAdjCtl(struct bmap * bmp, s64 blkno, int newval, int alloc, int level); @@ -98,8 +98,8 @@ static int dbExtend(struct inode *ip, s64 blkno, s64 nblocks, s64 addnblocks); static int dbFindBits(u32 word, int l2nb); static int dbFindCtl(struct bmap * bmp, int l2nb, int level, s64 * blkno); static int dbFindLeaf(dmtree_t * tp, int l2nb, int *leafidx); -static int dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno, - int nblocks); +static void dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno, + int nblocks); static int dbFreeDmap(struct bmap * bmp, struct dmap * dp, s64 blkno, int nblocks); static int dbMaxBud(u8 * cp); @@ -378,7 +378,6 @@ int dbFree(struct inode *ip, s64 blkno, s64 nblocks) /* free the blocks. */ if ((rc = dbFreeDmap(bmp, dp, blkno, nb))) { - jfs_error(ip->i_sb, "dbFree: error in block map\n"); release_metapage(mp); IREAD_UNLOCK(ipbmap); return (rc); @@ -2021,7 +2020,7 @@ static int dbFreeDmap(struct bmap * bmp, struct dmap * dp, s64 blkno, int nblocks) { s8 oldroot; - int rc = 0, word; + int rc, word; /* save the current value of the root (i.e. maximum free string) * of the dmap tree. @@ -2029,11 +2028,11 @@ static int dbFreeDmap(struct bmap * bmp, struct dmap * dp, s64 blkno, oldroot = dp->tree.stree[ROOT]; /* free the specified (blocks) bits */ - rc = dbFreeBits(bmp, dp, blkno, nblocks); + dbFreeBits(bmp, dp, blkno, nblocks); - /* if error or the root has not changed, done. */ - if (rc || (dp->tree.stree[ROOT] == oldroot)) - return (rc); + /* if the root has not changed, done. */ + if (dp->tree.stree[ROOT] == oldroot) + return (0); /* root changed. bubble the change up to the dmap control pages. * if the adjustment of the upper level control pages fails, @@ -2222,16 +2221,15 @@ static void dbAllocBits(struct bmap * bmp, struct dmap * dp, s64 blkno, * blkno - starting block number of the bits to be freed. * nblocks - number of bits to be freed. * - * RETURN VALUES: 0 for success + * RETURN VALUES: none * * serialization: IREAD_LOCK(ipbmap) or IWRITE_LOCK(ipbmap) held on entry/exit; */ -static int dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno, +static void dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno, int nblocks) { int dbitno, word, rembits, nb, nwords, wbitno, nw, agno; dmtree_t *tp = (dmtree_t *) & dp->tree; - int rc = 0; int size; /* determine the bit number and word within the dmap of the @@ -2280,10 +2278,8 @@ static int dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno, /* update the leaf for this dmap word. */ - rc = dbJoin(tp, word, - dbMaxBud((u8 *) & dp->wmap[word])); - if (rc) - return rc; + dbJoin(tp, word, + dbMaxBud((u8 *) & dp->wmap[word])); word += 1; } else { @@ -2314,9 +2310,7 @@ static int dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno, /* update the leaf. */ - rc = dbJoin(tp, word, size); - if (rc) - return rc; + dbJoin(tp, word, size); /* get the number of dmap words handled. */ @@ -2363,8 +2357,6 @@ static int dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno, } BMAP_UNLOCK(bmp); - - return 0; } @@ -2472,9 +2464,7 @@ dbAdjCtl(struct bmap * bmp, s64 blkno, int newval, int alloc, int level) } dbSplit((dmtree_t *) dcp, leafno, dcp->budmin, newval); } else { - rc = dbJoin((dmtree_t *) dcp, leafno, newval); - if (rc) - return rc; + dbJoin((dmtree_t *) dcp, leafno, newval); } /* check if the root of the current dmap control page changed due @@ -2699,7 +2689,7 @@ static void dbBackSplit(dmtree_t * tp, int leafno) * * RETURN VALUES: none */ -static int dbJoin(dmtree_t * tp, int leafno, int newval) +static void dbJoin(dmtree_t * tp, int leafno, int newval) { int budsz, buddy; s8 *leaf; @@ -2739,9 +2729,7 @@ static int dbJoin(dmtree_t * tp, int leafno, int newval) if (newval > leaf[buddy]) break; - /* It shouldn't be less */ - if (newval < leaf[buddy]) - return -EIO; + assert(newval == leaf[buddy]); /* check which (leafno or buddy) is the left buddy. * the left buddy gets to claim the blocks resulting @@ -2773,8 +2761,6 @@ static int dbJoin(dmtree_t * tp, int leafno, int newval) /* update the leaf value. */ dbAdjTree(tp, leafno, newval); - - return 0; } diff --git a/trunk/fs/jfs/jfs_dtree.c b/trunk/fs/jfs/jfs_dtree.c index 404f33eae507..73b5fc7eda80 100644 --- a/trunk/fs/jfs/jfs_dtree.c +++ b/trunk/fs/jfs/jfs_dtree.c @@ -381,12 +381,9 @@ static u32 add_index(tid_t tid, struct inode *ip, s64 bn, int slot) * It's time to move the inline table to an external * page and begin to build the xtree */ - if (DQUOT_ALLOC_BLOCK(ip, sbi->nbperpage)) - goto clean_up; - if (dbAlloc(ip, 0, sbi->nbperpage, &xaddr)) { - DQUOT_FREE_BLOCK(ip, sbi->nbperpage); - goto clean_up; - } + if (DQUOT_ALLOC_BLOCK(ip, sbi->nbperpage) || + dbAlloc(ip, 0, sbi->nbperpage, &xaddr)) + goto clean_up; /* No space */ /* * Save the table, we're going to overwrite it with the @@ -400,15 +397,13 @@ static u32 add_index(tid_t tid, struct inode *ip, s64 bn, int slot) xtInitRoot(tid, ip); /* - * Add the first block to the xtree + * Allocate the first block & add it to the xtree */ if (xtInsert(tid, ip, 0, 0, sbi->nbperpage, &xaddr, 0)) { /* This really shouldn't fail */ jfs_warn("add_index: xtInsert failed!"); memcpy(&jfs_ip->i_dirtable, temp_table, sizeof (temp_table)); - dbFree(ip, xaddr, sbi->nbperpage); - DQUOT_FREE_BLOCK(ip, sbi->nbperpage); goto clean_up; } ip->i_size = PSIZE; diff --git a/trunk/fs/jfs/jfs_logmgr.c b/trunk/fs/jfs/jfs_logmgr.c index 22815e88e7cc..79d07624bfe1 100644 --- a/trunk/fs/jfs/jfs_logmgr.c +++ b/trunk/fs/jfs/jfs_logmgr.c @@ -1030,8 +1030,7 @@ static int lmLogSync(struct jfs_log * log, int nosyncwait) * starting until all current transactions are completed * by setting syncbarrier flag. */ - if (!test_bit(log_SYNCBARRIER, &log->flag) && - (written > LOGSYNC_BARRIER(logsize)) && log->active) { + if (written > LOGSYNC_BARRIER(logsize) && logsize > 32 * LOGPSIZE) { set_bit(log_SYNCBARRIER, &log->flag); jfs_info("log barrier on: lsn=0x%x syncpt=0x%x", lsn, log->syncpt); diff --git a/trunk/fs/jfs/jfs_metapage.c b/trunk/fs/jfs/jfs_metapage.c index 13d7e3f1feb4..6c5485d16c39 100644 --- a/trunk/fs/jfs/jfs_metapage.c +++ b/trunk/fs/jfs/jfs_metapage.c @@ -561,6 +561,7 @@ static int metapage_releasepage(struct page *page, int gfp_mask) dump_mem("page", page, sizeof(struct page)); dump_stack(); } + WARN_ON(mp->lsn); if (mp->lsn) remove_from_logsync(mp); remove_metapage(page, mp); @@ -640,7 +641,7 @@ struct metapage *__get_metapage(struct inode *inode, unsigned long lblock, } else { page = read_cache_page(mapping, page_index, (filler_t *)mapping->a_ops->readpage, NULL); - if (IS_ERR(page) || !PageUptodate(page)) { + if (IS_ERR(page)) { jfs_err("read_cache_page failed!"); return NULL; } @@ -782,6 +783,14 @@ void release_metapage(struct metapage * mp) if (test_bit(META_discard, &mp->flag) && !mp->count) { clear_page_dirty(page); ClearPageUptodate(page); +#ifdef _NOT_YET + if (page->mapping) { + /* Remove from page cache and page cache reference */ + remove_from_page_cache(page); + page_cache_release(page); + metapage_releasepage(page, 0); + } +#endif } #else /* Try to keep metapages from using up too much memory */ diff --git a/trunk/fs/locks.c b/trunk/fs/locks.c index 11956b6179ff..29fa5da6c117 100644 --- a/trunk/fs/locks.c +++ b/trunk/fs/locks.c @@ -1591,8 +1591,7 @@ int fcntl_getlk(struct file *filp, struct flock __user *l) /* Apply the lock described by l to an open file descriptor. * This implements both the F_SETLK and F_SETLKW commands of fcntl(). */ -int fcntl_setlk(unsigned int fd, struct file *filp, unsigned int cmd, - struct flock __user *l) +int fcntl_setlk(struct file *filp, unsigned int cmd, struct flock __user *l) { struct file_lock *file_lock = locks_alloc_lock(); struct flock flock; @@ -1621,7 +1620,6 @@ int fcntl_setlk(unsigned int fd, struct file *filp, unsigned int cmd, goto out; } -again: error = flock_to_posix_lock(filp, file_lock, &flock); if (error) goto out; @@ -1650,33 +1648,25 @@ int fcntl_setlk(unsigned int fd, struct file *filp, unsigned int cmd, if (error) goto out; - if (filp->f_op && filp->f_op->lock != NULL) + if (filp->f_op && filp->f_op->lock != NULL) { error = filp->f_op->lock(filp, cmd, file_lock); - else { - for (;;) { - error = __posix_lock_file(inode, file_lock); - if ((error != -EAGAIN) || (cmd == F_SETLK)) - break; - error = wait_event_interruptible(file_lock->fl_wait, - !file_lock->fl_next); - if (!error) - continue; + goto out; + } - locks_delete_block(file_lock); + for (;;) { + error = __posix_lock_file(inode, file_lock); + if ((error != -EAGAIN) || (cmd == F_SETLK)) break; - } - } + error = wait_event_interruptible(file_lock->fl_wait, + !file_lock->fl_next); + if (!error) + continue; - /* - * Attempt to detect a close/fcntl race and recover by - * releasing the lock that was just acquired. - */ - if (!error && fcheck(fd) != filp && flock.l_type != F_UNLCK) { - flock.l_type = F_UNLCK; - goto again; + locks_delete_block(file_lock); + break; } -out: + out: locks_free_lock(file_lock); return error; } @@ -1734,8 +1724,7 @@ int fcntl_getlk64(struct file *filp, struct flock64 __user *l) /* Apply the lock described by l to an open file descriptor. * This implements both the F_SETLK and F_SETLKW commands of fcntl(). */ -int fcntl_setlk64(unsigned int fd, struct file *filp, unsigned int cmd, - struct flock64 __user *l) +int fcntl_setlk64(struct file *filp, unsigned int cmd, struct flock64 __user *l) { struct file_lock *file_lock = locks_alloc_lock(); struct flock64 flock; @@ -1764,7 +1753,6 @@ int fcntl_setlk64(unsigned int fd, struct file *filp, unsigned int cmd, goto out; } -again: error = flock64_to_posix_lock(filp, file_lock, &flock); if (error) goto out; @@ -1793,30 +1781,22 @@ int fcntl_setlk64(unsigned int fd, struct file *filp, unsigned int cmd, if (error) goto out; - if (filp->f_op && filp->f_op->lock != NULL) + if (filp->f_op && filp->f_op->lock != NULL) { error = filp->f_op->lock(filp, cmd, file_lock); - else { - for (;;) { - error = __posix_lock_file(inode, file_lock); - if ((error != -EAGAIN) || (cmd == F_SETLK64)) - break; - error = wait_event_interruptible(file_lock->fl_wait, - !file_lock->fl_next); - if (!error) - continue; + goto out; + } - locks_delete_block(file_lock); + for (;;) { + error = __posix_lock_file(inode, file_lock); + if ((error != -EAGAIN) || (cmd == F_SETLK64)) break; - } - } + error = wait_event_interruptible(file_lock->fl_wait, + !file_lock->fl_next); + if (!error) + continue; - /* - * Attempt to detect a close/fcntl race and recover by - * releasing the lock that was just acquired. - */ - if (!error && fcheck(fd) != filp && flock.l_type != F_UNLCK) { - flock.l_type = F_UNLCK; - goto again; + locks_delete_block(file_lock); + break; } out: @@ -1908,7 +1888,12 @@ void locks_remove_flock(struct file *filp) while ((fl = *before) != NULL) { if (fl->fl_file == filp) { - if (IS_FLOCK(fl)) { + /* + * We might have a POSIX lock that was created at the same time + * the filp was closed for the last time. Just remove that too, + * regardless of ownership, since nobody can own it. + */ + if (IS_FLOCK(fl) || IS_POSIX(fl)) { locks_delete_lock(before); continue; } diff --git a/trunk/fs/mbcache.c b/trunk/fs/mbcache.c index b002a088857d..c7170b9221a3 100644 --- a/trunk/fs/mbcache.c +++ b/trunk/fs/mbcache.c @@ -316,10 +316,11 @@ mb_cache_create(const char *name, struct mb_cache_op *cache_op, * currently in use cannot be freed, and thus remain in the cache. All others * are freed. * + * @cache: which cache to shrink * @bdev: which device's cache entries to shrink */ void -mb_cache_shrink(struct block_device *bdev) +mb_cache_shrink(struct mb_cache *cache, struct block_device *bdev) { LIST_HEAD(free_list); struct list_head *l, *ltmp; diff --git a/trunk/fs/ntfs/sysctl.h b/trunk/fs/ntfs/sysctl.h index c8064cae8f17..df749cc0aac8 100644 --- a/trunk/fs/ntfs/sysctl.h +++ b/trunk/fs/ntfs/sysctl.h @@ -26,7 +26,7 @@ #include -#if defined(DEBUG) && defined(CONFIG_SYSCTL) +#if (DEBUG && CONFIG_SYSCTL) extern int ntfs_sysctl(int add); diff --git a/trunk/fs/reiserfs/inode.c b/trunk/fs/reiserfs/inode.c index d9f614a57731..1aaf2c7d44e6 100644 --- a/trunk/fs/reiserfs/inode.c +++ b/trunk/fs/reiserfs/inode.c @@ -1980,17 +1980,7 @@ int reiserfs_new_inode(struct reiserfs_transaction_handle *th, out_inserted_sd: inode->i_nlink = 0; th->t_trans_id = 0; /* so the caller can't use this handle later */ - - /* If we were inheriting an ACL, we need to release the lock so that - * iput doesn't deadlock in reiserfs_delete_xattrs. The locking - * code really needs to be reworked, but this will take care of it - * for now. -jeffm */ - if (REISERFS_I(dir)->i_acl_default) { - reiserfs_write_unlock_xattrs(dir->i_sb); - iput(inode); - reiserfs_write_lock_xattrs(dir->i_sb); - } else - iput(inode); + iput(inode); return err; } diff --git a/trunk/fs/reiserfs/journal.c b/trunk/fs/reiserfs/journal.c index ca7989b04be3..c66c27ec4100 100644 --- a/trunk/fs/reiserfs/journal.c +++ b/trunk/fs/reiserfs/journal.c @@ -556,14 +556,14 @@ static inline void insert_journal_hash(struct reiserfs_journal_cnode **table, } /* lock the current transaction */ -static inline void lock_journal(struct super_block *p_s_sb) +inline static void lock_journal(struct super_block *p_s_sb) { PROC_INFO_INC(p_s_sb, journal.lock_journal); down(&SB_JOURNAL(p_s_sb)->j_lock); } /* unlock the current transaction */ -static inline void unlock_journal(struct super_block *p_s_sb) +inline static void unlock_journal(struct super_block *p_s_sb) { up(&SB_JOURNAL(p_s_sb)->j_lock); } diff --git a/trunk/fs/reiserfs/xattr.c b/trunk/fs/reiserfs/xattr.c index 87ac9dc8b381..e386d3db3051 100644 --- a/trunk/fs/reiserfs/xattr.c +++ b/trunk/fs/reiserfs/xattr.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/include/asm-cris/arch-v10/atomic.h b/trunk/include/asm-cris/arch-v10/atomic.h deleted file mode 100644 index 6ef5e7d09024..000000000000 --- a/trunk/include/asm-cris/arch-v10/atomic.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_ATOMIC__ -#define __ASM_CRIS_ARCH_ATOMIC__ - -#define cris_atomic_save(addr, flags) local_irq_save(flags); -#define cris_atomic_restore(addr, flags) local_irq_restore(flags); - -#endif diff --git a/trunk/include/asm-cris/arch-v10/bitops.h b/trunk/include/asm-cris/arch-v10/bitops.h index b73f5396e5a6..21b7ae8c9bb3 100644 --- a/trunk/include/asm-cris/arch-v10/bitops.h +++ b/trunk/include/asm-cris/arch-v10/bitops.h @@ -51,7 +51,7 @@ extern inline unsigned long ffz(unsigned long w) * * Undefined if no bit exists, so code should check against 0 first. */ -extern inline unsigned long __ffs(unsigned long word) +extern __inline__ unsigned long __ffs(unsigned long word) { return cris_swapnwbrlz(~word); } diff --git a/trunk/include/asm-cris/arch-v10/dma.h b/trunk/include/asm-cris/arch-v10/dma.h index ecb9dba6fa4f..9e078b9bc934 100644 --- a/trunk/include/asm-cris/arch-v10/dma.h +++ b/trunk/include/asm-cris/arch-v10/dma.h @@ -44,31 +44,3 @@ #define USB_RX_DMA_NBR 9 #endif - -enum dma_owner -{ - dma_eth, - dma_ser0, - dma_ser1, /* Async and sync */ - dma_ser2, - dma_ser3, /* Async and sync */ - dma_ata, - dma_par0, - dma_par1, - dma_ext0, - dma_ext1, - dma_int6, - dma_int7, - dma_usb, - dma_scsi0, - dma_scsi1 -}; - -/* Masks used by cris_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR (1<<0) -#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR) - -int cris_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, enum dma_owner owner); - -void cris_free_dma(unsigned int dmanr, const char * device_id); diff --git a/trunk/include/asm-cris/arch-v10/elf.h b/trunk/include/asm-cris/arch-v10/elf.h index 1c38ee728b17..2a2201ca538e 100644 --- a/trunk/include/asm-cris/arch-v10/elf.h +++ b/trunk/include/asm-cris/arch-v10/elf.h @@ -1,16 +1,6 @@ #ifndef __ASMCRIS_ARCH_ELF_H #define __ASMCRIS_ARCH_ELF_H -#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - /* * ELF register definitions.. */ diff --git a/trunk/include/asm-cris/arch-v10/ide.h b/trunk/include/asm-cris/arch-v10/ide.h deleted file mode 100644 index 8cf2d7cb22ac..000000000000 --- a/trunk/include/asm-cris/arch-v10/ide.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * linux/include/asm-cris/ide.h - * - * Copyright (C) 2000, 2001, 2002 Axis Communications AB - * - * Authors: Bjorn Wesen - * - */ - -/* - * This file contains the ETRAX 100LX specific IDE code. - */ - -#ifndef __ASMCRIS_IDE_H -#define __ASMCRIS_IDE_H - -#ifdef __KERNEL__ - -#include -#include -#include - - -/* ETRAX 100 can support 4 IDE busses on the same pins (serialized) */ - -#define MAX_HWIFS 4 - -extern __inline__ int ide_default_irq(unsigned long base) -{ - /* all IDE busses share the same IRQ, number 4. - * this has the side-effect that ide-probe.c will cluster our 4 interfaces - * together in a hwgroup, and will serialize accesses. this is good, because - * we can't access more than one interface at the same time on ETRAX100. - */ - return 4; -} - -extern __inline__ unsigned long ide_default_io_base(int index) -{ - /* we have no real I/O base address per interface, since all go through the - * same register. but in a bitfield in that register, we have the i/f number. - * so we can use the io_base to remember that bitfield. - */ - static const unsigned long io_bases[MAX_HWIFS] = { - IO_FIELD(R_ATA_CTRL_DATA, sel, 0), - IO_FIELD(R_ATA_CTRL_DATA, sel, 1), - IO_FIELD(R_ATA_CTRL_DATA, sel, 2), - IO_FIELD(R_ATA_CTRL_DATA, sel, 3) - }; - return io_bases[index]; -} - -/* this is called once for each interface, to setup the port addresses. data_port is the result - * of the ide_default_io_base call above. ctrl_port will be 0, but that is don't care for us. - */ - -extern __inline__ void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq) -{ - int i; - - /* fill in ports for ATA addresses 0 to 7 */ - - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { - hw->io_ports[i] = data_port | - IO_FIELD(R_ATA_CTRL_DATA, addr, i) | - IO_STATE(R_ATA_CTRL_DATA, cs0, active); - } - - /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */ - - hw->io_ports[IDE_CONTROL_OFFSET] = data_port | - IO_FIELD(R_ATA_CTRL_DATA, addr, 6) | - IO_STATE(R_ATA_CTRL_DATA, cs1, active); - - /* whats this for ? */ - - hw->io_ports[IDE_IRQ_OFFSET] = 0; -} - -extern __inline__ void ide_init_default_hwifs(void) -{ - hw_regs_t hw; - int index; - - for(index = 0; index < MAX_HWIFS; index++) { - ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL); - hw.irq = ide_default_irq(ide_default_io_base(index)); - ide_register_hw(&hw, NULL); - } -} - -/* some configuration options we don't need */ - -#undef SUPPORT_VLB_SYNC -#define SUPPORT_VLB_SYNC 0 - -#endif /* __KERNEL__ */ - -#endif /* __ASMCRIS_IDE_H */ diff --git a/trunk/include/asm-cris/arch-v10/io.h b/trunk/include/asm-cris/arch-v10/io.h index dd39198ec67d..0bc38a0313c1 100644 --- a/trunk/include/asm-cris/arch-v10/io.h +++ b/trunk/include/asm-cris/arch-v10/io.h @@ -6,7 +6,6 @@ /* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ -extern unsigned long gen_config_ii_shadow; extern unsigned long port_g_data_shadow; extern unsigned char port_pa_dir_shadow; extern unsigned char port_pa_data_shadow; diff --git a/trunk/include/asm-cris/arch-v10/io_interface_mux.h b/trunk/include/asm-cris/arch-v10/io_interface_mux.h deleted file mode 100644 index d92500080883..000000000000 --- a/trunk/include/asm-cris/arch-v10/io_interface_mux.h +++ /dev/null @@ -1,75 +0,0 @@ -/* IO interface mux allocator for ETRAX100LX. - * Copyright 2004, Axis Communications AB - * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $ - */ - - -#ifndef _IO_INTERFACE_MUX_H -#define _IO_INTERFACE_MUX_H - - -/* C.f. ETRAX100LX Designer's Reference 20.9 */ - -/* The order in enum must match the order of interfaces[] in - * io_interface_mux.c */ -enum cris_io_interface { - /* Begin Non-multiplexed interfaces */ - if_eth = 0, - if_serial_0, - /* End Non-multiplexed interfaces */ - if_serial_1, - if_serial_2, - if_serial_3, - if_sync_serial_1, - if_sync_serial_3, - if_shared_ram, - if_shared_ram_w, - if_par_0, - if_par_1, - if_par_w, - if_scsi8_0, - if_scsi8_1, - if_scsi_w, - if_ata, - if_csp, - if_i2c, - if_usb_1, - if_usb_2, - /* GPIO pins */ - if_gpio_grp_a, - if_gpio_grp_b, - if_gpio_grp_c, - if_gpio_grp_d, - if_gpio_grp_e, - if_gpio_grp_f, - if_max_interfaces, - if_unclaimed -}; - -int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id); - -void cris_free_io_interface(enum cris_io_interface ioif); - -/* port can be 'a', 'b' or 'g' */ -int cris_io_interface_allocate_pins(const enum cris_io_interface ioif, - const char port, - const unsigned start_bit, - const unsigned stop_bit); - -/* port can be 'a', 'b' or 'g' */ -int cris_io_interface_free_pins(const enum cris_io_interface ioif, - const char port, - const unsigned start_bit, - const unsigned stop_bit); - -int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)); - -void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)); - -#endif /* _IO_INTERFACE_MUX_H */ diff --git a/trunk/include/asm-cris/arch-v10/irq.h b/trunk/include/asm-cris/arch-v10/irq.h index 4fa8945b0263..a2a6e1533ea0 100644 --- a/trunk/include/asm-cris/arch-v10/irq.h +++ b/trunk/include/asm-cris/arch-v10/irq.h @@ -74,9 +74,12 @@ struct etrax_interrupt_vector { }; extern struct etrax_interrupt_vector *etrax_irv; -void set_int_vector(int n, irqvectptr addr); +void set_int_vector(int n, irqvectptr addr, irqvectptr saddr); void set_break_vector(int n, irqvectptr addr); +#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr)); +#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr)); + #define __STR(x) #x #define STR(x) __STR(x) @@ -118,17 +121,26 @@ void set_break_vector(int n, irqvectptr addr); #define BUILD_IRQ(nr,mask) \ void IRQ_NAME(nr); \ +void sIRQ_NAME(nr); \ +void BAD_IRQ_NAME(nr); \ __asm__ ( \ ".text\n\t" \ "IRQ" #nr "_interrupt:\n\t" \ SAVE_ALL \ + "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \ BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ "moveq "#nr",$r10\n\t" \ "move.d $sp,$r11\n\t" \ "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ UNBLOCK_IRQ(mask) \ "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t"); + "jump ret_from_intr\n\t" \ + "bad_IRQ" #nr "_interrupt:\n\t" \ + "push $r0\n\t" \ + BLOCK_IRQ(mask,nr) \ + "pop $r0\n\t" \ + "reti\n\t" \ + "nop\n"); /* This is subtle. The timer interrupt is crucial and it should not be disabled for * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would @@ -147,14 +159,23 @@ __asm__ ( \ #define BUILD_TIMER_IRQ(nr,mask) \ void IRQ_NAME(nr); \ +void sIRQ_NAME(nr); \ +void BAD_IRQ_NAME(nr); \ __asm__ ( \ ".text\n\t" \ "IRQ" #nr "_interrupt:\n\t" \ SAVE_ALL \ + "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \ "moveq "#nr",$r10\n\t" \ "move.d $sp,$r11\n\t" \ "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t"); + "jump ret_from_intr\n\t" \ + "bad_IRQ" #nr "_interrupt:\n\t" \ + "push $r0\n\t" \ + BLOCK_IRQ(mask,nr) \ + "pop $r0\n\t" \ + "reti\n\t" \ + "nop\n"); #endif diff --git a/trunk/include/asm-cris/arch-v10/memmap.h b/trunk/include/asm-cris/arch-v10/memmap.h deleted file mode 100644 index 13f3b971407f..000000000000 --- a/trunk/include/asm-cris/arch-v10/memmap.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/trunk/include/asm-cris/arch-v10/mmu.h b/trunk/include/asm-cris/arch-v10/mmu.h index df84f1716e6b..d18aa00e50bc 100644 --- a/trunk/include/asm-cris/arch-v10/mmu.h +++ b/trunk/include/asm-cris/arch-v10/mmu.h @@ -7,10 +7,7 @@ /* type used in struct mm to couple an MMU context to an active mm */ -typedef struct -{ - unsigned int page_id; -} mm_context_t; +typedef unsigned int mm_context_t; /* kernel memory segments */ diff --git a/trunk/include/asm-cris/arch-v10/offset.h b/trunk/include/asm-cris/arch-v10/offset.h index 675b51d85639..fcbd77eab281 100644 --- a/trunk/include/asm-cris/arch-v10/offset.h +++ b/trunk/include/asm-cris/arch-v10/offset.h @@ -25,7 +25,7 @@ #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ #define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ -#define TASK_pid 141 /* offsetof(struct task_struct, pid) */ +#define TASK_pid 133 /* offsetof(struct task_struct, pid) */ #define LCLONE_VM 256 /* CLONE_VM */ #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ diff --git a/trunk/include/asm-cris/arch-v10/processor.h b/trunk/include/asm-cris/arch-v10/processor.h index e23df8dc96e8..9355d8675a58 100644 --- a/trunk/include/asm-cris/arch-v10/processor.h +++ b/trunk/include/asm-cris/arch-v10/processor.h @@ -59,12 +59,4 @@ struct thread_struct { wrusp(usp); \ } while(0) -/* Called when handling a kernel bus fault fixup. - * - * After a fixup we do not want to return by restoring the CPU-state - * anymore, so switch frame-types (see ptrace.h) - */ -#define arch_fixup(regs) \ - regs->frametype = CRIS_FRAME_NORMAL; - #endif diff --git a/trunk/include/asm-cris/arch-v10/system.h b/trunk/include/asm-cris/arch-v10/system.h index 6cc35642b8ab..781ca30229a8 100644 --- a/trunk/include/asm-cris/arch-v10/system.h +++ b/trunk/include/asm-cris/arch-v10/system.h @@ -11,8 +11,6 @@ extern inline unsigned long rdvr(void) { return vr; } -#define cris_machine_name "cris" - /* read/write the user-mode stackpointer */ extern inline unsigned long rdusp(void) { diff --git a/trunk/include/asm-cris/arch-v32/arbiter.h b/trunk/include/asm-cris/arch-v32/arbiter.h deleted file mode 100644 index dba3c285cacd..000000000000 --- a/trunk/include/asm-cris/arch-v32/arbiter.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum -{ - arbiter_all_dmas = 0x3ff, - arbiter_cpu = 0xc00, - arbiter_all_clients = 0x3fff -}; - -enum -{ - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -int crisv32_arbiter_allocate_bandwith(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback* cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/trunk/include/asm-cris/arch-v32/atomic.h b/trunk/include/asm-cris/arch-v32/atomic.h deleted file mode 100644 index bbfb7a5ae315..000000000000 --- a/trunk/include/asm-cris/arch-v32/atomic.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_ATOMIC__ -#define __ASM_CRIS_ARCH_ATOMIC__ - -#include - -extern void cris_spin_unlock(void *l, int val); -extern void cris_spin_lock(void *l); -extern int cris_spin_trylock(void* l); - -#ifndef CONFIG_SMP -#define cris_atomic_save(addr, flags) local_irq_save(flags); -#define cris_atomic_restore(addr, flags) local_irq_restore(flags); -#else - -extern spinlock_t cris_atomic_locks[]; -#define LOCK_COUNT 128 -#define HASH_ADDR(a) (((int)a) & 127) - -#define cris_atomic_save(addr, flags) \ - local_irq_save(flags); \ - cris_spin_lock((void*)&cris_atomic_locks[HASH_ADDR(addr)].lock); - -#define cris_atomic_restore(addr, flags) \ - { \ - spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \ - __asm__ volatile ("move.d %1,%0" \ - : "=m" (lock->lock) \ - : "r" (1) \ - : "memory"); \ - local_irq_restore(flags); \ - } - -#endif - -#endif - diff --git a/trunk/include/asm-cris/arch-v32/bitops.h b/trunk/include/asm-cris/arch-v32/bitops.h deleted file mode 100644 index e40a58d3b862..000000000000 --- a/trunk/include/asm-cris/arch-v32/bitops.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_BITOPS_H -#define _ASM_CRIS_ARCH_BITOPS_H - -/* - * Helper functions for the core of the ff[sz] functions. They compute the - * number of leading zeroes of a bits-in-byte, byte-in-word and - * word-in-dword-swapped number. They differ in that the first function also - * inverts all bits in the input. - */ - -extern inline unsigned long -cris_swapnwbrlz(unsigned long w) -{ - unsigned long res; - - __asm__ __volatile__ ("swapnwbr %0\n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - - return res; -} - -extern inline unsigned long -cris_swapwbrlz(unsigned long w) -{ - unsigned long res; - - __asm__ __volatile__ ("swapwbr %0\n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - - return res; -} - -/* - * Find First Zero in word. Undefined if no zero exist, so the caller should - * check against ~0 first. - */ -extern inline unsigned long -ffz(unsigned long w) -{ - return cris_swapnwbrlz(w); -} - -/* - * Find First Set bit in word. Undefined if no 1 exist, so the caller - * should check against 0 first. - */ -extern inline unsigned long -__ffs(unsigned long w) -{ - return cris_swapnwbrlz(~w); -} - -/* - * Find First Bit that is set. - */ -extern inline unsigned long -kernel_ffs(unsigned long w) -{ - return w ? cris_swapwbrlz (w) + 1 : 0; -} - -#endif /* _ASM_CRIS_ARCH_BITOPS_H */ diff --git a/trunk/include/asm-cris/arch-v32/byteorder.h b/trunk/include/asm-cris/arch-v32/byteorder.h deleted file mode 100644 index 74846ee6cf99..000000000000 --- a/trunk/include/asm-cris/arch-v32/byteorder.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_BYTEORDER_H -#define _ASM_CRIS_ARCH_BYTEORDER_H - -#include - -extern __inline__ __const__ __u32 -___arch__swab32(__u32 x) -{ - __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x)); - return (x); -} - -extern __inline__ __const__ __u16 -___arch__swab16(__u16 x) -{ - __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x)); - return (x); -} - -#endif /* _ASM_CRIS_ARCH_BYTEORDER_H */ diff --git a/trunk/include/asm-cris/arch-v32/cache.h b/trunk/include/asm-cris/arch-v32/cache.h deleted file mode 100644 index 4fed8d62ccc8..000000000000 --- a/trunk/include/asm-cris/arch-v32/cache.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_CACHE_H -#define _ASM_CRIS_ARCH_CACHE_H - -/* A cache-line is 32 bytes. */ -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 -#define L1_CACHE_SHIFT_MAX 5 - -#endif /* _ASM_CRIS_ARCH_CACHE_H */ diff --git a/trunk/include/asm-cris/arch-v32/checksum.h b/trunk/include/asm-cris/arch-v32/checksum.h deleted file mode 100644 index a1d6b2a6cc44..000000000000 --- a/trunk/include/asm-cris/arch-v32/checksum.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_CHECKSUM_H -#define _ASM_CRIS_ARCH_CHECKSUM_H - -/* - * Check values used in TCP/UDP headers. - * - * The gain of doing this in assembler instead of C, is that C doesn't - * generate carry-additions for the 32-bit components of the - * checksum. Which means it would be necessary to split all those into - * 16-bit components and then add. - */ -extern inline unsigned int -csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, - unsigned short len, unsigned short proto, unsigned int sum) -{ - int res; - - __asm__ __volatile__ ("add.d %2, %0\n\t" - "addc %3, %0\n\t" - "addc %4, %0\n\t" - "addc 0, %0\n\t" - : "=r" (res) - : "0" (sum), "r" (daddr), "r" (saddr), \ - "r" ((ntohs(len) << 16) + (proto << 8))); - - return res; -} - -#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */ diff --git a/trunk/include/asm-cris/arch-v32/cryptocop.h b/trunk/include/asm-cris/arch-v32/cryptocop.h deleted file mode 100644 index dfa1f66fb987..000000000000 --- a/trunk/include/asm-cris/arch-v32/cryptocop.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * The device /dev/cryptocop is accessible using this driver using - * CRYPTOCOP_MAJOR (254) and minor number 0. - */ - -#ifndef CRYPTOCOP_H -#define CRYPTOCOP_H - -#include - - -#define CRYPTOCOP_SESSION_ID_NONE (0) - -typedef unsigned long long int cryptocop_session_id; - -/* cryptocop ioctls */ -#define ETRAXCRYPTOCOP_IOCTYPE (250) - -#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) -#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) -#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) -#define CRYPTOCOP_IO_MAXNR (3) - -typedef enum { - cryptocop_cipher_des = 0, - cryptocop_cipher_3des = 1, - cryptocop_cipher_aes = 2, - cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ - cryptocop_cipher_none -} cryptocop_cipher_type; - -typedef enum { - cryptocop_digest_sha1 = 0, - cryptocop_digest_md5 = 1, - cryptocop_digest_none -} cryptocop_digest_type; - -typedef enum { - cryptocop_csum_le = 0, - cryptocop_csum_be = 1, - cryptocop_csum_none -} cryptocop_csum_type; - -typedef enum { - cryptocop_cipher_mode_ecb = 0, - cryptocop_cipher_mode_cbc, - cryptocop_cipher_mode_none -} cryptocop_cipher_mode; - -typedef enum { - cryptocop_3des_eee = 0, - cryptocop_3des_eed = 1, - cryptocop_3des_ede = 2, - cryptocop_3des_edd = 3, - cryptocop_3des_dee = 4, - cryptocop_3des_ded = 5, - cryptocop_3des_dde = 6, - cryptocop_3des_ddd = 7 -} cryptocop_3des_mode; - -/* Usermode accessible (ioctl) operations. */ -struct strcop_session_op{ - cryptocop_session_id ses_id; - - cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ - - cryptocop_cipher_mode cmode; /* ECB, CBC, none */ - cryptocop_3des_mode des3_mode; - - cryptocop_digest_type digest; /* MD5, SHA1, none */ - - cryptocop_csum_type csum; /* BE, LE, none */ - - unsigned char *key; - size_t keylen; -}; - -#define CRYPTOCOP_CSUM_LENGTH (2) -#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ -#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ -#define CRYPTOCOP_MAX_KEY_LENGTH (32) - -struct strcop_crypto_op{ - cryptocop_session_id ses_id; - - /* Indata. */ - unsigned char *indata; - size_t inlen; /* Total indata length. */ - - /* Cipher configuration. */ - unsigned char do_cipher:1; - unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ - unsigned char cipher_explicit:1; - size_t cipher_start; - size_t cipher_len; - /* cipher_iv is used if do_cipher and cipher_explicit and the cipher - mode is CBC. The length is controlled by the type of cipher, - e.g. DES/3DES 8 octets and AES 16 octets. */ - unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; - /* Outdata. */ - unsigned char *cipher_outdata; - size_t cipher_outlen; - - /* digest configuration. */ - unsigned char do_digest:1; - size_t digest_start; - size_t digest_len; - /* Outdata. The actual length is determined by the type of the digest. */ - unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; - - /* Checksum configuration. */ - unsigned char do_csum:1; - size_t csum_start; - size_t csum_len; - /* Outdata. */ - unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; -}; - - - -#ifdef __KERNEL__ - -/********** The API to use from inside the kernel. ************/ - -#include - -typedef enum { - cryptocop_alg_csum = 0, - cryptocop_alg_mem2mem, - cryptocop_alg_md5, - cryptocop_alg_sha1, - cryptocop_alg_des, - cryptocop_alg_3des, - cryptocop_alg_aes, - cryptocop_no_alg, -} cryptocop_algorithm; - -typedef u8 cryptocop_tfrm_id; - - -struct cryptocop_operation; - -typedef void (cryptocop_callback)(struct cryptocop_operation*, void*); - -struct cryptocop_transform_init { - cryptocop_algorithm alg; - /* Keydata for ciphers. */ - unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH]; - unsigned int keylen; - cryptocop_cipher_mode cipher_mode; - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */ - - cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */ - struct cryptocop_transform_init *next; -}; - - -typedef enum { - cryptocop_source_dma = 0, - cryptocop_source_des, - cryptocop_source_3des, - cryptocop_source_aes, - cryptocop_source_md5, - cryptocop_source_sha1, - cryptocop_source_csum, - cryptocop_source_none, -} cryptocop_source; - - -struct cryptocop_desc_cfg { - cryptocop_tfrm_id tid; - cryptocop_source src; - unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */ - struct cryptocop_desc_cfg *next; -}; - -struct cryptocop_desc { - size_t length; - struct cryptocop_desc_cfg *cfg; - struct cryptocop_desc *next; -}; - - -/* Flags for cryptocop_tfrm_cfg */ -#define CRYPTOCOP_NO_FLAG (0x00) -#define CRYPTOCOP_ENCRYPT (0x01) -#define CRYPTOCOP_DECRYPT (0x02) -#define CRYPTOCOP_EXPLICIT_IV (0x04) - -struct cryptocop_tfrm_cfg { - cryptocop_tfrm_id tid; - - unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */ - - /* CBC initialisation vector for cihers. */ - u8 iv[CRYPTOCOP_MAX_IV_LENGTH]; - - /* The position in output where to write the transform output. The order - in which the driver writes the output is unspecified, hence if several - transforms write on the same positions in the output the result is - unspecified. */ - size_t inject_ix; - - struct cryptocop_tfrm_cfg *next; -}; - - - -struct cryptocop_dma_list_operation{ - /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in - struct cryptocop_operation must be set for the driver to use them. outlist, - out_data_buf, inlist and in_data_buf must all be physical addresses since they will - be loaded to DMA . */ - dma_descr_data *outlist; /* Out from memory to the co-processor. */ - char *out_data_buf; - dma_descr_data *inlist; /* In from the co-processor to memory. */ - char *in_data_buf; - - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; -}; - - -struct cryptocop_tfrm_operation{ - /* Operation configuration, if not 'use_dmalists' is set. */ - struct cryptocop_tfrm_cfg *tfrm_cfg; - struct cryptocop_desc *desc; - - struct iovec *indata; - size_t incount; - size_t inlen; /* Total inlength. */ - - struct iovec *outdata; - size_t outcount; - size_t outlen; /* Total outlength. */ -}; - - -struct cryptocop_operation { - cryptocop_callback *cb; - void *cb_data; - - cryptocop_session_id sid; - - /* The status of the operation when returned to consumer. */ - int operation_status; /* 0, -EAGAIN */ - - /* Flags */ - unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */ - unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */ - unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */ - - union{ - struct cryptocop_dma_list_operation list_op; - struct cryptocop_tfrm_operation tfrm_op; - }; -}; - - -int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag); -int cryptocop_free_session(cryptocop_session_id sid); - -int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation); - -int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation); - -int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation); - -#endif /* __KERNEL__ */ - -#endif /* CRYPTOCOP_H */ diff --git a/trunk/include/asm-cris/arch-v32/delay.h b/trunk/include/asm-cris/arch-v32/delay.h deleted file mode 100644 index f36f7f760e89..000000000000 --- a/trunk/include/asm-cris/arch-v32/delay.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_DELAY_H -#define _ASM_CRIS_ARCH_DELAY_H - -extern __inline__ void -__delay(int loops) -{ - __asm__ __volatile__ ( - "move.d %0, $r9\n\t" - "beq 2f\n\t" - "subq 1, $r9\n\t" - "1:\n\t" - "bne 1b\n\t" - "subq 1, $r9\n" - "2:" - : : "g" (loops) : "r9"); -} - -#endif /* _ASM_CRIS_ARCH_DELAY_H */ diff --git a/trunk/include/asm-cris/arch-v32/dma.h b/trunk/include/asm-cris/arch-v32/dma.h deleted file mode 100644 index 3674081389fd..000000000000 --- a/trunk/include/asm-cris/arch-v32/dma.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_DMA_H -#define _ASM_ARCH_CRIS_DMA_H - -/* Defines for using and allocating dma channels. */ - -#define MAX_DMA_CHANNELS 10 - -#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ -#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ - -#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ -#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ - -#define ATA_TX_DMA_NBR 2 /* ATA interface out. */ -#define ATA_RX_DMA_NBR 3 /* ATA interface in. */ - -#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ -#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ - -#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ -#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ - -#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ -#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ - -#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ -#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ - -#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ -#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ - -#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ -#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ - -#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ -#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ - -#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ -#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ - -#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ -#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ - -#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ -#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ - -#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ -#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ - -enum dma_owner -{ - dma_eth0, - dma_eth1, - dma_iop0, - dma_iop1, - dma_ser0, - dma_ser1, - dma_ser2, - dma_ser3, - dma_sser0, - dma_sser1, - dma_ata, - dma_strp, - dma_ext0, - dma_ext1, - dma_ext2, - dma_ext3 -}; - -int crisv32_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, unsigned bandwidth, enum dma_owner owner); -void crisv32_free_dma(unsigned int dmanr); - -/* Masks used by crisv32_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR 1 -#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) -#define DMA_INT_MEM 4 - -#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/trunk/include/asm-cris/arch-v32/elf.h b/trunk/include/asm-cris/arch-v32/elf.h deleted file mode 100644 index 1324e505a4d8..000000000000 --- a/trunk/include/asm-cris/arch-v32/elf.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef _ASM_CRIS_ELF_H -#define _ASM_CRIS_ELF_H - -#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - -/* CRISv32 ELF register definitions. */ - -#include - -/* Explicitly zero out registers to increase determinism. */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ - (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ - (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ - (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ - (_r)->acr = 0; \ -} while (0) - -/* - * An executable for which elf_read_implies_exec() returns TRUE will - * have the READ_IMPLIES_EXEC personality flag set automatically. - */ -#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack)) - -/* - * This is basically a pt_regs with the additional definition - * of the stack pointer since it's needed in a core dump. - * pr_regs is a elf_gregset_t and should be filled according - * to the layout of user_regs_struct. - */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - pr_reg[0] = regs->r0; \ - pr_reg[1] = regs->r1; \ - pr_reg[2] = regs->r2; \ - pr_reg[3] = regs->r3; \ - pr_reg[4] = regs->r4; \ - pr_reg[5] = regs->r5; \ - pr_reg[6] = regs->r6; \ - pr_reg[7] = regs->r7; \ - pr_reg[8] = regs->r8; \ - pr_reg[9] = regs->r9; \ - pr_reg[10] = regs->r10; \ - pr_reg[11] = regs->r11; \ - pr_reg[12] = regs->r12; \ - pr_reg[13] = regs->r13; \ - pr_reg[14] = rdusp(); /* SP */ \ - pr_reg[15] = regs->acr; /* ACR */ \ - pr_reg[16] = 0; /* BZ */ \ - pr_reg[17] = rdvr(); /* VR */ \ - pr_reg[18] = 0; /* PID */ \ - pr_reg[19] = regs->srs; /* SRS */ \ - pr_reg[20] = 0; /* WZ */ \ - pr_reg[21] = regs->exs; /* EXS */ \ - pr_reg[22] = regs->eda; /* EDA */ \ - pr_reg[23] = regs->mof; /* MOF */ \ - pr_reg[24] = 0; /* DZ */ \ - pr_reg[25] = 0; /* EBP */ \ - pr_reg[26] = regs->erp; /* ERP */ \ - pr_reg[27] = regs->srp; /* SRP */ \ - pr_reg[28] = 0; /* NRP */ \ - pr_reg[29] = regs->ccs; /* CCS */ \ - pr_reg[30] = rdusp(); /* USP */ \ - pr_reg[31] = regs->spc; /* SPC */ \ - -#endif /* _ASM_CRIS_ELF_H */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/Makefile b/trunk/include/asm-cris/arch-v32/hwregs/Makefile deleted file mode 100644 index c9160f9949a9..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/Makefile +++ /dev/null @@ -1,187 +0,0 @@ -# $Id: Makefile,v 1.8 2004/01/07 21:16:18 johana Exp $ -# Makefile to generate or copy the latest register definitions -# and related datastructures and helpermacros. -# The offical place for these files is at: -RELEASE ?= r1_alfa5 -OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ - -# which is updated on each new release. -INCL_ASMFILES = -INCL_FILES = ata_defs.h -INCL_FILES += bif_core_defs.h -INCL_ASMFILES += bif_core_defs_asm.h -INCL_FILES += bif_slave_defs.h -#INCL_FILES += bif_slave_ext_defs.h -INCL_FILES += config_defs.h -INCL_ASMFILES += config_defs_asm.h -INCL_FILES += cpu_vect.h -#INCL_FILES += cris_defs.h -#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h -INCL_FILES += dma.h -INCL_FILES += dma_defs.h -INCL_FILES += eth_defs.h -INCL_FILES += extmem_defs.h -INCL_FILES += gio_defs.h -INCL_ASMFILES += gio_defs_asm.h -INCL_FILES += intr_vect.h -INCL_FILES += intr_vect_defs.h -INCL_ASMFILES += intr_vect_defs_asm.h -INCL_FILES += marb_bp_defs.h -INCL_FILES += marb_defs.h -INCL_ASMFILES += mmu_defs_asm.h -#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h -#INCL_FILES += par_defs.h # No useful content -INCL_FILES += pinmux_defs.h -INCL_FILES += reg_map.h -INCL_ASMFILES += reg_map_asm.h -INCL_FILES += reg_rdwr.h -INCL_FILES += ser_defs.h -#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h -INCL_FILES += sser_defs.h -INCL_FILES += strcop_defs.h -#INCL_FILES += strcop.h # Where is this? -INCL_FILES += strmux_defs.h -#INCL_FILES += supp_reg.h # Handcrafted instead -INCL_FILES += timer_defs.h - -REGDESC = -REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r -REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r -REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r -#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r -REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r -REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r -REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r -REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r -REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r -REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r -REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r -REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r -#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r -REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r -REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r -REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r -REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r -REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r -#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r - - -BASEDIR = /n/asic/design -DESIGNDIR = /n/asic/projects/guinness/design -RDES2C = /n/asic/bin/rdes2c -RDES2C = /n/asic/design/tools/rdesc/rdes2c -RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr -RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt - -## all - Just print help - you probably want to do 'make gen' -all: help - -# Disable implicit rule that may generate deleted files from RCS/ directory. -%.r: - -%.h: - -## help - This help -help: - @grep '^## ' Makefile - -## gen - Generate include files -gen: $(INCL_FILES) $(INCL_ASMFILES) - -ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r - $(RDES2C) $< -config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r - $(RDES2C) $< -config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r - $(RDES2C) -asm $< -# Can't generate cpu_vect.h yet -#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ???? -# $(RDES2INTR) $< -cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r - $(RDES2C) $< -$(BASEDIR)/core/dma/sw/dma.h: -dma.h: $(BASEDIR)/core/dma/sw/dma.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r - $(RDES2C) $< -extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r - $(RDES2C) $< -gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r - $(RDES2C) $< -intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r - $(RDES2C) $< -intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r - $(RDES2C) -asm $< -# Can't generate intr_vect.h yet -#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r -# $(RDES2INTR) $< -intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r - $(RDES2C) -asm $< -par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r - $(RDES2C) $< - -# From /n/asic/projects/guinness/design/ -reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap - $(RDES2C) -base 0xb0000000 $^ -reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap - $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^ - -reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ - -ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r - $(RDES2C) $< -strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r - $(RDES2C) $< -strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r - $(RDES2C) $< -timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r - $(RDES2C) $< -usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r - $(RDES2C) $< - -## copy - Copy files from official location -copy: - @for HFILE in $(INCL_FILES); do \ - echo " $$HFILE"; \ - cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @for HFILE in $(INCL_ASMFILES); do \ - echo " $$HFILE"; \ - cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done -## ls_official - List official location -ls_official: - (cd $(OFFICIAL_INCDIR); ls -l *.h ) - -## diff_official - Diff current directory with official location -diff_official: - diff . $(OFFICIAL_INCDIR) - -## doc - Generate .axw files from register description. -doc: $(REGDESC) - for RDES in $^; do \ - $(RDES2TXT) $$RDES; \ - done - -.PHONY: axw -## %.axw - Generate the specified .axw file (doesn't work for all files -## due to inconsistent naming ir .r files. -%.axw: axw - @for RDES in $(REGDESC); do \ - if echo "$$RDES" | grep $* ; then \ - $(RDES2TXT) $$RDES; \ - fi \ - done - -.PHONY: clean -## clean - Remove .h files and .axw files. -clean: - rm -rf $(INCL_FILES) *.axw - diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h deleted file mode 100644 index 866191418f9c..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h +++ /dev/null @@ -1,222 +0,0 @@ -#ifndef __ata_defs_asm_h -#define __ata_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/ata/rtl/ata_regs.r - * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp - * last modfied: Mon Apr 11 16:06:25 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r - * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ctrl0, scope ata, type rw */ -#define reg_ata_rw_ctrl0___pio_hold___lsb 0 -#define reg_ata_rw_ctrl0___pio_hold___width 6 -#define reg_ata_rw_ctrl0___pio_strb___lsb 6 -#define reg_ata_rw_ctrl0___pio_strb___width 6 -#define reg_ata_rw_ctrl0___pio_setup___lsb 12 -#define reg_ata_rw_ctrl0___pio_setup___width 6 -#define reg_ata_rw_ctrl0___dma_hold___lsb 18 -#define reg_ata_rw_ctrl0___dma_hold___width 6 -#define reg_ata_rw_ctrl0___dma_strb___lsb 24 -#define reg_ata_rw_ctrl0___dma_strb___width 6 -#define reg_ata_rw_ctrl0___rst___lsb 30 -#define reg_ata_rw_ctrl0___rst___width 1 -#define reg_ata_rw_ctrl0___rst___bit 30 -#define reg_ata_rw_ctrl0___en___lsb 31 -#define reg_ata_rw_ctrl0___en___width 1 -#define reg_ata_rw_ctrl0___en___bit 31 -#define reg_ata_rw_ctrl0_offset 12 - -/* Register rw_ctrl1, scope ata, type rw */ -#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0 -#define reg_ata_rw_ctrl1___udma_tcyc___width 4 -#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4 -#define reg_ata_rw_ctrl1___udma_tdvs___width 4 -#define reg_ata_rw_ctrl1_offset 16 - -/* Register rw_ctrl2, scope ata, type rw */ -#define reg_ata_rw_ctrl2___data___lsb 0 -#define reg_ata_rw_ctrl2___data___width 16 -#define reg_ata_rw_ctrl2___dma_size___lsb 19 -#define reg_ata_rw_ctrl2___dma_size___width 1 -#define reg_ata_rw_ctrl2___dma_size___bit 19 -#define reg_ata_rw_ctrl2___multi___lsb 20 -#define reg_ata_rw_ctrl2___multi___width 1 -#define reg_ata_rw_ctrl2___multi___bit 20 -#define reg_ata_rw_ctrl2___hsh___lsb 21 -#define reg_ata_rw_ctrl2___hsh___width 2 -#define reg_ata_rw_ctrl2___trf_mode___lsb 23 -#define reg_ata_rw_ctrl2___trf_mode___width 1 -#define reg_ata_rw_ctrl2___trf_mode___bit 23 -#define reg_ata_rw_ctrl2___rw___lsb 24 -#define reg_ata_rw_ctrl2___rw___width 1 -#define reg_ata_rw_ctrl2___rw___bit 24 -#define reg_ata_rw_ctrl2___addr___lsb 25 -#define reg_ata_rw_ctrl2___addr___width 3 -#define reg_ata_rw_ctrl2___cs0___lsb 28 -#define reg_ata_rw_ctrl2___cs0___width 1 -#define reg_ata_rw_ctrl2___cs0___bit 28 -#define reg_ata_rw_ctrl2___cs1___lsb 29 -#define reg_ata_rw_ctrl2___cs1___width 1 -#define reg_ata_rw_ctrl2___cs1___bit 29 -#define reg_ata_rw_ctrl2___sel___lsb 30 -#define reg_ata_rw_ctrl2___sel___width 2 -#define reg_ata_rw_ctrl2_offset 0 - -/* Register rs_stat_data, scope ata, type rs */ -#define reg_ata_rs_stat_data___data___lsb 0 -#define reg_ata_rs_stat_data___data___width 16 -#define reg_ata_rs_stat_data___dav___lsb 16 -#define reg_ata_rs_stat_data___dav___width 1 -#define reg_ata_rs_stat_data___dav___bit 16 -#define reg_ata_rs_stat_data___busy___lsb 17 -#define reg_ata_rs_stat_data___busy___width 1 -#define reg_ata_rs_stat_data___busy___bit 17 -#define reg_ata_rs_stat_data_offset 4 - -/* Register r_stat_data, scope ata, type r */ -#define reg_ata_r_stat_data___data___lsb 0 -#define reg_ata_r_stat_data___data___width 16 -#define reg_ata_r_stat_data___dav___lsb 16 -#define reg_ata_r_stat_data___dav___width 1 -#define reg_ata_r_stat_data___dav___bit 16 -#define reg_ata_r_stat_data___busy___lsb 17 -#define reg_ata_r_stat_data___busy___width 1 -#define reg_ata_r_stat_data___busy___bit 17 -#define reg_ata_r_stat_data_offset 8 - -/* Register rw_trf_cnt, scope ata, type rw */ -#define reg_ata_rw_trf_cnt___cnt___lsb 0 -#define reg_ata_rw_trf_cnt___cnt___width 17 -#define reg_ata_rw_trf_cnt_offset 20 - -/* Register r_stat_misc, scope ata, type r */ -#define reg_ata_r_stat_misc___crc___lsb 0 -#define reg_ata_r_stat_misc___crc___width 16 -#define reg_ata_r_stat_misc_offset 24 - -/* Register rw_intr_mask, scope ata, type rw */ -#define reg_ata_rw_intr_mask___bus0___lsb 0 -#define reg_ata_rw_intr_mask___bus0___width 1 -#define reg_ata_rw_intr_mask___bus0___bit 0 -#define reg_ata_rw_intr_mask___bus1___lsb 1 -#define reg_ata_rw_intr_mask___bus1___width 1 -#define reg_ata_rw_intr_mask___bus1___bit 1 -#define reg_ata_rw_intr_mask___bus2___lsb 2 -#define reg_ata_rw_intr_mask___bus2___width 1 -#define reg_ata_rw_intr_mask___bus2___bit 2 -#define reg_ata_rw_intr_mask___bus3___lsb 3 -#define reg_ata_rw_intr_mask___bus3___width 1 -#define reg_ata_rw_intr_mask___bus3___bit 3 -#define reg_ata_rw_intr_mask_offset 28 - -/* Register rw_ack_intr, scope ata, type rw */ -#define reg_ata_rw_ack_intr___bus0___lsb 0 -#define reg_ata_rw_ack_intr___bus0___width 1 -#define reg_ata_rw_ack_intr___bus0___bit 0 -#define reg_ata_rw_ack_intr___bus1___lsb 1 -#define reg_ata_rw_ack_intr___bus1___width 1 -#define reg_ata_rw_ack_intr___bus1___bit 1 -#define reg_ata_rw_ack_intr___bus2___lsb 2 -#define reg_ata_rw_ack_intr___bus2___width 1 -#define reg_ata_rw_ack_intr___bus2___bit 2 -#define reg_ata_rw_ack_intr___bus3___lsb 3 -#define reg_ata_rw_ack_intr___bus3___width 1 -#define reg_ata_rw_ack_intr___bus3___bit 3 -#define reg_ata_rw_ack_intr_offset 32 - -/* Register r_intr, scope ata, type r */ -#define reg_ata_r_intr___bus0___lsb 0 -#define reg_ata_r_intr___bus0___width 1 -#define reg_ata_r_intr___bus0___bit 0 -#define reg_ata_r_intr___bus1___lsb 1 -#define reg_ata_r_intr___bus1___width 1 -#define reg_ata_r_intr___bus1___bit 1 -#define reg_ata_r_intr___bus2___lsb 2 -#define reg_ata_r_intr___bus2___width 1 -#define reg_ata_r_intr___bus2___bit 2 -#define reg_ata_r_intr___bus3___lsb 3 -#define reg_ata_r_intr___bus3___width 1 -#define reg_ata_r_intr___bus3___bit 3 -#define reg_ata_r_intr_offset 36 - -/* Register r_masked_intr, scope ata, type r */ -#define reg_ata_r_masked_intr___bus0___lsb 0 -#define reg_ata_r_masked_intr___bus0___width 1 -#define reg_ata_r_masked_intr___bus0___bit 0 -#define reg_ata_r_masked_intr___bus1___lsb 1 -#define reg_ata_r_masked_intr___bus1___width 1 -#define reg_ata_r_masked_intr___bus1___bit 1 -#define reg_ata_r_masked_intr___bus2___lsb 2 -#define reg_ata_r_masked_intr___bus2___width 1 -#define reg_ata_r_masked_intr___bus2___bit 2 -#define reg_ata_r_masked_intr___bus3___lsb 3 -#define reg_ata_r_masked_intr___bus3___width 1 -#define reg_ata_r_masked_intr___bus3___bit 3 -#define reg_ata_r_masked_intr_offset 40 - - -/* Constants */ -#define regk_ata_active 0x00000001 -#define regk_ata_byte 0x00000001 -#define regk_ata_data 0x00000001 -#define regk_ata_dma 0x00000001 -#define regk_ata_inactive 0x00000000 -#define regk_ata_no 0x00000000 -#define regk_ata_nodata 0x00000000 -#define regk_ata_pio 0x00000000 -#define regk_ata_rd 0x00000001 -#define regk_ata_reg 0x00000000 -#define regk_ata_rw_ctrl0_default 0x00000000 -#define regk_ata_rw_ctrl2_default 0x00000000 -#define regk_ata_rw_intr_mask_default 0x00000000 -#define regk_ata_udma 0x00000002 -#define regk_ata_word 0x00000000 -#define regk_ata_wr 0x00000000 -#define regk_ata_yes 0x00000001 -#endif /* __ata_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index c686cb335621..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h +++ /dev/null @@ -1,319 +0,0 @@ -#ifndef __bif_core_defs_asm_h -#define __bif_core_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp1_cfg___lw___width 6 -#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp1_cfg___ew___width 3 -#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp1_cfg___zw___width 3 -#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp1_cfg___aw___width 2 -#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp1_cfg___dw___width 2 -#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp1_cfg___ewb___width 2 -#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp1_cfg___bw___width 1 -#define reg_bif_core_rw_grp1_cfg___bw___bit 18 -#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp1_cfg___mode___width 1 -#define reg_bif_core_rw_grp1_cfg___mode___bit 21 -#define reg_bif_core_rw_grp1_cfg_offset 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp2_cfg___lw___width 6 -#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp2_cfg___ew___width 3 -#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp2_cfg___zw___width 3 -#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp2_cfg___aw___width 2 -#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp2_cfg___dw___width 2 -#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp2_cfg___ewb___width 2 -#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp2_cfg___bw___width 1 -#define reg_bif_core_rw_grp2_cfg___bw___bit 18 -#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp2_cfg___mode___width 1 -#define reg_bif_core_rw_grp2_cfg___mode___bit 21 -#define reg_bif_core_rw_grp2_cfg_offset 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp3_cfg___lw___width 6 -#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp3_cfg___ew___width 3 -#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp3_cfg___zw___width 3 -#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp3_cfg___aw___width 2 -#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp3_cfg___dw___width 2 -#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp3_cfg___ewb___width 2 -#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp3_cfg___bw___width 1 -#define reg_bif_core_rw_grp3_cfg___bw___bit 18 -#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp3_cfg___mode___width 1 -#define reg_bif_core_rw_grp3_cfg___mode___bit 21 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 -#define reg_bif_core_rw_grp3_cfg_offset 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp4_cfg___lw___width 6 -#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp4_cfg___ew___width 3 -#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp4_cfg___zw___width 3 -#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp4_cfg___aw___width 2 -#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp4_cfg___dw___width 2 -#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp4_cfg___ewb___width 2 -#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp4_cfg___bw___width 1 -#define reg_bif_core_rw_grp4_cfg___bw___bit 18 -#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp4_cfg___mode___width 1 -#define reg_bif_core_rw_grp4_cfg___mode___bit 21 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 -#define reg_bif_core_rw_grp4_cfg_offset 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_timing___cl___lsb 0 -#define reg_bif_core_rw_sdram_timing___cl___width 3 -#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 -#define reg_bif_core_rw_sdram_timing___rcd___width 3 -#define reg_bif_core_rw_sdram_timing___rp___lsb 6 -#define reg_bif_core_rw_sdram_timing___rp___width 3 -#define reg_bif_core_rw_sdram_timing___rc___lsb 9 -#define reg_bif_core_rw_sdram_timing___rc___width 2 -#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 -#define reg_bif_core_rw_sdram_timing___dpl___width 2 -#define reg_bif_core_rw_sdram_timing___pde___lsb 13 -#define reg_bif_core_rw_sdram_timing___pde___width 1 -#define reg_bif_core_rw_sdram_timing___pde___bit 13 -#define reg_bif_core_rw_sdram_timing___ref___lsb 14 -#define reg_bif_core_rw_sdram_timing___ref___width 2 -#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 -#define reg_bif_core_rw_sdram_timing___cpd___width 1 -#define reg_bif_core_rw_sdram_timing___cpd___bit 16 -#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 -#define reg_bif_core_rw_sdram_timing___sdcke___width 1 -#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 -#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 -#define reg_bif_core_rw_sdram_timing___sdclk___width 1 -#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 -#define reg_bif_core_rw_sdram_timing_offset 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 -#define reg_bif_core_rw_sdram_cmd___cmd___width 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 -#define reg_bif_core_rw_sdram_cmd_offset 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 -#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_rs_sdram_ref_stat_offset 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_r_sdram_ref_stat___ok___width 1 -#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_r_sdram_ref_stat_offset 36 - - -/* Constants */ -#define regk_bif_core_bank2 0x00000000 -#define regk_bif_core_bank4 0x00000001 -#define regk_bif_core_bit10 0x0000000a -#define regk_bif_core_bit11 0x0000000b -#define regk_bif_core_bit12 0x0000000c -#define regk_bif_core_bit13 0x0000000d -#define regk_bif_core_bit14 0x0000000e -#define regk_bif_core_bit15 0x0000000f -#define regk_bif_core_bit16 0x00000010 -#define regk_bif_core_bit17 0x00000011 -#define regk_bif_core_bit18 0x00000012 -#define regk_bif_core_bit19 0x00000013 -#define regk_bif_core_bit20 0x00000014 -#define regk_bif_core_bit21 0x00000015 -#define regk_bif_core_bit22 0x00000016 -#define regk_bif_core_bit23 0x00000017 -#define regk_bif_core_bit24 0x00000018 -#define regk_bif_core_bit25 0x00000019 -#define regk_bif_core_bit26 0x0000001a -#define regk_bif_core_bit27 0x0000001b -#define regk_bif_core_bit28 0x0000001c -#define regk_bif_core_bit29 0x0000001d -#define regk_bif_core_bit9 0x00000009 -#define regk_bif_core_bw16 0x00000001 -#define regk_bif_core_bw32 0x00000000 -#define regk_bif_core_bwe 0x00000000 -#define regk_bif_core_cwe 0x00000001 -#define regk_bif_core_e15us 0x00000001 -#define regk_bif_core_e7800ns 0x00000002 -#define regk_bif_core_grp0 0x00000000 -#define regk_bif_core_grp1 0x00000001 -#define regk_bif_core_mrs 0x00000003 -#define regk_bif_core_no 0x00000000 -#define regk_bif_core_none 0x00000000 -#define regk_bif_core_nop 0x00000000 -#define regk_bif_core_off 0x00000000 -#define regk_bif_core_pre 0x00000002 -#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rd 0x00000002 -#define regk_bif_core_ref 0x00000001 -#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rw_grp1_cfg_default 0x000006cf -#define regk_bif_core_rw_grp2_cfg_default 0x000006cf -#define regk_bif_core_rw_grp3_cfg_default 0x000006cf -#define regk_bif_core_rw_grp4_cfg_default 0x000006cf -#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 -#define regk_bif_core_slf 0x00000004 -#define regk_bif_core_wr 0x00000001 -#define regk_bif_core_yes 0x00000001 -#endif /* __bif_core_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h deleted file mode 100644 index 71532aa18168..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h +++ /dev/null @@ -1,495 +0,0 @@ -#ifndef __bif_dma_defs_asm_h -#define __bif_dma_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch0_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch0_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4 -#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19 -#define reg_bif_dma_rw_ch0_ctrl_offset 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch0_addr___addr___width 32 -#define reg_bif_dma_rw_ch0_addr_offset 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_start___run___lsb 0 -#define reg_bif_dma_rw_ch0_start___run___width 1 -#define reg_bif_dma_rw_ch0_start___run___bit 0 -#define reg_bif_dma_rw_ch0_start_offset 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch0_cnt_offset 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch0_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch0_stat___cnt___width 16 -#define reg_bif_dma_r_ch0_stat___run___lsb 31 -#define reg_bif_dma_r_ch0_stat___run___width 1 -#define reg_bif_dma_r_ch0_stat___run___bit 31 -#define reg_bif_dma_r_ch0_stat_offset 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch1_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch1_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4 -#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch1_ctrl_offset 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch1_addr___addr___width 32 -#define reg_bif_dma_rw_ch1_addr_offset 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_start___run___lsb 0 -#define reg_bif_dma_rw_ch1_start___run___width 1 -#define reg_bif_dma_rw_ch1_start___run___bit 0 -#define reg_bif_dma_rw_ch1_start_offset 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch1_cnt_offset 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch1_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch1_stat___cnt___width 16 -#define reg_bif_dma_r_ch1_stat___run___lsb 31 -#define reg_bif_dma_r_ch1_stat___run___width 1 -#define reg_bif_dma_r_ch1_stat___run___bit 31 -#define reg_bif_dma_r_ch1_stat_offset 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch2_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch2_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4 -#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19 -#define reg_bif_dma_rw_ch2_ctrl_offset 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch2_addr___addr___width 32 -#define reg_bif_dma_rw_ch2_addr_offset 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_start___run___lsb 0 -#define reg_bif_dma_rw_ch2_start___run___width 1 -#define reg_bif_dma_rw_ch2_start___run___bit 0 -#define reg_bif_dma_rw_ch2_start_offset 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch2_cnt_offset 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch2_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch2_stat___cnt___width 16 -#define reg_bif_dma_r_ch2_stat___run___lsb 31 -#define reg_bif_dma_r_ch2_stat___run___width 1 -#define reg_bif_dma_r_ch2_stat___run___bit 31 -#define reg_bif_dma_r_ch2_stat_offset 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch3_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch3_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4 -#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch3_ctrl_offset 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch3_addr___addr___width 32 -#define reg_bif_dma_rw_ch3_addr_offset 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_start___run___lsb 0 -#define reg_bif_dma_rw_ch3_start___run___width 1 -#define reg_bif_dma_rw_ch3_start___run___bit 0 -#define reg_bif_dma_rw_ch3_start_offset 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch3_cnt_offset 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch3_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch3_stat___cnt___width 16 -#define reg_bif_dma_r_ch3_stat___run___lsb 31 -#define reg_bif_dma_r_ch3_stat___run___width 1 -#define reg_bif_dma_r_ch3_stat___run___bit 31 -#define reg_bif_dma_r_ch3_stat_offset 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0 -#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0 -#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1 -#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1 -#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2 -#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2 -#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3 -#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3 -#define reg_bif_dma_rw_intr_mask_offset 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0 -#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0 -#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1 -#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1 -#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2 -#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2 -#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3 -#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3 -#define reg_bif_dma_rw_ack_intr_offset 132 - -/* Register r_intr, scope bif_dma, type r */ -#define reg_bif_dma_r_intr___ext_dma0___lsb 0 -#define reg_bif_dma_r_intr___ext_dma0___width 1 -#define reg_bif_dma_r_intr___ext_dma0___bit 0 -#define reg_bif_dma_r_intr___ext_dma1___lsb 1 -#define reg_bif_dma_r_intr___ext_dma1___width 1 -#define reg_bif_dma_r_intr___ext_dma1___bit 1 -#define reg_bif_dma_r_intr___ext_dma2___lsb 2 -#define reg_bif_dma_r_intr___ext_dma2___width 1 -#define reg_bif_dma_r_intr___ext_dma2___bit 2 -#define reg_bif_dma_r_intr___ext_dma3___lsb 3 -#define reg_bif_dma_r_intr___ext_dma3___width 1 -#define reg_bif_dma_r_intr___ext_dma3___bit 3 -#define reg_bif_dma_r_intr_offset 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0 -#define reg_bif_dma_r_masked_intr___ext_dma0___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0 -#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1 -#define reg_bif_dma_r_masked_intr___ext_dma1___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1 -#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2 -#define reg_bif_dma_r_masked_intr___ext_dma2___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2 -#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3 -#define reg_bif_dma_r_masked_intr___ext_dma3___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3 -#define reg_bif_dma_r_masked_intr_offset 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin0_cfg_offset 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin1_cfg_offset 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin2_cfg_offset 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin3_cfg_offset 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin4_cfg_offset 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin5_cfg_offset 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin6_cfg_offset 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin7_cfg_offset 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_pin_stat___pin0___lsb 0 -#define reg_bif_dma_r_pin_stat___pin0___width 1 -#define reg_bif_dma_r_pin_stat___pin0___bit 0 -#define reg_bif_dma_r_pin_stat___pin1___lsb 1 -#define reg_bif_dma_r_pin_stat___pin1___width 1 -#define reg_bif_dma_r_pin_stat___pin1___bit 1 -#define reg_bif_dma_r_pin_stat___pin2___lsb 2 -#define reg_bif_dma_r_pin_stat___pin2___width 1 -#define reg_bif_dma_r_pin_stat___pin2___bit 2 -#define reg_bif_dma_r_pin_stat___pin3___lsb 3 -#define reg_bif_dma_r_pin_stat___pin3___width 1 -#define reg_bif_dma_r_pin_stat___pin3___bit 3 -#define reg_bif_dma_r_pin_stat___pin4___lsb 4 -#define reg_bif_dma_r_pin_stat___pin4___width 1 -#define reg_bif_dma_r_pin_stat___pin4___bit 4 -#define reg_bif_dma_r_pin_stat___pin5___lsb 5 -#define reg_bif_dma_r_pin_stat___pin5___width 1 -#define reg_bif_dma_r_pin_stat___pin5___bit 5 -#define reg_bif_dma_r_pin_stat___pin6___lsb 6 -#define reg_bif_dma_r_pin_stat___pin6___width 1 -#define reg_bif_dma_r_pin_stat___pin6___bit 6 -#define reg_bif_dma_r_pin_stat___pin7___lsb 7 -#define reg_bif_dma_r_pin_stat___pin7___width 1 -#define reg_bif_dma_r_pin_stat___pin7___bit 7 -#define reg_bif_dma_r_pin_stat_offset 192 - - -/* Constants */ -#define regk_bif_dma_as_master 0x00000001 -#define regk_bif_dma_as_slave 0x00000001 -#define regk_bif_dma_burst1 0x00000000 -#define regk_bif_dma_burst8 0x00000001 -#define regk_bif_dma_bw16 0x00000001 -#define regk_bif_dma_bw32 0x00000002 -#define regk_bif_dma_bw8 0x00000000 -#define regk_bif_dma_dack 0x00000006 -#define regk_bif_dma_dack_inv 0x00000007 -#define regk_bif_dma_force 0x00000001 -#define regk_bif_dma_hi 0x00000003 -#define regk_bif_dma_inv 0x00000003 -#define regk_bif_dma_lo 0x00000002 -#define regk_bif_dma_master 0x00000001 -#define regk_bif_dma_no 0x00000000 -#define regk_bif_dma_norm 0x00000002 -#define regk_bif_dma_off 0x00000000 -#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch0_start_default 0x00000000 -#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch1_start_default 0x00000000 -#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch2_start_default 0x00000000 -#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch3_start_default 0x00000000 -#define regk_bif_dma_rw_intr_mask_default 0x00000000 -#define regk_bif_dma_rw_pin0_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin1_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin2_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin3_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin4_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin5_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin6_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin7_cfg_default 0x00000000 -#define regk_bif_dma_slave 0x00000002 -#define regk_bif_dma_sreq 0x00000006 -#define regk_bif_dma_sreq_inv 0x00000007 -#define regk_bif_dma_tc 0x00000004 -#define regk_bif_dma_tc_inv 0x00000005 -#define regk_bif_dma_yes 0x00000001 -#endif /* __bif_dma_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h deleted file mode 100644 index 031f33a365bb..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __bif_slave_defs_asm_h -#define __bif_slave_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0 -#define reg_bif_slave_rw_slave_cfg___slave_id___width 3 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4 -#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5 -#define reg_bif_slave_rw_slave_cfg___loopback___width 1 -#define reg_bif_slave_rw_slave_cfg___loopback___bit 5 -#define reg_bif_slave_rw_slave_cfg___dis___lsb 6 -#define reg_bif_slave_rw_slave_cfg___dis___width 1 -#define reg_bif_slave_rw_slave_cfg___dis___bit 6 -#define reg_bif_slave_rw_slave_cfg_offset 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0 -#define reg_bif_slave_r_slave_mode___ch0_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0 -#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1 -#define reg_bif_slave_r_slave_mode___ch1_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1 -#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2 -#define reg_bif_slave_r_slave_mode___ch2_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2 -#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3 -#define reg_bif_slave_r_slave_mode___ch3_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3 -#define reg_bif_slave_r_slave_mode_offset 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch0_cfg_offset 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch1_cfg_offset 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch2_cfg_offset 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch3_cfg_offset 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0 -#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1 -#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0 -#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1 -#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3 -#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4 -#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3 -#define reg_bif_slave_rw_arb_cfg___release___lsb 7 -#define reg_bif_slave_rw_arb_cfg___release___width 2 -#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9 -#define reg_bif_slave_rw_arb_cfg___acquire___width 1 -#define reg_bif_slave_rw_arb_cfg___acquire___bit 9 -#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10 -#define reg_bif_slave_rw_arb_cfg___settle_time___width 2 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12 -#define reg_bif_slave_rw_arb_cfg_offset 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -#define reg_bif_slave_r_arb_stat___init_mode___lsb 0 -#define reg_bif_slave_r_arb_stat___init_mode___width 1 -#define reg_bif_slave_r_arb_stat___init_mode___bit 0 -#define reg_bif_slave_r_arb_stat___mode___lsb 1 -#define reg_bif_slave_r_arb_stat___mode___width 1 -#define reg_bif_slave_r_arb_stat___mode___bit 1 -#define reg_bif_slave_r_arb_stat___brin___lsb 2 -#define reg_bif_slave_r_arb_stat___brin___width 1 -#define reg_bif_slave_r_arb_stat___brin___bit 2 -#define reg_bif_slave_r_arb_stat___brout___lsb 3 -#define reg_bif_slave_r_arb_stat___brout___width 1 -#define reg_bif_slave_r_arb_stat___brout___bit 3 -#define reg_bif_slave_r_arb_stat___bg___lsb 4 -#define reg_bif_slave_r_arb_stat___bg___width 1 -#define reg_bif_slave_r_arb_stat___bg___bit 4 -#define reg_bif_slave_r_arb_stat_offset 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0 -#define reg_bif_slave_rw_intr_mask___bus_release___width 1 -#define reg_bif_slave_rw_intr_mask___bus_release___bit 0 -#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1 -#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1 -#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1 -#define reg_bif_slave_rw_intr_mask_offset 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0 -#define reg_bif_slave_rw_ack_intr___bus_release___width 1 -#define reg_bif_slave_rw_ack_intr___bus_release___bit 0 -#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1 -#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1 -#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1 -#define reg_bif_slave_rw_ack_intr_offset 68 - -/* Register r_intr, scope bif_slave, type r */ -#define reg_bif_slave_r_intr___bus_release___lsb 0 -#define reg_bif_slave_r_intr___bus_release___width 1 -#define reg_bif_slave_r_intr___bus_release___bit 0 -#define reg_bif_slave_r_intr___bus_acquire___lsb 1 -#define reg_bif_slave_r_intr___bus_acquire___width 1 -#define reg_bif_slave_r_intr___bus_acquire___bit 1 -#define reg_bif_slave_r_intr_offset 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -#define reg_bif_slave_r_masked_intr___bus_release___lsb 0 -#define reg_bif_slave_r_masked_intr___bus_release___width 1 -#define reg_bif_slave_r_masked_intr___bus_release___bit 0 -#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1 -#define reg_bif_slave_r_masked_intr___bus_acquire___width 1 -#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1 -#define reg_bif_slave_r_masked_intr_offset 76 - - -/* Constants */ -#define regk_bif_slave_active_hi 0x00000003 -#define regk_bif_slave_active_lo 0x00000002 -#define regk_bif_slave_addr 0x00000000 -#define regk_bif_slave_always 0x00000001 -#define regk_bif_slave_at_idle 0x00000002 -#define regk_bif_slave_burst_end 0x00000003 -#define regk_bif_slave_dma 0x00000001 -#define regk_bif_slave_hi 0x00000003 -#define regk_bif_slave_inv 0x00000001 -#define regk_bif_slave_lo 0x00000002 -#define regk_bif_slave_local 0x00000001 -#define regk_bif_slave_master 0x00000000 -#define regk_bif_slave_mode_reg 0x00000001 -#define regk_bif_slave_no 0x00000000 -#define regk_bif_slave_norm 0x00000000 -#define regk_bif_slave_on_access 0x00000000 -#define regk_bif_slave_rw_arb_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch0_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch1_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch2_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch3_cfg_default 0x00000000 -#define regk_bif_slave_rw_intr_mask_default 0x00000000 -#define regk_bif_slave_rw_slave_cfg_default 0x00000000 -#define regk_bif_slave_shared 0x00000000 -#define regk_bif_slave_slave 0x00000001 -#define regk_bif_slave_t0ns 0x00000003 -#define regk_bif_slave_t10ns 0x00000002 -#define regk_bif_slave_t20ns 0x00000003 -#define regk_bif_slave_t30ns 0x00000002 -#define regk_bif_slave_t40ns 0x00000001 -#define regk_bif_slave_t50ns 0x00000000 -#define regk_bif_slave_yes 0x00000001 -#define regk_bif_slave_z 0x00000004 -#endif /* __bif_slave_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h deleted file mode 100644 index e98476332e1f..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h +++ /dev/null @@ -1,131 +0,0 @@ -#ifndef __config_defs_asm_h -#define __config_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r - * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope config, type r */ -#define reg_config_r_bootsel___boot_mode___lsb 0 -#define reg_config_r_bootsel___boot_mode___width 3 -#define reg_config_r_bootsel___full_duplex___lsb 3 -#define reg_config_r_bootsel___full_duplex___width 1 -#define reg_config_r_bootsel___full_duplex___bit 3 -#define reg_config_r_bootsel___user___lsb 4 -#define reg_config_r_bootsel___user___width 1 -#define reg_config_r_bootsel___user___bit 4 -#define reg_config_r_bootsel___pll___lsb 5 -#define reg_config_r_bootsel___pll___width 1 -#define reg_config_r_bootsel___pll___bit 5 -#define reg_config_r_bootsel___flash_bw___lsb 6 -#define reg_config_r_bootsel___flash_bw___width 1 -#define reg_config_r_bootsel___flash_bw___bit 6 -#define reg_config_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -#define reg_config_rw_clk_ctrl___pll___lsb 0 -#define reg_config_rw_clk_ctrl___pll___width 1 -#define reg_config_rw_clk_ctrl___pll___bit 0 -#define reg_config_rw_clk_ctrl___cpu___lsb 1 -#define reg_config_rw_clk_ctrl___cpu___width 1 -#define reg_config_rw_clk_ctrl___cpu___bit 1 -#define reg_config_rw_clk_ctrl___iop___lsb 2 -#define reg_config_rw_clk_ctrl___iop___width 1 -#define reg_config_rw_clk_ctrl___iop___bit 2 -#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 -#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 -#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 -#define reg_config_rw_clk_ctrl___dma23___lsb 4 -#define reg_config_rw_clk_ctrl___dma23___width 1 -#define reg_config_rw_clk_ctrl___dma23___bit 4 -#define reg_config_rw_clk_ctrl___dma45___lsb 5 -#define reg_config_rw_clk_ctrl___dma45___width 1 -#define reg_config_rw_clk_ctrl___dma45___bit 5 -#define reg_config_rw_clk_ctrl___dma67___lsb 6 -#define reg_config_rw_clk_ctrl___dma67___width 1 -#define reg_config_rw_clk_ctrl___dma67___bit 6 -#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 -#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 -#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 -#define reg_config_rw_clk_ctrl___bif___lsb 8 -#define reg_config_rw_clk_ctrl___bif___width 1 -#define reg_config_rw_clk_ctrl___bif___bit 8 -#define reg_config_rw_clk_ctrl___fix_io___lsb 9 -#define reg_config_rw_clk_ctrl___fix_io___width 1 -#define reg_config_rw_clk_ctrl___fix_io___bit 9 -#define reg_config_rw_clk_ctrl_offset 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 -#define reg_config_rw_pad_ctrl___usb_susp___width 1 -#define reg_config_rw_pad_ctrl___usb_susp___bit 0 -#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 -#define reg_config_rw_pad_ctrl___phyrst_n___width 1 -#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 -#define reg_config_rw_pad_ctrl_offset 8 - - -/* Constants */ -#define regk_config_bw16 0x00000000 -#define regk_config_bw32 0x00000001 -#define regk_config_master 0x00000005 -#define regk_config_nand 0x00000003 -#define regk_config_net_rx 0x00000001 -#define regk_config_net_tx_rx 0x00000002 -#define regk_config_no 0x00000000 -#define regk_config_none 0x00000007 -#define regk_config_nor 0x00000000 -#define regk_config_rw_clk_ctrl_default 0x00000002 -#define regk_config_rw_pad_ctrl_default 0x00000000 -#define regk_config_ser 0x00000004 -#define regk_config_slave 0x00000006 -#define regk_config_yes 0x00000001 -#endif /* __config_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h deleted file mode 100644 index 8370aee8a14a..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/crisp/doc/cpu_vect.r -version . */ - -#ifndef _______INST_CRISP_DOC_CPU_VECT_R -#define _______INST_CRISP_DOC_CPU_VECT_R -#define NMI_INTR_VECT 0x00 -#define RESERVED_1_INTR_VECT 0x01 -#define RESERVED_2_INTR_VECT 0x02 -#define SINGLE_STEP_INTR_VECT 0x03 -#define INSTR_TLB_REFILL_INTR_VECT 0x04 -#define INSTR_TLB_INV_INTR_VECT 0x05 -#define INSTR_TLB_ACC_INTR_VECT 0x06 -#define TLB_EX_INTR_VECT 0x07 -#define DATA_TLB_REFILL_INTR_VECT 0x08 -#define DATA_TLB_INV_INTR_VECT 0x09 -#define DATA_TLB_ACC_INTR_VECT 0x0a -#define DATA_TLB_WE_INTR_VECT 0x0b -#define HW_BP_INTR_VECT 0x0c -#define RESERVED_D_INTR_VECT 0x0d -#define RESERVED_E_INTR_VECT 0x0e -#define RESERVED_F_INTR_VECT 0x0f -#define BREAK_0_INTR_VECT 0x10 -#define BREAK_1_INTR_VECT 0x11 -#define BREAK_2_INTR_VECT 0x12 -#define BREAK_3_INTR_VECT 0x13 -#define BREAK_4_INTR_VECT 0x14 -#define BREAK_5_INTR_VECT 0x15 -#define BREAK_6_INTR_VECT 0x16 -#define BREAK_7_INTR_VECT 0x17 -#define BREAK_8_INTR_VECT 0x18 -#define BREAK_9_INTR_VECT 0x19 -#define BREAK_10_INTR_VECT 0x1a -#define BREAK_11_INTR_VECT 0x1b -#define BREAK_12_INTR_VECT 0x1c -#define BREAK_13_INTR_VECT 0x1d -#define BREAK_14_INTR_VECT 0x1e -#define BREAK_15_INTR_VECT 0x1f -#define MULTIPLE_INTR_VECT 0x30 - -#endif diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h deleted file mode 100644 index 7f768db272e2..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef __cris_defs_asm_h -#define __cris_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/crisp/doc/cris.r - * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp - * last modfied: Mon Apr 11 16:06:39 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r - * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gc_cfg, scope cris, type rw */ -#define reg_cris_rw_gc_cfg___ic___lsb 0 -#define reg_cris_rw_gc_cfg___ic___width 1 -#define reg_cris_rw_gc_cfg___ic___bit 0 -#define reg_cris_rw_gc_cfg___dc___lsb 1 -#define reg_cris_rw_gc_cfg___dc___width 1 -#define reg_cris_rw_gc_cfg___dc___bit 1 -#define reg_cris_rw_gc_cfg___im___lsb 2 -#define reg_cris_rw_gc_cfg___im___width 1 -#define reg_cris_rw_gc_cfg___im___bit 2 -#define reg_cris_rw_gc_cfg___dm___lsb 3 -#define reg_cris_rw_gc_cfg___dm___width 1 -#define reg_cris_rw_gc_cfg___dm___bit 3 -#define reg_cris_rw_gc_cfg___gb___lsb 4 -#define reg_cris_rw_gc_cfg___gb___width 1 -#define reg_cris_rw_gc_cfg___gb___bit 4 -#define reg_cris_rw_gc_cfg___gk___lsb 5 -#define reg_cris_rw_gc_cfg___gk___width 1 -#define reg_cris_rw_gc_cfg___gk___bit 5 -#define reg_cris_rw_gc_cfg___gp___lsb 6 -#define reg_cris_rw_gc_cfg___gp___width 1 -#define reg_cris_rw_gc_cfg___gp___bit 6 -#define reg_cris_rw_gc_cfg_offset 0 - -/* Register rw_gc_ccs, scope cris, type rw */ -#define reg_cris_rw_gc_ccs_offset 4 - -/* Register rw_gc_srs, scope cris, type rw */ -#define reg_cris_rw_gc_srs___srs___lsb 0 -#define reg_cris_rw_gc_srs___srs___width 8 -#define reg_cris_rw_gc_srs_offset 8 - -/* Register rw_gc_nrp, scope cris, type rw */ -#define reg_cris_rw_gc_nrp_offset 12 - -/* Register rw_gc_exs, scope cris, type rw */ -#define reg_cris_rw_gc_exs_offset 16 - -/* Register rw_gc_eda, scope cris, type rw */ -#define reg_cris_rw_gc_eda_offset 20 - -/* Register rw_gc_r0, scope cris, type rw */ -#define reg_cris_rw_gc_r0_offset 32 - -/* Register rw_gc_r1, scope cris, type rw */ -#define reg_cris_rw_gc_r1_offset 36 - -/* Register rw_gc_r2, scope cris, type rw */ -#define reg_cris_rw_gc_r2_offset 40 - -/* Register rw_gc_r3, scope cris, type rw */ -#define reg_cris_rw_gc_r3_offset 44 - - -/* Constants */ -#define regk_cris_no 0x00000000 -#define regk_cris_rw_gc_cfg_default 0x00000000 -#define regk_cris_yes 0x00000001 -#endif /* __cris_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h deleted file mode 100644 index 7d3689a6f80d..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h +++ /dev/null @@ -1,10 +0,0 @@ -#define RW_GC_CFG 0 -#define RW_GC_CCS 1 -#define RW_GC_SRS 2 -#define RW_GC_NRP 3 -#define RW_GC_EXS 4 -#define RW_GC_EDA 5 -#define RW_GC_R0 8 -#define RW_GC_R1 9 -#define RW_GC_R2 10 -#define RW_GC_R3 11 diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h deleted file mode 100644 index 0cb71bc127ae..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h +++ /dev/null @@ -1,368 +0,0 @@ -#ifndef __dma_defs_asm_h -#define __dma_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp - * last modfied: Mon Apr 11 16:06:51 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_data, scope dma, type rw */ -#define reg_dma_rw_data_offset 0 - -/* Register rw_data_next, scope dma, type rw */ -#define reg_dma_rw_data_next_offset 4 - -/* Register rw_data_buf, scope dma, type rw */ -#define reg_dma_rw_data_buf_offset 8 - -/* Register rw_data_ctrl, scope dma, type rw */ -#define reg_dma_rw_data_ctrl___eol___lsb 0 -#define reg_dma_rw_data_ctrl___eol___width 1 -#define reg_dma_rw_data_ctrl___eol___bit 0 -#define reg_dma_rw_data_ctrl___out_eop___lsb 3 -#define reg_dma_rw_data_ctrl___out_eop___width 1 -#define reg_dma_rw_data_ctrl___out_eop___bit 3 -#define reg_dma_rw_data_ctrl___intr___lsb 4 -#define reg_dma_rw_data_ctrl___intr___width 1 -#define reg_dma_rw_data_ctrl___intr___bit 4 -#define reg_dma_rw_data_ctrl___wait___lsb 5 -#define reg_dma_rw_data_ctrl___wait___width 1 -#define reg_dma_rw_data_ctrl___wait___bit 5 -#define reg_dma_rw_data_ctrl_offset 12 - -/* Register rw_data_stat, scope dma, type rw */ -#define reg_dma_rw_data_stat___in_eop___lsb 3 -#define reg_dma_rw_data_stat___in_eop___width 1 -#define reg_dma_rw_data_stat___in_eop___bit 3 -#define reg_dma_rw_data_stat_offset 16 - -/* Register rw_data_md, scope dma, type rw */ -#define reg_dma_rw_data_md___md___lsb 0 -#define reg_dma_rw_data_md___md___width 16 -#define reg_dma_rw_data_md_offset 20 - -/* Register rw_data_md_s, scope dma, type rw */ -#define reg_dma_rw_data_md_s___md_s___lsb 0 -#define reg_dma_rw_data_md_s___md_s___width 16 -#define reg_dma_rw_data_md_s_offset 24 - -/* Register rw_data_after, scope dma, type rw */ -#define reg_dma_rw_data_after_offset 28 - -/* Register rw_ctxt, scope dma, type rw */ -#define reg_dma_rw_ctxt_offset 32 - -/* Register rw_ctxt_next, scope dma, type rw */ -#define reg_dma_rw_ctxt_next_offset 36 - -/* Register rw_ctxt_ctrl, scope dma, type rw */ -#define reg_dma_rw_ctxt_ctrl___eol___lsb 0 -#define reg_dma_rw_ctxt_ctrl___eol___width 1 -#define reg_dma_rw_ctxt_ctrl___eol___bit 0 -#define reg_dma_rw_ctxt_ctrl___intr___lsb 4 -#define reg_dma_rw_ctxt_ctrl___intr___width 1 -#define reg_dma_rw_ctxt_ctrl___intr___bit 4 -#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6 -#define reg_dma_rw_ctxt_ctrl___store_mode___width 1 -#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6 -#define reg_dma_rw_ctxt_ctrl___en___lsb 7 -#define reg_dma_rw_ctxt_ctrl___en___width 1 -#define reg_dma_rw_ctxt_ctrl___en___bit 7 -#define reg_dma_rw_ctxt_ctrl_offset 40 - -/* Register rw_ctxt_stat, scope dma, type rw */ -#define reg_dma_rw_ctxt_stat___dis___lsb 7 -#define reg_dma_rw_ctxt_stat___dis___width 1 -#define reg_dma_rw_ctxt_stat___dis___bit 7 -#define reg_dma_rw_ctxt_stat_offset 44 - -/* Register rw_ctxt_md0, scope dma, type rw */ -#define reg_dma_rw_ctxt_md0___md0___lsb 0 -#define reg_dma_rw_ctxt_md0___md0___width 16 -#define reg_dma_rw_ctxt_md0_offset 48 - -/* Register rw_ctxt_md0_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0 -#define reg_dma_rw_ctxt_md0_s___md0_s___width 16 -#define reg_dma_rw_ctxt_md0_s_offset 52 - -/* Register rw_ctxt_md1, scope dma, type rw */ -#define reg_dma_rw_ctxt_md1_offset 56 - -/* Register rw_ctxt_md1_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md1_s_offset 60 - -/* Register rw_ctxt_md2, scope dma, type rw */ -#define reg_dma_rw_ctxt_md2_offset 64 - -/* Register rw_ctxt_md2_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md2_s_offset 68 - -/* Register rw_ctxt_md3, scope dma, type rw */ -#define reg_dma_rw_ctxt_md3_offset 72 - -/* Register rw_ctxt_md3_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md3_s_offset 76 - -/* Register rw_ctxt_md4, scope dma, type rw */ -#define reg_dma_rw_ctxt_md4_offset 80 - -/* Register rw_ctxt_md4_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md4_s_offset 84 - -/* Register rw_saved_data, scope dma, type rw */ -#define reg_dma_rw_saved_data_offset 88 - -/* Register rw_saved_data_buf, scope dma, type rw */ -#define reg_dma_rw_saved_data_buf_offset 92 - -/* Register rw_group, scope dma, type rw */ -#define reg_dma_rw_group_offset 96 - -/* Register rw_group_next, scope dma, type rw */ -#define reg_dma_rw_group_next_offset 100 - -/* Register rw_group_ctrl, scope dma, type rw */ -#define reg_dma_rw_group_ctrl___eol___lsb 0 -#define reg_dma_rw_group_ctrl___eol___width 1 -#define reg_dma_rw_group_ctrl___eol___bit 0 -#define reg_dma_rw_group_ctrl___tol___lsb 1 -#define reg_dma_rw_group_ctrl___tol___width 1 -#define reg_dma_rw_group_ctrl___tol___bit 1 -#define reg_dma_rw_group_ctrl___bol___lsb 2 -#define reg_dma_rw_group_ctrl___bol___width 1 -#define reg_dma_rw_group_ctrl___bol___bit 2 -#define reg_dma_rw_group_ctrl___intr___lsb 4 -#define reg_dma_rw_group_ctrl___intr___width 1 -#define reg_dma_rw_group_ctrl___intr___bit 4 -#define reg_dma_rw_group_ctrl___en___lsb 7 -#define reg_dma_rw_group_ctrl___en___width 1 -#define reg_dma_rw_group_ctrl___en___bit 7 -#define reg_dma_rw_group_ctrl_offset 104 - -/* Register rw_group_stat, scope dma, type rw */ -#define reg_dma_rw_group_stat___dis___lsb 7 -#define reg_dma_rw_group_stat___dis___width 1 -#define reg_dma_rw_group_stat___dis___bit 7 -#define reg_dma_rw_group_stat_offset 108 - -/* Register rw_group_md, scope dma, type rw */ -#define reg_dma_rw_group_md___md___lsb 0 -#define reg_dma_rw_group_md___md___width 16 -#define reg_dma_rw_group_md_offset 112 - -/* Register rw_group_md_s, scope dma, type rw */ -#define reg_dma_rw_group_md_s___md_s___lsb 0 -#define reg_dma_rw_group_md_s___md_s___width 16 -#define reg_dma_rw_group_md_s_offset 116 - -/* Register rw_group_up, scope dma, type rw */ -#define reg_dma_rw_group_up_offset 120 - -/* Register rw_group_down, scope dma, type rw */ -#define reg_dma_rw_group_down_offset 124 - -/* Register rw_cmd, scope dma, type rw */ -#define reg_dma_rw_cmd___cont_data___lsb 0 -#define reg_dma_rw_cmd___cont_data___width 1 -#define reg_dma_rw_cmd___cont_data___bit 0 -#define reg_dma_rw_cmd_offset 128 - -/* Register rw_cfg, scope dma, type rw */ -#define reg_dma_rw_cfg___en___lsb 0 -#define reg_dma_rw_cfg___en___width 1 -#define reg_dma_rw_cfg___en___bit 0 -#define reg_dma_rw_cfg___stop___lsb 1 -#define reg_dma_rw_cfg___stop___width 1 -#define reg_dma_rw_cfg___stop___bit 1 -#define reg_dma_rw_cfg_offset 132 - -/* Register rw_stat, scope dma, type rw */ -#define reg_dma_rw_stat___mode___lsb 0 -#define reg_dma_rw_stat___mode___width 5 -#define reg_dma_rw_stat___list_state___lsb 5 -#define reg_dma_rw_stat___list_state___width 3 -#define reg_dma_rw_stat___stream_cmd_src___lsb 8 -#define reg_dma_rw_stat___stream_cmd_src___width 8 -#define reg_dma_rw_stat___buf___lsb 24 -#define reg_dma_rw_stat___buf___width 8 -#define reg_dma_rw_stat_offset 136 - -/* Register rw_intr_mask, scope dma, type rw */ -#define reg_dma_rw_intr_mask___group___lsb 0 -#define reg_dma_rw_intr_mask___group___width 1 -#define reg_dma_rw_intr_mask___group___bit 0 -#define reg_dma_rw_intr_mask___ctxt___lsb 1 -#define reg_dma_rw_intr_mask___ctxt___width 1 -#define reg_dma_rw_intr_mask___ctxt___bit 1 -#define reg_dma_rw_intr_mask___data___lsb 2 -#define reg_dma_rw_intr_mask___data___width 1 -#define reg_dma_rw_intr_mask___data___bit 2 -#define reg_dma_rw_intr_mask___in_eop___lsb 3 -#define reg_dma_rw_intr_mask___in_eop___width 1 -#define reg_dma_rw_intr_mask___in_eop___bit 3 -#define reg_dma_rw_intr_mask___stream_cmd___lsb 4 -#define reg_dma_rw_intr_mask___stream_cmd___width 1 -#define reg_dma_rw_intr_mask___stream_cmd___bit 4 -#define reg_dma_rw_intr_mask_offset 140 - -/* Register rw_ack_intr, scope dma, type rw */ -#define reg_dma_rw_ack_intr___group___lsb 0 -#define reg_dma_rw_ack_intr___group___width 1 -#define reg_dma_rw_ack_intr___group___bit 0 -#define reg_dma_rw_ack_intr___ctxt___lsb 1 -#define reg_dma_rw_ack_intr___ctxt___width 1 -#define reg_dma_rw_ack_intr___ctxt___bit 1 -#define reg_dma_rw_ack_intr___data___lsb 2 -#define reg_dma_rw_ack_intr___data___width 1 -#define reg_dma_rw_ack_intr___data___bit 2 -#define reg_dma_rw_ack_intr___in_eop___lsb 3 -#define reg_dma_rw_ack_intr___in_eop___width 1 -#define reg_dma_rw_ack_intr___in_eop___bit 3 -#define reg_dma_rw_ack_intr___stream_cmd___lsb 4 -#define reg_dma_rw_ack_intr___stream_cmd___width 1 -#define reg_dma_rw_ack_intr___stream_cmd___bit 4 -#define reg_dma_rw_ack_intr_offset 144 - -/* Register r_intr, scope dma, type r */ -#define reg_dma_r_intr___group___lsb 0 -#define reg_dma_r_intr___group___width 1 -#define reg_dma_r_intr___group___bit 0 -#define reg_dma_r_intr___ctxt___lsb 1 -#define reg_dma_r_intr___ctxt___width 1 -#define reg_dma_r_intr___ctxt___bit 1 -#define reg_dma_r_intr___data___lsb 2 -#define reg_dma_r_intr___data___width 1 -#define reg_dma_r_intr___data___bit 2 -#define reg_dma_r_intr___in_eop___lsb 3 -#define reg_dma_r_intr___in_eop___width 1 -#define reg_dma_r_intr___in_eop___bit 3 -#define reg_dma_r_intr___stream_cmd___lsb 4 -#define reg_dma_r_intr___stream_cmd___width 1 -#define reg_dma_r_intr___stream_cmd___bit 4 -#define reg_dma_r_intr_offset 148 - -/* Register r_masked_intr, scope dma, type r */ -#define reg_dma_r_masked_intr___group___lsb 0 -#define reg_dma_r_masked_intr___group___width 1 -#define reg_dma_r_masked_intr___group___bit 0 -#define reg_dma_r_masked_intr___ctxt___lsb 1 -#define reg_dma_r_masked_intr___ctxt___width 1 -#define reg_dma_r_masked_intr___ctxt___bit 1 -#define reg_dma_r_masked_intr___data___lsb 2 -#define reg_dma_r_masked_intr___data___width 1 -#define reg_dma_r_masked_intr___data___bit 2 -#define reg_dma_r_masked_intr___in_eop___lsb 3 -#define reg_dma_r_masked_intr___in_eop___width 1 -#define reg_dma_r_masked_intr___in_eop___bit 3 -#define reg_dma_r_masked_intr___stream_cmd___lsb 4 -#define reg_dma_r_masked_intr___stream_cmd___width 1 -#define reg_dma_r_masked_intr___stream_cmd___bit 4 -#define reg_dma_r_masked_intr_offset 152 - -/* Register rw_stream_cmd, scope dma, type rw */ -#define reg_dma_rw_stream_cmd___cmd___lsb 0 -#define reg_dma_rw_stream_cmd___cmd___width 10 -#define reg_dma_rw_stream_cmd___n___lsb 16 -#define reg_dma_rw_stream_cmd___n___width 8 -#define reg_dma_rw_stream_cmd___busy___lsb 31 -#define reg_dma_rw_stream_cmd___busy___width 1 -#define reg_dma_rw_stream_cmd___busy___bit 31 -#define reg_dma_rw_stream_cmd_offset 156 - - -/* Constants */ -#define regk_dma_ack_pkt 0x00000100 -#define regk_dma_anytime 0x00000001 -#define regk_dma_array 0x00000008 -#define regk_dma_burst 0x00000020 -#define regk_dma_client 0x00000002 -#define regk_dma_copy_next 0x00000010 -#define regk_dma_copy_up 0x00000020 -#define regk_dma_data_at_eol 0x00000001 -#define regk_dma_dis_c 0x00000010 -#define regk_dma_dis_g 0x00000020 -#define regk_dma_idle 0x00000001 -#define regk_dma_intern 0x00000004 -#define regk_dma_load_c 0x00000200 -#define regk_dma_load_c_n 0x00000280 -#define regk_dma_load_c_next 0x00000240 -#define regk_dma_load_d 0x00000140 -#define regk_dma_load_g 0x00000300 -#define regk_dma_load_g_down 0x000003c0 -#define regk_dma_load_g_next 0x00000340 -#define regk_dma_load_g_up 0x00000380 -#define regk_dma_next_en 0x00000010 -#define regk_dma_next_pkt 0x00000010 -#define regk_dma_no 0x00000000 -#define regk_dma_only_at_wait 0x00000000 -#define regk_dma_restore 0x00000020 -#define regk_dma_rst 0x00000001 -#define regk_dma_running 0x00000004 -#define regk_dma_rw_cfg_default 0x00000000 -#define regk_dma_rw_cmd_default 0x00000000 -#define regk_dma_rw_intr_mask_default 0x00000000 -#define regk_dma_rw_stat_default 0x00000101 -#define regk_dma_rw_stream_cmd_default 0x00000000 -#define regk_dma_save_down 0x00000020 -#define regk_dma_save_up 0x00000020 -#define regk_dma_set_reg 0x00000050 -#define regk_dma_set_w_size1 0x00000190 -#define regk_dma_set_w_size2 0x000001a0 -#define regk_dma_set_w_size4 0x000001c0 -#define regk_dma_stopped 0x00000002 -#define regk_dma_store_c 0x00000002 -#define regk_dma_store_descr 0x00000000 -#define regk_dma_store_g 0x00000004 -#define regk_dma_store_md 0x00000001 -#define regk_dma_sw 0x00000008 -#define regk_dma_update_down 0x00000020 -#define regk_dma_yes 0x00000001 -#endif /* __dma_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h deleted file mode 100644 index c9f49864831b..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h +++ /dev/null @@ -1,498 +0,0 @@ -#ifndef __eth_defs_asm_h -#define __eth_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/eth/rtl/eth_regs.r - * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp - * last modfied: Mon Apr 11 16:07:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r - * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ma0_lo, scope eth, type rw */ -#define reg_eth_rw_ma0_lo___addr___lsb 0 -#define reg_eth_rw_ma0_lo___addr___width 32 -#define reg_eth_rw_ma0_lo_offset 0 - -/* Register rw_ma0_hi, scope eth, type rw */ -#define reg_eth_rw_ma0_hi___addr___lsb 0 -#define reg_eth_rw_ma0_hi___addr___width 16 -#define reg_eth_rw_ma0_hi_offset 4 - -/* Register rw_ma1_lo, scope eth, type rw */ -#define reg_eth_rw_ma1_lo___addr___lsb 0 -#define reg_eth_rw_ma1_lo___addr___width 32 -#define reg_eth_rw_ma1_lo_offset 8 - -/* Register rw_ma1_hi, scope eth, type rw */ -#define reg_eth_rw_ma1_hi___addr___lsb 0 -#define reg_eth_rw_ma1_hi___addr___width 16 -#define reg_eth_rw_ma1_hi_offset 12 - -/* Register rw_ga_lo, scope eth, type rw */ -#define reg_eth_rw_ga_lo___table___lsb 0 -#define reg_eth_rw_ga_lo___table___width 32 -#define reg_eth_rw_ga_lo_offset 16 - -/* Register rw_ga_hi, scope eth, type rw */ -#define reg_eth_rw_ga_hi___table___lsb 0 -#define reg_eth_rw_ga_hi___table___width 32 -#define reg_eth_rw_ga_hi_offset 20 - -/* Register rw_gen_ctrl, scope eth, type rw */ -#define reg_eth_rw_gen_ctrl___en___lsb 0 -#define reg_eth_rw_gen_ctrl___en___width 1 -#define reg_eth_rw_gen_ctrl___en___bit 0 -#define reg_eth_rw_gen_ctrl___phy___lsb 1 -#define reg_eth_rw_gen_ctrl___phy___width 2 -#define reg_eth_rw_gen_ctrl___protocol___lsb 3 -#define reg_eth_rw_gen_ctrl___protocol___width 1 -#define reg_eth_rw_gen_ctrl___protocol___bit 3 -#define reg_eth_rw_gen_ctrl___loopback___lsb 4 -#define reg_eth_rw_gen_ctrl___loopback___width 1 -#define reg_eth_rw_gen_ctrl___loopback___bit 4 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5 -#define reg_eth_rw_gen_ctrl_offset 24 - -/* Register rw_rec_ctrl, scope eth, type rw */ -#define reg_eth_rw_rec_ctrl___ma0___lsb 0 -#define reg_eth_rw_rec_ctrl___ma0___width 1 -#define reg_eth_rw_rec_ctrl___ma0___bit 0 -#define reg_eth_rw_rec_ctrl___ma1___lsb 1 -#define reg_eth_rw_rec_ctrl___ma1___width 1 -#define reg_eth_rw_rec_ctrl___ma1___bit 1 -#define reg_eth_rw_rec_ctrl___individual___lsb 2 -#define reg_eth_rw_rec_ctrl___individual___width 1 -#define reg_eth_rw_rec_ctrl___individual___bit 2 -#define reg_eth_rw_rec_ctrl___broadcast___lsb 3 -#define reg_eth_rw_rec_ctrl___broadcast___width 1 -#define reg_eth_rw_rec_ctrl___broadcast___bit 3 -#define reg_eth_rw_rec_ctrl___undersize___lsb 4 -#define reg_eth_rw_rec_ctrl___undersize___width 1 -#define reg_eth_rw_rec_ctrl___undersize___bit 4 -#define reg_eth_rw_rec_ctrl___oversize___lsb 5 -#define reg_eth_rw_rec_ctrl___oversize___width 1 -#define reg_eth_rw_rec_ctrl___oversize___bit 5 -#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6 -#define reg_eth_rw_rec_ctrl___bad_crc___width 1 -#define reg_eth_rw_rec_ctrl___bad_crc___bit 6 -#define reg_eth_rw_rec_ctrl___duplex___lsb 7 -#define reg_eth_rw_rec_ctrl___duplex___width 1 -#define reg_eth_rw_rec_ctrl___duplex___bit 7 -#define reg_eth_rw_rec_ctrl___max_size___lsb 8 -#define reg_eth_rw_rec_ctrl___max_size___width 1 -#define reg_eth_rw_rec_ctrl___max_size___bit 8 -#define reg_eth_rw_rec_ctrl_offset 28 - -/* Register rw_tr_ctrl, scope eth, type rw */ -#define reg_eth_rw_tr_ctrl___crc___lsb 0 -#define reg_eth_rw_tr_ctrl___crc___width 1 -#define reg_eth_rw_tr_ctrl___crc___bit 0 -#define reg_eth_rw_tr_ctrl___pad___lsb 1 -#define reg_eth_rw_tr_ctrl___pad___width 1 -#define reg_eth_rw_tr_ctrl___pad___bit 1 -#define reg_eth_rw_tr_ctrl___retry___lsb 2 -#define reg_eth_rw_tr_ctrl___retry___width 1 -#define reg_eth_rw_tr_ctrl___retry___bit 2 -#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3 -#define reg_eth_rw_tr_ctrl___ignore_col___width 1 -#define reg_eth_rw_tr_ctrl___ignore_col___bit 3 -#define reg_eth_rw_tr_ctrl___cancel___lsb 4 -#define reg_eth_rw_tr_ctrl___cancel___width 1 -#define reg_eth_rw_tr_ctrl___cancel___bit 4 -#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5 -#define reg_eth_rw_tr_ctrl___hsh_delay___width 1 -#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5 -#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6 -#define reg_eth_rw_tr_ctrl___ignore_crs___width 1 -#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6 -#define reg_eth_rw_tr_ctrl_offset 32 - -/* Register rw_clr_err, scope eth, type rw */ -#define reg_eth_rw_clr_err___clr___lsb 0 -#define reg_eth_rw_clr_err___clr___width 1 -#define reg_eth_rw_clr_err___clr___bit 0 -#define reg_eth_rw_clr_err_offset 36 - -/* Register rw_mgm_ctrl, scope eth, type rw */ -#define reg_eth_rw_mgm_ctrl___mdio___lsb 0 -#define reg_eth_rw_mgm_ctrl___mdio___width 1 -#define reg_eth_rw_mgm_ctrl___mdio___bit 0 -#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1 -#define reg_eth_rw_mgm_ctrl___mdoe___width 1 -#define reg_eth_rw_mgm_ctrl___mdoe___bit 1 -#define reg_eth_rw_mgm_ctrl___mdc___lsb 2 -#define reg_eth_rw_mgm_ctrl___mdc___width 1 -#define reg_eth_rw_mgm_ctrl___mdc___bit 2 -#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3 -#define reg_eth_rw_mgm_ctrl___phyclk___width 1 -#define reg_eth_rw_mgm_ctrl___phyclk___bit 3 -#define reg_eth_rw_mgm_ctrl___txdata___lsb 4 -#define reg_eth_rw_mgm_ctrl___txdata___width 4 -#define reg_eth_rw_mgm_ctrl___txen___lsb 8 -#define reg_eth_rw_mgm_ctrl___txen___width 1 -#define reg_eth_rw_mgm_ctrl___txen___bit 8 -#define reg_eth_rw_mgm_ctrl_offset 40 - -/* Register r_stat, scope eth, type r */ -#define reg_eth_r_stat___mdio___lsb 0 -#define reg_eth_r_stat___mdio___width 1 -#define reg_eth_r_stat___mdio___bit 0 -#define reg_eth_r_stat___exc_col___lsb 1 -#define reg_eth_r_stat___exc_col___width 1 -#define reg_eth_r_stat___exc_col___bit 1 -#define reg_eth_r_stat___urun___lsb 2 -#define reg_eth_r_stat___urun___width 1 -#define reg_eth_r_stat___urun___bit 2 -#define reg_eth_r_stat___phyclk___lsb 3 -#define reg_eth_r_stat___phyclk___width 1 -#define reg_eth_r_stat___phyclk___bit 3 -#define reg_eth_r_stat___txdata___lsb 4 -#define reg_eth_r_stat___txdata___width 4 -#define reg_eth_r_stat___txen___lsb 8 -#define reg_eth_r_stat___txen___width 1 -#define reg_eth_r_stat___txen___bit 8 -#define reg_eth_r_stat___col___lsb 9 -#define reg_eth_r_stat___col___width 1 -#define reg_eth_r_stat___col___bit 9 -#define reg_eth_r_stat___crs___lsb 10 -#define reg_eth_r_stat___crs___width 1 -#define reg_eth_r_stat___crs___bit 10 -#define reg_eth_r_stat___txclk___lsb 11 -#define reg_eth_r_stat___txclk___width 1 -#define reg_eth_r_stat___txclk___bit 11 -#define reg_eth_r_stat___rxdata___lsb 12 -#define reg_eth_r_stat___rxdata___width 4 -#define reg_eth_r_stat___rxer___lsb 16 -#define reg_eth_r_stat___rxer___width 1 -#define reg_eth_r_stat___rxer___bit 16 -#define reg_eth_r_stat___rxdv___lsb 17 -#define reg_eth_r_stat___rxdv___width 1 -#define reg_eth_r_stat___rxdv___bit 17 -#define reg_eth_r_stat___rxclk___lsb 18 -#define reg_eth_r_stat___rxclk___width 1 -#define reg_eth_r_stat___rxclk___bit 18 -#define reg_eth_r_stat_offset 44 - -/* Register rs_rec_cnt, scope eth, type rs */ -#define reg_eth_rs_rec_cnt___crc_err___lsb 0 -#define reg_eth_rs_rec_cnt___crc_err___width 8 -#define reg_eth_rs_rec_cnt___align_err___lsb 8 -#define reg_eth_rs_rec_cnt___align_err___width 8 -#define reg_eth_rs_rec_cnt___oversize___lsb 16 -#define reg_eth_rs_rec_cnt___oversize___width 8 -#define reg_eth_rs_rec_cnt___congestion___lsb 24 -#define reg_eth_rs_rec_cnt___congestion___width 8 -#define reg_eth_rs_rec_cnt_offset 48 - -/* Register r_rec_cnt, scope eth, type r */ -#define reg_eth_r_rec_cnt___crc_err___lsb 0 -#define reg_eth_r_rec_cnt___crc_err___width 8 -#define reg_eth_r_rec_cnt___align_err___lsb 8 -#define reg_eth_r_rec_cnt___align_err___width 8 -#define reg_eth_r_rec_cnt___oversize___lsb 16 -#define reg_eth_r_rec_cnt___oversize___width 8 -#define reg_eth_r_rec_cnt___congestion___lsb 24 -#define reg_eth_r_rec_cnt___congestion___width 8 -#define reg_eth_r_rec_cnt_offset 52 - -/* Register rs_tr_cnt, scope eth, type rs */ -#define reg_eth_rs_tr_cnt___single_col___lsb 0 -#define reg_eth_rs_tr_cnt___single_col___width 8 -#define reg_eth_rs_tr_cnt___mult_col___lsb 8 -#define reg_eth_rs_tr_cnt___mult_col___width 8 -#define reg_eth_rs_tr_cnt___late_col___lsb 16 -#define reg_eth_rs_tr_cnt___late_col___width 8 -#define reg_eth_rs_tr_cnt___deferred___lsb 24 -#define reg_eth_rs_tr_cnt___deferred___width 8 -#define reg_eth_rs_tr_cnt_offset 56 - -/* Register r_tr_cnt, scope eth, type r */ -#define reg_eth_r_tr_cnt___single_col___lsb 0 -#define reg_eth_r_tr_cnt___single_col___width 8 -#define reg_eth_r_tr_cnt___mult_col___lsb 8 -#define reg_eth_r_tr_cnt___mult_col___width 8 -#define reg_eth_r_tr_cnt___late_col___lsb 16 -#define reg_eth_r_tr_cnt___late_col___width 8 -#define reg_eth_r_tr_cnt___deferred___lsb 24 -#define reg_eth_r_tr_cnt___deferred___width 8 -#define reg_eth_r_tr_cnt_offset 60 - -/* Register rs_phy_cnt, scope eth, type rs */ -#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0 -#define reg_eth_rs_phy_cnt___carrier_loss___width 8 -#define reg_eth_rs_phy_cnt___sqe_err___lsb 8 -#define reg_eth_rs_phy_cnt___sqe_err___width 8 -#define reg_eth_rs_phy_cnt_offset 64 - -/* Register r_phy_cnt, scope eth, type r */ -#define reg_eth_r_phy_cnt___carrier_loss___lsb 0 -#define reg_eth_r_phy_cnt___carrier_loss___width 8 -#define reg_eth_r_phy_cnt___sqe_err___lsb 8 -#define reg_eth_r_phy_cnt___sqe_err___width 8 -#define reg_eth_r_phy_cnt_offset 68 - -/* Register rw_test_ctrl, scope eth, type rw */ -#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0 -#define reg_eth_rw_test_ctrl___snmp_inc___width 1 -#define reg_eth_rw_test_ctrl___snmp_inc___bit 0 -#define reg_eth_rw_test_ctrl___snmp___lsb 1 -#define reg_eth_rw_test_ctrl___snmp___width 1 -#define reg_eth_rw_test_ctrl___snmp___bit 1 -#define reg_eth_rw_test_ctrl___backoff___lsb 2 -#define reg_eth_rw_test_ctrl___backoff___width 1 -#define reg_eth_rw_test_ctrl___backoff___bit 2 -#define reg_eth_rw_test_ctrl_offset 72 - -/* Register rw_intr_mask, scope eth, type rw */ -#define reg_eth_rw_intr_mask___crc___lsb 0 -#define reg_eth_rw_intr_mask___crc___width 1 -#define reg_eth_rw_intr_mask___crc___bit 0 -#define reg_eth_rw_intr_mask___align___lsb 1 -#define reg_eth_rw_intr_mask___align___width 1 -#define reg_eth_rw_intr_mask___align___bit 1 -#define reg_eth_rw_intr_mask___oversize___lsb 2 -#define reg_eth_rw_intr_mask___oversize___width 1 -#define reg_eth_rw_intr_mask___oversize___bit 2 -#define reg_eth_rw_intr_mask___congestion___lsb 3 -#define reg_eth_rw_intr_mask___congestion___width 1 -#define reg_eth_rw_intr_mask___congestion___bit 3 -#define reg_eth_rw_intr_mask___single_col___lsb 4 -#define reg_eth_rw_intr_mask___single_col___width 1 -#define reg_eth_rw_intr_mask___single_col___bit 4 -#define reg_eth_rw_intr_mask___mult_col___lsb 5 -#define reg_eth_rw_intr_mask___mult_col___width 1 -#define reg_eth_rw_intr_mask___mult_col___bit 5 -#define reg_eth_rw_intr_mask___late_col___lsb 6 -#define reg_eth_rw_intr_mask___late_col___width 1 -#define reg_eth_rw_intr_mask___late_col___bit 6 -#define reg_eth_rw_intr_mask___deferred___lsb 7 -#define reg_eth_rw_intr_mask___deferred___width 1 -#define reg_eth_rw_intr_mask___deferred___bit 7 -#define reg_eth_rw_intr_mask___carrier_loss___lsb 8 -#define reg_eth_rw_intr_mask___carrier_loss___width 1 -#define reg_eth_rw_intr_mask___carrier_loss___bit 8 -#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9 -#define reg_eth_rw_intr_mask___sqe_test_err___width 1 -#define reg_eth_rw_intr_mask___sqe_test_err___bit 9 -#define reg_eth_rw_intr_mask___orun___lsb 10 -#define reg_eth_rw_intr_mask___orun___width 1 -#define reg_eth_rw_intr_mask___orun___bit 10 -#define reg_eth_rw_intr_mask___urun___lsb 11 -#define reg_eth_rw_intr_mask___urun___width 1 -#define reg_eth_rw_intr_mask___urun___bit 11 -#define reg_eth_rw_intr_mask___excessive_col___lsb 12 -#define reg_eth_rw_intr_mask___excessive_col___width 1 -#define reg_eth_rw_intr_mask___excessive_col___bit 12 -#define reg_eth_rw_intr_mask___mdio___lsb 13 -#define reg_eth_rw_intr_mask___mdio___width 1 -#define reg_eth_rw_intr_mask___mdio___bit 13 -#define reg_eth_rw_intr_mask_offset 76 - -/* Register rw_ack_intr, scope eth, type rw */ -#define reg_eth_rw_ack_intr___crc___lsb 0 -#define reg_eth_rw_ack_intr___crc___width 1 -#define reg_eth_rw_ack_intr___crc___bit 0 -#define reg_eth_rw_ack_intr___align___lsb 1 -#define reg_eth_rw_ack_intr___align___width 1 -#define reg_eth_rw_ack_intr___align___bit 1 -#define reg_eth_rw_ack_intr___oversize___lsb 2 -#define reg_eth_rw_ack_intr___oversize___width 1 -#define reg_eth_rw_ack_intr___oversize___bit 2 -#define reg_eth_rw_ack_intr___congestion___lsb 3 -#define reg_eth_rw_ack_intr___congestion___width 1 -#define reg_eth_rw_ack_intr___congestion___bit 3 -#define reg_eth_rw_ack_intr___single_col___lsb 4 -#define reg_eth_rw_ack_intr___single_col___width 1 -#define reg_eth_rw_ack_intr___single_col___bit 4 -#define reg_eth_rw_ack_intr___mult_col___lsb 5 -#define reg_eth_rw_ack_intr___mult_col___width 1 -#define reg_eth_rw_ack_intr___mult_col___bit 5 -#define reg_eth_rw_ack_intr___late_col___lsb 6 -#define reg_eth_rw_ack_intr___late_col___width 1 -#define reg_eth_rw_ack_intr___late_col___bit 6 -#define reg_eth_rw_ack_intr___deferred___lsb 7 -#define reg_eth_rw_ack_intr___deferred___width 1 -#define reg_eth_rw_ack_intr___deferred___bit 7 -#define reg_eth_rw_ack_intr___carrier_loss___lsb 8 -#define reg_eth_rw_ack_intr___carrier_loss___width 1 -#define reg_eth_rw_ack_intr___carrier_loss___bit 8 -#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9 -#define reg_eth_rw_ack_intr___sqe_test_err___width 1 -#define reg_eth_rw_ack_intr___sqe_test_err___bit 9 -#define reg_eth_rw_ack_intr___orun___lsb 10 -#define reg_eth_rw_ack_intr___orun___width 1 -#define reg_eth_rw_ack_intr___orun___bit 10 -#define reg_eth_rw_ack_intr___urun___lsb 11 -#define reg_eth_rw_ack_intr___urun___width 1 -#define reg_eth_rw_ack_intr___urun___bit 11 -#define reg_eth_rw_ack_intr___excessive_col___lsb 12 -#define reg_eth_rw_ack_intr___excessive_col___width 1 -#define reg_eth_rw_ack_intr___excessive_col___bit 12 -#define reg_eth_rw_ack_intr___mdio___lsb 13 -#define reg_eth_rw_ack_intr___mdio___width 1 -#define reg_eth_rw_ack_intr___mdio___bit 13 -#define reg_eth_rw_ack_intr_offset 80 - -/* Register r_intr, scope eth, type r */ -#define reg_eth_r_intr___crc___lsb 0 -#define reg_eth_r_intr___crc___width 1 -#define reg_eth_r_intr___crc___bit 0 -#define reg_eth_r_intr___align___lsb 1 -#define reg_eth_r_intr___align___width 1 -#define reg_eth_r_intr___align___bit 1 -#define reg_eth_r_intr___oversize___lsb 2 -#define reg_eth_r_intr___oversize___width 1 -#define reg_eth_r_intr___oversize___bit 2 -#define reg_eth_r_intr___congestion___lsb 3 -#define reg_eth_r_intr___congestion___width 1 -#define reg_eth_r_intr___congestion___bit 3 -#define reg_eth_r_intr___single_col___lsb 4 -#define reg_eth_r_intr___single_col___width 1 -#define reg_eth_r_intr___single_col___bit 4 -#define reg_eth_r_intr___mult_col___lsb 5 -#define reg_eth_r_intr___mult_col___width 1 -#define reg_eth_r_intr___mult_col___bit 5 -#define reg_eth_r_intr___late_col___lsb 6 -#define reg_eth_r_intr___late_col___width 1 -#define reg_eth_r_intr___late_col___bit 6 -#define reg_eth_r_intr___deferred___lsb 7 -#define reg_eth_r_intr___deferred___width 1 -#define reg_eth_r_intr___deferred___bit 7 -#define reg_eth_r_intr___carrier_loss___lsb 8 -#define reg_eth_r_intr___carrier_loss___width 1 -#define reg_eth_r_intr___carrier_loss___bit 8 -#define reg_eth_r_intr___sqe_test_err___lsb 9 -#define reg_eth_r_intr___sqe_test_err___width 1 -#define reg_eth_r_intr___sqe_test_err___bit 9 -#define reg_eth_r_intr___orun___lsb 10 -#define reg_eth_r_intr___orun___width 1 -#define reg_eth_r_intr___orun___bit 10 -#define reg_eth_r_intr___urun___lsb 11 -#define reg_eth_r_intr___urun___width 1 -#define reg_eth_r_intr___urun___bit 11 -#define reg_eth_r_intr___excessive_col___lsb 12 -#define reg_eth_r_intr___excessive_col___width 1 -#define reg_eth_r_intr___excessive_col___bit 12 -#define reg_eth_r_intr___mdio___lsb 13 -#define reg_eth_r_intr___mdio___width 1 -#define reg_eth_r_intr___mdio___bit 13 -#define reg_eth_r_intr_offset 84 - -/* Register r_masked_intr, scope eth, type r */ -#define reg_eth_r_masked_intr___crc___lsb 0 -#define reg_eth_r_masked_intr___crc___width 1 -#define reg_eth_r_masked_intr___crc___bit 0 -#define reg_eth_r_masked_intr___align___lsb 1 -#define reg_eth_r_masked_intr___align___width 1 -#define reg_eth_r_masked_intr___align___bit 1 -#define reg_eth_r_masked_intr___oversize___lsb 2 -#define reg_eth_r_masked_intr___oversize___width 1 -#define reg_eth_r_masked_intr___oversize___bit 2 -#define reg_eth_r_masked_intr___congestion___lsb 3 -#define reg_eth_r_masked_intr___congestion___width 1 -#define reg_eth_r_masked_intr___congestion___bit 3 -#define reg_eth_r_masked_intr___single_col___lsb 4 -#define reg_eth_r_masked_intr___single_col___width 1 -#define reg_eth_r_masked_intr___single_col___bit 4 -#define reg_eth_r_masked_intr___mult_col___lsb 5 -#define reg_eth_r_masked_intr___mult_col___width 1 -#define reg_eth_r_masked_intr___mult_col___bit 5 -#define reg_eth_r_masked_intr___late_col___lsb 6 -#define reg_eth_r_masked_intr___late_col___width 1 -#define reg_eth_r_masked_intr___late_col___bit 6 -#define reg_eth_r_masked_intr___deferred___lsb 7 -#define reg_eth_r_masked_intr___deferred___width 1 -#define reg_eth_r_masked_intr___deferred___bit 7 -#define reg_eth_r_masked_intr___carrier_loss___lsb 8 -#define reg_eth_r_masked_intr___carrier_loss___width 1 -#define reg_eth_r_masked_intr___carrier_loss___bit 8 -#define reg_eth_r_masked_intr___sqe_test_err___lsb 9 -#define reg_eth_r_masked_intr___sqe_test_err___width 1 -#define reg_eth_r_masked_intr___sqe_test_err___bit 9 -#define reg_eth_r_masked_intr___orun___lsb 10 -#define reg_eth_r_masked_intr___orun___width 1 -#define reg_eth_r_masked_intr___orun___bit 10 -#define reg_eth_r_masked_intr___urun___lsb 11 -#define reg_eth_r_masked_intr___urun___width 1 -#define reg_eth_r_masked_intr___urun___bit 11 -#define reg_eth_r_masked_intr___excessive_col___lsb 12 -#define reg_eth_r_masked_intr___excessive_col___width 1 -#define reg_eth_r_masked_intr___excessive_col___bit 12 -#define reg_eth_r_masked_intr___mdio___lsb 13 -#define reg_eth_r_masked_intr___mdio___width 1 -#define reg_eth_r_masked_intr___mdio___bit 13 -#define reg_eth_r_masked_intr_offset 88 - - -/* Constants */ -#define regk_eth_discard 0x00000000 -#define regk_eth_ether 0x00000000 -#define regk_eth_full 0x00000001 -#define regk_eth_half 0x00000000 -#define regk_eth_hsh 0x00000001 -#define regk_eth_mii 0x00000001 -#define regk_eth_mii_clk 0x00000000 -#define regk_eth_mii_rec 0x00000002 -#define regk_eth_no 0x00000000 -#define regk_eth_rec 0x00000001 -#define regk_eth_rw_ga_hi_default 0x00000000 -#define regk_eth_rw_ga_lo_default 0x00000000 -#define regk_eth_rw_gen_ctrl_default 0x00000000 -#define regk_eth_rw_intr_mask_default 0x00000000 -#define regk_eth_rw_ma0_hi_default 0x00000000 -#define regk_eth_rw_ma0_lo_default 0x00000000 -#define regk_eth_rw_ma1_hi_default 0x00000000 -#define regk_eth_rw_ma1_lo_default 0x00000000 -#define regk_eth_rw_mgm_ctrl_default 0x00000000 -#define regk_eth_rw_test_ctrl_default 0x00000000 -#define regk_eth_size1518 0x00000000 -#define regk_eth_size1522 0x00000001 -#define regk_eth_yes 0x00000001 -#endif /* __eth_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index 35356bc08629..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,276 +0,0 @@ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 8 -#define reg_gio_rw_pa_dout_offset 0 - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 8 -#define reg_gio_r_pa_din_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 8 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___pa0___lsb 0 -#define reg_gio_rw_intr_cfg___pa0___width 3 -#define reg_gio_rw_intr_cfg___pa1___lsb 3 -#define reg_gio_rw_intr_cfg___pa1___width 3 -#define reg_gio_rw_intr_cfg___pa2___lsb 6 -#define reg_gio_rw_intr_cfg___pa2___width 3 -#define reg_gio_rw_intr_cfg___pa3___lsb 9 -#define reg_gio_rw_intr_cfg___pa3___width 3 -#define reg_gio_rw_intr_cfg___pa4___lsb 12 -#define reg_gio_rw_intr_cfg___pa4___width 3 -#define reg_gio_rw_intr_cfg___pa5___lsb 15 -#define reg_gio_rw_intr_cfg___pa5___width 3 -#define reg_gio_rw_intr_cfg___pa6___lsb 18 -#define reg_gio_rw_intr_cfg___pa6___width 3 -#define reg_gio_rw_intr_cfg___pa7___lsb 21 -#define reg_gio_rw_intr_cfg___pa7___width 3 -#define reg_gio_rw_intr_cfg_offset 12 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___pa0___lsb 0 -#define reg_gio_rw_intr_mask___pa0___width 1 -#define reg_gio_rw_intr_mask___pa0___bit 0 -#define reg_gio_rw_intr_mask___pa1___lsb 1 -#define reg_gio_rw_intr_mask___pa1___width 1 -#define reg_gio_rw_intr_mask___pa1___bit 1 -#define reg_gio_rw_intr_mask___pa2___lsb 2 -#define reg_gio_rw_intr_mask___pa2___width 1 -#define reg_gio_rw_intr_mask___pa2___bit 2 -#define reg_gio_rw_intr_mask___pa3___lsb 3 -#define reg_gio_rw_intr_mask___pa3___width 1 -#define reg_gio_rw_intr_mask___pa3___bit 3 -#define reg_gio_rw_intr_mask___pa4___lsb 4 -#define reg_gio_rw_intr_mask___pa4___width 1 -#define reg_gio_rw_intr_mask___pa4___bit 4 -#define reg_gio_rw_intr_mask___pa5___lsb 5 -#define reg_gio_rw_intr_mask___pa5___width 1 -#define reg_gio_rw_intr_mask___pa5___bit 5 -#define reg_gio_rw_intr_mask___pa6___lsb 6 -#define reg_gio_rw_intr_mask___pa6___width 1 -#define reg_gio_rw_intr_mask___pa6___bit 6 -#define reg_gio_rw_intr_mask___pa7___lsb 7 -#define reg_gio_rw_intr_mask___pa7___width 1 -#define reg_gio_rw_intr_mask___pa7___bit 7 -#define reg_gio_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___pa0___lsb 0 -#define reg_gio_rw_ack_intr___pa0___width 1 -#define reg_gio_rw_ack_intr___pa0___bit 0 -#define reg_gio_rw_ack_intr___pa1___lsb 1 -#define reg_gio_rw_ack_intr___pa1___width 1 -#define reg_gio_rw_ack_intr___pa1___bit 1 -#define reg_gio_rw_ack_intr___pa2___lsb 2 -#define reg_gio_rw_ack_intr___pa2___width 1 -#define reg_gio_rw_ack_intr___pa2___bit 2 -#define reg_gio_rw_ack_intr___pa3___lsb 3 -#define reg_gio_rw_ack_intr___pa3___width 1 -#define reg_gio_rw_ack_intr___pa3___bit 3 -#define reg_gio_rw_ack_intr___pa4___lsb 4 -#define reg_gio_rw_ack_intr___pa4___width 1 -#define reg_gio_rw_ack_intr___pa4___bit 4 -#define reg_gio_rw_ack_intr___pa5___lsb 5 -#define reg_gio_rw_ack_intr___pa5___width 1 -#define reg_gio_rw_ack_intr___pa5___bit 5 -#define reg_gio_rw_ack_intr___pa6___lsb 6 -#define reg_gio_rw_ack_intr___pa6___width 1 -#define reg_gio_rw_ack_intr___pa6___bit 6 -#define reg_gio_rw_ack_intr___pa7___lsb 7 -#define reg_gio_rw_ack_intr___pa7___width 1 -#define reg_gio_rw_ack_intr___pa7___bit 7 -#define reg_gio_rw_ack_intr_offset 20 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___pa0___lsb 0 -#define reg_gio_r_intr___pa0___width 1 -#define reg_gio_r_intr___pa0___bit 0 -#define reg_gio_r_intr___pa1___lsb 1 -#define reg_gio_r_intr___pa1___width 1 -#define reg_gio_r_intr___pa1___bit 1 -#define reg_gio_r_intr___pa2___lsb 2 -#define reg_gio_r_intr___pa2___width 1 -#define reg_gio_r_intr___pa2___bit 2 -#define reg_gio_r_intr___pa3___lsb 3 -#define reg_gio_r_intr___pa3___width 1 -#define reg_gio_r_intr___pa3___bit 3 -#define reg_gio_r_intr___pa4___lsb 4 -#define reg_gio_r_intr___pa4___width 1 -#define reg_gio_r_intr___pa4___bit 4 -#define reg_gio_r_intr___pa5___lsb 5 -#define reg_gio_r_intr___pa5___width 1 -#define reg_gio_r_intr___pa5___bit 5 -#define reg_gio_r_intr___pa6___lsb 6 -#define reg_gio_r_intr___pa6___width 1 -#define reg_gio_r_intr___pa6___bit 6 -#define reg_gio_r_intr___pa7___lsb 7 -#define reg_gio_r_intr___pa7___width 1 -#define reg_gio_r_intr___pa7___bit 7 -#define reg_gio_r_intr_offset 24 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___pa0___lsb 0 -#define reg_gio_r_masked_intr___pa0___width 1 -#define reg_gio_r_masked_intr___pa0___bit 0 -#define reg_gio_r_masked_intr___pa1___lsb 1 -#define reg_gio_r_masked_intr___pa1___width 1 -#define reg_gio_r_masked_intr___pa1___bit 1 -#define reg_gio_r_masked_intr___pa2___lsb 2 -#define reg_gio_r_masked_intr___pa2___width 1 -#define reg_gio_r_masked_intr___pa2___bit 2 -#define reg_gio_r_masked_intr___pa3___lsb 3 -#define reg_gio_r_masked_intr___pa3___width 1 -#define reg_gio_r_masked_intr___pa3___bit 3 -#define reg_gio_r_masked_intr___pa4___lsb 4 -#define reg_gio_r_masked_intr___pa4___width 1 -#define reg_gio_r_masked_intr___pa4___bit 4 -#define reg_gio_r_masked_intr___pa5___lsb 5 -#define reg_gio_r_masked_intr___pa5___width 1 -#define reg_gio_r_masked_intr___pa5___bit 5 -#define reg_gio_r_masked_intr___pa6___lsb 6 -#define reg_gio_r_masked_intr___pa6___width 1 -#define reg_gio_r_masked_intr___pa6___bit 6 -#define reg_gio_r_masked_intr___pa7___lsb 7 -#define reg_gio_r_masked_intr___pa7___width 1 -#define reg_gio_r_masked_intr___pa7___bit 7 -#define reg_gio_r_masked_intr_offset 28 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 18 -#define reg_gio_rw_pb_dout_offset 32 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 18 -#define reg_gio_r_pb_din_offset 36 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 18 -#define reg_gio_rw_pb_oe_offset 40 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 18 -#define reg_gio_rw_pc_dout_offset 48 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 18 -#define reg_gio_r_pc_din_offset 52 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 18 -#define reg_gio_rw_pc_oe_offset 56 - -/* Register rw_pd_dout, scope gio, type rw */ -#define reg_gio_rw_pd_dout___data___lsb 0 -#define reg_gio_rw_pd_dout___data___width 18 -#define reg_gio_rw_pd_dout_offset 64 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 18 -#define reg_gio_r_pd_din_offset 68 - -/* Register rw_pd_oe, scope gio, type rw */ -#define reg_gio_rw_pd_oe___oe___lsb 0 -#define reg_gio_rw_pd_oe___oe___width 18 -#define reg_gio_rw_pd_oe_offset 72 - -/* Register rw_pe_dout, scope gio, type rw */ -#define reg_gio_rw_pe_dout___data___lsb 0 -#define reg_gio_rw_pe_dout___data___width 18 -#define reg_gio_rw_pe_dout_offset 80 - -/* Register r_pe_din, scope gio, type r */ -#define reg_gio_r_pe_din___data___lsb 0 -#define reg_gio_r_pe_din___data___width 18 -#define reg_gio_r_pe_din_offset 84 - -/* Register rw_pe_oe, scope gio, type rw */ -#define reg_gio_rw_pe_oe___oe___lsb 0 -#define reg_gio_rw_pe_oe___oe___width 18 -#define reg_gio_rw_pe_oe_offset 88 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_hi 0x00000001 -#define regk_gio_lo 0x00000002 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_off 0x00000000 -#define regk_gio_posedge 0x00000005 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_pd_oe_default 0x00000000 -#define regk_gio_rw_pe_oe_default 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h deleted file mode 100644 index c8315905c571..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e - -#endif diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h deleted file mode 100644 index 6df2a433b02d..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h +++ /dev/null @@ -1,355 +0,0 @@ -#ifndef __intr_vect_defs_asm_h -#define __intr_vect_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp - * last modfied: Mon Apr 11 16:08:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mask, scope intr_vect, type rw */ -#define reg_intr_vect_rw_mask___memarb___lsb 0 -#define reg_intr_vect_rw_mask___memarb___width 1 -#define reg_intr_vect_rw_mask___memarb___bit 0 -#define reg_intr_vect_rw_mask___gen_io___lsb 1 -#define reg_intr_vect_rw_mask___gen_io___width 1 -#define reg_intr_vect_rw_mask___gen_io___bit 1 -#define reg_intr_vect_rw_mask___iop0___lsb 2 -#define reg_intr_vect_rw_mask___iop0___width 1 -#define reg_intr_vect_rw_mask___iop0___bit 2 -#define reg_intr_vect_rw_mask___iop1___lsb 3 -#define reg_intr_vect_rw_mask___iop1___width 1 -#define reg_intr_vect_rw_mask___iop1___bit 3 -#define reg_intr_vect_rw_mask___iop2___lsb 4 -#define reg_intr_vect_rw_mask___iop2___width 1 -#define reg_intr_vect_rw_mask___iop2___bit 4 -#define reg_intr_vect_rw_mask___iop3___lsb 5 -#define reg_intr_vect_rw_mask___iop3___width 1 -#define reg_intr_vect_rw_mask___iop3___bit 5 -#define reg_intr_vect_rw_mask___dma0___lsb 6 -#define reg_intr_vect_rw_mask___dma0___width 1 -#define reg_intr_vect_rw_mask___dma0___bit 6 -#define reg_intr_vect_rw_mask___dma1___lsb 7 -#define reg_intr_vect_rw_mask___dma1___width 1 -#define reg_intr_vect_rw_mask___dma1___bit 7 -#define reg_intr_vect_rw_mask___dma2___lsb 8 -#define reg_intr_vect_rw_mask___dma2___width 1 -#define reg_intr_vect_rw_mask___dma2___bit 8 -#define reg_intr_vect_rw_mask___dma3___lsb 9 -#define reg_intr_vect_rw_mask___dma3___width 1 -#define reg_intr_vect_rw_mask___dma3___bit 9 -#define reg_intr_vect_rw_mask___dma4___lsb 10 -#define reg_intr_vect_rw_mask___dma4___width 1 -#define reg_intr_vect_rw_mask___dma4___bit 10 -#define reg_intr_vect_rw_mask___dma5___lsb 11 -#define reg_intr_vect_rw_mask___dma5___width 1 -#define reg_intr_vect_rw_mask___dma5___bit 11 -#define reg_intr_vect_rw_mask___dma6___lsb 12 -#define reg_intr_vect_rw_mask___dma6___width 1 -#define reg_intr_vect_rw_mask___dma6___bit 12 -#define reg_intr_vect_rw_mask___dma7___lsb 13 -#define reg_intr_vect_rw_mask___dma7___width 1 -#define reg_intr_vect_rw_mask___dma7___bit 13 -#define reg_intr_vect_rw_mask___dma8___lsb 14 -#define reg_intr_vect_rw_mask___dma8___width 1 -#define reg_intr_vect_rw_mask___dma8___bit 14 -#define reg_intr_vect_rw_mask___dma9___lsb 15 -#define reg_intr_vect_rw_mask___dma9___width 1 -#define reg_intr_vect_rw_mask___dma9___bit 15 -#define reg_intr_vect_rw_mask___ata___lsb 16 -#define reg_intr_vect_rw_mask___ata___width 1 -#define reg_intr_vect_rw_mask___ata___bit 16 -#define reg_intr_vect_rw_mask___sser0___lsb 17 -#define reg_intr_vect_rw_mask___sser0___width 1 -#define reg_intr_vect_rw_mask___sser0___bit 17 -#define reg_intr_vect_rw_mask___sser1___lsb 18 -#define reg_intr_vect_rw_mask___sser1___width 1 -#define reg_intr_vect_rw_mask___sser1___bit 18 -#define reg_intr_vect_rw_mask___ser0___lsb 19 -#define reg_intr_vect_rw_mask___ser0___width 1 -#define reg_intr_vect_rw_mask___ser0___bit 19 -#define reg_intr_vect_rw_mask___ser1___lsb 20 -#define reg_intr_vect_rw_mask___ser1___width 1 -#define reg_intr_vect_rw_mask___ser1___bit 20 -#define reg_intr_vect_rw_mask___ser2___lsb 21 -#define reg_intr_vect_rw_mask___ser2___width 1 -#define reg_intr_vect_rw_mask___ser2___bit 21 -#define reg_intr_vect_rw_mask___ser3___lsb 22 -#define reg_intr_vect_rw_mask___ser3___width 1 -#define reg_intr_vect_rw_mask___ser3___bit 22 -#define reg_intr_vect_rw_mask___p21___lsb 23 -#define reg_intr_vect_rw_mask___p21___width 1 -#define reg_intr_vect_rw_mask___p21___bit 23 -#define reg_intr_vect_rw_mask___eth0___lsb 24 -#define reg_intr_vect_rw_mask___eth0___width 1 -#define reg_intr_vect_rw_mask___eth0___bit 24 -#define reg_intr_vect_rw_mask___eth1___lsb 25 -#define reg_intr_vect_rw_mask___eth1___width 1 -#define reg_intr_vect_rw_mask___eth1___bit 25 -#define reg_intr_vect_rw_mask___timer___lsb 26 -#define reg_intr_vect_rw_mask___timer___width 1 -#define reg_intr_vect_rw_mask___timer___bit 26 -#define reg_intr_vect_rw_mask___bif_arb___lsb 27 -#define reg_intr_vect_rw_mask___bif_arb___width 1 -#define reg_intr_vect_rw_mask___bif_arb___bit 27 -#define reg_intr_vect_rw_mask___bif_dma___lsb 28 -#define reg_intr_vect_rw_mask___bif_dma___width 1 -#define reg_intr_vect_rw_mask___bif_dma___bit 28 -#define reg_intr_vect_rw_mask___ext___lsb 29 -#define reg_intr_vect_rw_mask___ext___width 1 -#define reg_intr_vect_rw_mask___ext___bit 29 -#define reg_intr_vect_rw_mask_offset 0 - -/* Register r_vect, scope intr_vect, type r */ -#define reg_intr_vect_r_vect___memarb___lsb 0 -#define reg_intr_vect_r_vect___memarb___width 1 -#define reg_intr_vect_r_vect___memarb___bit 0 -#define reg_intr_vect_r_vect___gen_io___lsb 1 -#define reg_intr_vect_r_vect___gen_io___width 1 -#define reg_intr_vect_r_vect___gen_io___bit 1 -#define reg_intr_vect_r_vect___iop0___lsb 2 -#define reg_intr_vect_r_vect___iop0___width 1 -#define reg_intr_vect_r_vect___iop0___bit 2 -#define reg_intr_vect_r_vect___iop1___lsb 3 -#define reg_intr_vect_r_vect___iop1___width 1 -#define reg_intr_vect_r_vect___iop1___bit 3 -#define reg_intr_vect_r_vect___iop2___lsb 4 -#define reg_intr_vect_r_vect___iop2___width 1 -#define reg_intr_vect_r_vect___iop2___bit 4 -#define reg_intr_vect_r_vect___iop3___lsb 5 -#define reg_intr_vect_r_vect___iop3___width 1 -#define reg_intr_vect_r_vect___iop3___bit 5 -#define reg_intr_vect_r_vect___dma0___lsb 6 -#define reg_intr_vect_r_vect___dma0___width 1 -#define reg_intr_vect_r_vect___dma0___bit 6 -#define reg_intr_vect_r_vect___dma1___lsb 7 -#define reg_intr_vect_r_vect___dma1___width 1 -#define reg_intr_vect_r_vect___dma1___bit 7 -#define reg_intr_vect_r_vect___dma2___lsb 8 -#define reg_intr_vect_r_vect___dma2___width 1 -#define reg_intr_vect_r_vect___dma2___bit 8 -#define reg_intr_vect_r_vect___dma3___lsb 9 -#define reg_intr_vect_r_vect___dma3___width 1 -#define reg_intr_vect_r_vect___dma3___bit 9 -#define reg_intr_vect_r_vect___dma4___lsb 10 -#define reg_intr_vect_r_vect___dma4___width 1 -#define reg_intr_vect_r_vect___dma4___bit 10 -#define reg_intr_vect_r_vect___dma5___lsb 11 -#define reg_intr_vect_r_vect___dma5___width 1 -#define reg_intr_vect_r_vect___dma5___bit 11 -#define reg_intr_vect_r_vect___dma6___lsb 12 -#define reg_intr_vect_r_vect___dma6___width 1 -#define reg_intr_vect_r_vect___dma6___bit 12 -#define reg_intr_vect_r_vect___dma7___lsb 13 -#define reg_intr_vect_r_vect___dma7___width 1 -#define reg_intr_vect_r_vect___dma7___bit 13 -#define reg_intr_vect_r_vect___dma8___lsb 14 -#define reg_intr_vect_r_vect___dma8___width 1 -#define reg_intr_vect_r_vect___dma8___bit 14 -#define reg_intr_vect_r_vect___dma9___lsb 15 -#define reg_intr_vect_r_vect___dma9___width 1 -#define reg_intr_vect_r_vect___dma9___bit 15 -#define reg_intr_vect_r_vect___ata___lsb 16 -#define reg_intr_vect_r_vect___ata___width 1 -#define reg_intr_vect_r_vect___ata___bit 16 -#define reg_intr_vect_r_vect___sser0___lsb 17 -#define reg_intr_vect_r_vect___sser0___width 1 -#define reg_intr_vect_r_vect___sser0___bit 17 -#define reg_intr_vect_r_vect___sser1___lsb 18 -#define reg_intr_vect_r_vect___sser1___width 1 -#define reg_intr_vect_r_vect___sser1___bit 18 -#define reg_intr_vect_r_vect___ser0___lsb 19 -#define reg_intr_vect_r_vect___ser0___width 1 -#define reg_intr_vect_r_vect___ser0___bit 19 -#define reg_intr_vect_r_vect___ser1___lsb 20 -#define reg_intr_vect_r_vect___ser1___width 1 -#define reg_intr_vect_r_vect___ser1___bit 20 -#define reg_intr_vect_r_vect___ser2___lsb 21 -#define reg_intr_vect_r_vect___ser2___width 1 -#define reg_intr_vect_r_vect___ser2___bit 21 -#define reg_intr_vect_r_vect___ser3___lsb 22 -#define reg_intr_vect_r_vect___ser3___width 1 -#define reg_intr_vect_r_vect___ser3___bit 22 -#define reg_intr_vect_r_vect___p21___lsb 23 -#define reg_intr_vect_r_vect___p21___width 1 -#define reg_intr_vect_r_vect___p21___bit 23 -#define reg_intr_vect_r_vect___eth0___lsb 24 -#define reg_intr_vect_r_vect___eth0___width 1 -#define reg_intr_vect_r_vect___eth0___bit 24 -#define reg_intr_vect_r_vect___eth1___lsb 25 -#define reg_intr_vect_r_vect___eth1___width 1 -#define reg_intr_vect_r_vect___eth1___bit 25 -#define reg_intr_vect_r_vect___timer___lsb 26 -#define reg_intr_vect_r_vect___timer___width 1 -#define reg_intr_vect_r_vect___timer___bit 26 -#define reg_intr_vect_r_vect___bif_arb___lsb 27 -#define reg_intr_vect_r_vect___bif_arb___width 1 -#define reg_intr_vect_r_vect___bif_arb___bit 27 -#define reg_intr_vect_r_vect___bif_dma___lsb 28 -#define reg_intr_vect_r_vect___bif_dma___width 1 -#define reg_intr_vect_r_vect___bif_dma___bit 28 -#define reg_intr_vect_r_vect___ext___lsb 29 -#define reg_intr_vect_r_vect___ext___width 1 -#define reg_intr_vect_r_vect___ext___bit 29 -#define reg_intr_vect_r_vect_offset 4 - -/* Register r_masked_vect, scope intr_vect, type r */ -#define reg_intr_vect_r_masked_vect___memarb___lsb 0 -#define reg_intr_vect_r_masked_vect___memarb___width 1 -#define reg_intr_vect_r_masked_vect___memarb___bit 0 -#define reg_intr_vect_r_masked_vect___gen_io___lsb 1 -#define reg_intr_vect_r_masked_vect___gen_io___width 1 -#define reg_intr_vect_r_masked_vect___gen_io___bit 1 -#define reg_intr_vect_r_masked_vect___iop0___lsb 2 -#define reg_intr_vect_r_masked_vect___iop0___width 1 -#define reg_intr_vect_r_masked_vect___iop0___bit 2 -#define reg_intr_vect_r_masked_vect___iop1___lsb 3 -#define reg_intr_vect_r_masked_vect___iop1___width 1 -#define reg_intr_vect_r_masked_vect___iop1___bit 3 -#define reg_intr_vect_r_masked_vect___iop2___lsb 4 -#define reg_intr_vect_r_masked_vect___iop2___width 1 -#define reg_intr_vect_r_masked_vect___iop2___bit 4 -#define reg_intr_vect_r_masked_vect___iop3___lsb 5 -#define reg_intr_vect_r_masked_vect___iop3___width 1 -#define reg_intr_vect_r_masked_vect___iop3___bit 5 -#define reg_intr_vect_r_masked_vect___dma0___lsb 6 -#define reg_intr_vect_r_masked_vect___dma0___width 1 -#define reg_intr_vect_r_masked_vect___dma0___bit 6 -#define reg_intr_vect_r_masked_vect___dma1___lsb 7 -#define reg_intr_vect_r_masked_vect___dma1___width 1 -#define reg_intr_vect_r_masked_vect___dma1___bit 7 -#define reg_intr_vect_r_masked_vect___dma2___lsb 8 -#define reg_intr_vect_r_masked_vect___dma2___width 1 -#define reg_intr_vect_r_masked_vect___dma2___bit 8 -#define reg_intr_vect_r_masked_vect___dma3___lsb 9 -#define reg_intr_vect_r_masked_vect___dma3___width 1 -#define reg_intr_vect_r_masked_vect___dma3___bit 9 -#define reg_intr_vect_r_masked_vect___dma4___lsb 10 -#define reg_intr_vect_r_masked_vect___dma4___width 1 -#define reg_intr_vect_r_masked_vect___dma4___bit 10 -#define reg_intr_vect_r_masked_vect___dma5___lsb 11 -#define reg_intr_vect_r_masked_vect___dma5___width 1 -#define reg_intr_vect_r_masked_vect___dma5___bit 11 -#define reg_intr_vect_r_masked_vect___dma6___lsb 12 -#define reg_intr_vect_r_masked_vect___dma6___width 1 -#define reg_intr_vect_r_masked_vect___dma6___bit 12 -#define reg_intr_vect_r_masked_vect___dma7___lsb 13 -#define reg_intr_vect_r_masked_vect___dma7___width 1 -#define reg_intr_vect_r_masked_vect___dma7___bit 13 -#define reg_intr_vect_r_masked_vect___dma8___lsb 14 -#define reg_intr_vect_r_masked_vect___dma8___width 1 -#define reg_intr_vect_r_masked_vect___dma8___bit 14 -#define reg_intr_vect_r_masked_vect___dma9___lsb 15 -#define reg_intr_vect_r_masked_vect___dma9___width 1 -#define reg_intr_vect_r_masked_vect___dma9___bit 15 -#define reg_intr_vect_r_masked_vect___ata___lsb 16 -#define reg_intr_vect_r_masked_vect___ata___width 1 -#define reg_intr_vect_r_masked_vect___ata___bit 16 -#define reg_intr_vect_r_masked_vect___sser0___lsb 17 -#define reg_intr_vect_r_masked_vect___sser0___width 1 -#define reg_intr_vect_r_masked_vect___sser0___bit 17 -#define reg_intr_vect_r_masked_vect___sser1___lsb 18 -#define reg_intr_vect_r_masked_vect___sser1___width 1 -#define reg_intr_vect_r_masked_vect___sser1___bit 18 -#define reg_intr_vect_r_masked_vect___ser0___lsb 19 -#define reg_intr_vect_r_masked_vect___ser0___width 1 -#define reg_intr_vect_r_masked_vect___ser0___bit 19 -#define reg_intr_vect_r_masked_vect___ser1___lsb 20 -#define reg_intr_vect_r_masked_vect___ser1___width 1 -#define reg_intr_vect_r_masked_vect___ser1___bit 20 -#define reg_intr_vect_r_masked_vect___ser2___lsb 21 -#define reg_intr_vect_r_masked_vect___ser2___width 1 -#define reg_intr_vect_r_masked_vect___ser2___bit 21 -#define reg_intr_vect_r_masked_vect___ser3___lsb 22 -#define reg_intr_vect_r_masked_vect___ser3___width 1 -#define reg_intr_vect_r_masked_vect___ser3___bit 22 -#define reg_intr_vect_r_masked_vect___p21___lsb 23 -#define reg_intr_vect_r_masked_vect___p21___width 1 -#define reg_intr_vect_r_masked_vect___p21___bit 23 -#define reg_intr_vect_r_masked_vect___eth0___lsb 24 -#define reg_intr_vect_r_masked_vect___eth0___width 1 -#define reg_intr_vect_r_masked_vect___eth0___bit 24 -#define reg_intr_vect_r_masked_vect___eth1___lsb 25 -#define reg_intr_vect_r_masked_vect___eth1___width 1 -#define reg_intr_vect_r_masked_vect___eth1___bit 25 -#define reg_intr_vect_r_masked_vect___timer___lsb 26 -#define reg_intr_vect_r_masked_vect___timer___width 1 -#define reg_intr_vect_r_masked_vect___timer___bit 26 -#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 -#define reg_intr_vect_r_masked_vect___bif_arb___width 1 -#define reg_intr_vect_r_masked_vect___bif_arb___bit 27 -#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 -#define reg_intr_vect_r_masked_vect___bif_dma___width 1 -#define reg_intr_vect_r_masked_vect___bif_dma___bit 28 -#define reg_intr_vect_r_masked_vect___ext___lsb 29 -#define reg_intr_vect_r_masked_vect___ext___width 1 -#define reg_intr_vect_r_masked_vect___ext___bit 29 -#define reg_intr_vect_r_masked_vect_offset 8 - -/* Register r_nmi, scope intr_vect, type r */ -#define reg_intr_vect_r_nmi___ext___lsb 0 -#define reg_intr_vect_r_nmi___ext___width 1 -#define reg_intr_vect_r_nmi___ext___bit 0 -#define reg_intr_vect_r_nmi___watchdog___lsb 1 -#define reg_intr_vect_r_nmi___watchdog___width 1 -#define reg_intr_vect_r_nmi___watchdog___bit 1 -#define reg_intr_vect_r_nmi_offset 12 - -/* Register r_guru, scope intr_vect, type r */ -#define reg_intr_vect_r_guru___jtag___lsb 0 -#define reg_intr_vect_r_guru___jtag___width 1 -#define reg_intr_vect_r_guru___jtag___bit 0 -#define reg_intr_vect_r_guru_offset 16 - - -/* Constants */ -#define regk_intr_vect_off 0x00000000 -#define regk_intr_vect_on 0x00000001 -#define regk_intr_vect_rw_mask_default 0x00000000 -#endif /* __intr_vect_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h deleted file mode 100644 index 0c8084054840..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef __irq_nmi_defs_asm_h -#define __irq_nmi_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../mod/irq_nmi.r - * id: - * last modfied: Thu Jan 22 09:22:43 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r - * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cmd, scope irq_nmi, type rw */ -#define reg_irq_nmi_rw_cmd___delay___lsb 0 -#define reg_irq_nmi_rw_cmd___delay___width 16 -#define reg_irq_nmi_rw_cmd___op___lsb 16 -#define reg_irq_nmi_rw_cmd___op___width 2 -#define reg_irq_nmi_rw_cmd_offset 0 - - -/* Constants */ -#define regk_irq_nmi_ack_irq 0x00000002 -#define regk_irq_nmi_ack_nmi 0x00000003 -#define regk_irq_nmi_irq 0x00000000 -#define regk_irq_nmi_nmi 0x00000001 -#endif /* __irq_nmi_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h deleted file mode 100644 index 45400eb8d389..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h +++ /dev/null @@ -1,579 +0,0 @@ -#ifndef __marb_defs_asm_h -#define __marb_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -#define reg_marb_rw_int_slots___owner___lsb 0 -#define reg_marb_rw_int_slots___owner___width 4 -#define reg_marb_rw_int_slots_offset 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -#define reg_marb_rw_ext_slots___owner___lsb 0 -#define reg_marb_rw_ext_slots___owner___width 4 -#define reg_marb_rw_ext_slots_offset 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -#define reg_marb_rw_regs_slots___owner___lsb 0 -#define reg_marb_rw_regs_slots___owner___width 4 -#define reg_marb_rw_regs_slots_offset 512 - -/* Register rw_intr_mask, scope marb, type rw */ -#define reg_marb_rw_intr_mask___bp0___lsb 0 -#define reg_marb_rw_intr_mask___bp0___width 1 -#define reg_marb_rw_intr_mask___bp0___bit 0 -#define reg_marb_rw_intr_mask___bp1___lsb 1 -#define reg_marb_rw_intr_mask___bp1___width 1 -#define reg_marb_rw_intr_mask___bp1___bit 1 -#define reg_marb_rw_intr_mask___bp2___lsb 2 -#define reg_marb_rw_intr_mask___bp2___width 1 -#define reg_marb_rw_intr_mask___bp2___bit 2 -#define reg_marb_rw_intr_mask___bp3___lsb 3 -#define reg_marb_rw_intr_mask___bp3___width 1 -#define reg_marb_rw_intr_mask___bp3___bit 3 -#define reg_marb_rw_intr_mask_offset 528 - -/* Register rw_ack_intr, scope marb, type rw */ -#define reg_marb_rw_ack_intr___bp0___lsb 0 -#define reg_marb_rw_ack_intr___bp0___width 1 -#define reg_marb_rw_ack_intr___bp0___bit 0 -#define reg_marb_rw_ack_intr___bp1___lsb 1 -#define reg_marb_rw_ack_intr___bp1___width 1 -#define reg_marb_rw_ack_intr___bp1___bit 1 -#define reg_marb_rw_ack_intr___bp2___lsb 2 -#define reg_marb_rw_ack_intr___bp2___width 1 -#define reg_marb_rw_ack_intr___bp2___bit 2 -#define reg_marb_rw_ack_intr___bp3___lsb 3 -#define reg_marb_rw_ack_intr___bp3___width 1 -#define reg_marb_rw_ack_intr___bp3___bit 3 -#define reg_marb_rw_ack_intr_offset 532 - -/* Register r_intr, scope marb, type r */ -#define reg_marb_r_intr___bp0___lsb 0 -#define reg_marb_r_intr___bp0___width 1 -#define reg_marb_r_intr___bp0___bit 0 -#define reg_marb_r_intr___bp1___lsb 1 -#define reg_marb_r_intr___bp1___width 1 -#define reg_marb_r_intr___bp1___bit 1 -#define reg_marb_r_intr___bp2___lsb 2 -#define reg_marb_r_intr___bp2___width 1 -#define reg_marb_r_intr___bp2___bit 2 -#define reg_marb_r_intr___bp3___lsb 3 -#define reg_marb_r_intr___bp3___width 1 -#define reg_marb_r_intr___bp3___bit 3 -#define reg_marb_r_intr_offset 536 - -/* Register r_masked_intr, scope marb, type r */ -#define reg_marb_r_masked_intr___bp0___lsb 0 -#define reg_marb_r_masked_intr___bp0___width 1 -#define reg_marb_r_masked_intr___bp0___bit 0 -#define reg_marb_r_masked_intr___bp1___lsb 1 -#define reg_marb_r_masked_intr___bp1___width 1 -#define reg_marb_r_masked_intr___bp1___bit 1 -#define reg_marb_r_masked_intr___bp2___lsb 2 -#define reg_marb_r_masked_intr___bp2___width 1 -#define reg_marb_r_masked_intr___bp2___bit 2 -#define reg_marb_r_masked_intr___bp3___lsb 3 -#define reg_marb_r_masked_intr___bp3___width 1 -#define reg_marb_r_masked_intr___bp3___bit 3 -#define reg_marb_r_masked_intr_offset 540 - -/* Register rw_stop_mask, scope marb, type rw */ -#define reg_marb_rw_stop_mask___dma0___lsb 0 -#define reg_marb_rw_stop_mask___dma0___width 1 -#define reg_marb_rw_stop_mask___dma0___bit 0 -#define reg_marb_rw_stop_mask___dma1___lsb 1 -#define reg_marb_rw_stop_mask___dma1___width 1 -#define reg_marb_rw_stop_mask___dma1___bit 1 -#define reg_marb_rw_stop_mask___dma2___lsb 2 -#define reg_marb_rw_stop_mask___dma2___width 1 -#define reg_marb_rw_stop_mask___dma2___bit 2 -#define reg_marb_rw_stop_mask___dma3___lsb 3 -#define reg_marb_rw_stop_mask___dma3___width 1 -#define reg_marb_rw_stop_mask___dma3___bit 3 -#define reg_marb_rw_stop_mask___dma4___lsb 4 -#define reg_marb_rw_stop_mask___dma4___width 1 -#define reg_marb_rw_stop_mask___dma4___bit 4 -#define reg_marb_rw_stop_mask___dma5___lsb 5 -#define reg_marb_rw_stop_mask___dma5___width 1 -#define reg_marb_rw_stop_mask___dma5___bit 5 -#define reg_marb_rw_stop_mask___dma6___lsb 6 -#define reg_marb_rw_stop_mask___dma6___width 1 -#define reg_marb_rw_stop_mask___dma6___bit 6 -#define reg_marb_rw_stop_mask___dma7___lsb 7 -#define reg_marb_rw_stop_mask___dma7___width 1 -#define reg_marb_rw_stop_mask___dma7___bit 7 -#define reg_marb_rw_stop_mask___dma8___lsb 8 -#define reg_marb_rw_stop_mask___dma8___width 1 -#define reg_marb_rw_stop_mask___dma8___bit 8 -#define reg_marb_rw_stop_mask___dma9___lsb 9 -#define reg_marb_rw_stop_mask___dma9___width 1 -#define reg_marb_rw_stop_mask___dma9___bit 9 -#define reg_marb_rw_stop_mask___cpui___lsb 10 -#define reg_marb_rw_stop_mask___cpui___width 1 -#define reg_marb_rw_stop_mask___cpui___bit 10 -#define reg_marb_rw_stop_mask___cpud___lsb 11 -#define reg_marb_rw_stop_mask___cpud___width 1 -#define reg_marb_rw_stop_mask___cpud___bit 11 -#define reg_marb_rw_stop_mask___iop___lsb 12 -#define reg_marb_rw_stop_mask___iop___width 1 -#define reg_marb_rw_stop_mask___iop___bit 12 -#define reg_marb_rw_stop_mask___slave___lsb 13 -#define reg_marb_rw_stop_mask___slave___width 1 -#define reg_marb_rw_stop_mask___slave___bit 13 -#define reg_marb_rw_stop_mask_offset 544 - -/* Register r_stopped, scope marb, type r */ -#define reg_marb_r_stopped___dma0___lsb 0 -#define reg_marb_r_stopped___dma0___width 1 -#define reg_marb_r_stopped___dma0___bit 0 -#define reg_marb_r_stopped___dma1___lsb 1 -#define reg_marb_r_stopped___dma1___width 1 -#define reg_marb_r_stopped___dma1___bit 1 -#define reg_marb_r_stopped___dma2___lsb 2 -#define reg_marb_r_stopped___dma2___width 1 -#define reg_marb_r_stopped___dma2___bit 2 -#define reg_marb_r_stopped___dma3___lsb 3 -#define reg_marb_r_stopped___dma3___width 1 -#define reg_marb_r_stopped___dma3___bit 3 -#define reg_marb_r_stopped___dma4___lsb 4 -#define reg_marb_r_stopped___dma4___width 1 -#define reg_marb_r_stopped___dma4___bit 4 -#define reg_marb_r_stopped___dma5___lsb 5 -#define reg_marb_r_stopped___dma5___width 1 -#define reg_marb_r_stopped___dma5___bit 5 -#define reg_marb_r_stopped___dma6___lsb 6 -#define reg_marb_r_stopped___dma6___width 1 -#define reg_marb_r_stopped___dma6___bit 6 -#define reg_marb_r_stopped___dma7___lsb 7 -#define reg_marb_r_stopped___dma7___width 1 -#define reg_marb_r_stopped___dma7___bit 7 -#define reg_marb_r_stopped___dma8___lsb 8 -#define reg_marb_r_stopped___dma8___width 1 -#define reg_marb_r_stopped___dma8___bit 8 -#define reg_marb_r_stopped___dma9___lsb 9 -#define reg_marb_r_stopped___dma9___width 1 -#define reg_marb_r_stopped___dma9___bit 9 -#define reg_marb_r_stopped___cpui___lsb 10 -#define reg_marb_r_stopped___cpui___width 1 -#define reg_marb_r_stopped___cpui___bit 10 -#define reg_marb_r_stopped___cpud___lsb 11 -#define reg_marb_r_stopped___cpud___width 1 -#define reg_marb_r_stopped___cpud___bit 11 -#define reg_marb_r_stopped___iop___lsb 12 -#define reg_marb_r_stopped___iop___width 1 -#define reg_marb_r_stopped___iop___bit 12 -#define reg_marb_r_stopped___slave___lsb 13 -#define reg_marb_r_stopped___slave___width 1 -#define reg_marb_r_stopped___slave___bit 13 -#define reg_marb_r_stopped_offset 548 - -/* Register rw_no_snoop, scope marb, type rw */ -#define reg_marb_rw_no_snoop___dma0___lsb 0 -#define reg_marb_rw_no_snoop___dma0___width 1 -#define reg_marb_rw_no_snoop___dma0___bit 0 -#define reg_marb_rw_no_snoop___dma1___lsb 1 -#define reg_marb_rw_no_snoop___dma1___width 1 -#define reg_marb_rw_no_snoop___dma1___bit 1 -#define reg_marb_rw_no_snoop___dma2___lsb 2 -#define reg_marb_rw_no_snoop___dma2___width 1 -#define reg_marb_rw_no_snoop___dma2___bit 2 -#define reg_marb_rw_no_snoop___dma3___lsb 3 -#define reg_marb_rw_no_snoop___dma3___width 1 -#define reg_marb_rw_no_snoop___dma3___bit 3 -#define reg_marb_rw_no_snoop___dma4___lsb 4 -#define reg_marb_rw_no_snoop___dma4___width 1 -#define reg_marb_rw_no_snoop___dma4___bit 4 -#define reg_marb_rw_no_snoop___dma5___lsb 5 -#define reg_marb_rw_no_snoop___dma5___width 1 -#define reg_marb_rw_no_snoop___dma5___bit 5 -#define reg_marb_rw_no_snoop___dma6___lsb 6 -#define reg_marb_rw_no_snoop___dma6___width 1 -#define reg_marb_rw_no_snoop___dma6___bit 6 -#define reg_marb_rw_no_snoop___dma7___lsb 7 -#define reg_marb_rw_no_snoop___dma7___width 1 -#define reg_marb_rw_no_snoop___dma7___bit 7 -#define reg_marb_rw_no_snoop___dma8___lsb 8 -#define reg_marb_rw_no_snoop___dma8___width 1 -#define reg_marb_rw_no_snoop___dma8___bit 8 -#define reg_marb_rw_no_snoop___dma9___lsb 9 -#define reg_marb_rw_no_snoop___dma9___width 1 -#define reg_marb_rw_no_snoop___dma9___bit 9 -#define reg_marb_rw_no_snoop___cpui___lsb 10 -#define reg_marb_rw_no_snoop___cpui___width 1 -#define reg_marb_rw_no_snoop___cpui___bit 10 -#define reg_marb_rw_no_snoop___cpud___lsb 11 -#define reg_marb_rw_no_snoop___cpud___width 1 -#define reg_marb_rw_no_snoop___cpud___bit 11 -#define reg_marb_rw_no_snoop___iop___lsb 12 -#define reg_marb_rw_no_snoop___iop___width 1 -#define reg_marb_rw_no_snoop___iop___bit 12 -#define reg_marb_rw_no_snoop___slave___lsb 13 -#define reg_marb_rw_no_snoop___slave___width 1 -#define reg_marb_rw_no_snoop___slave___bit 13 -#define reg_marb_rw_no_snoop_offset 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -#define reg_marb_rw_no_snoop_rq___cpui___lsb 10 -#define reg_marb_rw_no_snoop_rq___cpui___width 1 -#define reg_marb_rw_no_snoop_rq___cpui___bit 10 -#define reg_marb_rw_no_snoop_rq___cpud___lsb 11 -#define reg_marb_rw_no_snoop_rq___cpud___width 1 -#define reg_marb_rw_no_snoop_rq___cpud___bit 11 -#define reg_marb_rw_no_snoop_rq_offset 836 - - -/* Constants */ -#define regk_marb_cpud 0x0000000b -#define regk_marb_cpui 0x0000000a -#define regk_marb_dma0 0x00000000 -#define regk_marb_dma1 0x00000001 -#define regk_marb_dma2 0x00000002 -#define regk_marb_dma3 0x00000003 -#define regk_marb_dma4 0x00000004 -#define regk_marb_dma5 0x00000005 -#define regk_marb_dma6 0x00000006 -#define regk_marb_dma7 0x00000007 -#define regk_marb_dma8 0x00000008 -#define regk_marb_dma9 0x00000009 -#define regk_marb_iop 0x0000000c -#define regk_marb_no 0x00000000 -#define regk_marb_r_stopped_default 0x00000000 -#define regk_marb_rw_ext_slots_default 0x00000000 -#define regk_marb_rw_ext_slots_size 0x00000040 -#define regk_marb_rw_int_slots_default 0x00000000 -#define regk_marb_rw_int_slots_size 0x00000040 -#define regk_marb_rw_intr_mask_default 0x00000000 -#define regk_marb_rw_no_snoop_default 0x00000000 -#define regk_marb_rw_no_snoop_rq_default 0x00000000 -#define regk_marb_rw_regs_slots_default 0x00000000 -#define regk_marb_rw_regs_slots_size 0x00000004 -#define regk_marb_rw_stop_mask_default 0x00000000 -#define regk_marb_slave 0x0000000d -#define regk_marb_yes 0x00000001 -#endif /* __marb_defs_asm_h */ -#ifndef __marb_bp_defs_asm_h -#define __marb_bp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_first_addr, scope marb_bp, type rw */ -#define reg_marb_bp_rw_first_addr_offset 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -#define reg_marb_bp_rw_last_addr_offset 4 - -/* Register rw_op, scope marb_bp, type rw */ -#define reg_marb_bp_rw_op___rd___lsb 0 -#define reg_marb_bp_rw_op___rd___width 1 -#define reg_marb_bp_rw_op___rd___bit 0 -#define reg_marb_bp_rw_op___wr___lsb 1 -#define reg_marb_bp_rw_op___wr___width 1 -#define reg_marb_bp_rw_op___wr___bit 1 -#define reg_marb_bp_rw_op___rd_excl___lsb 2 -#define reg_marb_bp_rw_op___rd_excl___width 1 -#define reg_marb_bp_rw_op___rd_excl___bit 2 -#define reg_marb_bp_rw_op___pri_wr___lsb 3 -#define reg_marb_bp_rw_op___pri_wr___width 1 -#define reg_marb_bp_rw_op___pri_wr___bit 3 -#define reg_marb_bp_rw_op___us_rd___lsb 4 -#define reg_marb_bp_rw_op___us_rd___width 1 -#define reg_marb_bp_rw_op___us_rd___bit 4 -#define reg_marb_bp_rw_op___us_wr___lsb 5 -#define reg_marb_bp_rw_op___us_wr___width 1 -#define reg_marb_bp_rw_op___us_wr___bit 5 -#define reg_marb_bp_rw_op___us_rd_excl___lsb 6 -#define reg_marb_bp_rw_op___us_rd_excl___width 1 -#define reg_marb_bp_rw_op___us_rd_excl___bit 6 -#define reg_marb_bp_rw_op___us_pri_wr___lsb 7 -#define reg_marb_bp_rw_op___us_pri_wr___width 1 -#define reg_marb_bp_rw_op___us_pri_wr___bit 7 -#define reg_marb_bp_rw_op_offset 8 - -/* Register rw_clients, scope marb_bp, type rw */ -#define reg_marb_bp_rw_clients___dma0___lsb 0 -#define reg_marb_bp_rw_clients___dma0___width 1 -#define reg_marb_bp_rw_clients___dma0___bit 0 -#define reg_marb_bp_rw_clients___dma1___lsb 1 -#define reg_marb_bp_rw_clients___dma1___width 1 -#define reg_marb_bp_rw_clients___dma1___bit 1 -#define reg_marb_bp_rw_clients___dma2___lsb 2 -#define reg_marb_bp_rw_clients___dma2___width 1 -#define reg_marb_bp_rw_clients___dma2___bit 2 -#define reg_marb_bp_rw_clients___dma3___lsb 3 -#define reg_marb_bp_rw_clients___dma3___width 1 -#define reg_marb_bp_rw_clients___dma3___bit 3 -#define reg_marb_bp_rw_clients___dma4___lsb 4 -#define reg_marb_bp_rw_clients___dma4___width 1 -#define reg_marb_bp_rw_clients___dma4___bit 4 -#define reg_marb_bp_rw_clients___dma5___lsb 5 -#define reg_marb_bp_rw_clients___dma5___width 1 -#define reg_marb_bp_rw_clients___dma5___bit 5 -#define reg_marb_bp_rw_clients___dma6___lsb 6 -#define reg_marb_bp_rw_clients___dma6___width 1 -#define reg_marb_bp_rw_clients___dma6___bit 6 -#define reg_marb_bp_rw_clients___dma7___lsb 7 -#define reg_marb_bp_rw_clients___dma7___width 1 -#define reg_marb_bp_rw_clients___dma7___bit 7 -#define reg_marb_bp_rw_clients___dma8___lsb 8 -#define reg_marb_bp_rw_clients___dma8___width 1 -#define reg_marb_bp_rw_clients___dma8___bit 8 -#define reg_marb_bp_rw_clients___dma9___lsb 9 -#define reg_marb_bp_rw_clients___dma9___width 1 -#define reg_marb_bp_rw_clients___dma9___bit 9 -#define reg_marb_bp_rw_clients___cpui___lsb 10 -#define reg_marb_bp_rw_clients___cpui___width 1 -#define reg_marb_bp_rw_clients___cpui___bit 10 -#define reg_marb_bp_rw_clients___cpud___lsb 11 -#define reg_marb_bp_rw_clients___cpud___width 1 -#define reg_marb_bp_rw_clients___cpud___bit 11 -#define reg_marb_bp_rw_clients___iop___lsb 12 -#define reg_marb_bp_rw_clients___iop___width 1 -#define reg_marb_bp_rw_clients___iop___bit 12 -#define reg_marb_bp_rw_clients___slave___lsb 13 -#define reg_marb_bp_rw_clients___slave___width 1 -#define reg_marb_bp_rw_clients___slave___bit 13 -#define reg_marb_bp_rw_clients_offset 12 - -/* Register rw_options, scope marb_bp, type rw */ -#define reg_marb_bp_rw_options___wrap___lsb 0 -#define reg_marb_bp_rw_options___wrap___width 1 -#define reg_marb_bp_rw_options___wrap___bit 0 -#define reg_marb_bp_rw_options_offset 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_addr_offset 20 - -/* Register r_brk_op, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_op___rd___lsb 0 -#define reg_marb_bp_r_brk_op___rd___width 1 -#define reg_marb_bp_r_brk_op___rd___bit 0 -#define reg_marb_bp_r_brk_op___wr___lsb 1 -#define reg_marb_bp_r_brk_op___wr___width 1 -#define reg_marb_bp_r_brk_op___wr___bit 1 -#define reg_marb_bp_r_brk_op___rd_excl___lsb 2 -#define reg_marb_bp_r_brk_op___rd_excl___width 1 -#define reg_marb_bp_r_brk_op___rd_excl___bit 2 -#define reg_marb_bp_r_brk_op___pri_wr___lsb 3 -#define reg_marb_bp_r_brk_op___pri_wr___width 1 -#define reg_marb_bp_r_brk_op___pri_wr___bit 3 -#define reg_marb_bp_r_brk_op___us_rd___lsb 4 -#define reg_marb_bp_r_brk_op___us_rd___width 1 -#define reg_marb_bp_r_brk_op___us_rd___bit 4 -#define reg_marb_bp_r_brk_op___us_wr___lsb 5 -#define reg_marb_bp_r_brk_op___us_wr___width 1 -#define reg_marb_bp_r_brk_op___us_wr___bit 5 -#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6 -#define reg_marb_bp_r_brk_op___us_rd_excl___width 1 -#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6 -#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7 -#define reg_marb_bp_r_brk_op___us_pri_wr___width 1 -#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7 -#define reg_marb_bp_r_brk_op_offset 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_clients___dma0___lsb 0 -#define reg_marb_bp_r_brk_clients___dma0___width 1 -#define reg_marb_bp_r_brk_clients___dma0___bit 0 -#define reg_marb_bp_r_brk_clients___dma1___lsb 1 -#define reg_marb_bp_r_brk_clients___dma1___width 1 -#define reg_marb_bp_r_brk_clients___dma1___bit 1 -#define reg_marb_bp_r_brk_clients___dma2___lsb 2 -#define reg_marb_bp_r_brk_clients___dma2___width 1 -#define reg_marb_bp_r_brk_clients___dma2___bit 2 -#define reg_marb_bp_r_brk_clients___dma3___lsb 3 -#define reg_marb_bp_r_brk_clients___dma3___width 1 -#define reg_marb_bp_r_brk_clients___dma3___bit 3 -#define reg_marb_bp_r_brk_clients___dma4___lsb 4 -#define reg_marb_bp_r_brk_clients___dma4___width 1 -#define reg_marb_bp_r_brk_clients___dma4___bit 4 -#define reg_marb_bp_r_brk_clients___dma5___lsb 5 -#define reg_marb_bp_r_brk_clients___dma5___width 1 -#define reg_marb_bp_r_brk_clients___dma5___bit 5 -#define reg_marb_bp_r_brk_clients___dma6___lsb 6 -#define reg_marb_bp_r_brk_clients___dma6___width 1 -#define reg_marb_bp_r_brk_clients___dma6___bit 6 -#define reg_marb_bp_r_brk_clients___dma7___lsb 7 -#define reg_marb_bp_r_brk_clients___dma7___width 1 -#define reg_marb_bp_r_brk_clients___dma7___bit 7 -#define reg_marb_bp_r_brk_clients___dma8___lsb 8 -#define reg_marb_bp_r_brk_clients___dma8___width 1 -#define reg_marb_bp_r_brk_clients___dma8___bit 8 -#define reg_marb_bp_r_brk_clients___dma9___lsb 9 -#define reg_marb_bp_r_brk_clients___dma9___width 1 -#define reg_marb_bp_r_brk_clients___dma9___bit 9 -#define reg_marb_bp_r_brk_clients___cpui___lsb 10 -#define reg_marb_bp_r_brk_clients___cpui___width 1 -#define reg_marb_bp_r_brk_clients___cpui___bit 10 -#define reg_marb_bp_r_brk_clients___cpud___lsb 11 -#define reg_marb_bp_r_brk_clients___cpud___width 1 -#define reg_marb_bp_r_brk_clients___cpud___bit 11 -#define reg_marb_bp_r_brk_clients___iop___lsb 12 -#define reg_marb_bp_r_brk_clients___iop___width 1 -#define reg_marb_bp_r_brk_clients___iop___bit 12 -#define reg_marb_bp_r_brk_clients___slave___lsb 13 -#define reg_marb_bp_r_brk_clients___slave___width 1 -#define reg_marb_bp_r_brk_clients___slave___bit 13 -#define reg_marb_bp_r_brk_clients_offset 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_first_client___dma0___lsb 0 -#define reg_marb_bp_r_brk_first_client___dma0___width 1 -#define reg_marb_bp_r_brk_first_client___dma0___bit 0 -#define reg_marb_bp_r_brk_first_client___dma1___lsb 1 -#define reg_marb_bp_r_brk_first_client___dma1___width 1 -#define reg_marb_bp_r_brk_first_client___dma1___bit 1 -#define reg_marb_bp_r_brk_first_client___dma2___lsb 2 -#define reg_marb_bp_r_brk_first_client___dma2___width 1 -#define reg_marb_bp_r_brk_first_client___dma2___bit 2 -#define reg_marb_bp_r_brk_first_client___dma3___lsb 3 -#define reg_marb_bp_r_brk_first_client___dma3___width 1 -#define reg_marb_bp_r_brk_first_client___dma3___bit 3 -#define reg_marb_bp_r_brk_first_client___dma4___lsb 4 -#define reg_marb_bp_r_brk_first_client___dma4___width 1 -#define reg_marb_bp_r_brk_first_client___dma4___bit 4 -#define reg_marb_bp_r_brk_first_client___dma5___lsb 5 -#define reg_marb_bp_r_brk_first_client___dma5___width 1 -#define reg_marb_bp_r_brk_first_client___dma5___bit 5 -#define reg_marb_bp_r_brk_first_client___dma6___lsb 6 -#define reg_marb_bp_r_brk_first_client___dma6___width 1 -#define reg_marb_bp_r_brk_first_client___dma6___bit 6 -#define reg_marb_bp_r_brk_first_client___dma7___lsb 7 -#define reg_marb_bp_r_brk_first_client___dma7___width 1 -#define reg_marb_bp_r_brk_first_client___dma7___bit 7 -#define reg_marb_bp_r_brk_first_client___dma8___lsb 8 -#define reg_marb_bp_r_brk_first_client___dma8___width 1 -#define reg_marb_bp_r_brk_first_client___dma8___bit 8 -#define reg_marb_bp_r_brk_first_client___dma9___lsb 9 -#define reg_marb_bp_r_brk_first_client___dma9___width 1 -#define reg_marb_bp_r_brk_first_client___dma9___bit 9 -#define reg_marb_bp_r_brk_first_client___cpui___lsb 10 -#define reg_marb_bp_r_brk_first_client___cpui___width 1 -#define reg_marb_bp_r_brk_first_client___cpui___bit 10 -#define reg_marb_bp_r_brk_first_client___cpud___lsb 11 -#define reg_marb_bp_r_brk_first_client___cpud___width 1 -#define reg_marb_bp_r_brk_first_client___cpud___bit 11 -#define reg_marb_bp_r_brk_first_client___iop___lsb 12 -#define reg_marb_bp_r_brk_first_client___iop___width 1 -#define reg_marb_bp_r_brk_first_client___iop___bit 12 -#define reg_marb_bp_r_brk_first_client___slave___lsb 13 -#define reg_marb_bp_r_brk_first_client___slave___width 1 -#define reg_marb_bp_r_brk_first_client___slave___bit 13 -#define reg_marb_bp_r_brk_first_client_offset 32 - -/* Register r_brk_size, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_size_offset 36 - -/* Register rw_ack, scope marb_bp, type rw */ -#define reg_marb_bp_rw_ack_offset 40 - - -/* Constants */ -#define regk_marb_bp_no 0x00000000 -#define regk_marb_bp_rw_op_default 0x00000000 -#define regk_marb_bp_rw_options_default 0x00000000 -#define regk_marb_bp_yes 0x00000001 -#endif /* __marb_bp_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h deleted file mode 100644 index 505b7a16d878..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h +++ /dev/null @@ -1,212 +0,0 @@ -#ifndef __mmu_defs_asm_h -#define __mmu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/mmu/doc/mmu_regs.r - * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp - * last modfied: Mon Apr 11 17:03:20 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r - * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mm_cfg, scope mmu, type rw */ -#define reg_mmu_rw_mm_cfg___seg_0___lsb 0 -#define reg_mmu_rw_mm_cfg___seg_0___width 1 -#define reg_mmu_rw_mm_cfg___seg_0___bit 0 -#define reg_mmu_rw_mm_cfg___seg_1___lsb 1 -#define reg_mmu_rw_mm_cfg___seg_1___width 1 -#define reg_mmu_rw_mm_cfg___seg_1___bit 1 -#define reg_mmu_rw_mm_cfg___seg_2___lsb 2 -#define reg_mmu_rw_mm_cfg___seg_2___width 1 -#define reg_mmu_rw_mm_cfg___seg_2___bit 2 -#define reg_mmu_rw_mm_cfg___seg_3___lsb 3 -#define reg_mmu_rw_mm_cfg___seg_3___width 1 -#define reg_mmu_rw_mm_cfg___seg_3___bit 3 -#define reg_mmu_rw_mm_cfg___seg_4___lsb 4 -#define reg_mmu_rw_mm_cfg___seg_4___width 1 -#define reg_mmu_rw_mm_cfg___seg_4___bit 4 -#define reg_mmu_rw_mm_cfg___seg_5___lsb 5 -#define reg_mmu_rw_mm_cfg___seg_5___width 1 -#define reg_mmu_rw_mm_cfg___seg_5___bit 5 -#define reg_mmu_rw_mm_cfg___seg_6___lsb 6 -#define reg_mmu_rw_mm_cfg___seg_6___width 1 -#define reg_mmu_rw_mm_cfg___seg_6___bit 6 -#define reg_mmu_rw_mm_cfg___seg_7___lsb 7 -#define reg_mmu_rw_mm_cfg___seg_7___width 1 -#define reg_mmu_rw_mm_cfg___seg_7___bit 7 -#define reg_mmu_rw_mm_cfg___seg_8___lsb 8 -#define reg_mmu_rw_mm_cfg___seg_8___width 1 -#define reg_mmu_rw_mm_cfg___seg_8___bit 8 -#define reg_mmu_rw_mm_cfg___seg_9___lsb 9 -#define reg_mmu_rw_mm_cfg___seg_9___width 1 -#define reg_mmu_rw_mm_cfg___seg_9___bit 9 -#define reg_mmu_rw_mm_cfg___seg_a___lsb 10 -#define reg_mmu_rw_mm_cfg___seg_a___width 1 -#define reg_mmu_rw_mm_cfg___seg_a___bit 10 -#define reg_mmu_rw_mm_cfg___seg_b___lsb 11 -#define reg_mmu_rw_mm_cfg___seg_b___width 1 -#define reg_mmu_rw_mm_cfg___seg_b___bit 11 -#define reg_mmu_rw_mm_cfg___seg_c___lsb 12 -#define reg_mmu_rw_mm_cfg___seg_c___width 1 -#define reg_mmu_rw_mm_cfg___seg_c___bit 12 -#define reg_mmu_rw_mm_cfg___seg_d___lsb 13 -#define reg_mmu_rw_mm_cfg___seg_d___width 1 -#define reg_mmu_rw_mm_cfg___seg_d___bit 13 -#define reg_mmu_rw_mm_cfg___seg_e___lsb 14 -#define reg_mmu_rw_mm_cfg___seg_e___width 1 -#define reg_mmu_rw_mm_cfg___seg_e___bit 14 -#define reg_mmu_rw_mm_cfg___seg_f___lsb 15 -#define reg_mmu_rw_mm_cfg___seg_f___width 1 -#define reg_mmu_rw_mm_cfg___seg_f___bit 15 -#define reg_mmu_rw_mm_cfg___inv___lsb 16 -#define reg_mmu_rw_mm_cfg___inv___width 1 -#define reg_mmu_rw_mm_cfg___inv___bit 16 -#define reg_mmu_rw_mm_cfg___ex___lsb 17 -#define reg_mmu_rw_mm_cfg___ex___width 1 -#define reg_mmu_rw_mm_cfg___ex___bit 17 -#define reg_mmu_rw_mm_cfg___acc___lsb 18 -#define reg_mmu_rw_mm_cfg___acc___width 1 -#define reg_mmu_rw_mm_cfg___acc___bit 18 -#define reg_mmu_rw_mm_cfg___we___lsb 19 -#define reg_mmu_rw_mm_cfg___we___width 1 -#define reg_mmu_rw_mm_cfg___we___bit 19 -#define reg_mmu_rw_mm_cfg_offset 0 - -/* Register rw_mm_kbase_lo, scope mmu, type rw */ -#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0 -#define reg_mmu_rw_mm_kbase_lo___base_0___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4 -#define reg_mmu_rw_mm_kbase_lo___base_1___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8 -#define reg_mmu_rw_mm_kbase_lo___base_2___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12 -#define reg_mmu_rw_mm_kbase_lo___base_3___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16 -#define reg_mmu_rw_mm_kbase_lo___base_4___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20 -#define reg_mmu_rw_mm_kbase_lo___base_5___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24 -#define reg_mmu_rw_mm_kbase_lo___base_6___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28 -#define reg_mmu_rw_mm_kbase_lo___base_7___width 4 -#define reg_mmu_rw_mm_kbase_lo_offset 4 - -/* Register rw_mm_kbase_hi, scope mmu, type rw */ -#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0 -#define reg_mmu_rw_mm_kbase_hi___base_8___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4 -#define reg_mmu_rw_mm_kbase_hi___base_9___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8 -#define reg_mmu_rw_mm_kbase_hi___base_a___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12 -#define reg_mmu_rw_mm_kbase_hi___base_b___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16 -#define reg_mmu_rw_mm_kbase_hi___base_c___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20 -#define reg_mmu_rw_mm_kbase_hi___base_d___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24 -#define reg_mmu_rw_mm_kbase_hi___base_e___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28 -#define reg_mmu_rw_mm_kbase_hi___base_f___width 4 -#define reg_mmu_rw_mm_kbase_hi_offset 8 - -/* Register r_mm_cause, scope mmu, type r */ -#define reg_mmu_r_mm_cause___pid___lsb 0 -#define reg_mmu_r_mm_cause___pid___width 8 -#define reg_mmu_r_mm_cause___op___lsb 8 -#define reg_mmu_r_mm_cause___op___width 2 -#define reg_mmu_r_mm_cause___vpn___lsb 13 -#define reg_mmu_r_mm_cause___vpn___width 19 -#define reg_mmu_r_mm_cause_offset 12 - -/* Register rw_mm_tlb_sel, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0 -#define reg_mmu_rw_mm_tlb_sel___idx___width 4 -#define reg_mmu_rw_mm_tlb_sel___set___lsb 4 -#define reg_mmu_rw_mm_tlb_sel___set___width 2 -#define reg_mmu_rw_mm_tlb_sel_offset 16 - -/* Register rw_mm_tlb_lo, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_lo___x___lsb 0 -#define reg_mmu_rw_mm_tlb_lo___x___width 1 -#define reg_mmu_rw_mm_tlb_lo___x___bit 0 -#define reg_mmu_rw_mm_tlb_lo___w___lsb 1 -#define reg_mmu_rw_mm_tlb_lo___w___width 1 -#define reg_mmu_rw_mm_tlb_lo___w___bit 1 -#define reg_mmu_rw_mm_tlb_lo___k___lsb 2 -#define reg_mmu_rw_mm_tlb_lo___k___width 1 -#define reg_mmu_rw_mm_tlb_lo___k___bit 2 -#define reg_mmu_rw_mm_tlb_lo___v___lsb 3 -#define reg_mmu_rw_mm_tlb_lo___v___width 1 -#define reg_mmu_rw_mm_tlb_lo___v___bit 3 -#define reg_mmu_rw_mm_tlb_lo___g___lsb 4 -#define reg_mmu_rw_mm_tlb_lo___g___width 1 -#define reg_mmu_rw_mm_tlb_lo___g___bit 4 -#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13 -#define reg_mmu_rw_mm_tlb_lo___pfn___width 19 -#define reg_mmu_rw_mm_tlb_lo_offset 20 - -/* Register rw_mm_tlb_hi, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0 -#define reg_mmu_rw_mm_tlb_hi___pid___width 8 -#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13 -#define reg_mmu_rw_mm_tlb_hi___vpn___width 19 -#define reg_mmu_rw_mm_tlb_hi_offset 24 - - -/* Constants */ -#define regk_mmu_execute 0x00000000 -#define regk_mmu_flush 0x00000003 -#define regk_mmu_linear 0x00000001 -#define regk_mmu_no 0x00000000 -#define regk_mmu_off 0x00000000 -#define regk_mmu_on 0x00000001 -#define regk_mmu_page 0x00000000 -#define regk_mmu_read 0x00000001 -#define regk_mmu_write 0x00000002 -#define regk_mmu_yes 0x00000001 -#endif /* __mmu_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h deleted file mode 100644 index 339500bf3bc0..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h +++ /dev/null @@ -1,7 +0,0 @@ -#define RW_MM_CFG 0 -#define RW_MM_KBASE_LO 1 -#define RW_MM_KBASE_HI 2 -#define R_MM_CAUSE 3 -#define RW_MM_TLB_SEL 4 -#define RW_MM_TLB_LO 5 -#define RW_MM_TLB_HI 6 diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index 13c725e4c774..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,632 +0,0 @@ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_pa___pa0___lsb 0 -#define reg_pinmux_rw_pa___pa0___width 1 -#define reg_pinmux_rw_pa___pa0___bit 0 -#define reg_pinmux_rw_pa___pa1___lsb 1 -#define reg_pinmux_rw_pa___pa1___width 1 -#define reg_pinmux_rw_pa___pa1___bit 1 -#define reg_pinmux_rw_pa___pa2___lsb 2 -#define reg_pinmux_rw_pa___pa2___width 1 -#define reg_pinmux_rw_pa___pa2___bit 2 -#define reg_pinmux_rw_pa___pa3___lsb 3 -#define reg_pinmux_rw_pa___pa3___width 1 -#define reg_pinmux_rw_pa___pa3___bit 3 -#define reg_pinmux_rw_pa___pa4___lsb 4 -#define reg_pinmux_rw_pa___pa4___width 1 -#define reg_pinmux_rw_pa___pa4___bit 4 -#define reg_pinmux_rw_pa___pa5___lsb 5 -#define reg_pinmux_rw_pa___pa5___width 1 -#define reg_pinmux_rw_pa___pa5___bit 5 -#define reg_pinmux_rw_pa___pa6___lsb 6 -#define reg_pinmux_rw_pa___pa6___width 1 -#define reg_pinmux_rw_pa___pa6___bit 6 -#define reg_pinmux_rw_pa___pa7___lsb 7 -#define reg_pinmux_rw_pa___pa7___width 1 -#define reg_pinmux_rw_pa___pa7___bit 7 -#define reg_pinmux_rw_pa___csp2_n___lsb 8 -#define reg_pinmux_rw_pa___csp2_n___width 1 -#define reg_pinmux_rw_pa___csp2_n___bit 8 -#define reg_pinmux_rw_pa___csp3_n___lsb 9 -#define reg_pinmux_rw_pa___csp3_n___width 1 -#define reg_pinmux_rw_pa___csp3_n___bit 9 -#define reg_pinmux_rw_pa___csp5_n___lsb 10 -#define reg_pinmux_rw_pa___csp5_n___width 1 -#define reg_pinmux_rw_pa___csp5_n___bit 10 -#define reg_pinmux_rw_pa___csp6_n___lsb 11 -#define reg_pinmux_rw_pa___csp6_n___width 1 -#define reg_pinmux_rw_pa___csp6_n___bit 11 -#define reg_pinmux_rw_pa___hsh4___lsb 12 -#define reg_pinmux_rw_pa___hsh4___width 1 -#define reg_pinmux_rw_pa___hsh4___bit 12 -#define reg_pinmux_rw_pa___hsh5___lsb 13 -#define reg_pinmux_rw_pa___hsh5___width 1 -#define reg_pinmux_rw_pa___hsh5___bit 13 -#define reg_pinmux_rw_pa___hsh6___lsb 14 -#define reg_pinmux_rw_pa___hsh6___width 1 -#define reg_pinmux_rw_pa___hsh6___bit 14 -#define reg_pinmux_rw_pa___hsh7___lsb 15 -#define reg_pinmux_rw_pa___hsh7___width 1 -#define reg_pinmux_rw_pa___hsh7___bit 15 -#define reg_pinmux_rw_pa_offset 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___ser1___lsb 0 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 0 -#define reg_pinmux_rw_hwprot___ser2___lsb 1 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 1 -#define reg_pinmux_rw_hwprot___ser3___lsb 2 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 2 -#define reg_pinmux_rw_hwprot___sser0___lsb 3 -#define reg_pinmux_rw_hwprot___sser0___width 1 -#define reg_pinmux_rw_hwprot___sser0___bit 3 -#define reg_pinmux_rw_hwprot___sser1___lsb 4 -#define reg_pinmux_rw_hwprot___sser1___width 1 -#define reg_pinmux_rw_hwprot___sser1___bit 4 -#define reg_pinmux_rw_hwprot___ata0___lsb 5 -#define reg_pinmux_rw_hwprot___ata0___width 1 -#define reg_pinmux_rw_hwprot___ata0___bit 5 -#define reg_pinmux_rw_hwprot___ata1___lsb 6 -#define reg_pinmux_rw_hwprot___ata1___width 1 -#define reg_pinmux_rw_hwprot___ata1___bit 6 -#define reg_pinmux_rw_hwprot___ata2___lsb 7 -#define reg_pinmux_rw_hwprot___ata2___width 1 -#define reg_pinmux_rw_hwprot___ata2___bit 7 -#define reg_pinmux_rw_hwprot___ata3___lsb 8 -#define reg_pinmux_rw_hwprot___ata3___width 1 -#define reg_pinmux_rw_hwprot___ata3___bit 8 -#define reg_pinmux_rw_hwprot___ata___lsb 9 -#define reg_pinmux_rw_hwprot___ata___width 1 -#define reg_pinmux_rw_hwprot___ata___bit 9 -#define reg_pinmux_rw_hwprot___eth1___lsb 10 -#define reg_pinmux_rw_hwprot___eth1___width 1 -#define reg_pinmux_rw_hwprot___eth1___bit 10 -#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 -#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 -#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 -#define reg_pinmux_rw_hwprot___timer___lsb 12 -#define reg_pinmux_rw_hwprot___timer___width 1 -#define reg_pinmux_rw_hwprot___timer___bit 12 -#define reg_pinmux_rw_hwprot___p21___lsb 13 -#define reg_pinmux_rw_hwprot___p21___width 1 -#define reg_pinmux_rw_hwprot___p21___bit 13 -#define reg_pinmux_rw_hwprot_offset 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_gio___pb0___lsb 0 -#define reg_pinmux_rw_pb_gio___pb0___width 1 -#define reg_pinmux_rw_pb_gio___pb0___bit 0 -#define reg_pinmux_rw_pb_gio___pb1___lsb 1 -#define reg_pinmux_rw_pb_gio___pb1___width 1 -#define reg_pinmux_rw_pb_gio___pb1___bit 1 -#define reg_pinmux_rw_pb_gio___pb2___lsb 2 -#define reg_pinmux_rw_pb_gio___pb2___width 1 -#define reg_pinmux_rw_pb_gio___pb2___bit 2 -#define reg_pinmux_rw_pb_gio___pb3___lsb 3 -#define reg_pinmux_rw_pb_gio___pb3___width 1 -#define reg_pinmux_rw_pb_gio___pb3___bit 3 -#define reg_pinmux_rw_pb_gio___pb4___lsb 4 -#define reg_pinmux_rw_pb_gio___pb4___width 1 -#define reg_pinmux_rw_pb_gio___pb4___bit 4 -#define reg_pinmux_rw_pb_gio___pb5___lsb 5 -#define reg_pinmux_rw_pb_gio___pb5___width 1 -#define reg_pinmux_rw_pb_gio___pb5___bit 5 -#define reg_pinmux_rw_pb_gio___pb6___lsb 6 -#define reg_pinmux_rw_pb_gio___pb6___width 1 -#define reg_pinmux_rw_pb_gio___pb6___bit 6 -#define reg_pinmux_rw_pb_gio___pb7___lsb 7 -#define reg_pinmux_rw_pb_gio___pb7___width 1 -#define reg_pinmux_rw_pb_gio___pb7___bit 7 -#define reg_pinmux_rw_pb_gio___pb8___lsb 8 -#define reg_pinmux_rw_pb_gio___pb8___width 1 -#define reg_pinmux_rw_pb_gio___pb8___bit 8 -#define reg_pinmux_rw_pb_gio___pb9___lsb 9 -#define reg_pinmux_rw_pb_gio___pb9___width 1 -#define reg_pinmux_rw_pb_gio___pb9___bit 9 -#define reg_pinmux_rw_pb_gio___pb10___lsb 10 -#define reg_pinmux_rw_pb_gio___pb10___width 1 -#define reg_pinmux_rw_pb_gio___pb10___bit 10 -#define reg_pinmux_rw_pb_gio___pb11___lsb 11 -#define reg_pinmux_rw_pb_gio___pb11___width 1 -#define reg_pinmux_rw_pb_gio___pb11___bit 11 -#define reg_pinmux_rw_pb_gio___pb12___lsb 12 -#define reg_pinmux_rw_pb_gio___pb12___width 1 -#define reg_pinmux_rw_pb_gio___pb12___bit 12 -#define reg_pinmux_rw_pb_gio___pb13___lsb 13 -#define reg_pinmux_rw_pb_gio___pb13___width 1 -#define reg_pinmux_rw_pb_gio___pb13___bit 13 -#define reg_pinmux_rw_pb_gio___pb14___lsb 14 -#define reg_pinmux_rw_pb_gio___pb14___width 1 -#define reg_pinmux_rw_pb_gio___pb14___bit 14 -#define reg_pinmux_rw_pb_gio___pb15___lsb 15 -#define reg_pinmux_rw_pb_gio___pb15___width 1 -#define reg_pinmux_rw_pb_gio___pb15___bit 15 -#define reg_pinmux_rw_pb_gio___pb16___lsb 16 -#define reg_pinmux_rw_pb_gio___pb16___width 1 -#define reg_pinmux_rw_pb_gio___pb16___bit 16 -#define reg_pinmux_rw_pb_gio___pb17___lsb 17 -#define reg_pinmux_rw_pb_gio___pb17___width 1 -#define reg_pinmux_rw_pb_gio___pb17___bit 17 -#define reg_pinmux_rw_pb_gio_offset 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_iop___pb0___lsb 0 -#define reg_pinmux_rw_pb_iop___pb0___width 1 -#define reg_pinmux_rw_pb_iop___pb0___bit 0 -#define reg_pinmux_rw_pb_iop___pb1___lsb 1 -#define reg_pinmux_rw_pb_iop___pb1___width 1 -#define reg_pinmux_rw_pb_iop___pb1___bit 1 -#define reg_pinmux_rw_pb_iop___pb2___lsb 2 -#define reg_pinmux_rw_pb_iop___pb2___width 1 -#define reg_pinmux_rw_pb_iop___pb2___bit 2 -#define reg_pinmux_rw_pb_iop___pb3___lsb 3 -#define reg_pinmux_rw_pb_iop___pb3___width 1 -#define reg_pinmux_rw_pb_iop___pb3___bit 3 -#define reg_pinmux_rw_pb_iop___pb4___lsb 4 -#define reg_pinmux_rw_pb_iop___pb4___width 1 -#define reg_pinmux_rw_pb_iop___pb4___bit 4 -#define reg_pinmux_rw_pb_iop___pb5___lsb 5 -#define reg_pinmux_rw_pb_iop___pb5___width 1 -#define reg_pinmux_rw_pb_iop___pb5___bit 5 -#define reg_pinmux_rw_pb_iop___pb6___lsb 6 -#define reg_pinmux_rw_pb_iop___pb6___width 1 -#define reg_pinmux_rw_pb_iop___pb6___bit 6 -#define reg_pinmux_rw_pb_iop___pb7___lsb 7 -#define reg_pinmux_rw_pb_iop___pb7___width 1 -#define reg_pinmux_rw_pb_iop___pb7___bit 7 -#define reg_pinmux_rw_pb_iop___pb8___lsb 8 -#define reg_pinmux_rw_pb_iop___pb8___width 1 -#define reg_pinmux_rw_pb_iop___pb8___bit 8 -#define reg_pinmux_rw_pb_iop___pb9___lsb 9 -#define reg_pinmux_rw_pb_iop___pb9___width 1 -#define reg_pinmux_rw_pb_iop___pb9___bit 9 -#define reg_pinmux_rw_pb_iop___pb10___lsb 10 -#define reg_pinmux_rw_pb_iop___pb10___width 1 -#define reg_pinmux_rw_pb_iop___pb10___bit 10 -#define reg_pinmux_rw_pb_iop___pb11___lsb 11 -#define reg_pinmux_rw_pb_iop___pb11___width 1 -#define reg_pinmux_rw_pb_iop___pb11___bit 11 -#define reg_pinmux_rw_pb_iop___pb12___lsb 12 -#define reg_pinmux_rw_pb_iop___pb12___width 1 -#define reg_pinmux_rw_pb_iop___pb12___bit 12 -#define reg_pinmux_rw_pb_iop___pb13___lsb 13 -#define reg_pinmux_rw_pb_iop___pb13___width 1 -#define reg_pinmux_rw_pb_iop___pb13___bit 13 -#define reg_pinmux_rw_pb_iop___pb14___lsb 14 -#define reg_pinmux_rw_pb_iop___pb14___width 1 -#define reg_pinmux_rw_pb_iop___pb14___bit 14 -#define reg_pinmux_rw_pb_iop___pb15___lsb 15 -#define reg_pinmux_rw_pb_iop___pb15___width 1 -#define reg_pinmux_rw_pb_iop___pb15___bit 15 -#define reg_pinmux_rw_pb_iop___pb16___lsb 16 -#define reg_pinmux_rw_pb_iop___pb16___width 1 -#define reg_pinmux_rw_pb_iop___pb16___bit 16 -#define reg_pinmux_rw_pb_iop___pb17___lsb 17 -#define reg_pinmux_rw_pb_iop___pb17___width 1 -#define reg_pinmux_rw_pb_iop___pb17___bit 17 -#define reg_pinmux_rw_pb_iop_offset 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_gio___pc0___lsb 0 -#define reg_pinmux_rw_pc_gio___pc0___width 1 -#define reg_pinmux_rw_pc_gio___pc0___bit 0 -#define reg_pinmux_rw_pc_gio___pc1___lsb 1 -#define reg_pinmux_rw_pc_gio___pc1___width 1 -#define reg_pinmux_rw_pc_gio___pc1___bit 1 -#define reg_pinmux_rw_pc_gio___pc2___lsb 2 -#define reg_pinmux_rw_pc_gio___pc2___width 1 -#define reg_pinmux_rw_pc_gio___pc2___bit 2 -#define reg_pinmux_rw_pc_gio___pc3___lsb 3 -#define reg_pinmux_rw_pc_gio___pc3___width 1 -#define reg_pinmux_rw_pc_gio___pc3___bit 3 -#define reg_pinmux_rw_pc_gio___pc4___lsb 4 -#define reg_pinmux_rw_pc_gio___pc4___width 1 -#define reg_pinmux_rw_pc_gio___pc4___bit 4 -#define reg_pinmux_rw_pc_gio___pc5___lsb 5 -#define reg_pinmux_rw_pc_gio___pc5___width 1 -#define reg_pinmux_rw_pc_gio___pc5___bit 5 -#define reg_pinmux_rw_pc_gio___pc6___lsb 6 -#define reg_pinmux_rw_pc_gio___pc6___width 1 -#define reg_pinmux_rw_pc_gio___pc6___bit 6 -#define reg_pinmux_rw_pc_gio___pc7___lsb 7 -#define reg_pinmux_rw_pc_gio___pc7___width 1 -#define reg_pinmux_rw_pc_gio___pc7___bit 7 -#define reg_pinmux_rw_pc_gio___pc8___lsb 8 -#define reg_pinmux_rw_pc_gio___pc8___width 1 -#define reg_pinmux_rw_pc_gio___pc8___bit 8 -#define reg_pinmux_rw_pc_gio___pc9___lsb 9 -#define reg_pinmux_rw_pc_gio___pc9___width 1 -#define reg_pinmux_rw_pc_gio___pc9___bit 9 -#define reg_pinmux_rw_pc_gio___pc10___lsb 10 -#define reg_pinmux_rw_pc_gio___pc10___width 1 -#define reg_pinmux_rw_pc_gio___pc10___bit 10 -#define reg_pinmux_rw_pc_gio___pc11___lsb 11 -#define reg_pinmux_rw_pc_gio___pc11___width 1 -#define reg_pinmux_rw_pc_gio___pc11___bit 11 -#define reg_pinmux_rw_pc_gio___pc12___lsb 12 -#define reg_pinmux_rw_pc_gio___pc12___width 1 -#define reg_pinmux_rw_pc_gio___pc12___bit 12 -#define reg_pinmux_rw_pc_gio___pc13___lsb 13 -#define reg_pinmux_rw_pc_gio___pc13___width 1 -#define reg_pinmux_rw_pc_gio___pc13___bit 13 -#define reg_pinmux_rw_pc_gio___pc14___lsb 14 -#define reg_pinmux_rw_pc_gio___pc14___width 1 -#define reg_pinmux_rw_pc_gio___pc14___bit 14 -#define reg_pinmux_rw_pc_gio___pc15___lsb 15 -#define reg_pinmux_rw_pc_gio___pc15___width 1 -#define reg_pinmux_rw_pc_gio___pc15___bit 15 -#define reg_pinmux_rw_pc_gio___pc16___lsb 16 -#define reg_pinmux_rw_pc_gio___pc16___width 1 -#define reg_pinmux_rw_pc_gio___pc16___bit 16 -#define reg_pinmux_rw_pc_gio___pc17___lsb 17 -#define reg_pinmux_rw_pc_gio___pc17___width 1 -#define reg_pinmux_rw_pc_gio___pc17___bit 17 -#define reg_pinmux_rw_pc_gio_offset 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_iop___pc0___lsb 0 -#define reg_pinmux_rw_pc_iop___pc0___width 1 -#define reg_pinmux_rw_pc_iop___pc0___bit 0 -#define reg_pinmux_rw_pc_iop___pc1___lsb 1 -#define reg_pinmux_rw_pc_iop___pc1___width 1 -#define reg_pinmux_rw_pc_iop___pc1___bit 1 -#define reg_pinmux_rw_pc_iop___pc2___lsb 2 -#define reg_pinmux_rw_pc_iop___pc2___width 1 -#define reg_pinmux_rw_pc_iop___pc2___bit 2 -#define reg_pinmux_rw_pc_iop___pc3___lsb 3 -#define reg_pinmux_rw_pc_iop___pc3___width 1 -#define reg_pinmux_rw_pc_iop___pc3___bit 3 -#define reg_pinmux_rw_pc_iop___pc4___lsb 4 -#define reg_pinmux_rw_pc_iop___pc4___width 1 -#define reg_pinmux_rw_pc_iop___pc4___bit 4 -#define reg_pinmux_rw_pc_iop___pc5___lsb 5 -#define reg_pinmux_rw_pc_iop___pc5___width 1 -#define reg_pinmux_rw_pc_iop___pc5___bit 5 -#define reg_pinmux_rw_pc_iop___pc6___lsb 6 -#define reg_pinmux_rw_pc_iop___pc6___width 1 -#define reg_pinmux_rw_pc_iop___pc6___bit 6 -#define reg_pinmux_rw_pc_iop___pc7___lsb 7 -#define reg_pinmux_rw_pc_iop___pc7___width 1 -#define reg_pinmux_rw_pc_iop___pc7___bit 7 -#define reg_pinmux_rw_pc_iop___pc8___lsb 8 -#define reg_pinmux_rw_pc_iop___pc8___width 1 -#define reg_pinmux_rw_pc_iop___pc8___bit 8 -#define reg_pinmux_rw_pc_iop___pc9___lsb 9 -#define reg_pinmux_rw_pc_iop___pc9___width 1 -#define reg_pinmux_rw_pc_iop___pc9___bit 9 -#define reg_pinmux_rw_pc_iop___pc10___lsb 10 -#define reg_pinmux_rw_pc_iop___pc10___width 1 -#define reg_pinmux_rw_pc_iop___pc10___bit 10 -#define reg_pinmux_rw_pc_iop___pc11___lsb 11 -#define reg_pinmux_rw_pc_iop___pc11___width 1 -#define reg_pinmux_rw_pc_iop___pc11___bit 11 -#define reg_pinmux_rw_pc_iop___pc12___lsb 12 -#define reg_pinmux_rw_pc_iop___pc12___width 1 -#define reg_pinmux_rw_pc_iop___pc12___bit 12 -#define reg_pinmux_rw_pc_iop___pc13___lsb 13 -#define reg_pinmux_rw_pc_iop___pc13___width 1 -#define reg_pinmux_rw_pc_iop___pc13___bit 13 -#define reg_pinmux_rw_pc_iop___pc14___lsb 14 -#define reg_pinmux_rw_pc_iop___pc14___width 1 -#define reg_pinmux_rw_pc_iop___pc14___bit 14 -#define reg_pinmux_rw_pc_iop___pc15___lsb 15 -#define reg_pinmux_rw_pc_iop___pc15___width 1 -#define reg_pinmux_rw_pc_iop___pc15___bit 15 -#define reg_pinmux_rw_pc_iop___pc16___lsb 16 -#define reg_pinmux_rw_pc_iop___pc16___width 1 -#define reg_pinmux_rw_pc_iop___pc16___bit 16 -#define reg_pinmux_rw_pc_iop___pc17___lsb 17 -#define reg_pinmux_rw_pc_iop___pc17___width 1 -#define reg_pinmux_rw_pc_iop___pc17___bit 17 -#define reg_pinmux_rw_pc_iop_offset 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_gio___pd0___lsb 0 -#define reg_pinmux_rw_pd_gio___pd0___width 1 -#define reg_pinmux_rw_pd_gio___pd0___bit 0 -#define reg_pinmux_rw_pd_gio___pd1___lsb 1 -#define reg_pinmux_rw_pd_gio___pd1___width 1 -#define reg_pinmux_rw_pd_gio___pd1___bit 1 -#define reg_pinmux_rw_pd_gio___pd2___lsb 2 -#define reg_pinmux_rw_pd_gio___pd2___width 1 -#define reg_pinmux_rw_pd_gio___pd2___bit 2 -#define reg_pinmux_rw_pd_gio___pd3___lsb 3 -#define reg_pinmux_rw_pd_gio___pd3___width 1 -#define reg_pinmux_rw_pd_gio___pd3___bit 3 -#define reg_pinmux_rw_pd_gio___pd4___lsb 4 -#define reg_pinmux_rw_pd_gio___pd4___width 1 -#define reg_pinmux_rw_pd_gio___pd4___bit 4 -#define reg_pinmux_rw_pd_gio___pd5___lsb 5 -#define reg_pinmux_rw_pd_gio___pd5___width 1 -#define reg_pinmux_rw_pd_gio___pd5___bit 5 -#define reg_pinmux_rw_pd_gio___pd6___lsb 6 -#define reg_pinmux_rw_pd_gio___pd6___width 1 -#define reg_pinmux_rw_pd_gio___pd6___bit 6 -#define reg_pinmux_rw_pd_gio___pd7___lsb 7 -#define reg_pinmux_rw_pd_gio___pd7___width 1 -#define reg_pinmux_rw_pd_gio___pd7___bit 7 -#define reg_pinmux_rw_pd_gio___pd8___lsb 8 -#define reg_pinmux_rw_pd_gio___pd8___width 1 -#define reg_pinmux_rw_pd_gio___pd8___bit 8 -#define reg_pinmux_rw_pd_gio___pd9___lsb 9 -#define reg_pinmux_rw_pd_gio___pd9___width 1 -#define reg_pinmux_rw_pd_gio___pd9___bit 9 -#define reg_pinmux_rw_pd_gio___pd10___lsb 10 -#define reg_pinmux_rw_pd_gio___pd10___width 1 -#define reg_pinmux_rw_pd_gio___pd10___bit 10 -#define reg_pinmux_rw_pd_gio___pd11___lsb 11 -#define reg_pinmux_rw_pd_gio___pd11___width 1 -#define reg_pinmux_rw_pd_gio___pd11___bit 11 -#define reg_pinmux_rw_pd_gio___pd12___lsb 12 -#define reg_pinmux_rw_pd_gio___pd12___width 1 -#define reg_pinmux_rw_pd_gio___pd12___bit 12 -#define reg_pinmux_rw_pd_gio___pd13___lsb 13 -#define reg_pinmux_rw_pd_gio___pd13___width 1 -#define reg_pinmux_rw_pd_gio___pd13___bit 13 -#define reg_pinmux_rw_pd_gio___pd14___lsb 14 -#define reg_pinmux_rw_pd_gio___pd14___width 1 -#define reg_pinmux_rw_pd_gio___pd14___bit 14 -#define reg_pinmux_rw_pd_gio___pd15___lsb 15 -#define reg_pinmux_rw_pd_gio___pd15___width 1 -#define reg_pinmux_rw_pd_gio___pd15___bit 15 -#define reg_pinmux_rw_pd_gio___pd16___lsb 16 -#define reg_pinmux_rw_pd_gio___pd16___width 1 -#define reg_pinmux_rw_pd_gio___pd16___bit 16 -#define reg_pinmux_rw_pd_gio___pd17___lsb 17 -#define reg_pinmux_rw_pd_gio___pd17___width 1 -#define reg_pinmux_rw_pd_gio___pd17___bit 17 -#define reg_pinmux_rw_pd_gio_offset 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_iop___pd0___lsb 0 -#define reg_pinmux_rw_pd_iop___pd0___width 1 -#define reg_pinmux_rw_pd_iop___pd0___bit 0 -#define reg_pinmux_rw_pd_iop___pd1___lsb 1 -#define reg_pinmux_rw_pd_iop___pd1___width 1 -#define reg_pinmux_rw_pd_iop___pd1___bit 1 -#define reg_pinmux_rw_pd_iop___pd2___lsb 2 -#define reg_pinmux_rw_pd_iop___pd2___width 1 -#define reg_pinmux_rw_pd_iop___pd2___bit 2 -#define reg_pinmux_rw_pd_iop___pd3___lsb 3 -#define reg_pinmux_rw_pd_iop___pd3___width 1 -#define reg_pinmux_rw_pd_iop___pd3___bit 3 -#define reg_pinmux_rw_pd_iop___pd4___lsb 4 -#define reg_pinmux_rw_pd_iop___pd4___width 1 -#define reg_pinmux_rw_pd_iop___pd4___bit 4 -#define reg_pinmux_rw_pd_iop___pd5___lsb 5 -#define reg_pinmux_rw_pd_iop___pd5___width 1 -#define reg_pinmux_rw_pd_iop___pd5___bit 5 -#define reg_pinmux_rw_pd_iop___pd6___lsb 6 -#define reg_pinmux_rw_pd_iop___pd6___width 1 -#define reg_pinmux_rw_pd_iop___pd6___bit 6 -#define reg_pinmux_rw_pd_iop___pd7___lsb 7 -#define reg_pinmux_rw_pd_iop___pd7___width 1 -#define reg_pinmux_rw_pd_iop___pd7___bit 7 -#define reg_pinmux_rw_pd_iop___pd8___lsb 8 -#define reg_pinmux_rw_pd_iop___pd8___width 1 -#define reg_pinmux_rw_pd_iop___pd8___bit 8 -#define reg_pinmux_rw_pd_iop___pd9___lsb 9 -#define reg_pinmux_rw_pd_iop___pd9___width 1 -#define reg_pinmux_rw_pd_iop___pd9___bit 9 -#define reg_pinmux_rw_pd_iop___pd10___lsb 10 -#define reg_pinmux_rw_pd_iop___pd10___width 1 -#define reg_pinmux_rw_pd_iop___pd10___bit 10 -#define reg_pinmux_rw_pd_iop___pd11___lsb 11 -#define reg_pinmux_rw_pd_iop___pd11___width 1 -#define reg_pinmux_rw_pd_iop___pd11___bit 11 -#define reg_pinmux_rw_pd_iop___pd12___lsb 12 -#define reg_pinmux_rw_pd_iop___pd12___width 1 -#define reg_pinmux_rw_pd_iop___pd12___bit 12 -#define reg_pinmux_rw_pd_iop___pd13___lsb 13 -#define reg_pinmux_rw_pd_iop___pd13___width 1 -#define reg_pinmux_rw_pd_iop___pd13___bit 13 -#define reg_pinmux_rw_pd_iop___pd14___lsb 14 -#define reg_pinmux_rw_pd_iop___pd14___width 1 -#define reg_pinmux_rw_pd_iop___pd14___bit 14 -#define reg_pinmux_rw_pd_iop___pd15___lsb 15 -#define reg_pinmux_rw_pd_iop___pd15___width 1 -#define reg_pinmux_rw_pd_iop___pd15___bit 15 -#define reg_pinmux_rw_pd_iop___pd16___lsb 16 -#define reg_pinmux_rw_pd_iop___pd16___width 1 -#define reg_pinmux_rw_pd_iop___pd16___bit 16 -#define reg_pinmux_rw_pd_iop___pd17___lsb 17 -#define reg_pinmux_rw_pd_iop___pd17___width 1 -#define reg_pinmux_rw_pd_iop___pd17___bit 17 -#define reg_pinmux_rw_pd_iop_offset 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_gio___pe0___lsb 0 -#define reg_pinmux_rw_pe_gio___pe0___width 1 -#define reg_pinmux_rw_pe_gio___pe0___bit 0 -#define reg_pinmux_rw_pe_gio___pe1___lsb 1 -#define reg_pinmux_rw_pe_gio___pe1___width 1 -#define reg_pinmux_rw_pe_gio___pe1___bit 1 -#define reg_pinmux_rw_pe_gio___pe2___lsb 2 -#define reg_pinmux_rw_pe_gio___pe2___width 1 -#define reg_pinmux_rw_pe_gio___pe2___bit 2 -#define reg_pinmux_rw_pe_gio___pe3___lsb 3 -#define reg_pinmux_rw_pe_gio___pe3___width 1 -#define reg_pinmux_rw_pe_gio___pe3___bit 3 -#define reg_pinmux_rw_pe_gio___pe4___lsb 4 -#define reg_pinmux_rw_pe_gio___pe4___width 1 -#define reg_pinmux_rw_pe_gio___pe4___bit 4 -#define reg_pinmux_rw_pe_gio___pe5___lsb 5 -#define reg_pinmux_rw_pe_gio___pe5___width 1 -#define reg_pinmux_rw_pe_gio___pe5___bit 5 -#define reg_pinmux_rw_pe_gio___pe6___lsb 6 -#define reg_pinmux_rw_pe_gio___pe6___width 1 -#define reg_pinmux_rw_pe_gio___pe6___bit 6 -#define reg_pinmux_rw_pe_gio___pe7___lsb 7 -#define reg_pinmux_rw_pe_gio___pe7___width 1 -#define reg_pinmux_rw_pe_gio___pe7___bit 7 -#define reg_pinmux_rw_pe_gio___pe8___lsb 8 -#define reg_pinmux_rw_pe_gio___pe8___width 1 -#define reg_pinmux_rw_pe_gio___pe8___bit 8 -#define reg_pinmux_rw_pe_gio___pe9___lsb 9 -#define reg_pinmux_rw_pe_gio___pe9___width 1 -#define reg_pinmux_rw_pe_gio___pe9___bit 9 -#define reg_pinmux_rw_pe_gio___pe10___lsb 10 -#define reg_pinmux_rw_pe_gio___pe10___width 1 -#define reg_pinmux_rw_pe_gio___pe10___bit 10 -#define reg_pinmux_rw_pe_gio___pe11___lsb 11 -#define reg_pinmux_rw_pe_gio___pe11___width 1 -#define reg_pinmux_rw_pe_gio___pe11___bit 11 -#define reg_pinmux_rw_pe_gio___pe12___lsb 12 -#define reg_pinmux_rw_pe_gio___pe12___width 1 -#define reg_pinmux_rw_pe_gio___pe12___bit 12 -#define reg_pinmux_rw_pe_gio___pe13___lsb 13 -#define reg_pinmux_rw_pe_gio___pe13___width 1 -#define reg_pinmux_rw_pe_gio___pe13___bit 13 -#define reg_pinmux_rw_pe_gio___pe14___lsb 14 -#define reg_pinmux_rw_pe_gio___pe14___width 1 -#define reg_pinmux_rw_pe_gio___pe14___bit 14 -#define reg_pinmux_rw_pe_gio___pe15___lsb 15 -#define reg_pinmux_rw_pe_gio___pe15___width 1 -#define reg_pinmux_rw_pe_gio___pe15___bit 15 -#define reg_pinmux_rw_pe_gio___pe16___lsb 16 -#define reg_pinmux_rw_pe_gio___pe16___width 1 -#define reg_pinmux_rw_pe_gio___pe16___bit 16 -#define reg_pinmux_rw_pe_gio___pe17___lsb 17 -#define reg_pinmux_rw_pe_gio___pe17___width 1 -#define reg_pinmux_rw_pe_gio___pe17___bit 17 -#define reg_pinmux_rw_pe_gio_offset 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_iop___pe0___lsb 0 -#define reg_pinmux_rw_pe_iop___pe0___width 1 -#define reg_pinmux_rw_pe_iop___pe0___bit 0 -#define reg_pinmux_rw_pe_iop___pe1___lsb 1 -#define reg_pinmux_rw_pe_iop___pe1___width 1 -#define reg_pinmux_rw_pe_iop___pe1___bit 1 -#define reg_pinmux_rw_pe_iop___pe2___lsb 2 -#define reg_pinmux_rw_pe_iop___pe2___width 1 -#define reg_pinmux_rw_pe_iop___pe2___bit 2 -#define reg_pinmux_rw_pe_iop___pe3___lsb 3 -#define reg_pinmux_rw_pe_iop___pe3___width 1 -#define reg_pinmux_rw_pe_iop___pe3___bit 3 -#define reg_pinmux_rw_pe_iop___pe4___lsb 4 -#define reg_pinmux_rw_pe_iop___pe4___width 1 -#define reg_pinmux_rw_pe_iop___pe4___bit 4 -#define reg_pinmux_rw_pe_iop___pe5___lsb 5 -#define reg_pinmux_rw_pe_iop___pe5___width 1 -#define reg_pinmux_rw_pe_iop___pe5___bit 5 -#define reg_pinmux_rw_pe_iop___pe6___lsb 6 -#define reg_pinmux_rw_pe_iop___pe6___width 1 -#define reg_pinmux_rw_pe_iop___pe6___bit 6 -#define reg_pinmux_rw_pe_iop___pe7___lsb 7 -#define reg_pinmux_rw_pe_iop___pe7___width 1 -#define reg_pinmux_rw_pe_iop___pe7___bit 7 -#define reg_pinmux_rw_pe_iop___pe8___lsb 8 -#define reg_pinmux_rw_pe_iop___pe8___width 1 -#define reg_pinmux_rw_pe_iop___pe8___bit 8 -#define reg_pinmux_rw_pe_iop___pe9___lsb 9 -#define reg_pinmux_rw_pe_iop___pe9___width 1 -#define reg_pinmux_rw_pe_iop___pe9___bit 9 -#define reg_pinmux_rw_pe_iop___pe10___lsb 10 -#define reg_pinmux_rw_pe_iop___pe10___width 1 -#define reg_pinmux_rw_pe_iop___pe10___bit 10 -#define reg_pinmux_rw_pe_iop___pe11___lsb 11 -#define reg_pinmux_rw_pe_iop___pe11___width 1 -#define reg_pinmux_rw_pe_iop___pe11___bit 11 -#define reg_pinmux_rw_pe_iop___pe12___lsb 12 -#define reg_pinmux_rw_pe_iop___pe12___width 1 -#define reg_pinmux_rw_pe_iop___pe12___bit 12 -#define reg_pinmux_rw_pe_iop___pe13___lsb 13 -#define reg_pinmux_rw_pe_iop___pe13___width 1 -#define reg_pinmux_rw_pe_iop___pe13___bit 13 -#define reg_pinmux_rw_pe_iop___pe14___lsb 14 -#define reg_pinmux_rw_pe_iop___pe14___width 1 -#define reg_pinmux_rw_pe_iop___pe14___bit 14 -#define reg_pinmux_rw_pe_iop___pe15___lsb 15 -#define reg_pinmux_rw_pe_iop___pe15___width 1 -#define reg_pinmux_rw_pe_iop___pe15___bit 15 -#define reg_pinmux_rw_pe_iop___pe16___lsb 16 -#define reg_pinmux_rw_pe_iop___pe16___width 1 -#define reg_pinmux_rw_pe_iop___pe16___bit 16 -#define reg_pinmux_rw_pe_iop___pe17___lsb 17 -#define reg_pinmux_rw_pe_iop___pe17___width 1 -#define reg_pinmux_rw_pe_iop___pe17___bit 17 -#define reg_pinmux_rw_pe_iop_offset 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 -#define reg_pinmux_rw_usb_phy___en_usb0___width 1 -#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 -#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 -#define reg_pinmux_rw_usb_phy___en_usb1___width 1 -#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 -#define reg_pinmux_rw_usb_phy_offset 40 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_pa_default 0x00000000 -#define regk_pinmux_rw_pb_gio_default 0x00000000 -#define regk_pinmux_rw_pb_iop_default 0x00000000 -#define regk_pinmux_rw_pc_gio_default 0x00000000 -#define regk_pinmux_rw_pc_iop_default 0x00000000 -#define regk_pinmux_rw_pd_gio_default 0x00000000 -#define regk_pinmux_rw_pd_iop_default 0x00000000 -#define regk_pinmux_rw_pe_gio_default 0x00000000 -#define regk_pinmux_rw_pe_iop_default 0x00000000 -#define regk_pinmux_rw_usb_phy_default 0x00000000 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 76959b70cd2c..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,96 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_artpec_mod 0xb7044000 -#define regi_ata 0xb0032000 -#define regi_ata_mod 0xb7006000 -#define regi_barber 0xb701a000 -#define regi_bif_core 0xb0014000 -#define regi_bif_dma 0xb0016000 -#define regi_bif_slave 0xb0018000 -#define regi_bif_slave_ext 0xac000000 -#define regi_bus_master 0xb703c000 -#define regi_config 0xb003c000 -#define regi_dma0 0xb0000000 -#define regi_dma1 0xb0002000 -#define regi_dma2 0xb0004000 -#define regi_dma3 0xb0006000 -#define regi_dma4 0xb0008000 -#define regi_dma5 0xb000a000 -#define regi_dma6 0xb000c000 -#define regi_dma7 0xb000e000 -#define regi_dma8 0xb0010000 -#define regi_dma9 0xb0012000 -#define regi_eth0 0xb0034000 -#define regi_eth1 0xb0036000 -#define regi_eth_mod 0xb7004000 -#define regi_eth_mod1 0xb701c000 -#define regi_eth_strmod 0xb7008000 -#define regi_eth_strmod1 0xb7032000 -#define regi_ext_dma 0xb703a000 -#define regi_ext_mem 0xb7046000 -#define regi_gen_io 0xb7016000 -#define regi_gio 0xb001a000 -#define regi_hook 0xb7000000 -#define regi_iop 0xb0020000 -#define regi_irq 0xb001c000 -#define regi_irq_nmi 0xb701e000 -#define regi_marb 0xb003e000 -#define regi_marb_bp0 0xb003e240 -#define regi_marb_bp1 0xb003e280 -#define regi_marb_bp2 0xb003e2c0 -#define regi_marb_bp3 0xb003e300 -#define regi_nand_mod 0xb7014000 -#define regi_p21 0xb002e000 -#define regi_p21_mod 0xb7042000 -#define regi_pci_mod 0xb7010000 -#define regi_pin_test 0xb7018000 -#define regi_pinmux 0xb0038000 -#define regi_sdram_chk 0xb703e000 -#define regi_sdram_mod 0xb7012000 -#define regi_ser0 0xb0026000 -#define regi_ser1 0xb0028000 -#define regi_ser2 0xb002a000 -#define regi_ser3 0xb002c000 -#define regi_ser_mod0 0xb7020000 -#define regi_ser_mod1 0xb7022000 -#define regi_ser_mod2 0xb7024000 -#define regi_ser_mod3 0xb7026000 -#define regi_smif_stat 0xb700e000 -#define regi_sser0 0xb0022000 -#define regi_sser1 0xb0024000 -#define regi_sser_mod0 0xb700a000 -#define regi_sser_mod1 0xb700c000 -#define regi_strcop 0xb0030000 -#define regi_strmux 0xb003a000 -#define regi_strmux_tst 0xb7040000 -#define regi_tap 0xb7002000 -#define regi_timer 0xb001e000 -#define regi_timer_mod 0xb7034000 -#define regi_trace 0xb0040000 -#define regi_usb0 0xb7028000 -#define regi_usb1 0xb702a000 -#define regi_usb2 0xb702c000 -#define regi_usb3 0xb702e000 -#define regi_usb_dev 0xb7030000 -#define regi_utmi_mod0 0xb7036000 -#define regi_utmi_mod1 0xb7038000 -#endif /* __reg_map_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h deleted file mode 100644 index 10246f49fb28..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __rt_trace_defs_asm_h -#define __rt_trace_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/rt_trace/rtl/rt_regs.r - * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp - * last modfied: Mon Apr 11 16:09:14 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r - * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope rt_trace, type rw */ -#define reg_rt_trace_rw_cfg___en___lsb 0 -#define reg_rt_trace_rw_cfg___en___width 1 -#define reg_rt_trace_rw_cfg___en___bit 0 -#define reg_rt_trace_rw_cfg___mode___lsb 1 -#define reg_rt_trace_rw_cfg___mode___width 1 -#define reg_rt_trace_rw_cfg___mode___bit 1 -#define reg_rt_trace_rw_cfg___owner___lsb 2 -#define reg_rt_trace_rw_cfg___owner___width 1 -#define reg_rt_trace_rw_cfg___owner___bit 2 -#define reg_rt_trace_rw_cfg___wp___lsb 3 -#define reg_rt_trace_rw_cfg___wp___width 1 -#define reg_rt_trace_rw_cfg___wp___bit 3 -#define reg_rt_trace_rw_cfg___stall___lsb 4 -#define reg_rt_trace_rw_cfg___stall___width 1 -#define reg_rt_trace_rw_cfg___stall___bit 4 -#define reg_rt_trace_rw_cfg___wp_start___lsb 8 -#define reg_rt_trace_rw_cfg___wp_start___width 7 -#define reg_rt_trace_rw_cfg___wp_stop___lsb 16 -#define reg_rt_trace_rw_cfg___wp_stop___width 7 -#define reg_rt_trace_rw_cfg_offset 0 - -/* Register rw_tap_ctrl, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0 -#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1 -#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1 -#define reg_rt_trace_rw_tap_ctrl_offset 4 - -/* Register r_tap_stat, scope rt_trace, type r */ -#define reg_rt_trace_r_tap_stat___dav___lsb 0 -#define reg_rt_trace_r_tap_stat___dav___width 1 -#define reg_rt_trace_r_tap_stat___dav___bit 0 -#define reg_rt_trace_r_tap_stat___empty___lsb 1 -#define reg_rt_trace_r_tap_stat___empty___width 1 -#define reg_rt_trace_r_tap_stat___empty___bit 1 -#define reg_rt_trace_r_tap_stat_offset 8 - -/* Register rw_tap_data, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_data_offset 12 - -/* Register rw_tap_hdata, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_hdata___op___lsb 0 -#define reg_rt_trace_rw_tap_hdata___op___width 4 -#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4 -#define reg_rt_trace_rw_tap_hdata___sub_op___width 4 -#define reg_rt_trace_rw_tap_hdata_offset 16 - -/* Register r_redir, scope rt_trace, type r */ -#define reg_rt_trace_r_redir_offset 20 - - -/* Constants */ -#define regk_rt_trace_brk 0x0000000c -#define regk_rt_trace_dbg 0x00000003 -#define regk_rt_trace_dbgdi 0x00000004 -#define regk_rt_trace_dbgdo 0x00000005 -#define regk_rt_trace_gmode 0x00000000 -#define regk_rt_trace_no 0x00000000 -#define regk_rt_trace_nop 0x00000000 -#define regk_rt_trace_normal 0x00000000 -#define regk_rt_trace_rdmem 0x00000007 -#define regk_rt_trace_rdmemb 0x00000009 -#define regk_rt_trace_rdpreg 0x00000002 -#define regk_rt_trace_rdreg 0x00000001 -#define regk_rt_trace_rdsreg 0x00000003 -#define regk_rt_trace_redir 0x00000006 -#define regk_rt_trace_ret 0x0000000b -#define regk_rt_trace_rw_cfg_default 0x00000000 -#define regk_rt_trace_trcfg 0x00000001 -#define regk_rt_trace_wp 0x00000001 -#define regk_rt_trace_wp0 0x00000001 -#define regk_rt_trace_wp1 0x00000002 -#define regk_rt_trace_wp2 0x00000004 -#define regk_rt_trace_wp3 0x00000008 -#define regk_rt_trace_wp4 0x00000010 -#define regk_rt_trace_wp5 0x00000020 -#define regk_rt_trace_wp6 0x00000040 -#define regk_rt_trace_wrmem 0x00000008 -#define regk_rt_trace_wrmemb 0x0000000a -#define regk_rt_trace_wrpreg 0x00000005 -#define regk_rt_trace_wrreg 0x00000004 -#define regk_rt_trace_wrsreg 0x00000006 -#define regk_rt_trace_yes 0x00000001 -#endif /* __rt_trace_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h deleted file mode 100644 index 4a2808bdf390..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h +++ /dev/null @@ -1,359 +0,0 @@ -#ifndef __ser_defs_asm_h -#define __ser_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/ser/rtl/ser_regs.r - * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp - * last modfied: Mon Apr 11 16:09:21 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r - * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tr_ctrl, scope ser, type rw */ -#define reg_ser_rw_tr_ctrl___base_freq___lsb 0 -#define reg_ser_rw_tr_ctrl___base_freq___width 3 -#define reg_ser_rw_tr_ctrl___en___lsb 3 -#define reg_ser_rw_tr_ctrl___en___width 1 -#define reg_ser_rw_tr_ctrl___en___bit 3 -#define reg_ser_rw_tr_ctrl___par___lsb 4 -#define reg_ser_rw_tr_ctrl___par___width 2 -#define reg_ser_rw_tr_ctrl___par_en___lsb 6 -#define reg_ser_rw_tr_ctrl___par_en___width 1 -#define reg_ser_rw_tr_ctrl___par_en___bit 6 -#define reg_ser_rw_tr_ctrl___data_bits___lsb 7 -#define reg_ser_rw_tr_ctrl___data_bits___width 1 -#define reg_ser_rw_tr_ctrl___data_bits___bit 7 -#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8 -#define reg_ser_rw_tr_ctrl___stop_bits___width 1 -#define reg_ser_rw_tr_ctrl___stop_bits___bit 8 -#define reg_ser_rw_tr_ctrl___stop___lsb 9 -#define reg_ser_rw_tr_ctrl___stop___width 1 -#define reg_ser_rw_tr_ctrl___stop___bit 9 -#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10 -#define reg_ser_rw_tr_ctrl___rts_delay___width 3 -#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13 -#define reg_ser_rw_tr_ctrl___rts_setup___width 1 -#define reg_ser_rw_tr_ctrl___rts_setup___bit 13 -#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14 -#define reg_ser_rw_tr_ctrl___auto_rts___width 1 -#define reg_ser_rw_tr_ctrl___auto_rts___bit 14 -#define reg_ser_rw_tr_ctrl___txd___lsb 15 -#define reg_ser_rw_tr_ctrl___txd___width 1 -#define reg_ser_rw_tr_ctrl___txd___bit 15 -#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16 -#define reg_ser_rw_tr_ctrl___auto_cts___width 1 -#define reg_ser_rw_tr_ctrl___auto_cts___bit 16 -#define reg_ser_rw_tr_ctrl_offset 0 - -/* Register rw_tr_dma_en, scope ser, type rw */ -#define reg_ser_rw_tr_dma_en___en___lsb 0 -#define reg_ser_rw_tr_dma_en___en___width 1 -#define reg_ser_rw_tr_dma_en___en___bit 0 -#define reg_ser_rw_tr_dma_en_offset 4 - -/* Register rw_rec_ctrl, scope ser, type rw */ -#define reg_ser_rw_rec_ctrl___base_freq___lsb 0 -#define reg_ser_rw_rec_ctrl___base_freq___width 3 -#define reg_ser_rw_rec_ctrl___en___lsb 3 -#define reg_ser_rw_rec_ctrl___en___width 1 -#define reg_ser_rw_rec_ctrl___en___bit 3 -#define reg_ser_rw_rec_ctrl___par___lsb 4 -#define reg_ser_rw_rec_ctrl___par___width 2 -#define reg_ser_rw_rec_ctrl___par_en___lsb 6 -#define reg_ser_rw_rec_ctrl___par_en___width 1 -#define reg_ser_rw_rec_ctrl___par_en___bit 6 -#define reg_ser_rw_rec_ctrl___data_bits___lsb 7 -#define reg_ser_rw_rec_ctrl___data_bits___width 1 -#define reg_ser_rw_rec_ctrl___data_bits___bit 7 -#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8 -#define reg_ser_rw_rec_ctrl___dma_mode___width 1 -#define reg_ser_rw_rec_ctrl___dma_mode___bit 8 -#define reg_ser_rw_rec_ctrl___dma_err___lsb 9 -#define reg_ser_rw_rec_ctrl___dma_err___width 1 -#define reg_ser_rw_rec_ctrl___dma_err___bit 9 -#define reg_ser_rw_rec_ctrl___sampling___lsb 10 -#define reg_ser_rw_rec_ctrl___sampling___width 1 -#define reg_ser_rw_rec_ctrl___sampling___bit 10 -#define reg_ser_rw_rec_ctrl___timeout___lsb 11 -#define reg_ser_rw_rec_ctrl___timeout___width 3 -#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14 -#define reg_ser_rw_rec_ctrl___auto_eop___width 1 -#define reg_ser_rw_rec_ctrl___auto_eop___bit 14 -#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15 -#define reg_ser_rw_rec_ctrl___half_duplex___width 1 -#define reg_ser_rw_rec_ctrl___half_duplex___bit 15 -#define reg_ser_rw_rec_ctrl___rts_n___lsb 16 -#define reg_ser_rw_rec_ctrl___rts_n___width 1 -#define reg_ser_rw_rec_ctrl___rts_n___bit 16 -#define reg_ser_rw_rec_ctrl___loopback___lsb 17 -#define reg_ser_rw_rec_ctrl___loopback___width 1 -#define reg_ser_rw_rec_ctrl___loopback___bit 17 -#define reg_ser_rw_rec_ctrl_offset 8 - -/* Register rw_tr_baud_div, scope ser, type rw */ -#define reg_ser_rw_tr_baud_div___div___lsb 0 -#define reg_ser_rw_tr_baud_div___div___width 16 -#define reg_ser_rw_tr_baud_div_offset 12 - -/* Register rw_rec_baud_div, scope ser, type rw */ -#define reg_ser_rw_rec_baud_div___div___lsb 0 -#define reg_ser_rw_rec_baud_div___div___width 16 -#define reg_ser_rw_rec_baud_div_offset 16 - -/* Register rw_xoff, scope ser, type rw */ -#define reg_ser_rw_xoff___chr___lsb 0 -#define reg_ser_rw_xoff___chr___width 8 -#define reg_ser_rw_xoff___automatic___lsb 8 -#define reg_ser_rw_xoff___automatic___width 1 -#define reg_ser_rw_xoff___automatic___bit 8 -#define reg_ser_rw_xoff_offset 20 - -/* Register rw_xoff_clr, scope ser, type rw */ -#define reg_ser_rw_xoff_clr___clr___lsb 0 -#define reg_ser_rw_xoff_clr___clr___width 1 -#define reg_ser_rw_xoff_clr___clr___bit 0 -#define reg_ser_rw_xoff_clr_offset 24 - -/* Register rw_dout, scope ser, type rw */ -#define reg_ser_rw_dout___data___lsb 0 -#define reg_ser_rw_dout___data___width 8 -#define reg_ser_rw_dout_offset 28 - -/* Register rs_stat_din, scope ser, type rs */ -#define reg_ser_rs_stat_din___data___lsb 0 -#define reg_ser_rs_stat_din___data___width 8 -#define reg_ser_rs_stat_din___dav___lsb 16 -#define reg_ser_rs_stat_din___dav___width 1 -#define reg_ser_rs_stat_din___dav___bit 16 -#define reg_ser_rs_stat_din___framing_err___lsb 17 -#define reg_ser_rs_stat_din___framing_err___width 1 -#define reg_ser_rs_stat_din___framing_err___bit 17 -#define reg_ser_rs_stat_din___par_err___lsb 18 -#define reg_ser_rs_stat_din___par_err___width 1 -#define reg_ser_rs_stat_din___par_err___bit 18 -#define reg_ser_rs_stat_din___orun___lsb 19 -#define reg_ser_rs_stat_din___orun___width 1 -#define reg_ser_rs_stat_din___orun___bit 19 -#define reg_ser_rs_stat_din___rec_err___lsb 20 -#define reg_ser_rs_stat_din___rec_err___width 1 -#define reg_ser_rs_stat_din___rec_err___bit 20 -#define reg_ser_rs_stat_din___rxd___lsb 21 -#define reg_ser_rs_stat_din___rxd___width 1 -#define reg_ser_rs_stat_din___rxd___bit 21 -#define reg_ser_rs_stat_din___tr_idle___lsb 22 -#define reg_ser_rs_stat_din___tr_idle___width 1 -#define reg_ser_rs_stat_din___tr_idle___bit 22 -#define reg_ser_rs_stat_din___tr_empty___lsb 23 -#define reg_ser_rs_stat_din___tr_empty___width 1 -#define reg_ser_rs_stat_din___tr_empty___bit 23 -#define reg_ser_rs_stat_din___tr_rdy___lsb 24 -#define reg_ser_rs_stat_din___tr_rdy___width 1 -#define reg_ser_rs_stat_din___tr_rdy___bit 24 -#define reg_ser_rs_stat_din___cts_n___lsb 25 -#define reg_ser_rs_stat_din___cts_n___width 1 -#define reg_ser_rs_stat_din___cts_n___bit 25 -#define reg_ser_rs_stat_din___xoff_detect___lsb 26 -#define reg_ser_rs_stat_din___xoff_detect___width 1 -#define reg_ser_rs_stat_din___xoff_detect___bit 26 -#define reg_ser_rs_stat_din___rts_n___lsb 27 -#define reg_ser_rs_stat_din___rts_n___width 1 -#define reg_ser_rs_stat_din___rts_n___bit 27 -#define reg_ser_rs_stat_din___txd___lsb 28 -#define reg_ser_rs_stat_din___txd___width 1 -#define reg_ser_rs_stat_din___txd___bit 28 -#define reg_ser_rs_stat_din_offset 32 - -/* Register r_stat_din, scope ser, type r */ -#define reg_ser_r_stat_din___data___lsb 0 -#define reg_ser_r_stat_din___data___width 8 -#define reg_ser_r_stat_din___dav___lsb 16 -#define reg_ser_r_stat_din___dav___width 1 -#define reg_ser_r_stat_din___dav___bit 16 -#define reg_ser_r_stat_din___framing_err___lsb 17 -#define reg_ser_r_stat_din___framing_err___width 1 -#define reg_ser_r_stat_din___framing_err___bit 17 -#define reg_ser_r_stat_din___par_err___lsb 18 -#define reg_ser_r_stat_din___par_err___width 1 -#define reg_ser_r_stat_din___par_err___bit 18 -#define reg_ser_r_stat_din___orun___lsb 19 -#define reg_ser_r_stat_din___orun___width 1 -#define reg_ser_r_stat_din___orun___bit 19 -#define reg_ser_r_stat_din___rec_err___lsb 20 -#define reg_ser_r_stat_din___rec_err___width 1 -#define reg_ser_r_stat_din___rec_err___bit 20 -#define reg_ser_r_stat_din___rxd___lsb 21 -#define reg_ser_r_stat_din___rxd___width 1 -#define reg_ser_r_stat_din___rxd___bit 21 -#define reg_ser_r_stat_din___tr_idle___lsb 22 -#define reg_ser_r_stat_din___tr_idle___width 1 -#define reg_ser_r_stat_din___tr_idle___bit 22 -#define reg_ser_r_stat_din___tr_empty___lsb 23 -#define reg_ser_r_stat_din___tr_empty___width 1 -#define reg_ser_r_stat_din___tr_empty___bit 23 -#define reg_ser_r_stat_din___tr_rdy___lsb 24 -#define reg_ser_r_stat_din___tr_rdy___width 1 -#define reg_ser_r_stat_din___tr_rdy___bit 24 -#define reg_ser_r_stat_din___cts_n___lsb 25 -#define reg_ser_r_stat_din___cts_n___width 1 -#define reg_ser_r_stat_din___cts_n___bit 25 -#define reg_ser_r_stat_din___xoff_detect___lsb 26 -#define reg_ser_r_stat_din___xoff_detect___width 1 -#define reg_ser_r_stat_din___xoff_detect___bit 26 -#define reg_ser_r_stat_din___rts_n___lsb 27 -#define reg_ser_r_stat_din___rts_n___width 1 -#define reg_ser_r_stat_din___rts_n___bit 27 -#define reg_ser_r_stat_din___txd___lsb 28 -#define reg_ser_r_stat_din___txd___width 1 -#define reg_ser_r_stat_din___txd___bit 28 -#define reg_ser_r_stat_din_offset 36 - -/* Register rw_rec_eop, scope ser, type rw */ -#define reg_ser_rw_rec_eop___set___lsb 0 -#define reg_ser_rw_rec_eop___set___width 1 -#define reg_ser_rw_rec_eop___set___bit 0 -#define reg_ser_rw_rec_eop_offset 40 - -/* Register rw_intr_mask, scope ser, type rw */ -#define reg_ser_rw_intr_mask___tr_rdy___lsb 0 -#define reg_ser_rw_intr_mask___tr_rdy___width 1 -#define reg_ser_rw_intr_mask___tr_rdy___bit 0 -#define reg_ser_rw_intr_mask___tr_empty___lsb 1 -#define reg_ser_rw_intr_mask___tr_empty___width 1 -#define reg_ser_rw_intr_mask___tr_empty___bit 1 -#define reg_ser_rw_intr_mask___tr_idle___lsb 2 -#define reg_ser_rw_intr_mask___tr_idle___width 1 -#define reg_ser_rw_intr_mask___tr_idle___bit 2 -#define reg_ser_rw_intr_mask___dav___lsb 3 -#define reg_ser_rw_intr_mask___dav___width 1 -#define reg_ser_rw_intr_mask___dav___bit 3 -#define reg_ser_rw_intr_mask_offset 44 - -/* Register rw_ack_intr, scope ser, type rw */ -#define reg_ser_rw_ack_intr___tr_rdy___lsb 0 -#define reg_ser_rw_ack_intr___tr_rdy___width 1 -#define reg_ser_rw_ack_intr___tr_rdy___bit 0 -#define reg_ser_rw_ack_intr___tr_empty___lsb 1 -#define reg_ser_rw_ack_intr___tr_empty___width 1 -#define reg_ser_rw_ack_intr___tr_empty___bit 1 -#define reg_ser_rw_ack_intr___tr_idle___lsb 2 -#define reg_ser_rw_ack_intr___tr_idle___width 1 -#define reg_ser_rw_ack_intr___tr_idle___bit 2 -#define reg_ser_rw_ack_intr___dav___lsb 3 -#define reg_ser_rw_ack_intr___dav___width 1 -#define reg_ser_rw_ack_intr___dav___bit 3 -#define reg_ser_rw_ack_intr_offset 48 - -/* Register r_intr, scope ser, type r */ -#define reg_ser_r_intr___tr_rdy___lsb 0 -#define reg_ser_r_intr___tr_rdy___width 1 -#define reg_ser_r_intr___tr_rdy___bit 0 -#define reg_ser_r_intr___tr_empty___lsb 1 -#define reg_ser_r_intr___tr_empty___width 1 -#define reg_ser_r_intr___tr_empty___bit 1 -#define reg_ser_r_intr___tr_idle___lsb 2 -#define reg_ser_r_intr___tr_idle___width 1 -#define reg_ser_r_intr___tr_idle___bit 2 -#define reg_ser_r_intr___dav___lsb 3 -#define reg_ser_r_intr___dav___width 1 -#define reg_ser_r_intr___dav___bit 3 -#define reg_ser_r_intr_offset 52 - -/* Register r_masked_intr, scope ser, type r */ -#define reg_ser_r_masked_intr___tr_rdy___lsb 0 -#define reg_ser_r_masked_intr___tr_rdy___width 1 -#define reg_ser_r_masked_intr___tr_rdy___bit 0 -#define reg_ser_r_masked_intr___tr_empty___lsb 1 -#define reg_ser_r_masked_intr___tr_empty___width 1 -#define reg_ser_r_masked_intr___tr_empty___bit 1 -#define reg_ser_r_masked_intr___tr_idle___lsb 2 -#define reg_ser_r_masked_intr___tr_idle___width 1 -#define reg_ser_r_masked_intr___tr_idle___bit 2 -#define reg_ser_r_masked_intr___dav___lsb 3 -#define reg_ser_r_masked_intr___dav___width 1 -#define reg_ser_r_masked_intr___dav___bit 3 -#define reg_ser_r_masked_intr_offset 56 - - -/* Constants */ -#define regk_ser_active 0x00000000 -#define regk_ser_bits1 0x00000000 -#define regk_ser_bits2 0x00000001 -#define regk_ser_bits7 0x00000001 -#define regk_ser_bits8 0x00000000 -#define regk_ser_del0_5 0x00000000 -#define regk_ser_del1 0x00000001 -#define regk_ser_del1_5 0x00000002 -#define regk_ser_del2 0x00000003 -#define regk_ser_del2_5 0x00000004 -#define regk_ser_del3 0x00000005 -#define regk_ser_del3_5 0x00000006 -#define regk_ser_del4 0x00000007 -#define regk_ser_even 0x00000000 -#define regk_ser_ext 0x00000001 -#define regk_ser_f100 0x00000007 -#define regk_ser_f29_493 0x00000004 -#define regk_ser_f32 0x00000005 -#define regk_ser_f32_768 0x00000006 -#define regk_ser_ignore 0x00000001 -#define regk_ser_inactive 0x00000001 -#define regk_ser_majority 0x00000001 -#define regk_ser_mark 0x00000002 -#define regk_ser_middle 0x00000000 -#define regk_ser_no 0x00000000 -#define regk_ser_odd 0x00000001 -#define regk_ser_off 0x00000000 -#define regk_ser_rw_intr_mask_default 0x00000000 -#define regk_ser_rw_rec_baud_div_default 0x00000000 -#define regk_ser_rw_rec_ctrl_default 0x00010000 -#define regk_ser_rw_tr_baud_div_default 0x00000000 -#define regk_ser_rw_tr_ctrl_default 0x00008000 -#define regk_ser_rw_tr_dma_en_default 0x00000000 -#define regk_ser_rw_xoff_default 0x00000000 -#define regk_ser_space 0x00000003 -#define regk_ser_stop 0x00000000 -#define regk_ser_yes 0x00000001 -#endif /* __ser_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h deleted file mode 100644 index 27d4d91b3abd..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h +++ /dev/null @@ -1,462 +0,0 @@ -#ifndef __sser_defs_asm_h -#define __sser_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/syncser/rtl/sser_regs.r - * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp - * last modfied: Mon Apr 11 16:09:48 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r - * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope sser, type rw */ -#define reg_sser_rw_cfg___clk_div___lsb 0 -#define reg_sser_rw_cfg___clk_div___width 16 -#define reg_sser_rw_cfg___base_freq___lsb 16 -#define reg_sser_rw_cfg___base_freq___width 3 -#define reg_sser_rw_cfg___gate_clk___lsb 19 -#define reg_sser_rw_cfg___gate_clk___width 1 -#define reg_sser_rw_cfg___gate_clk___bit 19 -#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 -#define reg_sser_rw_cfg___clkgate_ctrl___width 1 -#define reg_sser_rw_cfg___clkgate_ctrl___bit 20 -#define reg_sser_rw_cfg___clkgate_in___lsb 21 -#define reg_sser_rw_cfg___clkgate_in___width 1 -#define reg_sser_rw_cfg___clkgate_in___bit 21 -#define reg_sser_rw_cfg___clk_dir___lsb 22 -#define reg_sser_rw_cfg___clk_dir___width 1 -#define reg_sser_rw_cfg___clk_dir___bit 22 -#define reg_sser_rw_cfg___clk_od_mode___lsb 23 -#define reg_sser_rw_cfg___clk_od_mode___width 1 -#define reg_sser_rw_cfg___clk_od_mode___bit 23 -#define reg_sser_rw_cfg___out_clk_pol___lsb 24 -#define reg_sser_rw_cfg___out_clk_pol___width 1 -#define reg_sser_rw_cfg___out_clk_pol___bit 24 -#define reg_sser_rw_cfg___out_clk_src___lsb 25 -#define reg_sser_rw_cfg___out_clk_src___width 2 -#define reg_sser_rw_cfg___clk_in_sel___lsb 27 -#define reg_sser_rw_cfg___clk_in_sel___width 1 -#define reg_sser_rw_cfg___clk_in_sel___bit 27 -#define reg_sser_rw_cfg___hold_pol___lsb 28 -#define reg_sser_rw_cfg___hold_pol___width 1 -#define reg_sser_rw_cfg___hold_pol___bit 28 -#define reg_sser_rw_cfg___prepare___lsb 29 -#define reg_sser_rw_cfg___prepare___width 1 -#define reg_sser_rw_cfg___prepare___bit 29 -#define reg_sser_rw_cfg___en___lsb 30 -#define reg_sser_rw_cfg___en___width 1 -#define reg_sser_rw_cfg___en___bit 30 -#define reg_sser_rw_cfg_offset 0 - -/* Register rw_frm_cfg, scope sser, type rw */ -#define reg_sser_rw_frm_cfg___wordrate___lsb 0 -#define reg_sser_rw_frm_cfg___wordrate___width 10 -#define reg_sser_rw_frm_cfg___rec_delay___lsb 10 -#define reg_sser_rw_frm_cfg___rec_delay___width 3 -#define reg_sser_rw_frm_cfg___tr_delay___lsb 13 -#define reg_sser_rw_frm_cfg___tr_delay___width 3 -#define reg_sser_rw_frm_cfg___early_wend___lsb 16 -#define reg_sser_rw_frm_cfg___early_wend___width 1 -#define reg_sser_rw_frm_cfg___early_wend___bit 16 -#define reg_sser_rw_frm_cfg___level___lsb 17 -#define reg_sser_rw_frm_cfg___level___width 2 -#define reg_sser_rw_frm_cfg___type___lsb 19 -#define reg_sser_rw_frm_cfg___type___width 1 -#define reg_sser_rw_frm_cfg___type___bit 19 -#define reg_sser_rw_frm_cfg___clk_pol___lsb 20 -#define reg_sser_rw_frm_cfg___clk_pol___width 1 -#define reg_sser_rw_frm_cfg___clk_pol___bit 20 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 -#define reg_sser_rw_frm_cfg___clk_src___lsb 22 -#define reg_sser_rw_frm_cfg___clk_src___width 1 -#define reg_sser_rw_frm_cfg___clk_src___bit 22 -#define reg_sser_rw_frm_cfg___out_off___lsb 23 -#define reg_sser_rw_frm_cfg___out_off___width 1 -#define reg_sser_rw_frm_cfg___out_off___bit 23 -#define reg_sser_rw_frm_cfg___out_on___lsb 24 -#define reg_sser_rw_frm_cfg___out_on___width 1 -#define reg_sser_rw_frm_cfg___out_on___bit 24 -#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 -#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 -#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 -#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 -#define reg_sser_rw_frm_cfg___frame_pin_use___width 2 -#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 -#define reg_sser_rw_frm_cfg___status_pin_dir___width 1 -#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 -#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 -#define reg_sser_rw_frm_cfg___status_pin_use___width 2 -#define reg_sser_rw_frm_cfg_offset 4 - -/* Register rw_tr_cfg, scope sser, type rw */ -#define reg_sser_rw_tr_cfg___tr_en___lsb 0 -#define reg_sser_rw_tr_cfg___tr_en___width 1 -#define reg_sser_rw_tr_cfg___tr_en___bit 0 -#define reg_sser_rw_tr_cfg___stop___lsb 1 -#define reg_sser_rw_tr_cfg___stop___width 1 -#define reg_sser_rw_tr_cfg___stop___bit 1 -#define reg_sser_rw_tr_cfg___urun_stop___lsb 2 -#define reg_sser_rw_tr_cfg___urun_stop___width 1 -#define reg_sser_rw_tr_cfg___urun_stop___bit 2 -#define reg_sser_rw_tr_cfg___eop_stop___lsb 3 -#define reg_sser_rw_tr_cfg___eop_stop___width 1 -#define reg_sser_rw_tr_cfg___eop_stop___bit 3 -#define reg_sser_rw_tr_cfg___sample_size___lsb 4 -#define reg_sser_rw_tr_cfg___sample_size___width 6 -#define reg_sser_rw_tr_cfg___sh_dir___lsb 10 -#define reg_sser_rw_tr_cfg___sh_dir___width 1 -#define reg_sser_rw_tr_cfg___sh_dir___bit 10 -#define reg_sser_rw_tr_cfg___clk_pol___lsb 11 -#define reg_sser_rw_tr_cfg___clk_pol___width 1 -#define reg_sser_rw_tr_cfg___clk_pol___bit 11 -#define reg_sser_rw_tr_cfg___clk_src___lsb 12 -#define reg_sser_rw_tr_cfg___clk_src___width 1 -#define reg_sser_rw_tr_cfg___clk_src___bit 12 -#define reg_sser_rw_tr_cfg___use_dma___lsb 13 -#define reg_sser_rw_tr_cfg___use_dma___width 1 -#define reg_sser_rw_tr_cfg___use_dma___bit 13 -#define reg_sser_rw_tr_cfg___mode___lsb 14 -#define reg_sser_rw_tr_cfg___mode___width 2 -#define reg_sser_rw_tr_cfg___frm_src___lsb 16 -#define reg_sser_rw_tr_cfg___frm_src___width 1 -#define reg_sser_rw_tr_cfg___frm_src___bit 16 -#define reg_sser_rw_tr_cfg___use60958___lsb 17 -#define reg_sser_rw_tr_cfg___use60958___width 1 -#define reg_sser_rw_tr_cfg___use60958___bit 17 -#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 -#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 -#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 -#define reg_sser_rw_tr_cfg___rate_ctrl___width 1 -#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 -#define reg_sser_rw_tr_cfg___use_md___lsb 21 -#define reg_sser_rw_tr_cfg___use_md___width 1 -#define reg_sser_rw_tr_cfg___use_md___bit 21 -#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 -#define reg_sser_rw_tr_cfg___dual_i2s___width 1 -#define reg_sser_rw_tr_cfg___dual_i2s___bit 22 -#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 -#define reg_sser_rw_tr_cfg___data_pin_use___width 2 -#define reg_sser_rw_tr_cfg___od_mode___lsb 25 -#define reg_sser_rw_tr_cfg___od_mode___width 1 -#define reg_sser_rw_tr_cfg___od_mode___bit 25 -#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 -#define reg_sser_rw_tr_cfg___bulk_wspace___width 2 -#define reg_sser_rw_tr_cfg_offset 8 - -/* Register rw_rec_cfg, scope sser, type rw */ -#define reg_sser_rw_rec_cfg___rec_en___lsb 0 -#define reg_sser_rw_rec_cfg___rec_en___width 1 -#define reg_sser_rw_rec_cfg___rec_en___bit 0 -#define reg_sser_rw_rec_cfg___force_eop___lsb 1 -#define reg_sser_rw_rec_cfg___force_eop___width 1 -#define reg_sser_rw_rec_cfg___force_eop___bit 1 -#define reg_sser_rw_rec_cfg___stop___lsb 2 -#define reg_sser_rw_rec_cfg___stop___width 1 -#define reg_sser_rw_rec_cfg___stop___bit 2 -#define reg_sser_rw_rec_cfg___orun_stop___lsb 3 -#define reg_sser_rw_rec_cfg___orun_stop___width 1 -#define reg_sser_rw_rec_cfg___orun_stop___bit 3 -#define reg_sser_rw_rec_cfg___eop_stop___lsb 4 -#define reg_sser_rw_rec_cfg___eop_stop___width 1 -#define reg_sser_rw_rec_cfg___eop_stop___bit 4 -#define reg_sser_rw_rec_cfg___sample_size___lsb 5 -#define reg_sser_rw_rec_cfg___sample_size___width 6 -#define reg_sser_rw_rec_cfg___sh_dir___lsb 11 -#define reg_sser_rw_rec_cfg___sh_dir___width 1 -#define reg_sser_rw_rec_cfg___sh_dir___bit 11 -#define reg_sser_rw_rec_cfg___clk_pol___lsb 12 -#define reg_sser_rw_rec_cfg___clk_pol___width 1 -#define reg_sser_rw_rec_cfg___clk_pol___bit 12 -#define reg_sser_rw_rec_cfg___clk_src___lsb 13 -#define reg_sser_rw_rec_cfg___clk_src___width 1 -#define reg_sser_rw_rec_cfg___clk_src___bit 13 -#define reg_sser_rw_rec_cfg___use_dma___lsb 14 -#define reg_sser_rw_rec_cfg___use_dma___width 1 -#define reg_sser_rw_rec_cfg___use_dma___bit 14 -#define reg_sser_rw_rec_cfg___mode___lsb 15 -#define reg_sser_rw_rec_cfg___mode___width 2 -#define reg_sser_rw_rec_cfg___frm_src___lsb 17 -#define reg_sser_rw_rec_cfg___frm_src___width 2 -#define reg_sser_rw_rec_cfg___use60958___lsb 19 -#define reg_sser_rw_rec_cfg___use60958___width 1 -#define reg_sser_rw_rec_cfg___use60958___bit 19 -#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 -#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 -#define reg_sser_rw_rec_cfg___slave2_en___lsb 25 -#define reg_sser_rw_rec_cfg___slave2_en___width 1 -#define reg_sser_rw_rec_cfg___slave2_en___bit 25 -#define reg_sser_rw_rec_cfg___slave3_en___lsb 26 -#define reg_sser_rw_rec_cfg___slave3_en___width 1 -#define reg_sser_rw_rec_cfg___slave3_en___bit 26 -#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 -#define reg_sser_rw_rec_cfg___fifo_thr___width 2 -#define reg_sser_rw_rec_cfg_offset 12 - -/* Register rw_tr_data, scope sser, type rw */ -#define reg_sser_rw_tr_data___data___lsb 0 -#define reg_sser_rw_tr_data___data___width 16 -#define reg_sser_rw_tr_data___md___lsb 16 -#define reg_sser_rw_tr_data___md___width 1 -#define reg_sser_rw_tr_data___md___bit 16 -#define reg_sser_rw_tr_data_offset 16 - -/* Register r_rec_data, scope sser, type r */ -#define reg_sser_r_rec_data___data___lsb 0 -#define reg_sser_r_rec_data___data___width 16 -#define reg_sser_r_rec_data___md___lsb 16 -#define reg_sser_r_rec_data___md___width 1 -#define reg_sser_r_rec_data___md___bit 16 -#define reg_sser_r_rec_data___ext_clk___lsb 17 -#define reg_sser_r_rec_data___ext_clk___width 1 -#define reg_sser_r_rec_data___ext_clk___bit 17 -#define reg_sser_r_rec_data___status_in___lsb 18 -#define reg_sser_r_rec_data___status_in___width 1 -#define reg_sser_r_rec_data___status_in___bit 18 -#define reg_sser_r_rec_data___frame_in___lsb 19 -#define reg_sser_r_rec_data___frame_in___width 1 -#define reg_sser_r_rec_data___frame_in___bit 19 -#define reg_sser_r_rec_data___din___lsb 20 -#define reg_sser_r_rec_data___din___width 1 -#define reg_sser_r_rec_data___din___bit 20 -#define reg_sser_r_rec_data___data_in___lsb 21 -#define reg_sser_r_rec_data___data_in___width 1 -#define reg_sser_r_rec_data___data_in___bit 21 -#define reg_sser_r_rec_data___clk_in___lsb 22 -#define reg_sser_r_rec_data___clk_in___width 1 -#define reg_sser_r_rec_data___clk_in___bit 22 -#define reg_sser_r_rec_data_offset 20 - -/* Register rw_extra, scope sser, type rw */ -#define reg_sser_rw_extra___clkoff_cycles___lsb 0 -#define reg_sser_rw_extra___clkoff_cycles___width 20 -#define reg_sser_rw_extra___clkoff_en___lsb 20 -#define reg_sser_rw_extra___clkoff_en___width 1 -#define reg_sser_rw_extra___clkoff_en___bit 20 -#define reg_sser_rw_extra___clkon_en___lsb 21 -#define reg_sser_rw_extra___clkon_en___width 1 -#define reg_sser_rw_extra___clkon_en___bit 21 -#define reg_sser_rw_extra___dout_delay___lsb 22 -#define reg_sser_rw_extra___dout_delay___width 5 -#define reg_sser_rw_extra_offset 24 - -/* Register rw_intr_mask, scope sser, type rw */ -#define reg_sser_rw_intr_mask___trdy___lsb 0 -#define reg_sser_rw_intr_mask___trdy___width 1 -#define reg_sser_rw_intr_mask___trdy___bit 0 -#define reg_sser_rw_intr_mask___rdav___lsb 1 -#define reg_sser_rw_intr_mask___rdav___width 1 -#define reg_sser_rw_intr_mask___rdav___bit 1 -#define reg_sser_rw_intr_mask___tidle___lsb 2 -#define reg_sser_rw_intr_mask___tidle___width 1 -#define reg_sser_rw_intr_mask___tidle___bit 2 -#define reg_sser_rw_intr_mask___rstop___lsb 3 -#define reg_sser_rw_intr_mask___rstop___width 1 -#define reg_sser_rw_intr_mask___rstop___bit 3 -#define reg_sser_rw_intr_mask___urun___lsb 4 -#define reg_sser_rw_intr_mask___urun___width 1 -#define reg_sser_rw_intr_mask___urun___bit 4 -#define reg_sser_rw_intr_mask___orun___lsb 5 -#define reg_sser_rw_intr_mask___orun___width 1 -#define reg_sser_rw_intr_mask___orun___bit 5 -#define reg_sser_rw_intr_mask___md_rec___lsb 6 -#define reg_sser_rw_intr_mask___md_rec___width 1 -#define reg_sser_rw_intr_mask___md_rec___bit 6 -#define reg_sser_rw_intr_mask___md_sent___lsb 7 -#define reg_sser_rw_intr_mask___md_sent___width 1 -#define reg_sser_rw_intr_mask___md_sent___bit 7 -#define reg_sser_rw_intr_mask___r958err___lsb 8 -#define reg_sser_rw_intr_mask___r958err___width 1 -#define reg_sser_rw_intr_mask___r958err___bit 8 -#define reg_sser_rw_intr_mask_offset 28 - -/* Register rw_ack_intr, scope sser, type rw */ -#define reg_sser_rw_ack_intr___trdy___lsb 0 -#define reg_sser_rw_ack_intr___trdy___width 1 -#define reg_sser_rw_ack_intr___trdy___bit 0 -#define reg_sser_rw_ack_intr___rdav___lsb 1 -#define reg_sser_rw_ack_intr___rdav___width 1 -#define reg_sser_rw_ack_intr___rdav___bit 1 -#define reg_sser_rw_ack_intr___tidle___lsb 2 -#define reg_sser_rw_ack_intr___tidle___width 1 -#define reg_sser_rw_ack_intr___tidle___bit 2 -#define reg_sser_rw_ack_intr___rstop___lsb 3 -#define reg_sser_rw_ack_intr___rstop___width 1 -#define reg_sser_rw_ack_intr___rstop___bit 3 -#define reg_sser_rw_ack_intr___urun___lsb 4 -#define reg_sser_rw_ack_intr___urun___width 1 -#define reg_sser_rw_ack_intr___urun___bit 4 -#define reg_sser_rw_ack_intr___orun___lsb 5 -#define reg_sser_rw_ack_intr___orun___width 1 -#define reg_sser_rw_ack_intr___orun___bit 5 -#define reg_sser_rw_ack_intr___md_rec___lsb 6 -#define reg_sser_rw_ack_intr___md_rec___width 1 -#define reg_sser_rw_ack_intr___md_rec___bit 6 -#define reg_sser_rw_ack_intr___md_sent___lsb 7 -#define reg_sser_rw_ack_intr___md_sent___width 1 -#define reg_sser_rw_ack_intr___md_sent___bit 7 -#define reg_sser_rw_ack_intr___r958err___lsb 8 -#define reg_sser_rw_ack_intr___r958err___width 1 -#define reg_sser_rw_ack_intr___r958err___bit 8 -#define reg_sser_rw_ack_intr_offset 32 - -/* Register r_intr, scope sser, type r */ -#define reg_sser_r_intr___trdy___lsb 0 -#define reg_sser_r_intr___trdy___width 1 -#define reg_sser_r_intr___trdy___bit 0 -#define reg_sser_r_intr___rdav___lsb 1 -#define reg_sser_r_intr___rdav___width 1 -#define reg_sser_r_intr___rdav___bit 1 -#define reg_sser_r_intr___tidle___lsb 2 -#define reg_sser_r_intr___tidle___width 1 -#define reg_sser_r_intr___tidle___bit 2 -#define reg_sser_r_intr___rstop___lsb 3 -#define reg_sser_r_intr___rstop___width 1 -#define reg_sser_r_intr___rstop___bit 3 -#define reg_sser_r_intr___urun___lsb 4 -#define reg_sser_r_intr___urun___width 1 -#define reg_sser_r_intr___urun___bit 4 -#define reg_sser_r_intr___orun___lsb 5 -#define reg_sser_r_intr___orun___width 1 -#define reg_sser_r_intr___orun___bit 5 -#define reg_sser_r_intr___md_rec___lsb 6 -#define reg_sser_r_intr___md_rec___width 1 -#define reg_sser_r_intr___md_rec___bit 6 -#define reg_sser_r_intr___md_sent___lsb 7 -#define reg_sser_r_intr___md_sent___width 1 -#define reg_sser_r_intr___md_sent___bit 7 -#define reg_sser_r_intr___r958err___lsb 8 -#define reg_sser_r_intr___r958err___width 1 -#define reg_sser_r_intr___r958err___bit 8 -#define reg_sser_r_intr_offset 36 - -/* Register r_masked_intr, scope sser, type r */ -#define reg_sser_r_masked_intr___trdy___lsb 0 -#define reg_sser_r_masked_intr___trdy___width 1 -#define reg_sser_r_masked_intr___trdy___bit 0 -#define reg_sser_r_masked_intr___rdav___lsb 1 -#define reg_sser_r_masked_intr___rdav___width 1 -#define reg_sser_r_masked_intr___rdav___bit 1 -#define reg_sser_r_masked_intr___tidle___lsb 2 -#define reg_sser_r_masked_intr___tidle___width 1 -#define reg_sser_r_masked_intr___tidle___bit 2 -#define reg_sser_r_masked_intr___rstop___lsb 3 -#define reg_sser_r_masked_intr___rstop___width 1 -#define reg_sser_r_masked_intr___rstop___bit 3 -#define reg_sser_r_masked_intr___urun___lsb 4 -#define reg_sser_r_masked_intr___urun___width 1 -#define reg_sser_r_masked_intr___urun___bit 4 -#define reg_sser_r_masked_intr___orun___lsb 5 -#define reg_sser_r_masked_intr___orun___width 1 -#define reg_sser_r_masked_intr___orun___bit 5 -#define reg_sser_r_masked_intr___md_rec___lsb 6 -#define reg_sser_r_masked_intr___md_rec___width 1 -#define reg_sser_r_masked_intr___md_rec___bit 6 -#define reg_sser_r_masked_intr___md_sent___lsb 7 -#define reg_sser_r_masked_intr___md_sent___width 1 -#define reg_sser_r_masked_intr___md_sent___bit 7 -#define reg_sser_r_masked_intr___r958err___lsb 8 -#define reg_sser_r_masked_intr___r958err___width 1 -#define reg_sser_r_masked_intr___r958err___bit 8 -#define reg_sser_r_masked_intr_offset 40 - - -/* Constants */ -#define regk_sser_both 0x00000002 -#define regk_sser_bulk 0x00000001 -#define regk_sser_clk100 0x00000000 -#define regk_sser_clk_in 0x00000000 -#define regk_sser_const0 0x00000003 -#define regk_sser_dout 0x00000002 -#define regk_sser_edge 0x00000000 -#define regk_sser_ext 0x00000001 -#define regk_sser_ext_clk 0x00000001 -#define regk_sser_f100 0x00000000 -#define regk_sser_f29_493 0x00000004 -#define regk_sser_f32 0x00000005 -#define regk_sser_f32_768 0x00000006 -#define regk_sser_frm 0x00000003 -#define regk_sser_gio0 0x00000000 -#define regk_sser_gio1 0x00000001 -#define regk_sser_hispeed 0x00000001 -#define regk_sser_hold 0x00000002 -#define regk_sser_in 0x00000000 -#define regk_sser_inf 0x00000003 -#define regk_sser_intern 0x00000000 -#define regk_sser_intern_clk 0x00000001 -#define regk_sser_intern_tb 0x00000000 -#define regk_sser_iso 0x00000000 -#define regk_sser_level 0x00000001 -#define regk_sser_lospeed 0x00000000 -#define regk_sser_lsbfirst 0x00000000 -#define regk_sser_msbfirst 0x00000001 -#define regk_sser_neg 0x00000001 -#define regk_sser_neg_lo 0x00000000 -#define regk_sser_no 0x00000000 -#define regk_sser_no_clk 0x00000007 -#define regk_sser_nojitter 0x00000002 -#define regk_sser_out 0x00000001 -#define regk_sser_pos 0x00000000 -#define regk_sser_pos_hi 0x00000001 -#define regk_sser_rec 0x00000000 -#define regk_sser_rw_cfg_default 0x00000000 -#define regk_sser_rw_extra_default 0x00000000 -#define regk_sser_rw_frm_cfg_default 0x00000000 -#define regk_sser_rw_intr_mask_default 0x00000000 -#define regk_sser_rw_rec_cfg_default 0x00000000 -#define regk_sser_rw_tr_cfg_default 0x01800000 -#define regk_sser_rw_tr_data_default 0x00000000 -#define regk_sser_thr16 0x00000001 -#define regk_sser_thr32 0x00000002 -#define regk_sser_thr8 0x00000000 -#define regk_sser_tr 0x00000001 -#define regk_sser_ts_out 0x00000003 -#define regk_sser_tx_bulk 0x00000002 -#define regk_sser_wiresave 0x00000002 -#define regk_sser_yes 0x00000001 -#endif /* __sser_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h deleted file mode 100644 index 55083e6aec93..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef __strcop_defs_asm_h -#define __strcop_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/strcop/rtl/strcop_regs.r - * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp - * last modfied: Mon Apr 11 16:09:38 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r - * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope strcop, type rw */ -#define reg_strcop_rw_cfg___td3___lsb 0 -#define reg_strcop_rw_cfg___td3___width 1 -#define reg_strcop_rw_cfg___td3___bit 0 -#define reg_strcop_rw_cfg___td2___lsb 1 -#define reg_strcop_rw_cfg___td2___width 1 -#define reg_strcop_rw_cfg___td2___bit 1 -#define reg_strcop_rw_cfg___td1___lsb 2 -#define reg_strcop_rw_cfg___td1___width 1 -#define reg_strcop_rw_cfg___td1___bit 2 -#define reg_strcop_rw_cfg___ipend___lsb 3 -#define reg_strcop_rw_cfg___ipend___width 1 -#define reg_strcop_rw_cfg___ipend___bit 3 -#define reg_strcop_rw_cfg___ignore_sync___lsb 4 -#define reg_strcop_rw_cfg___ignore_sync___width 1 -#define reg_strcop_rw_cfg___ignore_sync___bit 4 -#define reg_strcop_rw_cfg___en___lsb 5 -#define reg_strcop_rw_cfg___en___width 1 -#define reg_strcop_rw_cfg___en___bit 5 -#define reg_strcop_rw_cfg_offset 0 - - -/* Constants */ -#define regk_strcop_big 0x00000001 -#define regk_strcop_d 0x00000001 -#define regk_strcop_e 0x00000000 -#define regk_strcop_little 0x00000000 -#define regk_strcop_rw_cfg_default 0x00000002 -#endif /* __strcop_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h deleted file mode 100644 index 69b299920f71..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h +++ /dev/null @@ -1,100 +0,0 @@ -#ifndef __strmux_defs_asm_h -#define __strmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope strmux, type rw */ -#define reg_strmux_rw_cfg___dma0___lsb 0 -#define reg_strmux_rw_cfg___dma0___width 3 -#define reg_strmux_rw_cfg___dma1___lsb 3 -#define reg_strmux_rw_cfg___dma1___width 3 -#define reg_strmux_rw_cfg___dma2___lsb 6 -#define reg_strmux_rw_cfg___dma2___width 3 -#define reg_strmux_rw_cfg___dma3___lsb 9 -#define reg_strmux_rw_cfg___dma3___width 3 -#define reg_strmux_rw_cfg___dma4___lsb 12 -#define reg_strmux_rw_cfg___dma4___width 3 -#define reg_strmux_rw_cfg___dma5___lsb 15 -#define reg_strmux_rw_cfg___dma5___width 3 -#define reg_strmux_rw_cfg___dma6___lsb 18 -#define reg_strmux_rw_cfg___dma6___width 3 -#define reg_strmux_rw_cfg___dma7___lsb 21 -#define reg_strmux_rw_cfg___dma7___width 3 -#define reg_strmux_rw_cfg___dma8___lsb 24 -#define reg_strmux_rw_cfg___dma8___width 3 -#define reg_strmux_rw_cfg___dma9___lsb 27 -#define reg_strmux_rw_cfg___dma9___width 3 -#define reg_strmux_rw_cfg_offset 0 - - -/* Constants */ -#define regk_strmux_ata 0x00000003 -#define regk_strmux_eth0 0x00000001 -#define regk_strmux_eth1 0x00000004 -#define regk_strmux_ext0 0x00000001 -#define regk_strmux_ext1 0x00000001 -#define regk_strmux_ext2 0x00000001 -#define regk_strmux_ext3 0x00000001 -#define regk_strmux_iop0 0x00000002 -#define regk_strmux_iop1 0x00000001 -#define regk_strmux_off 0x00000000 -#define regk_strmux_p21 0x00000004 -#define regk_strmux_rw_cfg_default 0x00000000 -#define regk_strmux_ser0 0x00000002 -#define regk_strmux_ser1 0x00000002 -#define regk_strmux_ser2 0x00000004 -#define regk_strmux_ser3 0x00000003 -#define regk_strmux_sser0 0x00000003 -#define regk_strmux_sser1 0x00000003 -#define regk_strmux_strcop 0x00000002 -#endif /* __strmux_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index 43146021fc16..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,229 +0,0 @@ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/ata_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/ata_defs.h deleted file mode 100644 index 43b6643ff0d3..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/ata_defs.h +++ /dev/null @@ -1,222 +0,0 @@ -#ifndef __ata_defs_h -#define __ata_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ata/rtl/ata_regs.r - * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp - * last modfied: Mon Apr 11 16:06:25 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r - * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ata */ - -/* Register rw_ctrl0, scope ata, type rw */ -typedef struct { - unsigned int pio_hold : 6; - unsigned int pio_strb : 6; - unsigned int pio_setup : 6; - unsigned int dma_hold : 6; - unsigned int dma_strb : 6; - unsigned int rst : 1; - unsigned int en : 1; -} reg_ata_rw_ctrl0; -#define REG_RD_ADDR_ata_rw_ctrl0 12 -#define REG_WR_ADDR_ata_rw_ctrl0 12 - -/* Register rw_ctrl1, scope ata, type rw */ -typedef struct { - unsigned int udma_tcyc : 4; - unsigned int udma_tdvs : 4; - unsigned int dummy1 : 24; -} reg_ata_rw_ctrl1; -#define REG_RD_ADDR_ata_rw_ctrl1 16 -#define REG_WR_ADDR_ata_rw_ctrl1 16 - -/* Register rw_ctrl2, scope ata, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 3; - unsigned int dma_size : 1; - unsigned int multi : 1; - unsigned int hsh : 2; - unsigned int trf_mode : 1; - unsigned int rw : 1; - unsigned int addr : 3; - unsigned int cs0 : 1; - unsigned int cs1 : 1; - unsigned int sel : 2; -} reg_ata_rw_ctrl2; -#define REG_RD_ADDR_ata_rw_ctrl2 0 -#define REG_WR_ADDR_ata_rw_ctrl2 0 - -/* Register rs_stat_data, scope ata, type rs */ -typedef struct { - unsigned int data : 16; - unsigned int dav : 1; - unsigned int busy : 1; - unsigned int dummy1 : 14; -} reg_ata_rs_stat_data; -#define REG_RD_ADDR_ata_rs_stat_data 4 - -/* Register r_stat_data, scope ata, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dav : 1; - unsigned int busy : 1; - unsigned int dummy1 : 14; -} reg_ata_r_stat_data; -#define REG_RD_ADDR_ata_r_stat_data 8 - -/* Register rw_trf_cnt, scope ata, type rw */ -typedef struct { - unsigned int cnt : 17; - unsigned int dummy1 : 15; -} reg_ata_rw_trf_cnt; -#define REG_RD_ADDR_ata_rw_trf_cnt 20 -#define REG_WR_ADDR_ata_rw_trf_cnt 20 - -/* Register r_stat_misc, scope ata, type r */ -typedef struct { - unsigned int crc : 16; - unsigned int dummy1 : 16; -} reg_ata_r_stat_misc; -#define REG_RD_ADDR_ata_r_stat_misc 24 - -/* Register rw_intr_mask, scope ata, type rw */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_rw_intr_mask; -#define REG_RD_ADDR_ata_rw_intr_mask 28 -#define REG_WR_ADDR_ata_rw_intr_mask 28 - -/* Register rw_ack_intr, scope ata, type rw */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_rw_ack_intr; -#define REG_RD_ADDR_ata_rw_ack_intr 32 -#define REG_WR_ADDR_ata_rw_ack_intr 32 - -/* Register r_intr, scope ata, type r */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_r_intr; -#define REG_RD_ADDR_ata_r_intr 36 - -/* Register r_masked_intr, scope ata, type r */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_r_masked_intr; -#define REG_RD_ADDR_ata_r_masked_intr 40 - - -/* Constants */ -enum { - regk_ata_active = 0x00000001, - regk_ata_byte = 0x00000001, - regk_ata_data = 0x00000001, - regk_ata_dma = 0x00000001, - regk_ata_inactive = 0x00000000, - regk_ata_no = 0x00000000, - regk_ata_nodata = 0x00000000, - regk_ata_pio = 0x00000000, - regk_ata_rd = 0x00000001, - regk_ata_reg = 0x00000000, - regk_ata_rw_ctrl0_default = 0x00000000, - regk_ata_rw_ctrl2_default = 0x00000000, - regk_ata_rw_intr_mask_default = 0x00000000, - regk_ata_udma = 0x00000002, - regk_ata_word = 0x00000000, - regk_ata_wr = 0x00000000, - regk_ata_yes = 0x00000001 -}; -#endif /* __ata_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/bif_core_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/bif_core_defs.h deleted file mode 100644 index a56608b50359..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/bif_core_defs.h +++ /dev/null @@ -1,284 +0,0 @@ -#ifndef __bif_core_defs_h -#define __bif_core_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_core */ - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp1_cfg; -#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 -#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp2_cfg; -#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 -#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 2; - unsigned int gated_csp0 : 2; - unsigned int gated_csp1 : 2; - unsigned int gated_csp2 : 2; - unsigned int gated_csp3 : 2; -} reg_bif_core_rw_grp3_cfg; -#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 -#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 4; - unsigned int gated_csp4 : 2; - unsigned int gated_csp5 : 2; - unsigned int gated_csp6 : 2; -} reg_bif_core_rw_grp4_cfg; -#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 -#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int grp_sel : 5; - unsigned int dummy1 : 12; -} reg_bif_core_rw_sdram_cfg_grp0; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int dummy1 : 17; -} reg_bif_core_rw_sdram_cfg_grp1; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -typedef struct { - unsigned int cl : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int rc : 2; - unsigned int dpl : 2; - unsigned int pde : 1; - unsigned int ref : 2; - unsigned int cpd : 1; - unsigned int sdcke : 1; - unsigned int sdclk : 1; - unsigned int dummy1 : 13; -} reg_bif_core_rw_sdram_timing; -#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 -#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -typedef struct { - unsigned int cmd : 3; - unsigned int mrs_data : 15; - unsigned int dummy1 : 14; -} reg_bif_core_rw_sdram_cmd; -#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 -#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_rs_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_r_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 - - -/* Constants */ -enum { - regk_bif_core_bank2 = 0x00000000, - regk_bif_core_bank4 = 0x00000001, - regk_bif_core_bit10 = 0x0000000a, - regk_bif_core_bit11 = 0x0000000b, - regk_bif_core_bit12 = 0x0000000c, - regk_bif_core_bit13 = 0x0000000d, - regk_bif_core_bit14 = 0x0000000e, - regk_bif_core_bit15 = 0x0000000f, - regk_bif_core_bit16 = 0x00000010, - regk_bif_core_bit17 = 0x00000011, - regk_bif_core_bit18 = 0x00000012, - regk_bif_core_bit19 = 0x00000013, - regk_bif_core_bit20 = 0x00000014, - regk_bif_core_bit21 = 0x00000015, - regk_bif_core_bit22 = 0x00000016, - regk_bif_core_bit23 = 0x00000017, - regk_bif_core_bit24 = 0x00000018, - regk_bif_core_bit25 = 0x00000019, - regk_bif_core_bit26 = 0x0000001a, - regk_bif_core_bit27 = 0x0000001b, - regk_bif_core_bit28 = 0x0000001c, - regk_bif_core_bit29 = 0x0000001d, - regk_bif_core_bit9 = 0x00000009, - regk_bif_core_bw16 = 0x00000001, - regk_bif_core_bw32 = 0x00000000, - regk_bif_core_bwe = 0x00000000, - regk_bif_core_cwe = 0x00000001, - regk_bif_core_e15us = 0x00000001, - regk_bif_core_e7800ns = 0x00000002, - regk_bif_core_grp0 = 0x00000000, - regk_bif_core_grp1 = 0x00000001, - regk_bif_core_mrs = 0x00000003, - regk_bif_core_no = 0x00000000, - regk_bif_core_none = 0x00000000, - regk_bif_core_nop = 0x00000000, - regk_bif_core_off = 0x00000000, - regk_bif_core_pre = 0x00000002, - regk_bif_core_r_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rd = 0x00000002, - regk_bif_core_ref = 0x00000001, - regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rw_grp1_cfg_default = 0x000006cf, - regk_bif_core_rw_grp2_cfg_default = 0x000006cf, - regk_bif_core_rw_grp3_cfg_default = 0x000006cf, - regk_bif_core_rw_grp4_cfg_default = 0x000006cf, - regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, - regk_bif_core_slf = 0x00000004, - regk_bif_core_wr = 0x00000001, - regk_bif_core_yes = 0x00000001 -}; -#endif /* __bif_core_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h deleted file mode 100644 index b931c1aab679..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h +++ /dev/null @@ -1,473 +0,0 @@ -#ifndef __bif_dma_defs_h -#define __bif_dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_dma */ - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch0_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 -#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch0_addr; -#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 -#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch0_start; -#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 -#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch0_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 -#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch0_stat; -#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch1_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 -#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch1_addr; -#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 -#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch1_start; -#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 -#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch1_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 -#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch1_stat; -#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch2_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 -#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch2_addr; -#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 -#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch2_start; -#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 -#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch2_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 -#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch2_stat; -#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch3_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 -#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch3_addr; -#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 -#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch3_start; -#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 -#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch3_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 -#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch3_stat; -#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_intr_mask; -#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 -#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_ack_intr; -#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 -#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 - -/* Register r_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_intr; -#define REG_RD_ADDR_bif_dma_r_intr 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_masked_intr; -#define REG_RD_ADDR_bif_dma_r_masked_intr 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin0_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 -#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin1_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 -#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin2_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 -#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin3_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 -#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin4_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 -#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin5_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 -#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin6_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 -#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin7_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 -#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -typedef struct { - unsigned int pin0 : 1; - unsigned int pin1 : 1; - unsigned int pin2 : 1; - unsigned int pin3 : 1; - unsigned int pin4 : 1; - unsigned int pin5 : 1; - unsigned int pin6 : 1; - unsigned int pin7 : 1; - unsigned int dummy1 : 24; -} reg_bif_dma_r_pin_stat; -#define REG_RD_ADDR_bif_dma_r_pin_stat 192 - - -/* Constants */ -enum { - regk_bif_dma_as_master = 0x00000001, - regk_bif_dma_as_slave = 0x00000001, - regk_bif_dma_burst1 = 0x00000000, - regk_bif_dma_burst8 = 0x00000001, - regk_bif_dma_bw16 = 0x00000001, - regk_bif_dma_bw32 = 0x00000002, - regk_bif_dma_bw8 = 0x00000000, - regk_bif_dma_dack = 0x00000006, - regk_bif_dma_dack_inv = 0x00000007, - regk_bif_dma_force = 0x00000001, - regk_bif_dma_hi = 0x00000003, - regk_bif_dma_inv = 0x00000003, - regk_bif_dma_lo = 0x00000002, - regk_bif_dma_master = 0x00000001, - regk_bif_dma_no = 0x00000000, - regk_bif_dma_norm = 0x00000002, - regk_bif_dma_off = 0x00000000, - regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch0_start_default = 0x00000000, - regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch1_start_default = 0x00000000, - regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch2_start_default = 0x00000000, - regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch3_start_default = 0x00000000, - regk_bif_dma_rw_intr_mask_default = 0x00000000, - regk_bif_dma_rw_pin0_cfg_default = 0x00000000, - regk_bif_dma_rw_pin1_cfg_default = 0x00000000, - regk_bif_dma_rw_pin2_cfg_default = 0x00000000, - regk_bif_dma_rw_pin3_cfg_default = 0x00000000, - regk_bif_dma_rw_pin4_cfg_default = 0x00000000, - regk_bif_dma_rw_pin5_cfg_default = 0x00000000, - regk_bif_dma_rw_pin6_cfg_default = 0x00000000, - regk_bif_dma_rw_pin7_cfg_default = 0x00000000, - regk_bif_dma_slave = 0x00000002, - regk_bif_dma_sreq = 0x00000006, - regk_bif_dma_sreq_inv = 0x00000007, - regk_bif_dma_tc = 0x00000004, - regk_bif_dma_tc_inv = 0x00000005, - regk_bif_dma_yes = 0x00000001 -}; -#endif /* __bif_dma_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h deleted file mode 100644 index d18fc3c9f569..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __bif_slave_defs_h -#define __bif_slave_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_slave */ - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int slave_id : 3; - unsigned int use_slave_id : 1; - unsigned int boot_rdy : 1; - unsigned int loopback : 1; - unsigned int dis : 1; - unsigned int dummy1 : 25; -} reg_bif_slave_rw_slave_cfg; -#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 -#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -typedef struct { - unsigned int ch0_mode : 1; - unsigned int ch1_mode : 1; - unsigned int ch2_mode : 1; - unsigned int ch3_mode : 1; - unsigned int dummy1 : 28; -} reg_bif_slave_r_slave_mode; -#define REG_RD_ADDR_bif_slave_r_slave_mode 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch0_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 -#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch1_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 -#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch2_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 -#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch3_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 -#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int brin_mode : 1; - unsigned int brout_mode : 3; - unsigned int bg_mode : 3; - unsigned int release : 2; - unsigned int acquire : 1; - unsigned int settle_time : 2; - unsigned int dram_ctrl : 1; - unsigned int dummy1 : 19; -} reg_bif_slave_rw_arb_cfg; -#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 -#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -typedef struct { - unsigned int init_mode : 1; - unsigned int mode : 1; - unsigned int brin : 1; - unsigned int brout : 1; - unsigned int bg : 1; - unsigned int dummy1 : 27; -} reg_bif_slave_r_arb_stat; -#define REG_RD_ADDR_bif_slave_r_arb_stat 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_intr_mask; -#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 -#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_ack_intr; -#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 -#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 - -/* Register r_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_intr; -#define REG_RD_ADDR_bif_slave_r_intr 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_masked_intr; -#define REG_RD_ADDR_bif_slave_r_masked_intr 76 - - -/* Constants */ -enum { - regk_bif_slave_active_hi = 0x00000003, - regk_bif_slave_active_lo = 0x00000002, - regk_bif_slave_addr = 0x00000000, - regk_bif_slave_always = 0x00000001, - regk_bif_slave_at_idle = 0x00000002, - regk_bif_slave_burst_end = 0x00000003, - regk_bif_slave_dma = 0x00000001, - regk_bif_slave_hi = 0x00000003, - regk_bif_slave_inv = 0x00000001, - regk_bif_slave_lo = 0x00000002, - regk_bif_slave_local = 0x00000001, - regk_bif_slave_master = 0x00000000, - regk_bif_slave_mode_reg = 0x00000001, - regk_bif_slave_no = 0x00000000, - regk_bif_slave_norm = 0x00000000, - regk_bif_slave_on_access = 0x00000000, - regk_bif_slave_rw_arb_cfg_default = 0x00000000, - regk_bif_slave_rw_ch0_cfg_default = 0x00000000, - regk_bif_slave_rw_ch1_cfg_default = 0x00000000, - regk_bif_slave_rw_ch2_cfg_default = 0x00000000, - regk_bif_slave_rw_ch3_cfg_default = 0x00000000, - regk_bif_slave_rw_intr_mask_default = 0x00000000, - regk_bif_slave_rw_slave_cfg_default = 0x00000000, - regk_bif_slave_shared = 0x00000000, - regk_bif_slave_slave = 0x00000001, - regk_bif_slave_t0ns = 0x00000003, - regk_bif_slave_t10ns = 0x00000002, - regk_bif_slave_t20ns = 0x00000003, - regk_bif_slave_t30ns = 0x00000002, - regk_bif_slave_t40ns = 0x00000001, - regk_bif_slave_t50ns = 0x00000000, - regk_bif_slave_yes = 0x00000001, - regk_bif_slave_z = 0x00000004 -}; -#endif /* __bif_slave_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/config_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/config_defs.h deleted file mode 100644 index 45457a4e3817..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/config_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __config_defs_h -#define __config_defs_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r - * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope config */ - -/* Register r_bootsel, scope config, type r */ -typedef struct { - unsigned int boot_mode : 3; - unsigned int full_duplex : 1; - unsigned int user : 1; - unsigned int pll : 1; - unsigned int flash_bw : 1; - unsigned int dummy1 : 25; -} reg_config_r_bootsel; -#define REG_RD_ADDR_config_r_bootsel 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop : 1; - unsigned int dma01_eth0 : 1; - unsigned int dma23 : 1; - unsigned int dma45 : 1; - unsigned int dma67 : 1; - unsigned int dma89_strcop : 1; - unsigned int bif : 1; - unsigned int fix_io : 1; - unsigned int dummy1 : 22; -} reg_config_rw_clk_ctrl; -#define REG_RD_ADDR_config_rw_clk_ctrl 4 -#define REG_WR_ADDR_config_rw_clk_ctrl 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -typedef struct { - unsigned int usb_susp : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 30; -} reg_config_rw_pad_ctrl; -#define REG_RD_ADDR_config_rw_pad_ctrl 8 -#define REG_WR_ADDR_config_rw_pad_ctrl 8 - - -/* Constants */ -enum { - regk_config_bw16 = 0x00000000, - regk_config_bw32 = 0x00000001, - regk_config_master = 0x00000005, - regk_config_nand = 0x00000003, - regk_config_net_rx = 0x00000001, - regk_config_net_tx_rx = 0x00000002, - regk_config_no = 0x00000000, - regk_config_none = 0x00000007, - regk_config_nor = 0x00000000, - regk_config_rw_clk_ctrl_default = 0x00000002, - regk_config_rw_pad_ctrl_default = 0x00000000, - regk_config_ser = 0x00000004, - regk_config_slave = 0x00000006, - regk_config_yes = 0x00000001 -}; -#endif /* __config_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/cpu_vect.h b/trunk/include/asm-cris/arch-v32/hwregs/cpu_vect.h deleted file mode 100644 index 8370aee8a14a..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/cpu_vect.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/crisp/doc/cpu_vect.r -version . */ - -#ifndef _______INST_CRISP_DOC_CPU_VECT_R -#define _______INST_CRISP_DOC_CPU_VECT_R -#define NMI_INTR_VECT 0x00 -#define RESERVED_1_INTR_VECT 0x01 -#define RESERVED_2_INTR_VECT 0x02 -#define SINGLE_STEP_INTR_VECT 0x03 -#define INSTR_TLB_REFILL_INTR_VECT 0x04 -#define INSTR_TLB_INV_INTR_VECT 0x05 -#define INSTR_TLB_ACC_INTR_VECT 0x06 -#define TLB_EX_INTR_VECT 0x07 -#define DATA_TLB_REFILL_INTR_VECT 0x08 -#define DATA_TLB_INV_INTR_VECT 0x09 -#define DATA_TLB_ACC_INTR_VECT 0x0a -#define DATA_TLB_WE_INTR_VECT 0x0b -#define HW_BP_INTR_VECT 0x0c -#define RESERVED_D_INTR_VECT 0x0d -#define RESERVED_E_INTR_VECT 0x0e -#define RESERVED_F_INTR_VECT 0x0f -#define BREAK_0_INTR_VECT 0x10 -#define BREAK_1_INTR_VECT 0x11 -#define BREAK_2_INTR_VECT 0x12 -#define BREAK_3_INTR_VECT 0x13 -#define BREAK_4_INTR_VECT 0x14 -#define BREAK_5_INTR_VECT 0x15 -#define BREAK_6_INTR_VECT 0x16 -#define BREAK_7_INTR_VECT 0x17 -#define BREAK_8_INTR_VECT 0x18 -#define BREAK_9_INTR_VECT 0x19 -#define BREAK_10_INTR_VECT 0x1a -#define BREAK_11_INTR_VECT 0x1b -#define BREAK_12_INTR_VECT 0x1c -#define BREAK_13_INTR_VECT 0x1d -#define BREAK_14_INTR_VECT 0x1e -#define BREAK_15_INTR_VECT 0x1f -#define MULTIPLE_INTR_VECT 0x30 - -#endif diff --git a/trunk/include/asm-cris/arch-v32/hwregs/dma.h b/trunk/include/asm-cris/arch-v32/hwregs/dma.h deleted file mode 100644 index c31832d3d6be..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/dma.h +++ /dev/null @@ -1,128 +0,0 @@ -/* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * - * DMA C definitions and help macros - * - */ - -#ifndef dma_h -#define dma_h - -/* registers */ /* Really needed, since both are listed in sw.list? */ -#include "dma_defs.h" - - -/* descriptors */ - -// ------------------------------------------------------------ dma_descr_group -typedef struct dma_descr_group { - struct dma_descr_group *next; - unsigned eol : 1; - unsigned tol : 1; - unsigned bol : 1; - unsigned : 1; - unsigned intr : 1; - unsigned : 2; - unsigned en : 1; - unsigned : 7; - unsigned dis : 1; - unsigned md : 16; - struct dma_descr_group *up; - union { - struct dma_descr_context *context; - struct dma_descr_group *group; - } down; -} dma_descr_group; - -// ---------------------------------------------------------- dma_descr_context -typedef struct dma_descr_context { - struct dma_descr_context *next; - unsigned eol : 1; - unsigned : 3; - unsigned intr : 1; - unsigned : 1; - unsigned store_mode : 1; - unsigned en : 1; - unsigned : 7; - unsigned dis : 1; - unsigned md0 : 16; - unsigned md1; - unsigned md2; - unsigned md3; - unsigned md4; - struct dma_descr_data *saved_data; - char *saved_data_buf; -} dma_descr_context; - -// ------------------------------------------------------------- dma_descr_data -typedef struct dma_descr_data { - struct dma_descr_data *next; - char *buf; - unsigned eol : 1; - unsigned : 2; - unsigned out_eop : 1; - unsigned intr : 1; - unsigned wait : 1; - unsigned : 2; - unsigned : 3; - unsigned in_eop : 1; - unsigned : 4; - unsigned md : 16; - char *after; -} dma_descr_data; - -// --------------------------------------------------------------------- macros - -// enable DMA channel -#define DMA_ENABLE( inst ) \ - do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\ - e.en = regk_dma_yes; \ - REG_WR( dma, inst, rw_cfg, e); } while( 0 ) - -// reset DMA channel -#define DMA_RESET( inst ) \ - do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\ - r.en = regk_dma_no; \ - REG_WR( dma, inst, rw_cfg, r); } while( 0 ) - -// stop DMA channel -#define DMA_STOP( inst ) \ - do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\ - s.stop = regk_dma_yes; \ - REG_WR( dma, inst, rw_cfg, s); } while( 0 ) - -// continue DMA channel operation -#define DMA_CONTINUE( inst ) \ - do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\ - c.stop = regk_dma_no; \ - REG_WR( dma, inst, rw_cfg, c); } while( 0 ) - -// give stream command -#define DMA_WR_CMD( inst, cmd_par ) \ - do { reg_dma_rw_stream_cmd r = {0}; \ - do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \ - r.cmd = (cmd_par); \ - REG_WR( dma, inst, rw_stream_cmd, r ); \ - } while( 0 ) - -// load: g,c,d:burst -#define DMA_START_GROUP( inst, group_descr ) \ - do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \ - DMA_WR_CMD( inst, regk_dma_load_g ); \ - DMA_WR_CMD( inst, regk_dma_load_c ); \ - DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ - } while( 0 ) - -// load: c,d:burst -#define DMA_START_CONTEXT( inst, ctx_descr ) \ - do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \ - DMA_WR_CMD( inst, regk_dma_load_c ); \ - DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ - } while( 0 ) - -// if the DMA is at the end of the data list, the last data descr is reloaded -#define DMA_CONTINUE_DATA( inst ) \ -do { reg_dma_rw_cmd c = {0}; \ - c.cont_data = regk_dma_yes;\ - REG_WR( dma, inst, rw_cmd, c ); } while( 0 ) - -#endif diff --git a/trunk/include/asm-cris/arch-v32/hwregs/dma_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/dma_defs.h deleted file mode 100644 index 48ac8cef7ebe..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/dma_defs.h +++ /dev/null @@ -1,436 +0,0 @@ -#ifndef __dma_defs_h -#define __dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp - * last modfied: Mon Apr 11 16:06:51 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope dma */ - -/* Register rw_data, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data; -#define REG_RD_ADDR_dma_rw_data 0 -#define REG_WR_ADDR_dma_rw_data 0 - -/* Register rw_data_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_next; -#define REG_RD_ADDR_dma_rw_data_next 4 -#define REG_WR_ADDR_dma_rw_data_next 4 - -/* Register rw_data_buf, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_buf; -#define REG_RD_ADDR_dma_rw_data_buf 8 -#define REG_WR_ADDR_dma_rw_data_buf 8 - -/* Register rw_data_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int dummy1 : 2; - unsigned int out_eop : 1; - unsigned int intr : 1; - unsigned int wait : 1; - unsigned int dummy2 : 26; -} reg_dma_rw_data_ctrl; -#define REG_RD_ADDR_dma_rw_data_ctrl 12 -#define REG_WR_ADDR_dma_rw_data_ctrl 12 - -/* Register rw_data_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 3; - unsigned int in_eop : 1; - unsigned int dummy2 : 28; -} reg_dma_rw_data_stat; -#define REG_RD_ADDR_dma_rw_data_stat 16 -#define REG_WR_ADDR_dma_rw_data_stat 16 - -/* Register rw_data_md, scope dma, type rw */ -typedef struct { - unsigned int md : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_data_md; -#define REG_RD_ADDR_dma_rw_data_md 20 -#define REG_WR_ADDR_dma_rw_data_md 20 - -/* Register rw_data_md_s, scope dma, type rw */ -typedef struct { - unsigned int md_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_data_md_s; -#define REG_RD_ADDR_dma_rw_data_md_s 24 -#define REG_WR_ADDR_dma_rw_data_md_s 24 - -/* Register rw_data_after, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_after; -#define REG_RD_ADDR_dma_rw_data_after 28 -#define REG_WR_ADDR_dma_rw_data_after 28 - -/* Register rw_ctxt, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt; -#define REG_RD_ADDR_dma_rw_ctxt 32 -#define REG_WR_ADDR_dma_rw_ctxt 32 - -/* Register rw_ctxt_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_next; -#define REG_RD_ADDR_dma_rw_ctxt_next 36 -#define REG_WR_ADDR_dma_rw_ctxt_next 36 - -/* Register rw_ctxt_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int dummy1 : 3; - unsigned int intr : 1; - unsigned int dummy2 : 1; - unsigned int store_mode : 1; - unsigned int en : 1; - unsigned int dummy3 : 24; -} reg_dma_rw_ctxt_ctrl; -#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40 -#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40 - -/* Register rw_ctxt_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int dis : 1; - unsigned int dummy2 : 24; -} reg_dma_rw_ctxt_stat; -#define REG_RD_ADDR_dma_rw_ctxt_stat 44 -#define REG_WR_ADDR_dma_rw_ctxt_stat 44 - -/* Register rw_ctxt_md0, scope dma, type rw */ -typedef struct { - unsigned int md0 : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_ctxt_md0; -#define REG_RD_ADDR_dma_rw_ctxt_md0 48 -#define REG_WR_ADDR_dma_rw_ctxt_md0 48 - -/* Register rw_ctxt_md0_s, scope dma, type rw */ -typedef struct { - unsigned int md0_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_ctxt_md0_s; -#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52 -#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52 - -/* Register rw_ctxt_md1, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md1; -#define REG_RD_ADDR_dma_rw_ctxt_md1 56 -#define REG_WR_ADDR_dma_rw_ctxt_md1 56 - -/* Register rw_ctxt_md1_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md1_s; -#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60 -#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60 - -/* Register rw_ctxt_md2, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md2; -#define REG_RD_ADDR_dma_rw_ctxt_md2 64 -#define REG_WR_ADDR_dma_rw_ctxt_md2 64 - -/* Register rw_ctxt_md2_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md2_s; -#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68 -#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68 - -/* Register rw_ctxt_md3, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md3; -#define REG_RD_ADDR_dma_rw_ctxt_md3 72 -#define REG_WR_ADDR_dma_rw_ctxt_md3 72 - -/* Register rw_ctxt_md3_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md3_s; -#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76 -#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76 - -/* Register rw_ctxt_md4, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md4; -#define REG_RD_ADDR_dma_rw_ctxt_md4 80 -#define REG_WR_ADDR_dma_rw_ctxt_md4 80 - -/* Register rw_ctxt_md4_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md4_s; -#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84 -#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84 - -/* Register rw_saved_data, scope dma, type rw */ -typedef unsigned int reg_dma_rw_saved_data; -#define REG_RD_ADDR_dma_rw_saved_data 88 -#define REG_WR_ADDR_dma_rw_saved_data 88 - -/* Register rw_saved_data_buf, scope dma, type rw */ -typedef unsigned int reg_dma_rw_saved_data_buf; -#define REG_RD_ADDR_dma_rw_saved_data_buf 92 -#define REG_WR_ADDR_dma_rw_saved_data_buf 92 - -/* Register rw_group, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group; -#define REG_RD_ADDR_dma_rw_group 96 -#define REG_WR_ADDR_dma_rw_group 96 - -/* Register rw_group_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_next; -#define REG_RD_ADDR_dma_rw_group_next 100 -#define REG_WR_ADDR_dma_rw_group_next 100 - -/* Register rw_group_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int tol : 1; - unsigned int bol : 1; - unsigned int dummy1 : 1; - unsigned int intr : 1; - unsigned int dummy2 : 2; - unsigned int en : 1; - unsigned int dummy3 : 24; -} reg_dma_rw_group_ctrl; -#define REG_RD_ADDR_dma_rw_group_ctrl 104 -#define REG_WR_ADDR_dma_rw_group_ctrl 104 - -/* Register rw_group_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int dis : 1; - unsigned int dummy2 : 24; -} reg_dma_rw_group_stat; -#define REG_RD_ADDR_dma_rw_group_stat 108 -#define REG_WR_ADDR_dma_rw_group_stat 108 - -/* Register rw_group_md, scope dma, type rw */ -typedef struct { - unsigned int md : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_group_md; -#define REG_RD_ADDR_dma_rw_group_md 112 -#define REG_WR_ADDR_dma_rw_group_md 112 - -/* Register rw_group_md_s, scope dma, type rw */ -typedef struct { - unsigned int md_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_group_md_s; -#define REG_RD_ADDR_dma_rw_group_md_s 116 -#define REG_WR_ADDR_dma_rw_group_md_s 116 - -/* Register rw_group_up, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_up; -#define REG_RD_ADDR_dma_rw_group_up 120 -#define REG_WR_ADDR_dma_rw_group_up 120 - -/* Register rw_group_down, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_down; -#define REG_RD_ADDR_dma_rw_group_down 124 -#define REG_WR_ADDR_dma_rw_group_down 124 - -/* Register rw_cmd, scope dma, type rw */ -typedef struct { - unsigned int cont_data : 1; - unsigned int dummy1 : 31; -} reg_dma_rw_cmd; -#define REG_RD_ADDR_dma_rw_cmd 128 -#define REG_WR_ADDR_dma_rw_cmd 128 - -/* Register rw_cfg, scope dma, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int stop : 1; - unsigned int dummy1 : 30; -} reg_dma_rw_cfg; -#define REG_RD_ADDR_dma_rw_cfg 132 -#define REG_WR_ADDR_dma_rw_cfg 132 - -/* Register rw_stat, scope dma, type rw */ -typedef struct { - unsigned int mode : 5; - unsigned int list_state : 3; - unsigned int stream_cmd_src : 8; - unsigned int dummy1 : 8; - unsigned int buf : 8; -} reg_dma_rw_stat; -#define REG_RD_ADDR_dma_rw_stat 136 -#define REG_WR_ADDR_dma_rw_stat 136 - -/* Register rw_intr_mask, scope dma, type rw */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_rw_intr_mask; -#define REG_RD_ADDR_dma_rw_intr_mask 140 -#define REG_WR_ADDR_dma_rw_intr_mask 140 - -/* Register rw_ack_intr, scope dma, type rw */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_rw_ack_intr; -#define REG_RD_ADDR_dma_rw_ack_intr 144 -#define REG_WR_ADDR_dma_rw_ack_intr 144 - -/* Register r_intr, scope dma, type r */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_r_intr; -#define REG_RD_ADDR_dma_r_intr 148 - -/* Register r_masked_intr, scope dma, type r */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_r_masked_intr; -#define REG_RD_ADDR_dma_r_masked_intr 152 - -/* Register rw_stream_cmd, scope dma, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 7; - unsigned int busy : 1; -} reg_dma_rw_stream_cmd; -#define REG_RD_ADDR_dma_rw_stream_cmd 156 -#define REG_WR_ADDR_dma_rw_stream_cmd 156 - - -/* Constants */ -enum { - regk_dma_ack_pkt = 0x00000100, - regk_dma_anytime = 0x00000001, - regk_dma_array = 0x00000008, - regk_dma_burst = 0x00000020, - regk_dma_client = 0x00000002, - regk_dma_copy_next = 0x00000010, - regk_dma_copy_up = 0x00000020, - regk_dma_data_at_eol = 0x00000001, - regk_dma_dis_c = 0x00000010, - regk_dma_dis_g = 0x00000020, - regk_dma_idle = 0x00000001, - regk_dma_intern = 0x00000004, - regk_dma_load_c = 0x00000200, - regk_dma_load_c_n = 0x00000280, - regk_dma_load_c_next = 0x00000240, - regk_dma_load_d = 0x00000140, - regk_dma_load_g = 0x00000300, - regk_dma_load_g_down = 0x000003c0, - regk_dma_load_g_next = 0x00000340, - regk_dma_load_g_up = 0x00000380, - regk_dma_next_en = 0x00000010, - regk_dma_next_pkt = 0x00000010, - regk_dma_no = 0x00000000, - regk_dma_only_at_wait = 0x00000000, - regk_dma_restore = 0x00000020, - regk_dma_rst = 0x00000001, - regk_dma_running = 0x00000004, - regk_dma_rw_cfg_default = 0x00000000, - regk_dma_rw_cmd_default = 0x00000000, - regk_dma_rw_intr_mask_default = 0x00000000, - regk_dma_rw_stat_default = 0x00000101, - regk_dma_rw_stream_cmd_default = 0x00000000, - regk_dma_save_down = 0x00000020, - regk_dma_save_up = 0x00000020, - regk_dma_set_reg = 0x00000050, - regk_dma_set_w_size1 = 0x00000190, - regk_dma_set_w_size2 = 0x000001a0, - regk_dma_set_w_size4 = 0x000001c0, - regk_dma_stopped = 0x00000002, - regk_dma_store_c = 0x00000002, - regk_dma_store_descr = 0x00000000, - regk_dma_store_g = 0x00000004, - regk_dma_store_md = 0x00000001, - regk_dma_sw = 0x00000008, - regk_dma_update_down = 0x00000020, - regk_dma_yes = 0x00000001 -}; -#endif /* __dma_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/eth_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/eth_defs.h deleted file mode 100644 index 1196d7cc783f..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/eth_defs.h +++ /dev/null @@ -1,384 +0,0 @@ -#ifndef __eth_defs_h -#define __eth_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/eth/rtl/eth_regs.r - * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp - * last modfied: Mon Apr 11 16:07:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r - * id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope eth */ - -/* Register rw_ma0_lo, scope eth, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_eth_rw_ma0_lo; -#define REG_RD_ADDR_eth_rw_ma0_lo 0 -#define REG_WR_ADDR_eth_rw_ma0_lo 0 - -/* Register rw_ma0_hi, scope eth, type rw */ -typedef struct { - unsigned int addr : 16; - unsigned int dummy1 : 16; -} reg_eth_rw_ma0_hi; -#define REG_RD_ADDR_eth_rw_ma0_hi 4 -#define REG_WR_ADDR_eth_rw_ma0_hi 4 - -/* Register rw_ma1_lo, scope eth, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_eth_rw_ma1_lo; -#define REG_RD_ADDR_eth_rw_ma1_lo 8 -#define REG_WR_ADDR_eth_rw_ma1_lo 8 - -/* Register rw_ma1_hi, scope eth, type rw */ -typedef struct { - unsigned int addr : 16; - unsigned int dummy1 : 16; -} reg_eth_rw_ma1_hi; -#define REG_RD_ADDR_eth_rw_ma1_hi 12 -#define REG_WR_ADDR_eth_rw_ma1_hi 12 - -/* Register rw_ga_lo, scope eth, type rw */ -typedef struct { - unsigned int table : 32; -} reg_eth_rw_ga_lo; -#define REG_RD_ADDR_eth_rw_ga_lo 16 -#define REG_WR_ADDR_eth_rw_ga_lo 16 - -/* Register rw_ga_hi, scope eth, type rw */ -typedef struct { - unsigned int table : 32; -} reg_eth_rw_ga_hi; -#define REG_RD_ADDR_eth_rw_ga_hi 20 -#define REG_WR_ADDR_eth_rw_ga_hi 20 - -/* Register rw_gen_ctrl, scope eth, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int phy : 2; - unsigned int protocol : 1; - unsigned int loopback : 1; - unsigned int flow_ctrl_dis : 1; - unsigned int dummy1 : 26; -} reg_eth_rw_gen_ctrl; -#define REG_RD_ADDR_eth_rw_gen_ctrl 24 -#define REG_WR_ADDR_eth_rw_gen_ctrl 24 - -/* Register rw_rec_ctrl, scope eth, type rw */ -typedef struct { - unsigned int ma0 : 1; - unsigned int ma1 : 1; - unsigned int individual : 1; - unsigned int broadcast : 1; - unsigned int undersize : 1; - unsigned int oversize : 1; - unsigned int bad_crc : 1; - unsigned int duplex : 1; - unsigned int max_size : 1; - unsigned int dummy1 : 23; -} reg_eth_rw_rec_ctrl; -#define REG_RD_ADDR_eth_rw_rec_ctrl 28 -#define REG_WR_ADDR_eth_rw_rec_ctrl 28 - -/* Register rw_tr_ctrl, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int pad : 1; - unsigned int retry : 1; - unsigned int ignore_col : 1; - unsigned int cancel : 1; - unsigned int hsh_delay : 1; - unsigned int ignore_crs : 1; - unsigned int dummy1 : 25; -} reg_eth_rw_tr_ctrl; -#define REG_RD_ADDR_eth_rw_tr_ctrl 32 -#define REG_WR_ADDR_eth_rw_tr_ctrl 32 - -/* Register rw_clr_err, scope eth, type rw */ -typedef struct { - unsigned int clr : 1; - unsigned int dummy1 : 31; -} reg_eth_rw_clr_err; -#define REG_RD_ADDR_eth_rw_clr_err 36 -#define REG_WR_ADDR_eth_rw_clr_err 36 - -/* Register rw_mgm_ctrl, scope eth, type rw */ -typedef struct { - unsigned int mdio : 1; - unsigned int mdoe : 1; - unsigned int mdc : 1; - unsigned int phyclk : 1; - unsigned int txdata : 4; - unsigned int txen : 1; - unsigned int dummy1 : 23; -} reg_eth_rw_mgm_ctrl; -#define REG_RD_ADDR_eth_rw_mgm_ctrl 40 -#define REG_WR_ADDR_eth_rw_mgm_ctrl 40 - -/* Register r_stat, scope eth, type r */ -typedef struct { - unsigned int mdio : 1; - unsigned int exc_col : 1; - unsigned int urun : 1; - unsigned int phyclk : 1; - unsigned int txdata : 4; - unsigned int txen : 1; - unsigned int col : 1; - unsigned int crs : 1; - unsigned int txclk : 1; - unsigned int rxdata : 4; - unsigned int rxer : 1; - unsigned int rxdv : 1; - unsigned int rxclk : 1; - unsigned int dummy1 : 13; -} reg_eth_r_stat; -#define REG_RD_ADDR_eth_r_stat 44 - -/* Register rs_rec_cnt, scope eth, type rs */ -typedef struct { - unsigned int crc_err : 8; - unsigned int align_err : 8; - unsigned int oversize : 8; - unsigned int congestion : 8; -} reg_eth_rs_rec_cnt; -#define REG_RD_ADDR_eth_rs_rec_cnt 48 - -/* Register r_rec_cnt, scope eth, type r */ -typedef struct { - unsigned int crc_err : 8; - unsigned int align_err : 8; - unsigned int oversize : 8; - unsigned int congestion : 8; -} reg_eth_r_rec_cnt; -#define REG_RD_ADDR_eth_r_rec_cnt 52 - -/* Register rs_tr_cnt, scope eth, type rs */ -typedef struct { - unsigned int single_col : 8; - unsigned int mult_col : 8; - unsigned int late_col : 8; - unsigned int deferred : 8; -} reg_eth_rs_tr_cnt; -#define REG_RD_ADDR_eth_rs_tr_cnt 56 - -/* Register r_tr_cnt, scope eth, type r */ -typedef struct { - unsigned int single_col : 8; - unsigned int mult_col : 8; - unsigned int late_col : 8; - unsigned int deferred : 8; -} reg_eth_r_tr_cnt; -#define REG_RD_ADDR_eth_r_tr_cnt 60 - -/* Register rs_phy_cnt, scope eth, type rs */ -typedef struct { - unsigned int carrier_loss : 8; - unsigned int sqe_err : 8; - unsigned int dummy1 : 16; -} reg_eth_rs_phy_cnt; -#define REG_RD_ADDR_eth_rs_phy_cnt 64 - -/* Register r_phy_cnt, scope eth, type r */ -typedef struct { - unsigned int carrier_loss : 8; - unsigned int sqe_err : 8; - unsigned int dummy1 : 16; -} reg_eth_r_phy_cnt; -#define REG_RD_ADDR_eth_r_phy_cnt 68 - -/* Register rw_test_ctrl, scope eth, type rw */ -typedef struct { - unsigned int snmp_inc : 1; - unsigned int snmp : 1; - unsigned int backoff : 1; - unsigned int dummy1 : 29; -} reg_eth_rw_test_ctrl; -#define REG_RD_ADDR_eth_rw_test_ctrl 72 -#define REG_WR_ADDR_eth_rw_test_ctrl 72 - -/* Register rw_intr_mask, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int excessive_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_rw_intr_mask; -#define REG_RD_ADDR_eth_rw_intr_mask 76 -#define REG_WR_ADDR_eth_rw_intr_mask 76 - -/* Register rw_ack_intr, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int excessive_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_rw_ack_intr; -#define REG_RD_ADDR_eth_rw_ack_intr 80 -#define REG_WR_ADDR_eth_rw_ack_intr 80 - -/* Register r_intr, scope eth, type r */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int excessive_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_r_intr; -#define REG_RD_ADDR_eth_r_intr 84 - -/* Register r_masked_intr, scope eth, type r */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int excessive_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_r_masked_intr; -#define REG_RD_ADDR_eth_r_masked_intr 88 - - -/* Constants */ -enum { - regk_eth_discard = 0x00000000, - regk_eth_ether = 0x00000000, - regk_eth_full = 0x00000001, - regk_eth_half = 0x00000000, - regk_eth_hsh = 0x00000001, - regk_eth_mii = 0x00000001, - regk_eth_mii_clk = 0x00000000, - regk_eth_mii_rec = 0x00000002, - regk_eth_no = 0x00000000, - regk_eth_rec = 0x00000001, - regk_eth_rw_ga_hi_default = 0x00000000, - regk_eth_rw_ga_lo_default = 0x00000000, - regk_eth_rw_gen_ctrl_default = 0x00000000, - regk_eth_rw_intr_mask_default = 0x00000000, - regk_eth_rw_ma0_hi_default = 0x00000000, - regk_eth_rw_ma0_lo_default = 0x00000000, - regk_eth_rw_ma1_hi_default = 0x00000000, - regk_eth_rw_ma1_lo_default = 0x00000000, - regk_eth_rw_mgm_ctrl_default = 0x00000000, - regk_eth_rw_test_ctrl_default = 0x00000000, - regk_eth_size1518 = 0x00000000, - regk_eth_size1522 = 0x00000001, - regk_eth_yes = 0x00000001 -}; -#endif /* __eth_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/extmem_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/extmem_defs.h deleted file mode 100644 index c47b5ca48ece..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/extmem_defs.h +++ /dev/null @@ -1,369 +0,0 @@ -#ifndef __extmem_defs_h -#define __extmem_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ext_mem/mod/extmem_regs.r - * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp - * last modfied: Tue Mar 30 22:26:21 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r - * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope extmem */ - -/* Register rw_cse0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_cse0_cfg; -#define REG_RD_ADDR_extmem_rw_cse0_cfg 0 -#define REG_WR_ADDR_extmem_rw_cse0_cfg 0 - -/* Register rw_cse1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_cse1_cfg; -#define REG_RD_ADDR_extmem_rw_cse1_cfg 4 -#define REG_WR_ADDR_extmem_rw_cse1_cfg 4 - -/* Register rw_csr0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csr0_cfg; -#define REG_RD_ADDR_extmem_rw_csr0_cfg 8 -#define REG_WR_ADDR_extmem_rw_csr0_cfg 8 - -/* Register rw_csr1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csr1_cfg; -#define REG_RD_ADDR_extmem_rw_csr1_cfg 12 -#define REG_WR_ADDR_extmem_rw_csr1_cfg 12 - -/* Register rw_csp0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp0_cfg; -#define REG_RD_ADDR_extmem_rw_csp0_cfg 16 -#define REG_WR_ADDR_extmem_rw_csp0_cfg 16 - -/* Register rw_csp1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp1_cfg; -#define REG_RD_ADDR_extmem_rw_csp1_cfg 20 -#define REG_WR_ADDR_extmem_rw_csp1_cfg 20 - -/* Register rw_csp2_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp2_cfg; -#define REG_RD_ADDR_extmem_rw_csp2_cfg 24 -#define REG_WR_ADDR_extmem_rw_csp2_cfg 24 - -/* Register rw_csp3_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp3_cfg; -#define REG_RD_ADDR_extmem_rw_csp3_cfg 28 -#define REG_WR_ADDR_extmem_rw_csp3_cfg 28 - -/* Register rw_csp4_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp4_cfg; -#define REG_RD_ADDR_extmem_rw_csp4_cfg 32 -#define REG_WR_ADDR_extmem_rw_csp4_cfg 32 - -/* Register rw_csp5_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp5_cfg; -#define REG_RD_ADDR_extmem_rw_csp5_cfg 36 -#define REG_WR_ADDR_extmem_rw_csp5_cfg 36 - -/* Register rw_csp6_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp6_cfg; -#define REG_RD_ADDR_extmem_rw_csp6_cfg 40 -#define REG_WR_ADDR_extmem_rw_csp6_cfg 40 - -/* Register rw_css_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_css_cfg; -#define REG_RD_ADDR_extmem_rw_css_cfg 44 -#define REG_WR_ADDR_extmem_rw_css_cfg 44 - -/* Register rw_status_handle, scope extmem, type rw */ -typedef struct { - unsigned int h : 32; -} reg_extmem_rw_status_handle; -#define REG_RD_ADDR_extmem_rw_status_handle 48 -#define REG_WR_ADDR_extmem_rw_status_handle 48 - -/* Register rw_wait_pin, scope extmem, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 15; - unsigned int start : 1; -} reg_extmem_rw_wait_pin; -#define REG_RD_ADDR_extmem_rw_wait_pin 52 -#define REG_WR_ADDR_extmem_rw_wait_pin 52 - -/* Register rw_gated_csp, scope extmem, type rw */ -typedef struct { - unsigned int dummy1 : 31; - unsigned int en : 1; -} reg_extmem_rw_gated_csp; -#define REG_RD_ADDR_extmem_rw_gated_csp 56 -#define REG_WR_ADDR_extmem_rw_gated_csp 56 - - -/* Constants */ -enum { - regk_extmem_b16 = 0x00000001, - regk_extmem_b32 = 0x00000000, - regk_extmem_bwe = 0x00000000, - regk_extmem_cwe = 0x00000001, - regk_extmem_no = 0x00000000, - regk_extmem_rw_cse0_cfg_default = 0x000006cf, - regk_extmem_rw_cse1_cfg_default = 0x000006cf, - regk_extmem_rw_csp0_cfg_default = 0x000006cf, - regk_extmem_rw_csp1_cfg_default = 0x000006cf, - regk_extmem_rw_csp2_cfg_default = 0x000006cf, - regk_extmem_rw_csp3_cfg_default = 0x000006cf, - regk_extmem_rw_csp4_cfg_default = 0x000006cf, - regk_extmem_rw_csp5_cfg_default = 0x000006cf, - regk_extmem_rw_csp6_cfg_default = 0x000006cf, - regk_extmem_rw_csr0_cfg_default = 0x000006cf, - regk_extmem_rw_csr1_cfg_default = 0x000006cf, - regk_extmem_rw_css_cfg_default = 0x000006cf, - regk_extmem_s128KB = 0x00000000, - regk_extmem_s16MB = 0x00000005, - regk_extmem_s1MB = 0x00000001, - regk_extmem_s2MB = 0x00000002, - regk_extmem_s32MB = 0x00000006, - regk_extmem_s4MB = 0x00000003, - regk_extmem_s64MB = 0x00000007, - regk_extmem_s8MB = 0x00000004, - regk_extmem_yes = 0x00000001 -}; -#endif /* __extmem_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/gio_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/gio_defs.h deleted file mode 100644 index 3e9a0b25366f..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/gio_defs.h +++ /dev/null @@ -1,295 +0,0 @@ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 0 -#define REG_WR_ADDR_gio_rw_pa_dout 0 - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 3; - unsigned int pa1 : 3; - unsigned int pa2 : 3; - unsigned int pa3 : 3; - unsigned int pa4 : 3; - unsigned int pa5 : 3; - unsigned int pa6 : 3; - unsigned int pa7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 12 -#define REG_WR_ADDR_gio_rw_intr_cfg 12 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 16 -#define REG_WR_ADDR_gio_rw_intr_mask 16 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 20 -#define REG_WR_ADDR_gio_rw_ack_intr 20 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 24 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 28 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 32 -#define REG_WR_ADDR_gio_rw_pb_dout 32 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 36 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 40 -#define REG_WR_ADDR_gio_rw_pb_oe 40 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 48 -#define REG_WR_ADDR_gio_rw_pc_dout 48 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 52 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 56 -#define REG_WR_ADDR_gio_rw_pc_oe 56 - -/* Register rw_pd_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_dout; -#define REG_RD_ADDR_gio_rw_pd_dout 64 -#define REG_WR_ADDR_gio_rw_pd_dout 64 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 68 - -/* Register rw_pd_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_oe; -#define REG_RD_ADDR_gio_rw_pd_oe 72 -#define REG_WR_ADDR_gio_rw_pd_oe 72 - -/* Register rw_pe_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_dout; -#define REG_RD_ADDR_gio_rw_pe_dout 80 -#define REG_WR_ADDR_gio_rw_pe_dout 80 - -/* Register r_pe_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pe_din; -#define REG_RD_ADDR_gio_r_pe_din 84 - -/* Register rw_pe_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_oe; -#define REG_RD_ADDR_gio_rw_pe_oe 88 -#define REG_WR_ADDR_gio_rw_pe_oe 88 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_hi = 0x00000001, - regk_gio_lo = 0x00000002, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_off = 0x00000000, - regk_gio_posedge = 0x00000005, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_pd_oe_default = 0x00000000, - regk_gio_rw_pe_oe_default = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/intr_vect.h b/trunk/include/asm-cris/arch-v32/hwregs/intr_vect.h deleted file mode 100644 index 5c1b28fb205d..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/intr_vect.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e -#define IPI_INTR_VECT 0x4f - -#endif diff --git a/trunk/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h deleted file mode 100644 index 535aaf1b4b52..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h +++ /dev/null @@ -1,225 +0,0 @@ -#ifndef __intr_vect_defs_h -#define __intr_vect_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp - * last modfied: Mon Apr 11 16:08:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs.h,v 1.8 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope intr_vect */ - -/* Register rw_mask, scope intr_vect, type rw */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_rw_mask; -#define REG_RD_ADDR_intr_vect_rw_mask 0 -#define REG_WR_ADDR_intr_vect_rw_mask 0 - -/* Register r_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_vect; -#define REG_RD_ADDR_intr_vect_r_vect 4 - -/* Register r_masked_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_masked_vect; -#define REG_RD_ADDR_intr_vect_r_masked_vect 8 - -/* Register r_nmi, scope intr_vect, type r */ -typedef struct { - unsigned int ext : 1; - unsigned int watchdog : 1; - unsigned int dummy1 : 30; -} reg_intr_vect_r_nmi; -#define REG_RD_ADDR_intr_vect_r_nmi 12 - -/* Register r_guru, scope intr_vect, type r */ -typedef struct { - unsigned int jtag : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_r_guru; -#define REG_RD_ADDR_intr_vect_r_guru 16 - -/* Register rw_ipi, scope intr_vect, type rw */ -typedef struct -{ - unsigned int vector; -} reg_intr_vect_rw_ipi; -#define REG_RD_ADDR_intr_vect_rw_ipi 20 -#define REG_WR_ADDR_intr_vect_rw_ipi 20 - -/* Constants */ -enum { - regk_intr_vect_off = 0x00000000, - regk_intr_vect_on = 0x00000001, - regk_intr_vect_rw_mask_default = 0x00000000 -}; -#endif /* __intr_vect_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/Makefile b/trunk/include/asm-cris/arch-v32/hwregs/iop/Makefile deleted file mode 100644 index a90056a095e3..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/Makefile +++ /dev/null @@ -1,146 +0,0 @@ -# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $ -# Makefile to generate or copy the latest register definitions -# and related datastructures and helpermacros. -# The offical place for these files is probably at: -RELEASE ?= r1_alfa5 -IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ - -IOPROCDIR = /n/asic/design/io/io_proc/rtl - -IOPROCINCL_FILES = -IOPROCINCL_FILES2= -IOPROCINCL_FILES += iop_crc_par_defs.h -IOPROCINCL_FILES += iop_dmc_in_defs.h -IOPROCINCL_FILES += iop_dmc_out_defs.h -IOPROCINCL_FILES += iop_fifo_in_defs.h -IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h -IOPROCINCL_FILES += iop_fifo_out_defs.h -IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h -IOPROCINCL_FILES += iop_mpu_defs.h -IOPROCINCL_FILES2+= iop_mpu_macros.h -IOPROCINCL_FILES2+= iop_reg_space.h -IOPROCINCL_FILES += iop_sap_in_defs.h -IOPROCINCL_FILES += iop_sap_out_defs.h -IOPROCINCL_FILES += iop_scrc_in_defs.h -IOPROCINCL_FILES += iop_scrc_out_defs.h -IOPROCINCL_FILES += iop_spu_defs.h -# in guiness/ -IOPROCINCL_FILES += iop_sw_cfg_defs.h -IOPROCINCL_FILES += iop_sw_cpu_defs.h -IOPROCINCL_FILES += iop_sw_mpu_defs.h -IOPROCINCL_FILES += iop_sw_spu_defs.h -# -IOPROCINCL_FILES += iop_timer_grp_defs.h -IOPROCINCL_FILES += iop_trigger_grp_defs.h -# in guiness/ -IOPROCINCL_FILES += iop_version_defs.h - -IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES)) -IOPROCASMINCL_FILES+= iop_reg_space_asm.h - - -IOPROCREGDESC = -IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r -#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r -IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r -IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r -IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r -IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r -IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r - - -RDES2C = /n/asic/bin/rdes2c -RDES2C = /n/asic/design/tools/rdesc/rdes2c -RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr -RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt - -## all - Just print help - you probably want to do 'make gen' -all: help - -## help - This help -help: - @grep '^## ' Makefile - -## gen - Generate include files -gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) - echo "INCL: $(IOPROCINCL_FILES)" - echo "INCL2: $(IOPROCINCL_FILES2)" - echo "ASMINCL: $(IOPROCASMINCL_FILES)" - -# From the official location... -iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ - -## copy - Copy files from official location -copy: - @echo "## Copying and fixing iop files ##" - @for HFILE in $(IOPROCINCL_FILES); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @for HFILE in $(IOPROCINCL_FILES2); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @echo "## Copying and fixing iop asm files ##" - @for HFILE in $(IOPROCASMINCL_FILES); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \ - done - -# I/O processor files: -## iop - Generate I/O processor include files -iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) -iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r - $(RDES2C) $< -iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r - $(RDES2C) $< -%_defs.h: $(IOPROCDIR)/%.r - $(RDES2C) $< -%_defs_asm.h: $(IOPROCDIR)/%.r - $(RDES2C) -asm $< -iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r - $(RDES2C) -asm $< - -## doc - Generate .axw files from register description. -doc: $(IOPROCREGDESC) - for RDES in $^; do \ - $(RDES2TXT) $$RDES; \ - done - -.PHONY: axw -## %.axw - Generate the specified .axw file (doesn't work for all files -## due to inconsistent naming of .r files. -%.axw: axw - @for RDES in $(IOPROCREGDESC); do \ - if echo "$$RDES" | grep $* ; then \ - $(RDES2TXT) $$RDES; \ - fi \ - done - -.PHONY: clean -## clean - Remove .h files and .axw files. -clean: - rm -rf $(IOPROCINCL_FILES) *.axw - -.PHONY: cleandoc -## cleandoc - Remove .axw files. -cleandoc: - rm -rf *.axw - diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h deleted file mode 100644 index a4b58000c164..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h +++ /dev/null @@ -1,171 +0,0 @@ -#ifndef __iop_crc_par_defs_asm_h -#define __iop_crc_par_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_crc_par.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r - * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_cfg___mode___lsb 0 -#define reg_iop_crc_par_rw_cfg___mode___width 1 -#define reg_iop_crc_par_rw_cfg___mode___bit 0 -#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1 -#define reg_iop_crc_par_rw_cfg___crc_out___width 1 -#define reg_iop_crc_par_rw_cfg___crc_out___bit 1 -#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2 -#define reg_iop_crc_par_rw_cfg___rev_out___width 1 -#define reg_iop_crc_par_rw_cfg___rev_out___bit 2 -#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3 -#define reg_iop_crc_par_rw_cfg___inv_out___width 1 -#define reg_iop_crc_par_rw_cfg___inv_out___bit 3 -#define reg_iop_crc_par_rw_cfg___trig___lsb 4 -#define reg_iop_crc_par_rw_cfg___trig___width 2 -#define reg_iop_crc_par_rw_cfg___poly___lsb 6 -#define reg_iop_crc_par_rw_cfg___poly___width 3 -#define reg_iop_crc_par_rw_cfg_offset 0 - -/* Register rw_init_crc, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_init_crc_offset 4 - -/* Register rw_correct_crc, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_correct_crc_offset 8 - -/* Register rw_ctrl, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_ctrl___en___lsb 0 -#define reg_iop_crc_par_rw_ctrl___en___width 1 -#define reg_iop_crc_par_rw_ctrl___en___bit 0 -#define reg_iop_crc_par_rw_ctrl_offset 12 - -/* Register rw_set_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0 -#define reg_iop_crc_par_rw_set_last___tr_dif___width 1 -#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0 -#define reg_iop_crc_par_rw_set_last_offset 16 - -/* Register rw_wr1byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr1byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr1byte___data___width 8 -#define reg_iop_crc_par_rw_wr1byte_offset 20 - -/* Register rw_wr2byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr2byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr2byte___data___width 16 -#define reg_iop_crc_par_rw_wr2byte_offset 24 - -/* Register rw_wr3byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr3byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr3byte___data___width 24 -#define reg_iop_crc_par_rw_wr3byte_offset 28 - -/* Register rw_wr4byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr4byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr4byte___data___width 32 -#define reg_iop_crc_par_rw_wr4byte_offset 32 - -/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr1byte_last___data___width 8 -#define reg_iop_crc_par_rw_wr1byte_last_offset 36 - -/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr2byte_last___data___width 16 -#define reg_iop_crc_par_rw_wr2byte_last_offset 40 - -/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr3byte_last___data___width 24 -#define reg_iop_crc_par_rw_wr3byte_last_offset 44 - -/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr4byte_last___data___width 32 -#define reg_iop_crc_par_rw_wr4byte_last_offset 48 - -/* Register r_stat, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_stat___err___lsb 0 -#define reg_iop_crc_par_r_stat___err___width 1 -#define reg_iop_crc_par_r_stat___err___bit 0 -#define reg_iop_crc_par_r_stat___busy___lsb 1 -#define reg_iop_crc_par_r_stat___busy___width 1 -#define reg_iop_crc_par_r_stat___busy___bit 1 -#define reg_iop_crc_par_r_stat_offset 52 - -/* Register r_sh_reg, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_sh_reg_offset 56 - -/* Register r_crc, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_crc_offset 60 - -/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0 -#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2 -#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64 - - -/* Constants */ -#define regk_iop_crc_par_calc 0x00000001 -#define regk_iop_crc_par_ccitt 0x00000002 -#define regk_iop_crc_par_check 0x00000000 -#define regk_iop_crc_par_crc16 0x00000001 -#define regk_iop_crc_par_crc32 0x00000000 -#define regk_iop_crc_par_crc5 0x00000003 -#define regk_iop_crc_par_crc5_11 0x00000004 -#define regk_iop_crc_par_dif_in 0x00000002 -#define regk_iop_crc_par_hi 0x00000000 -#define regk_iop_crc_par_neg 0x00000002 -#define regk_iop_crc_par_no 0x00000000 -#define regk_iop_crc_par_pos 0x00000001 -#define regk_iop_crc_par_pos_neg 0x00000003 -#define regk_iop_crc_par_rw_cfg_default 0x00000000 -#define regk_iop_crc_par_rw_ctrl_default 0x00000000 -#define regk_iop_crc_par_yes 0x00000001 -#endif /* __iop_crc_par_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h deleted file mode 100644 index e7d539feccb1..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h +++ /dev/null @@ -1,321 +0,0 @@ -#ifndef __iop_dmc_in_defs_asm_h -#define __iop_dmc_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_in.r - * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r - * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0 -#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3 -#define reg_iop_dmc_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0 -#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1 -#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2 -#define reg_iop_dmc_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_stat___dif_en___lsb 0 -#define reg_iop_dmc_in_r_stat___dif_en___width 1 -#define reg_iop_dmc_in_r_stat___dif_en___bit 0 -#define reg_iop_dmc_in_r_stat_offset 8 - -/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0 -#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10 -#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16 -#define reg_iop_dmc_in_rw_stream_cmd___n___width 8 -#define reg_iop_dmc_in_rw_stream_cmd_offset 12 - -/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_wr_data_offset 16 - -/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20 - -/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0 -#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2 -#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3 -#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3 -#define reg_iop_dmc_in_rw_stream_ctrl_offset 24 - -/* Register r_stream_stat, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0 -#define reg_iop_dmc_in_r_stream_stat___sth___width 7 -#define reg_iop_dmc_in_r_stream_stat___full___lsb 16 -#define reg_iop_dmc_in_r_stream_stat___full___width 1 -#define reg_iop_dmc_in_r_stream_stat___full___bit 16 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22 -#define reg_iop_dmc_in_r_stream_stat_offset 28 - -/* Register r_data_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_data_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_data_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_data_descr___stat___width 8 -#define reg_iop_dmc_in_r_data_descr___md___lsb 16 -#define reg_iop_dmc_in_r_data_descr___md___width 16 -#define reg_iop_dmc_in_r_data_descr_offset 32 - -/* Register r_ctxt_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8 -#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16 -#define reg_iop_dmc_in_r_ctxt_descr_offset 36 - -/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40 - -/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44 - -/* Register r_group_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_group_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_group_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_group_descr___stat___width 8 -#define reg_iop_dmc_in_r_group_descr___md___lsb 16 -#define reg_iop_dmc_in_r_group_descr___md___width 16 -#define reg_iop_dmc_in_r_group_descr_offset 56 - -/* Register rw_data_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_data_descr___md___lsb 16 -#define reg_iop_dmc_in_rw_data_descr___md___width 16 -#define reg_iop_dmc_in_rw_data_descr_offset 60 - -/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16 -#define reg_iop_dmc_in_rw_ctxt_descr_offset 64 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72 - -/* Register rw_group_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_group_descr___md___lsb 16 -#define reg_iop_dmc_in_rw_group_descr___md___width 16 -#define reg_iop_dmc_in_rw_group_descr_offset 84 - -/* Register rw_intr_mask, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0 -#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1 -#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2 -#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3 -#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4 -#define reg_iop_dmc_in_rw_intr_mask___sth___width 1 -#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4 -#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5 -#define reg_iop_dmc_in_rw_intr_mask___full___width 1 -#define reg_iop_dmc_in_rw_intr_mask___full___bit 5 -#define reg_iop_dmc_in_rw_intr_mask_offset 88 - -/* Register rw_ack_intr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0 -#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2 -#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4 -#define reg_iop_dmc_in_rw_ack_intr___sth___width 1 -#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4 -#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5 -#define reg_iop_dmc_in_rw_ack_intr___full___width 1 -#define reg_iop_dmc_in_rw_ack_intr___full___bit 5 -#define reg_iop_dmc_in_rw_ack_intr_offset 92 - -/* Register r_intr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_intr___data_md___lsb 0 -#define reg_iop_dmc_in_r_intr___data_md___width 1 -#define reg_iop_dmc_in_r_intr___data_md___bit 0 -#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_r_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_r_intr___group_md___lsb 2 -#define reg_iop_dmc_in_r_intr___group_md___width 1 -#define reg_iop_dmc_in_r_intr___group_md___bit 2 -#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_r_intr___sth___lsb 4 -#define reg_iop_dmc_in_r_intr___sth___width 1 -#define reg_iop_dmc_in_r_intr___sth___bit 4 -#define reg_iop_dmc_in_r_intr___full___lsb 5 -#define reg_iop_dmc_in_r_intr___full___width 1 -#define reg_iop_dmc_in_r_intr___full___bit 5 -#define reg_iop_dmc_in_r_intr_offset 96 - -/* Register r_masked_intr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0 -#define reg_iop_dmc_in_r_masked_intr___data_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2 -#define reg_iop_dmc_in_r_masked_intr___group_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4 -#define reg_iop_dmc_in_r_masked_intr___sth___width 1 -#define reg_iop_dmc_in_r_masked_intr___sth___bit 4 -#define reg_iop_dmc_in_r_masked_intr___full___lsb 5 -#define reg_iop_dmc_in_r_masked_intr___full___width 1 -#define reg_iop_dmc_in_r_masked_intr___full___bit 5 -#define reg_iop_dmc_in_r_masked_intr_offset 100 - - -/* Constants */ -#define regk_iop_dmc_in_ack_pkt 0x00000100 -#define regk_iop_dmc_in_array 0x00000008 -#define regk_iop_dmc_in_burst 0x00000020 -#define regk_iop_dmc_in_copy_next 0x00000010 -#define regk_iop_dmc_in_copy_up 0x00000020 -#define regk_iop_dmc_in_dis_c 0x00000010 -#define regk_iop_dmc_in_dis_g 0x00000020 -#define regk_iop_dmc_in_lim1 0x00000000 -#define regk_iop_dmc_in_lim16 0x00000004 -#define regk_iop_dmc_in_lim2 0x00000001 -#define regk_iop_dmc_in_lim32 0x00000005 -#define regk_iop_dmc_in_lim4 0x00000002 -#define regk_iop_dmc_in_lim64 0x00000006 -#define regk_iop_dmc_in_lim8 0x00000003 -#define regk_iop_dmc_in_load_c 0x00000200 -#define regk_iop_dmc_in_load_c_n 0x00000280 -#define regk_iop_dmc_in_load_c_next 0x00000240 -#define regk_iop_dmc_in_load_d 0x00000140 -#define regk_iop_dmc_in_load_g 0x00000300 -#define regk_iop_dmc_in_load_g_down 0x000003c0 -#define regk_iop_dmc_in_load_g_next 0x00000340 -#define regk_iop_dmc_in_load_g_up 0x00000380 -#define regk_iop_dmc_in_next_en 0x00000010 -#define regk_iop_dmc_in_next_pkt 0x00000010 -#define regk_iop_dmc_in_no 0x00000000 -#define regk_iop_dmc_in_restore 0x00000020 -#define regk_iop_dmc_in_rw_cfg_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000 -#define regk_iop_dmc_in_rw_data_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_group_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000 -#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000 -#define regk_iop_dmc_in_save_down 0x00000020 -#define regk_iop_dmc_in_save_up 0x00000020 -#define regk_iop_dmc_in_set_reg 0x00000050 -#define regk_iop_dmc_in_set_w_size1 0x00000190 -#define regk_iop_dmc_in_set_w_size2 0x000001a0 -#define regk_iop_dmc_in_set_w_size4 0x000001c0 -#define regk_iop_dmc_in_store_c 0x00000002 -#define regk_iop_dmc_in_store_descr 0x00000000 -#define regk_iop_dmc_in_store_g 0x00000004 -#define regk_iop_dmc_in_store_md 0x00000001 -#define regk_iop_dmc_in_update_down 0x00000020 -#define regk_iop_dmc_in_yes 0x00000001 -#endif /* __iop_dmc_in_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h deleted file mode 100644 index 9fe1a8054371..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h +++ /dev/null @@ -1,349 +0,0 @@ -#ifndef __iop_dmc_out_defs_asm_h -#define __iop_dmc_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_out.r - * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r - * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0 -#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16 -#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17 -#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3 -#define reg_iop_dmc_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0 -#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1 -#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1 -#define reg_iop_dmc_out_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stat___dif_en___lsb 0 -#define reg_iop_dmc_out_r_stat___dif_en___width 1 -#define reg_iop_dmc_out_r_stat___dif_en___bit 0 -#define reg_iop_dmc_out_r_stat_offset 8 - -/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0 -#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10 -#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16 -#define reg_iop_dmc_out_rw_stream_cmd___n___width 8 -#define reg_iop_dmc_out_rw_stream_cmd_offset 12 - -/* Register rs_stream_data, scope iop_dmc_out, type rs */ -#define reg_iop_dmc_out_rs_stream_data_offset 16 - -/* Register r_stream_data, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stream_data_offset 20 - -/* Register r_stream_stat, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0 -#define reg_iop_dmc_out_r_stream_stat___dth___width 7 -#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16 -#define reg_iop_dmc_out_r_stream_stat___dv___width 1 -#define reg_iop_dmc_out_r_stream_stat___dv___bit 16 -#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17 -#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1 -#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17 -#define reg_iop_dmc_out_r_stream_stat___last___lsb 18 -#define reg_iop_dmc_out_r_stream_stat___last___width 1 -#define reg_iop_dmc_out_r_stream_stat___last___bit 18 -#define reg_iop_dmc_out_r_stream_stat___size___lsb 19 -#define reg_iop_dmc_out_r_stream_stat___size___width 3 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27 -#define reg_iop_dmc_out_r_stream_stat_offset 24 - -/* Register r_data_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_data_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_data_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_data_descr___stat___width 8 -#define reg_iop_dmc_out_r_data_descr___md___lsb 16 -#define reg_iop_dmc_out_r_data_descr___md___width 16 -#define reg_iop_dmc_out_r_data_descr_offset 28 - -/* Register r_ctxt_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8 -#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16 -#define reg_iop_dmc_out_r_ctxt_descr_offset 32 - -/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36 - -/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40 - -/* Register r_group_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_group_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_group_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_group_descr___stat___width 8 -#define reg_iop_dmc_out_r_group_descr___md___lsb 16 -#define reg_iop_dmc_out_r_group_descr___md___width 16 -#define reg_iop_dmc_out_r_group_descr_offset 52 - -/* Register rw_data_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_data_descr___md___lsb 16 -#define reg_iop_dmc_out_rw_data_descr___md___width 16 -#define reg_iop_dmc_out_rw_data_descr_offset 56 - -/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16 -#define reg_iop_dmc_out_rw_ctxt_descr_offset 60 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68 - -/* Register rw_group_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_group_descr___md___lsb 16 -#define reg_iop_dmc_out_rw_group_descr___md___width 16 -#define reg_iop_dmc_out_rw_group_descr_offset 80 - -/* Register rw_intr_mask, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0 -#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1 -#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2 -#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3 -#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4 -#define reg_iop_dmc_out_rw_intr_mask___dth___width 1 -#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4 -#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5 -#define reg_iop_dmc_out_rw_intr_mask___dv___width 1 -#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5 -#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6 -#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1 -#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8 -#define reg_iop_dmc_out_rw_intr_mask_offset 84 - -/* Register rw_ack_intr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0 -#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2 -#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4 -#define reg_iop_dmc_out_rw_ack_intr___dth___width 1 -#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4 -#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5 -#define reg_iop_dmc_out_rw_ack_intr___dv___width 1 -#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5 -#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6 -#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1 -#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_rw_ack_intr_offset 88 - -/* Register r_intr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_intr___data_md___lsb 0 -#define reg_iop_dmc_out_r_intr___data_md___width 1 -#define reg_iop_dmc_out_r_intr___data_md___bit 0 -#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_r_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_r_intr___group_md___lsb 2 -#define reg_iop_dmc_out_r_intr___group_md___width 1 -#define reg_iop_dmc_out_r_intr___group_md___bit 2 -#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_r_intr___dth___lsb 4 -#define reg_iop_dmc_out_r_intr___dth___width 1 -#define reg_iop_dmc_out_r_intr___dth___bit 4 -#define reg_iop_dmc_out_r_intr___dv___lsb 5 -#define reg_iop_dmc_out_r_intr___dv___width 1 -#define reg_iop_dmc_out_r_intr___dv___bit 5 -#define reg_iop_dmc_out_r_intr___last_data___lsb 6 -#define reg_iop_dmc_out_r_intr___last_data___width 1 -#define reg_iop_dmc_out_r_intr___last_data___bit 6 -#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_r_intr___trf_lim___width 1 -#define reg_iop_dmc_out_r_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_r_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_r_intr_offset 92 - -/* Register r_masked_intr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0 -#define reg_iop_dmc_out_r_masked_intr___data_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2 -#define reg_iop_dmc_out_r_masked_intr___group_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4 -#define reg_iop_dmc_out_r_masked_intr___dth___width 1 -#define reg_iop_dmc_out_r_masked_intr___dth___bit 4 -#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5 -#define reg_iop_dmc_out_r_masked_intr___dv___width 1 -#define reg_iop_dmc_out_r_masked_intr___dv___bit 5 -#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6 -#define reg_iop_dmc_out_r_masked_intr___last_data___width 1 -#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_r_masked_intr_offset 96 - - -/* Constants */ -#define regk_iop_dmc_out_ack_pkt 0x00000100 -#define regk_iop_dmc_out_array 0x00000008 -#define regk_iop_dmc_out_burst 0x00000020 -#define regk_iop_dmc_out_copy_next 0x00000010 -#define regk_iop_dmc_out_copy_up 0x00000020 -#define regk_iop_dmc_out_dis_c 0x00000010 -#define regk_iop_dmc_out_dis_g 0x00000020 -#define regk_iop_dmc_out_lim1 0x00000000 -#define regk_iop_dmc_out_lim16 0x00000004 -#define regk_iop_dmc_out_lim2 0x00000001 -#define regk_iop_dmc_out_lim32 0x00000005 -#define regk_iop_dmc_out_lim4 0x00000002 -#define regk_iop_dmc_out_lim64 0x00000006 -#define regk_iop_dmc_out_lim8 0x00000003 -#define regk_iop_dmc_out_load_c 0x00000200 -#define regk_iop_dmc_out_load_c_n 0x00000280 -#define regk_iop_dmc_out_load_c_next 0x00000240 -#define regk_iop_dmc_out_load_d 0x00000140 -#define regk_iop_dmc_out_load_g 0x00000300 -#define regk_iop_dmc_out_load_g_down 0x000003c0 -#define regk_iop_dmc_out_load_g_next 0x00000340 -#define regk_iop_dmc_out_load_g_up 0x00000380 -#define regk_iop_dmc_out_next_en 0x00000010 -#define regk_iop_dmc_out_next_pkt 0x00000010 -#define regk_iop_dmc_out_no 0x00000000 -#define regk_iop_dmc_out_restore 0x00000020 -#define regk_iop_dmc_out_rw_cfg_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000 -#define regk_iop_dmc_out_rw_data_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_group_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000 -#define regk_iop_dmc_out_save_down 0x00000020 -#define regk_iop_dmc_out_save_up 0x00000020 -#define regk_iop_dmc_out_set_reg 0x00000050 -#define regk_iop_dmc_out_set_w_size1 0x00000190 -#define regk_iop_dmc_out_set_w_size2 0x000001a0 -#define regk_iop_dmc_out_set_w_size4 0x000001c0 -#define regk_iop_dmc_out_store_c 0x00000002 -#define regk_iop_dmc_out_store_descr 0x00000000 -#define regk_iop_dmc_out_store_g 0x00000004 -#define regk_iop_dmc_out_store_md 0x00000001 -#define regk_iop_dmc_out_update_down 0x00000020 -#define regk_iop_dmc_out_yes 0x00000001 -#endif /* __iop_dmc_out_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h deleted file mode 100644 index 974dee082f9f..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h +++ /dev/null @@ -1,234 +0,0 @@ -#ifndef __iop_fifo_in_defs_asm_h -#define __iop_fifo_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in.r - * id: - * last modfied: Mon Apr 11 16:10:07 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r - * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0 -#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3 -#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3 -#define reg_iop_fifo_in_rw_cfg___byte_order___width 2 -#define reg_iop_fifo_in_rw_cfg___trig___lsb 5 -#define reg_iop_fifo_in_rw_cfg___trig___width 2 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7 -#define reg_iop_fifo_in_rw_cfg___mode___lsb 8 -#define reg_iop_fifo_in_rw_cfg___mode___width 2 -#define reg_iop_fifo_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1 -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1 -#define reg_iop_fifo_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_in_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_in_r_stat___last___lsb 4 -#define reg_iop_fifo_in_r_stat___last___width 8 -#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_in_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_in_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_in_r_stat_offset 8 - -/* Register rs_rd1byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd1byte___data___width 8 -#define reg_iop_fifo_in_rs_rd1byte_offset 12 - -/* Register r_rd1byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd1byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd1byte___data___width 8 -#define reg_iop_fifo_in_r_rd1byte_offset 16 - -/* Register rs_rd2byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd2byte___data___width 16 -#define reg_iop_fifo_in_rs_rd2byte_offset 20 - -/* Register r_rd2byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd2byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd2byte___data___width 16 -#define reg_iop_fifo_in_r_rd2byte_offset 24 - -/* Register rs_rd3byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd3byte___data___width 24 -#define reg_iop_fifo_in_rs_rd3byte_offset 28 - -/* Register r_rd3byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd3byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd3byte___data___width 24 -#define reg_iop_fifo_in_r_rd3byte_offset 32 - -/* Register rs_rd4byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd4byte___data___width 32 -#define reg_iop_fifo_in_rs_rd4byte_offset 36 - -/* Register r_rd4byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd4byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd4byte___data___width 32 -#define reg_iop_fifo_in_r_rd4byte_offset 40 - -/* Register rw_set_last, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_set_last_offset 44 - -/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0 -#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2 -#define reg_iop_fifo_in_rw_strb_dif_in_offset 48 - -/* Register rw_intr_mask, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_in_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_in_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3 -#define reg_iop_fifo_in_rw_intr_mask___avail___width 1 -#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3 -#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_in_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_in_rw_intr_mask_offset 52 - -/* Register rw_ack_intr, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_in_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_in_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3 -#define reg_iop_fifo_in_rw_ack_intr___avail___width 1 -#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3 -#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_in_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_in_rw_ack_intr_offset 56 - -/* Register r_intr, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_intr___urun___lsb 0 -#define reg_iop_fifo_in_r_intr___urun___width 1 -#define reg_iop_fifo_in_r_intr___urun___bit 0 -#define reg_iop_fifo_in_r_intr___last_data___lsb 1 -#define reg_iop_fifo_in_r_intr___last_data___width 1 -#define reg_iop_fifo_in_r_intr___last_data___bit 1 -#define reg_iop_fifo_in_r_intr___dav___lsb 2 -#define reg_iop_fifo_in_r_intr___dav___width 1 -#define reg_iop_fifo_in_r_intr___dav___bit 2 -#define reg_iop_fifo_in_r_intr___avail___lsb 3 -#define reg_iop_fifo_in_r_intr___avail___width 1 -#define reg_iop_fifo_in_r_intr___avail___bit 3 -#define reg_iop_fifo_in_r_intr___orun___lsb 4 -#define reg_iop_fifo_in_r_intr___orun___width 1 -#define reg_iop_fifo_in_r_intr___orun___bit 4 -#define reg_iop_fifo_in_r_intr_offset 60 - -/* Register r_masked_intr, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_in_r_masked_intr___urun___width 1 -#define reg_iop_fifo_in_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_in_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_in_r_masked_intr___dav___width 1 -#define reg_iop_fifo_in_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3 -#define reg_iop_fifo_in_r_masked_intr___avail___width 1 -#define reg_iop_fifo_in_r_masked_intr___avail___bit 3 -#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_in_r_masked_intr___orun___width 1 -#define reg_iop_fifo_in_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_in_r_masked_intr_offset 64 - - -/* Constants */ -#define regk_iop_fifo_in_dif_in 0x00000002 -#define regk_iop_fifo_in_hi 0x00000000 -#define regk_iop_fifo_in_neg 0x00000002 -#define regk_iop_fifo_in_no 0x00000000 -#define regk_iop_fifo_in_order16 0x00000001 -#define regk_iop_fifo_in_order24 0x00000002 -#define regk_iop_fifo_in_order32 0x00000003 -#define regk_iop_fifo_in_order8 0x00000000 -#define regk_iop_fifo_in_pos 0x00000001 -#define regk_iop_fifo_in_pos_neg 0x00000003 -#define regk_iop_fifo_in_rw_cfg_default 0x00000024 -#define regk_iop_fifo_in_rw_ctrl_default 0x00000000 -#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_in_rw_set_last_default 0x00000000 -#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000 -#define regk_iop_fifo_in_size16 0x00000002 -#define regk_iop_fifo_in_size24 0x00000001 -#define regk_iop_fifo_in_size32 0x00000000 -#define regk_iop_fifo_in_size8 0x00000003 -#define regk_iop_fifo_in_yes 0x00000001 -#endif /* __iop_fifo_in_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h deleted file mode 100644 index e00fab0c9335..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef __iop_fifo_in_extra_defs_asm_h -#define __iop_fifo_in_extra_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: - * last modfied: Mon Apr 11 16:10:08 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_wr_data_offset 0 - -/* Register r_stat, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_in_extra_r_stat___last___lsb 4 -#define reg_iop_fifo_in_extra_r_stat___last___width 8 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_in_extra_r_stat_offset 4 - -/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0 -#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2 -#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8 - -/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12 - -/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16 - -/* Register r_intr, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_r_intr___urun___width 1 -#define reg_iop_fifo_in_extra_r_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_r_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_r_intr___dav___width 1 -#define reg_iop_fifo_in_extra_r_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_r_intr___avail___width 1 -#define reg_iop_fifo_in_extra_r_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_r_intr___orun___width 1 -#define reg_iop_fifo_in_extra_r_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_r_intr_offset 20 - -/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_r_masked_intr_offset 24 - - -/* Constants */ -#define regk_iop_fifo_in_extra_fifo_in 0x00000002 -#define regk_iop_fifo_in_extra_no 0x00000000 -#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_in_extra_yes 0x00000001 -#endif /* __iop_fifo_in_extra_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h deleted file mode 100644 index 9ec5f4a826df..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h +++ /dev/null @@ -1,254 +0,0 @@ -#ifndef __iop_fifo_out_defs_asm_h -#define __iop_fifo_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out.r - * id: - * last modfied: Mon Apr 11 16:10:09 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r - * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0 -#define reg_iop_fifo_out_rw_cfg___free_lim___width 3 -#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3 -#define reg_iop_fifo_out_rw_cfg___byte_order___width 2 -#define reg_iop_fifo_out_rw_cfg___trig___lsb 5 -#define reg_iop_fifo_out_rw_cfg___trig___width 2 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7 -#define reg_iop_fifo_out_rw_cfg___mode___lsb 8 -#define reg_iop_fifo_out_rw_cfg___mode___width 2 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11 -#define reg_iop_fifo_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1 -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1 -#define reg_iop_fifo_out_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_out_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_out_r_stat___last___lsb 4 -#define reg_iop_fifo_out_r_stat___last___width 8 -#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_out_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_out_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14 -#define reg_iop_fifo_out_r_stat___zero_data_last___width 1 -#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14 -#define reg_iop_fifo_out_r_stat_offset 8 - -/* Register rw_wr1byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr1byte___data___width 8 -#define reg_iop_fifo_out_rw_wr1byte_offset 12 - -/* Register rw_wr2byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr2byte___data___width 16 -#define reg_iop_fifo_out_rw_wr2byte_offset 16 - -/* Register rw_wr3byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr3byte___data___width 24 -#define reg_iop_fifo_out_rw_wr3byte_offset 20 - -/* Register rw_wr4byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr4byte___data___width 32 -#define reg_iop_fifo_out_rw_wr4byte_offset 24 - -/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8 -#define reg_iop_fifo_out_rw_wr1byte_last_offset 28 - -/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16 -#define reg_iop_fifo_out_rw_wr2byte_last_offset 32 - -/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24 -#define reg_iop_fifo_out_rw_wr3byte_last_offset 36 - -/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32 -#define reg_iop_fifo_out_rw_wr4byte_last_offset 40 - -/* Register rw_set_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_set_last_offset 44 - -/* Register rs_rd_data, scope iop_fifo_out, type rs */ -#define reg_iop_fifo_out_rs_rd_data_offset 48 - -/* Register r_rd_data, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_rd_data_offset 52 - -/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_strb_dif_out_offset 56 - -/* Register rw_intr_mask, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_out_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_out_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3 -#define reg_iop_fifo_out_rw_intr_mask___free___width 1 -#define reg_iop_fifo_out_rw_intr_mask___free___bit 3 -#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_out_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_out_rw_intr_mask_offset 60 - -/* Register rw_ack_intr, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_out_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_out_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3 -#define reg_iop_fifo_out_rw_ack_intr___free___width 1 -#define reg_iop_fifo_out_rw_ack_intr___free___bit 3 -#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_out_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_out_rw_ack_intr_offset 64 - -/* Register r_intr, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_intr___urun___lsb 0 -#define reg_iop_fifo_out_r_intr___urun___width 1 -#define reg_iop_fifo_out_r_intr___urun___bit 0 -#define reg_iop_fifo_out_r_intr___last_data___lsb 1 -#define reg_iop_fifo_out_r_intr___last_data___width 1 -#define reg_iop_fifo_out_r_intr___last_data___bit 1 -#define reg_iop_fifo_out_r_intr___dav___lsb 2 -#define reg_iop_fifo_out_r_intr___dav___width 1 -#define reg_iop_fifo_out_r_intr___dav___bit 2 -#define reg_iop_fifo_out_r_intr___free___lsb 3 -#define reg_iop_fifo_out_r_intr___free___width 1 -#define reg_iop_fifo_out_r_intr___free___bit 3 -#define reg_iop_fifo_out_r_intr___orun___lsb 4 -#define reg_iop_fifo_out_r_intr___orun___width 1 -#define reg_iop_fifo_out_r_intr___orun___bit 4 -#define reg_iop_fifo_out_r_intr_offset 68 - -/* Register r_masked_intr, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_out_r_masked_intr___urun___width 1 -#define reg_iop_fifo_out_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_out_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_out_r_masked_intr___dav___width 1 -#define reg_iop_fifo_out_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_out_r_masked_intr___free___lsb 3 -#define reg_iop_fifo_out_r_masked_intr___free___width 1 -#define reg_iop_fifo_out_r_masked_intr___free___bit 3 -#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_out_r_masked_intr___orun___width 1 -#define reg_iop_fifo_out_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_out_r_masked_intr_offset 72 - - -/* Constants */ -#define regk_iop_fifo_out_hi 0x00000000 -#define regk_iop_fifo_out_neg 0x00000002 -#define regk_iop_fifo_out_no 0x00000000 -#define regk_iop_fifo_out_order16 0x00000001 -#define regk_iop_fifo_out_order24 0x00000002 -#define regk_iop_fifo_out_order32 0x00000003 -#define regk_iop_fifo_out_order8 0x00000000 -#define regk_iop_fifo_out_pos 0x00000001 -#define regk_iop_fifo_out_pos_neg 0x00000003 -#define regk_iop_fifo_out_rw_cfg_default 0x00000024 -#define regk_iop_fifo_out_rw_ctrl_default 0x00000000 -#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_out_rw_set_last_default 0x00000000 -#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000 -#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000 -#define regk_iop_fifo_out_size16 0x00000002 -#define regk_iop_fifo_out_size24 0x00000001 -#define regk_iop_fifo_out_size32 0x00000000 -#define regk_iop_fifo_out_size8 0x00000003 -#define regk_iop_fifo_out_yes 0x00000001 -#endif /* __iop_fifo_out_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h deleted file mode 100644 index 0f84a50cf77c..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h +++ /dev/null @@ -1,158 +0,0 @@ -#ifndef __iop_fifo_out_extra_defs_asm_h -#define __iop_fifo_out_extra_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: - * last modfied: Mon Apr 11 16:10:10 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ -#define reg_iop_fifo_out_extra_rs_rd_data_offset 0 - -/* Register r_rd_data, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_rd_data_offset 4 - -/* Register r_stat, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_out_extra_r_stat___last___lsb 4 -#define reg_iop_fifo_out_extra_r_stat___last___width 8 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14 -#define reg_iop_fifo_out_extra_r_stat_offset 8 - -/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12 - -/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20 - -/* Register r_intr, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_r_intr___urun___width 1 -#define reg_iop_fifo_out_extra_r_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_r_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_r_intr___dav___width 1 -#define reg_iop_fifo_out_extra_r_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_r_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_r_intr___free___width 1 -#define reg_iop_fifo_out_extra_r_intr___free___bit 3 -#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_r_intr___orun___width 1 -#define reg_iop_fifo_out_extra_r_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_r_intr_offset 24 - -/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_r_masked_intr_offset 28 - - -/* Constants */ -#define regk_iop_fifo_out_extra_no 0x00000000 -#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_out_extra_yes 0x00000001 -#endif /* __iop_fifo_out_extra_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h deleted file mode 100644 index 80490c82cc29..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h +++ /dev/null @@ -1,177 +0,0 @@ -#ifndef __iop_mpu_defs_asm_h -#define __iop_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_mpu.r - * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r - * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_mpu_rw_r 4 -/* Register rw_r, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_r_offset 0 - -/* Register rw_ctrl, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_ctrl___en___lsb 0 -#define reg_iop_mpu_rw_ctrl___en___width 1 -#define reg_iop_mpu_rw_ctrl___en___bit 0 -#define reg_iop_mpu_rw_ctrl_offset 128 - -/* Register r_pc, scope iop_mpu, type r */ -#define reg_iop_mpu_r_pc___addr___lsb 0 -#define reg_iop_mpu_r_pc___addr___width 12 -#define reg_iop_mpu_r_pc_offset 132 - -/* Register r_stat, scope iop_mpu, type r */ -#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0 -#define reg_iop_mpu_r_stat___instr_reg_busy___width 1 -#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0 -#define reg_iop_mpu_r_stat___intr_busy___lsb 1 -#define reg_iop_mpu_r_stat___intr_busy___width 1 -#define reg_iop_mpu_r_stat___intr_busy___bit 1 -#define reg_iop_mpu_r_stat___intr_vect___lsb 2 -#define reg_iop_mpu_r_stat___intr_vect___width 16 -#define reg_iop_mpu_r_stat_offset 136 - -/* Register rw_instr, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_instr_offset 140 - -/* Register rw_immediate, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_immediate_offset 144 - -/* Register r_trace, scope iop_mpu, type r */ -#define reg_iop_mpu_r_trace___intr_vect___lsb 0 -#define reg_iop_mpu_r_trace___intr_vect___width 16 -#define reg_iop_mpu_r_trace___pc___lsb 16 -#define reg_iop_mpu_r_trace___pc___width 12 -#define reg_iop_mpu_r_trace___en___lsb 28 -#define reg_iop_mpu_r_trace___en___width 1 -#define reg_iop_mpu_r_trace___en___bit 28 -#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29 -#define reg_iop_mpu_r_trace___instr_reg_busy___width 1 -#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29 -#define reg_iop_mpu_r_trace___intr_busy___lsb 30 -#define reg_iop_mpu_r_trace___intr_busy___width 1 -#define reg_iop_mpu_r_trace___intr_busy___bit 30 -#define reg_iop_mpu_r_trace_offset 148 - -/* Register r_wr_stat, scope iop_mpu, type r */ -#define reg_iop_mpu_r_wr_stat___r0___lsb 0 -#define reg_iop_mpu_r_wr_stat___r0___width 1 -#define reg_iop_mpu_r_wr_stat___r0___bit 0 -#define reg_iop_mpu_r_wr_stat___r1___lsb 1 -#define reg_iop_mpu_r_wr_stat___r1___width 1 -#define reg_iop_mpu_r_wr_stat___r1___bit 1 -#define reg_iop_mpu_r_wr_stat___r2___lsb 2 -#define reg_iop_mpu_r_wr_stat___r2___width 1 -#define reg_iop_mpu_r_wr_stat___r2___bit 2 -#define reg_iop_mpu_r_wr_stat___r3___lsb 3 -#define reg_iop_mpu_r_wr_stat___r3___width 1 -#define reg_iop_mpu_r_wr_stat___r3___bit 3 -#define reg_iop_mpu_r_wr_stat___r4___lsb 4 -#define reg_iop_mpu_r_wr_stat___r4___width 1 -#define reg_iop_mpu_r_wr_stat___r4___bit 4 -#define reg_iop_mpu_r_wr_stat___r5___lsb 5 -#define reg_iop_mpu_r_wr_stat___r5___width 1 -#define reg_iop_mpu_r_wr_stat___r5___bit 5 -#define reg_iop_mpu_r_wr_stat___r6___lsb 6 -#define reg_iop_mpu_r_wr_stat___r6___width 1 -#define reg_iop_mpu_r_wr_stat___r6___bit 6 -#define reg_iop_mpu_r_wr_stat___r7___lsb 7 -#define reg_iop_mpu_r_wr_stat___r7___width 1 -#define reg_iop_mpu_r_wr_stat___r7___bit 7 -#define reg_iop_mpu_r_wr_stat___r8___lsb 8 -#define reg_iop_mpu_r_wr_stat___r8___width 1 -#define reg_iop_mpu_r_wr_stat___r8___bit 8 -#define reg_iop_mpu_r_wr_stat___r9___lsb 9 -#define reg_iop_mpu_r_wr_stat___r9___width 1 -#define reg_iop_mpu_r_wr_stat___r9___bit 9 -#define reg_iop_mpu_r_wr_stat___r10___lsb 10 -#define reg_iop_mpu_r_wr_stat___r10___width 1 -#define reg_iop_mpu_r_wr_stat___r10___bit 10 -#define reg_iop_mpu_r_wr_stat___r11___lsb 11 -#define reg_iop_mpu_r_wr_stat___r11___width 1 -#define reg_iop_mpu_r_wr_stat___r11___bit 11 -#define reg_iop_mpu_r_wr_stat___r12___lsb 12 -#define reg_iop_mpu_r_wr_stat___r12___width 1 -#define reg_iop_mpu_r_wr_stat___r12___bit 12 -#define reg_iop_mpu_r_wr_stat___r13___lsb 13 -#define reg_iop_mpu_r_wr_stat___r13___width 1 -#define reg_iop_mpu_r_wr_stat___r13___bit 13 -#define reg_iop_mpu_r_wr_stat___r14___lsb 14 -#define reg_iop_mpu_r_wr_stat___r14___width 1 -#define reg_iop_mpu_r_wr_stat___r14___bit 14 -#define reg_iop_mpu_r_wr_stat___r15___lsb 15 -#define reg_iop_mpu_r_wr_stat___r15___width 1 -#define reg_iop_mpu_r_wr_stat___r15___bit 15 -#define reg_iop_mpu_r_wr_stat_offset 152 - -#define STRIDE_iop_mpu_rw_thread 4 -/* Register rw_thread, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_thread___addr___lsb 0 -#define reg_iop_mpu_rw_thread___addr___width 12 -#define reg_iop_mpu_rw_thread_offset 156 - -#define STRIDE_iop_mpu_rw_intr 4 -/* Register rw_intr, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_intr___addr___lsb 0 -#define reg_iop_mpu_rw_intr___addr___width 12 -#define reg_iop_mpu_rw_intr_offset 196 - - -/* Constants */ -#define regk_iop_mpu_no 0x00000000 -#define regk_iop_mpu_r_pc_default 0x00000000 -#define regk_iop_mpu_rw_ctrl_default 0x00000000 -#define regk_iop_mpu_rw_intr_size 0x00000010 -#define regk_iop_mpu_rw_r_size 0x00000010 -#define regk_iop_mpu_rw_thread_default 0x00000000 -#define regk_iop_mpu_rw_thread_size 0x00000004 -#define regk_iop_mpu_yes 0x00000001 -#endif /* __iop_mpu_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index a20b8857b4d0..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg - */ -#define iop_version 0 -#define iop_fifo_in0_extra 64 -#define iop_fifo_in1_extra 128 -#define iop_fifo_out0_extra 192 -#define iop_fifo_out1_extra 256 -#define iop_trigger_grp0 320 -#define iop_trigger_grp1 384 -#define iop_trigger_grp2 448 -#define iop_trigger_grp3 512 -#define iop_trigger_grp4 576 -#define iop_trigger_grp5 640 -#define iop_trigger_grp6 704 -#define iop_trigger_grp7 768 -#define iop_crc_par0 896 -#define iop_crc_par1 1024 -#define iop_dmc_in0 1152 -#define iop_dmc_in1 1280 -#define iop_dmc_out0 1408 -#define iop_dmc_out1 1536 -#define iop_fifo_in0 1664 -#define iop_fifo_in1 1792 -#define iop_fifo_out0 1920 -#define iop_fifo_out1 2048 -#define iop_scrc_in0 2176 -#define iop_scrc_in1 2304 -#define iop_scrc_out0 2432 -#define iop_scrc_out1 2560 -#define iop_timer_grp0 2688 -#define iop_timer_grp1 2816 -#define iop_timer_grp2 2944 -#define iop_timer_grp3 3072 -#define iop_sap_in 3328 -#define iop_sap_out 3584 -#define iop_spu0 3840 -#define iop_spu1 4096 -#define iop_sw_cfg 4352 -#define iop_sw_cpu 4608 -#define iop_sw_mpu 4864 -#define iop_sw_spu0 5120 -#define iop_sw_spu1 5376 -#define iop_mpu 5632 diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index a4a10ff300b3..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null @@ -1,182 +0,0 @@ -#ifndef __iop_sap_in_defs_asm_h -#define __iop_sap_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_in.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r - * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_bus0_sync, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0 -#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5 -#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7 -#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8 -#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10 -#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13 -#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15 -#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16 -#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18 -#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21 -#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23 -#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24 -#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26 -#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29 -#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31 -#define reg_iop_sap_in_rw_bus0_sync_offset 0 - -/* Register rw_bus1_sync, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0 -#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5 -#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7 -#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8 -#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10 -#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13 -#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15 -#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16 -#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18 -#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21 -#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23 -#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24 -#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26 -#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29 -#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31 -#define reg_iop_sap_in_rw_bus1_sync_offset 4 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_gio___sync_sel___width 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_gio___sync_edge___width 2 -#define reg_iop_sap_in_rw_gio___delay___lsb 7 -#define reg_iop_sap_in_rw_gio___delay___width 1 -#define reg_iop_sap_in_rw_gio___delay___bit 7 -#define reg_iop_sap_in_rw_gio___logic___lsb 8 -#define reg_iop_sap_in_rw_gio___logic___width 2 -#define reg_iop_sap_in_rw_gio_offset 8 - - -/* Constants */ -#define regk_iop_sap_in_and 0x00000002 -#define regk_iop_sap_in_ext_clk200 0x00000003 -#define regk_iop_sap_in_gio1 0x00000000 -#define regk_iop_sap_in_gio13 0x00000005 -#define regk_iop_sap_in_gio18 0x00000003 -#define regk_iop_sap_in_gio19 0x00000004 -#define regk_iop_sap_in_gio21 0x00000006 -#define regk_iop_sap_in_gio23 0x00000005 -#define regk_iop_sap_in_gio29 0x00000007 -#define regk_iop_sap_in_gio5 0x00000004 -#define regk_iop_sap_in_gio6 0x00000001 -#define regk_iop_sap_in_gio7 0x00000002 -#define regk_iop_sap_in_inv 0x00000001 -#define regk_iop_sap_in_neg 0x00000002 -#define regk_iop_sap_in_no 0x00000000 -#define regk_iop_sap_in_no_del_ext_clk200 0x00000001 -#define regk_iop_sap_in_none 0x00000000 -#define regk_iop_sap_in_or 0x00000003 -#define regk_iop_sap_in_pos 0x00000001 -#define regk_iop_sap_in_pos_neg 0x00000003 -#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202 -#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202 -#define regk_iop_sap_in_rw_gio_default 0x00000002 -#define regk_iop_sap_in_rw_gio_size 0x00000020 -#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006 -#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004 -#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005 -#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007 -#define regk_iop_sap_in_tmr_clk200 0x00000000 -#define regk_iop_sap_in_two_clk200 0x00000002 -#define regk_iop_sap_in_yes 0x00000001 -#endif /* __iop_sap_in_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index 0ec727f92a25..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef __iop_sap_out_defs_asm_h -#define __iop_sap_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_out.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r - * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 -#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14 -#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16 -#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18 -#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21 -#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23 -#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25 -#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated_offset 0 - -/* Register rw_bus0, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3 -#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6 -#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9 -#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11 -#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17 -#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18 -#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21 -#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23 -#define reg_iop_sap_out_rw_bus0_offset 4 - -/* Register rw_bus1, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3 -#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6 -#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9 -#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11 -#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17 -#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18 -#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21 -#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23 -#define reg_iop_sap_out_rw_bus1_offset 8 - -/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12 - -/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16 - -/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20 - -/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4 -#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7 -#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2 -#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9 -#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9 -#define reg_iop_sap_out_rw_gio___out_logic___lsb 10 -#define reg_iop_sap_out_rw_gio___out_logic___width 1 -#define reg_iop_sap_out_rw_gio___out_logic___bit 10 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19 -#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 -#define reg_iop_sap_out_rw_gio___oe_logic___width 2 -#define reg_iop_sap_out_rw_gio_offset 28 - - -/* Constants */ -#define regk_iop_sap_out_and 0x00000002 -#define regk_iop_sap_out_clk0 0x00000000 -#define regk_iop_sap_out_clk1 0x00000001 -#define regk_iop_sap_out_clk12 0x00000002 -#define regk_iop_sap_out_clk2 0x00000002 -#define regk_iop_sap_out_clk200 0x00000001 -#define regk_iop_sap_out_clk3 0x00000003 -#define regk_iop_sap_out_ext 0x00000003 -#define regk_iop_sap_out_gated 0x00000004 -#define regk_iop_sap_out_gio1 0x00000000 -#define regk_iop_sap_out_gio13 0x00000002 -#define regk_iop_sap_out_gio13_clk 0x0000000c -#define regk_iop_sap_out_gio15 0x00000001 -#define regk_iop_sap_out_gio18 0x00000003 -#define regk_iop_sap_out_gio18_clk 0x0000000d -#define regk_iop_sap_out_gio1_clk 0x00000008 -#define regk_iop_sap_out_gio21_clk 0x0000000e -#define regk_iop_sap_out_gio23 0x00000002 -#define regk_iop_sap_out_gio29_clk 0x0000000f -#define regk_iop_sap_out_gio31 0x00000003 -#define regk_iop_sap_out_gio5 0x00000001 -#define regk_iop_sap_out_gio5_clk 0x00000009 -#define regk_iop_sap_out_gio6_clk 0x0000000a -#define regk_iop_sap_out_gio7 0x00000000 -#define regk_iop_sap_out_gio7_clk 0x0000000b -#define regk_iop_sap_out_gio_in13 0x00000001 -#define regk_iop_sap_out_gio_in21 0x00000002 -#define regk_iop_sap_out_gio_in29 0x00000003 -#define regk_iop_sap_out_gio_in5 0x00000000 -#define regk_iop_sap_out_inv 0x00000001 -#define regk_iop_sap_out_nand 0x00000003 -#define regk_iop_sap_out_no 0x00000000 -#define regk_iop_sap_out_none 0x00000000 -#define regk_iop_sap_out_rw_bus0_default 0x00000000 -#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 -#define regk_iop_sap_out_rw_gio_default 0x00000000 -#define regk_iop_sap_out_rw_gio_size 0x00000020 -#define regk_iop_sap_out_spu0_gio0 0x00000002 -#define regk_iop_sap_out_spu0_gio1 0x00000003 -#define regk_iop_sap_out_spu0_gio12 0x00000004 -#define regk_iop_sap_out_spu0_gio13 0x00000004 -#define regk_iop_sap_out_spu0_gio14 0x00000004 -#define regk_iop_sap_out_spu0_gio15 0x00000004 -#define regk_iop_sap_out_spu0_gio2 0x00000002 -#define regk_iop_sap_out_spu0_gio3 0x00000003 -#define regk_iop_sap_out_spu0_gio4 0x00000002 -#define regk_iop_sap_out_spu0_gio5 0x00000003 -#define regk_iop_sap_out_spu0_gio6 0x00000002 -#define regk_iop_sap_out_spu0_gio7 0x00000003 -#define regk_iop_sap_out_spu1_gio0 0x00000005 -#define regk_iop_sap_out_spu1_gio1 0x00000006 -#define regk_iop_sap_out_spu1_gio12 0x00000007 -#define regk_iop_sap_out_spu1_gio13 0x00000007 -#define regk_iop_sap_out_spu1_gio14 0x00000007 -#define regk_iop_sap_out_spu1_gio15 0x00000007 -#define regk_iop_sap_out_spu1_gio2 0x00000005 -#define regk_iop_sap_out_spu1_gio3 0x00000006 -#define regk_iop_sap_out_spu1_gio4 0x00000005 -#define regk_iop_sap_out_spu1_gio5 0x00000006 -#define regk_iop_sap_out_spu1_gio6 0x00000005 -#define regk_iop_sap_out_spu1_gio7 0x00000006 -#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004 -#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005 -#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006 -#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007 -#define regk_iop_sap_out_tmr 0x00000005 -#define regk_iop_sap_out_yes 0x00000001 -#endif /* __iop_sap_out_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h deleted file mode 100644 index 2cf5721597fc..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h +++ /dev/null @@ -1,111 +0,0 @@ -#ifndef __iop_scrc_in_defs_asm_h -#define __iop_scrc_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_in.r - * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r - * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_cfg___trig___lsb 0 -#define reg_iop_scrc_in_rw_cfg___trig___width 2 -#define reg_iop_scrc_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1 -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_scrc_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_scrc_in, type r */ -#define reg_iop_scrc_in_r_stat___err___lsb 0 -#define reg_iop_scrc_in_r_stat___err___width 1 -#define reg_iop_scrc_in_r_stat___err___bit 0 -#define reg_iop_scrc_in_r_stat_offset 8 - -/* Register rw_init_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_init_crc_offset 12 - -/* Register rs_computed_crc, scope iop_scrc_in, type rs */ -#define reg_iop_scrc_in_rs_computed_crc_offset 16 - -/* Register r_computed_crc, scope iop_scrc_in, type r */ -#define reg_iop_scrc_in_r_computed_crc_offset 20 - -/* Register rw_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_crc_offset 24 - -/* Register rw_correct_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_correct_crc_offset 28 - -/* Register rw_wr1bit, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0 -#define reg_iop_scrc_in_rw_wr1bit___data___width 2 -#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2 -#define reg_iop_scrc_in_rw_wr1bit___last___width 2 -#define reg_iop_scrc_in_rw_wr1bit_offset 32 - - -/* Constants */ -#define regk_iop_scrc_in_dif_in 0x00000002 -#define regk_iop_scrc_in_hi 0x00000000 -#define regk_iop_scrc_in_neg 0x00000002 -#define regk_iop_scrc_in_no 0x00000000 -#define regk_iop_scrc_in_pos 0x00000001 -#define regk_iop_scrc_in_pos_neg 0x00000003 -#define regk_iop_scrc_in_r_computed_crc_default 0x00000000 -#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000 -#define regk_iop_scrc_in_rw_cfg_default 0x00000000 -#define regk_iop_scrc_in_rw_ctrl_default 0x00000000 -#define regk_iop_scrc_in_rw_init_crc_default 0x00000000 -#define regk_iop_scrc_in_set0 0x00000000 -#define regk_iop_scrc_in_set1 0x00000001 -#define regk_iop_scrc_in_yes 0x00000001 -#endif /* __iop_scrc_in_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h deleted file mode 100644 index 640a25725f20..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h +++ /dev/null @@ -1,105 +0,0 @@ -#ifndef __iop_scrc_out_defs_asm_h -#define __iop_scrc_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_out.r - * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r - * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_cfg___trig___lsb 0 -#define reg_iop_scrc_out_rw_cfg___trig___width 2 -#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2 -#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1 -#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2 -#define reg_iop_scrc_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0 -#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1 -#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0 -#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1 -#define reg_iop_scrc_out_rw_ctrl___out_src___width 1 -#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1 -#define reg_iop_scrc_out_rw_ctrl_offset 4 - -/* Register rw_init_crc, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_init_crc_offset 8 - -/* Register rw_crc, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_crc_offset 12 - -/* Register rw_data, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_data___val___lsb 0 -#define reg_iop_scrc_out_rw_data___val___width 1 -#define reg_iop_scrc_out_rw_data___val___bit 0 -#define reg_iop_scrc_out_rw_data_offset 16 - -/* Register r_computed_crc, scope iop_scrc_out, type r */ -#define reg_iop_scrc_out_r_computed_crc_offset 20 - - -/* Constants */ -#define regk_iop_scrc_out_crc 0x00000001 -#define regk_iop_scrc_out_data 0x00000000 -#define regk_iop_scrc_out_dif 0x00000001 -#define regk_iop_scrc_out_hi 0x00000000 -#define regk_iop_scrc_out_neg 0x00000002 -#define regk_iop_scrc_out_no 0x00000000 -#define regk_iop_scrc_out_pos 0x00000001 -#define regk_iop_scrc_out_pos_neg 0x00000003 -#define regk_iop_scrc_out_reg 0x00000000 -#define regk_iop_scrc_out_rw_cfg_default 0x00000000 -#define regk_iop_scrc_out_rw_crc_default 0x00000000 -#define regk_iop_scrc_out_rw_ctrl_default 0x00000000 -#define regk_iop_scrc_out_rw_data_default 0x00000000 -#define regk_iop_scrc_out_rw_init_crc_default 0x00000000 -#define regk_iop_scrc_out_yes 0x00000001 -#endif /* __iop_scrc_out_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h deleted file mode 100644 index bb402c1aa761..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h +++ /dev/null @@ -1,573 +0,0 @@ -#ifndef __iop_spu_defs_asm_h -#define __iop_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_spu.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r - * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_spu_rw_r 4 -/* Register rw_r, scope iop_spu, type rw */ -#define reg_iop_spu_rw_r_offset 0 - -/* Register rw_seq_pc, scope iop_spu, type rw */ -#define reg_iop_spu_rw_seq_pc___addr___lsb 0 -#define reg_iop_spu_rw_seq_pc___addr___width 12 -#define reg_iop_spu_rw_seq_pc_offset 64 - -/* Register rw_fsm_pc, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_pc___addr___lsb 0 -#define reg_iop_spu_rw_fsm_pc___addr___width 12 -#define reg_iop_spu_rw_fsm_pc_offset 68 - -/* Register rw_ctrl, scope iop_spu, type rw */ -#define reg_iop_spu_rw_ctrl___fsm___lsb 0 -#define reg_iop_spu_rw_ctrl___fsm___width 1 -#define reg_iop_spu_rw_ctrl___fsm___bit 0 -#define reg_iop_spu_rw_ctrl___en___lsb 1 -#define reg_iop_spu_rw_ctrl___en___width 1 -#define reg_iop_spu_rw_ctrl___en___bit 1 -#define reg_iop_spu_rw_ctrl_offset 72 - -/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0 -#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8 -#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13 -#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16 -#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21 -#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24 -#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29 -#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0_offset 76 - -/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0 -#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8 -#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13 -#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16 -#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21 -#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24 -#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29 -#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4_offset 80 - -/* Register rw_gio_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_offset 84 - -/* Register rw_bus0_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_bus0_out_offset 88 - -/* Register rw_bus1_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_bus1_out_offset 92 - -/* Register r_gio_in, scope iop_spu, type r */ -#define reg_iop_spu_r_gio_in_offset 96 - -/* Register r_bus0_in, scope iop_spu, type r */ -#define reg_iop_spu_r_bus0_in_offset 100 - -/* Register r_bus1_in, scope iop_spu, type r */ -#define reg_iop_spu_r_bus1_in_offset 104 - -/* Register rw_gio_out_set, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_set_offset 108 - -/* Register rw_gio_out_clr, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_clr_offset 112 - -/* Register rs_wr_stat, scope iop_spu, type rs */ -#define reg_iop_spu_rs_wr_stat___r0___lsb 0 -#define reg_iop_spu_rs_wr_stat___r0___width 1 -#define reg_iop_spu_rs_wr_stat___r0___bit 0 -#define reg_iop_spu_rs_wr_stat___r1___lsb 1 -#define reg_iop_spu_rs_wr_stat___r1___width 1 -#define reg_iop_spu_rs_wr_stat___r1___bit 1 -#define reg_iop_spu_rs_wr_stat___r2___lsb 2 -#define reg_iop_spu_rs_wr_stat___r2___width 1 -#define reg_iop_spu_rs_wr_stat___r2___bit 2 -#define reg_iop_spu_rs_wr_stat___r3___lsb 3 -#define reg_iop_spu_rs_wr_stat___r3___width 1 -#define reg_iop_spu_rs_wr_stat___r3___bit 3 -#define reg_iop_spu_rs_wr_stat___r4___lsb 4 -#define reg_iop_spu_rs_wr_stat___r4___width 1 -#define reg_iop_spu_rs_wr_stat___r4___bit 4 -#define reg_iop_spu_rs_wr_stat___r5___lsb 5 -#define reg_iop_spu_rs_wr_stat___r5___width 1 -#define reg_iop_spu_rs_wr_stat___r5___bit 5 -#define reg_iop_spu_rs_wr_stat___r6___lsb 6 -#define reg_iop_spu_rs_wr_stat___r6___width 1 -#define reg_iop_spu_rs_wr_stat___r6___bit 6 -#define reg_iop_spu_rs_wr_stat___r7___lsb 7 -#define reg_iop_spu_rs_wr_stat___r7___width 1 -#define reg_iop_spu_rs_wr_stat___r7___bit 7 -#define reg_iop_spu_rs_wr_stat___r8___lsb 8 -#define reg_iop_spu_rs_wr_stat___r8___width 1 -#define reg_iop_spu_rs_wr_stat___r8___bit 8 -#define reg_iop_spu_rs_wr_stat___r9___lsb 9 -#define reg_iop_spu_rs_wr_stat___r9___width 1 -#define reg_iop_spu_rs_wr_stat___r9___bit 9 -#define reg_iop_spu_rs_wr_stat___r10___lsb 10 -#define reg_iop_spu_rs_wr_stat___r10___width 1 -#define reg_iop_spu_rs_wr_stat___r10___bit 10 -#define reg_iop_spu_rs_wr_stat___r11___lsb 11 -#define reg_iop_spu_rs_wr_stat___r11___width 1 -#define reg_iop_spu_rs_wr_stat___r11___bit 11 -#define reg_iop_spu_rs_wr_stat___r12___lsb 12 -#define reg_iop_spu_rs_wr_stat___r12___width 1 -#define reg_iop_spu_rs_wr_stat___r12___bit 12 -#define reg_iop_spu_rs_wr_stat___r13___lsb 13 -#define reg_iop_spu_rs_wr_stat___r13___width 1 -#define reg_iop_spu_rs_wr_stat___r13___bit 13 -#define reg_iop_spu_rs_wr_stat___r14___lsb 14 -#define reg_iop_spu_rs_wr_stat___r14___width 1 -#define reg_iop_spu_rs_wr_stat___r14___bit 14 -#define reg_iop_spu_rs_wr_stat___r15___lsb 15 -#define reg_iop_spu_rs_wr_stat___r15___width 1 -#define reg_iop_spu_rs_wr_stat___r15___bit 15 -#define reg_iop_spu_rs_wr_stat_offset 116 - -/* Register r_wr_stat, scope iop_spu, type r */ -#define reg_iop_spu_r_wr_stat___r0___lsb 0 -#define reg_iop_spu_r_wr_stat___r0___width 1 -#define reg_iop_spu_r_wr_stat___r0___bit 0 -#define reg_iop_spu_r_wr_stat___r1___lsb 1 -#define reg_iop_spu_r_wr_stat___r1___width 1 -#define reg_iop_spu_r_wr_stat___r1___bit 1 -#define reg_iop_spu_r_wr_stat___r2___lsb 2 -#define reg_iop_spu_r_wr_stat___r2___width 1 -#define reg_iop_spu_r_wr_stat___r2___bit 2 -#define reg_iop_spu_r_wr_stat___r3___lsb 3 -#define reg_iop_spu_r_wr_stat___r3___width 1 -#define reg_iop_spu_r_wr_stat___r3___bit 3 -#define reg_iop_spu_r_wr_stat___r4___lsb 4 -#define reg_iop_spu_r_wr_stat___r4___width 1 -#define reg_iop_spu_r_wr_stat___r4___bit 4 -#define reg_iop_spu_r_wr_stat___r5___lsb 5 -#define reg_iop_spu_r_wr_stat___r5___width 1 -#define reg_iop_spu_r_wr_stat___r5___bit 5 -#define reg_iop_spu_r_wr_stat___r6___lsb 6 -#define reg_iop_spu_r_wr_stat___r6___width 1 -#define reg_iop_spu_r_wr_stat___r6___bit 6 -#define reg_iop_spu_r_wr_stat___r7___lsb 7 -#define reg_iop_spu_r_wr_stat___r7___width 1 -#define reg_iop_spu_r_wr_stat___r7___bit 7 -#define reg_iop_spu_r_wr_stat___r8___lsb 8 -#define reg_iop_spu_r_wr_stat___r8___width 1 -#define reg_iop_spu_r_wr_stat___r8___bit 8 -#define reg_iop_spu_r_wr_stat___r9___lsb 9 -#define reg_iop_spu_r_wr_stat___r9___width 1 -#define reg_iop_spu_r_wr_stat___r9___bit 9 -#define reg_iop_spu_r_wr_stat___r10___lsb 10 -#define reg_iop_spu_r_wr_stat___r10___width 1 -#define reg_iop_spu_r_wr_stat___r10___bit 10 -#define reg_iop_spu_r_wr_stat___r11___lsb 11 -#define reg_iop_spu_r_wr_stat___r11___width 1 -#define reg_iop_spu_r_wr_stat___r11___bit 11 -#define reg_iop_spu_r_wr_stat___r12___lsb 12 -#define reg_iop_spu_r_wr_stat___r12___width 1 -#define reg_iop_spu_r_wr_stat___r12___bit 12 -#define reg_iop_spu_r_wr_stat___r13___lsb 13 -#define reg_iop_spu_r_wr_stat___r13___width 1 -#define reg_iop_spu_r_wr_stat___r13___bit 13 -#define reg_iop_spu_r_wr_stat___r14___lsb 14 -#define reg_iop_spu_r_wr_stat___r14___width 1 -#define reg_iop_spu_r_wr_stat___r14___bit 14 -#define reg_iop_spu_r_wr_stat___r15___lsb 15 -#define reg_iop_spu_r_wr_stat___r15___width 1 -#define reg_iop_spu_r_wr_stat___r15___bit 15 -#define reg_iop_spu_r_wr_stat_offset 120 - -/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ -#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124 - -/* Register r_stat_in, scope iop_spu, type r */ -#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0 -#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4 -#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4 -#define reg_iop_spu_r_stat_in___fifo_out_last___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5 -#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6 -#define reg_iop_spu_r_stat_in___fifo_out_all___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7 -#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8 -#define reg_iop_spu_r_stat_in___dmc_out_all___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8 -#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9 -#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9 -#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10 -#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10 -#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11 -#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11 -#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12 -#define reg_iop_spu_r_stat_in___dmc_out_last___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14 -#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15 -#define reg_iop_spu_r_stat_in___pcrc_correct___width 1 -#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15 -#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16 -#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4 -#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20 -#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20 -#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21 -#define reg_iop_spu_r_stat_in___dmc_in_full___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22 -#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23 -#define reg_iop_spu_r_stat_in___spu_gio_out___width 4 -#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27 -#define reg_iop_spu_r_stat_in___sync_clk12___width 1 -#define reg_iop_spu_r_stat_in___sync_clk12___bit 27 -#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28 -#define reg_iop_spu_r_stat_in___scrc_out_data___width 1 -#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28 -#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29 -#define reg_iop_spu_r_stat_in___scrc_in_err___width 1 -#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29 -#define reg_iop_spu_r_stat_in___mc_busy___lsb 30 -#define reg_iop_spu_r_stat_in___mc_busy___width 1 -#define reg_iop_spu_r_stat_in___mc_busy___bit 30 -#define reg_iop_spu_r_stat_in___mc_owned___lsb 31 -#define reg_iop_spu_r_stat_in___mc_owned___width 1 -#define reg_iop_spu_r_stat_in___mc_owned___bit 31 -#define reg_iop_spu_r_stat_in_offset 128 - -/* Register r_trigger_in, scope iop_spu, type r */ -#define reg_iop_spu_r_trigger_in_offset 132 - -/* Register r_special_stat, scope iop_spu, type r */ -#define reg_iop_spu_r_special_stat___c_flag___lsb 0 -#define reg_iop_spu_r_special_stat___c_flag___width 1 -#define reg_iop_spu_r_special_stat___c_flag___bit 0 -#define reg_iop_spu_r_special_stat___v_flag___lsb 1 -#define reg_iop_spu_r_special_stat___v_flag___width 1 -#define reg_iop_spu_r_special_stat___v_flag___bit 1 -#define reg_iop_spu_r_special_stat___z_flag___lsb 2 -#define reg_iop_spu_r_special_stat___z_flag___width 1 -#define reg_iop_spu_r_special_stat___z_flag___bit 2 -#define reg_iop_spu_r_special_stat___n_flag___lsb 3 -#define reg_iop_spu_r_special_stat___n_flag___width 1 -#define reg_iop_spu_r_special_stat___n_flag___bit 3 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7 -#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8 -#define reg_iop_spu_r_special_stat___fsm_in0___width 1 -#define reg_iop_spu_r_special_stat___fsm_in0___bit 8 -#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9 -#define reg_iop_spu_r_special_stat___fsm_in1___width 1 -#define reg_iop_spu_r_special_stat___fsm_in1___bit 9 -#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10 -#define reg_iop_spu_r_special_stat___fsm_in2___width 1 -#define reg_iop_spu_r_special_stat___fsm_in2___bit 10 -#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11 -#define reg_iop_spu_r_special_stat___fsm_in3___width 1 -#define reg_iop_spu_r_special_stat___fsm_in3___bit 11 -#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12 -#define reg_iop_spu_r_special_stat___fsm_in4___width 1 -#define reg_iop_spu_r_special_stat___fsm_in4___bit 12 -#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13 -#define reg_iop_spu_r_special_stat___fsm_in5___width 1 -#define reg_iop_spu_r_special_stat___fsm_in5___bit 13 -#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14 -#define reg_iop_spu_r_special_stat___fsm_in6___width 1 -#define reg_iop_spu_r_special_stat___fsm_in6___bit 14 -#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15 -#define reg_iop_spu_r_special_stat___fsm_in7___width 1 -#define reg_iop_spu_r_special_stat___fsm_in7___bit 15 -#define reg_iop_spu_r_special_stat___event0___lsb 16 -#define reg_iop_spu_r_special_stat___event0___width 1 -#define reg_iop_spu_r_special_stat___event0___bit 16 -#define reg_iop_spu_r_special_stat___event1___lsb 17 -#define reg_iop_spu_r_special_stat___event1___width 1 -#define reg_iop_spu_r_special_stat___event1___bit 17 -#define reg_iop_spu_r_special_stat___event2___lsb 18 -#define reg_iop_spu_r_special_stat___event2___width 1 -#define reg_iop_spu_r_special_stat___event2___bit 18 -#define reg_iop_spu_r_special_stat___event3___lsb 19 -#define reg_iop_spu_r_special_stat___event3___width 1 -#define reg_iop_spu_r_special_stat___event3___bit 19 -#define reg_iop_spu_r_special_stat_offset 136 - -/* Register rw_reg_access, scope iop_spu, type rw */ -#define reg_iop_spu_rw_reg_access___addr___lsb 0 -#define reg_iop_spu_rw_reg_access___addr___width 13 -#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16 -#define reg_iop_spu_rw_reg_access___imm_hi___width 16 -#define reg_iop_spu_rw_reg_access_offset 140 - -#define STRIDE_iop_spu_rw_event_cfg 4 -/* Register rw_event_cfg, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_cfg___addr___lsb 0 -#define reg_iop_spu_rw_event_cfg___addr___width 12 -#define reg_iop_spu_rw_event_cfg___src___lsb 12 -#define reg_iop_spu_rw_event_cfg___src___width 2 -#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14 -#define reg_iop_spu_rw_event_cfg___eq_en___width 1 -#define reg_iop_spu_rw_event_cfg___eq_en___bit 14 -#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15 -#define reg_iop_spu_rw_event_cfg___eq_inv___width 1 -#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15 -#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16 -#define reg_iop_spu_rw_event_cfg___gt_en___width 1 -#define reg_iop_spu_rw_event_cfg___gt_en___bit 16 -#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17 -#define reg_iop_spu_rw_event_cfg___gt_inv___width 1 -#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17 -#define reg_iop_spu_rw_event_cfg_offset 144 - -#define STRIDE_iop_spu_rw_event_mask 4 -/* Register rw_event_mask, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_mask_offset 160 - -#define STRIDE_iop_spu_rw_event_val 4 -/* Register rw_event_val, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_val_offset 176 - -/* Register rw_event_ret, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_ret___addr___lsb 0 -#define reg_iop_spu_rw_event_ret___addr___width 12 -#define reg_iop_spu_rw_event_ret_offset 192 - -/* Register r_trace, scope iop_spu, type r */ -#define reg_iop_spu_r_trace___fsm___lsb 0 -#define reg_iop_spu_r_trace___fsm___width 1 -#define reg_iop_spu_r_trace___fsm___bit 0 -#define reg_iop_spu_r_trace___en___lsb 1 -#define reg_iop_spu_r_trace___en___width 1 -#define reg_iop_spu_r_trace___en___bit 1 -#define reg_iop_spu_r_trace___c_flag___lsb 2 -#define reg_iop_spu_r_trace___c_flag___width 1 -#define reg_iop_spu_r_trace___c_flag___bit 2 -#define reg_iop_spu_r_trace___v_flag___lsb 3 -#define reg_iop_spu_r_trace___v_flag___width 1 -#define reg_iop_spu_r_trace___v_flag___bit 3 -#define reg_iop_spu_r_trace___z_flag___lsb 4 -#define reg_iop_spu_r_trace___z_flag___width 1 -#define reg_iop_spu_r_trace___z_flag___bit 4 -#define reg_iop_spu_r_trace___n_flag___lsb 5 -#define reg_iop_spu_r_trace___n_flag___width 1 -#define reg_iop_spu_r_trace___n_flag___bit 5 -#define reg_iop_spu_r_trace___seq_addr___lsb 6 -#define reg_iop_spu_r_trace___seq_addr___width 12 -#define reg_iop_spu_r_trace___fsm_addr___lsb 20 -#define reg_iop_spu_r_trace___fsm_addr___width 12 -#define reg_iop_spu_r_trace_offset 196 - -/* Register r_fsm_trace, scope iop_spu, type r */ -#define reg_iop_spu_r_fsm_trace___fsm___lsb 0 -#define reg_iop_spu_r_fsm_trace___fsm___width 1 -#define reg_iop_spu_r_fsm_trace___fsm___bit 0 -#define reg_iop_spu_r_fsm_trace___en___lsb 1 -#define reg_iop_spu_r_fsm_trace___en___width 1 -#define reg_iop_spu_r_fsm_trace___en___bit 1 -#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2 -#define reg_iop_spu_r_fsm_trace___tmr_done___width 1 -#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2 -#define reg_iop_spu_r_fsm_trace___inp0___lsb 3 -#define reg_iop_spu_r_fsm_trace___inp0___width 1 -#define reg_iop_spu_r_fsm_trace___inp0___bit 3 -#define reg_iop_spu_r_fsm_trace___inp1___lsb 4 -#define reg_iop_spu_r_fsm_trace___inp1___width 1 -#define reg_iop_spu_r_fsm_trace___inp1___bit 4 -#define reg_iop_spu_r_fsm_trace___inp2___lsb 5 -#define reg_iop_spu_r_fsm_trace___inp2___width 1 -#define reg_iop_spu_r_fsm_trace___inp2___bit 5 -#define reg_iop_spu_r_fsm_trace___inp3___lsb 6 -#define reg_iop_spu_r_fsm_trace___inp3___width 1 -#define reg_iop_spu_r_fsm_trace___inp3___bit 6 -#define reg_iop_spu_r_fsm_trace___event0___lsb 7 -#define reg_iop_spu_r_fsm_trace___event0___width 1 -#define reg_iop_spu_r_fsm_trace___event0___bit 7 -#define reg_iop_spu_r_fsm_trace___event1___lsb 8 -#define reg_iop_spu_r_fsm_trace___event1___width 1 -#define reg_iop_spu_r_fsm_trace___event1___bit 8 -#define reg_iop_spu_r_fsm_trace___event2___lsb 9 -#define reg_iop_spu_r_fsm_trace___event2___width 1 -#define reg_iop_spu_r_fsm_trace___event2___bit 9 -#define reg_iop_spu_r_fsm_trace___event3___lsb 10 -#define reg_iop_spu_r_fsm_trace___event3___width 1 -#define reg_iop_spu_r_fsm_trace___event3___bit 10 -#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11 -#define reg_iop_spu_r_fsm_trace___gio_out___width 8 -#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20 -#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12 -#define reg_iop_spu_r_fsm_trace_offset 200 - -#define STRIDE_iop_spu_rw_brp 4 -/* Register rw_brp, scope iop_spu, type rw */ -#define reg_iop_spu_rw_brp___addr___lsb 0 -#define reg_iop_spu_rw_brp___addr___width 12 -#define reg_iop_spu_rw_brp___fsm___lsb 12 -#define reg_iop_spu_rw_brp___fsm___width 1 -#define reg_iop_spu_rw_brp___fsm___bit 12 -#define reg_iop_spu_rw_brp___en___lsb 13 -#define reg_iop_spu_rw_brp___en___width 1 -#define reg_iop_spu_rw_brp___en___bit 13 -#define reg_iop_spu_rw_brp_offset 204 - - -/* Constants */ -#define regk_iop_spu_attn_hi 0x00000005 -#define regk_iop_spu_attn_lo 0x00000005 -#define regk_iop_spu_attn_r0 0x00000000 -#define regk_iop_spu_attn_r1 0x00000001 -#define regk_iop_spu_attn_r10 0x00000002 -#define regk_iop_spu_attn_r11 0x00000003 -#define regk_iop_spu_attn_r12 0x00000004 -#define regk_iop_spu_attn_r13 0x00000005 -#define regk_iop_spu_attn_r14 0x00000006 -#define regk_iop_spu_attn_r15 0x00000007 -#define regk_iop_spu_attn_r2 0x00000002 -#define regk_iop_spu_attn_r3 0x00000003 -#define regk_iop_spu_attn_r4 0x00000004 -#define regk_iop_spu_attn_r5 0x00000005 -#define regk_iop_spu_attn_r6 0x00000006 -#define regk_iop_spu_attn_r7 0x00000007 -#define regk_iop_spu_attn_r8 0x00000000 -#define regk_iop_spu_attn_r9 0x00000001 -#define regk_iop_spu_c 0x00000000 -#define regk_iop_spu_flag 0x00000002 -#define regk_iop_spu_gio_in 0x00000000 -#define regk_iop_spu_gio_out 0x00000005 -#define regk_iop_spu_gio_out0 0x00000008 -#define regk_iop_spu_gio_out1 0x00000009 -#define regk_iop_spu_gio_out2 0x0000000a -#define regk_iop_spu_gio_out3 0x0000000b -#define regk_iop_spu_gio_out4 0x0000000c -#define regk_iop_spu_gio_out5 0x0000000d -#define regk_iop_spu_gio_out6 0x0000000e -#define regk_iop_spu_gio_out7 0x0000000f -#define regk_iop_spu_n 0x00000003 -#define regk_iop_spu_no 0x00000000 -#define regk_iop_spu_r0 0x00000008 -#define regk_iop_spu_r1 0x00000009 -#define regk_iop_spu_r10 0x0000000a -#define regk_iop_spu_r11 0x0000000b -#define regk_iop_spu_r12 0x0000000c -#define regk_iop_spu_r13 0x0000000d -#define regk_iop_spu_r14 0x0000000e -#define regk_iop_spu_r15 0x0000000f -#define regk_iop_spu_r2 0x0000000a -#define regk_iop_spu_r3 0x0000000b -#define regk_iop_spu_r4 0x0000000c -#define regk_iop_spu_r5 0x0000000d -#define regk_iop_spu_r6 0x0000000e -#define regk_iop_spu_r7 0x0000000f -#define regk_iop_spu_r8 0x00000008 -#define regk_iop_spu_r9 0x00000009 -#define regk_iop_spu_reg_hi 0x00000002 -#define regk_iop_spu_reg_lo 0x00000002 -#define regk_iop_spu_rw_brp_default 0x00000000 -#define regk_iop_spu_rw_brp_size 0x00000004 -#define regk_iop_spu_rw_ctrl_default 0x00000000 -#define regk_iop_spu_rw_event_cfg_size 0x00000004 -#define regk_iop_spu_rw_event_mask_size 0x00000004 -#define regk_iop_spu_rw_event_val_size 0x00000004 -#define regk_iop_spu_rw_gio_out_default 0x00000000 -#define regk_iop_spu_rw_r_size 0x00000010 -#define regk_iop_spu_rw_reg_access_default 0x00000000 -#define regk_iop_spu_stat_in 0x00000002 -#define regk_iop_spu_statin_hi 0x00000004 -#define regk_iop_spu_statin_lo 0x00000004 -#define regk_iop_spu_trig 0x00000003 -#define regk_iop_spu_trigger 0x00000006 -#define regk_iop_spu_v 0x00000001 -#define regk_iop_spu_wsts_gioout_spec 0x00000001 -#define regk_iop_spu_xor 0x00000003 -#define regk_iop_spu_xor_bus0_r2_0 0x00000000 -#define regk_iop_spu_xor_bus0m_r2_0 0x00000002 -#define regk_iop_spu_xor_bus1_r3_0 0x00000001 -#define regk_iop_spu_xor_bus1m_r3_0 0x00000003 -#define regk_iop_spu_yes 0x00000001 -#define regk_iop_spu_z 0x00000002 -#endif /* __iop_spu_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index 3be60f9b024c..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null @@ -1,1052 +0,0 @@ -#ifndef __iop_sw_cfg_defs_asm_h -#define __iop_sw_cfg_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0 - -/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4 - -/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8 - -/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12 - -/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16 - -/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20 - -/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24 - -/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28 - -/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32 - -/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36 - -/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40 - -/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44 - -/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48 - -/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60 - -/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64 - -/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68 - -/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72 - -/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76 - -/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_spu0_owner_offset 80 - -/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_spu1_owner_offset 84 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92 - -/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96 - -/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132 - -/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask_offset 136 - -/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140 - -/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask_offset 144 - -/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_mask_offset 152 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 -#define reg_iop_sw_cfg_rw_pinmapping_offset 160 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196 - -/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2 -#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200 - -/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2 -#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212 - -/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216 - -/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224 - -/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0 -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18 -#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228 - -/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0 -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18 -#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236 - - -/* Constants */ -#define regk_iop_sw_cfg_a 0x00000001 -#define regk_iop_sw_cfg_b 0x00000002 -#define regk_iop_sw_cfg_bus0 0x00000000 -#define regk_iop_sw_cfg_bus0_rot16 0x00000004 -#define regk_iop_sw_cfg_bus0_rot24 0x00000006 -#define regk_iop_sw_cfg_bus0_rot8 0x00000002 -#define regk_iop_sw_cfg_bus1 0x00000001 -#define regk_iop_sw_cfg_bus1_rot16 0x00000005 -#define regk_iop_sw_cfg_bus1_rot24 0x00000007 -#define regk_iop_sw_cfg_bus1_rot8 0x00000003 -#define regk_iop_sw_cfg_clk12 0x00000000 -#define regk_iop_sw_cfg_cpu 0x00000000 -#define regk_iop_sw_cfg_dmc0 0x00000000 -#define regk_iop_sw_cfg_dmc1 0x00000001 -#define regk_iop_sw_cfg_gated_clk0 0x00000010 -#define regk_iop_sw_cfg_gated_clk1 0x00000011 -#define regk_iop_sw_cfg_gated_clk2 0x00000012 -#define regk_iop_sw_cfg_gated_clk3 0x00000013 -#define regk_iop_sw_cfg_gio0 0x00000004 -#define regk_iop_sw_cfg_gio1 0x00000001 -#define regk_iop_sw_cfg_gio2 0x00000005 -#define regk_iop_sw_cfg_gio3 0x00000002 -#define regk_iop_sw_cfg_gio4 0x00000006 -#define regk_iop_sw_cfg_gio5 0x00000003 -#define regk_iop_sw_cfg_gio6 0x00000007 -#define regk_iop_sw_cfg_gio7 0x00000004 -#define regk_iop_sw_cfg_gio_in0 0x00000000 -#define regk_iop_sw_cfg_gio_in1 0x00000001 -#define regk_iop_sw_cfg_gio_in10 0x00000002 -#define regk_iop_sw_cfg_gio_in11 0x00000003 -#define regk_iop_sw_cfg_gio_in14 0x00000004 -#define regk_iop_sw_cfg_gio_in15 0x00000005 -#define regk_iop_sw_cfg_gio_in18 0x00000002 -#define regk_iop_sw_cfg_gio_in19 0x00000003 -#define regk_iop_sw_cfg_gio_in20 0x00000004 -#define regk_iop_sw_cfg_gio_in21 0x00000005 -#define regk_iop_sw_cfg_gio_in26 0x00000006 -#define regk_iop_sw_cfg_gio_in27 0x00000007 -#define regk_iop_sw_cfg_gio_in28 0x00000006 -#define regk_iop_sw_cfg_gio_in29 0x00000007 -#define regk_iop_sw_cfg_gio_in4 0x00000000 -#define regk_iop_sw_cfg_gio_in5 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003 -#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003 -#define regk_iop_sw_cfg_mpu 0x00000001 -#define regk_iop_sw_cfg_none 0x00000000 -#define regk_iop_sw_cfg_par0 0x00000000 -#define regk_iop_sw_cfg_par1 0x00000001 -#define regk_iop_sw_cfg_pdp_out0 0x00000002 -#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001 -#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005 -#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000 -#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004 -#define regk_iop_sw_cfg_pdp_out1 0x00000003 -#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003 -#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005 -#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002 -#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004 -#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555 -#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 -#define regk_iop_sw_cfg_sdp_out0 0x00000008 -#define regk_iop_sw_cfg_sdp_out1 0x00000009 -#define regk_iop_sw_cfg_size16 0x00000002 -#define regk_iop_sw_cfg_size24 0x00000003 -#define regk_iop_sw_cfg_size32 0x00000004 -#define regk_iop_sw_cfg_size8 0x00000001 -#define regk_iop_sw_cfg_spu0 0x00000002 -#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006 -#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006 -#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007 -#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007 -#define regk_iop_sw_cfg_spu0_g0 0x0000000e -#define regk_iop_sw_cfg_spu0_g1 0x0000000e -#define regk_iop_sw_cfg_spu0_g2 0x0000000e -#define regk_iop_sw_cfg_spu0_g3 0x0000000e -#define regk_iop_sw_cfg_spu0_g4 0x0000000e -#define regk_iop_sw_cfg_spu0_g5 0x0000000e -#define regk_iop_sw_cfg_spu0_g6 0x0000000e -#define regk_iop_sw_cfg_spu0_g7 0x0000000e -#define regk_iop_sw_cfg_spu0_gio0 0x00000000 -#define regk_iop_sw_cfg_spu0_gio1 0x00000001 -#define regk_iop_sw_cfg_spu0_gio2 0x00000000 -#define regk_iop_sw_cfg_spu0_gio5 0x00000005 -#define regk_iop_sw_cfg_spu0_gio6 0x00000006 -#define regk_iop_sw_cfg_spu0_gio7 0x00000007 -#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu0_gioout0 0x00000000 -#define regk_iop_sw_cfg_spu0_gioout1 0x00000000 -#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout2 0x00000002 -#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout3 0x00000002 -#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout4 0x00000004 -#define regk_iop_sw_cfg_spu0_gioout5 0x00000004 -#define regk_iop_sw_cfg_spu0_gioout6 0x00000006 -#define regk_iop_sw_cfg_spu0_gioout7 0x00000006 -#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e -#define regk_iop_sw_cfg_spu1 0x00000003 -#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006 -#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006 -#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007 -#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007 -#define regk_iop_sw_cfg_spu1_g0 0x0000000f -#define regk_iop_sw_cfg_spu1_g1 0x0000000f -#define regk_iop_sw_cfg_spu1_g2 0x0000000f -#define regk_iop_sw_cfg_spu1_g3 0x0000000f -#define regk_iop_sw_cfg_spu1_g4 0x0000000f -#define regk_iop_sw_cfg_spu1_g5 0x0000000f -#define regk_iop_sw_cfg_spu1_g6 0x0000000f -#define regk_iop_sw_cfg_spu1_g7 0x0000000f -#define regk_iop_sw_cfg_spu1_gio0 0x00000002 -#define regk_iop_sw_cfg_spu1_gio1 0x00000003 -#define regk_iop_sw_cfg_spu1_gio2 0x00000002 -#define regk_iop_sw_cfg_spu1_gio5 0x00000005 -#define regk_iop_sw_cfg_spu1_gio6 0x00000006 -#define regk_iop_sw_cfg_spu1_gio7 0x00000007 -#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout0 0x00000001 -#define regk_iop_sw_cfg_spu1_gioout1 0x00000001 -#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout2 0x00000003 -#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout3 0x00000003 -#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout4 0x00000005 -#define regk_iop_sw_cfg_spu1_gioout5 0x00000005 -#define regk_iop_sw_cfg_spu1_gioout6 0x00000007 -#define regk_iop_sw_cfg_spu1_gioout7 0x00000007 -#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f -#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002 -#define regk_iop_sw_cfg_timer_grp0 0x00000000 -#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004 -#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004 -#define regk_iop_sw_cfg_timer_grp1 0x00000000 -#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005 -#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005 -#define regk_iop_sw_cfg_timer_grp2 0x00000000 -#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006 -#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006 -#define regk_iop_sw_cfg_timer_grp3 0x00000000 -#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007 -#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007 -#define regk_iop_sw_cfg_trig0_0 0x00000000 -#define regk_iop_sw_cfg_trig0_1 0x00000000 -#define regk_iop_sw_cfg_trig0_2 0x00000000 -#define regk_iop_sw_cfg_trig0_3 0x00000000 -#define regk_iop_sw_cfg_trig1_0 0x00000000 -#define regk_iop_sw_cfg_trig1_1 0x00000000 -#define regk_iop_sw_cfg_trig1_2 0x00000000 -#define regk_iop_sw_cfg_trig1_3 0x00000000 -#define regk_iop_sw_cfg_trig2_0 0x00000000 -#define regk_iop_sw_cfg_trig2_1 0x00000000 -#define regk_iop_sw_cfg_trig2_2 0x00000000 -#define regk_iop_sw_cfg_trig2_3 0x00000000 -#define regk_iop_sw_cfg_trig3_0 0x00000000 -#define regk_iop_sw_cfg_trig3_1 0x00000000 -#define regk_iop_sw_cfg_trig3_2 0x00000000 -#define regk_iop_sw_cfg_trig3_3 0x00000000 -#define regk_iop_sw_cfg_trig4_0 0x00000001 -#define regk_iop_sw_cfg_trig4_1 0x00000001 -#define regk_iop_sw_cfg_trig4_2 0x00000001 -#define regk_iop_sw_cfg_trig4_3 0x00000001 -#define regk_iop_sw_cfg_trig5_0 0x00000001 -#define regk_iop_sw_cfg_trig5_1 0x00000001 -#define regk_iop_sw_cfg_trig5_2 0x00000001 -#define regk_iop_sw_cfg_trig5_3 0x00000001 -#define regk_iop_sw_cfg_trig6_0 0x00000001 -#define regk_iop_sw_cfg_trig6_1 0x00000001 -#define regk_iop_sw_cfg_trig6_2 0x00000001 -#define regk_iop_sw_cfg_trig6_3 0x00000001 -#define regk_iop_sw_cfg_trig7_0 0x00000001 -#define regk_iop_sw_cfg_trig7_1 0x00000001 -#define regk_iop_sw_cfg_trig7_2 0x00000001 -#define regk_iop_sw_cfg_trig7_3 0x00000001 -#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index db347bcba025..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null @@ -1,1758 +0,0 @@ -#ifndef __iop_sw_cpu_defs_asm_h -#define __iop_sw_cpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_cpu_rw_mc_data___val___width 32 -#define reg_iop_sw_cpu_rw_mc_data_offset 4 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_addr_offset 8 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -#define reg_iop_sw_cpu_rs_mc_data_offset 12 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_data_offset 16 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_cpu_r_mc_stat_offset 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24 - -/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36 - -/* Register r_bus0_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus0_in_offset 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44 - -/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56 - -/* Register r_bus1_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus1_in_offset 60 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_gio_in_offset 80 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31 -#define reg_iop_sw_cpu_rw_intr0_mask_offset 84 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr0_offset 88 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_r_intr0_offset 92 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_r_masked_intr0_offset 96 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31 -#define reg_iop_sw_cpu_rw_intr1_mask_offset 100 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr1_offset 104 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_r_intr1_offset 108 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_r_masked_intr1_offset 112 - -/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31 -#define reg_iop_sw_cpu_rw_intr2_mask_offset 116 - -/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr2_offset 120 - -/* Register r_intr2, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_intr2_offset 124 - -/* Register r_masked_intr2, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_masked_intr2_offset 128 - -/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31 -#define reg_iop_sw_cpu_rw_intr3_mask_offset 132 - -/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr3_offset 136 - -/* Register r_intr3, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31 -#define reg_iop_sw_cpu_r_intr3_offset 140 - -/* Register r_masked_intr3, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31 -#define reg_iop_sw_cpu_r_masked_intr3_offset 144 - - -/* Constants */ -#define regk_iop_sw_cpu_copy 0x00000000 -#define regk_iop_sw_cpu_no 0x00000000 -#define regk_iop_sw_cpu_rd 0x00000002 -#define regk_iop_sw_cpu_reg_copy 0x00000001 -#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000 -#define regk_iop_sw_cpu_wr 0x00000003 -#define regk_iop_sw_cpu_yes 0x00000001 -#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index ee7dc0435b59..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null @@ -1,1776 +0,0 @@ -#ifndef __iop_sw_mpu_defs_asm_h -#define __iop_sw_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 -#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_mpu_rw_mc_data___val___width 32 -#define reg_iop_sw_mpu_rw_mc_data_offset 8 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_addr_offset 12 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -#define reg_iop_sw_mpu_rs_mc_data_offset 16 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_data_offset 20 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_mpu_r_mc_stat_offset 24 - -/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28 - -/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40 - -/* Register r_bus0_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus0_in_offset 44 - -/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48 - -/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60 - -/* Register r_bus1_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus1_in_offset 64 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_gio_in_offset 84 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_rw_cpu_intr_offset 88 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_r_cpu_intr_offset 92 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp0_offset 104 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp1_offset 120 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp2_offset 136 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp3_offset 152 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156 - - -/* Constants */ -#define regk_iop_sw_mpu_copy 0x00000000 -#define regk_iop_sw_mpu_cpu 0x00000000 -#define regk_iop_sw_mpu_mpu 0x00000001 -#define regk_iop_sw_mpu_no 0x00000000 -#define regk_iop_sw_mpu_nop 0x00000000 -#define regk_iop_sw_mpu_rd 0x00000002 -#define regk_iop_sw_mpu_reg_copy 0x00000001 -#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 -#define regk_iop_sw_mpu_set 0x00000001 -#define regk_iop_sw_mpu_spu0 0x00000002 -#define regk_iop_sw_mpu_spu1 0x00000003 -#define regk_iop_sw_mpu_wr 0x00000003 -#define regk_iop_sw_mpu_yes 0x00000001 -#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 0929f144cfa1..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null @@ -1,691 +0,0 @@ -#ifndef __iop_sw_spu_defs_asm_h -#define __iop_sw_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_spu_rw_mc_ctrl_offset 0 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_spu_rw_mc_data___val___width 32 -#define reg_iop_sw_spu_rw_mc_data_offset 4 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_addr_offset 8 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -#define reg_iop_sw_spu_rs_mc_data_offset 12 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_data_offset 16 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_spu_r_mc_stat_offset 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24 - -/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36 - -/* Register r_bus0_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus0_in_offset 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44 - -/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56 - -/* Register r_bus1_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus1_in_offset 60 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_set_mask_offset 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_gio_in_offset 80 - -/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84 - -/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88 - -/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92 - -/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96 - -/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100 - -/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104 - -/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108 - -/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_cpu_intr_offset 148 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_cpu_intr_offset 152 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23 -#define reg_iop_sw_spu_r_hw_intr_offset 156 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_mpu_intr_offset 160 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31 -#define reg_iop_sw_spu_r_mpu_intr_offset 164 - - -/* Constants */ -#define regk_iop_sw_spu_copy 0x00000000 -#define regk_iop_sw_spu_no 0x00000000 -#define regk_iop_sw_spu_nop 0x00000000 -#define regk_iop_sw_spu_rd 0x00000002 -#define regk_iop_sw_spu_reg_copy 0x00000001 -#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_spu_set 0x00000001 -#define regk_iop_sw_spu_wr 0x00000003 -#define regk_iop_sw_spu_yes 0x00000001 -#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h deleted file mode 100644 index 7129a9a4bedc..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h +++ /dev/null @@ -1,237 +0,0 @@ -#ifndef __iop_timer_grp_defs_asm_h -#define __iop_timer_grp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_timer_grp.r - * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r - * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0 -#define reg_iop_timer_grp_rw_cfg___clk_src___width 1 -#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0 -#define reg_iop_timer_grp_rw_cfg___trig___lsb 1 -#define reg_iop_timer_grp_rw_cfg___trig___width 2 -#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3 -#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8 -#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11 -#define reg_iop_timer_grp_rw_cfg___clk_div___width 8 -#define reg_iop_timer_grp_rw_cfg_offset 0 - -/* Register rw_half_period, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0 -#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30 -#define reg_iop_timer_grp_rw_half_period_offset 4 - -/* Register rw_half_period_len, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_half_period_len_offset 8 - -#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 -/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0 -#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3 -#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3 -#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5 -#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7 -#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8 -#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10 -#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11 -#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17 -#define reg_iop_timer_grp_rw_tmr_cfg_offset 12 - -#define STRIDE_iop_timer_grp_rw_tmr_len 4 -/* Register rw_tmr_len, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0 -#define reg_iop_timer_grp_rw_tmr_len___val___width 16 -#define reg_iop_timer_grp_rw_tmr_len_offset 44 - -/* Register rw_cmd, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_cmd___rst___lsb 0 -#define reg_iop_timer_grp_rw_cmd___rst___width 4 -#define reg_iop_timer_grp_rw_cmd___en___lsb 4 -#define reg_iop_timer_grp_rw_cmd___en___width 4 -#define reg_iop_timer_grp_rw_cmd___dis___lsb 8 -#define reg_iop_timer_grp_rw_cmd___dis___width 4 -#define reg_iop_timer_grp_rw_cmd___strb___lsb 12 -#define reg_iop_timer_grp_rw_cmd___strb___width 4 -#define reg_iop_timer_grp_rw_cmd_offset 60 - -/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64 - -#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 -/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ -#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0 -#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16 -#define reg_iop_timer_grp_rs_tmr_cnt_offset 68 - -#define STRIDE_iop_timer_grp_r_tmr_cnt 8 -/* Register r_tmr_cnt, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0 -#define reg_iop_timer_grp_r_tmr_cnt___val___width 16 -#define reg_iop_timer_grp_r_tmr_cnt_offset 72 - -/* Register rw_intr_mask, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0 -#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3 -#define reg_iop_timer_grp_rw_intr_mask_offset 100 - -/* Register rw_ack_intr, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3 -#define reg_iop_timer_grp_rw_ack_intr_offset 104 - -/* Register r_intr, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_r_intr___tmr0___width 1 -#define reg_iop_timer_grp_r_intr___tmr0___bit 0 -#define reg_iop_timer_grp_r_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_r_intr___tmr1___width 1 -#define reg_iop_timer_grp_r_intr___tmr1___bit 1 -#define reg_iop_timer_grp_r_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_r_intr___tmr2___width 1 -#define reg_iop_timer_grp_r_intr___tmr2___bit 2 -#define reg_iop_timer_grp_r_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_r_intr___tmr3___width 1 -#define reg_iop_timer_grp_r_intr___tmr3___bit 3 -#define reg_iop_timer_grp_r_intr_offset 108 - -/* Register r_masked_intr, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0 -#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1 -#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2 -#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3 -#define reg_iop_timer_grp_r_masked_intr_offset 112 - - -/* Constants */ -#define regk_iop_timer_grp_clk200 0x00000000 -#define regk_iop_timer_grp_clk_gen 0x00000002 -#define regk_iop_timer_grp_complete 0x00000002 -#define regk_iop_timer_grp_div_clk200 0x00000001 -#define regk_iop_timer_grp_div_clk_gen 0x00000003 -#define regk_iop_timer_grp_ext 0x00000001 -#define regk_iop_timer_grp_hi 0x00000000 -#define regk_iop_timer_grp_long_period 0x00000001 -#define regk_iop_timer_grp_neg 0x00000002 -#define regk_iop_timer_grp_no 0x00000000 -#define regk_iop_timer_grp_once 0x00000003 -#define regk_iop_timer_grp_pause 0x00000001 -#define regk_iop_timer_grp_pos 0x00000001 -#define regk_iop_timer_grp_pos_neg 0x00000003 -#define regk_iop_timer_grp_pulse 0x00000000 -#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004 -#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004 -#define regk_iop_timer_grp_rw_cfg_default 0x00000002 -#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000 -#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000 -#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900 -#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200 -#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00 -#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004 -#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000 -#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004 -#define regk_iop_timer_grp_short_period 0x00000000 -#define regk_iop_timer_grp_stop 0x00000000 -#define regk_iop_timer_grp_tmr 0x00000004 -#define regk_iop_timer_grp_toggle 0x00000001 -#define regk_iop_timer_grp_yes 0x00000001 -#endif /* __iop_timer_grp_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h deleted file mode 100644 index 1005d9db80dc..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h +++ /dev/null @@ -1,157 +0,0 @@ -#ifndef __iop_trigger_grp_defs_asm_h -#define __iop_trigger_grp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_trigger_grp_rw_cfg 4 -/* Register rw_cfg, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_cfg___action___lsb 0 -#define reg_iop_trigger_grp_rw_cfg___action___width 2 -#define reg_iop_trigger_grp_rw_cfg___once___lsb 2 -#define reg_iop_trigger_grp_rw_cfg___once___width 1 -#define reg_iop_trigger_grp_rw_cfg___once___bit 2 -#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3 -#define reg_iop_trigger_grp_rw_cfg___trig___width 3 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7 -#define reg_iop_trigger_grp_rw_cfg_offset 0 - -/* Register rw_cmd, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0 -#define reg_iop_trigger_grp_rw_cmd___dis___width 4 -#define reg_iop_trigger_grp_rw_cmd___en___lsb 4 -#define reg_iop_trigger_grp_rw_cmd___en___width 4 -#define reg_iop_trigger_grp_rw_cmd_offset 16 - -/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0 -#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3 -#define reg_iop_trigger_grp_rw_intr_mask_offset 20 - -/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3 -#define reg_iop_trigger_grp_rw_ack_intr_offset 24 - -/* Register r_intr, scope iop_trigger_grp, type r */ -#define reg_iop_trigger_grp_r_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_r_intr___trig0___width 1 -#define reg_iop_trigger_grp_r_intr___trig0___bit 0 -#define reg_iop_trigger_grp_r_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_r_intr___trig1___width 1 -#define reg_iop_trigger_grp_r_intr___trig1___bit 1 -#define reg_iop_trigger_grp_r_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_r_intr___trig2___width 1 -#define reg_iop_trigger_grp_r_intr___trig2___bit 2 -#define reg_iop_trigger_grp_r_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_r_intr___trig3___width 1 -#define reg_iop_trigger_grp_r_intr___trig3___bit 3 -#define reg_iop_trigger_grp_r_intr_offset 28 - -/* Register r_masked_intr, scope iop_trigger_grp, type r */ -#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0 -#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1 -#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2 -#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3 -#define reg_iop_trigger_grp_r_masked_intr_offset 32 - - -/* Constants */ -#define regk_iop_trigger_grp_fall 0x00000002 -#define regk_iop_trigger_grp_fall_lo 0x00000006 -#define regk_iop_trigger_grp_no 0x00000000 -#define regk_iop_trigger_grp_off 0x00000000 -#define regk_iop_trigger_grp_pulse 0x00000000 -#define regk_iop_trigger_grp_rise 0x00000001 -#define regk_iop_trigger_grp_rise_fall 0x00000003 -#define regk_iop_trigger_grp_rise_fall_hi 0x00000007 -#define regk_iop_trigger_grp_rise_fall_lo 0x00000004 -#define regk_iop_trigger_grp_rise_hi 0x00000005 -#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0 -#define regk_iop_trigger_grp_rw_cfg_size 0x00000004 -#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000 -#define regk_iop_trigger_grp_toggle 0x00000003 -#define regk_iop_trigger_grp_yes 0x00000001 -#endif /* __iop_trigger_grp_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index e13feb20a7e3..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __iop_version_defs_asm_h -#define __iop_version_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_version.r - * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp - * last modfied: Mon Apr 11 16:08:44 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r - * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_version, scope iop_version, type r */ -#define reg_iop_version_r_version___nr___lsb 0 -#define reg_iop_version_r_version___nr___width 8 -#define reg_iop_version_r_version_offset 0 - - -/* Constants */ -#define regk_iop_version_v1_0 0x00000001 -#endif /* __iop_version_defs_asm_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h deleted file mode 100644 index 90e4785b6474..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h +++ /dev/null @@ -1,232 +0,0 @@ -#ifndef __iop_crc_par_defs_h -#define __iop_crc_par_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_crc_par.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r - * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_crc_par */ - -/* Register rw_cfg, scope iop_crc_par, type rw */ -typedef struct { - unsigned int mode : 1; - unsigned int crc_out : 1; - unsigned int rev_out : 1; - unsigned int inv_out : 1; - unsigned int trig : 2; - unsigned int poly : 3; - unsigned int dummy1 : 23; -} reg_iop_crc_par_rw_cfg; -#define REG_RD_ADDR_iop_crc_par_rw_cfg 0 -#define REG_WR_ADDR_iop_crc_par_rw_cfg 0 - -/* Register rw_init_crc, scope iop_crc_par, type rw */ -typedef unsigned int reg_iop_crc_par_rw_init_crc; -#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4 -#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4 - -/* Register rw_correct_crc, scope iop_crc_par, type rw */ -typedef unsigned int reg_iop_crc_par_rw_correct_crc; -#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8 -#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8 - -/* Register rw_ctrl, scope iop_crc_par, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_iop_crc_par_rw_ctrl; -#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12 -#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12 - -/* Register rw_set_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int tr_dif : 1; - unsigned int dummy1 : 31; -} reg_iop_crc_par_rw_set_last; -#define REG_RD_ADDR_iop_crc_par_rw_set_last 16 -#define REG_WR_ADDR_iop_crc_par_rw_set_last 16 - -/* Register rw_wr1byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_crc_par_rw_wr1byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20 -#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20 - -/* Register rw_wr2byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_crc_par_rw_wr2byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24 -#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24 - -/* Register rw_wr3byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_crc_par_rw_wr3byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28 -#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28 - -/* Register rw_wr4byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_crc_par_rw_wr4byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32 -#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32 - -/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_crc_par_rw_wr1byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36 -#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36 - -/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_crc_par_rw_wr2byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40 -#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40 - -/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_crc_par_rw_wr3byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44 -#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44 - -/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_crc_par_rw_wr4byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48 -#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48 - -/* Register r_stat, scope iop_crc_par, type r */ -typedef struct { - unsigned int err : 1; - unsigned int busy : 1; - unsigned int dummy1 : 30; -} reg_iop_crc_par_r_stat; -#define REG_RD_ADDR_iop_crc_par_r_stat 52 - -/* Register r_sh_reg, scope iop_crc_par, type r */ -typedef unsigned int reg_iop_crc_par_r_sh_reg; -#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56 - -/* Register r_crc, scope iop_crc_par, type r */ -typedef unsigned int reg_iop_crc_par_r_crc; -#define REG_RD_ADDR_iop_crc_par_r_crc 60 - -/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_crc_par_rw_strb_rec_dif_in; -#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 -#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 - - -/* Constants */ -enum { - regk_iop_crc_par_calc = 0x00000001, - regk_iop_crc_par_ccitt = 0x00000002, - regk_iop_crc_par_check = 0x00000000, - regk_iop_crc_par_crc16 = 0x00000001, - regk_iop_crc_par_crc32 = 0x00000000, - regk_iop_crc_par_crc5 = 0x00000003, - regk_iop_crc_par_crc5_11 = 0x00000004, - regk_iop_crc_par_dif_in = 0x00000002, - regk_iop_crc_par_hi = 0x00000000, - regk_iop_crc_par_neg = 0x00000002, - regk_iop_crc_par_no = 0x00000000, - regk_iop_crc_par_pos = 0x00000001, - regk_iop_crc_par_pos_neg = 0x00000003, - regk_iop_crc_par_rw_cfg_default = 0x00000000, - regk_iop_crc_par_rw_ctrl_default = 0x00000000, - regk_iop_crc_par_yes = 0x00000001 -}; -#endif /* __iop_crc_par_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h deleted file mode 100644 index 76aec6e37f3e..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h +++ /dev/null @@ -1,325 +0,0 @@ -#ifndef __iop_dmc_in_defs_h -#define __iop_dmc_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_in.r - * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r - * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_dmc_in */ - -/* Register rw_cfg, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int sth_intr : 3; - unsigned int last_dis_dif : 1; - unsigned int dummy1 : 28; -} reg_iop_dmc_in_rw_cfg; -#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0 -#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dif_dis : 1; - unsigned int stream_clr : 1; - unsigned int dummy1 : 29; -} reg_iop_dmc_in_rw_ctrl; -#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4 - -/* Register r_stat, scope iop_dmc_in, type r */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dummy1 : 31; -} reg_iop_dmc_in_r_stat; -#define REG_RD_ADDR_iop_dmc_in_r_stat 8 - -/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 8; -} reg_iop_dmc_in_rw_stream_cmd; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12 - -/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16 - -/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 - -/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int eop : 1; - unsigned int wait : 1; - unsigned int keep_md : 1; - unsigned int size : 3; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_stream_ctrl; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24 - -/* Register r_stream_stat, scope iop_dmc_in, type r */ -typedef struct { - unsigned int sth : 7; - unsigned int dummy1 : 9; - unsigned int full : 1; - unsigned int last_pkt : 1; - unsigned int data_md_valid : 1; - unsigned int ctxt_md_valid : 1; - unsigned int group_md_valid : 1; - unsigned int stream_busy : 1; - unsigned int cmd_rdy : 1; - unsigned int dummy2 : 9; -} reg_iop_dmc_in_r_stream_stat; -#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28 - -/* Register r_data_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_in_r_data_descr; -#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32 - -/* Register r_ctxt_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md0 : 16; -} reg_iop_dmc_in_r_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36 - -/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ -typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40 - -/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ -typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44 - -/* Register r_group_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_in_r_group_descr; -#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56 - -/* Register rw_data_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_in_rw_data_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60 -#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60 - -/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md0 : 16; -} reg_iop_dmc_in_rw_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 - -/* Register rw_group_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_in_rw_group_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84 -#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84 - -/* Register rw_intr_mask, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_intr_mask; -#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88 -#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88 - -/* Register rw_ack_intr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_ack_intr; -#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92 -#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92 - -/* Register r_intr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_r_intr; -#define REG_RD_ADDR_iop_dmc_in_r_intr 96 - -/* Register r_masked_intr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_r_masked_intr; -#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100 - - -/* Constants */ -enum { - regk_iop_dmc_in_ack_pkt = 0x00000100, - regk_iop_dmc_in_array = 0x00000008, - regk_iop_dmc_in_burst = 0x00000020, - regk_iop_dmc_in_copy_next = 0x00000010, - regk_iop_dmc_in_copy_up = 0x00000020, - regk_iop_dmc_in_dis_c = 0x00000010, - regk_iop_dmc_in_dis_g = 0x00000020, - regk_iop_dmc_in_lim1 = 0x00000000, - regk_iop_dmc_in_lim16 = 0x00000004, - regk_iop_dmc_in_lim2 = 0x00000001, - regk_iop_dmc_in_lim32 = 0x00000005, - regk_iop_dmc_in_lim4 = 0x00000002, - regk_iop_dmc_in_lim64 = 0x00000006, - regk_iop_dmc_in_lim8 = 0x00000003, - regk_iop_dmc_in_load_c = 0x00000200, - regk_iop_dmc_in_load_c_n = 0x00000280, - regk_iop_dmc_in_load_c_next = 0x00000240, - regk_iop_dmc_in_load_d = 0x00000140, - regk_iop_dmc_in_load_g = 0x00000300, - regk_iop_dmc_in_load_g_down = 0x000003c0, - regk_iop_dmc_in_load_g_next = 0x00000340, - regk_iop_dmc_in_load_g_up = 0x00000380, - regk_iop_dmc_in_next_en = 0x00000010, - regk_iop_dmc_in_next_pkt = 0x00000010, - regk_iop_dmc_in_no = 0x00000000, - regk_iop_dmc_in_restore = 0x00000020, - regk_iop_dmc_in_rw_cfg_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000, - regk_iop_dmc_in_rw_data_descr_default = 0x00000000, - regk_iop_dmc_in_rw_group_descr_default = 0x00000000, - regk_iop_dmc_in_rw_intr_mask_default = 0x00000000, - regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000, - regk_iop_dmc_in_save_down = 0x00000020, - regk_iop_dmc_in_save_up = 0x00000020, - regk_iop_dmc_in_set_reg = 0x00000050, - regk_iop_dmc_in_set_w_size1 = 0x00000190, - regk_iop_dmc_in_set_w_size2 = 0x000001a0, - regk_iop_dmc_in_set_w_size4 = 0x000001c0, - regk_iop_dmc_in_store_c = 0x00000002, - regk_iop_dmc_in_store_descr = 0x00000000, - regk_iop_dmc_in_store_g = 0x00000004, - regk_iop_dmc_in_store_md = 0x00000001, - regk_iop_dmc_in_update_down = 0x00000020, - regk_iop_dmc_in_yes = 0x00000001 -}; -#endif /* __iop_dmc_in_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h deleted file mode 100644 index 938a0d4c4604..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h +++ /dev/null @@ -1,326 +0,0 @@ -#ifndef __iop_dmc_out_defs_h -#define __iop_dmc_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_out.r - * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r - * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_dmc_out */ - -/* Register rw_cfg, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int trf_lim : 16; - unsigned int last_at_trf_lim : 1; - unsigned int dth_intr : 3; - unsigned int dummy1 : 12; -} reg_iop_dmc_out_rw_cfg; -#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0 -#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dif_dis : 1; - unsigned int dummy1 : 30; -} reg_iop_dmc_out_rw_ctrl; -#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4 - -/* Register r_stat, scope iop_dmc_out, type r */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dummy1 : 31; -} reg_iop_dmc_out_r_stat; -#define REG_RD_ADDR_iop_dmc_out_r_stat 8 - -/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 8; -} reg_iop_dmc_out_rw_stream_cmd; -#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12 -#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12 - -/* Register rs_stream_data, scope iop_dmc_out, type rs */ -typedef unsigned int reg_iop_dmc_out_rs_stream_data; -#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16 - -/* Register r_stream_data, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_stream_data; -#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20 - -/* Register r_stream_stat, scope iop_dmc_out, type r */ -typedef struct { - unsigned int dth : 7; - unsigned int dummy1 : 9; - unsigned int dv : 1; - unsigned int all_avail : 1; - unsigned int last : 1; - unsigned int size : 3; - unsigned int data_md_valid : 1; - unsigned int ctxt_md_valid : 1; - unsigned int group_md_valid : 1; - unsigned int stream_busy : 1; - unsigned int cmd_rdy : 1; - unsigned int cmd_rq : 1; - unsigned int dummy2 : 4; -} reg_iop_dmc_out_r_stream_stat; -#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24 - -/* Register r_data_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_out_r_data_descr; -#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28 - -/* Register r_ctxt_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md0 : 16; -} reg_iop_dmc_out_r_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32 - -/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36 - -/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40 - -/* Register r_group_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_out_r_group_descr; -#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52 - -/* Register rw_data_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_out_rw_data_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56 -#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56 - -/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md0 : 16; -} reg_iop_dmc_out_rw_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ -typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ -typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 - -/* Register rw_group_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_out_rw_group_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80 -#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80 - -/* Register rw_intr_mask, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_rw_intr_mask; -#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84 -#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84 - -/* Register rw_ack_intr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_rw_ack_intr; -#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88 -#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88 - -/* Register r_intr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_r_intr; -#define REG_RD_ADDR_iop_dmc_out_r_intr 92 - -/* Register r_masked_intr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_r_masked_intr; -#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96 - - -/* Constants */ -enum { - regk_iop_dmc_out_ack_pkt = 0x00000100, - regk_iop_dmc_out_array = 0x00000008, - regk_iop_dmc_out_burst = 0x00000020, - regk_iop_dmc_out_copy_next = 0x00000010, - regk_iop_dmc_out_copy_up = 0x00000020, - regk_iop_dmc_out_dis_c = 0x00000010, - regk_iop_dmc_out_dis_g = 0x00000020, - regk_iop_dmc_out_lim1 = 0x00000000, - regk_iop_dmc_out_lim16 = 0x00000004, - regk_iop_dmc_out_lim2 = 0x00000001, - regk_iop_dmc_out_lim32 = 0x00000005, - regk_iop_dmc_out_lim4 = 0x00000002, - regk_iop_dmc_out_lim64 = 0x00000006, - regk_iop_dmc_out_lim8 = 0x00000003, - regk_iop_dmc_out_load_c = 0x00000200, - regk_iop_dmc_out_load_c_n = 0x00000280, - regk_iop_dmc_out_load_c_next = 0x00000240, - regk_iop_dmc_out_load_d = 0x00000140, - regk_iop_dmc_out_load_g = 0x00000300, - regk_iop_dmc_out_load_g_down = 0x000003c0, - regk_iop_dmc_out_load_g_next = 0x00000340, - regk_iop_dmc_out_load_g_up = 0x00000380, - regk_iop_dmc_out_next_en = 0x00000010, - regk_iop_dmc_out_next_pkt = 0x00000010, - regk_iop_dmc_out_no = 0x00000000, - regk_iop_dmc_out_restore = 0x00000020, - regk_iop_dmc_out_rw_cfg_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000, - regk_iop_dmc_out_rw_data_descr_default = 0x00000000, - regk_iop_dmc_out_rw_group_descr_default = 0x00000000, - regk_iop_dmc_out_rw_intr_mask_default = 0x00000000, - regk_iop_dmc_out_save_down = 0x00000020, - regk_iop_dmc_out_save_up = 0x00000020, - regk_iop_dmc_out_set_reg = 0x00000050, - regk_iop_dmc_out_set_w_size1 = 0x00000190, - regk_iop_dmc_out_set_w_size2 = 0x000001a0, - regk_iop_dmc_out_set_w_size4 = 0x000001c0, - regk_iop_dmc_out_store_c = 0x00000002, - regk_iop_dmc_out_store_descr = 0x00000000, - regk_iop_dmc_out_store_g = 0x00000004, - regk_iop_dmc_out_store_md = 0x00000001, - regk_iop_dmc_out_update_down = 0x00000020, - regk_iop_dmc_out_yes = 0x00000001 -}; -#endif /* __iop_dmc_out_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h deleted file mode 100644 index e0c982b263fa..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h +++ /dev/null @@ -1,255 +0,0 @@ -#ifndef __iop_fifo_in_defs_h -#define __iop_fifo_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in.r - * id: - * last modfied: Mon Apr 11 16:10:07 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r - * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_in */ - -/* Register rw_cfg, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int avail_lim : 3; - unsigned int byte_order : 2; - unsigned int trig : 2; - unsigned int last_dis_dif_in : 1; - unsigned int mode : 2; - unsigned int dummy1 : 22; -} reg_iop_fifo_in_rw_cfg; -#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0 -#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_rw_ctrl; -#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4 - -/* Register r_stat, scope iop_fifo_in, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 18; -} reg_iop_fifo_in_r_stat; -#define REG_RD_ADDR_iop_fifo_in_r_stat 8 - -/* Register rs_rd1byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_in_rs_rd1byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12 - -/* Register r_rd1byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_in_r_rd1byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16 - -/* Register rs_rd2byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_in_rs_rd2byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20 - -/* Register r_rd2byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_in_r_rd2byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24 - -/* Register rs_rd3byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_in_rs_rd3byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28 - -/* Register r_rd3byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_in_r_rd3byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32 - -/* Register rs_rd4byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_in_rs_rd4byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36 - -/* Register r_rd4byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_in_r_rd4byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40 - -/* Register rw_set_last, scope iop_fifo_in, type rw */ -typedef unsigned int reg_iop_fifo_in_rw_set_last; -#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44 -#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44 - -/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_rw_strb_dif_in; -#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48 -#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48 - -/* Register rw_intr_mask, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52 -#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52 - -/* Register rw_ack_intr, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56 -#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56 - -/* Register r_intr, scope iop_fifo_in, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_r_intr; -#define REG_RD_ADDR_iop_fifo_in_r_intr 60 - -/* Register r_masked_intr, scope iop_fifo_in, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64 - - -/* Constants */ -enum { - regk_iop_fifo_in_dif_in = 0x00000002, - regk_iop_fifo_in_hi = 0x00000000, - regk_iop_fifo_in_neg = 0x00000002, - regk_iop_fifo_in_no = 0x00000000, - regk_iop_fifo_in_order16 = 0x00000001, - regk_iop_fifo_in_order24 = 0x00000002, - regk_iop_fifo_in_order32 = 0x00000003, - regk_iop_fifo_in_order8 = 0x00000000, - regk_iop_fifo_in_pos = 0x00000001, - regk_iop_fifo_in_pos_neg = 0x00000003, - regk_iop_fifo_in_rw_cfg_default = 0x00000024, - regk_iop_fifo_in_rw_ctrl_default = 0x00000000, - regk_iop_fifo_in_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_in_rw_set_last_default = 0x00000000, - regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000, - regk_iop_fifo_in_size16 = 0x00000002, - regk_iop_fifo_in_size24 = 0x00000001, - regk_iop_fifo_in_size32 = 0x00000000, - regk_iop_fifo_in_size8 = 0x00000003, - regk_iop_fifo_in_yes = 0x00000001 -}; -#endif /* __iop_fifo_in_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h deleted file mode 100644 index 798ac95870e9..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef __iop_fifo_in_extra_defs_h -#define __iop_fifo_in_extra_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: - * last modfied: Mon Apr 11 16:10:08 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_in_extra */ - -/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ -typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0 - -/* Register r_stat, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 18; -} reg_iop_fifo_in_extra_r_stat; -#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4 - -/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_extra_rw_strb_dif_in; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 - -/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12 - -/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16 - -/* Register r_intr, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_r_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20 - -/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24 - - -/* Constants */ -enum { - regk_iop_fifo_in_extra_fifo_in = 0x00000002, - regk_iop_fifo_in_extra_no = 0x00000000, - regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_in_extra_yes = 0x00000001 -}; -#endif /* __iop_fifo_in_extra_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h deleted file mode 100644 index 833e10f02526..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h +++ /dev/null @@ -1,278 +0,0 @@ -#ifndef __iop_fifo_out_defs_h -#define __iop_fifo_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out.r - * id: - * last modfied: Mon Apr 11 16:10:09 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r - * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_out */ - -/* Register rw_cfg, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int free_lim : 3; - unsigned int byte_order : 2; - unsigned int trig : 2; - unsigned int last_dis_dif_in : 1; - unsigned int mode : 2; - unsigned int delay_out_last : 1; - unsigned int last_dis_dif_out : 1; - unsigned int dummy1 : 20; -} reg_iop_fifo_out_rw_cfg; -#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0 -#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 30; -} reg_iop_fifo_out_rw_ctrl; -#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4 - -/* Register r_stat, scope iop_fifo_out, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int zero_data_last : 1; - unsigned int dummy1 : 17; -} reg_iop_fifo_out_r_stat; -#define REG_RD_ADDR_iop_fifo_out_r_stat 8 - -/* Register rw_wr1byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_out_rw_wr1byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12 -#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12 - -/* Register rw_wr2byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_out_rw_wr2byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16 -#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16 - -/* Register rw_wr3byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_out_rw_wr3byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20 -#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20 - -/* Register rw_wr4byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_out_rw_wr4byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24 -#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24 - -/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_out_rw_wr1byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28 -#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28 - -/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_out_rw_wr2byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32 -#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32 - -/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_out_rw_wr3byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36 -#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36 - -/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_out_rw_wr4byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40 -#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40 - -/* Register rw_set_last, scope iop_fifo_out, type rw */ -typedef unsigned int reg_iop_fifo_out_rw_set_last; -#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44 -#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44 - -/* Register rs_rd_data, scope iop_fifo_out, type rs */ -typedef unsigned int reg_iop_fifo_out_rs_rd_data; -#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48 - -/* Register r_rd_data, scope iop_fifo_out, type r */ -typedef unsigned int reg_iop_fifo_out_r_rd_data; -#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52 - -/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ -typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out; -#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56 -#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56 - -/* Register rw_intr_mask, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60 -#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60 - -/* Register rw_ack_intr, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64 -#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64 - -/* Register r_intr, scope iop_fifo_out, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_r_intr; -#define REG_RD_ADDR_iop_fifo_out_r_intr 68 - -/* Register r_masked_intr, scope iop_fifo_out, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72 - - -/* Constants */ -enum { - regk_iop_fifo_out_hi = 0x00000000, - regk_iop_fifo_out_neg = 0x00000002, - regk_iop_fifo_out_no = 0x00000000, - regk_iop_fifo_out_order16 = 0x00000001, - regk_iop_fifo_out_order24 = 0x00000002, - regk_iop_fifo_out_order32 = 0x00000003, - regk_iop_fifo_out_order8 = 0x00000000, - regk_iop_fifo_out_pos = 0x00000001, - regk_iop_fifo_out_pos_neg = 0x00000003, - regk_iop_fifo_out_rw_cfg_default = 0x00000024, - regk_iop_fifo_out_rw_ctrl_default = 0x00000000, - regk_iop_fifo_out_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_out_rw_set_last_default = 0x00000000, - regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000, - regk_iop_fifo_out_rw_wr1byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr2byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr3byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr4byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000, - regk_iop_fifo_out_size16 = 0x00000002, - regk_iop_fifo_out_size24 = 0x00000001, - regk_iop_fifo_out_size32 = 0x00000000, - regk_iop_fifo_out_size8 = 0x00000003, - regk_iop_fifo_out_yes = 0x00000001 -}; -#endif /* __iop_fifo_out_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h deleted file mode 100644 index 4a840aae84ee..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef __iop_fifo_out_extra_defs_h -#define __iop_fifo_out_extra_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: - * last modfied: Mon Apr 11 16:10:10 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_out_extra */ - -/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ -typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data; -#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0 - -/* Register r_rd_data, scope iop_fifo_out_extra, type r */ -typedef unsigned int reg_iop_fifo_out_extra_r_rd_data; -#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4 - -/* Register r_stat, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int zero_data_last : 1; - unsigned int dummy1 : 17; -} reg_iop_fifo_out_extra_r_stat; -#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8 - -/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ -typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 - -/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16 - -/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20 - -/* Register r_intr, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_r_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24 - -/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28 - - -/* Constants */ -enum { - regk_iop_fifo_out_extra_no = 0x00000000, - regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_out_extra_yes = 0x00000001 -}; -#endif /* __iop_fifo_out_extra_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h deleted file mode 100644 index c2b0ba1be60f..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h +++ /dev/null @@ -1,190 +0,0 @@ -#ifndef __iop_mpu_defs_h -#define __iop_mpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_mpu.r - * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r - * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_mpu */ - -#define STRIDE_iop_mpu_rw_r 4 -/* Register rw_r, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_r; -#define REG_RD_ADDR_iop_mpu_rw_r 0 -#define REG_WR_ADDR_iop_mpu_rw_r 0 - -/* Register rw_ctrl, scope iop_mpu, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_iop_mpu_rw_ctrl; -#define REG_RD_ADDR_iop_mpu_rw_ctrl 128 -#define REG_WR_ADDR_iop_mpu_rw_ctrl 128 - -/* Register r_pc, scope iop_mpu, type r */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_r_pc; -#define REG_RD_ADDR_iop_mpu_r_pc 132 - -/* Register r_stat, scope iop_mpu, type r */ -typedef struct { - unsigned int instr_reg_busy : 1; - unsigned int intr_busy : 1; - unsigned int intr_vect : 16; - unsigned int dummy1 : 14; -} reg_iop_mpu_r_stat; -#define REG_RD_ADDR_iop_mpu_r_stat 136 - -/* Register rw_instr, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_instr; -#define REG_RD_ADDR_iop_mpu_rw_instr 140 -#define REG_WR_ADDR_iop_mpu_rw_instr 140 - -/* Register rw_immediate, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_immediate; -#define REG_RD_ADDR_iop_mpu_rw_immediate 144 -#define REG_WR_ADDR_iop_mpu_rw_immediate 144 - -/* Register r_trace, scope iop_mpu, type r */ -typedef struct { - unsigned int intr_vect : 16; - unsigned int pc : 12; - unsigned int en : 1; - unsigned int instr_reg_busy : 1; - unsigned int intr_busy : 1; - unsigned int dummy1 : 1; -} reg_iop_mpu_r_trace; -#define REG_RD_ADDR_iop_mpu_r_trace 148 - -/* Register r_wr_stat, scope iop_mpu, type r */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_mpu_r_wr_stat; -#define REG_RD_ADDR_iop_mpu_r_wr_stat 152 - -#define STRIDE_iop_mpu_rw_thread 4 -/* Register rw_thread, scope iop_mpu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_rw_thread; -#define REG_RD_ADDR_iop_mpu_rw_thread 156 -#define REG_WR_ADDR_iop_mpu_rw_thread 156 - -#define STRIDE_iop_mpu_rw_intr 4 -/* Register rw_intr, scope iop_mpu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_rw_intr; -#define REG_RD_ADDR_iop_mpu_rw_intr 196 -#define REG_WR_ADDR_iop_mpu_rw_intr 196 - - -/* Constants */ -enum { - regk_iop_mpu_no = 0x00000000, - regk_iop_mpu_r_pc_default = 0x00000000, - regk_iop_mpu_rw_ctrl_default = 0x00000000, - regk_iop_mpu_rw_intr_size = 0x00000010, - regk_iop_mpu_rw_r_size = 0x00000010, - regk_iop_mpu_rw_thread_default = 0x00000000, - regk_iop_mpu_rw_thread_size = 0x00000004, - regk_iop_mpu_yes = 0x00000001 -}; -#endif /* __iop_mpu_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h deleted file mode 100644 index 2ec897ced166..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h +++ /dev/null @@ -1,764 +0,0 @@ -/* ************************************************************************* */ -/* This file is autogenerated by IOPASM Version 1.2 */ -/* DO NOT EDIT THIS FILE - All changes will be lost! */ -/* ************************************************************************* */ - - - -#ifndef __IOP_MPU_MACROS_H__ -#define __IOP_MPU_MACROS_H__ - - -/* ************************************************************************* */ -/* REGISTER DEFINITIONS */ -/* ************************************************************************* */ -#define MPU_R0 (0x0) -#define MPU_R1 (0x1) -#define MPU_R2 (0x2) -#define MPU_R3 (0x3) -#define MPU_R4 (0x4) -#define MPU_R5 (0x5) -#define MPU_R6 (0x6) -#define MPU_R7 (0x7) -#define MPU_R8 (0x8) -#define MPU_R9 (0x9) -#define MPU_R10 (0xa) -#define MPU_R11 (0xb) -#define MPU_R12 (0xc) -#define MPU_R13 (0xd) -#define MPU_R14 (0xe) -#define MPU_R15 (0xf) -#define MPU_PC (0x2) -#define MPU_WSTS (0x3) -#define MPU_JADDR (0x4) -#define MPU_IRP (0x5) -#define MPU_SRP (0x6) -#define MPU_T0 (0x8) -#define MPU_T1 (0x9) -#define MPU_T2 (0xa) -#define MPU_T3 (0xb) -#define MPU_I0 (0x10) -#define MPU_I1 (0x11) -#define MPU_I2 (0x12) -#define MPU_I3 (0x13) -#define MPU_I4 (0x14) -#define MPU_I5 (0x15) -#define MPU_I6 (0x16) -#define MPU_I7 (0x17) -#define MPU_I8 (0x18) -#define MPU_I9 (0x19) -#define MPU_I10 (0x1a) -#define MPU_I11 (0x1b) -#define MPU_I12 (0x1c) -#define MPU_I13 (0x1d) -#define MPU_I14 (0x1e) -#define MPU_I15 (0x1f) -#define MPU_P2 (0x2) -#define MPU_P3 (0x3) -#define MPU_P5 (0x5) -#define MPU_P6 (0x6) -#define MPU_P8 (0x8) -#define MPU_P9 (0x9) -#define MPU_P10 (0xa) -#define MPU_P11 (0xb) -#define MPU_P16 (0x10) -#define MPU_P17 (0x12) -#define MPU_P18 (0x12) -#define MPU_P19 (0x13) -#define MPU_P20 (0x14) -#define MPU_P21 (0x15) -#define MPU_P22 (0x16) -#define MPU_P23 (0x17) -#define MPU_P24 (0x18) -#define MPU_P25 (0x19) -#define MPU_P26 (0x1a) -#define MPU_P27 (0x1b) -#define MPU_P28 (0x1c) -#define MPU_P29 (0x1d) -#define MPU_P30 (0x1e) -#define MPU_P31 (0x1f) -#define MPU_P1 (0x1) -#define MPU_REGA (0x1) - - - -/* ************************************************************************* */ -/* ADDRESS MACROS */ -/* ************************************************************************* */ -#define MK_DWORD_ADDR(ADDR) (ADDR >> 2) -#define MK_BYTE_ADDR(ADDR) (ADDR) - - - -/* ************************************************************************* */ -/* INSTRUCTION MACROS */ -/* ************************************************************************* */ -#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 21)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 21)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_DI() (0x40000001) - -#define MPU_EI() (0x40000003) - -#define MPU_HALT() (0x40000002) - -#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JNT() (0x61000000) - -#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_NOP() (0x40000000) - -#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_RET() (0x63003000) - -#define MPU_RETI() (0x63602800) - -#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\ - | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - - -#endif /* end of __IOP_MPU_MACROS_H__ */ -/* End of iop_mpu_macros.h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h deleted file mode 100644 index 756550f5d6cb..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg - */ -#define regi_iop_version (regi_iop + 0) -#define regi_iop_fifo_in0_extra (regi_iop + 64) -#define regi_iop_fifo_in1_extra (regi_iop + 128) -#define regi_iop_fifo_out0_extra (regi_iop + 192) -#define regi_iop_fifo_out1_extra (regi_iop + 256) -#define regi_iop_trigger_grp0 (regi_iop + 320) -#define regi_iop_trigger_grp1 (regi_iop + 384) -#define regi_iop_trigger_grp2 (regi_iop + 448) -#define regi_iop_trigger_grp3 (regi_iop + 512) -#define regi_iop_trigger_grp4 (regi_iop + 576) -#define regi_iop_trigger_grp5 (regi_iop + 640) -#define regi_iop_trigger_grp6 (regi_iop + 704) -#define regi_iop_trigger_grp7 (regi_iop + 768) -#define regi_iop_crc_par0 (regi_iop + 896) -#define regi_iop_crc_par1 (regi_iop + 1024) -#define regi_iop_dmc_in0 (regi_iop + 1152) -#define regi_iop_dmc_in1 (regi_iop + 1280) -#define regi_iop_dmc_out0 (regi_iop + 1408) -#define regi_iop_dmc_out1 (regi_iop + 1536) -#define regi_iop_fifo_in0 (regi_iop + 1664) -#define regi_iop_fifo_in1 (regi_iop + 1792) -#define regi_iop_fifo_out0 (regi_iop + 1920) -#define regi_iop_fifo_out1 (regi_iop + 2048) -#define regi_iop_scrc_in0 (regi_iop + 2176) -#define regi_iop_scrc_in1 (regi_iop + 2304) -#define regi_iop_scrc_out0 (regi_iop + 2432) -#define regi_iop_scrc_out1 (regi_iop + 2560) -#define regi_iop_timer_grp0 (regi_iop + 2688) -#define regi_iop_timer_grp1 (regi_iop + 2816) -#define regi_iop_timer_grp2 (regi_iop + 2944) -#define regi_iop_timer_grp3 (regi_iop + 3072) -#define regi_iop_sap_in (regi_iop + 3328) -#define regi_iop_sap_out (regi_iop + 3584) -#define regi_iop_spu0 (regi_iop + 3840) -#define regi_iop_spu1 (regi_iop + 4096) -#define regi_iop_sw_cfg (regi_iop + 4352) -#define regi_iop_sw_cpu (regi_iop + 4608) -#define regi_iop_sw_mpu (regi_iop + 4864) -#define regi_iop_sw_spu0 (regi_iop + 5120) -#define regi_iop_sw_spu1 (regi_iop + 5376) -#define regi_iop_mpu (regi_iop + 5632) diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 5548ac10074f..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h +++ /dev/null @@ -1,179 +0,0 @@ -#ifndef __iop_sap_in_defs_h -#define __iop_sap_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_in.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r - * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_in */ - -/* Register rw_bus0_sync, scope iop_sap_in, type rw */ -typedef struct { - unsigned int byte0_sel : 2; - unsigned int byte0_ext_src : 3; - unsigned int byte0_edge : 2; - unsigned int byte0_delay : 1; - unsigned int byte1_sel : 2; - unsigned int byte1_ext_src : 3; - unsigned int byte1_edge : 2; - unsigned int byte1_delay : 1; - unsigned int byte2_sel : 2; - unsigned int byte2_ext_src : 3; - unsigned int byte2_edge : 2; - unsigned int byte2_delay : 1; - unsigned int byte3_sel : 2; - unsigned int byte3_ext_src : 3; - unsigned int byte3_edge : 2; - unsigned int byte3_delay : 1; -} reg_iop_sap_in_rw_bus0_sync; -#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 -#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 - -/* Register rw_bus1_sync, scope iop_sap_in, type rw */ -typedef struct { - unsigned int byte0_sel : 2; - unsigned int byte0_ext_src : 3; - unsigned int byte0_edge : 2; - unsigned int byte0_delay : 1; - unsigned int byte1_sel : 2; - unsigned int byte1_ext_src : 3; - unsigned int byte1_edge : 2; - unsigned int byte1_delay : 1; - unsigned int byte2_sel : 2; - unsigned int byte2_ext_src : 3; - unsigned int byte2_edge : 2; - unsigned int byte2_delay : 1; - unsigned int byte3_sel : 2; - unsigned int byte3_ext_src : 3; - unsigned int byte3_edge : 2; - unsigned int byte3_delay : 1; -} reg_iop_sap_in_rw_bus1_sync; -#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 -#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 1; - unsigned int logic : 2; - unsigned int dummy1 : 22; -} reg_iop_sap_in_rw_gio; -#define REG_RD_ADDR_iop_sap_in_rw_gio 8 -#define REG_WR_ADDR_iop_sap_in_rw_gio 8 - - -/* Constants */ -enum { - regk_iop_sap_in_and = 0x00000002, - regk_iop_sap_in_ext_clk200 = 0x00000003, - regk_iop_sap_in_gio1 = 0x00000000, - regk_iop_sap_in_gio13 = 0x00000005, - regk_iop_sap_in_gio18 = 0x00000003, - regk_iop_sap_in_gio19 = 0x00000004, - regk_iop_sap_in_gio21 = 0x00000006, - regk_iop_sap_in_gio23 = 0x00000005, - regk_iop_sap_in_gio29 = 0x00000007, - regk_iop_sap_in_gio5 = 0x00000004, - regk_iop_sap_in_gio6 = 0x00000001, - regk_iop_sap_in_gio7 = 0x00000002, - regk_iop_sap_in_inv = 0x00000001, - regk_iop_sap_in_neg = 0x00000002, - regk_iop_sap_in_no = 0x00000000, - regk_iop_sap_in_no_del_ext_clk200 = 0x00000001, - regk_iop_sap_in_none = 0x00000000, - regk_iop_sap_in_or = 0x00000003, - regk_iop_sap_in_pos = 0x00000001, - regk_iop_sap_in_pos_neg = 0x00000003, - regk_iop_sap_in_rw_bus0_sync_default = 0x02020202, - regk_iop_sap_in_rw_bus1_sync_default = 0x02020202, - regk_iop_sap_in_rw_gio_default = 0x00000002, - regk_iop_sap_in_rw_gio_size = 0x00000020, - regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006, - regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004, - regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005, - regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007, - regk_iop_sap_in_tmr_clk200 = 0x00000000, - regk_iop_sap_in_two_clk200 = 0x00000002, - regk_iop_sap_in_yes = 0x00000001 -}; -#endif /* __iop_sap_in_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 273936996183..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h +++ /dev/null @@ -1,306 +0,0 @@ -#ifndef __iop_sap_out_defs_h -#define __iop_sap_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_out.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r - * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_out */ - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -typedef struct { - unsigned int clk0_src : 2; - unsigned int clk0_gate_src : 2; - unsigned int clk0_force_src : 3; - unsigned int clk1_src : 2; - unsigned int clk1_gate_src : 2; - unsigned int clk1_force_src : 3; - unsigned int clk2_src : 2; - unsigned int clk2_gate_src : 2; - unsigned int clk2_force_src : 3; - unsigned int clk3_src : 2; - unsigned int clk3_gate_src : 2; - unsigned int clk3_force_src : 3; - unsigned int dummy1 : 4; -} reg_iop_sap_out_rw_gen_gated; -#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 -#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 - -/* Register rw_bus0, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte2_clk_sel : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_bus0; -#define REG_RD_ADDR_iop_sap_out_rw_bus0 4 -#define REG_WR_ADDR_iop_sap_out_rw_bus0 4 - -/* Register rw_bus1, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte2_clk_sel : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_bus1; -#define REG_RD_ADDR_iop_sap_out_rw_bus1 8 -#define REG_WR_ADDR_iop_sap_out_rw_bus1 8 - -/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_clk_ext : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_logic : 2; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_clk_ext : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus0_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12 -#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12 - -/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 3; - unsigned int byte2_clk_ext : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_logic : 2; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_clk_ext : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus0_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16 -#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16 - -/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_clk_ext : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_logic : 2; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_clk_ext : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus1_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20 -#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20 - -/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 3; - unsigned int byte2_clk_ext : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_logic : 2; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_clk_ext : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus1_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24 -#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -typedef struct { - unsigned int out_clk_sel : 3; - unsigned int out_clk_ext : 4; - unsigned int out_gated_clk : 2; - unsigned int out_clk_inv : 1; - unsigned int out_logic : 1; - unsigned int oe_clk_sel : 3; - unsigned int oe_clk_ext : 3; - unsigned int oe_gated_clk : 2; - unsigned int oe_clk_inv : 1; - unsigned int oe_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_gio; -#define REG_RD_ADDR_iop_sap_out_rw_gio 28 -#define REG_WR_ADDR_iop_sap_out_rw_gio 28 - - -/* Constants */ -enum { - regk_iop_sap_out_and = 0x00000002, - regk_iop_sap_out_clk0 = 0x00000000, - regk_iop_sap_out_clk1 = 0x00000001, - regk_iop_sap_out_clk12 = 0x00000002, - regk_iop_sap_out_clk2 = 0x00000002, - regk_iop_sap_out_clk200 = 0x00000001, - regk_iop_sap_out_clk3 = 0x00000003, - regk_iop_sap_out_ext = 0x00000003, - regk_iop_sap_out_gated = 0x00000004, - regk_iop_sap_out_gio1 = 0x00000000, - regk_iop_sap_out_gio13 = 0x00000002, - regk_iop_sap_out_gio13_clk = 0x0000000c, - regk_iop_sap_out_gio15 = 0x00000001, - regk_iop_sap_out_gio18 = 0x00000003, - regk_iop_sap_out_gio18_clk = 0x0000000d, - regk_iop_sap_out_gio1_clk = 0x00000008, - regk_iop_sap_out_gio21_clk = 0x0000000e, - regk_iop_sap_out_gio23 = 0x00000002, - regk_iop_sap_out_gio29_clk = 0x0000000f, - regk_iop_sap_out_gio31 = 0x00000003, - regk_iop_sap_out_gio5 = 0x00000001, - regk_iop_sap_out_gio5_clk = 0x00000009, - regk_iop_sap_out_gio6_clk = 0x0000000a, - regk_iop_sap_out_gio7 = 0x00000000, - regk_iop_sap_out_gio7_clk = 0x0000000b, - regk_iop_sap_out_gio_in13 = 0x00000001, - regk_iop_sap_out_gio_in21 = 0x00000002, - regk_iop_sap_out_gio_in29 = 0x00000003, - regk_iop_sap_out_gio_in5 = 0x00000000, - regk_iop_sap_out_inv = 0x00000001, - regk_iop_sap_out_nand = 0x00000003, - regk_iop_sap_out_no = 0x00000000, - regk_iop_sap_out_none = 0x00000000, - regk_iop_sap_out_rw_bus0_default = 0x00000000, - regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus1_default = 0x00000000, - regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_gen_gated_default = 0x00000000, - regk_iop_sap_out_rw_gio_default = 0x00000000, - regk_iop_sap_out_rw_gio_size = 0x00000020, - regk_iop_sap_out_spu0_gio0 = 0x00000002, - regk_iop_sap_out_spu0_gio1 = 0x00000003, - regk_iop_sap_out_spu0_gio12 = 0x00000004, - regk_iop_sap_out_spu0_gio13 = 0x00000004, - regk_iop_sap_out_spu0_gio14 = 0x00000004, - regk_iop_sap_out_spu0_gio15 = 0x00000004, - regk_iop_sap_out_spu0_gio2 = 0x00000002, - regk_iop_sap_out_spu0_gio3 = 0x00000003, - regk_iop_sap_out_spu0_gio4 = 0x00000002, - regk_iop_sap_out_spu0_gio5 = 0x00000003, - regk_iop_sap_out_spu0_gio6 = 0x00000002, - regk_iop_sap_out_spu0_gio7 = 0x00000003, - regk_iop_sap_out_spu1_gio0 = 0x00000005, - regk_iop_sap_out_spu1_gio1 = 0x00000006, - regk_iop_sap_out_spu1_gio12 = 0x00000007, - regk_iop_sap_out_spu1_gio13 = 0x00000007, - regk_iop_sap_out_spu1_gio14 = 0x00000007, - regk_iop_sap_out_spu1_gio15 = 0x00000007, - regk_iop_sap_out_spu1_gio2 = 0x00000005, - regk_iop_sap_out_spu1_gio3 = 0x00000006, - regk_iop_sap_out_spu1_gio4 = 0x00000005, - regk_iop_sap_out_spu1_gio5 = 0x00000006, - regk_iop_sap_out_spu1_gio6 = 0x00000005, - regk_iop_sap_out_spu1_gio7 = 0x00000006, - regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004, - regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005, - regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006, - regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007, - regk_iop_sap_out_tmr = 0x00000005, - regk_iop_sap_out_yes = 0x00000001 -}; -#endif /* __iop_sap_out_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h deleted file mode 100644 index 4f0a9a81e737..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h +++ /dev/null @@ -1,160 +0,0 @@ -#ifndef __iop_scrc_in_defs_h -#define __iop_scrc_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_in.r - * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r - * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_scrc_in */ - -/* Register rw_cfg, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int trig : 2; - unsigned int dummy1 : 30; -} reg_iop_scrc_in_rw_cfg; -#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0 -#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_in_rw_ctrl; -#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4 - -/* Register r_stat, scope iop_scrc_in, type r */ -typedef struct { - unsigned int err : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_in_r_stat; -#define REG_RD_ADDR_iop_scrc_in_r_stat 8 - -/* Register rw_init_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_init_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12 -#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12 - -/* Register rs_computed_crc, scope iop_scrc_in, type rs */ -typedef unsigned int reg_iop_scrc_in_rs_computed_crc; -#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16 - -/* Register r_computed_crc, scope iop_scrc_in, type r */ -typedef unsigned int reg_iop_scrc_in_r_computed_crc; -#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20 - -/* Register rw_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_crc 24 -#define REG_WR_ADDR_iop_scrc_in_rw_crc 24 - -/* Register rw_correct_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_correct_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28 -#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28 - -/* Register rw_wr1bit, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int data : 2; - unsigned int last : 2; - unsigned int dummy1 : 28; -} reg_iop_scrc_in_rw_wr1bit; -#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32 -#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32 - - -/* Constants */ -enum { - regk_iop_scrc_in_dif_in = 0x00000002, - regk_iop_scrc_in_hi = 0x00000000, - regk_iop_scrc_in_neg = 0x00000002, - regk_iop_scrc_in_no = 0x00000000, - regk_iop_scrc_in_pos = 0x00000001, - regk_iop_scrc_in_pos_neg = 0x00000003, - regk_iop_scrc_in_r_computed_crc_default = 0x00000000, - regk_iop_scrc_in_rs_computed_crc_default = 0x00000000, - regk_iop_scrc_in_rw_cfg_default = 0x00000000, - regk_iop_scrc_in_rw_ctrl_default = 0x00000000, - regk_iop_scrc_in_rw_init_crc_default = 0x00000000, - regk_iop_scrc_in_set0 = 0x00000000, - regk_iop_scrc_in_set1 = 0x00000001, - regk_iop_scrc_in_yes = 0x00000001 -}; -#endif /* __iop_scrc_in_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h deleted file mode 100644 index fd1d6ea1d484..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h +++ /dev/null @@ -1,146 +0,0 @@ -#ifndef __iop_scrc_out_defs_h -#define __iop_scrc_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_out.r - * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r - * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_scrc_out */ - -/* Register rw_cfg, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int trig : 2; - unsigned int inv_crc : 1; - unsigned int dummy1 : 29; -} reg_iop_scrc_out_rw_cfg; -#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0 -#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int strb_src : 1; - unsigned int out_src : 1; - unsigned int dummy1 : 30; -} reg_iop_scrc_out_rw_ctrl; -#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4 - -/* Register rw_init_crc, scope iop_scrc_out, type rw */ -typedef unsigned int reg_iop_scrc_out_rw_init_crc; -#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8 -#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8 - -/* Register rw_crc, scope iop_scrc_out, type rw */ -typedef unsigned int reg_iop_scrc_out_rw_crc; -#define REG_RD_ADDR_iop_scrc_out_rw_crc 12 -#define REG_WR_ADDR_iop_scrc_out_rw_crc 12 - -/* Register rw_data, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int val : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_out_rw_data; -#define REG_RD_ADDR_iop_scrc_out_rw_data 16 -#define REG_WR_ADDR_iop_scrc_out_rw_data 16 - -/* Register r_computed_crc, scope iop_scrc_out, type r */ -typedef unsigned int reg_iop_scrc_out_r_computed_crc; -#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20 - - -/* Constants */ -enum { - regk_iop_scrc_out_crc = 0x00000001, - regk_iop_scrc_out_data = 0x00000000, - regk_iop_scrc_out_dif = 0x00000001, - regk_iop_scrc_out_hi = 0x00000000, - regk_iop_scrc_out_neg = 0x00000002, - regk_iop_scrc_out_no = 0x00000000, - regk_iop_scrc_out_pos = 0x00000001, - regk_iop_scrc_out_pos_neg = 0x00000003, - regk_iop_scrc_out_reg = 0x00000000, - regk_iop_scrc_out_rw_cfg_default = 0x00000000, - regk_iop_scrc_out_rw_crc_default = 0x00000000, - regk_iop_scrc_out_rw_ctrl_default = 0x00000000, - regk_iop_scrc_out_rw_data_default = 0x00000000, - regk_iop_scrc_out_rw_init_crc_default = 0x00000000, - regk_iop_scrc_out_yes = 0x00000001 -}; -#endif /* __iop_scrc_out_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h deleted file mode 100644 index 0fda26e2f06f..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h +++ /dev/null @@ -1,453 +0,0 @@ -#ifndef __iop_spu_defs_h -#define __iop_spu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_spu.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r - * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_spu */ - -#define STRIDE_iop_spu_rw_r 4 -/* Register rw_r, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_r; -#define REG_RD_ADDR_iop_spu_rw_r 0 -#define REG_WR_ADDR_iop_spu_rw_r 0 - -/* Register rw_seq_pc, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_seq_pc; -#define REG_RD_ADDR_iop_spu_rw_seq_pc 64 -#define REG_WR_ADDR_iop_spu_rw_seq_pc 64 - -/* Register rw_fsm_pc, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_fsm_pc; -#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68 -#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68 - -/* Register rw_ctrl, scope iop_spu, type rw */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_iop_spu_rw_ctrl; -#define REG_RD_ADDR_iop_spu_rw_ctrl 72 -#define REG_WR_ADDR_iop_spu_rw_ctrl 72 - -/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ -typedef struct { - unsigned int val0 : 5; - unsigned int src0 : 3; - unsigned int val1 : 5; - unsigned int src1 : 3; - unsigned int val2 : 5; - unsigned int src2 : 3; - unsigned int val3 : 5; - unsigned int src3 : 3; -} reg_iop_spu_rw_fsm_inputs3_0; -#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76 -#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76 - -/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ -typedef struct { - unsigned int val4 : 5; - unsigned int src4 : 3; - unsigned int val5 : 5; - unsigned int src5 : 3; - unsigned int val6 : 5; - unsigned int src6 : 3; - unsigned int val7 : 5; - unsigned int src7 : 3; -} reg_iop_spu_rw_fsm_inputs7_4; -#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80 -#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80 - -/* Register rw_gio_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out; -#define REG_RD_ADDR_iop_spu_rw_gio_out 84 -#define REG_WR_ADDR_iop_spu_rw_gio_out 84 - -/* Register rw_bus0_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_bus0_out; -#define REG_RD_ADDR_iop_spu_rw_bus0_out 88 -#define REG_WR_ADDR_iop_spu_rw_bus0_out 88 - -/* Register rw_bus1_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_bus1_out; -#define REG_RD_ADDR_iop_spu_rw_bus1_out 92 -#define REG_WR_ADDR_iop_spu_rw_bus1_out 92 - -/* Register r_gio_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_gio_in; -#define REG_RD_ADDR_iop_spu_r_gio_in 96 - -/* Register r_bus0_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_bus0_in; -#define REG_RD_ADDR_iop_spu_r_bus0_in 100 - -/* Register r_bus1_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_bus1_in; -#define REG_RD_ADDR_iop_spu_r_bus1_in 104 - -/* Register rw_gio_out_set, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out_set; -#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108 -#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108 - -/* Register rw_gio_out_clr, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out_clr; -#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112 -#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112 - -/* Register rs_wr_stat, scope iop_spu, type rs */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_spu_rs_wr_stat; -#define REG_RD_ADDR_iop_spu_rs_wr_stat 116 - -/* Register r_wr_stat, scope iop_spu, type r */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_spu_r_wr_stat; -#define REG_RD_ADDR_iop_spu_r_wr_stat 120 - -/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in; -#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124 - -/* Register r_stat_in, scope iop_spu, type r */ -typedef struct { - unsigned int timer_grp_lo : 4; - unsigned int fifo_out_last : 1; - unsigned int fifo_out_rdy : 1; - unsigned int fifo_out_all : 1; - unsigned int fifo_in_rdy : 1; - unsigned int dmc_out_all : 1; - unsigned int dmc_out_dth : 1; - unsigned int dmc_out_eop : 1; - unsigned int dmc_out_dv : 1; - unsigned int dmc_out_last : 1; - unsigned int dmc_out_cmd_rq : 1; - unsigned int dmc_out_cmd_rdy : 1; - unsigned int pcrc_correct : 1; - unsigned int timer_grp_hi : 4; - unsigned int dmc_in_sth : 1; - unsigned int dmc_in_full : 1; - unsigned int dmc_in_cmd_rdy : 1; - unsigned int spu_gio_out : 4; - unsigned int sync_clk12 : 1; - unsigned int scrc_out_data : 1; - unsigned int scrc_in_err : 1; - unsigned int mc_busy : 1; - unsigned int mc_owned : 1; -} reg_iop_spu_r_stat_in; -#define REG_RD_ADDR_iop_spu_r_stat_in 128 - -/* Register r_trigger_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_trigger_in; -#define REG_RD_ADDR_iop_spu_r_trigger_in 132 - -/* Register r_special_stat, scope iop_spu, type r */ -typedef struct { - unsigned int c_flag : 1; - unsigned int v_flag : 1; - unsigned int z_flag : 1; - unsigned int n_flag : 1; - unsigned int xor_bus0_r2_0 : 1; - unsigned int xor_bus1_r3_0 : 1; - unsigned int xor_bus0m_r2_0 : 1; - unsigned int xor_bus1m_r3_0 : 1; - unsigned int fsm_in0 : 1; - unsigned int fsm_in1 : 1; - unsigned int fsm_in2 : 1; - unsigned int fsm_in3 : 1; - unsigned int fsm_in4 : 1; - unsigned int fsm_in5 : 1; - unsigned int fsm_in6 : 1; - unsigned int fsm_in7 : 1; - unsigned int event0 : 1; - unsigned int event1 : 1; - unsigned int event2 : 1; - unsigned int event3 : 1; - unsigned int dummy1 : 12; -} reg_iop_spu_r_special_stat; -#define REG_RD_ADDR_iop_spu_r_special_stat 136 - -/* Register rw_reg_access, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 13; - unsigned int dummy1 : 3; - unsigned int imm_hi : 16; -} reg_iop_spu_rw_reg_access; -#define REG_RD_ADDR_iop_spu_rw_reg_access 140 -#define REG_WR_ADDR_iop_spu_rw_reg_access 140 - -#define STRIDE_iop_spu_rw_event_cfg 4 -/* Register rw_event_cfg, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int src : 2; - unsigned int eq_en : 1; - unsigned int eq_inv : 1; - unsigned int gt_en : 1; - unsigned int gt_inv : 1; - unsigned int dummy1 : 14; -} reg_iop_spu_rw_event_cfg; -#define REG_RD_ADDR_iop_spu_rw_event_cfg 144 -#define REG_WR_ADDR_iop_spu_rw_event_cfg 144 - -#define STRIDE_iop_spu_rw_event_mask 4 -/* Register rw_event_mask, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_event_mask; -#define REG_RD_ADDR_iop_spu_rw_event_mask 160 -#define REG_WR_ADDR_iop_spu_rw_event_mask 160 - -#define STRIDE_iop_spu_rw_event_val 4 -/* Register rw_event_val, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_event_val; -#define REG_RD_ADDR_iop_spu_rw_event_val 176 -#define REG_WR_ADDR_iop_spu_rw_event_val 176 - -/* Register rw_event_ret, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_event_ret; -#define REG_RD_ADDR_iop_spu_rw_event_ret 192 -#define REG_WR_ADDR_iop_spu_rw_event_ret 192 - -/* Register r_trace, scope iop_spu, type r */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int c_flag : 1; - unsigned int v_flag : 1; - unsigned int z_flag : 1; - unsigned int n_flag : 1; - unsigned int seq_addr : 12; - unsigned int dummy1 : 2; - unsigned int fsm_addr : 12; -} reg_iop_spu_r_trace; -#define REG_RD_ADDR_iop_spu_r_trace 196 - -/* Register r_fsm_trace, scope iop_spu, type r */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int tmr_done : 1; - unsigned int inp0 : 1; - unsigned int inp1 : 1; - unsigned int inp2 : 1; - unsigned int inp3 : 1; - unsigned int event0 : 1; - unsigned int event1 : 1; - unsigned int event2 : 1; - unsigned int event3 : 1; - unsigned int gio_out : 8; - unsigned int dummy1 : 1; - unsigned int fsm_addr : 12; -} reg_iop_spu_r_fsm_trace; -#define REG_RD_ADDR_iop_spu_r_fsm_trace 200 - -#define STRIDE_iop_spu_rw_brp 4 -/* Register rw_brp, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int dummy1 : 18; -} reg_iop_spu_rw_brp; -#define REG_RD_ADDR_iop_spu_rw_brp 204 -#define REG_WR_ADDR_iop_spu_rw_brp 204 - - -/* Constants */ -enum { - regk_iop_spu_attn_hi = 0x00000005, - regk_iop_spu_attn_lo = 0x00000005, - regk_iop_spu_attn_r0 = 0x00000000, - regk_iop_spu_attn_r1 = 0x00000001, - regk_iop_spu_attn_r10 = 0x00000002, - regk_iop_spu_attn_r11 = 0x00000003, - regk_iop_spu_attn_r12 = 0x00000004, - regk_iop_spu_attn_r13 = 0x00000005, - regk_iop_spu_attn_r14 = 0x00000006, - regk_iop_spu_attn_r15 = 0x00000007, - regk_iop_spu_attn_r2 = 0x00000002, - regk_iop_spu_attn_r3 = 0x00000003, - regk_iop_spu_attn_r4 = 0x00000004, - regk_iop_spu_attn_r5 = 0x00000005, - regk_iop_spu_attn_r6 = 0x00000006, - regk_iop_spu_attn_r7 = 0x00000007, - regk_iop_spu_attn_r8 = 0x00000000, - regk_iop_spu_attn_r9 = 0x00000001, - regk_iop_spu_c = 0x00000000, - regk_iop_spu_flag = 0x00000002, - regk_iop_spu_gio_in = 0x00000000, - regk_iop_spu_gio_out = 0x00000005, - regk_iop_spu_gio_out0 = 0x00000008, - regk_iop_spu_gio_out1 = 0x00000009, - regk_iop_spu_gio_out2 = 0x0000000a, - regk_iop_spu_gio_out3 = 0x0000000b, - regk_iop_spu_gio_out4 = 0x0000000c, - regk_iop_spu_gio_out5 = 0x0000000d, - regk_iop_spu_gio_out6 = 0x0000000e, - regk_iop_spu_gio_out7 = 0x0000000f, - regk_iop_spu_n = 0x00000003, - regk_iop_spu_no = 0x00000000, - regk_iop_spu_r0 = 0x00000008, - regk_iop_spu_r1 = 0x00000009, - regk_iop_spu_r10 = 0x0000000a, - regk_iop_spu_r11 = 0x0000000b, - regk_iop_spu_r12 = 0x0000000c, - regk_iop_spu_r13 = 0x0000000d, - regk_iop_spu_r14 = 0x0000000e, - regk_iop_spu_r15 = 0x0000000f, - regk_iop_spu_r2 = 0x0000000a, - regk_iop_spu_r3 = 0x0000000b, - regk_iop_spu_r4 = 0x0000000c, - regk_iop_spu_r5 = 0x0000000d, - regk_iop_spu_r6 = 0x0000000e, - regk_iop_spu_r7 = 0x0000000f, - regk_iop_spu_r8 = 0x00000008, - regk_iop_spu_r9 = 0x00000009, - regk_iop_spu_reg_hi = 0x00000002, - regk_iop_spu_reg_lo = 0x00000002, - regk_iop_spu_rw_brp_default = 0x00000000, - regk_iop_spu_rw_brp_size = 0x00000004, - regk_iop_spu_rw_ctrl_default = 0x00000000, - regk_iop_spu_rw_event_cfg_size = 0x00000004, - regk_iop_spu_rw_event_mask_size = 0x00000004, - regk_iop_spu_rw_event_val_size = 0x00000004, - regk_iop_spu_rw_gio_out_default = 0x00000000, - regk_iop_spu_rw_r_size = 0x00000010, - regk_iop_spu_rw_reg_access_default = 0x00000000, - regk_iop_spu_stat_in = 0x00000002, - regk_iop_spu_statin_hi = 0x00000004, - regk_iop_spu_statin_lo = 0x00000004, - regk_iop_spu_trig = 0x00000003, - regk_iop_spu_trigger = 0x00000006, - regk_iop_spu_v = 0x00000001, - regk_iop_spu_wsts_gioout_spec = 0x00000001, - regk_iop_spu_xor = 0x00000003, - regk_iop_spu_xor_bus0_r2_0 = 0x00000000, - regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, - regk_iop_spu_xor_bus1_r3_0 = 0x00000001, - regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, - regk_iop_spu_yes = 0x00000001, - regk_iop_spu_z = 0x00000002 -}; -#endif /* __iop_spu_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index d7b6d75884d2..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null @@ -1,1042 +0,0 @@ -#ifndef __iop_sw_cfg_defs_h -#define __iop_sw_cfg_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cfg */ - -/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 - -/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 - -/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 - -/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 - -/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 - -/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 - -/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 - -/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in0_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 - -/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 - -/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in1_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 - -/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 - -/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out0_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 - -/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 - -/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out1_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60 - -/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 - -/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 - -/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 - -/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 - -/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80 - -/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 - -/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 - -/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp4_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp5_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp6_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp7_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 - -/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus0_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136 - -/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus0_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 - -/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus1_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144 - -/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus1_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_byte0 : 2; - unsigned int bus0_byte1 : 2; - unsigned int bus0_byte2 : 2; - unsigned int bus0_byte3 : 2; - unsigned int bus1_byte0 : 2; - unsigned int bus1_byte1 : 2; - unsigned int bus1_byte2 : 2; - unsigned int bus1_byte3 : 2; - unsigned int gio3_0 : 2; - unsigned int gio7_4 : 2; - unsigned int gio11_8 : 2; - unsigned int gio15_12 : 2; - unsigned int gio19_16 : 2; - unsigned int gio23_20 : 2; - unsigned int gio27_24 : 2; - unsigned int gio31_28 : 2; -} reg_iop_sw_cfg_rw_pinmapping; -#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160 -#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_lo : 3; - unsigned int bus0_hi : 3; - unsigned int bus0_lo_oe : 3; - unsigned int bus0_hi_oe : 3; - unsigned int bus1_lo : 3; - unsigned int bus1_hi : 3; - unsigned int bus1_lo_oe : 3; - unsigned int bus1_hi_oe : 3; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_bus_out_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio0 : 4; - unsigned int gio0_oe : 2; - unsigned int gio1 : 4; - unsigned int gio1_oe : 2; - unsigned int gio2 : 4; - unsigned int gio2_oe : 2; - unsigned int gio3 : 4; - unsigned int gio3_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio4 : 4; - unsigned int gio4_oe : 2; - unsigned int gio5 : 4; - unsigned int gio5_oe : 2; - unsigned int gio6 : 4; - unsigned int gio6_oe : 2; - unsigned int gio7 : 4; - unsigned int gio7_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio8 : 4; - unsigned int gio8_oe : 2; - unsigned int gio9 : 4; - unsigned int gio9_oe : 2; - unsigned int gio10 : 4; - unsigned int gio10_oe : 2; - unsigned int gio11 : 4; - unsigned int gio11_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio12 : 4; - unsigned int gio12_oe : 2; - unsigned int gio13 : 4; - unsigned int gio13_oe : 2; - unsigned int gio14 : 4; - unsigned int gio14_oe : 2; - unsigned int gio15 : 4; - unsigned int gio15_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio16 : 4; - unsigned int gio16_oe : 2; - unsigned int gio17 : 4; - unsigned int gio17_oe : 2; - unsigned int gio18 : 4; - unsigned int gio18_oe : 2; - unsigned int gio19 : 4; - unsigned int gio19_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio20 : 4; - unsigned int gio20_oe : 2; - unsigned int gio21 : 4; - unsigned int gio21_oe : 2; - unsigned int gio22 : 4; - unsigned int gio22_oe : 2; - unsigned int gio23 : 4; - unsigned int gio23_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio24 : 4; - unsigned int gio24_oe : 2; - unsigned int gio25 : 4; - unsigned int gio25_oe : 2; - unsigned int gio26 : 4; - unsigned int gio26_oe : 2; - unsigned int gio27 : 4; - unsigned int gio27_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio28 : 4; - unsigned int gio28_oe : 2; - unsigned int gio29 : 4; - unsigned int gio29_oe : 2; - unsigned int gio30 : 4; - unsigned int gio30_oe : 2; - unsigned int gio31 : 4; - unsigned int gio31_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 - -/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 2; - unsigned int bus1_in : 2; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_spu0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200 - -/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 2; - unsigned int bus1_in : 2; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_spu1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 - -/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 - -/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int grp0_dis : 1; - unsigned int grp0_en : 1; - unsigned int grp1_dis : 1; - unsigned int grp1_en : 1; - unsigned int grp2_dis : 1; - unsigned int grp2_en : 1; - unsigned int grp3_dis : 1; - unsigned int grp3_en : 1; - unsigned int grp4_dis : 1; - unsigned int grp4_en : 1; - unsigned int grp5_dis : 1; - unsigned int grp5_en : 1; - unsigned int grp6_dis : 1; - unsigned int grp6_en : 1; - unsigned int grp7_dis : 1; - unsigned int grp7_en : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_trigger_grps_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 - -/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int dmc0_usr : 1; - unsigned int out_strb : 5; - unsigned int in_src : 3; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int out_src : 1; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_pdp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 - -/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int dmc1_usr : 1; - unsigned int out_strb : 5; - unsigned int in_src : 3; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int out_src : 1; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_pdp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int sdp_out0_strb : 3; - unsigned int sdp_out1_strb : 3; - unsigned int sdp_in0_data : 3; - unsigned int sdp_in0_last : 2; - unsigned int sdp_in0_strb : 3; - unsigned int sdp_in1_data : 3; - unsigned int sdp_in1_last : 2; - unsigned int sdp_in1_strb : 3; - unsigned int dummy1 : 10; -} reg_iop_sw_cfg_rw_sdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236 -#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236 - - -/* Constants */ -enum { - regk_iop_sw_cfg_a = 0x00000001, - regk_iop_sw_cfg_b = 0x00000002, - regk_iop_sw_cfg_bus0 = 0x00000000, - regk_iop_sw_cfg_bus0_rot16 = 0x00000004, - regk_iop_sw_cfg_bus0_rot24 = 0x00000006, - regk_iop_sw_cfg_bus0_rot8 = 0x00000002, - regk_iop_sw_cfg_bus1 = 0x00000001, - regk_iop_sw_cfg_bus1_rot16 = 0x00000005, - regk_iop_sw_cfg_bus1_rot24 = 0x00000007, - regk_iop_sw_cfg_bus1_rot8 = 0x00000003, - regk_iop_sw_cfg_clk12 = 0x00000000, - regk_iop_sw_cfg_cpu = 0x00000000, - regk_iop_sw_cfg_dmc0 = 0x00000000, - regk_iop_sw_cfg_dmc1 = 0x00000001, - regk_iop_sw_cfg_gated_clk0 = 0x00000010, - regk_iop_sw_cfg_gated_clk1 = 0x00000011, - regk_iop_sw_cfg_gated_clk2 = 0x00000012, - regk_iop_sw_cfg_gated_clk3 = 0x00000013, - regk_iop_sw_cfg_gio0 = 0x00000004, - regk_iop_sw_cfg_gio1 = 0x00000001, - regk_iop_sw_cfg_gio2 = 0x00000005, - regk_iop_sw_cfg_gio3 = 0x00000002, - regk_iop_sw_cfg_gio4 = 0x00000006, - regk_iop_sw_cfg_gio5 = 0x00000003, - regk_iop_sw_cfg_gio6 = 0x00000007, - regk_iop_sw_cfg_gio7 = 0x00000004, - regk_iop_sw_cfg_gio_in0 = 0x00000000, - regk_iop_sw_cfg_gio_in1 = 0x00000001, - regk_iop_sw_cfg_gio_in10 = 0x00000002, - regk_iop_sw_cfg_gio_in11 = 0x00000003, - regk_iop_sw_cfg_gio_in14 = 0x00000004, - regk_iop_sw_cfg_gio_in15 = 0x00000005, - regk_iop_sw_cfg_gio_in18 = 0x00000002, - regk_iop_sw_cfg_gio_in19 = 0x00000003, - regk_iop_sw_cfg_gio_in20 = 0x00000004, - regk_iop_sw_cfg_gio_in21 = 0x00000005, - regk_iop_sw_cfg_gio_in26 = 0x00000006, - regk_iop_sw_cfg_gio_in27 = 0x00000007, - regk_iop_sw_cfg_gio_in28 = 0x00000006, - regk_iop_sw_cfg_gio_in29 = 0x00000007, - regk_iop_sw_cfg_gio_in4 = 0x00000000, - regk_iop_sw_cfg_gio_in5 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, - regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, - regk_iop_sw_cfg_mpu = 0x00000001, - regk_iop_sw_cfg_none = 0x00000000, - regk_iop_sw_cfg_par0 = 0x00000000, - regk_iop_sw_cfg_par1 = 0x00000001, - regk_iop_sw_cfg_pdp_out0 = 0x00000002, - regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, - regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, - regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, - regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, - regk_iop_sw_cfg_pdp_out1 = 0x00000003, - regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, - regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, - regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, - regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, - regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, - regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, - regk_iop_sw_cfg_sdp_out0 = 0x00000008, - regk_iop_sw_cfg_sdp_out1 = 0x00000009, - regk_iop_sw_cfg_size16 = 0x00000002, - regk_iop_sw_cfg_size24 = 0x00000003, - regk_iop_sw_cfg_size32 = 0x00000004, - regk_iop_sw_cfg_size8 = 0x00000001, - regk_iop_sw_cfg_spu0 = 0x00000002, - regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, - regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, - regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, - regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, - regk_iop_sw_cfg_spu0_g0 = 0x0000000e, - regk_iop_sw_cfg_spu0_g1 = 0x0000000e, - regk_iop_sw_cfg_spu0_g2 = 0x0000000e, - regk_iop_sw_cfg_spu0_g3 = 0x0000000e, - regk_iop_sw_cfg_spu0_g4 = 0x0000000e, - regk_iop_sw_cfg_spu0_g5 = 0x0000000e, - regk_iop_sw_cfg_spu0_g6 = 0x0000000e, - regk_iop_sw_cfg_spu0_g7 = 0x0000000e, - regk_iop_sw_cfg_spu0_gio0 = 0x00000000, - regk_iop_sw_cfg_spu0_gio1 = 0x00000001, - regk_iop_sw_cfg_spu0_gio2 = 0x00000000, - regk_iop_sw_cfg_spu0_gio5 = 0x00000005, - regk_iop_sw_cfg_spu0_gio6 = 0x00000006, - regk_iop_sw_cfg_spu0_gio7 = 0x00000007, - regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, - regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, - regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, - regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, - regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, - regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, - regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, - regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, - regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, - regk_iop_sw_cfg_spu1 = 0x00000003, - regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, - regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, - regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, - regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, - regk_iop_sw_cfg_spu1_g0 = 0x0000000f, - regk_iop_sw_cfg_spu1_g1 = 0x0000000f, - regk_iop_sw_cfg_spu1_g2 = 0x0000000f, - regk_iop_sw_cfg_spu1_g3 = 0x0000000f, - regk_iop_sw_cfg_spu1_g4 = 0x0000000f, - regk_iop_sw_cfg_spu1_g5 = 0x0000000f, - regk_iop_sw_cfg_spu1_g6 = 0x0000000f, - regk_iop_sw_cfg_spu1_g7 = 0x0000000f, - regk_iop_sw_cfg_spu1_gio0 = 0x00000002, - regk_iop_sw_cfg_spu1_gio1 = 0x00000003, - regk_iop_sw_cfg_spu1_gio2 = 0x00000002, - regk_iop_sw_cfg_spu1_gio5 = 0x00000005, - regk_iop_sw_cfg_spu1_gio6 = 0x00000006, - regk_iop_sw_cfg_spu1_gio7 = 0x00000007, - regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, - regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, - regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, - regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, - regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, - regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, - regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, - regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, - regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, - regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, - regk_iop_sw_cfg_timer_grp0 = 0x00000000, - regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, - regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, - regk_iop_sw_cfg_timer_grp1 = 0x00000000, - regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, - regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, - regk_iop_sw_cfg_timer_grp2 = 0x00000000, - regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, - regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, - regk_iop_sw_cfg_timer_grp3 = 0x00000000, - regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, - regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, - regk_iop_sw_cfg_trig0_0 = 0x00000000, - regk_iop_sw_cfg_trig0_1 = 0x00000000, - regk_iop_sw_cfg_trig0_2 = 0x00000000, - regk_iop_sw_cfg_trig0_3 = 0x00000000, - regk_iop_sw_cfg_trig1_0 = 0x00000000, - regk_iop_sw_cfg_trig1_1 = 0x00000000, - regk_iop_sw_cfg_trig1_2 = 0x00000000, - regk_iop_sw_cfg_trig1_3 = 0x00000000, - regk_iop_sw_cfg_trig2_0 = 0x00000000, - regk_iop_sw_cfg_trig2_1 = 0x00000000, - regk_iop_sw_cfg_trig2_2 = 0x00000000, - regk_iop_sw_cfg_trig2_3 = 0x00000000, - regk_iop_sw_cfg_trig3_0 = 0x00000000, - regk_iop_sw_cfg_trig3_1 = 0x00000000, - regk_iop_sw_cfg_trig3_2 = 0x00000000, - regk_iop_sw_cfg_trig3_3 = 0x00000000, - regk_iop_sw_cfg_trig4_0 = 0x00000001, - regk_iop_sw_cfg_trig4_1 = 0x00000001, - regk_iop_sw_cfg_trig4_2 = 0x00000001, - regk_iop_sw_cfg_trig4_3 = 0x00000001, - regk_iop_sw_cfg_trig5_0 = 0x00000001, - regk_iop_sw_cfg_trig5_1 = 0x00000001, - regk_iop_sw_cfg_trig5_2 = 0x00000001, - regk_iop_sw_cfg_trig5_3 = 0x00000001, - regk_iop_sw_cfg_trig6_0 = 0x00000001, - regk_iop_sw_cfg_trig6_1 = 0x00000001, - regk_iop_sw_cfg_trig6_2 = 0x00000001, - regk_iop_sw_cfg_trig6_3 = 0x00000001, - regk_iop_sw_cfg_trig7_0 = 0x00000001, - regk_iop_sw_cfg_trig7_1 = 0x00000001, - regk_iop_sw_cfg_trig7_2 = 0x00000001, - regk_iop_sw_cfg_trig7_3 = 0x00000001 -}; -#endif /* __iop_sw_cfg_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index 5fed844b19e2..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null @@ -1,853 +0,0 @@ -#ifndef __iop_sw_cpu_defs_h -#define __iop_sw_cpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cpu */ - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_cpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -typedef unsigned int reg_iop_sw_cpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_cpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 - -/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 - -/* Register r_bus0_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 - -/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 - -/* Register r_bus1_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_rw_intr0_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_rw_ack_intr0; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_r_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_r_masked_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_rw_intr1_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_rw_ack_intr1; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_r_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_r_masked_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112 - -/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_rw_intr2_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116 - -/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr2; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120 - -/* Register r_intr2, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_intr2; -#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124 - -/* Register r_masked_intr2, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_masked_intr2; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128 - -/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_rw_intr3_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132 - -/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr3; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136 - -/* Register r_intr3, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_r_intr3; -#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140 - -/* Register r_masked_intr3, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_r_masked_intr3; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144 - - -/* Constants */ -enum { - regk_iop_sw_cpu_copy = 0x00000000, - regk_iop_sw_cpu_no = 0x00000000, - regk_iop_sw_cpu_rd = 0x00000002, - regk_iop_sw_cpu_reg_copy = 0x00000001, - regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000, - regk_iop_sw_cpu_wr = 0x00000003, - regk_iop_sw_cpu_yes = 0x00000001 -}; -#endif /* __iop_sw_cpu_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index da718f2a8cad..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null @@ -1,893 +0,0 @@ -#ifndef __iop_sw_mpu_defs_h -#define __iop_sw_mpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_mpu */ - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_mpu_rw_sw_cfg_owner; -#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 -#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_mpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -typedef unsigned int reg_iop_sw_mpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_mpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24 - -/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 - -/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 - -/* Register r_bus0_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44 - -/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 - -/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 - -/* Register r_bus1_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88 -#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp0_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp1_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp2_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp3_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156 - - -/* Constants */ -enum { - regk_iop_sw_mpu_copy = 0x00000000, - regk_iop_sw_mpu_cpu = 0x00000000, - regk_iop_sw_mpu_mpu = 0x00000001, - regk_iop_sw_mpu_no = 0x00000000, - regk_iop_sw_mpu_nop = 0x00000000, - regk_iop_sw_mpu_rd = 0x00000002, - regk_iop_sw_mpu_reg_copy = 0x00000001, - regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, - regk_iop_sw_mpu_set = 0x00000001, - regk_iop_sw_mpu_spu0 = 0x00000002, - regk_iop_sw_mpu_spu1 = 0x00000003, - regk_iop_sw_mpu_wr = 0x00000003, - regk_iop_sw_mpu_yes = 0x00000001 -}; -#endif /* __iop_sw_mpu_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index b59dde4bd0d1..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null @@ -1,552 +0,0 @@ -#ifndef __iop_sw_spu_defs_h -#define __iop_sw_spu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_spu */ - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_spu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -typedef unsigned int reg_iop_sw_spu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -typedef unsigned int reg_iop_sw_spu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mc_data; -#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_spu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 - -/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 - -/* Register r_bus0_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 - -/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 - -/* Register r_bus1_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_gio_in; -#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80 - -/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 - -/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 - -/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 - -/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 - -/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 - -/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 - -/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 - -/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148 -#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out1 : 1; - unsigned int dmc_in1 : 1; - unsigned int dummy1 : 8; -} reg_iop_sw_spu_r_hw_intr; -#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160 -#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int other_spu_intr0 : 1; - unsigned int other_spu_intr1 : 1; - unsigned int other_spu_intr2 : 1; - unsigned int other_spu_intr3 : 1; - unsigned int other_spu_intr4 : 1; - unsigned int other_spu_intr5 : 1; - unsigned int other_spu_intr6 : 1; - unsigned int other_spu_intr7 : 1; - unsigned int other_spu_intr8 : 1; - unsigned int other_spu_intr9 : 1; - unsigned int other_spu_intr10 : 1; - unsigned int other_spu_intr11 : 1; - unsigned int other_spu_intr12 : 1; - unsigned int other_spu_intr13 : 1; - unsigned int other_spu_intr14 : 1; - unsigned int other_spu_intr15 : 1; -} reg_iop_sw_spu_r_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164 - - -/* Constants */ -enum { - regk_iop_sw_spu_copy = 0x00000000, - regk_iop_sw_spu_no = 0x00000000, - regk_iop_sw_spu_nop = 0x00000000, - regk_iop_sw_spu_rd = 0x00000002, - regk_iop_sw_spu_reg_copy = 0x00000001, - regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_spu_set = 0x00000001, - regk_iop_sw_spu_wr = 0x00000003, - regk_iop_sw_spu_yes = 0x00000001 -}; -#endif /* __iop_sw_spu_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h deleted file mode 100644 index c994114f3b51..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __iop_timer_grp_defs_h -#define __iop_timer_grp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_timer_grp.r - * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r - * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_timer_grp */ - -/* Register rw_cfg, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int clk_src : 1; - unsigned int trig : 2; - unsigned int clk_gen_div : 8; - unsigned int clk_div : 8; - unsigned int dummy1 : 13; -} reg_iop_timer_grp_rw_cfg; -#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0 -#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0 - -/* Register rw_half_period, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int quota_lo : 15; - unsigned int quota_hi : 15; - unsigned int quota_hi_sel : 1; - unsigned int dummy1 : 1; -} reg_iop_timer_grp_rw_half_period; -#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4 -#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4 - -/* Register rw_half_period_len, scope iop_timer_grp, type rw */ -typedef unsigned int reg_iop_timer_grp_rw_half_period_len; -#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8 -#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8 - -#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 -/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int clk_src : 3; - unsigned int strb : 2; - unsigned int run_mode : 2; - unsigned int out_mode : 1; - unsigned int active_on_tmr : 2; - unsigned int inv : 1; - unsigned int en_by_tmr : 2; - unsigned int dis_by_tmr : 2; - unsigned int en_only_by_reg : 1; - unsigned int dis_only_by_reg : 1; - unsigned int rst_at_en_strb : 1; - unsigned int dummy1 : 14; -} reg_iop_timer_grp_rw_tmr_cfg; -#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12 -#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12 - -#define STRIDE_iop_timer_grp_rw_tmr_len 4 -/* Register rw_tmr_len, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rw_tmr_len; -#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44 -#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44 - -/* Register rw_cmd, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int rst : 4; - unsigned int en : 4; - unsigned int dis : 4; - unsigned int strb : 4; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rw_cmd; -#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60 -#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60 - -/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ -typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt; -#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64 - -#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 -/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rs_tmr_cnt; -#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68 - -#define STRIDE_iop_timer_grp_r_tmr_cnt 8 -/* Register r_tmr_cnt, scope iop_timer_grp, type r */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_r_tmr_cnt; -#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72 - -/* Register rw_intr_mask, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_rw_intr_mask; -#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100 -#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100 - -/* Register rw_ack_intr, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_rw_ack_intr; -#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104 -#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104 - -/* Register r_intr, scope iop_timer_grp, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_r_intr; -#define REG_RD_ADDR_iop_timer_grp_r_intr 108 - -/* Register r_masked_intr, scope iop_timer_grp, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_r_masked_intr; -#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112 - - -/* Constants */ -enum { - regk_iop_timer_grp_clk200 = 0x00000000, - regk_iop_timer_grp_clk_gen = 0x00000002, - regk_iop_timer_grp_complete = 0x00000002, - regk_iop_timer_grp_div_clk200 = 0x00000001, - regk_iop_timer_grp_div_clk_gen = 0x00000003, - regk_iop_timer_grp_ext = 0x00000001, - regk_iop_timer_grp_hi = 0x00000000, - regk_iop_timer_grp_long_period = 0x00000001, - regk_iop_timer_grp_neg = 0x00000002, - regk_iop_timer_grp_no = 0x00000000, - regk_iop_timer_grp_once = 0x00000003, - regk_iop_timer_grp_pause = 0x00000001, - regk_iop_timer_grp_pos = 0x00000001, - regk_iop_timer_grp_pos_neg = 0x00000003, - regk_iop_timer_grp_pulse = 0x00000000, - regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004, - regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004, - regk_iop_timer_grp_rw_cfg_default = 0x00000002, - regk_iop_timer_grp_rw_intr_mask_default = 0x00000000, - regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000, - regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900, - regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200, - regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00, - regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004, - regk_iop_timer_grp_rw_tmr_len_default = 0x00000000, - regk_iop_timer_grp_rw_tmr_len_size = 0x00000004, - regk_iop_timer_grp_short_period = 0x00000000, - regk_iop_timer_grp_stop = 0x00000000, - regk_iop_timer_grp_tmr = 0x00000004, - regk_iop_timer_grp_toggle = 0x00000001, - regk_iop_timer_grp_yes = 0x00000001 -}; -#endif /* __iop_timer_grp_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h deleted file mode 100644 index 36e44282399d..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h +++ /dev/null @@ -1,170 +0,0 @@ -#ifndef __iop_trigger_grp_defs_h -#define __iop_trigger_grp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_trigger_grp */ - -#define STRIDE_iop_trigger_grp_rw_cfg 4 -/* Register rw_cfg, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int action : 2; - unsigned int once : 1; - unsigned int trig : 3; - unsigned int en_only_by_reg : 1; - unsigned int dis_only_by_reg : 1; - unsigned int dummy1 : 24; -} reg_iop_trigger_grp_rw_cfg; -#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0 -#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0 - -/* Register rw_cmd, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int dis : 4; - unsigned int en : 4; - unsigned int dummy1 : 24; -} reg_iop_trigger_grp_rw_cmd; -#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16 -#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16 - -/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_rw_intr_mask; -#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20 -#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20 - -/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_rw_ack_intr; -#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24 -#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24 - -/* Register r_intr, scope iop_trigger_grp, type r */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_r_intr; -#define REG_RD_ADDR_iop_trigger_grp_r_intr 28 - -/* Register r_masked_intr, scope iop_trigger_grp, type r */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_r_masked_intr; -#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32 - - -/* Constants */ -enum { - regk_iop_trigger_grp_fall = 0x00000002, - regk_iop_trigger_grp_fall_lo = 0x00000006, - regk_iop_trigger_grp_no = 0x00000000, - regk_iop_trigger_grp_off = 0x00000000, - regk_iop_trigger_grp_pulse = 0x00000000, - regk_iop_trigger_grp_rise = 0x00000001, - regk_iop_trigger_grp_rise_fall = 0x00000003, - regk_iop_trigger_grp_rise_fall_hi = 0x00000007, - regk_iop_trigger_grp_rise_fall_lo = 0x00000004, - regk_iop_trigger_grp_rise_hi = 0x00000005, - regk_iop_trigger_grp_rw_cfg_default = 0x000000c0, - regk_iop_trigger_grp_rw_cfg_size = 0x00000004, - regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000, - regk_iop_trigger_grp_toggle = 0x00000003, - regk_iop_trigger_grp_yes = 0x00000001 -}; -#endif /* __iop_trigger_grp_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h deleted file mode 100644 index b8d6a910c71c..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h +++ /dev/null @@ -1,99 +0,0 @@ -#ifndef __iop_version_defs_h -#define __iop_version_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_version.r - * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp - * last modfied: Mon Apr 11 16:08:44 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r - * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_version */ - -/* Register r_version, scope iop_version, type r */ -typedef struct { - unsigned int nr : 8; - unsigned int dummy1 : 24; -} reg_iop_version_r_version; -#define REG_RD_ADDR_iop_version_r_version 0 - - -/* Constants */ -enum { - regk_iop_version_v1_0 = 0x00000001 -}; -#endif /* __iop_version_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h deleted file mode 100644 index 7b167e3c0572..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef __irq_nmi_defs_h -#define __irq_nmi_defs_h - -/* - * This file is autogenerated from - * file: ../../mod/irq_nmi.r - * id: - * last modfied: Thu Jan 22 09:22:43 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r - * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope irq_nmi */ - -/* Register rw_cmd, scope irq_nmi, type rw */ -typedef struct { - unsigned int delay : 16; - unsigned int op : 2; - unsigned int dummy1 : 14; -} reg_irq_nmi_rw_cmd; -#define REG_RD_ADDR_irq_nmi_rw_cmd 0 -#define REG_WR_ADDR_irq_nmi_rw_cmd 0 - - -/* Constants */ -enum { - regk_irq_nmi_ack_irq = 0x00000002, - regk_irq_nmi_ack_nmi = 0x00000003, - regk_irq_nmi_irq = 0x00000000, - regk_irq_nmi_nmi = 0x00000001 -}; -#endif /* __irq_nmi_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h deleted file mode 100644 index a11fdd3cd907..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h +++ /dev/null @@ -1,205 +0,0 @@ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Fri Nov 7 15:36:04 2003 - * - * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_break_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_addr; -#define REG_RD_ADDR_marb_bp_r_break_addr 20 - -/* Register r_break_op, scope marb_bp, type r */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_break_op; -#define REG_RD_ADDR_marb_bp_r_break_op 24 - -/* Register r_break_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_clients; -#define REG_RD_ADDR_marb_bp_r_break_clients 28 - -/* Register r_break_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_first_client; -#define REG_RD_ADDR_marb_bp_r_break_first_client 32 - -/* Register r_break_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_size; -#define REG_RD_ADDR_marb_bp_r_break_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/marb_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/marb_defs.h deleted file mode 100644 index 71e8af0bb3a4..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/marb_defs.h +++ /dev/null @@ -1,475 +0,0 @@ -#ifndef __marb_defs_h -#define __marb_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb */ - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_int_slots; -#define REG_RD_ADDR_marb_rw_int_slots 0 -#define REG_WR_ADDR_marb_rw_int_slots 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_ext_slots; -#define REG_RD_ADDR_marb_rw_ext_slots 256 -#define REG_WR_ADDR_marb_rw_ext_slots 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_regs_slots; -#define REG_RD_ADDR_marb_rw_regs_slots 512 -#define REG_WR_ADDR_marb_rw_regs_slots 512 - -/* Register rw_intr_mask, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_intr_mask; -#define REG_RD_ADDR_marb_rw_intr_mask 528 -#define REG_WR_ADDR_marb_rw_intr_mask 528 - -/* Register rw_ack_intr, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_ack_intr; -#define REG_RD_ADDR_marb_rw_ack_intr 532 -#define REG_WR_ADDR_marb_rw_ack_intr 532 - -/* Register r_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_intr; -#define REG_RD_ADDR_marb_r_intr 536 - -/* Register r_masked_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_masked_intr; -#define REG_RD_ADDR_marb_r_masked_intr 540 - -/* Register rw_stop_mask, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_stop_mask; -#define REG_RD_ADDR_marb_rw_stop_mask 544 -#define REG_WR_ADDR_marb_rw_stop_mask 544 - -/* Register r_stopped, scope marb, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_r_stopped; -#define REG_RD_ADDR_marb_r_stopped 548 - -/* Register rw_no_snoop, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_no_snoop; -#define REG_RD_ADDR_marb_rw_no_snoop 832 -#define REG_WR_ADDR_marb_rw_no_snoop 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -typedef struct { - unsigned int dummy1 : 10; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 20; -} reg_marb_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 -#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 - - -/* Constants */ -enum { - regk_marb_cpud = 0x0000000b, - regk_marb_cpui = 0x0000000a, - regk_marb_dma0 = 0x00000000, - regk_marb_dma1 = 0x00000001, - regk_marb_dma2 = 0x00000002, - regk_marb_dma3 = 0x00000003, - regk_marb_dma4 = 0x00000004, - regk_marb_dma5 = 0x00000005, - regk_marb_dma6 = 0x00000006, - regk_marb_dma7 = 0x00000007, - regk_marb_dma8 = 0x00000008, - regk_marb_dma9 = 0x00000009, - regk_marb_iop = 0x0000000c, - regk_marb_no = 0x00000000, - regk_marb_r_stopped_default = 0x00000000, - regk_marb_rw_ext_slots_default = 0x00000000, - regk_marb_rw_ext_slots_size = 0x00000040, - regk_marb_rw_int_slots_default = 0x00000000, - regk_marb_rw_int_slots_size = 0x00000040, - regk_marb_rw_intr_mask_default = 0x00000000, - regk_marb_rw_no_snoop_default = 0x00000000, - regk_marb_rw_no_snoop_rq_default = 0x00000000, - regk_marb_rw_regs_slots_default = 0x00000000, - regk_marb_rw_regs_slots_size = 0x00000004, - regk_marb_rw_stop_mask_default = 0x00000000, - regk_marb_slave = 0x0000000d, - regk_marb_yes = 0x00000001 -}; -#endif /* __marb_defs_h */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_brk_op; -#define REG_RD_ADDR_marb_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_size; -#define REG_RD_ADDR_marb_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/pinmux_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/pinmux_defs.h deleted file mode 100644 index 9d91c2de1b07..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/pinmux_defs.h +++ /dev/null @@ -1,357 +0,0 @@ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int csp2_n : 1; - unsigned int csp3_n : 1; - unsigned int csp5_n : 1; - unsigned int csp6_n : 1; - unsigned int hsh4 : 1; - unsigned int hsh5 : 1; - unsigned int hsh6 : 1; - unsigned int hsh7 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_pa; -#define REG_RD_ADDR_pinmux_rw_pa 0 -#define REG_WR_ADDR_pinmux_rw_pa 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ata0 : 1; - unsigned int ata1 : 1; - unsigned int ata2 : 1; - unsigned int ata3 : 1; - unsigned int ata : 1; - unsigned int eth1 : 1; - unsigned int eth1_mgm : 1; - unsigned int timer : 1; - unsigned int p21 : 1; - unsigned int dummy1 : 18; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 4 -#define REG_WR_ADDR_pinmux_rw_hwprot 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_gio; -#define REG_RD_ADDR_pinmux_rw_pb_gio 8 -#define REG_WR_ADDR_pinmux_rw_pb_gio 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_iop; -#define REG_RD_ADDR_pinmux_rw_pb_iop 12 -#define REG_WR_ADDR_pinmux_rw_pb_iop 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_gio; -#define REG_RD_ADDR_pinmux_rw_pc_gio 16 -#define REG_WR_ADDR_pinmux_rw_pc_gio 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_iop; -#define REG_RD_ADDR_pinmux_rw_pc_iop 20 -#define REG_WR_ADDR_pinmux_rw_pc_iop 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_gio; -#define REG_RD_ADDR_pinmux_rw_pd_gio 24 -#define REG_WR_ADDR_pinmux_rw_pd_gio 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_iop; -#define REG_RD_ADDR_pinmux_rw_pd_iop 28 -#define REG_WR_ADDR_pinmux_rw_pd_iop 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_gio; -#define REG_RD_ADDR_pinmux_rw_pe_gio 32 -#define REG_WR_ADDR_pinmux_rw_pe_gio 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_iop; -#define REG_RD_ADDR_pinmux_rw_pe_iop 36 -#define REG_WR_ADDR_pinmux_rw_pe_iop 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -typedef struct { - unsigned int en_usb0 : 1; - unsigned int en_usb1 : 1; - unsigned int dummy1 : 30; -} reg_pinmux_rw_usb_phy; -#define REG_RD_ADDR_pinmux_rw_usb_phy 40 -#define REG_WR_ADDR_pinmux_rw_usb_phy 40 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_pa_default = 0x00000000, - regk_pinmux_rw_pb_gio_default = 0x00000000, - regk_pinmux_rw_pb_iop_default = 0x00000000, - regk_pinmux_rw_pc_gio_default = 0x00000000, - regk_pinmux_rw_pc_iop_default = 0x00000000, - regk_pinmux_rw_pd_gio_default = 0x00000000, - regk_pinmux_rw_pd_iop_default = 0x00000000, - regk_pinmux_rw_pe_gio_default = 0x00000000, - regk_pinmux_rw_pe_iop_default = 0x00000000, - regk_pinmux_rw_usb_phy_default = 0x00000000, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/reg_map.h b/trunk/include/asm-cris/arch-v32/hwregs/reg_map.h deleted file mode 100644 index e31502838ec6..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/reg_map.h +++ /dev/null @@ -1,103 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -typedef enum { - regi_ata = 0xb0032000, - regi_bif_core = 0xb0014000, - regi_bif_dma = 0xb0016000, - regi_bif_slave = 0xb0018000, - regi_config = 0xb003c000, - regi_dma0 = 0xb0000000, - regi_dma1 = 0xb0002000, - regi_dma2 = 0xb0004000, - regi_dma3 = 0xb0006000, - regi_dma4 = 0xb0008000, - regi_dma5 = 0xb000a000, - regi_dma6 = 0xb000c000, - regi_dma7 = 0xb000e000, - regi_dma8 = 0xb0010000, - regi_dma9 = 0xb0012000, - regi_eth0 = 0xb0034000, - regi_eth1 = 0xb0036000, - regi_gio = 0xb001a000, - regi_iop = 0xb0020000, - regi_iop_version = 0xb0020000, - regi_iop_fifo_in0_extra = 0xb0020040, - regi_iop_fifo_in1_extra = 0xb0020080, - regi_iop_fifo_out0_extra = 0xb00200c0, - regi_iop_fifo_out1_extra = 0xb0020100, - regi_iop_trigger_grp0 = 0xb0020140, - regi_iop_trigger_grp1 = 0xb0020180, - regi_iop_trigger_grp2 = 0xb00201c0, - regi_iop_trigger_grp3 = 0xb0020200, - regi_iop_trigger_grp4 = 0xb0020240, - regi_iop_trigger_grp5 = 0xb0020280, - regi_iop_trigger_grp6 = 0xb00202c0, - regi_iop_trigger_grp7 = 0xb0020300, - regi_iop_crc_par0 = 0xb0020380, - regi_iop_crc_par1 = 0xb0020400, - regi_iop_dmc_in0 = 0xb0020480, - regi_iop_dmc_in1 = 0xb0020500, - regi_iop_dmc_out0 = 0xb0020580, - regi_iop_dmc_out1 = 0xb0020600, - regi_iop_fifo_in0 = 0xb0020680, - regi_iop_fifo_in1 = 0xb0020700, - regi_iop_fifo_out0 = 0xb0020780, - regi_iop_fifo_out1 = 0xb0020800, - regi_iop_scrc_in0 = 0xb0020880, - regi_iop_scrc_in1 = 0xb0020900, - regi_iop_scrc_out0 = 0xb0020980, - regi_iop_scrc_out1 = 0xb0020a00, - regi_iop_timer_grp0 = 0xb0020a80, - regi_iop_timer_grp1 = 0xb0020b00, - regi_iop_timer_grp2 = 0xb0020b80, - regi_iop_timer_grp3 = 0xb0020c00, - regi_iop_sap_in = 0xb0020d00, - regi_iop_sap_out = 0xb0020e00, - regi_iop_spu0 = 0xb0020f00, - regi_iop_spu1 = 0xb0021000, - regi_iop_sw_cfg = 0xb0021100, - regi_iop_sw_cpu = 0xb0021200, - regi_iop_sw_mpu = 0xb0021300, - regi_iop_sw_spu0 = 0xb0021400, - regi_iop_sw_spu1 = 0xb0021500, - regi_iop_mpu = 0xb0021600, - regi_irq = 0xb001c000, - regi_irq2 = 0xb005c000, - regi_marb = 0xb003e000, - regi_marb_bp0 = 0xb003e240, - regi_marb_bp1 = 0xb003e280, - regi_marb_bp2 = 0xb003e2c0, - regi_marb_bp3 = 0xb003e300, - regi_pinmux = 0xb0038000, - regi_ser0 = 0xb0026000, - regi_ser1 = 0xb0028000, - regi_ser2 = 0xb002a000, - regi_ser3 = 0xb002c000, - regi_sser0 = 0xb0022000, - regi_sser1 = 0xb0024000, - regi_strcop = 0xb0030000, - regi_strmux = 0xb003a000, - regi_timer = 0xb001e000, - regi_timer2 = 0xb005e000, - regi_trace = 0xb0040000, -} reg_scope_instances; -#endif /* __reg_map_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/trunk/include/asm-cris/arch-v32/hwregs/reg_rdwr.h deleted file mode 100644 index 44e60233c68f..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/reg_rdwr.h +++ /dev/null @@ -1,15 +0,0 @@ -/* $Id: reg_rdwr.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * - * Read/write register macros used by *_defs.h - */ - -#ifndef reg_rdwr_h -#define reg_rdwr_h - - -#define REG_READ(type, addr) *((volatile type *) (addr)) - -#define REG_WRITE(type, addr, val) \ - do { *((volatile type *) (addr)) = (val); } while(0) - -#endif diff --git a/trunk/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h deleted file mode 100644 index d9f0e924fb23..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h +++ /dev/null @@ -1,173 +0,0 @@ -#ifndef __rt_trace_defs_h -#define __rt_trace_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/rt_trace/rtl/rt_regs.r - * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp - * last modfied: Mon Apr 11 16:09:14 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r - * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope rt_trace */ - -/* Register rw_cfg, scope rt_trace, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int mode : 1; - unsigned int owner : 1; - unsigned int wp : 1; - unsigned int stall : 1; - unsigned int dummy1 : 3; - unsigned int wp_start : 7; - unsigned int dummy2 : 1; - unsigned int wp_stop : 7; - unsigned int dummy3 : 9; -} reg_rt_trace_rw_cfg; -#define REG_RD_ADDR_rt_trace_rw_cfg 0 -#define REG_WR_ADDR_rt_trace_rw_cfg 0 - -/* Register rw_tap_ctrl, scope rt_trace, type rw */ -typedef struct { - unsigned int ack_data : 1; - unsigned int ack_guru : 1; - unsigned int dummy1 : 30; -} reg_rt_trace_rw_tap_ctrl; -#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4 -#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4 - -/* Register r_tap_stat, scope rt_trace, type r */ -typedef struct { - unsigned int dav : 1; - unsigned int empty : 1; - unsigned int dummy1 : 30; -} reg_rt_trace_r_tap_stat; -#define REG_RD_ADDR_rt_trace_r_tap_stat 8 - -/* Register rw_tap_data, scope rt_trace, type rw */ -typedef unsigned int reg_rt_trace_rw_tap_data; -#define REG_RD_ADDR_rt_trace_rw_tap_data 12 -#define REG_WR_ADDR_rt_trace_rw_tap_data 12 - -/* Register rw_tap_hdata, scope rt_trace, type rw */ -typedef struct { - unsigned int op : 4; - unsigned int sub_op : 4; - unsigned int dummy1 : 24; -} reg_rt_trace_rw_tap_hdata; -#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16 -#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16 - -/* Register r_redir, scope rt_trace, type r */ -typedef unsigned int reg_rt_trace_r_redir; -#define REG_RD_ADDR_rt_trace_r_redir 20 - - -/* Constants */ -enum { - regk_rt_trace_brk = 0x0000000c, - regk_rt_trace_dbg = 0x00000003, - regk_rt_trace_dbgdi = 0x00000004, - regk_rt_trace_dbgdo = 0x00000005, - regk_rt_trace_gmode = 0x00000000, - regk_rt_trace_no = 0x00000000, - regk_rt_trace_nop = 0x00000000, - regk_rt_trace_normal = 0x00000000, - regk_rt_trace_rdmem = 0x00000007, - regk_rt_trace_rdmemb = 0x00000009, - regk_rt_trace_rdpreg = 0x00000002, - regk_rt_trace_rdreg = 0x00000001, - regk_rt_trace_rdsreg = 0x00000003, - regk_rt_trace_redir = 0x00000006, - regk_rt_trace_ret = 0x0000000b, - regk_rt_trace_rw_cfg_default = 0x00000000, - regk_rt_trace_trcfg = 0x00000001, - regk_rt_trace_wp = 0x00000001, - regk_rt_trace_wp0 = 0x00000001, - regk_rt_trace_wp1 = 0x00000002, - regk_rt_trace_wp2 = 0x00000004, - regk_rt_trace_wp3 = 0x00000008, - regk_rt_trace_wp4 = 0x00000010, - regk_rt_trace_wp5 = 0x00000020, - regk_rt_trace_wp6 = 0x00000040, - regk_rt_trace_wrmem = 0x00000008, - regk_rt_trace_wrmemb = 0x0000000a, - regk_rt_trace_wrpreg = 0x00000005, - regk_rt_trace_wrreg = 0x00000004, - regk_rt_trace_wrsreg = 0x00000006, - regk_rt_trace_yes = 0x00000001 -}; -#endif /* __rt_trace_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/ser_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/ser_defs.h deleted file mode 100644 index 01c2fab97d43..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/ser_defs.h +++ /dev/null @@ -1,308 +0,0 @@ -#ifndef __ser_defs_h -#define __ser_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ser/rtl/ser_regs.r - * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp - * last modfied: Mon Apr 11 16:09:21 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r - * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ser */ - -/* Register rw_tr_ctrl, scope ser, type rw */ -typedef struct { - unsigned int base_freq : 3; - unsigned int en : 1; - unsigned int par : 2; - unsigned int par_en : 1; - unsigned int data_bits : 1; - unsigned int stop_bits : 1; - unsigned int stop : 1; - unsigned int rts_delay : 3; - unsigned int rts_setup : 1; - unsigned int auto_rts : 1; - unsigned int txd : 1; - unsigned int auto_cts : 1; - unsigned int dummy1 : 15; -} reg_ser_rw_tr_ctrl; -#define REG_RD_ADDR_ser_rw_tr_ctrl 0 -#define REG_WR_ADDR_ser_rw_tr_ctrl 0 - -/* Register rw_tr_dma_en, scope ser, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_tr_dma_en; -#define REG_RD_ADDR_ser_rw_tr_dma_en 4 -#define REG_WR_ADDR_ser_rw_tr_dma_en 4 - -/* Register rw_rec_ctrl, scope ser, type rw */ -typedef struct { - unsigned int base_freq : 3; - unsigned int en : 1; - unsigned int par : 2; - unsigned int par_en : 1; - unsigned int data_bits : 1; - unsigned int dma_mode : 1; - unsigned int dma_err : 1; - unsigned int sampling : 1; - unsigned int timeout : 3; - unsigned int auto_eop : 1; - unsigned int half_duplex : 1; - unsigned int rts_n : 1; - unsigned int loopback : 1; - unsigned int dummy1 : 14; -} reg_ser_rw_rec_ctrl; -#define REG_RD_ADDR_ser_rw_rec_ctrl 8 -#define REG_WR_ADDR_ser_rw_rec_ctrl 8 - -/* Register rw_tr_baud_div, scope ser, type rw */ -typedef struct { - unsigned int div : 16; - unsigned int dummy1 : 16; -} reg_ser_rw_tr_baud_div; -#define REG_RD_ADDR_ser_rw_tr_baud_div 12 -#define REG_WR_ADDR_ser_rw_tr_baud_div 12 - -/* Register rw_rec_baud_div, scope ser, type rw */ -typedef struct { - unsigned int div : 16; - unsigned int dummy1 : 16; -} reg_ser_rw_rec_baud_div; -#define REG_RD_ADDR_ser_rw_rec_baud_div 16 -#define REG_WR_ADDR_ser_rw_rec_baud_div 16 - -/* Register rw_xoff, scope ser, type rw */ -typedef struct { - unsigned int chr : 8; - unsigned int automatic : 1; - unsigned int dummy1 : 23; -} reg_ser_rw_xoff; -#define REG_RD_ADDR_ser_rw_xoff 20 -#define REG_WR_ADDR_ser_rw_xoff 20 - -/* Register rw_xoff_clr, scope ser, type rw */ -typedef struct { - unsigned int clr : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_xoff_clr; -#define REG_RD_ADDR_ser_rw_xoff_clr 24 -#define REG_WR_ADDR_ser_rw_xoff_clr 24 - -/* Register rw_dout, scope ser, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_ser_rw_dout; -#define REG_RD_ADDR_ser_rw_dout 28 -#define REG_WR_ADDR_ser_rw_dout 28 - -/* Register rs_stat_din, scope ser, type rs */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 8; - unsigned int dav : 1; - unsigned int framing_err : 1; - unsigned int par_err : 1; - unsigned int orun : 1; - unsigned int rec_err : 1; - unsigned int rxd : 1; - unsigned int tr_idle : 1; - unsigned int tr_empty : 1; - unsigned int tr_rdy : 1; - unsigned int cts_n : 1; - unsigned int xoff_detect : 1; - unsigned int rts_n : 1; - unsigned int txd : 1; - unsigned int dummy2 : 3; -} reg_ser_rs_stat_din; -#define REG_RD_ADDR_ser_rs_stat_din 32 - -/* Register r_stat_din, scope ser, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 8; - unsigned int dav : 1; - unsigned int framing_err : 1; - unsigned int par_err : 1; - unsigned int orun : 1; - unsigned int rec_err : 1; - unsigned int rxd : 1; - unsigned int tr_idle : 1; - unsigned int tr_empty : 1; - unsigned int tr_rdy : 1; - unsigned int cts_n : 1; - unsigned int xoff_detect : 1; - unsigned int rts_n : 1; - unsigned int txd : 1; - unsigned int dummy2 : 3; -} reg_ser_r_stat_din; -#define REG_RD_ADDR_ser_r_stat_din 36 - -/* Register rw_rec_eop, scope ser, type rw */ -typedef struct { - unsigned int set : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_rec_eop; -#define REG_RD_ADDR_ser_rw_rec_eop 40 -#define REG_WR_ADDR_ser_rw_rec_eop 40 - -/* Register rw_intr_mask, scope ser, type rw */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_rw_intr_mask; -#define REG_RD_ADDR_ser_rw_intr_mask 44 -#define REG_WR_ADDR_ser_rw_intr_mask 44 - -/* Register rw_ack_intr, scope ser, type rw */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_rw_ack_intr; -#define REG_RD_ADDR_ser_rw_ack_intr 48 -#define REG_WR_ADDR_ser_rw_ack_intr 48 - -/* Register r_intr, scope ser, type r */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_r_intr; -#define REG_RD_ADDR_ser_r_intr 52 - -/* Register r_masked_intr, scope ser, type r */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_r_masked_intr; -#define REG_RD_ADDR_ser_r_masked_intr 56 - - -/* Constants */ -enum { - regk_ser_active = 0x00000000, - regk_ser_bits1 = 0x00000000, - regk_ser_bits2 = 0x00000001, - regk_ser_bits7 = 0x00000001, - regk_ser_bits8 = 0x00000000, - regk_ser_del0_5 = 0x00000000, - regk_ser_del1 = 0x00000001, - regk_ser_del1_5 = 0x00000002, - regk_ser_del2 = 0x00000003, - regk_ser_del2_5 = 0x00000004, - regk_ser_del3 = 0x00000005, - regk_ser_del3_5 = 0x00000006, - regk_ser_del4 = 0x00000007, - regk_ser_even = 0x00000000, - regk_ser_ext = 0x00000001, - regk_ser_f100 = 0x00000007, - regk_ser_f29_493 = 0x00000004, - regk_ser_f32 = 0x00000005, - regk_ser_f32_768 = 0x00000006, - regk_ser_ignore = 0x00000001, - regk_ser_inactive = 0x00000001, - regk_ser_majority = 0x00000001, - regk_ser_mark = 0x00000002, - regk_ser_middle = 0x00000000, - regk_ser_no = 0x00000000, - regk_ser_odd = 0x00000001, - regk_ser_off = 0x00000000, - regk_ser_rw_intr_mask_default = 0x00000000, - regk_ser_rw_rec_baud_div_default = 0x00000000, - regk_ser_rw_rec_ctrl_default = 0x00010000, - regk_ser_rw_tr_baud_div_default = 0x00000000, - regk_ser_rw_tr_ctrl_default = 0x00008000, - regk_ser_rw_tr_dma_en_default = 0x00000000, - regk_ser_rw_xoff_default = 0x00000000, - regk_ser_space = 0x00000003, - regk_ser_stop = 0x00000000, - regk_ser_yes = 0x00000001 -}; -#endif /* __ser_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/sser_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/sser_defs.h deleted file mode 100644 index 8d1dab218b91..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/sser_defs.h +++ /dev/null @@ -1,331 +0,0 @@ -#ifndef __sser_defs_h -#define __sser_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/syncser/rtl/sser_regs.r - * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp - * last modfied: Mon Apr 11 16:09:48 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r - * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope sser */ - -/* Register rw_cfg, scope sser, type rw */ -typedef struct { - unsigned int clk_div : 16; - unsigned int base_freq : 3; - unsigned int gate_clk : 1; - unsigned int clkgate_ctrl : 1; - unsigned int clkgate_in : 1; - unsigned int clk_dir : 1; - unsigned int clk_od_mode : 1; - unsigned int out_clk_pol : 1; - unsigned int out_clk_src : 2; - unsigned int clk_in_sel : 1; - unsigned int hold_pol : 1; - unsigned int prepare : 1; - unsigned int en : 1; - unsigned int dummy1 : 1; -} reg_sser_rw_cfg; -#define REG_RD_ADDR_sser_rw_cfg 0 -#define REG_WR_ADDR_sser_rw_cfg 0 - -/* Register rw_frm_cfg, scope sser, type rw */ -typedef struct { - unsigned int wordrate : 10; - unsigned int rec_delay : 3; - unsigned int tr_delay : 3; - unsigned int early_wend : 1; - unsigned int level : 2; - unsigned int type : 1; - unsigned int clk_pol : 1; - unsigned int fr_in_rxclk : 1; - unsigned int clk_src : 1; - unsigned int out_off : 1; - unsigned int out_on : 1; - unsigned int frame_pin_dir : 1; - unsigned int frame_pin_use : 2; - unsigned int status_pin_dir : 1; - unsigned int status_pin_use : 2; - unsigned int dummy1 : 1; -} reg_sser_rw_frm_cfg; -#define REG_RD_ADDR_sser_rw_frm_cfg 4 -#define REG_WR_ADDR_sser_rw_frm_cfg 4 - -/* Register rw_tr_cfg, scope sser, type rw */ -typedef struct { - unsigned int tr_en : 1; - unsigned int stop : 1; - unsigned int urun_stop : 1; - unsigned int eop_stop : 1; - unsigned int sample_size : 6; - unsigned int sh_dir : 1; - unsigned int clk_pol : 1; - unsigned int clk_src : 1; - unsigned int use_dma : 1; - unsigned int mode : 2; - unsigned int frm_src : 1; - unsigned int use60958 : 1; - unsigned int iec60958_ckdiv : 2; - unsigned int rate_ctrl : 1; - unsigned int use_md : 1; - unsigned int dual_i2s : 1; - unsigned int data_pin_use : 2; - unsigned int od_mode : 1; - unsigned int bulk_wspace : 2; - unsigned int dummy1 : 4; -} reg_sser_rw_tr_cfg; -#define REG_RD_ADDR_sser_rw_tr_cfg 8 -#define REG_WR_ADDR_sser_rw_tr_cfg 8 - -/* Register rw_rec_cfg, scope sser, type rw */ -typedef struct { - unsigned int rec_en : 1; - unsigned int force_eop : 1; - unsigned int stop : 1; - unsigned int orun_stop : 1; - unsigned int eop_stop : 1; - unsigned int sample_size : 6; - unsigned int sh_dir : 1; - unsigned int clk_pol : 1; - unsigned int clk_src : 1; - unsigned int use_dma : 1; - unsigned int mode : 2; - unsigned int frm_src : 2; - unsigned int use60958 : 1; - unsigned int iec60958_ui_len : 5; - unsigned int slave2_en : 1; - unsigned int slave3_en : 1; - unsigned int fifo_thr : 2; - unsigned int dummy1 : 3; -} reg_sser_rw_rec_cfg; -#define REG_RD_ADDR_sser_rw_rec_cfg 12 -#define REG_WR_ADDR_sser_rw_rec_cfg 12 - -/* Register rw_tr_data, scope sser, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int md : 1; - unsigned int dummy1 : 15; -} reg_sser_rw_tr_data; -#define REG_RD_ADDR_sser_rw_tr_data 16 -#define REG_WR_ADDR_sser_rw_tr_data 16 - -/* Register r_rec_data, scope sser, type r */ -typedef struct { - unsigned int data : 16; - unsigned int md : 1; - unsigned int ext_clk : 1; - unsigned int status_in : 1; - unsigned int frame_in : 1; - unsigned int din : 1; - unsigned int data_in : 1; - unsigned int clk_in : 1; - unsigned int dummy1 : 9; -} reg_sser_r_rec_data; -#define REG_RD_ADDR_sser_r_rec_data 20 - -/* Register rw_extra, scope sser, type rw */ -typedef struct { - unsigned int clkoff_cycles : 20; - unsigned int clkoff_en : 1; - unsigned int clkon_en : 1; - unsigned int dout_delay : 5; - unsigned int dummy1 : 5; -} reg_sser_rw_extra; -#define REG_RD_ADDR_sser_rw_extra 24 -#define REG_WR_ADDR_sser_rw_extra 24 - -/* Register rw_intr_mask, scope sser, type rw */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_rw_intr_mask; -#define REG_RD_ADDR_sser_rw_intr_mask 28 -#define REG_WR_ADDR_sser_rw_intr_mask 28 - -/* Register rw_ack_intr, scope sser, type rw */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_rw_ack_intr; -#define REG_RD_ADDR_sser_rw_ack_intr 32 -#define REG_WR_ADDR_sser_rw_ack_intr 32 - -/* Register r_intr, scope sser, type r */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_r_intr; -#define REG_RD_ADDR_sser_r_intr 36 - -/* Register r_masked_intr, scope sser, type r */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_r_masked_intr; -#define REG_RD_ADDR_sser_r_masked_intr 40 - - -/* Constants */ -enum { - regk_sser_both = 0x00000002, - regk_sser_bulk = 0x00000001, - regk_sser_clk100 = 0x00000000, - regk_sser_clk_in = 0x00000000, - regk_sser_const0 = 0x00000003, - regk_sser_dout = 0x00000002, - regk_sser_edge = 0x00000000, - regk_sser_ext = 0x00000001, - regk_sser_ext_clk = 0x00000001, - regk_sser_f100 = 0x00000000, - regk_sser_f29_493 = 0x00000004, - regk_sser_f32 = 0x00000005, - regk_sser_f32_768 = 0x00000006, - regk_sser_frm = 0x00000003, - regk_sser_gio0 = 0x00000000, - regk_sser_gio1 = 0x00000001, - regk_sser_hispeed = 0x00000001, - regk_sser_hold = 0x00000002, - regk_sser_in = 0x00000000, - regk_sser_inf = 0x00000003, - regk_sser_intern = 0x00000000, - regk_sser_intern_clk = 0x00000001, - regk_sser_intern_tb = 0x00000000, - regk_sser_iso = 0x00000000, - regk_sser_level = 0x00000001, - regk_sser_lospeed = 0x00000000, - regk_sser_lsbfirst = 0x00000000, - regk_sser_msbfirst = 0x00000001, - regk_sser_neg = 0x00000001, - regk_sser_neg_lo = 0x00000000, - regk_sser_no = 0x00000000, - regk_sser_no_clk = 0x00000007, - regk_sser_nojitter = 0x00000002, - regk_sser_out = 0x00000001, - regk_sser_pos = 0x00000000, - regk_sser_pos_hi = 0x00000001, - regk_sser_rec = 0x00000000, - regk_sser_rw_cfg_default = 0x00000000, - regk_sser_rw_extra_default = 0x00000000, - regk_sser_rw_frm_cfg_default = 0x00000000, - regk_sser_rw_intr_mask_default = 0x00000000, - regk_sser_rw_rec_cfg_default = 0x00000000, - regk_sser_rw_tr_cfg_default = 0x01800000, - regk_sser_rw_tr_data_default = 0x00000000, - regk_sser_thr16 = 0x00000001, - regk_sser_thr32 = 0x00000002, - regk_sser_thr8 = 0x00000000, - regk_sser_tr = 0x00000001, - regk_sser_ts_out = 0x00000003, - regk_sser_tx_bulk = 0x00000002, - regk_sser_wiresave = 0x00000002, - regk_sser_yes = 0x00000001 -}; -#endif /* __sser_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/strcop.h b/trunk/include/asm-cris/arch-v32/hwregs/strcop.h deleted file mode 100644 index 35131ba466f3..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/strcop.h +++ /dev/null @@ -1,57 +0,0 @@ -// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $ - -// Streamcop meta-data configuration structs - -struct strcop_meta_out { - unsigned char csumsel : 3; - unsigned char ciphsel : 3; - unsigned char ciphconf : 2; - unsigned char hashsel : 3; - unsigned char hashconf : 1; - unsigned char hashmode : 1; - unsigned char decrypt : 1; - unsigned char dlkey : 1; - unsigned char cbcmode : 1; -}; - -struct strcop_meta_in { - unsigned char dmasel : 3; - unsigned char sync : 1; - unsigned char res1 : 5; - unsigned char res2; -}; - -// Source definitions - -enum { - src_none = 0, - src_dma = 1, - src_des = 2, - src_sha1 = 3, - src_csum = 4, - src_aes = 5, - src_md5 = 6, - src_res = 7 -}; - -// Cipher definitions - -enum { - ciph_des = 0, - ciph_3des = 1, - ciph_aes = 2 -}; - -// Hash definitions - -enum { - hash_sha1 = 0, - hash_md5 = 1 -}; - -enum { - hash_noiv = 0, - hash_iv = 1 -}; - - diff --git a/trunk/include/asm-cris/arch-v32/hwregs/strcop_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/strcop_defs.h deleted file mode 100644 index bd145a49b2c4..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/strcop_defs.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef __strcop_defs_h -#define __strcop_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strcop/rtl/strcop_regs.r - * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp - * last modfied: Mon Apr 11 16:09:38 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r - * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strcop */ - -/* Register rw_cfg, scope strcop, type rw */ -typedef struct { - unsigned int td3 : 1; - unsigned int td2 : 1; - unsigned int td1 : 1; - unsigned int ipend : 1; - unsigned int ignore_sync : 1; - unsigned int en : 1; - unsigned int dummy1 : 26; -} reg_strcop_rw_cfg; -#define REG_RD_ADDR_strcop_rw_cfg 0 -#define REG_WR_ADDR_strcop_rw_cfg 0 - - -/* Constants */ -enum { - regk_strcop_big = 0x00000001, - regk_strcop_d = 0x00000001, - regk_strcop_e = 0x00000000, - regk_strcop_little = 0x00000000, - regk_strcop_rw_cfg_default = 0x00000002 -}; -#endif /* __strcop_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/strmux_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/strmux_defs.h deleted file mode 100644 index 67474855c499..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/strmux_defs.h +++ /dev/null @@ -1,127 +0,0 @@ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 3; - unsigned int dma1 : 3; - unsigned int dma2 : 3; - unsigned int dma3 : 3; - unsigned int dma4 : 3; - unsigned int dma5 : 3; - unsigned int dma6 : 3; - unsigned int dma7 : 3; - unsigned int dma8 : 3; - unsigned int dma9 : 3; - unsigned int dummy1 : 2; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_ata = 0x00000003, - regk_strmux_eth0 = 0x00000001, - regk_strmux_eth1 = 0x00000004, - regk_strmux_ext0 = 0x00000001, - regk_strmux_ext1 = 0x00000001, - regk_strmux_ext2 = 0x00000001, - regk_strmux_ext3 = 0x00000001, - regk_strmux_iop0 = 0x00000002, - regk_strmux_iop1 = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_p21 = 0x00000004, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000004, - regk_strmux_ser3 = 0x00000003, - regk_strmux_sser0 = 0x00000003, - regk_strmux_sser1 = 0x00000003, - regk_strmux_strcop = 0x00000002 -}; -#endif /* __strmux_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/supp_reg.h b/trunk/include/asm-cris/arch-v32/hwregs/supp_reg.h deleted file mode 100644 index ffe49625ae36..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/supp_reg.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef __SUPP_REG_H__ -#define __SUPP_REG_H__ - -/* Macros for reading and writing support/special registers. */ - -#ifndef STRINGIFYFY -#define STRINGIFYFY(i) #i -#endif - -#ifndef STRINGIFY -#define STRINGIFY(i) STRINGIFYFY(i) -#endif - -#define SPEC_REG_BZ "BZ" -#define SPEC_REG_VR "VR" -#define SPEC_REG_PID "PID" -#define SPEC_REG_SRS "SRS" -#define SPEC_REG_WZ "WZ" -#define SPEC_REG_EXS "EXS" -#define SPEC_REG_EDA "EDA" -#define SPEC_REG_MOF "MOF" -#define SPEC_REG_DZ "DZ" -#define SPEC_REG_EBP "EBP" -#define SPEC_REG_ERP "ERP" -#define SPEC_REG_SRP "SRP" -#define SPEC_REG_NRP "NRP" -#define SPEC_REG_CCS "CCS" -#define SPEC_REG_USP "USP" -#define SPEC_REG_SPC "SPC" - -#define RW_MM_CFG 0 -#define RW_MM_KBASE_LO 1 -#define RW_MM_KBASE_HI 2 -#define RW_MM_CAUSE 3 -#define RW_MM_TLB_SEL 4 -#define RW_MM_TLB_LO 5 -#define RW_MM_TLB_HI 6 -#define RW_MM_TLB_PGD 7 - -#define BANK_GC 0 -#define BANK_IM 1 -#define BANK_DM 2 -#define BANK_BP 3 - -#define RW_GC_CFG 0 -#define RW_GC_CCS 1 -#define RW_GC_SRS 2 -#define RW_GC_NRP 3 -#define RW_GC_EXS 4 -#define RW_GC_R0 8 -#define RW_GC_R1 9 - -#define SPEC_REG_WR(r,v) \ -__asm__ __volatile__ ("move %0, $" r : : "r" (v)); - -#define SPEC_REG_RD(r,v) \ -__asm__ __volatile__ ("move $" r ",%0" : "=r" (v)); - -#define NOP() \ - __asm__ __volatile__ ("nop"); - -#define SUPP_BANK_SEL(b) \ - SPEC_REG_WR(SPEC_REG_SRS,b); \ - NOP(); \ - NOP(); \ - NOP(); - -#define SUPP_REG_WR(r,v) \ -__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - : : "r" (v)); - -#define SUPP_REG_RD(r,v) \ -__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v)); - -#endif /* __SUPP_REG_H__ */ diff --git a/trunk/include/asm-cris/arch-v32/hwregs/timer_defs.h b/trunk/include/asm-cris/arch-v32/hwregs/timer_defs.h deleted file mode 100644 index 20c8c89ec076..000000000000 --- a/trunk/include/asm-cris/arch-v32/hwregs/timer_defs.h +++ /dev/null @@ -1,266 +0,0 @@ -#ifndef __timer_defs_h -#define __timer_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope timer */ - -/* Register rw_tmr0_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr0_div; -#define REG_RD_ADDR_timer_rw_tmr0_div 0 -#define REG_WR_ADDR_timer_rw_tmr0_div 0 - -/* Register r_tmr0_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr0_data; -#define REG_RD_ADDR_timer_r_tmr0_data 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr0_ctrl; -#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 -#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr1_div; -#define REG_RD_ADDR_timer_rw_tmr1_div 16 -#define REG_WR_ADDR_timer_rw_tmr1_div 16 - -/* Register r_tmr1_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr1_data; -#define REG_RD_ADDR_timer_r_tmr1_data 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr1_ctrl; -#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 -#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 - -/* Register rs_cnt_data, scope timer, type rs */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_rs_cnt_data; -#define REG_RD_ADDR_timer_rs_cnt_data 32 - -/* Register r_cnt_data, scope timer, type r */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_r_cnt_data; -#define REG_RD_ADDR_timer_r_cnt_data 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -typedef struct { - unsigned int clk : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_cnt_cfg; -#define REG_RD_ADDR_timer_rw_cnt_cfg 40 -#define REG_WR_ADDR_timer_rw_cnt_cfg 40 - -/* Register rw_trig, scope timer, type rw */ -typedef unsigned int reg_timer_rw_trig; -#define REG_RD_ADDR_timer_rw_trig 48 -#define REG_WR_ADDR_timer_rw_trig 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_trig_cfg; -#define REG_RD_ADDR_timer_rw_trig_cfg 52 -#define REG_WR_ADDR_timer_rw_trig_cfg 52 - -/* Register r_time, scope timer, type r */ -typedef unsigned int reg_timer_r_time; -#define REG_RD_ADDR_timer_r_time 56 - -/* Register rw_out, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_out; -#define REG_RD_ADDR_timer_rw_out 60 -#define REG_WR_ADDR_timer_rw_out 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int key : 7; - unsigned int dummy1 : 16; -} reg_timer_rw_wd_ctrl; -#define REG_RD_ADDR_timer_rw_wd_ctrl 64 -#define REG_WR_ADDR_timer_rw_wd_ctrl 64 - -/* Register r_wd_stat, scope timer, type r */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int dummy1 : 23; -} reg_timer_r_wd_stat; -#define REG_RD_ADDR_timer_r_wd_stat 68 - -/* Register rw_intr_mask, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_intr_mask; -#define REG_RD_ADDR_timer_rw_intr_mask 72 -#define REG_WR_ADDR_timer_rw_intr_mask 72 - -/* Register rw_ack_intr, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_ack_intr; -#define REG_RD_ADDR_timer_rw_ack_intr 76 -#define REG_WR_ADDR_timer_rw_ack_intr 76 - -/* Register r_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_intr; -#define REG_RD_ADDR_timer_r_intr 80 - -/* Register r_masked_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_masked_intr; -#define REG_RD_ADDR_timer_r_masked_intr 84 - -/* Register rw_test, scope timer, type rw */ -typedef struct { - unsigned int dis : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_timer_rw_test; -#define REG_RD_ADDR_timer_rw_test 88 -#define REG_WR_ADDR_timer_rw_test 88 - - -/* Constants */ -enum { - regk_timer_ext = 0x00000001, - regk_timer_f100 = 0x00000007, - regk_timer_f29_493 = 0x00000004, - regk_timer_f32 = 0x00000005, - regk_timer_f32_768 = 0x00000006, - regk_timer_hold = 0x00000001, - regk_timer_ld = 0x00000000, - regk_timer_no = 0x00000000, - regk_timer_off = 0x00000000, - regk_timer_run = 0x00000002, - regk_timer_rw_cnt_cfg_default = 0x00000000, - regk_timer_rw_intr_mask_default = 0x00000000, - regk_timer_rw_out_default = 0x00000000, - regk_timer_rw_test_default = 0x00000000, - regk_timer_rw_tmr0_ctrl_default = 0x00000000, - regk_timer_rw_tmr1_ctrl_default = 0x00000000, - regk_timer_rw_trig_cfg_default = 0x00000000, - regk_timer_start = 0x00000001, - regk_timer_stop = 0x00000000, - regk_timer_time = 0x00000001, - regk_timer_tmr0 = 0x00000002, - regk_timer_tmr1 = 0x00000003, - regk_timer_yes = 0x00000001 -}; -#endif /* __timer_defs_h */ diff --git a/trunk/include/asm-cris/arch-v32/ide.h b/trunk/include/asm-cris/arch-v32/ide.h deleted file mode 100644 index 24f5604f566a..000000000000 --- a/trunk/include/asm-cris/arch-v32/ide.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * linux/include/asm-cris/ide.h - * - * Copyright (C) 2000-2004 Axis Communications AB - * - * Authors: Bjorn Wesen, Mikael Starvik - * - */ - -/* - * This file contains the ETRAX FS specific IDE code. - */ - -#ifndef __ASMCRIS_IDE_H -#define __ASMCRIS_IDE_H - -#ifdef __KERNEL__ - -#include -#include -#include -#include - - -/* ETRAX FS can support 4 IDE busses on the same pins (serialized) */ - -#define MAX_HWIFS 4 - -extern __inline__ int ide_default_irq(unsigned long base) -{ - /* all IDE busses share the same IRQ, - * this has the side-effect that ide-probe.c will cluster our 4 interfaces - * together in a hwgroup, and will serialize accesses. this is good, because - * we can't access more than one interface at the same time on ETRAX100. - */ - return ATA_INTR_VECT; -} - -extern __inline__ unsigned long ide_default_io_base(int index) -{ - reg_ata_rw_ctrl2 ctrl2 = {.sel = index}; - /* we have no real I/O base address per interface, since all go through the - * same register. but in a bitfield in that register, we have the i/f number. - * so we can use the io_base to remember that bitfield. - */ - ctrl2.sel = index; - - return REG_TYPE_CONV(unsigned long, reg_ata_rw_ctrl2, ctrl2); -} - -/* some configuration options we don't need */ - -#undef SUPPORT_VLB_SYNC -#define SUPPORT_VLB_SYNC 0 - -#define IDE_ARCH_ACK_INTR -#define ide_ack_intr(hwif) (hwif)->hw.ack_intr(hwif) - -#endif /* __KERNEL__ */ - -#endif /* __ASMCRIS_IDE_H */ diff --git a/trunk/include/asm-cris/arch-v32/intmem.h b/trunk/include/asm-cris/arch-v32/intmem.h deleted file mode 100644 index c0ada33bf90f..000000000000 --- a/trunk/include/asm-cris/arch-v32/intmem.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_CRIS_INTMEM_H -#define _ASM_CRIS_INTMEM_H - -void* crisv32_intmem_alloc(unsigned size, unsigned align); -void crisv32_intmem_free(void* addr); -void* crisv32_intmem_phys_to_virt(unsigned long addr); -unsigned long crisv32_intmem_virt_to_phys(void *addr); - -#endif /* _ASM_CRIS_ARCH_INTMEM_H */ diff --git a/trunk/include/asm-cris/arch-v32/io.h b/trunk/include/asm-cris/arch-v32/io.h deleted file mode 100644 index 4c80263ec634..000000000000 --- a/trunk/include/asm-cris/arch-v32/io.h +++ /dev/null @@ -1,98 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_IO_H -#define _ASM_ARCH_CRIS_IO_H - -#include -#include -#include -#include - -enum crisv32_io_dir -{ - crisv32_io_dir_in = 0, - crisv32_io_dir_out = 1 -}; - -struct crisv32_ioport -{ - unsigned long* oe; - unsigned long* data; - unsigned long* data_in; - unsigned int pin_count; -}; - -struct crisv32_iopin -{ - struct crisv32_ioport* port; - int bit; -}; - -extern struct crisv32_ioport crisv32_ioports[]; - -extern struct crisv32_iopin crisv32_led1_green; -extern struct crisv32_iopin crisv32_led1_red; -extern struct crisv32_iopin crisv32_led2_green; -extern struct crisv32_iopin crisv32_led2_red; -extern struct crisv32_iopin crisv32_led3_green; -extern struct crisv32_iopin crisv32_led3_red; - -extern inline void crisv32_io_set(struct crisv32_iopin* iopin, - int val) -{ - if (val) - *iopin->port->data |= iopin->bit; - else - *iopin->port->data &= ~iopin->bit; -} - -extern inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, - enum crisv32_io_dir dir) -{ - if (dir == crisv32_io_dir_in) - *iopin->port->oe &= ~iopin->bit; - else - *iopin->port->oe |= iopin->bit; -} - -extern inline int crisv32_io_rd(struct crisv32_iopin* iopin) -{ - return ((*iopin->port->data_in & iopin->bit) ? 1 : 0); -} - -int crisv32_io_get(struct crisv32_iopin* iopin, - unsigned int port, unsigned int pin); -int crisv32_io_get_name(struct crisv32_iopin* iopin, - char* name); - -#define LED_OFF 0x00 -#define LED_GREEN 0x01 -#define LED_RED 0x02 -#define LED_ORANGE (LED_GREEN | LED_RED) - -#define LED_NETWORK_SET(x) \ - do { \ - LED_NETWORK_SET_G((x) & LED_GREEN); \ - LED_NETWORK_SET_R((x) & LED_RED); \ - } while (0) -#define LED_ACTIVE_SET(x) \ - do { \ - LED_ACTIVE_SET_G((x) & LED_GREEN); \ - LED_ACTIVE_SET_R((x) & LED_RED); \ - } while (0) - -#define LED_NETWORK_SET_G(x) \ - crisv32_io_set(&crisv32_led1_green, !(x)); -#define LED_NETWORK_SET_R(x) \ - crisv32_io_set(&crisv32_led1_red, !(x)); -#define LED_ACTIVE_SET_G(x) \ - crisv32_io_set(&crisv32_led2_green, !(x)); -#define LED_ACTIVE_SET_R(x) \ - crisv32_io_set(&crisv32_led2_red, !(x)); -#define LED_DISK_WRITE(x) \ - do{\ - crisv32_io_set(&crisv32_led3_green, !(x)); \ - crisv32_io_set(&crisv32_led3_red, !(x)); \ - }while(0) -#define LED_DISK_READ(x) \ - crisv32_io_set(&crisv32_led3_green, !(x)); - -#endif diff --git a/trunk/include/asm-cris/arch-v32/irq.h b/trunk/include/asm-cris/arch-v32/irq.h deleted file mode 100644 index d35aa8174c2f..000000000000 --- a/trunk/include/asm-cris/arch-v32/irq.h +++ /dev/null @@ -1,120 +0,0 @@ -#ifndef _ASM_ARCH_IRQ_H -#define _ASM_ARCH_IRQ_H - -#include -#include "hwregs/intr_vect.h" - -/* Number of non-cpu interrupts. */ -#define NR_IRQS 0x50 /* Exceptions + IRQs */ -#define NR_REAL_IRQS 0x20 /* IRQs */ -#define FIRST_IRQ 0x31 /* Exception number for first IRQ */ - -#ifndef __ASSEMBLY__ -/* Global IRQ vector. */ -typedef void (*irqvectptr)(void); - -struct etrax_interrupt_vector { - irqvectptr v[256]; -}; - -extern struct etrax_interrupt_vector *etrax_irv; /* head.S */ - -void mask_irq(int irq); -void unmask_irq(int irq); - -void set_exception_vector(int n, irqvectptr addr); - -/* Save registers so that they match pt_regs. */ -#define SAVE_ALL \ - "subq 12,$sp\n\t" \ - "move $erp,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $srp,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $ccs,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $spc,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $mof,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $srs,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move.d $acr,[$sp]\n\t" \ - "subq 14*4,$sp\n\t" \ - "movem $r13,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move.d $r10,[$sp]\n" - -#define STR2(x) #x -#define STR(x) STR2(x) - -#define IRQ_NAME2(nr) nr##_interrupt(void) -#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) - -/* - * The reason for setting the S-bit when debugging the kernel is that we want - * hardware breakpoints to remain active while we are in an exception handler. - * Note that we cannot simply copy S1, since we may come here from user-space, - * or any context where the S-bit wasn't set. - */ -#ifdef CONFIG_ETRAX_KGDB -#define KGDB_FIXUP \ - "move $ccs, $r10\n\t" \ - "or.d (1<<9), $r10\n\t" \ - "move $r10, $ccs\n\t" -#else -#define KGDB_FIXUP "" -#endif - -/* - * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock - * and jump to ret_from_intr which is found in entry.S. - * - * The reason for blocking the IRQ is to allow an sti() before the handler, - * which will acknowledge the interrupt, is run. The actual blocking is made - * by crisv32_do_IRQ. - */ -#define BUILD_IRQ(nr, mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - KGDB_FIXUP \ - "move.d "#nr",$r10\n\t" \ - "move.d $sp,$r12\n\t" \ - "jsr crisv32_do_IRQ\n\t" \ - "moveq 1, $r11\n\t" \ - "jump ret_from_intr\n\t" \ - "nop\n\t"); -/* - * This is subtle. The timer interrupt is crucial and it should not be disabled - * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it - * would have been BLOCK'ed, and then softirq's are run before we return here to - * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run - * and the watchdog will kill us. - * - * Furthermore, if a lot of other irq's occur before we return here, the - * multiple_irq handler is run and it prioritizes the timer interrupt. However - * if we had BLOCK'edit here, we would not get the multiple_irq at all. - * - * The non-blocking here is based on the knowledge that the timer interrupt is - * registred as a fast interrupt (SA_INTERRUPT) so that we _know_ there will not - * be an sti() before the timer irq handler is run to acknowledge the interrupt. - */ -#define BUILD_TIMER_IRQ(nr, mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - KGDB_FIXUP \ - "move.d "#nr",$r10\n\t" \ - "move.d $sp,$r12\n\t" \ - "jsr crisv32_do_IRQ\n\t" \ - "moveq 0,$r11\n\t" \ - "jump ret_from_intr\n\t" \ - "nop\n\t"); - -#endif /* __ASSEMBLY__ */ -#endif /* _ASM_ARCH_IRQ_H */ diff --git a/trunk/include/asm-cris/arch-v32/juliette.h b/trunk/include/asm-cris/arch-v32/juliette.h deleted file mode 100644 index f1f81725e57b..000000000000 --- a/trunk/include/asm-cris/arch-v32/juliette.h +++ /dev/null @@ -1,326 +0,0 @@ -#ifndef _ASM_JULIETTE_H -#define _ASM_JULIETTE_H - -/* juliette _IOC_TYPE, bits 8 to 15 in ioctl cmd */ - -#define JULIOCTYPE 42 - -/* supported ioctl _IOC_NR's */ - -#define JULSTARTDMA 0x1 /* start a picture asynchronously */ - -/* set parameters */ - -#define SETDEFAULT 0x2 /* CCD/VIDEO/SS1M */ -#define SETPARAMETERS 0x3 /* CCD/VIDEO */ -#define SETSIZE 0x4 /* CCD/VIDEO/SS1M */ -#define SETCOMPRESSION 0x5 /* CCD/VIDEO/SS1M */ -#define SETCOLORLEVEL 0x6 /* CCD/VIDEO */ -#define SETBRIGHTNESS 0x7 /* CCD */ -#define SETROTATION 0x8 /* CCD */ -#define SETTEXT 0x9 /* CCD/VIDEO/SS1M */ -#define SETCLOCK 0xa /* CCD/VIDEO/SS1M */ -#define SETDATE 0xb /* CCD/VIDEO/SS1M */ -#define SETTIMEFORMAT 0xc /* CCD/VIDEO/SS1M */ -#define SETDATEFORMAT 0xd /* VIDEO */ -#define SETTEXTALIGNMENT 0xe /* VIDEO */ -#define SETFPS 0xf /* CCD/VIDEO/SS1M */ -#define SETVGA 0xff /* VIDEO */ -#define SETCOMMENT 0xfe /* CCD/VIDEO */ - -/* get parameters */ - -#define GETDRIVERTYPE 0x10 /* CCD/VIDEO/SS1M */ -#define GETNBROFCAMERAS 0x11 /* CCD/VIDEO/SS1M */ -#define GETPARAMETERS 0x12 /* CCD/VIDEO/SS1M */ -#define GETBUFFERSIZE 0x13 /* CCD/VIDEO/SS1M */ -#define GETVIDEOTYPE 0x14 /* VIDEO/SS1M */ -#define GETVIDEOSIGNAL 0x15 /* VIDEO */ -#define GETMODULATION 0x16 /* VIDEO */ -#define GETDCYVALUES 0xa0 /* CCD /SS1M */ -#define GETDCYWIDTH 0xa1 /* CCD /SS1M */ -#define GETDCYHEIGHT 0xa2 /* CCD /SS1M */ -#define GETSIZE 0xa3 /* CCD/VIDEO */ -#define GETCOMPRESSION 0xa4 /* CCD/VIDEO */ - -/* detect and get parameters */ - -#define DETECTMODULATION 0x17 /* VIDEO */ -#define DETECTVIDEOTYPE 0x18 /* VIDEO */ -#define DETECTVIDEOSIGNAL 0x19 /* VIDEO */ - -/* configure default parameters */ - -#define CONFIGUREDEFAULT 0x20 /* CCD/VIDEO/SS1M */ -#define DEFSIZE 0x21 /* CCD/VIDEO/SS1M */ -#define DEFCOMPRESSION 0x22 /* CCD/VIDEO/SS1M */ -#define DEFCOLORLEVEL 0x23 /* CCD/VIDEO */ -#define DEFBRIGHTNESS 0x24 /* CCD */ -#define DEFROTATION 0x25 /* CCD */ -#define DEFWHITEBALANCE 0x26 /* CCD */ -#define DEFEXPOSURE 0x27 /* CCD */ -#define DEFAUTOEXPWINDOW 0x28 /* CCD */ -#define DEFTEXT 0x29 /* CCD/VIDEO/SS1M */ -#define DEFCLOCK 0x2a /* CCD/VIDEO/SS1M */ -#define DEFDATE 0x2b /* CCD/VIDEO/SS1M */ -#define DEFTIMEFORMAT 0x2c /* CCD/VIDEO/SS1M */ -#define DEFDATEFORMAT 0x2d /* VIDEO */ -#define DEFTEXTALIGNMENT 0x2e /* VIDEO */ -#define DEFFPS 0x2f /* CCD/VIDEO/SS1M */ -#define DEFTEXTSTRING 0x30 /* CCD/VIDEO/SS1M */ -#define DEFHEADERINFO 0x31 /* CCD/VIDEO/SS1M */ -#define DEFWEXAR 0x32 /* CCD */ -#define DEFLINEDELAY 0x33 /* CCD */ -#define DEFDISABLEDVIDEO 0x34 /* VIDEO */ -#define DEFVIDEOTYPE 0x35 /* VIDEO */ -#define DEFMODULATION 0x36 /* VIDEO */ -#define DEFXOFFSET 0x37 /* VIDEO */ -#define DEFYOFFSET 0x38 /* VIDEO */ -#define DEFYCMODE 0x39 /* VIDEO */ -#define DEFVCRMODE 0x3a /* VIDEO */ -#define DEFSTOREDCYVALUES 0x3b /* CCD/VIDEO/SS1M */ -#define DEFWCDS 0x3c /* CCD */ -#define DEFVGA 0x3d /* VIDEO */ -#define DEFCOMMENT 0x3e /* CCD/VIDEO */ -#define DEFCOMMENTSIZE 0x3f /* CCD/VIDEO */ -#define DEFCOMMENTTEXT 0x50 /* CCD/VIDEO */ -#define DEFSTOREDCYTEXT 0x51 /* VIDEO */ - - -#define JULABORTDMA 0x70 /* Abort current DMA transfer */ - -/* juliette general i/o port */ - -#define JIO_READBITS 0x40 /* read and return current port bits */ -#define JIO_SETBITS 0x41 /* set bits marked by 1 in the argument */ -#define JIO_CLRBITS 0x42 /* clr bits marked by 1 in the argument */ -#define JIO_READDIR 0x43 /* read direction, 0=input 1=output */ -#define JIO_SETINPUT 0x44 /* set direction, 0=unchanged 1=input - returns current dir */ -#define JIO_SETOUTPUT 0x45 /* set direction, 0=unchanged 1=output - returns current dir */ - -/**** YumYum internal adresses ****/ - -/* Juliette buffer addresses */ - -#define BUFFER1_VIDEO 0x1100 -#define BUFFER2_VIDEO 0x2800 -#define ACDC_BUFF_VIDEO 0x0aaa -#define BUFFER1 0x1700 -#define BUFFER2 0x2b01 -#define ACDC_BUFFER 0x1200 -#define BUFFER1_SS1M 0x1100 -#define BUFFER2_SS1M 0x2800 -#define ACDC_BUFF_SS1M 0x0900 - -/* Juliette parameter memory addresses */ - -#define PA_BUFFER_CNT 0x3f09 /* CCD/VIDEO */ -#define PA_CCD_BUFFER 0x3f10 /* CCD */ -#define PA_VIDEO_BUFFER 0x3f10 /* VIDEO */ -#define PA_DCT_BUFFER 0x3f11 /* CCD/VIDEO */ -#define PA_TEMP 0x3f12 /* CCD/VIDEO */ -#define PA_VIDEOLINE_RD 0x3f13 /* VIDEO */ -#define PA_VIDEOLINE_WR 0x3f14 /* VIDEO */ -#define PA_VI_HDELAY0 0x3f15 /* VIDEO */ -#define PA_VI_VDELAY0 0x3f16 /* VIDEO */ -#define PA_VI_HDELAY1 0x3f17 /* VIDEO */ -#define PA_VI_VDELAY1 0x3f18 /* VIDEO */ -#define PA_VI_HDELAY2 0x3f19 /* VIDEO */ -#define PA_VI_VDELAY2 0x3f1a /* VIDEO */ -#define PA_VI_HDELAY3 0x3f1b /* VIDEO */ -#define PA_VI_VDELAY3 0x3f1c /* VIDEO */ -#define PA_VI_CTRL 0x3f20 /* VIDEO */ -#define PA_JPEG_CTRL 0x3f22 /* CCD/VIDEO */ -#define PA_BUFFER_SIZE 0x3f24 /* CCD/VIDEO */ -#define PA_PAL_NTSC 0x3f25 /* VIDEO */ -#define PA_MACROBLOCKS 0x3f26 /* CCD/VIDEO */ -#define PA_COLOR 0x3f27 /* VIDEO */ -#define PA_MEMCH1CNT2 0x3f28 /* CCD/VIDEO */ -#define PA_MEMCH1CNT3 0x3f29 /* VIDEO */ -#define PA_MEMCH1STR2 0x3f2a /* CCD/VIDEO */ -#define PA_MEMCH1STR3 0x3f2b /* VIDEO */ -#define PA_BUFFERS 0x3f2c /* CCD/VIDEO */ -#define PA_PROGRAM 0x3f2d /* CCD/VIDEO */ -#define PA_ROTATION 0x3f2e /* CCD */ -#define PA_PC 0x3f30 /* CCD/VIDEO */ -#define PA_PC2 0x3f31 /* VIDEO */ -#define PA_ODD_LINE 0x3f32 /* VIDEO */ -#define PA_EXP_DELAY 0x3f34 /* CCD */ -#define PA_MACROBLOCK_CNT 0x3f35 /* CCD/VIDEO */ -#define PA_DRAM_PTR1_L 0x3f36 /* CCD/VIDEO */ -#define PA_CLPOB_CNT 0x3f37 /* CCD */ -#define PA_DRAM_PTR1_H 0x3f38 /* CCD/VIDEO */ -#define PA_DRAM_PTR2_L 0x3f3a /* VIDEO */ -#define PA_DRAM_PTR2_H 0x3f3c /* VIDEO */ -#define PA_CCD_LINE_CNT 0x3f3f /* CCD */ -#define PA_VIDEO_LINE_CNT 0x3f3f /* VIDEO */ -#define PA_TEXT 0x3f41 /* CCD/VIDEO */ -#define PA_CAMERA_CHANGED 0x3f42 /* VIDEO */ -#define PA_TEXTALIGNMENT 0x3f43 /* VIDEO */ -#define PA_DISABLED 0x3f44 /* VIDEO */ -#define PA_MACROBLOCKTEXT 0x3f45 /* VIDEO */ -#define PA_VGA 0x3f46 /* VIDEO */ -#define PA_ZERO 0x3ffe /* VIDEO */ -#define PA_NULL 0x3fff /* CCD/VIDEO */ - -typedef enum { - jpeg = 0, - dummy = 1 -} request_type; - -typedef enum { - hugesize = 0, - fullsize = 1, - halfsize = 2, - fieldsize = 3 -} size_type; - -typedef enum { - min = 0, - low = 1, - medium = 2, - high = 3, - very_high = 4, - very_low = 5, - q1 = 6, - q2 = 7, - q3 = 8, - q4 = 9, - q5 = 10, - q6 = 11 -} compr_type; - -typedef enum { - deg_0 = 0, - deg_180 = 1, - deg_90 = 2, - deg_270 = 3 -} rotation_type; - -typedef enum { - auto_white = 0, - hold = 1, - fixed_outdoor = 2, - fixed_indoor = 3, - fixed_fluor = 4 -} white_balance_type; - -typedef enum { - auto_exp = 0, - fixed_exp = 1 -} exposure_type; - -typedef enum { - no_window = 0, - center = 1, - top = 2, - lower = 3, - left = 4, - right = 5, - spot = 6, - cw = 7 -} exp_window_type; - -typedef enum { - h_24 = 0, - h_12 = 1, - h_24P = 2 -} hour_type; - -typedef enum { - standard = 0, - YYYY_MM_DD = 1, - Www_Mmm_DD_YYYY = 2, - Www_DD_MM_YYYY = 3 -} date_type; - -typedef enum { - left_align = 0, - center_align = 1, - right_align = 2 -} alignment_type; - -typedef enum { - off = 0, - on = 1, - no = 0, - yes = 1 -} enable_type; - -typedef enum { - disabled = 0, - enabled = 1, - extended = 2 -} comment_type; - -typedef enum { - pal = 0, - ntsc = 1 -} video_type; - -typedef enum { - pal_bghi_ntsc_m = 0, - ntsc_4_43_50hz_pal_4_43_60hz = 1, - pal_n_ntsc_4_43_60hz = 2, - ntsc_n_pal_m = 3, - secam_pal_4_43_60hz = 4 -} modulation_type; - -typedef enum { - cam0 = 0, - cam1 = 1, - cam2 = 2, - cam3 = 3, - quad = 32 -} camera_type; - -typedef enum { - video_driver = 0, - ccd_driver = 1 -} driver_type; - -struct jul_param { - request_type req_type; - size_type size; - compr_type compression; - rotation_type rotation; - int color_level; - int brightness; - white_balance_type white_balance; - exposure_type exposure; - exp_window_type auto_exp_window; - hour_type time_format; - date_type date_format; - alignment_type text_alignment; - enable_type text; - enable_type clock; - enable_type date; - enable_type fps; - enable_type vga; - enable_type comment; -}; - -struct video_param { - enable_type disabled; - modulation_type modulation; - video_type video; - enable_type signal; - enable_type vcr; - int xoffset; - int yoffset; -}; - -/* The juliette_request structure is used during the JULSTARTDMA asynchronous - * picture-taking ioctl call as an argument to specify a buffer which will get - * the final picture. - */ - -struct juliette_request { - char *buf; /* Pointer to the buffer to hold picture data */ - unsigned int buflen; /* Length of the above buffer */ - unsigned int size; /* Resulting length, 0 if the picture is not ready */ -}; - -#endif diff --git a/trunk/include/asm-cris/arch-v32/memmap.h b/trunk/include/asm-cris/arch-v32/memmap.h deleted file mode 100644 index d29df5644d3e..000000000000 --- a/trunk/include/asm-cris/arch-v32/memmap.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_INTMEM_START (0x38000000) -#define MEM_INTMEM_SIZE (0x00020000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/trunk/include/asm-cris/arch-v32/mmu.h b/trunk/include/asm-cris/arch-v32/mmu.h deleted file mode 100644 index 6bcdc3fdf7dc..000000000000 --- a/trunk/include/asm-cris/arch-v32/mmu.h +++ /dev/null @@ -1,111 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_MMU_H -#define _ASM_CRIS_ARCH_MMU_H - -/* MMU context type. */ -typedef struct -{ - unsigned int page_id; -} mm_context_t; - -/* Kernel memory segments. */ -#define KSEG_F 0xf0000000UL -#define KSEG_E 0xe0000000UL -#define KSEG_D 0xd0000000UL -#define KSEG_C 0xc0000000UL -#define KSEG_B 0xb0000000UL -#define KSEG_A 0xa0000000UL -#define KSEG_9 0x90000000UL -#define KSEG_8 0x80000000UL -#define KSEG_7 0x70000000UL -#define KSEG_6 0x60000000UL -#define KSEG_5 0x50000000UL -#define KSEG_4 0x40000000UL -#define KSEG_3 0x30000000UL -#define KSEG_2 0x20000000UL -#define KSEG_1 0x10000000UL -#define KSEG_0 0x00000000UL - -/* - * CRISv32 PTE bits: - * - * Bit: 31-13 12-5 4 3 2 1 0 - * +-----+------+--------+-------+--------+-------+---------+ - * | pfn | zero | global | valid | kernel | write | execute | - * +-----+------+--------+-------+--------+-------+---------+ - */ - -/* - * Defines for accessing the bits. Also define some synonyms for use with - * the software-based defined bits below. - */ -#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */ -#define _PAGE_WE (1 << 1) /* Write bit. */ -#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */ -#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */ -#define _PAGE_VALID (1 << 3) /* Page is valid. */ -#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ -#define _PAGE_GLOBAL (1 << 4) /* Global page. */ - -/* - * The hardware doesn't care about these bits, but the kernel uses them in - * software. - */ -#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */ -#define _PAGE_FILE (1 << 6) /* 1=pagecache, 0=swap (when !present) */ -#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */ -#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */ -#define _PAGE_READ (1 << 8) /* Read enabled. */ -#define _PAGE_WRITE (1 << 9) /* Write enabled. */ - -/* Define some higher level generic page attributes. */ -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED) -#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED | _PAGE_EXECUTE) - -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED) - -#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE) -#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \ - _PAGE_PRESENT | __READABLE) - -#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) - -/* CRISv32 can do page protection for execute. - * Write permissions imply read permissions. - * Note that the numbers are in Execute-Write-Read order! - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY_EXEC -#define __P101 PAGE_READONLY_EXEC -#define __P110 PAGE_COPY_EXEC -#define __P111 PAGE_COPY_EXEC - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY_EXEC -#define __S101 PAGE_READONLY_EXEC -#define __S110 PAGE_SHARED_EXEC -#define __S111 PAGE_SHARED_EXEC - -#define PTE_FILE_MAX_BITS 25 - -#endif /* _ASM_CRIS_ARCH_MMU_H */ diff --git a/trunk/include/asm-cris/arch-v32/offset.h b/trunk/include/asm-cris/arch-v32/offset.h deleted file mode 100644 index 597419b033f9..000000000000 --- a/trunk/include/asm-cris/arch-v32/offset.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by arch/cris/Makefile - * - */ - -#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */ -#define PT_r13 56 /* offsetof(struct pt_regs, r13) */ -#define PT_r12 52 /* offsetof(struct pt_regs, r12) */ -#define PT_r11 48 /* offsetof(struct pt_regs, r11) */ -#define PT_r10 44 /* offsetof(struct pt_regs, r10) */ -#define PT_r9 40 /* offsetof(struct pt_regs, r9) */ -#define PT_acr 60 /* offsetof(struct pt_regs, acr) */ -#define PT_srs 64 /* offsetof(struct pt_regs, srs) */ -#define PT_mof 68 /* offsetof(struct pt_regs, mof) */ -#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */ -#define PT_srp 80 /* offsetof(struct pt_regs, srp) */ - -#define TI_task 0 /* offsetof(struct thread_info, task) */ -#define TI_flags 8 /* offsetof(struct thread_info, flags) */ -#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ - -#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ -#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ -#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ - -#define TASK_pid 149 /* offsetof(struct task_struct, pid) */ - -#define LCLONE_VM 256 /* CLONE_VM */ -#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ - -#endif diff --git a/trunk/include/asm-cris/arch-v32/page.h b/trunk/include/asm-cris/arch-v32/page.h deleted file mode 100644 index 77827bc17cca..000000000000 --- a/trunk/include/asm-cris/arch-v32/page.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PAGE_H -#define _ASM_CRIS_ARCH_PAGE_H - -#include - -#ifdef __KERNEL__ - -#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ - -/* - * Macros to convert between physical and virtual addresses. By stripiing a - * selected bit it's possible to convert between KSEG_x and 0x40000000 where the - * DRAM really resides. DRAM is virtually at 0xc. - */ -#ifndef CONFIG_ETRAXFS_SIM -#define __pa(x) ((unsigned long)(x) & 0x7fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) -#else -#define __pa(x) ((unsigned long)(x) & 0x3fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0xc0000000)) -#endif - -#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ - VM_MAYREAD | VM_MAYWRITE) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_CRIS_ARCH_PAGE_H */ diff --git a/trunk/include/asm-cris/arch-v32/pgtable.h b/trunk/include/asm-cris/arch-v32/pgtable.h deleted file mode 100644 index 08cb7ff7e4e7..000000000000 --- a/trunk/include/asm-cris/arch-v32/pgtable.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PGTABLE_H -#define _ASM_CRIS_ARCH_PGTABLE_H - -/* Define the kernels virtual memory area. */ -#define VMALLOC_START KSEG_D -#define VMALLOC_END KSEG_E -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) - -#endif /* _ASM_CRIS_ARCH_PGTABLE_H */ diff --git a/trunk/include/asm-cris/arch-v32/pinmux.h b/trunk/include/asm-cris/arch-v32/pinmux.h deleted file mode 100644 index a66dc9970919..000000000000 --- a/trunk/include/asm-cris/arch-v32/pinmux.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_B 0 -#define PORT_C 1 -#define PORT_D 2 -#define PORT_E 3 - -enum pin_mode -{ - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function -{ - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_sser0, - pinmux_sser1, - pinmux_ata0, - pinmux_ata1, - pinmux_ata2, - pinmux_ata3, - pinmux_ata, - pinmux_eth1, - pinmux_timer -}; - -int crisv32_pinmux_init(void); -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -void crisv32_pinmux_dump(void); - -#endif diff --git a/trunk/include/asm-cris/arch-v32/processor.h b/trunk/include/asm-cris/arch-v32/processor.h deleted file mode 100644 index 8c939bf27987..000000000000 --- a/trunk/include/asm-cris/arch-v32/processor.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PROCESSOR_H -#define _ASM_CRIS_ARCH_PROCESSOR_H - -#include - -/* Return current instruction pointer. */ -#define current_text_addr() \ - ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;}) - -/* - * Since CRIS doesn't do hardware task-switching this hasn't really anything to - * do with the proccessor itself, it's just here for legacy reasons. This is - * used when task-switching using _resume defined in entry.S. The offsets here - * are hardcoded into _resume, so if this struct is changed, entry.S needs to be - * changed as well. - */ -struct thread_struct { - unsigned long ksp; /* Kernel stack pointer. */ - unsigned long usp; /* User stack pointer. */ - unsigned long ccs; /* Saved flags register. */ -}; - -/* - * User-space process size. This is hardcoded into a few places, so don't - * changed it unless everything's clear! - */ -#ifndef CONFIG_ETRAXFS_SIM -#define TASK_SIZE (0xB0000000UL) -#else -#define TASK_SIZE (0xA0000000UL) -#endif - -/* CCS I=1, enable interrupts. */ -#define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) } - -#define KSTK_EIP(tsk) \ -({ \ - unsigned long eip = 0; \ - unsigned long regs = (unsigned long)user_regs(tsk); \ - if (regs > PAGE_SIZE && virt_addr_valid(regs)) \ - eip = ((struct pt_regs *)regs)->erp; \ - eip; \ -}) - -/* - * Give the thread a program location, set user-mode and switch user - * stackpointer. - */ -#define start_thread(regs, ip, usp) \ -do { \ - set_fs(USER_DS); \ - regs->erp = ip; \ - regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \ - wrusp(usp); \ -} while(0) - -/* Nothing special to do for v32 when handling a kernel bus fault fixup. */ -#define arch_fixup(regs) {}; - -#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */ diff --git a/trunk/include/asm-cris/arch-v32/ptrace.h b/trunk/include/asm-cris/arch-v32/ptrace.h deleted file mode 100644 index 516cc7062d94..000000000000 --- a/trunk/include/asm-cris/arch-v32/ptrace.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef _CRIS_ARCH_PTRACE_H -#define _CRIS_ARCH_PTRACE_H - -/* Register numbers in the ptrace system call interface */ - -#define PT_ORIG_R10 0 -#define PT_R0 1 -#define PT_R1 2 -#define PT_R2 3 -#define PT_R3 4 -#define PT_R4 5 -#define PT_R5 6 -#define PT_R6 7 -#define PT_R7 8 -#define PT_R8 9 -#define PT_R9 10 -#define PT_R10 11 -#define PT_R11 12 -#define PT_R12 13 -#define PT_R13 14 -#define PT_ACR 15 -#define PT_SRS 16 -#define PT_MOF 17 -#define PT_SPC 18 -#define PT_CCS 19 -#define PT_SRP 20 -#define PT_ERP 21 /* This is actually the debugged process' PC */ -#define PT_EXS 22 -#define PT_EDA 23 -#define PT_USP 24 /* special case - USP is not in the pt_regs */ -#define PT_PPC 25 /* special case - pseudo PC */ -#define PT_BP 26 /* Base number for BP registers. */ -#define PT_BP_CTRL 26 /* BP control register. */ -#define PT_MAX 40 - -/* Condition code bit numbers. */ -#define C_CCS_BITNR 0 -#define V_CCS_BITNR 1 -#define Z_CCS_BITNR 2 -#define N_CCS_BITNR 3 -#define X_CCS_BITNR 4 -#define I_CCS_BITNR 5 -#define U_CCS_BITNR 6 -#define P_CCS_BITNR 7 -#define R_CCS_BITNR 8 -#define S_CCS_BITNR 9 -#define M_CCS_BITNR 30 -#define Q_CCS_BITNR 31 -#define CCS_SHIFT 10 /* Shift count for each level in CCS */ - -/* pt_regs not only specifices the format in the user-struct during - * ptrace but is also the frame format used in the kernel prologue/epilogues - * themselves - */ - -struct pt_regs { - unsigned long orig_r10; - /* pushed by movem r13, [sp] in SAVE_ALL. */ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long acr; - unsigned long srs; - unsigned long mof; - unsigned long spc; - unsigned long ccs; - unsigned long srp; - unsigned long erp; /* This is actually the debugged process' PC */ - /* For debugging purposes; saved only when needed. */ - unsigned long exs; - unsigned long eda; -}; - -/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) - * when doing a context-switch. it is used (apart from in resume) when a new - * thread is made and we need to make _resume (which is starting it for the - * first time) realise what is going on. - * - * Actually, the use is very close to the thread struct (TSS) in that both the - * switch_stack and the TSS are used to keep thread stuff when switching in - * _resume. - */ - -struct switch_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long return_ip; /* ip that _resume will return to */ -}; - -#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0) -#define instruction_pointer(regs) ((regs)->erp) -extern void show_regs(struct pt_regs *); -#define profile_pc(regs) instruction_pointer(regs) - -#endif diff --git a/trunk/include/asm-cris/arch-v32/spinlock.h b/trunk/include/asm-cris/arch-v32/spinlock.h deleted file mode 100644 index 52df72a62232..000000000000 --- a/trunk/include/asm-cris/arch-v32/spinlock.h +++ /dev/null @@ -1,163 +0,0 @@ -#ifndef __ASM_ARCH_SPINLOCK_H -#define __ASM_ARCH_SPINLOCK_H - -#include - -#define RW_LOCK_BIAS 0x01000000 -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } -#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0) - -#define spin_is_locked(x) (*(volatile signed char *)(&(x)->lock) <= 0) -#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) - -extern void cris_spin_unlock(void *l, int val); -extern void cris_spin_lock(void *l); -extern int cris_spin_trylock(void* l); - -static inline void _raw_spin_unlock(spinlock_t *lock) -{ - __asm__ volatile ("move.d %1,%0" \ - : "=m" (lock->lock) \ - : "r" (1) \ - : "memory"); -} - -static inline int _raw_spin_trylock(spinlock_t *lock) -{ - return cris_spin_trylock((void*)&lock->lock); -} - -static inline void _raw_spin_lock(spinlock_t *lock) -{ - cris_spin_lock((void*)&lock->lock); -} - -static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags) -{ - _raw_spin_lock(lock); -} - -/* - * Read-write spinlocks, allowing multiple readers - * but only one writer. - * - * NOTE! it is quite common to have readers in interrupts - * but no interrupt writers. For those circumstances we - * can "mix" irq-safe locks - any writer needs to get a - * irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - */ -typedef struct { - spinlock_t lock; - volatile int counter; -#ifdef CONFIG_PREEMPT - unsigned int break_lock; -#endif -} rwlock_t; - -#define RW_LOCK_UNLOCKED (rwlock_t) { {1}, 0 } - -#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while (0) - -/** - * read_can_lock - would read_trylock() succeed? - * @lock: the rwlock in question. - */ -#define read_can_lock(x) ((int)(x)->counter >= 0) - -/** - * write_can_lock - would write_trylock() succeed? - * @lock: the rwlock in question. - */ -#define write_can_lock(x) ((x)->counter == 0) - -#define _raw_read_trylock(lock) generic_raw_read_trylock(lock) - -/* read_lock, read_unlock are pretty straightforward. Of course it somehow - * sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */ - -static __inline__ void _raw_read_lock(rwlock_t *rw) -{ - unsigned long flags; - local_irq_save(flags); - _raw_spin_lock(&rw->lock); - - rw->counter++; - - _raw_spin_unlock(&rw->lock); - local_irq_restore(flags); -} - -static __inline__ void _raw_read_unlock(rwlock_t *rw) -{ - unsigned long flags; - local_irq_save(flags); - _raw_spin_lock(&rw->lock); - - rw->counter--; - - _raw_spin_unlock(&rw->lock); - local_irq_restore(flags); -} - -/* write_lock is less trivial. We optimistically grab the lock and check - * if we surprised any readers. If so we release the lock and wait till - * they're all gone before trying again - * - * Also note that we don't use the _irqsave / _irqrestore suffixes here. - * If we're called with interrupts enabled and we've got readers (or other - * writers) in interrupt handlers someone fucked up and we'd dead-lock - * sooner or later anyway. prumpf */ - -static __inline__ void _raw_write_lock(rwlock_t *rw) -{ -retry: - _raw_spin_lock(&rw->lock); - - if(rw->counter != 0) { - /* this basically never happens */ - _raw_spin_unlock(&rw->lock); - - while(rw->counter != 0); - - goto retry; - } - - /* got it. now leave without unlocking */ - rw->counter = -1; /* remember we are locked */ -} - -/* write_unlock is absolutely trivial - we don't have to wait for anything */ - -static __inline__ void _raw_write_unlock(rwlock_t *rw) -{ - rw->counter = 0; - _raw_spin_unlock(&rw->lock); -} - -static __inline__ int _raw_write_trylock(rwlock_t *rw) -{ - _raw_spin_lock(&rw->lock); - if (rw->counter != 0) { - /* this basically never happens */ - _raw_spin_unlock(&rw->lock); - - return 0; - } - - /* got it. now leave without unlocking */ - rw->counter = -1; /* remember we are locked */ - return 1; -} - -static __inline__ int is_read_locked(rwlock_t *rw) -{ - return rw->counter > 0; -} - -static __inline__ int is_write_locked(rwlock_t *rw) -{ - return rw->counter < 0; -} - -#endif /* __ASM_ARCH_SPINLOCK_H */ diff --git a/trunk/include/asm-cris/arch-v32/system.h b/trunk/include/asm-cris/arch-v32/system.h deleted file mode 100644 index b9afbb95e0bb..000000000000 --- a/trunk/include/asm-cris/arch-v32/system.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_SYSTEM_H -#define _ASM_CRIS_ARCH_SYSTEM_H - -#include - -/* Read the CPU version register. */ -extern inline unsigned long rdvr(void) -{ - unsigned char vr; - - __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr)); - return vr; -} - -#define cris_machine_name "crisv32" - -/* Read the user-mode stack pointer. */ -extern inline unsigned long rdusp(void) -{ - unsigned long usp; - - __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp)); - return usp; -} - -/* Read the current stack pointer. */ -extern inline unsigned long rdsp(void) -{ - unsigned long sp; - - __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp)); - return sp; -} - -/* Write the user-mode stack pointer. */ -#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp)) - -#define nop() __asm__ __volatile__ ("nop"); - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr)))) - -#define tas(ptr) (xchg((ptr),1)) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((struct __xchg_dummy *)(x)) - -/* Used for interrupt control. */ -#define local_save_flags(x) \ - __asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory"); - -#define local_irq_restore(x) \ - __asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory"); - -#define local_irq_disable() __asm__ __volatile__ ("di" : : : "memory"); -#define local_irq_enable() __asm__ __volatile__ ("ei" : : : "memory"); - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - \ - local_save_flags(flags);\ - !(flags & (1 << I_CCS_BITNR)); \ -}) - -/* Used for spinlocks, etc. */ -#define local_irq_save(x) \ - __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); - -#ifdef CONFIG_SMP -typedef struct { - volatile unsigned int lock __attribute__ ((aligned(4))); -#ifdef CONFIG_PREEMPT - unsigned int break_lock; -#endif -} spinlock_t; -#endif - -#endif /* _ASM_CRIS_ARCH_SYSTEM_H */ diff --git a/trunk/include/asm-cris/arch-v32/thread_info.h b/trunk/include/asm-cris/arch-v32/thread_info.h deleted file mode 100644 index a7a182307da0..000000000000 --- a/trunk/include/asm-cris/arch-v32/thread_info.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H -#define _ASM_CRIS_ARCH_THREAD_INFO_H - -/* Return a thread_info struct. */ -extern inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - - __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL)); - return ti; -} - -#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */ diff --git a/trunk/include/asm-cris/arch-v32/timex.h b/trunk/include/asm-cris/arch-v32/timex.h deleted file mode 100644 index 4d0fd23b21e9..000000000000 --- a/trunk/include/asm-cris/arch-v32/timex.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_TIMEX_H -#define _ASM_CRIS_ARCH_TIMEX_H - -#include -#include -#include - -/* - * The clock runs at 100MHz, we divide it by 1000000. If you change anything - * here you must check time.c as well. - */ - -#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */ - -/* The timer0 values gives 10 ns resolution but interrupts at HZ. */ -#define TIMER0_FREQ (CLOCK_TICK_RATE) -#define TIMER0_DIV (TIMER0_FREQ/(HZ)) - -/* Convert the value in step of 10 ns to 1us without overflow: */ -#define GET_JIFFIES_USEC() \ - ( (TIMER0_DIV - REG_RD(timer, regi_timer, r_tmr0_data)) /100 ) - -extern unsigned long get_ns_in_jiffie(void); - -extern inline unsigned long get_us_in_jiffie_highres(void) -{ - return get_ns_in_jiffie() / 1000; -} - -#endif - diff --git a/trunk/include/asm-cris/arch-v32/tlb.h b/trunk/include/asm-cris/arch-v32/tlb.h deleted file mode 100644 index 4effb1253660..000000000000 --- a/trunk/include/asm-cris/arch-v32/tlb.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _CRIS_ARCH_TLB_H -#define _CRIS_ARCH_TLB_H - -/* - * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used - * to store the "process" it belongs to (=> fast mm context switch). The - * last page_id is never used so we can make TLB entries that never matches. - */ -#define NUM_TLB_ENTRIES 64 -#define NUM_PAGEID 256 -#define INVALID_PAGEID 255 -#define NO_CONTEXT -1 - -#endif /* _CRIS_ARCH_TLB_H */ diff --git a/trunk/include/asm-cris/arch-v32/uaccess.h b/trunk/include/asm-cris/arch-v32/uaccess.h deleted file mode 100644 index 055a0bdbe835..000000000000 --- a/trunk/include/asm-cris/arch-v32/uaccess.h +++ /dev/null @@ -1,748 +0,0 @@ -/* - * Authors: Hans-Peter Nilsson (hp@axis.com) - * - */ -#ifndef _CRIS_ARCH_UACCESS_H -#define _CRIS_ARCH_UACCESS_H - -/* - * We don't tell gcc that we are accessing memory, but this is OK - * because we do not write to any memory gcc knows about, so there - * are no aliasing issues. - * - * Note that PC at a fault is the address *at* the faulting - * instruction for CRISv32. - */ -#define __put_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - "2: "op" %1,[%2]\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " nop\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __put_user_asm_64(x, addr, err) do { \ - int dummy_for_put_user_asm_64_; \ - __asm__ __volatile__( \ - "2: move.d %M2,[%1+]\n" \ - "4: move.d %H2,[%1]\n" \ - "5:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %4,%0\n" \ - " jump 5b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \ - : "r" (x), "1" (addr), "g" (-EFAULT), \ - "0" (err)); \ - } while (0) - -/* See comment before __put_user_asm. */ - -#define __get_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - "2: "op" [%2],%1\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " moveq 0,%1\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __get_user_asm_64(x, addr, err) do { \ - int dummy_for_get_user_asm_64_; \ - __asm__ __volatile__( \ - "2: move.d [%2+],%M1\n" \ - "4: move.d [%2],%H1\n" \ - "5:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %4,%0\n" \ - " jump 5b\n" \ - " moveq 0,%1\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x), \ - "=b" (dummy_for_get_user_asm_64_) \ - : "2" (addr), "g" (-EFAULT), "0" (err));\ - } while (0) - -/* - * Copy a null terminated string from userspace. - * - * Must return: - * -EFAULT for an exception - * count if we hit the buffer limit - * bytes copied if we hit a null byte - * (without the null byte) - */ -extern inline long -__do_strncpy_from_user(char *dst, const char *src, long count) -{ - long res; - - if (count == 0) - return 0; - - /* - * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. - * So do we. - * - * This code is deduced from: - * - * char tmp2; - * long tmp1, tmp3; - * tmp1 = count; - * while ((*dst++ = (tmp2 = *src++)) != 0 - * && --tmp1) - * ; - * - * res = count - tmp1; - * - * with tweaks. - */ - - __asm__ __volatile__ ( - " move.d %3,%0\n" - "5: move.b [%2+],$acr\n" - "1: beq 2f\n" - " move.b $acr,[%1+]\n" - - " subq 1,%0\n" - "2: bne 1b\n" - " move.b [%2+],$acr\n" - - " sub.d %3,%0\n" - " neg.d %0,%0\n" - "3:\n" - " .section .fixup,\"ax\"\n" - "4: move.d %7,%0\n" - " jump 3b\n" - " nop\n" - - /* The address for a fault at the first move is trivial. - The address for a fault at the second move is that of - the preceding branch insn, since the move insn is in - its delay-slot. That address is also a branch - target. Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 5b,4b\n" - " .dword 2b,4b\n" - " .previous" - : "=r" (res), "=b" (dst), "=b" (src), "=r" (count) - : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) - : "acr"); - - return res; -} - -/* A few copy asms to build up the more complex ones from. - - Note again, a post-increment is performed regardless of whether a bus - fault occurred in that instruction, and PC for a faulted insn is the - address for the insn, or for the preceding branch when in a delay-slot. */ - -#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - COPY \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous\n" \ - : "=b" (to), "=b" (from), "=r" (ret) \ - : "0" (to), "1" (from), "2" (ret) \ - : "acr", "memory") - -#define __asm_copy_from_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - "2: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "3: addq 1,%2\n" \ - " jump 1b\n" \ - " clear.b [%0+]\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - "2: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "3: addq 2,%2\n" \ - " jump 1b\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_3(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, \ - "4: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - "2: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "3: addq 4,%2\n" \ - " jump 1b\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_4(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_5(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - "4: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - COPY \ - "4: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "5: addq 2,%2\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_7(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, \ - "6: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - COPY \ - "4: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "5: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_8(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_9(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - "6: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - COPY \ - "6: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "7: addq 2,%2\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_11(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, \ - "8: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - COPY \ - "6: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "7: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_12(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_13(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - "8: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - COPY \ - "8: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "9: addq 2,%2\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_15(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, \ - "10: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "11: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - COPY \ - "8: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "9: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_16(to, from, ret) \ - __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_16x_cont(to, from, ret, \ - COPY \ - "10: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "11: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_20(to, from, ret) \ - __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_20x_cont(to, from, ret, \ - COPY \ - "12: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "13: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_copy_from_user_24(to, from, ret) \ - __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") - -/* And now, the to-user ones. */ - -#define __asm_copy_to_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "2: move.b $acr,[%0+]\n", \ - "3: jump 1b\n" \ - " addq 1,%2\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "2: move.w $acr,[%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 2,%2\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_3(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "4: move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "2: move.d $acr,[%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 4,%2\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_4(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_5(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "4: move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "4: move.w $acr,[%0+]\n", \ - FIXUP \ - "5: addq 2,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_7(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "6: move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "4: move.d $acr,[%0+]\n", \ - FIXUP \ - "5: addq 4,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_8(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_9(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "6: move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "6: move.w $acr,[%0+]\n", \ - FIXUP \ - "7: addq 2,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_11(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "8: move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "6: move.d $acr,[%0+]\n", \ - FIXUP \ - "7: addq 4,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_12(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_13(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "8: move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "8: move.w $acr,[%0+]\n", \ - FIXUP \ - "9: addq 2,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_15(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "10: move.b $acr,[%0+]\n", \ - "11: addq 1,%2\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "8: move.d $acr,[%0+]\n", \ - FIXUP \ - "9: addq 4,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_16(to, from, ret) \ - __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_16x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "10: move.d $acr,[%0+]\n", \ - FIXUP \ - "11: addq 4,%2\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_20(to, from, ret) \ - __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_20x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "12: move.d $acr,[%0+]\n", \ - FIXUP \ - "13: addq 4,%2\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_copy_to_user_24(to, from, ret) \ - __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") - -/* Define a few clearing asms with exception handlers. */ - -/* This frame-asm is like the __asm_copy_user_cont one, but has one less - input. */ - -#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - CLEAR \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous" \ - : "=b" (to), "=r" (ret) \ - : "0" (to), "1" (ret) \ - : "memory") - -#define __asm_clear_1(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.b [%0+]\n", \ - "3: jump 1b\n" \ - " addq 1,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_2(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.w [%0+]\n", \ - "3: jump 1b\n" \ - " addq 2,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_3(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.w [%0+]\n" \ - "3: clear.b [%0+]\n", \ - "4: addq 2,%1\n" \ - "5: jump 1b\n" \ - " addq 1,%1\n", \ - " .dword 2b,4b\n" \ - " .dword 3b,5b\n") - -#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear(to, ret, \ - CLEAR \ - "2: clear.d [%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 4,%1\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_clear_4(to, ret) \ - __asm_clear_4x_cont(to, ret, "", "", "") - -#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_4x_cont(to, ret, \ - CLEAR \ - "4: clear.d [%0+]\n", \ - FIXUP \ - "5: addq 4,%1\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_clear_8(to, ret) \ - __asm_clear_8x_cont(to, ret, "", "", "") - -#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_8x_cont(to, ret, \ - CLEAR \ - "6: clear.d [%0+]\n", \ - FIXUP \ - "7: addq 4,%1\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_clear_12(to, ret) \ - __asm_clear_12x_cont(to, ret, "", "", "") - -#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_12x_cont(to, ret, \ - CLEAR \ - "8: clear.d [%0+]\n", \ - FIXUP \ - "9: addq 4,%1\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_clear_16(to, ret) \ - __asm_clear_16x_cont(to, ret, "", "", "") - -#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_16x_cont(to, ret, \ - CLEAR \ - "10: clear.d [%0+]\n", \ - FIXUP \ - "11: addq 4,%1\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_clear_20(to, ret) \ - __asm_clear_20x_cont(to, ret, "", "", "") - -#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_20x_cont(to, ret, \ - CLEAR \ - "12: clear.d [%0+]\n", \ - FIXUP \ - "13: addq 4,%1\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_clear_24(to, ret) \ - __asm_clear_24x_cont(to, ret, "", "", "") - -/* - * Return the size of a string (including the ending 0) - * - * Return length of string in userspace including terminating 0 - * or 0 for error. Return a value greater than N if too long. - */ - -extern inline long -strnlen_user(const char *s, long n) -{ - long res, tmp1; - - if (!access_ok(VERIFY_READ, s, 0)) - return 0; - - /* - * This code is deduced from: - * - * tmp1 = n; - * while (tmp1-- > 0 && *s++) - * ; - * - * res = n - tmp1; - * - * (with tweaks). - */ - - __asm__ __volatile__ ( - " move.d %1,$acr\n" - " cmpq 0,$acr\n" - "0:\n" - " ble 1f\n" - " subq 1,$acr\n" - - "4: test.b [%0+]\n" - " bne 0b\n" - " cmpq 0,$acr\n" - "1:\n" - " move.d %1,%0\n" - " sub.d $acr,%0\n" - "2:\n" - " .section .fixup,\"ax\"\n" - - "3: jump 2b\n" - " clear.d %0\n" - - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 4b,3b\n" - " .previous\n" - : "=r" (res), "=r" (tmp1) - : "0" (s), "1" (n) - : "acr"); - - return res; -} - -#endif diff --git a/trunk/include/asm-cris/arch-v32/unistd.h b/trunk/include/asm-cris/arch-v32/unistd.h deleted file mode 100644 index 5d369d4439d9..000000000000 --- a/trunk/include/asm-cris/arch-v32/unistd.h +++ /dev/null @@ -1,148 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_UNISTD_H_ -#define _ASM_CRIS_ARCH_UNISTD_H_ - -/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ -/* - * Don't remove the .ifnc tests; they are an insurance against - * any hard-to-spot gcc register allocation bugs. - */ -#define _syscall0(type,name) \ -type name(void) \ -{ \ - register long __a __asm__ ("r10"); \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall1(type,name,type1,arg1) \ -type name(type1 arg1) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall2(type,name,type1,arg1,type2,arg2) \ -type name(type1 arg1,type2 arg2) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ -type name(type1 arg1,type2 arg2,type3 arg3) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ -type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __e __asm__ ("mof") = (long) arg5; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5,type6,arg6) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __e __asm__ ("mof") = (long) arg5; \ - register long __f __asm__ ("srp") = (long) arg6; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e), "x" (__f)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#endif diff --git a/trunk/include/asm-cris/arch-v32/user.h b/trunk/include/asm-cris/arch-v32/user.h deleted file mode 100644 index 03fa1f3c3c00..000000000000 --- a/trunk/include/asm-cris/arch-v32/user.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_USER_H -#define _ASM_CRIS_ARCH_USER_H - -/* User-mode register used for core dumps. */ - -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* R14, Stack pointer. */ - unsigned long acr; /* R15, Address calculation register. */ - unsigned long bz; /* P0, Constant zero (8-bits). */ - unsigned long vr; /* P1, Version register (8-bits). */ - unsigned long pid; /* P2, Process ID (8-bits). */ - unsigned long srs; /* P3, Support register select (8-bits). */ - unsigned long wz; /* P4, Constant zero (16-bits). */ - unsigned long exs; /* P5, Exception status. */ - unsigned long eda; /* P6, Exception data address. */ - unsigned long mof; /* P7, Multiply overflow regiter. */ - unsigned long dz; /* P8, Constant zero (32-bits). */ - unsigned long ebp; /* P9, Exception base pointer. */ - unsigned long erp; /* P10, Exception return pointer. */ - unsigned long srp; /* P11, Subroutine return pointer. */ - unsigned long nrp; /* P12, NMI return pointer. */ - unsigned long ccs; /* P13, Condition code stack. */ - unsigned long usp; /* P14, User mode stack pointer. */ - unsigned long spc; /* P15, Single step PC. */ -}; - -#endif /* _ASM_CRIS_ARCH_USER_H */ diff --git a/trunk/include/asm-cris/atomic.h b/trunk/include/asm-cris/atomic.h index 70605b09e8b7..b3dfea5a71e4 100644 --- a/trunk/include/asm-cris/atomic.h +++ b/trunk/include/asm-cris/atomic.h @@ -4,14 +4,21 @@ #define __ASM_CRIS_ATOMIC__ #include -#include /* * Atomic operations that C can't guarantee us. Useful for * resource counting etc.. */ -typedef struct { volatile int counter; } atomic_t; +/* + * Make sure gcc doesn't try to be clever and move things around + * on us. We need to use _exactly_ the address the user gave us, + * not some alias that contains the same information. + */ + +#define __atomic_fool_gcc(x) (*(struct { int a[100]; } *)x) + +typedef struct { int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } @@ -23,26 +30,29 @@ typedef struct { volatile int counter; } atomic_t; extern __inline__ void atomic_add(int i, volatile atomic_t *v) { unsigned long flags; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); v->counter += i; - cris_atomic_restore(v, flags); + local_irq_restore(flags); } extern __inline__ void atomic_sub(int i, volatile atomic_t *v) { unsigned long flags; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); v->counter -= i; - cris_atomic_restore(v, flags); + local_irq_restore(flags); } extern __inline__ int atomic_add_return(int i, volatile atomic_t *v) { unsigned long flags; int retval; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); retval = (v->counter += i); - cris_atomic_restore(v, flags); + local_irq_restore(flags); return retval; } @@ -52,9 +62,10 @@ extern __inline__ int atomic_sub_return(int i, volatile atomic_t *v) { unsigned long flags; int retval; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); retval = (v->counter -= i); - cris_atomic_restore(v, flags); + local_irq_restore(flags); return retval; } @@ -62,35 +73,39 @@ extern __inline__ int atomic_sub_and_test(int i, volatile atomic_t *v) { int retval; unsigned long flags; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); retval = (v->counter -= i) == 0; - cris_atomic_restore(v, flags); + local_irq_restore(flags); return retval; } extern __inline__ void atomic_inc(volatile atomic_t *v) { unsigned long flags; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); (v->counter)++; - cris_atomic_restore(v, flags); + local_irq_restore(flags); } extern __inline__ void atomic_dec(volatile atomic_t *v) { unsigned long flags; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); (v->counter)--; - cris_atomic_restore(v, flags); + local_irq_restore(flags); } extern __inline__ int atomic_inc_return(volatile atomic_t *v) { unsigned long flags; int retval; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); retval = (v->counter)++; - cris_atomic_restore(v, flags); + local_irq_restore(flags); return retval; } @@ -98,18 +113,20 @@ extern __inline__ int atomic_dec_return(volatile atomic_t *v) { unsigned long flags; int retval; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); retval = (v->counter)--; - cris_atomic_restore(v, flags); + local_irq_restore(flags); return retval; } extern __inline__ int atomic_dec_and_test(volatile atomic_t *v) { int retval; unsigned long flags; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); retval = --(v->counter) == 0; - cris_atomic_restore(v, flags); + local_irq_restore(flags); return retval; } @@ -117,9 +134,10 @@ extern __inline__ int atomic_inc_and_test(volatile atomic_t *v) { int retval; unsigned long flags; - cris_atomic_save(v, flags); + local_save_flags(flags); + local_irq_disable(); retval = ++(v->counter) == 0; - cris_atomic_restore(v, flags); + local_irq_restore(flags); return retval; } diff --git a/trunk/include/asm-cris/axisflashmap.h b/trunk/include/asm-cris/axisflashmap.h index 7a8d3114e682..600bb8715d89 100644 --- a/trunk/include/asm-cris/axisflashmap.h +++ b/trunk/include/asm-cris/axisflashmap.h @@ -40,7 +40,4 @@ struct partitiontable_entry { #define PARTITION_TYPE_KERNEL 0x0002 #define PARTITION_TYPE_JFFS 0x0003 -/* The master mtd for the entire flash. */ -extern struct mtd_info* axisflash_mtd; - #endif diff --git a/trunk/include/asm-cris/bitops.h b/trunk/include/asm-cris/bitops.h index e3da57f97964..d7861115d731 100644 --- a/trunk/include/asm-cris/bitops.h +++ b/trunk/include/asm-cris/bitops.h @@ -16,7 +16,6 @@ #include #include -#include #include /* @@ -89,7 +88,7 @@ struct __dummy { unsigned long a[100]; }; * It also implies a memory barrier. */ -extern inline int test_and_set_bit(int nr, volatile unsigned long *addr) +extern inline int test_and_set_bit(int nr, void *addr) { unsigned int mask, retval; unsigned long flags; @@ -97,15 +96,15 @@ extern inline int test_and_set_bit(int nr, volatile unsigned long *addr) adr += nr >> 5; mask = 1 << (nr & 0x1f); - cris_atomic_save(addr, flags); + local_save_flags(flags); + local_irq_disable(); retval = (mask & *adr) != 0; *adr |= mask; - cris_atomic_restore(addr, flags); local_irq_restore(flags); return retval; } -extern inline int __test_and_set_bit(int nr, volatile unsigned long *addr) +extern inline int __test_and_set_bit(int nr, void *addr) { unsigned int mask, retval; unsigned int *adr = (unsigned int *)addr; @@ -132,7 +131,7 @@ extern inline int __test_and_set_bit(int nr, volatile unsigned long *addr) * It also implies a memory barrier. */ -extern inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +extern inline int test_and_clear_bit(int nr, void *addr) { unsigned int mask, retval; unsigned long flags; @@ -140,10 +139,11 @@ extern inline int test_and_clear_bit(int nr, volatile unsigned long *addr) adr += nr >> 5; mask = 1 << (nr & 0x1f); - cris_atomic_save(addr, flags); + local_save_flags(flags); + local_irq_disable(); retval = (mask & *adr) != 0; *adr &= ~mask; - cris_atomic_restore(addr, flags); + local_irq_restore(flags); return retval; } @@ -157,7 +157,7 @@ extern inline int test_and_clear_bit(int nr, volatile unsigned long *addr) * but actually fail. You must protect multiple accesses with a lock. */ -extern inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) +extern inline int __test_and_clear_bit(int nr, void *addr) { unsigned int mask, retval; unsigned int *adr = (unsigned int *)addr; @@ -177,23 +177,24 @@ extern inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) * It also implies a memory barrier. */ -extern inline int test_and_change_bit(int nr, volatile unsigned long *addr) +extern inline int test_and_change_bit(int nr, void *addr) { unsigned int mask, retval; unsigned long flags; unsigned int *adr = (unsigned int *)addr; adr += nr >> 5; mask = 1 << (nr & 0x1f); - cris_atomic_save(addr, flags); + local_save_flags(flags); + local_irq_disable(); retval = (mask & *adr) != 0; *adr ^= mask; - cris_atomic_restore(addr, flags); + local_irq_restore(flags); return retval; } /* WARNING: non atomic and it can be reordered! */ -extern inline int __test_and_change_bit(int nr, volatile unsigned long *addr) +extern inline int __test_and_change_bit(int nr, void *addr) { unsigned int mask, retval; unsigned int *adr = (unsigned int *)addr; @@ -214,7 +215,7 @@ extern inline int __test_and_change_bit(int nr, volatile unsigned long *addr) * This routine doesn't need to be atomic. */ -extern inline int test_bit(int nr, const volatile unsigned long *addr) +extern inline int test_bit(int nr, const void *addr) { unsigned int mask; unsigned int *adr = (unsigned int *)addr; @@ -258,7 +259,7 @@ extern inline int test_bit(int nr, const volatile unsigned long *addr) * @offset: The bitnumber to start searching at * @size: The maximum size to search */ -extern inline int find_next_zero_bit (const unsigned long * addr, int size, int offset) +extern inline int find_next_zero_bit (void * addr, int size, int offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; @@ -300,7 +301,7 @@ extern inline int find_next_zero_bit (const unsigned long * addr, int size, int * @offset: The bitnumber to start searching at * @size: The maximum size to search */ -static __inline__ int find_next_bit(const unsigned long *addr, int size, int offset) +static __inline__ int find_next_bit(void *addr, int size, int offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; @@ -366,7 +367,7 @@ static __inline__ int find_next_bit(const unsigned long *addr, int size, int off #define minix_test_bit(nr,addr) test_bit(nr,addr) #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) -extern inline int sched_find_first_bit(const unsigned long *b) +extern inline int sched_find_first_bit(unsigned long *b) { if (unlikely(b[0])) return __ffs(b[0]); diff --git a/trunk/include/asm-cris/dma-mapping.h b/trunk/include/asm-cris/dma-mapping.h index 0b5c3fdaefe1..0d770f60127a 100644 --- a/trunk/include/asm-cris/dma-mapping.h +++ b/trunk/include/asm-cris/dma-mapping.h @@ -1,179 +1,125 @@ -/* DMA mapping. Nothing tricky here, just virt_to_phys */ - #ifndef _ASM_CRIS_DMA_MAPPING_H #define _ASM_CRIS_DMA_MAPPING_H -#include -#include - -#include -#include -#include +#include "scatterlist.h" -#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) -#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +static inline int +dma_supported(struct device *dev, u64 mask) +{ + BUG(); + return 0; +} -#ifdef CONFIG_PCI -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, int flag); +static inline int +dma_set_mask(struct device *dev, u64 dma_mask) +{ + BUG(); + return 1; +} -void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); -#else static inline void * dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, - int flag) + int flag) { - BUG(); - return NULL; + BUG(); + return NULL; } static inline void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, - dma_addr_t dma_handle) + dma_addr_t dma_handle) { - BUG(); + BUG(); } -#endif + static inline dma_addr_t -dma_map_single(struct device *dev, void *ptr, size_t size, +dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - return virt_to_phys(ptr); + BUG(); + return 0; } static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); -} - -static inline int -dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) -{ - printk("Map sg\n"); - return nents; + BUG(); } static inline dma_addr_t -dma_map_page(struct device *dev, struct page *page, unsigned long offset, - size_t size, enum dma_data_direction direction) +dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - return page_to_phys(page) + offset; + BUG(); + return 0; } static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); -} - - -static inline void -dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); -} - -static inline void -dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ + BUG(); } -static inline void -dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) +static inline int +dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction) { + BUG(); + return 1; } static inline void -dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) +dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, + enum dma_data_direction direction) { + BUG(); } static inline void -dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) +dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) { + BUG(); } static inline void -dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) +dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) { + BUG(); } -static inline int -dma_mapping_error(dma_addr_t dma_addr) -{ - return 0; -} +/* Now for the API extensions over the pci_ one */ -static inline int -dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if(mask < 0x00ffffff) - return 0; - - return 1; -} - -static inline int -dma_set_mask(struct device *dev, u64 mask) -{ - if(!dev->dma_mask || !dma_supported(dev, mask)) - return -EIO; - - *dev->dma_mask = mask; - - return 0; -} +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +#define dma_is_consistent(d) (1) static inline int dma_get_cache_alignment(void) { + /* no easy way to get cache size on all processors, so return + * the maximum possible, to be safe */ return (1 << L1_CACHE_SHIFT_MAX); } -#define dma_is_consistent(d) (1) +static inline void +dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + BUG(); +} static inline void dma_cache_sync(void *vaddr, size_t size, enum dma_data_direction direction) { + BUG(); } -#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY -extern int -dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, - dma_addr_t device_addr, size_t size, int flags); - -extern void -dma_release_declared_memory(struct device *dev); - -extern void * -dma_mark_declared_memory_occupied(struct device *dev, - dma_addr_t device_addr, size_t size); - #endif + diff --git a/trunk/include/asm-cris/dma.h b/trunk/include/asm-cris/dma.h index 6f188dc56138..c229fac35cdc 100644 --- a/trunk/include/asm-cris/dma.h +++ b/trunk/include/asm-cris/dma.h @@ -10,12 +10,4 @@ #define MAX_DMA_ADDRESS PAGE_OFFSET -/* From PCI */ - -#ifdef CONFIG_PCI -extern int isa_dma_bridge_buggy; -#else -#define isa_dma_bridge_buggy (0) -#endif - #endif /* _ASM_DMA_H */ diff --git a/trunk/include/asm-cris/elf.h b/trunk/include/asm-cris/elf.h index 87a60bd8e667..d37fd5c4a567 100644 --- a/trunk/include/asm-cris/elf.h +++ b/trunk/include/asm-cris/elf.h @@ -8,27 +8,6 @@ #include #include -#define R_CRIS_NONE 0 -#define R_CRIS_8 1 -#define R_CRIS_16 2 -#define R_CRIS_32 3 -#define R_CRIS_8_PCREL 4 -#define R_CRIS_16_PCREL 5 -#define R_CRIS_32_PCREL 6 -#define R_CRIS_GNU_VTINHERIT 7 -#define R_CRIS_GNU_VTENTRY 8 -#define R_CRIS_COPY 9 -#define R_CRIS_GLOB_DAT 10 -#define R_CRIS_JUMP_SLOT 11 -#define R_CRIS_RELATIVE 12 -#define R_CRIS_16_GOT 13 -#define R_CRIS_32_GOT 14 -#define R_CRIS_16_GOTPLT 15 -#define R_CRIS_32_GOTPLT 16 -#define R_CRIS_32_GOTREL 17 -#define R_CRIS_32_PLT_GOTREL 18 -#define R_CRIS_32_PLT_PCREL 19 - typedef unsigned long elf_greg_t; /* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is @@ -39,30 +18,18 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG]; /* A placeholder; CRIS does not have any fp regs. */ typedef unsigned long elf_fpregset_t; +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ( (x)->e_machine == EM_CRIS ) + /* * These are used to set parameters in the core dumps. */ #define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB +#define ELF_DATA ELFDATA2LSB; #define ELF_ARCH EM_CRIS -/* The master for these definitions is {binutils}/include/elf/cris.h: */ -/* User symbols in this file have a leading underscore. */ -#define EF_CRIS_UNDERSCORE 0x00000001 - -/* This is a mask for different incompatible machine variants. */ -#define EF_CRIS_VARIANT_MASK 0x0000000e - -/* Variant 0; may contain v0..10 object. */ -#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 - -/* Variant 1; contains v32 object. */ -#define EF_CRIS_VARIANT_V32 0x00000002 - -/* Variant 2; contains object compatible with v32 and v10. */ -#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 -/* End of excerpt from {binutils}/include/elf/cris.h. */ - #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 8192 diff --git a/trunk/include/asm-cris/etraxgpio.h b/trunk/include/asm-cris/etraxgpio.h index 80ee10f70d43..cf04af9635cc 100644 --- a/trunk/include/asm-cris/etraxgpio.h +++ b/trunk/include/asm-cris/etraxgpio.h @@ -13,7 +13,7 @@ are enabled. * * - * For ETRAX FS (ARCH_V32): + * For ETRAX 200 (ARCH_V32): * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction * /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction @@ -39,10 +39,10 @@ #define ETRAXGPIO_IOCTYPE 43 #define GPIO_MINOR_A 0 #define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_C 3 -#define GPIO_MINOR_D 4 -#define GPIO_MINOR_E 5 +#define GPIO_MINOR_C 2 +#define GPIO_MINOR_D 3 +#define GPIO_MINOR_E 4 +#define GPIO_MINOR_LEDS 5 #define GPIO_MINOR_LAST 5 #endif diff --git a/trunk/include/asm-cris/hardirq.h b/trunk/include/asm-cris/hardirq.h index 1c13dd3faac3..f4d136228ee1 100644 --- a/trunk/include/asm-cris/hardirq.h +++ b/trunk/include/asm-cris/hardirq.h @@ -1,17 +1,18 @@ #ifndef __ASM_HARDIRQ_H #define __ASM_HARDIRQ_H +/* only non-SMP supported */ + #include #include +/* entry.S is sensitive to the offsets of these fields */ typedef struct { unsigned int __softirq_pending; } ____cacheline_aligned irq_cpustat_t; #include /* Standard mappings for irq_cpustat_t above */ -void ack_bad_irq(unsigned int irq); - #define HARDIRQ_BITS 8 /* diff --git a/trunk/include/asm-cris/hw_irq.h b/trunk/include/asm-cris/hw_irq.h deleted file mode 100644 index 341536a234e9..000000000000 --- a/trunk/include/asm-cris/hw_irq.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _ASM_HW_IRQ_H -#define _ASM_HW_IRQ_H - -static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {} - -#endif - diff --git a/trunk/include/asm-cris/ide.h b/trunk/include/asm-cris/ide.h deleted file mode 100644 index a894f66665f8..000000000000 --- a/trunk/include/asm-cris/ide.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/include/asm-cris/io.h b/trunk/include/asm-cris/io.h index 16e791b3c721..1d2b51701e8d 100644 --- a/trunk/include/asm-cris/io.h +++ b/trunk/include/asm-cris/io.h @@ -3,21 +3,6 @@ #include /* for __va, __pa */ #include -#include - -struct cris_io_operations -{ - u32 (*read_mem)(void *addr, int size); - void (*write_mem)(u32 val, int size, void *addr); - u32 (*read_io)(u32 port, void *addr, int size, int count); - void (*write_io)(u32 port, void *addr, int size, int count); -}; - -#ifdef CONFIG_PCI -extern struct cris_io_operations *cris_iops; -#else -#define cris_iops ((struct cris_io_operations*)NULL) -#endif /* * Change virtual addresses to physical addresses and vv. @@ -33,17 +18,14 @@ extern inline void * phys_to_virt(unsigned long address) return __va(address); } -extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); -extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot); +extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); -extern inline void __iomem * ioremap (unsigned long offset, unsigned long size) +extern inline void * ioremap (unsigned long offset, unsigned long size) { return __ioremap(offset, size, 0); } -extern void iounmap(volatile void * __iomem addr); - -extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); +extern void iounmap(void *addr); /* * IO bus memory addresses are also 1:1 with the physical address @@ -57,32 +39,9 @@ extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); * differently. On the CRIS architecture, we just read/write the * memory location directly. */ -#ifdef CONFIG_PCI -#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000) -#else -#define PCI_SPACE(x) 0 -#endif -static inline unsigned char readb(const volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - return cris_iops->read_mem((void*)addr, 1); - else - return *(volatile unsigned char __force *) addr; -} -static inline unsigned short readw(const volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - return cris_iops->read_mem((void*)addr, 2); - else - return *(volatile unsigned short __force *) addr; -} -static inline unsigned int readl(const volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - return cris_iops->read_mem((void*)addr, 4); - else - return *(volatile unsigned int __force *) addr; -} +#define readb(addr) (*(volatile unsigned char *) (addr)) +#define readw(addr) (*(volatile unsigned short *) (addr)) +#define readl(addr) (*(volatile unsigned int *) (addr)) #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) #define readl_relaxed(addr) readl(addr) @@ -90,27 +49,9 @@ static inline unsigned int readl(const volatile void __iomem *addr) #define __raw_readw readw #define __raw_readl readl -static inline void writeb(unsigned char b, volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - cris_iops->write_mem(b, 1, (void*)addr); - else - *(volatile unsigned char __force *) addr = b; -} -static inline void writew(unsigned short b, volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - cris_iops->write_mem(b, 2, (void*)addr); - else - *(volatile unsigned short __force *) addr = b; -} -static inline void writel(unsigned int b, volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - cris_iops->write_mem(b, 4, (void*)addr); - else - *(volatile unsigned int __force *) addr = b; -} +#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel @@ -125,25 +66,25 @@ static inline void writel(unsigned int b, volatile void __iomem *addr) * Again, CRIS does not require mem IO specific function. */ -#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void __force *)(b),(c),(d)) +#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void *)(b),(c),(d)) /* The following is junk needed for the arch-independent code but which * we never use in the CRIS port */ #define IO_SPACE_LIMIT 0xffff -#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0) -#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0) -#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0) -#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0) -#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0) -#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0) -#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1) -#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1) -#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1) -#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count) -#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count) -#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count) +#define inb(x) (0) +#define inw(x) (0) +#define inl(x) (0) +#define outb(x,y) +#define outw(x,y) +#define outl(x,y) +#define insb(x,y,z) +#define insw(x,y,z) +#define insl(x,y,z) +#define outsb(x,y,z) +#define outsw(x,y,z) +#define outsl(x,y,z) /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem diff --git a/trunk/include/asm-cris/irq.h b/trunk/include/asm-cris/irq.h index 8e787fdaedd4..87f342517bb1 100644 --- a/trunk/include/asm-cris/irq.h +++ b/trunk/include/asm-cris/irq.h @@ -8,6 +8,16 @@ extern __inline__ int irq_canonicalize(int irq) return irq; } +extern void disable_irq(unsigned int); +extern void enable_irq(unsigned int); + +#define disable_irq_nosync disable_irq +#define enable_irq_nosync enable_irq + +struct irqaction; +struct pt_regs; +int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); + #endif /* _ASM_IRQ_H */ diff --git a/trunk/include/asm-cris/kmap_types.h b/trunk/include/asm-cris/kmap_types.h index 492988cb9077..eec0974c2417 100644 --- a/trunk/include/asm-cris/kmap_types.h +++ b/trunk/include/asm-cris/kmap_types.h @@ -17,8 +17,8 @@ enum km_type { KM_PTE1, KM_IRQ0, KM_IRQ1, - KM_SOFTIRQ0, - KM_SOFTIRQ1, + KM_CRYPTO_USER, + KM_CRYPTO_SOFTIRQ, KM_TYPE_NR }; diff --git a/trunk/include/asm-cris/mmu_context.h b/trunk/include/asm-cris/mmu_context.h index e6e659dc757b..f9308c5bbd99 100644 --- a/trunk/include/asm-cris/mmu_context.h +++ b/trunk/include/asm-cris/mmu_context.h @@ -15,7 +15,7 @@ extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, * registers like cr3 on the i386 */ -extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */ +extern volatile pgd_t *current_pgd; /* defined in arch/cris/mm/fault.c */ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { diff --git a/trunk/include/asm-cris/page.h b/trunk/include/asm-cris/page.h index bbf17bd39385..c767da1ef8f5 100644 --- a/trunk/include/asm-cris/page.h +++ b/trunk/include/asm-cris/page.h @@ -29,15 +29,18 @@ */ #ifndef __ASSEMBLY__ typedef struct { unsigned long pte; } pte_t; +typedef struct { unsigned long pmd; } pmd_t; typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; #endif #define pte_val(x) ((x).pte) +#define pmd_val(x) ((x).pmd) #define pgd_val(x) ((x).pgd) #define pgprot_val(x) ((x).pgprot) #define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) @@ -70,6 +73,10 @@ typedef struct { unsigned long pgprot; } pgprot_t; #ifndef __ASSEMBLY__ +#define BUG() do { \ + printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ +} while (0) + /* Pure 2^n version of get_order */ static inline int get_order(unsigned long size) { diff --git a/trunk/include/asm-cris/pci.h b/trunk/include/asm-cris/pci.h index 2064bc1de074..c61041531889 100644 --- a/trunk/include/asm-cris/pci.h +++ b/trunk/include/asm-cris/pci.h @@ -1,105 +1,13 @@ #ifndef __ASM_CRIS_PCI_H #define __ASM_CRIS_PCI_H -#include - -#ifdef __KERNEL__ -#include /* for struct page */ - -/* Can be used to override the logic in pci_scan_bus for skipping - already-configured bus numbers - to be used for buggy BIOSes - or architectures with incomplete PCI setup by the loader */ - -#define pcibios_assign_all_busses(void) 1 - -extern unsigned long pci_mem_start; -#define PCIBIOS_MIN_IO 0x1000 -#define PCIBIOS_MIN_MEM 0x10000000 - -#define PCIBIOS_MIN_CARDBUS_IO 0x4000 - -void pcibios_config_init(void); -struct pci_bus * pcibios_scan_root(int bus); -int pcibios_assign_resources(void); - -void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq); -struct irq_routing_table *pcibios_get_irq_routing_table(void); -int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); - -/* Dynamic DMA mapping stuff. - * i386 has everything mapped statically. - */ - -#include -#include #include -#include -#include - -struct pci_dev; - -/* The PCI address space does equal the physical memory - * address space. The networking and block device layers use - * this boolean for bounce buffer decisions. - */ -#define PCI_DMA_BUS_IS_PHYS (1) - -/* pci_unmap_{page,single} is a nop so... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) -#define pci_unmap_addr(PTR, ADDR_NAME) (0) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) -#define pci_unmap_len(PTR, LEN_NAME) (0) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) - -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - -static inline dma64_addr_t -pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) -{ - return ((dma64_addr_t) page_to_phys(page) + - (dma64_addr_t) offset); -} - -static inline struct page * -pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return pfn_to_page(dma_addr >> PAGE_SHIFT); -} - -static inline unsigned long -pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return (dma_addr & ~PAGE_MASK); -} - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - -#define HAVE_PCI_MMAP -extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, - enum pci_mmap_state mmap_state, int write_combine); - - -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - -#endif /* __KERNEL__ */ - -/* implement the pci_ DMA API in terms of the generic device dma_ one */ #include -/* generic pci stuff */ -#include +/* ETRAX chips don't have a PCI bus. This file is just here because some stupid .c code + * includes it even if CONFIG_PCI is not set. + */ +#define PCI_DMA_BUS_IS_PHYS (1) #endif /* __ASM_CRIS_PCI_H */ + diff --git a/trunk/include/asm-cris/pgalloc.h b/trunk/include/asm-cris/pgalloc.h index a131776edf41..b202e62ed6e0 100644 --- a/trunk/include/asm-cris/pgalloc.h +++ b/trunk/include/asm-cris/pgalloc.h @@ -47,6 +47,16 @@ extern inline void pte_free(struct page *pte) #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +/* + * We don't have any real pmd's, and this code never triggers because + * the pgd will always be present.. + */ + +#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); }) +#define pmd_free(x) do { } while (0) +#define __pmd_free_tlb(tlb,x) do { } while (0) +#define pgd_populate(mm, pmd, pte) BUG() + #define check_pgt_cache() do { } while (0) #endif diff --git a/trunk/include/asm-cris/pgtable.h b/trunk/include/asm-cris/pgtable.h index a9143bed99db..f7042944b073 100644 --- a/trunk/include/asm-cris/pgtable.h +++ b/trunk/include/asm-cris/pgtable.h @@ -5,8 +5,7 @@ #ifndef _CRIS_PGTABLE_H #define _CRIS_PGTABLE_H -#include -#include +#include #ifndef __ASSEMBLY__ #include @@ -42,14 +41,22 @@ extern void paging_init(void); * but the define is needed for a generic inline function.) */ #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) -#define set_pgu(pudptr, pudval) (*(pudptr) = pudval) +#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval) -/* PGDIR_SHIFT determines the size of the area a second-level page table can +/* PMD_SHIFT determines the size of the area a second-level page table can * map. It is equal to the page size times the number of PTE's that fit in * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. */ -#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) +#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) + +/* PGDIR_SHIFT determines what a third-level page table entry can map. + * Since we fold into a two-level structure, this is the same as PMD_SHIFT. + */ + +#define PGDIR_SHIFT PMD_SHIFT #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -60,6 +67,7 @@ extern void paging_init(void); * divide it by 4 (shift by 2). */ #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) +#define PTRS_PER_PMD 1 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) /* calculate how many PGD entries a user-level program can use @@ -97,7 +105,7 @@ extern unsigned long empty_zero_page; #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) -#define pmd_none(x) (!pmd_val(x)) +#define pmd_none(x) (!pmd_val(x)) /* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. */ @@ -107,6 +115,16 @@ extern unsigned long empty_zero_page; #ifndef __ASSEMBLY__ +/* + * The "pgd_xxx()" functions here are trivial for a folded two-level + * setup: the pgd is never bad, and a pmd always exists (as it's folded + * into the pgd entry) + */ +extern inline int pgd_none(pgd_t pgd) { return 0; } +extern inline int pgd_bad(pgd_t pgd) { return 0; } +extern inline int pgd_present(pgd_t pgd) { return 1; } +extern inline void pgd_clear(pgd_t * pgdp) { } + /* * The following only work if pte_present() is true. * Undefined behaviour if not.. @@ -257,7 +275,7 @@ extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep) #define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) /* to find an entry in a page-table-directory. */ -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) +#define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) /* to find an entry in a page-table-directory */ extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) @@ -268,6 +286,12 @@ extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(address) pgd_offset(&init_mm, address) +/* Find an entry in the second-level page table.. */ +extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) +{ + return (pmd_t *) dir; +} + /* Find an entry in the third-level page table.. */ #define __pte_offset(address) \ (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) @@ -284,6 +308,8 @@ extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) #define pte_ERROR(e) \ printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) +#define pmd_ERROR(e) \ + printk("%s:%d: bad pmd %p(%08lx).\n", __FILE__, __LINE__, &(e), pmd_val(e)) #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) @@ -322,7 +348,5 @@ extern inline void update_mmu_cache(struct vm_area_struct * vma, #define pte_to_pgoff(x) (pte_val(x) >> 6) #define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE) -typedef pte_t *pte_addr_t; - #endif /* __ASSEMBLY__ */ #endif /* _CRIS_PGTABLE_H */ diff --git a/trunk/include/asm-cris/processor.h b/trunk/include/asm-cris/processor.h index 0dc218117bd8..623bdf06d911 100644 --- a/trunk/include/asm-cris/processor.h +++ b/trunk/include/asm-cris/processor.h @@ -55,6 +55,15 @@ unsigned long get_wchan(struct task_struct *p); #define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) +/* + * Free current thread data structures etc.. + */ + +extern inline void exit_thread(void) +{ + /* Nothing needs to be done. */ +} + extern unsigned long thread_saved_pc(struct task_struct *tsk); /* Free all resources held by a thread. */ diff --git a/trunk/include/asm-cris/ptrace.h b/trunk/include/asm-cris/ptrace.h index 1ec69a7ea836..7a8c2880e487 100644 --- a/trunk/include/asm-cris/ptrace.h +++ b/trunk/include/asm-cris/ptrace.h @@ -9,6 +9,4 @@ #define PTRACE_SETREGS 13 #endif -#define profile_pc(regs) instruction_pointer(regs) - #endif /* _CRIS_PTRACE_H */ diff --git a/trunk/include/asm-cris/semaphore.h b/trunk/include/asm-cris/semaphore.h index 8ed7636ab311..605aa7eaaaf8 100644 --- a/trunk/include/asm-cris/semaphore.h +++ b/trunk/include/asm-cris/semaphore.h @@ -72,9 +72,10 @@ extern inline void down(struct semaphore * sem) might_sleep(); /* atomically decrement the semaphores count, and if its negative, we wait */ - cris_atomic_save(sem, flags); + local_save_flags(flags); + local_irq_disable(); failed = --(sem->count.counter) < 0; - cris_atomic_restore(sem, flags); + local_irq_restore(flags); if(failed) { __down(sem); } @@ -94,9 +95,10 @@ extern inline int down_interruptible(struct semaphore * sem) might_sleep(); /* atomically decrement the semaphores count, and if its negative, we wait */ - cris_atomic_save(sem, flags); + local_save_flags(flags); + local_irq_disable(); failed = --(sem->count.counter) < 0; - cris_atomic_restore(sem, flags); + local_irq_restore(flags); if(failed) failed = __down_interruptible(sem); return(failed); @@ -107,13 +109,13 @@ extern inline int down_trylock(struct semaphore * sem) unsigned long flags; int failed; - cris_atomic_save(sem, flags); + local_save_flags(flags); + local_irq_disable(); failed = --(sem->count.counter) < 0; - cris_atomic_restore(sem, flags); + local_irq_restore(flags); if(failed) failed = __down_trylock(sem); return(failed); - } /* @@ -128,9 +130,10 @@ extern inline void up(struct semaphore * sem) int wakeup; /* atomically increment the semaphores count, and if it was negative, we wake people */ - cris_atomic_save(sem, flags); + local_save_flags(flags); + local_irq_disable(); wakeup = ++(sem->count.counter) <= 0; - cris_atomic_restore(sem, flags); + local_irq_restore(flags); if(wakeup) { __up(sem); } diff --git a/trunk/include/asm-cris/smp.h b/trunk/include/asm-cris/smp.h index dca5ef1d8c97..c2f4feaa041d 100644 --- a/trunk/include/asm-cris/smp.h +++ b/trunk/include/asm-cris/smp.h @@ -1,11 +1,4 @@ #ifndef __ASM_SMP_H #define __ASM_SMP_H -#include - -extern cpumask_t phys_cpu_present_map; -#define cpu_possible_map phys_cpu_present_map - -#define __smp_processor_id() (current_thread_info()->cpu) - #endif diff --git a/trunk/include/asm-cris/spinlock.h b/trunk/include/asm-cris/spinlock.h deleted file mode 100644 index 2e8ba8afc7af..000000000000 --- a/trunk/include/asm-cris/spinlock.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/include/asm-cris/sync_serial.h b/trunk/include/asm-cris/sync_serial.h deleted file mode 100644 index f930b6e00663..000000000000 --- a/trunk/include/asm-cris/sync_serial.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * ioctl defines for synchronous serial port driver - * - * Copyright (c) 2001-2003 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef SYNC_SERIAL_H -#define SYNC_SERIAL_H - -#include - -#define SSP_SPEED _IOR('S', 0, unsigned int) -#define SSP_MODE _IOR('S', 1, unsigned int) -#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) -#define SSP_IPOLARITY _IOR('S', 3, unsigned int) -#define SSP_OPOLARITY _IOR('S', 4, unsigned int) -#define SSP_SPI _IOR('S', 5, unsigned int) -#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) - -/* Values for SSP_SPEED */ -#define SSP150 0 -#define SSP300 1 -#define SSP600 2 -#define SSP1200 3 -#define SSP2400 4 -#define SSP4800 5 -#define SSP9600 6 -#define SSP19200 7 -#define SSP28800 8 -#define SSP57600 9 -#define SSP115200 10 -#define SSP230400 11 -#define SSP460800 12 -#define SSP921600 13 -#define SSP3125000 14 -#define CODEC 15 - -#define FREQ_4MHz 0 -#define FREQ_2MHz 1 -#define FREQ_1MHz 2 -#define FREQ_512kHz 3 -#define FREQ_256kHz 4 -#define FREQ_128kHz 5 -#define FREQ_64kHz 6 -#define FREQ_32kHz 7 - -/* Used by application to set CODEC divider, word rate and frame rate */ -#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28)) - -/* Used by driver to extract speed */ -#define GET_SPEED(x) (x & 0xff) -#define GET_FREQ(x) ((x & 0xff00) >> 8) -#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) -#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) - -/* Values for SSP_MODE */ -#define MASTER_OUTPUT 0 -#define SLAVE_OUTPUT 1 -#define MASTER_INPUT 2 -#define SLAVE_INPUT 3 -#define MASTER_BIDIR 4 -#define SLAVE_BIDIR 5 - -/* Values for SSP_FRAME_SYNC */ -#define NORMAL_SYNC 1 -#define EARLY_SYNC 2 - -#define BIT_SYNC 4 -#define WORD_SYNC 8 -#define EXTENDED_SYNC 0x10 - -#define SYNC_OFF 0x20 -#define SYNC_ON 0x40 -#define WORD_SIZE_8 0x80 -#define WORD_SIZE_12 0x100 -#define WORD_SIZE_16 0x200 -#define WORD_SIZE_24 0x400 -#define WORD_SIZE_32 0x800 -#define BIT_ORDER_LSB 0x1000 -#define BIT_ORDER_MSB 0x2000 -#define FLOW_CONTROL_ENABLE 0x4000 -#define FLOW_CONTROL_DISABLE 0x8000 -#define CLOCK_GATED 0x10000 -#define CLOCK_NOT_GATED 0x20000 - -/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ -#define CLOCK_NORMAL 1 -#define CLOCK_INVERT 2 -#define CLOCK_INEGEDGE CLOCK_NORMAL -#define CLOCK_IPOSEDGE CLOCK_INVERT -#define FRAME_NORMAL 4 -#define FRAME_INVERT 8 -#define STATUS_NORMAL 0x10 -#define STATUS_INVERT 0x20 - -/* Values for SSP_SPI */ -#define SPI_MASTER 0 -#define SPI_SLAVE 1 - -/* Values for SSP_INBUFCHUNK */ -/* plain integer with the size of DMA chunks */ - -#endif diff --git a/trunk/include/asm-cris/termbits.h b/trunk/include/asm-cris/termbits.h index be0836d2f282..16d9a491fdb3 100644 --- a/trunk/include/asm-cris/termbits.h +++ b/trunk/include/asm-cris/termbits.h @@ -152,7 +152,7 @@ struct termios { #define B921600 0010005 #define B1843200 0010006 #define B6250000 0010007 -/* ETRAX FS supports this as well */ +/* etrax 200 supports this as well */ #define B12500000 0010010 #define CIBAUD 002003600000 /* input baud rate (used in v32) */ /* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX diff --git a/trunk/include/asm-cris/thread_info.h b/trunk/include/asm-cris/thread_info.h index cef0140fc104..5ba4b7865cc5 100644 --- a/trunk/include/asm-cris/thread_info.h +++ b/trunk/include/asm-cris/thread_info.h @@ -43,7 +43,7 @@ struct thread_info { #endif -#define PREEMPT_ACTIVE 0x10000000 +#define PREEMPT_ACTIVE 0x4000000 /* * macros/functions for gaining access to the thread information structure diff --git a/trunk/include/asm-cris/timex.h b/trunk/include/asm-cris/timex.h index 3fb069a37717..375c41af47de 100644 --- a/trunk/include/asm-cris/timex.h +++ b/trunk/include/asm-cris/timex.h @@ -14,7 +14,7 @@ * used so it does not matter. */ -typedef unsigned long long cycles_t; +typedef unsigned int cycles_t; extern inline cycles_t get_cycles(void) { diff --git a/trunk/include/asm-cris/tlbflush.h b/trunk/include/asm-cris/tlbflush.h index 6ed7d9ae90db..1781fe1a32f6 100644 --- a/trunk/include/asm-cris/tlbflush.h +++ b/trunk/include/asm-cris/tlbflush.h @@ -18,26 +18,13 @@ * */ -extern void __flush_tlb_all(void); -extern void __flush_tlb_mm(struct mm_struct *mm); -extern void __flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr); - -#ifdef CONFIG_SMP extern void flush_tlb_all(void); extern void flush_tlb_mm(struct mm_struct *mm); extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); -#else -#define flush_tlb_all __flush_tlb_all -#define flush_tlb_mm __flush_tlb_mm -#define flush_tlb_page __flush_tlb_page -#endif - -static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) -{ - flush_tlb_mm(vma->vm_mm); -} +extern void flush_tlb_range(struct vm_area_struct *vma, + unsigned long start, + unsigned long end); extern inline void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end) diff --git a/trunk/include/asm-cris/types.h b/trunk/include/asm-cris/types.h index 8fa6d6c7afce..41a0d450ba1d 100644 --- a/trunk/include/asm-cris/types.h +++ b/trunk/include/asm-cris/types.h @@ -52,7 +52,7 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; typedef u32 dma64_addr_t; -typedef unsigned short kmem_bufctl_t; +typedef unsigned int kmem_bufctl_t; #endif /* __ASSEMBLY__ */ diff --git a/trunk/include/asm-cris/unistd.h b/trunk/include/asm-cris/unistd.h index 28232ad2ff34..e80bf276b101 100644 --- a/trunk/include/asm-cris/unistd.h +++ b/trunk/include/asm-cris/unistd.h @@ -288,15 +288,8 @@ #define __NR_mq_timedreceive (__NR_mq_open+3) #define __NR_mq_notify (__NR_mq_open+4) #define __NR_mq_getsetattr (__NR_mq_open+5) -#define __NR_sys_kexec_load 283 -#define __NR_waitid 284 -/* #define __NR_sys_setaltroot 285 */ -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 - -#define NR_syscalls 289 - + +#define NR_syscalls 283 #ifdef __KERNEL__ diff --git a/trunk/include/asm-i386/ptrace.h b/trunk/include/asm-i386/ptrace.h index 05532875e39e..b926cb4f4cfd 100644 --- a/trunk/include/asm-i386/ptrace.h +++ b/trunk/include/asm-i386/ptrace.h @@ -55,9 +55,6 @@ struct pt_regs { #define PTRACE_SET_THREAD_AREA 26 #ifdef __KERNEL__ - -#include - struct task_struct; extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, int error_code); diff --git a/trunk/include/asm-ia64/unistd.h b/trunk/include/asm-ia64/unistd.h index 3a0c69524656..517f1649ee64 100644 --- a/trunk/include/asm-ia64/unistd.h +++ b/trunk/include/asm-ia64/unistd.h @@ -266,9 +266,6 @@ #define __NR_ioprio_set 1274 #define __NR_ioprio_get 1275 #define __NR_set_zone_reclaim 1276 -#define __NR_inotify_init 1277 -#define __NR_inotify_add_watch 1278 -#define __NR_inotify_rm_watch 1279 #ifdef __KERNEL__ diff --git a/trunk/include/asm-ppc/cpm2.h b/trunk/include/asm-ppc/cpm2.h index 9483d4bfacf7..c5883dbed63f 100644 --- a/trunk/include/asm-ppc/cpm2.h +++ b/trunk/include/asm-ppc/cpm2.h @@ -109,7 +109,6 @@ static inline long IS_DPERR(const uint offset) * and dual port ram. */ extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ - extern uint cpm_dpalloc(uint size, uint align); extern int cpm_dpfree(uint offset); extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align); @@ -117,8 +116,6 @@ extern void cpm_dpdump(void); extern void *cpm_dpram_addr(uint offset); extern void cpm_setbrg(uint brg, uint rate); extern void cpm2_fastbrg(uint brg, uint rate, int div16); -extern void cpm2_reset(void); - /* Buffer descriptors used by many of the CPM protocols. */ @@ -1090,3 +1087,5 @@ typedef struct im_idma { #endif /* __CPM2__ */ #endif /* __KERNEL__ */ + + diff --git a/trunk/include/asm-ppc/dma-mapping.h b/trunk/include/asm-ppc/dma-mapping.h index 6f74f59938d4..7f0487afebbe 100644 --- a/trunk/include/asm-ppc/dma-mapping.h +++ b/trunk/include/asm-ppc/dma-mapping.h @@ -117,7 +117,7 @@ dma_map_page(struct device *dev, struct page *page, __dma_sync_page(page, offset, size, direction); - return page_to_bus(page) + offset; + return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset; } /* We do nothing. */ diff --git a/trunk/include/asm-ppc/mpc10x.h b/trunk/include/asm-ppc/mpc10x.h index 77b1e092c206..f5196a4efbe0 100644 --- a/trunk/include/asm-ppc/mpc10x.h +++ b/trunk/include/asm-ppc/mpc10x.h @@ -163,8 +163,7 @@ enum ppc_sys_devices { MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, - MPC10X_UART0, - MPC10X_UART1, + MPC10X_DUART, }; int mpc10x_bridge_init(struct pci_controller *hose, diff --git a/trunk/include/asm-ppc64/iSeries/HvReleaseData.h b/trunk/include/asm-ppc64/iSeries/HvReleaseData.h index c8162e5ccb21..01a1f13ea4a0 100644 --- a/trunk/include/asm-ppc64/iSeries/HvReleaseData.h +++ b/trunk/include/asm-ppc64/iSeries/HvReleaseData.h @@ -39,11 +39,6 @@ * know that this PLIC does not support running an OS "that old". */ -#define HVREL_TAGSINACTIVE 0x8000 -#define HVREL_32BIT 0x4000 -#define HVREL_NOSHAREDPROCS 0x2000 -#define HVREL_NOHMT 0x1000 - struct HvReleaseData { u32 xDesc; /* Descriptor "HvRD" ebcdic x00-x03 */ u16 xSize; /* Size of this control block x04-x05 */ @@ -51,7 +46,11 @@ struct HvReleaseData { struct naca_struct *xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */ u32 xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */ u32 xRsvd1; /* Reserved x14-x17 */ - u16 xFlags; + u16 xTagsMode:1; /* 0 == tags active, 1 == tags inactive */ + u16 xAddressSize:1; /* 0 == 64-bit, 1 == 32-bit */ + u16 xNoSharedProcs:1; /* 0 == shared procs, 1 == no shared */ + u16 xNoHMT:1; /* 0 == allow HMT, 1 == no HMT */ + u16 xRsvd2:12; /* Reserved x18-x19 */ u16 xVrmIndex; /* VRM Index of OS image x1A-x1B */ u16 xMinSupportedPlicVrmIndex; /* Min PLIC level (soft) x1C-x1D */ u16 xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */ diff --git a/trunk/include/asm-ppc64/iSeries/LparMap.h b/trunk/include/asm-ppc64/iSeries/LparMap.h index 5c32e38c1c01..038e5df7e9f8 100644 --- a/trunk/include/asm-ppc64/iSeries/LparMap.h +++ b/trunk/include/asm-ppc64/iSeries/LparMap.h @@ -49,26 +49,19 @@ * entry to map the Esid to the Vsid. */ -#define HvEsidsToMap 2 -#define HvRangesToMap 1 - /* Hypervisor initially maps 32MB of the load area */ #define HvPagesToMap 8192 struct LparMap { - u64 xNumberEsids; // Number of ESID/VSID pairs - u64 xNumberRanges; // Number of VA ranges to map - u64 xSegmentTableOffs; // Page number within load area of seg table + u64 xNumberEsids; // Number of ESID/VSID pairs (1) + u64 xNumberRanges; // Number of VA ranges to map (1) + u64 xSegmentTableOffs; // Page number within load area of seg table (0) u64 xRsvd[5]; - struct { - u64 xKernelEsid; // Esid used to map kernel load - u64 xKernelVsid; // Vsid used to map kernel load - } xEsids[HvEsidsToMap]; - struct { - u64 xPages; // Number of pages to be mapped - u64 xOffset; // Offset from start of load area - u64 xVPN; // Virtual Page Number - } xRanges[HvRangesToMap]; + u64 xKernelEsid; // Esid used to map kernel load (0x0C00000000) + u64 xKernelVsid; // Vsid used to map kernel load (0x0C00000000) + u64 xPages; // Number of pages to be mapped (8192) + u64 xOffset; // Offset from start of load area (0) + u64 xVPN; // Virtual Page Number (0x000C000000000000) }; extern struct LparMap xLparMap; diff --git a/trunk/include/asm-ppc64/mmu.h b/trunk/include/asm-ppc64/mmu.h index 70348a851313..3d07ddd11e3b 100644 --- a/trunk/include/asm-ppc64/mmu.h +++ b/trunk/include/asm-ppc64/mmu.h @@ -200,8 +200,6 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va, unsigned long prpn, unsigned long vflags, unsigned long rflags); -extern void stabs_alloc(void); - #endif /* __ASSEMBLY__ */ /* @@ -338,9 +336,6 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea) | (ea >> SID_SHIFT)); } -#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS) -#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea)) - #endif /* __ASSEMBLY */ #endif /* _PPC64_MMU_H_ */ diff --git a/trunk/include/asm-s390/atomic.h b/trunk/include/asm-s390/atomic.h index 9d86ba6f12d0..d5a05cf47168 100644 --- a/trunk/include/asm-s390/atomic.h +++ b/trunk/include/asm-s390/atomic.h @@ -123,19 +123,19 @@ typedef struct { #define atomic64_read(v) ((v)->counter) #define atomic64_set(v,i) (((v)->counter) = (i)) -static __inline__ void atomic64_add(long long i, atomic64_t * v) +static __inline__ void atomic64_add(int i, atomic64_t * v) { __CSG_LOOP(v, i, "agr"); } -static __inline__ long long atomic64_add_return(long long i, atomic64_t * v) +static __inline__ long long atomic64_add_return(int i, atomic64_t * v) { return __CSG_LOOP(v, i, "agr"); } -static __inline__ long long atomic64_add_negative(long long i, atomic64_t * v) +static __inline__ long long atomic64_add_negative(int i, atomic64_t * v) { return __CSG_LOOP(v, i, "agr") < 0; } -static __inline__ void atomic64_sub(long long i, atomic64_t * v) +static __inline__ void atomic64_sub(int i, atomic64_t * v) { __CSG_LOOP(v, i, "sgr"); } diff --git a/trunk/include/asm-s390/bitops.h b/trunk/include/asm-s390/bitops.h index 8651524217fd..16bb08499c7f 100644 --- a/trunk/include/asm-s390/bitops.h +++ b/trunk/include/asm-s390/bitops.h @@ -527,64 +527,13 @@ __constant_test_bit(unsigned long nr, const volatile unsigned long *addr) { __constant_test_bit((nr),(addr)) : \ __test_bit((nr),(addr)) ) -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - unsigned long bit = 0; - -#ifdef __s390x__ - if (likely((word & 0xffffffff) == 0xffffffff)) { - word >>= 32; - bit += 32; - } -#endif - if (likely((word & 0xffff) == 0xffff)) { - word >>= 16; - bit += 16; - } - if (likely((word & 0xff) == 0xff)) { - word >>= 8; - bit += 8; - } - return bit + _zb_findmap[word & 0xff]; -} - -/* - * __ffs = find first bit in word. Undefined if no bit exists, - * so code should check against 0UL first.. - */ -static inline unsigned long __ffs (unsigned long word) -{ - unsigned long bit = 0; - -#ifdef __s390x__ - if (likely((word & 0xffffffff) == 0)) { - word >>= 32; - bit += 32; - } -#endif - if (likely((word & 0xffff) == 0)) { - word >>= 16; - bit += 16; - } - if (likely((word & 0xff) == 0)) { - word >>= 8; - bit += 8; - } - return bit + _sb_findmap[word & 0xff]; -} +#ifndef __s390x__ /* * Find-bit routines.. */ - -#ifndef __s390x__ - static inline int -find_first_zero_bit(const unsigned long * addr, unsigned long size) +find_first_zero_bit(const unsigned long * addr, unsigned int size) { typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype; unsigned long cmp, count; @@ -599,7 +548,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned long size) " srl %2,5\n" "0: c %1,0(%0,%4)\n" " jne 1f\n" - " la %0,4(%0)\n" + " ahi %0,4\n" " brct %2,0b\n" " lr %0,%3\n" " j 4f\n" @@ -625,7 +574,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned long size) } static inline int -find_first_bit(const unsigned long * addr, unsigned long size) +find_first_bit(const unsigned long * addr, unsigned int size) { typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype; unsigned long cmp, count; @@ -640,7 +589,7 @@ find_first_bit(const unsigned long * addr, unsigned long size) " srl %2,5\n" "0: c %1,0(%0,%4)\n" " jne 1f\n" - " la %0,4(%0)\n" + " ahi %0,4\n" " brct %2,0b\n" " lr %0,%3\n" " j 4f\n" @@ -665,8 +614,89 @@ find_first_bit(const unsigned long * addr, unsigned long size) return (res < size) ? res : size; } +static inline int +find_next_zero_bit (const unsigned long * addr, int size, int offset) +{ + unsigned long * p = ((unsigned long *) addr) + (offset >> 5); + unsigned long bitvec, reg; + int set, bit = offset & 31, res; + + if (bit) { + /* + * Look for zero in first word + */ + bitvec = (*p) >> bit; + __asm__(" slr %0,%0\n" + " lhi %2,0xff\n" + " tml %1,0xffff\n" + " jno 0f\n" + " ahi %0,16\n" + " srl %1,16\n" + "0: tml %1,0x00ff\n" + " jno 1f\n" + " ahi %0,8\n" + " srl %1,8\n" + "1: nr %1,%2\n" + " ic %1,0(%1,%3)\n" + " alr %0,%1" + : "=&d" (set), "+a" (bitvec), "=&d" (reg) + : "a" (&_zb_findmap) : "cc" ); + if (set < (32 - bit)) + return set + offset; + offset += 32 - bit; + p++; + } + /* + * No zero yet, search remaining full words for a zero + */ + res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr)); + return (offset + res); +} + +static inline int +find_next_bit (const unsigned long * addr, int size, int offset) +{ + unsigned long * p = ((unsigned long *) addr) + (offset >> 5); + unsigned long bitvec, reg; + int set, bit = offset & 31, res; + + if (bit) { + /* + * Look for set bit in first word + */ + bitvec = (*p) >> bit; + __asm__(" slr %0,%0\n" + " lhi %2,0xff\n" + " tml %1,0xffff\n" + " jnz 0f\n" + " ahi %0,16\n" + " srl %1,16\n" + "0: tml %1,0x00ff\n" + " jnz 1f\n" + " ahi %0,8\n" + " srl %1,8\n" + "1: nr %1,%2\n" + " ic %1,0(%1,%3)\n" + " alr %0,%1" + : "=&d" (set), "+a" (bitvec), "=&d" (reg) + : "a" (&_sb_findmap) : "cc" ); + if (set < (32 - bit)) + return set + offset; + offset += 32 - bit; + p++; + } + /* + * No set bit yet, search remaining full words for a bit + */ + res = find_first_bit (p, size - 32 * (p - (unsigned long *) addr)); + return (offset + res); +} + #else /* __s390x__ */ +/* + * Find-bit routines.. + */ static inline unsigned long find_first_zero_bit(const unsigned long * addr, unsigned long size) { @@ -682,7 +712,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned long size) " srlg %2,%2,6\n" "0: cg %1,0(%0,%4)\n" " jne 1f\n" - " la %0,8(%0)\n" + " aghi %0,8\n" " brct %2,0b\n" " lgr %0,%3\n" " j 5f\n" @@ -755,66 +785,143 @@ find_first_bit(const unsigned long * addr, unsigned long size) return (res < size) ? res : size; } +static inline unsigned long +find_next_zero_bit (const unsigned long * addr, unsigned long size, unsigned long offset) +{ + unsigned long * p = ((unsigned long *) addr) + (offset >> 6); + unsigned long bitvec, reg; + unsigned long set, bit = offset & 63, res; + + if (bit) { + /* + * Look for zero in first word + */ + bitvec = (*p) >> bit; + __asm__(" lhi %2,-1\n" + " slgr %0,%0\n" + " clr %1,%2\n" + " jne 0f\n" + " aghi %0,32\n" + " srlg %1,%1,32\n" + "0: lghi %2,0xff\n" + " tmll %1,0xffff\n" + " jno 1f\n" + " aghi %0,16\n" + " srlg %1,%1,16\n" + "1: tmll %1,0x00ff\n" + " jno 2f\n" + " aghi %0,8\n" + " srlg %1,%1,8\n" + "2: ngr %1,%2\n" + " ic %1,0(%1,%3)\n" + " algr %0,%1" + : "=&d" (set), "+a" (bitvec), "=&d" (reg) + : "a" (&_zb_findmap) : "cc" ); + if (set < (64 - bit)) + return set + offset; + offset += 64 - bit; + p++; + } + /* + * No zero yet, search remaining full words for a zero + */ + res = find_first_zero_bit (p, size - 64 * (p - (unsigned long *) addr)); + return (offset + res); +} + +static inline unsigned long +find_next_bit (const unsigned long * addr, unsigned long size, unsigned long offset) +{ + unsigned long * p = ((unsigned long *) addr) + (offset >> 6); + unsigned long bitvec, reg; + unsigned long set, bit = offset & 63, res; + + if (bit) { + /* + * Look for zero in first word + */ + bitvec = (*p) >> bit; + __asm__(" slgr %0,%0\n" + " ltr %1,%1\n" + " jnz 0f\n" + " aghi %0,32\n" + " srlg %1,%1,32\n" + "0: lghi %2,0xff\n" + " tmll %1,0xffff\n" + " jnz 1f\n" + " aghi %0,16\n" + " srlg %1,%1,16\n" + "1: tmll %1,0x00ff\n" + " jnz 2f\n" + " aghi %0,8\n" + " srlg %1,%1,8\n" + "2: ngr %1,%2\n" + " ic %1,0(%1,%3)\n" + " algr %0,%1" + : "=&d" (set), "+a" (bitvec), "=&d" (reg) + : "a" (&_sb_findmap) : "cc" ); + if (set < (64 - bit)) + return set + offset; + offset += 64 - bit; + p++; + } + /* + * No set bit yet, search remaining full words for a bit + */ + res = find_first_bit (p, size - 64 * (p - (unsigned long *) addr)); + return (offset + res); +} + #endif /* __s390x__ */ -static inline int -find_next_zero_bit (const unsigned long * addr, unsigned long size, - unsigned long offset) +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long word) { - const unsigned long *p; - unsigned long bit, set; - - if (offset >= size) - return size; - bit = offset & (__BITOPS_WORDSIZE - 1); - offset -= bit; - size -= offset; - p = addr + offset / __BITOPS_WORDSIZE; - if (bit) { - /* - * s390 version of ffz returns __BITOPS_WORDSIZE - * if no zero bit is present in the word. - */ - set = ffz(*p >> bit) + bit; - if (set >= size) - return size + offset; - if (set < __BITOPS_WORDSIZE) - return set + offset; - offset += __BITOPS_WORDSIZE; - size -= __BITOPS_WORDSIZE; - p++; + unsigned long bit = 0; + +#ifdef __s390x__ + if (likely((word & 0xffffffff) == 0xffffffff)) { + word >>= 32; + bit += 32; + } +#endif + if (likely((word & 0xffff) == 0xffff)) { + word >>= 16; + bit += 16; } - return offset + find_first_zero_bit(p, size); + if (likely((word & 0xff) == 0xff)) { + word >>= 8; + bit += 8; + } + return bit + _zb_findmap[word & 0xff]; } -static inline int -find_next_bit (const unsigned long * addr, unsigned long size, - unsigned long offset) +/* + * __ffs = find first bit in word. Undefined if no bit exists, + * so code should check against 0UL first.. + */ +static inline unsigned long __ffs (unsigned long word) { - const unsigned long *p; - unsigned long bit, set; - - if (offset >= size) - return size; - bit = offset & (__BITOPS_WORDSIZE - 1); - offset -= bit; - size -= offset; - p = addr + offset / __BITOPS_WORDSIZE; - if (bit) { - /* - * s390 version of __ffs returns __BITOPS_WORDSIZE - * if no one bit is present in the word. - */ - set = __ffs(*p & (~0UL << bit)); - if (set >= size) - return size + offset; - if (set < __BITOPS_WORDSIZE) - return set + offset; - offset += __BITOPS_WORDSIZE; - size -= __BITOPS_WORDSIZE; - p++; + unsigned long bit = 0; + +#ifdef __s390x__ + if (likely((word & 0xffffffff) == 0)) { + word >>= 32; + bit += 32; } - return offset + find_first_bit(p, size); +#endif + if (likely((word & 0xffff) == 0)) { + word >>= 16; + bit += 16; + } + if (likely((word & 0xff) == 0)) { + word >>= 8; + bit += 8; + } + return bit + _sb_findmap[word & 0xff]; } /* @@ -924,6 +1031,49 @@ ext2_find_first_zero_bit(void *vaddr, unsigned int size) return (res < size) ? res : size; } +static inline int +ext2_find_next_zero_bit(void *vaddr, unsigned int size, unsigned offset) +{ + unsigned long *addr = vaddr; + unsigned long *p = addr + (offset >> 5); + unsigned long word, reg; + unsigned int bit = offset & 31UL, res; + + if (offset >= size) + return size; + + if (bit) { + __asm__(" ic %0,0(%1)\n" + " icm %0,2,1(%1)\n" + " icm %0,4,2(%1)\n" + " icm %0,8,3(%1)" + : "=&a" (word) : "a" (p) : "cc" ); + word >>= bit; + res = bit; + /* Look for zero in first longword */ + __asm__(" lhi %2,0xff\n" + " tml %1,0xffff\n" + " jno 0f\n" + " ahi %0,16\n" + " srl %1,16\n" + "0: tml %1,0x00ff\n" + " jno 1f\n" + " ahi %0,8\n" + " srl %1,8\n" + "1: nr %1,%2\n" + " ic %1,0(%1,%3)\n" + " alr %0,%1" + : "+&d" (res), "+&a" (word), "=&d" (reg) + : "a" (&_zb_findmap) : "cc" ); + if (res < 32) + return (p - addr)*32 + res; + p++; + } + /* No zero yet, search remaining full bytes for a zero */ + res = ext2_find_first_zero_bit (p, size - 32 * (p - addr)); + return (p - addr) * 32 + res; +} + #else /* __s390x__ */ static inline unsigned long @@ -970,46 +1120,56 @@ ext2_find_first_zero_bit(void *vaddr, unsigned long size) return (res < size) ? res : size; } -#endif /* __s390x__ */ - -static inline int +static inline unsigned long ext2_find_next_zero_bit(void *vaddr, unsigned long size, unsigned long offset) { - unsigned long *addr = vaddr, *p; - unsigned long word, bit, set; + unsigned long *addr = vaddr; + unsigned long *p = addr + (offset >> 6); + unsigned long word, reg; + unsigned long bit = offset & 63UL, res; if (offset >= size) return size; - bit = offset & (__BITOPS_WORDSIZE - 1); - offset -= bit; - size -= offset; - p = addr + offset / __BITOPS_WORDSIZE; + if (bit) { -#ifndef __s390x__ - asm(" ic %0,0(%1)\n" - " icm %0,2,1(%1)\n" - " icm %0,4,2(%1)\n" - " icm %0,8,3(%1)" - : "=&a" (word) : "a" (p), "m" (*p) : "cc" ); -#else - asm(" lrvg %0,%1" : "=a" (word) : "m" (*p) ); -#endif - /* - * s390 version of ffz returns __BITOPS_WORDSIZE - * if no zero bit is present in the word. - */ - set = ffz(word >> bit) + bit; - if (set >= size) - return size + offset; - if (set < __BITOPS_WORDSIZE) - return set + offset; - offset += __BITOPS_WORDSIZE; - size -= __BITOPS_WORDSIZE; - p++; + __asm__(" lrvg %0,%1" /* load reversed, neat instruction */ + : "=a" (word) : "m" (*p) ); + word >>= bit; + res = bit; + /* Look for zero in first 8 byte word */ + __asm__(" lghi %2,0xff\n" + " tmll %1,0xffff\n" + " jno 2f\n" + " ahi %0,16\n" + " srlg %1,%1,16\n" + "0: tmll %1,0xffff\n" + " jno 2f\n" + " ahi %0,16\n" + " srlg %1,%1,16\n" + "1: tmll %1,0xffff\n" + " jno 2f\n" + " ahi %0,16\n" + " srl %1,16\n" + "2: tmll %1,0x00ff\n" + " jno 3f\n" + " ahi %0,8\n" + " srl %1,8\n" + "3: ngr %1,%2\n" + " ic %1,0(%1,%3)\n" + " alr %0,%1" + : "+&d" (res), "+a" (word), "=&d" (reg) + : "a" (&_zb_findmap) : "cc" ); + if (res < 64) + return (p - addr)*64 + res; + p++; } - return offset + ext2_find_first_zero_bit(p, size); + /* No zero yet, search remaining full bytes for a zero */ + res = ext2_find_first_zero_bit (p, size - 64 * (p - addr)); + return (p - addr) * 64 + res; } +#endif /* __s390x__ */ + /* Bitmap functions for the minix filesystem. */ /* FIXME !!! */ #define minix_test_and_set_bit(nr,addr) \ diff --git a/trunk/include/asm-s390/lowcore.h b/trunk/include/asm-s390/lowcore.h index afe6a9f9b0ae..76b5b19c0ae2 100644 --- a/trunk/include/asm-s390/lowcore.h +++ b/trunk/include/asm-s390/lowcore.h @@ -90,6 +90,7 @@ #define __LC_SYSTEM_TIMER 0x278 #define __LC_LAST_UPDATE_CLOCK 0x280 #define __LC_STEAL_CLOCK 0x288 +#define __LC_DIAG44_OPCODE 0x290 #define __LC_KERNEL_STACK 0xD40 #define __LC_THREAD_INFO 0xD48 #define __LC_ASYNC_STACK 0xD50 @@ -285,7 +286,8 @@ struct _lowcore __u64 system_timer; /* 0x278 */ __u64 last_update_clock; /* 0x280 */ __u64 steal_clock; /* 0x288 */ - __u8 pad8[0xc00-0x290]; /* 0x290 */ + __u32 diag44_opcode; /* 0x290 */ + __u8 pad8[0xc00-0x294]; /* 0x294 */ /* System info area */ __u64 save_area[16]; /* 0xc00 */ __u8 pad9[0xd40-0xc80]; /* 0xc80 */ diff --git a/trunk/include/asm-s390/processor.h b/trunk/include/asm-s390/processor.h index 4ec652ebb3b1..8bd14de69e35 100644 --- a/trunk/include/asm-s390/processor.h +++ b/trunk/include/asm-s390/processor.h @@ -203,10 +203,7 @@ unsigned long get_wchan(struct task_struct *p); # define cpu_relax() asm volatile ("diag 0,0,68" : : : "memory") #else /* __s390x__ */ # define cpu_relax() \ - do { \ - if (MACHINE_HAS_DIAG44) \ - asm volatile ("diag 0,0,68" : : : "memory"); \ - } while (0) + asm volatile ("ex 0,%0" : : "i" (__LC_DIAG44_OPCODE) : "memory") #endif /* __s390x__ */ /* diff --git a/trunk/include/asm-s390/spinlock.h b/trunk/include/asm-s390/spinlock.h index 8ff10300f7ee..53cc736b9820 100644 --- a/trunk/include/asm-s390/spinlock.h +++ b/trunk/include/asm-s390/spinlock.h @@ -11,16 +11,21 @@ #ifndef __ASM_SPINLOCK_H #define __ASM_SPINLOCK_H -static inline int -_raw_compare_and_swap(volatile unsigned int *lock, - unsigned int old, unsigned int new) -{ - asm volatile ("cs %0,%3,0(%4)" - : "=d" (old), "=m" (*lock) - : "0" (old), "d" (new), "a" (lock), "m" (*lock) - : "cc", "memory" ); - return old; -} +#ifdef __s390x__ +/* + * Grmph, take care of %&#! user space programs that include + * asm/spinlock.h. The diagnose is only available in kernel + * context. + */ +#ifdef __KERNEL__ +#include +#define __DIAG44_INSN "ex" +#define __DIAG44_OPERAND __LC_DIAG44_OPCODE +#else +#define __DIAG44_INSN "#" +#define __DIAG44_OPERAND 0 +#endif +#endif /* __s390x__ */ /* * Simple spin lock operations. There are two variants, one clears IRQ's @@ -36,35 +41,58 @@ typedef struct { #endif } __attribute__ ((aligned (4))) spinlock_t; -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } -#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0) +#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } +#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0) #define spin_unlock_wait(lp) do { barrier(); } while(((volatile spinlock_t *)(lp))->lock) -#define spin_is_locked(x) ((x)->lock != 0) +#define spin_is_locked(x) ((x)->lock != 0) #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock) -extern void _raw_spin_lock_wait(spinlock_t *lp, unsigned int pc); -extern int _raw_spin_trylock_retry(spinlock_t *lp, unsigned int pc); - -static inline void _raw_spin_lock(spinlock_t *lp) +extern inline void _raw_spin_lock(spinlock_t *lp) { - unsigned long pc = (unsigned long) __builtin_return_address(0); - - if (unlikely(_raw_compare_and_swap(&lp->lock, 0, pc) != 0)) - _raw_spin_lock_wait(lp, pc); +#ifndef __s390x__ + unsigned int reg1, reg2; + __asm__ __volatile__(" bras %0,1f\n" + "0: diag 0,0,68\n" + "1: slr %1,%1\n" + " cs %1,%0,0(%3)\n" + " jl 0b\n" + : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock) + : "a" (&lp->lock), "m" (lp->lock) + : "cc", "memory" ); +#else /* __s390x__ */ + unsigned long reg1, reg2; + __asm__ __volatile__(" bras %1,1f\n" + "0: " __DIAG44_INSN " 0,%4\n" + "1: slr %0,%0\n" + " cs %0,%1,0(%3)\n" + " jl 0b\n" + : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock) + : "a" (&lp->lock), "i" (__DIAG44_OPERAND), + "m" (lp->lock) : "cc", "memory" ); +#endif /* __s390x__ */ } -static inline int _raw_spin_trylock(spinlock_t *lp) +extern inline int _raw_spin_trylock(spinlock_t *lp) { - unsigned long pc = (unsigned long) __builtin_return_address(0); - - if (likely(_raw_compare_and_swap(&lp->lock, 0, pc) == 0)) - return 1; - return _raw_spin_trylock_retry(lp, pc); + unsigned long reg; + unsigned int result; + + __asm__ __volatile__(" basr %1,0\n" + "0: cs %0,%1,0(%3)" + : "=d" (result), "=&d" (reg), "=m" (lp->lock) + : "a" (&lp->lock), "m" (lp->lock), "0" (0) + : "cc", "memory" ); + return !result; } -static inline void _raw_spin_unlock(spinlock_t *lp) +extern inline void _raw_spin_unlock(spinlock_t *lp) { - _raw_compare_and_swap(&lp->lock, lp->lock, 0); + unsigned int old; + + __asm__ __volatile__("cs %0,%3,0(%4)" + : "=d" (old), "=m" (lp->lock) + : "0" (lp->lock), "d" (0), "a" (lp) + : "cc", "memory" ); } /* @@ -78,7 +106,7 @@ static inline void _raw_spin_unlock(spinlock_t *lp) * read-locks. */ typedef struct { - volatile unsigned int lock; + volatile unsigned long lock; volatile unsigned long owner_pc; #ifdef CONFIG_PREEMPT unsigned int break_lock; @@ -101,55 +129,123 @@ typedef struct { */ #define write_can_lock(x) ((x)->lock == 0) -extern void _raw_read_lock_wait(rwlock_t *lp); -extern int _raw_read_trylock_retry(rwlock_t *lp); -extern void _raw_write_lock_wait(rwlock_t *lp); -extern int _raw_write_trylock_retry(rwlock_t *lp); - -static inline void _raw_read_lock(rwlock_t *rw) -{ - unsigned int old; - old = rw->lock & 0x7fffffffU; - if (_raw_compare_and_swap(&rw->lock, old, old + 1) != old) - _raw_read_lock_wait(rw); -} - -static inline void _raw_read_unlock(rwlock_t *rw) -{ - unsigned int old, cmp; - - old = rw->lock; - do { - cmp = old; - old = _raw_compare_and_swap(&rw->lock, old, old - 1); - } while (cmp != old); -} - -static inline void _raw_write_lock(rwlock_t *rw) -{ - if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0)) - _raw_write_lock_wait(rw); -} - -static inline void _raw_write_unlock(rwlock_t *rw) -{ - _raw_compare_and_swap(&rw->lock, 0x80000000, 0); -} - -static inline int _raw_read_trylock(rwlock_t *rw) -{ - unsigned int old; - old = rw->lock & 0x7fffffffU; - if (likely(_raw_compare_and_swap(&rw->lock, old, old + 1) == old)) - return 1; - return _raw_read_trylock_retry(rw); -} - -static inline int _raw_write_trylock(rwlock_t *rw) +#ifndef __s390x__ +#define _raw_read_lock(rw) \ + asm volatile(" l 2,0(%1)\n" \ + " j 1f\n" \ + "0: diag 0,0,68\n" \ + "1: la 2,0(2)\n" /* clear high (=write) bit */ \ + " la 3,1(2)\n" /* one more reader */ \ + " cs 2,3,0(%1)\n" /* try to write new value */ \ + " jl 0b" \ + : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ + "m" ((rw)->lock) : "2", "3", "cc", "memory" ) +#else /* __s390x__ */ +#define _raw_read_lock(rw) \ + asm volatile(" lg 2,0(%1)\n" \ + " j 1f\n" \ + "0: " __DIAG44_INSN " 0,%2\n" \ + "1: nihh 2,0x7fff\n" /* clear high (=write) bit */ \ + " la 3,1(2)\n" /* one more reader */ \ + " csg 2,3,0(%1)\n" /* try to write new value */ \ + " jl 0b" \ + : "=m" ((rw)->lock) \ + : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \ + "m" ((rw)->lock) : "2", "3", "cc", "memory" ) +#endif /* __s390x__ */ + +#ifndef __s390x__ +#define _raw_read_unlock(rw) \ + asm volatile(" l 2,0(%1)\n" \ + " j 1f\n" \ + "0: diag 0,0,68\n" \ + "1: lr 3,2\n" \ + " ahi 3,-1\n" /* one less reader */ \ + " cs 2,3,0(%1)\n" \ + " jl 0b" \ + : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ + "m" ((rw)->lock) : "2", "3", "cc", "memory" ) +#else /* __s390x__ */ +#define _raw_read_unlock(rw) \ + asm volatile(" lg 2,0(%1)\n" \ + " j 1f\n" \ + "0: " __DIAG44_INSN " 0,%2\n" \ + "1: lgr 3,2\n" \ + " bctgr 3,0\n" /* one less reader */ \ + " csg 2,3,0(%1)\n" \ + " jl 0b" \ + : "=m" ((rw)->lock) \ + : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \ + "m" ((rw)->lock) : "2", "3", "cc", "memory" ) +#endif /* __s390x__ */ + +#ifndef __s390x__ +#define _raw_write_lock(rw) \ + asm volatile(" lhi 3,1\n" \ + " sll 3,31\n" /* new lock value = 0x80000000 */ \ + " j 1f\n" \ + "0: diag 0,0,68\n" \ + "1: slr 2,2\n" /* old lock value must be 0 */ \ + " cs 2,3,0(%1)\n" \ + " jl 0b" \ + : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ + "m" ((rw)->lock) : "2", "3", "cc", "memory" ) +#else /* __s390x__ */ +#define _raw_write_lock(rw) \ + asm volatile(" llihh 3,0x8000\n" /* new lock value = 0x80...0 */ \ + " j 1f\n" \ + "0: " __DIAG44_INSN " 0,%2\n" \ + "1: slgr 2,2\n" /* old lock value must be 0 */ \ + " csg 2,3,0(%1)\n" \ + " jl 0b" \ + : "=m" ((rw)->lock) \ + : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \ + "m" ((rw)->lock) : "2", "3", "cc", "memory" ) +#endif /* __s390x__ */ + +#ifndef __s390x__ +#define _raw_write_unlock(rw) \ + asm volatile(" slr 3,3\n" /* new lock value = 0 */ \ + " j 1f\n" \ + "0: diag 0,0,68\n" \ + "1: lhi 2,1\n" \ + " sll 2,31\n" /* old lock value must be 0x80000000 */ \ + " cs 2,3,0(%1)\n" \ + " jl 0b" \ + : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ + "m" ((rw)->lock) : "2", "3", "cc", "memory" ) +#else /* __s390x__ */ +#define _raw_write_unlock(rw) \ + asm volatile(" slgr 3,3\n" /* new lock value = 0 */ \ + " j 1f\n" \ + "0: " __DIAG44_INSN " 0,%2\n" \ + "1: llihh 2,0x8000\n" /* old lock value must be 0x8..0 */\ + " csg 2,3,0(%1)\n" \ + " jl 0b" \ + : "=m" ((rw)->lock) \ + : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \ + "m" ((rw)->lock) : "2", "3", "cc", "memory" ) +#endif /* __s390x__ */ + +#define _raw_read_trylock(lock) generic_raw_read_trylock(lock) + +extern inline int _raw_write_trylock(rwlock_t *rw) { - if (likely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0)) - return 1; - return _raw_write_trylock_retry(rw); + unsigned long result, reg; + + __asm__ __volatile__( +#ifndef __s390x__ + " lhi %1,1\n" + " sll %1,31\n" + " cs %0,%1,0(%3)" +#else /* __s390x__ */ + " llihh %1,0x8000\n" + "0: csg %0,%1,0(%3)\n" +#endif /* __s390x__ */ + : "=d" (result), "=&d" (reg), "=m" (rw->lock) + : "a" (&rw->lock), "m" (rw->lock), "0" (0UL) + : "cc", "memory" ); + return result == 0; } #endif /* __ASM_SPINLOCK_H */ diff --git a/trunk/include/asm-sparc/unistd.h b/trunk/include/asm-sparc/unistd.h index aee17d7e2e44..58dba518239e 100644 --- a/trunk/include/asm-sparc/unistd.h +++ b/trunk/include/asm-sparc/unistd.h @@ -167,12 +167,12 @@ #define __NR_pciconfig_read 148 /* ENOSYS under SunOS */ #define __NR_pciconfig_write 149 /* ENOSYS under SunOS */ #define __NR_getsockname 150 /* Common */ -/* #define __NR_getmsg 151 SunOS Specific */ -/* #define __NR_putmsg 152 SunOS Specific */ +#define __NR_inotify_init 151 /* Linux specific */ +#define __NR_inotify_add_watch 152 /* Linux specific */ #define __NR_poll 153 /* Common */ #define __NR_getdents64 154 /* Linux specific */ #define __NR_fcntl64 155 /* Linux sparc32 Specific */ -/* #define __NR_getdirentires 156 SunOS Specific */ +#define __NR_inotify_rm_watch 156 /* Linux specific */ #define __NR_statfs 157 /* Common */ #define __NR_fstatfs 158 /* Common */ #define __NR_umount 159 /* Common */ diff --git a/trunk/include/asm-sparc64/unistd.h b/trunk/include/asm-sparc64/unistd.h index f59144c6b76a..51ec2879b881 100644 --- a/trunk/include/asm-sparc64/unistd.h +++ b/trunk/include/asm-sparc64/unistd.h @@ -167,12 +167,12 @@ #define __NR_pciconfig_read 148 /* ENOSYS under SunOS */ #define __NR_pciconfig_write 149 /* ENOSYS under SunOS */ #define __NR_getsockname 150 /* Common */ -/* #define __NR_getmsg 151 SunOS Specific */ -/* #define __NR_putmsg 152 SunOS Specific */ +#define __NR_inotify_init 151 /* Linux specific */ +#define __NR_inotify_add_watch 152 /* Linux specific */ #define __NR_poll 153 /* Common */ #define __NR_getdents64 154 /* Linux specific */ /* #define __NR_fcntl64 155 Linux sparc32 Specific */ -/* #define __NR_getdirentries 156 SunOS Specific */ +#define __NR_inotify_rm_watch 156 /* Linux specific */ #define __NR_statfs 157 /* Common */ #define __NR_fstatfs 158 /* Common */ #define __NR_umount 159 /* Common */ diff --git a/trunk/include/asm-v850/bitops.h b/trunk/include/asm-v850/bitops.h index 0e5c2f210872..7c4ecaf5151c 100644 --- a/trunk/include/asm-v850/bitops.h +++ b/trunk/include/asm-v850/bitops.h @@ -1,8 +1,8 @@ /* * include/asm-v850/bitops.h -- Bit operations * - * Copyright (C) 2001,02,03,04,05 NEC Electronics Corporation - * Copyright (C) 2001,02,03,04,05 Miles Bader + * Copyright (C) 2001,02,03,04 NEC Electronics Corporation + * Copyright (C) 2001,02,03,04 Miles Bader * Copyright (C) 1992 Linus Torvalds. * * This file is subject to the terms and conditions of the GNU General @@ -157,7 +157,7 @@ extern __inline__ int __test_bit (int nr, const void *addr) #define find_first_zero_bit(addr, size) \ find_next_zero_bit ((addr), (size), 0) -extern __inline__ int find_next_zero_bit(const void *addr, int size, int offset) +extern __inline__ int find_next_zero_bit (void *addr, int size, int offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; diff --git a/trunk/include/asm-v850/cache.h b/trunk/include/asm-v850/cache.h index cbf9096e8517..027f8c9090cd 100644 --- a/trunk/include/asm-v850/cache.h +++ b/trunk/include/asm-v850/cache.h @@ -1,8 +1,8 @@ /* * include/asm-v850/cache.h -- Cache operations * - * Copyright (C) 2001,05 NEC Corporation - * Copyright (C) 2001,05 Miles Bader + * Copyright (C) 2001 NEC Corporation + * Copyright (C) 2001 Miles Bader * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -20,9 +20,6 @@ #ifndef L1_CACHE_BYTES /* This processor has no cache, so just choose an arbitrary value. */ #define L1_CACHE_BYTES 16 -#define L1_CACHE_SHIFT 4 #endif -#define L1_CACHE_SHIFT_MAX L1_CACHE_SHIFT - #endif /* __V850_CACHE_H__ */ diff --git a/trunk/include/asm-v850/io.h b/trunk/include/asm-v850/io.h index cc364fcbec10..bb5efd1b4b7d 100644 --- a/trunk/include/asm-v850/io.h +++ b/trunk/include/asm-v850/io.h @@ -1,8 +1,8 @@ /* * include/asm-v850/io.h -- Misc I/O operations * - * Copyright (C) 2001,02,03,04,05 NEC Electronics Corporation - * Copyright (C) 2001,02,03,04,05 Miles Bader + * Copyright (C) 2001,02,03,04 NEC Electronics Corporation + * Copyright (C) 2001,02,03,04 Miles Bader * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -27,12 +27,12 @@ #define readw_relaxed(a) readw(a) #define readl_relaxed(a) readl(a) -#define writeb(val, addr) \ - (void)((*(volatile unsigned char *) (addr)) = (val)) -#define writew(val, addr) \ - (void)((*(volatile unsigned short *) (addr)) = (val)) -#define writel(val, addr) \ - (void)((*(volatile unsigned int *) (addr)) = (val)) +#define writeb(b, addr) \ + (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b, addr) \ + (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b, addr) \ + (void)((*(volatile unsigned int *) (addr)) = (b)) #define __raw_readb readb #define __raw_readw readw @@ -96,22 +96,11 @@ outsl (unsigned long port, const void *src, unsigned long count) outl (*p++, port); } - -/* Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to - long before casting it to a pointer to avoid compiler warnings. */ -#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr)) -#define iounmap(addr) ((void)0) - -#define ioremap_nocache(physaddr, size) ioremap (physaddr, size) -#define ioremap_writethrough(physaddr, size) ioremap (physaddr, size) -#define ioremap_fullcache(physaddr, size) ioremap (physaddr, size) - -#define ioread8(addr) readb (addr) -#define ioread16(addr) readw (addr) -#define ioread32(addr) readl (addr) -#define iowrite8(val, addr) writeb (val, addr) -#define iowrite16(val, addr) writew (val, addr) -#define iowrite32(val, addr) writel (val, addr) +#define iounmap(addr) ((void)0) +#define ioremap(physaddr, size) (physaddr) +#define ioremap_nocache(physaddr, size) (physaddr) +#define ioremap_writethrough(physaddr, size) (physaddr) +#define ioremap_fullcache(physaddr, size) (physaddr) #define mmiowb() diff --git a/trunk/include/asm-v850/page.h b/trunk/include/asm-v850/page.h index d6091622935d..06085b0c043e 100644 --- a/trunk/include/asm-v850/page.h +++ b/trunk/include/asm-v850/page.h @@ -1,8 +1,8 @@ /* * include/asm-v850/page.h -- VM ops * - * Copyright (C) 2001,02,03,05 NEC Electronics Corporation - * Copyright (C) 2001,02,03,05 Miles Bader + * Copyright (C) 2001,02,03 NEC Electronics Corporation + * Copyright (C) 2001,02,03 Miles Bader * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -132,7 +132,6 @@ extern __inline__ int get_order (unsigned long size) #define pfn_to_page(pfn) virt_to_page (pfn_to_virt (pfn)) #define page_to_pfn(page) virt_to_pfn (page_to_virt (page)) -#define pfn_valid(pfn) ((pfn) < max_mapnr) #define virt_addr_valid(kaddr) \ (((void *)(kaddr) >= (void *)PAGE_OFFSET) && MAP_NR (kaddr) < max_mapnr) diff --git a/trunk/include/asm-v850/pci.h b/trunk/include/asm-v850/pci.h index 4581826e1cac..8e79be0fe99d 100644 --- a/trunk/include/asm-v850/pci.h +++ b/trunk/include/asm-v850/pci.h @@ -1,8 +1,8 @@ /* * include/asm-v850/pci.h -- PCI support * - * Copyright (C) 2001,02,05 NEC Corporation - * Copyright (C) 2001,02,05 Miles Bader + * Copyright (C) 2001,02 NEC Corporation + * Copyright (C) 2001,02 Miles Bader * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -48,12 +48,12 @@ pci_unmap_single (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size, perform a pci_dma_sync_for_device, and then the device again owns the buffer. */ extern void -pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr, - size_t size, int dir); +pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr, size_t size, + int dir); extern void -pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr, - size_t size, int dir); +pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr, size_t size, + int dir); /* Do multiple DMA mappings at once. */ @@ -65,28 +65,6 @@ extern void pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len, int dir); -/* SG-list versions of pci_dma_sync functions. */ -extern void -pci_dma_sync_sg_for_cpu (struct pci_dev *dev, - struct scatterlist *sg, int sg_len, - int dir); -extern void -pci_dma_sync_sg_for_device (struct pci_dev *dev, - struct scatterlist *sg, int sg_len, - int dir); - -#define pci_map_page(dev, page, offs, size, dir) \ - pci_map_single(dev, (page_address(page) + (offs)), size, dir) -#define pci_unmap_page(dev,addr,sz,dir) \ - pci_unmap_single(dev, addr, sz, dir) - -/* Test for pci_map_single or pci_map_page having generated an error. */ -static inline int -pci_dma_mapping_error (dma_addr_t dma_addr) -{ - return dma_addr == 0; -} - /* Allocate and map kernel buffer using consistent mode DMA for PCI device. Returns non-NULL cpu-view pointer to the buffer if successful and sets *DMA_ADDR to the pci side dma address as well, @@ -113,9 +91,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); -extern void pci_iounmap (struct pci_dev *dev, void __iomem *addr); - static inline void pcibios_add_platform_entries(struct pci_dev *dev) { } diff --git a/trunk/include/asm-v850/pgtable.h b/trunk/include/asm-v850/pgtable.h index 3cf8775ce85f..76e380e481e9 100644 --- a/trunk/include/asm-v850/pgtable.h +++ b/trunk/include/asm-v850/pgtable.h @@ -23,8 +23,6 @@ #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) -static inline int pte_file (pte_t pte) { return 0; } - /* These mean nothing to !CONFIG_MMU. */ #define PAGE_NONE __pgprot(0) diff --git a/trunk/include/asm-v850/v850e2_cache.h b/trunk/include/asm-v850/v850e2_cache.h index 87edf0d311d5..61acda1023e8 100644 --- a/trunk/include/asm-v850/v850e2_cache.h +++ b/trunk/include/asm-v850/v850e2_cache.h @@ -2,8 +2,8 @@ * include/asm-v850/v850e2_cache_cache.h -- Cache control for V850E2 * cache memories * - * Copyright (C) 2003,05 NEC Electronics Corporation - * Copyright (C) 2003,05 Miles Bader + * Copyright (C) 2003 NEC Electronics Corporation + * Copyright (C) 2003 Miles Bader * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -69,7 +69,6 @@ /* For */ #define L1_CACHE_BYTES V850E2_CACHE_LINE_SIZE -#define L1_CACHE_SHIFT V850E2_CACHE_LINE_SIZE_BITS #endif /* __V850_V850E2_CACHE_H__ */ diff --git a/trunk/include/linux/fs.h b/trunk/include/linux/fs.h index f9adf75fd9b4..0f53e0124941 100644 --- a/trunk/include/linux/fs.h +++ b/trunk/include/linux/fs.h @@ -697,13 +697,11 @@ extern struct list_head file_lock_list; #include extern int fcntl_getlk(struct file *, struct flock __user *); -extern int fcntl_setlk(unsigned int, struct file *, unsigned int, - struct flock __user *); +extern int fcntl_setlk(struct file *, unsigned int, struct flock __user *); #if BITS_PER_LONG == 32 extern int fcntl_getlk64(struct file *, struct flock64 __user *); -extern int fcntl_setlk64(unsigned int, struct file *, unsigned int, - struct flock64 __user *); +extern int fcntl_setlk64(struct file *, unsigned int, struct flock64 __user *); #endif extern void send_sigio(struct fown_struct *fown, int fd, int band); diff --git a/trunk/include/linux/ftape.h b/trunk/include/linux/ftape.h index 72faeec9f6e1..c6b38d5b9186 100644 --- a/trunk/include/linux/ftape.h +++ b/trunk/include/linux/ftape.h @@ -165,7 +165,7 @@ typedef union { # undef CONFIG_FT_FDC_DMA # define CONFIG_FT_FDC_DMA 2 # endif -#elif defined(CONFIG_FT_ALT_FDC) /* CONFIG_FT_MACH2 */ +#elif CONFIG_FT_ALT_FDC == 1 /* CONFIG_FT_MACH2 */ # if CONFIG_FT_FDC_BASE == 0 # undef CONFIG_FT_FDC_BASE # define CONFIG_FT_FDC_BASE 0x370 diff --git a/trunk/include/linux/mbcache.h b/trunk/include/linux/mbcache.h index 9263d2db2d67..8e5a10410a30 100644 --- a/trunk/include/linux/mbcache.h +++ b/trunk/include/linux/mbcache.h @@ -29,7 +29,7 @@ struct mb_cache_op { struct mb_cache * mb_cache_create(const char *, struct mb_cache_op *, size_t, int, int); -void mb_cache_shrink(struct block_device *); +void mb_cache_shrink(struct mb_cache *, struct block_device *); void mb_cache_destroy(struct mb_cache *); /* Functions on cache entries */ diff --git a/trunk/include/linux/pci_ids.h b/trunk/include/linux/pci_ids.h index bc4cc10fabe9..d2ad2c4f835a 100644 --- a/trunk/include/linux/pci_ids.h +++ b/trunk/include/linux/pci_ids.h @@ -1020,7 +1020,6 @@ #define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 #define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 #define PCI_DEVICE_ID_PLX_R753 0x1152 -#define PCI_DEVICE_ID_PLX_OLITEC 0x1187 #define PCI_DEVICE_ID_PLX_9030 0x9030 #define PCI_DEVICE_ID_PLX_9050 0x9050 #define PCI_DEVICE_ID_PLX_9060 0x9060 diff --git a/trunk/include/linux/serial_core.h b/trunk/include/linux/serial_core.h index f6fca8f2f3ca..30b64f3534f4 100644 --- a/trunk/include/linux/serial_core.h +++ b/trunk/include/linux/serial_core.h @@ -104,7 +104,7 @@ #define PORT_MPSC 63 /* TXX9 type number */ -#define PORT_TXX9 64 +#define PORT_TXX9 64 /* NEC VR4100 series SIU/DSIU */ #define PORT_VR41XX_SIU 65 diff --git a/trunk/include/linux/slab.h b/trunk/include/linux/slab.h index 80b2dfde2e80..4c8e552471b0 100644 --- a/trunk/include/linux/slab.h +++ b/trunk/include/linux/slab.h @@ -111,7 +111,7 @@ static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, int flags, int n { return kmem_cache_alloc(cachep, flags); } -static inline void *kmalloc_node(size_t size, unsigned int __nocast flags, int node) +static inline void *kmalloc_node(size_t size, int flags, int node) { return kmalloc(size, flags); } diff --git a/trunk/include/linux/sysctl.h b/trunk/include/linux/sysctl.h index e82be96d4906..bfbbe94b297d 100644 --- a/trunk/include/linux/sysctl.h +++ b/trunk/include/linux/sysctl.h @@ -145,7 +145,6 @@ enum KERN_BOOTLOADER_TYPE=67, /* int: boot loader type */ KERN_RANDOMIZE=68, /* int: randomize virtual address space */ KERN_SETUID_DUMPABLE=69, /* int: behaviour of dumps for setuid core */ - KERN_SPIN_RETRY=70, /* int: number of spinlock retries */ }; diff --git a/trunk/include/linux/watchdog.h b/trunk/include/linux/watchdog.h index 1192ed8f4fe8..88ba0d29f8c8 100644 --- a/trunk/include/linux/watchdog.h +++ b/trunk/include/linux/watchdog.h @@ -47,14 +47,4 @@ struct watchdog_info { #define WDIOS_ENABLECARD 0x0002 /* Turn on the watchdog timer */ #define WDIOS_TEMPPANIC 0x0004 /* Kernel panic on temperature trip */ -#ifdef __KERNEL__ - -#ifdef CONFIG_WATCHDOG_NOWAYOUT -#define WATCHDOG_NOWAYOUT 1 -#else -#define WATCHDOG_NOWAYOUT 0 -#endif - -#endif /* __KERNEL__ */ - #endif /* ifndef _LINUX_WATCHDOG_H */ diff --git a/trunk/include/media/tveeprom.h b/trunk/include/media/tveeprom.h index 854a2c2f105b..5c4fe30e8d1d 100644 --- a/trunk/include/media/tveeprom.h +++ b/trunk/include/media/tveeprom.h @@ -24,3 +24,4 @@ void tveeprom_hauppauge_analog(struct tveeprom *tvee, unsigned char *eeprom_data); int tveeprom_read(struct i2c_client *c, unsigned char *eedata, int len); +int tveeprom_dump(unsigned char *eedata, int len); diff --git a/trunk/include/sound/vx_core.h b/trunk/include/sound/vx_core.h index 7a60a3888667..a7e29933f2d0 100644 --- a/trunk/include/sound/vx_core.h +++ b/trunk/include/sound/vx_core.h @@ -233,37 +233,37 @@ irqreturn_t snd_vx_irq_handler(int irq, void *dev, struct pt_regs *regs); /* * lowlevel functions */ -static inline int vx_test_and_ack(vx_core_t *chip) +inline static int vx_test_and_ack(vx_core_t *chip) { snd_assert(chip->ops->test_and_ack, return -ENXIO); return chip->ops->test_and_ack(chip); } -static inline void vx_validate_irq(vx_core_t *chip, int enable) +inline static void vx_validate_irq(vx_core_t *chip, int enable) { snd_assert(chip->ops->validate_irq, return); chip->ops->validate_irq(chip, enable); } -static inline unsigned char snd_vx_inb(vx_core_t *chip, int reg) +inline static unsigned char snd_vx_inb(vx_core_t *chip, int reg) { snd_assert(chip->ops->in8, return 0); return chip->ops->in8(chip, reg); } -static inline unsigned int snd_vx_inl(vx_core_t *chip, int reg) +inline static unsigned int snd_vx_inl(vx_core_t *chip, int reg) { snd_assert(chip->ops->in32, return 0); return chip->ops->in32(chip, reg); } -static inline void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val) +inline static void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val) { snd_assert(chip->ops->out8, return); chip->ops->out8(chip, reg, val); } -static inline void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val) +inline static void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val) { snd_assert(chip->ops->out32, return); chip->ops->out32(chip, reg, val); @@ -303,14 +303,14 @@ int snd_vx_check_reg_bit(vx_core_t *chip, int reg, int mask, int bit, int time); /* * pseudo-DMA transfer */ -static inline void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime, +inline static void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime, vx_pipe_t *pipe, int count) { snd_assert(chip->ops->dma_write, return); chip->ops->dma_write(chip, runtime, pipe, count); } -static inline void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime, +inline static void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime, vx_pipe_t *pipe, int count) { snd_assert(chip->ops->dma_read, return); diff --git a/trunk/init/Kconfig b/trunk/init/Kconfig index 05a75c4f5ce2..75755ef50c89 100644 --- a/trunk/init/Kconfig +++ b/trunk/init/Kconfig @@ -231,7 +231,7 @@ config CPUSETS bool "Cpuset support" depends on SMP help - This option will let you create and manage CPUSETs which + This options will let you create and manage CPUSET's which allow dynamically partitioning a system into sets of CPUs and Memory Nodes and assigning tasks to run only within those sets. This is primarily useful on large SMP or NUMA systems. diff --git a/trunk/kernel/capability.c b/trunk/kernel/capability.c index 8986a37a67ea..64db1ee820c2 100644 --- a/trunk/kernel/capability.c +++ b/trunk/kernel/capability.c @@ -31,14 +31,8 @@ static DEFINE_SPINLOCK(task_capability_lock); * uninteresting and/or not to be changed. */ -/** +/* * sys_capget - get the capabilities of a given process. - * @header: pointer to struct that contains capability version and - * target pid data - * @dataptr: pointer to struct that contains the effective, permitted, - * and inheritable capabilities that are returned - * - * Returns 0 on success and < 0 on error. */ asmlinkage long sys_capget(cap_user_header_t header, cap_user_data_t dataptr) { @@ -147,14 +141,8 @@ static inline int cap_set_all(kernel_cap_t *effective, return ret; } -/** - * sys_capset - set capabilities for a process or a group of processes - * @header: pointer to struct that contains capability version and - * target pid data - * @data: pointer to struct that contains the effective, permitted, - * and inheritable capabilities - * - * Set capabilities for a given process, all processes, or all +/* + * sys_capset - set capabilities for a given process, all processes, or all * processes in a given process group. * * The restrictions on setting capabilities are specified as: @@ -164,8 +152,6 @@ static inline int cap_set_all(kernel_cap_t *effective, * I: any raised capabilities must be a subset of the (old current) permitted * P: any raised capabilities must be a subset of the (old current) permitted * E: must be set to a subset of (new target) permitted - * - * Returns 0 on success and < 0 on error. */ asmlinkage long sys_capset(cap_user_header_t header, const cap_user_data_t data) { diff --git a/trunk/kernel/cpuset.c b/trunk/kernel/cpuset.c index 805fb9097318..984c0bf3807f 100644 --- a/trunk/kernel/cpuset.c +++ b/trunk/kernel/cpuset.c @@ -1440,10 +1440,10 @@ void __init cpuset_init_smp(void) /** * cpuset_fork - attach newly forked task to its parents cpuset. - * @tsk: pointer to task_struct of forking parent process. + * @p: pointer to task_struct of forking parent process. * * Description: By default, on fork, a task inherits its - * parent's cpuset. The pointer to the shared cpuset is + * parents cpuset. The pointer to the shared cpuset is * automatically copied in fork.c by dup_task_struct(). * This cpuset_fork() routine need only increment the usage * counter in that cpuset. @@ -1471,6 +1471,7 @@ void cpuset_fork(struct task_struct *tsk) * by the cpuset_sem semaphore. If you don't hold cpuset_sem, * then a zero cpuset use count is a license to any other task to * nuke the cpuset immediately. + * **/ void cpuset_exit(struct task_struct *tsk) @@ -1520,9 +1521,7 @@ void cpuset_init_current_mems_allowed(void) current->mems_allowed = NODE_MASK_ALL; } -/** - * cpuset_update_current_mems_allowed - update mems parameters to new values - * +/* * If the current tasks cpusets mems_allowed changed behind our backs, * update current->mems_allowed and mems_generation to the new value. * Do not call this routine if in_interrupt(). @@ -1541,20 +1540,13 @@ void cpuset_update_current_mems_allowed(void) } } -/** - * cpuset_restrict_to_mems_allowed - limit nodes to current mems_allowed - * @nodes: pointer to a node bitmap that is and-ed with mems_allowed - */ void cpuset_restrict_to_mems_allowed(unsigned long *nodes) { bitmap_and(nodes, nodes, nodes_addr(current->mems_allowed), MAX_NUMNODES); } -/** - * cpuset_zonelist_valid_mems_allowed - check zonelist vs. curremt mems_allowed - * @zl: the zonelist to be checked - * +/* * Are any of the nodes on zonelist zl allowed in current->mems_allowed? */ int cpuset_zonelist_valid_mems_allowed(struct zonelist *zl) @@ -1570,12 +1562,8 @@ int cpuset_zonelist_valid_mems_allowed(struct zonelist *zl) return 0; } -/** - * cpuset_zone_allowed - is zone z allowed in current->mems_allowed - * @z: zone in question - * - * Is zone z allowed in current->mems_allowed, or is - * the CPU in interrupt context? (zone is always allowed in this case) +/* + * Is 'current' valid, and is zone z allowed in current->mems_allowed? */ int cpuset_zone_allowed(struct zone *z) { diff --git a/trunk/kernel/crash_dump.c b/trunk/kernel/crash_dump.c index 334c37f5218a..459ba49e376a 100644 --- a/trunk/kernel/crash_dump.c +++ b/trunk/kernel/crash_dump.c @@ -18,16 +18,7 @@ /* Stores the physical address of elf header of crash image. */ unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; -/** - * copy_oldmem_page - copy one page from "oldmem" - * @pfn: page frame number to be copied - * @buf: target memory address for the copy; this can be in kernel address - * space or user address space (see @userbuf) - * @csize: number of bytes to copy - * @offset: offset in bytes into the page (based on pfn) to begin the copy - * @userbuf: if set, @buf is in user address space, use copy_to_user(), - * otherwise @buf is in kernel address space, use memcpy(). - * +/* * Copy a page from "oldmem". For this page, there is no pte mapped * in the current kernel. We stitch up a pte, similar to kmap_atomic. */ diff --git a/trunk/kernel/itimer.c b/trunk/kernel/itimer.c index 7c1b25e25e47..a72cb0e5aa4b 100644 --- a/trunk/kernel/itimer.c +++ b/trunk/kernel/itimer.c @@ -112,11 +112,28 @@ asmlinkage long sys_getitimer(int which, struct itimerval __user *value) return error; } +/* + * Called with P->sighand->siglock held and P->signal->real_timer inactive. + * If interval is nonzero, arm the timer for interval ticks from now. + */ +static inline void it_real_arm(struct task_struct *p, unsigned long interval) +{ + p->signal->it_real_value = interval; /* XXX unnecessary field?? */ + if (interval == 0) + return; + if (interval > (unsigned long) LONG_MAX) + interval = LONG_MAX; + /* the "+ 1" below makes sure that the timer doesn't go off before + * the interval requested. This could happen if + * time requested % (usecs per jiffy) is more than the usecs left + * in the current jiffy */ + p->signal->real_timer.expires = jiffies + interval + 1; + add_timer(&p->signal->real_timer); +} void it_real_fn(unsigned long __data) { struct task_struct * p = (struct task_struct *) __data; - unsigned long inc = p->signal->it_real_incr; send_group_sig_info(SIGALRM, SEND_SIG_PRIV, p); @@ -124,23 +141,14 @@ void it_real_fn(unsigned long __data) * Now restart the timer if necessary. We don't need any locking * here because do_setitimer makes sure we have finished running * before it touches anything. - * Note, we KNOW we are (or should be) at a jiffie edge here so - * we don't need the +1 stuff. Also, we want to use the prior - * expire value so as to not "slip" a jiffie if we are late. - * Deal with requesting a time prior to "now" here rather than - * in add_timer. */ - if (!inc) - return; - while (time_before_eq(p->signal->real_timer.expires, jiffies)) - p->signal->real_timer.expires += inc; - add_timer(&p->signal->real_timer); + it_real_arm(p, p->signal->it_real_incr); } int do_setitimer(int which, struct itimerval *value, struct itimerval *ovalue) { struct task_struct *tsk = current; - unsigned long val, interval, expires; + unsigned long val, interval; cputime_t cval, cinterval, nval, ninterval; switch (which) { @@ -156,10 +164,7 @@ int do_setitimer(int which, struct itimerval *value, struct itimerval *ovalue) } tsk->signal->it_real_incr = timeval_to_jiffies(&value->it_interval); - expires = timeval_to_jiffies(&value->it_value); - if (expires) - mod_timer(&tsk->signal->real_timer, - jiffies + 1 + expires); + it_real_arm(tsk, timeval_to_jiffies(&value->it_value)); spin_unlock_irq(&tsk->sighand->siglock); if (ovalue) { jiffies_to_timeval(val, &ovalue->it_value); diff --git a/trunk/kernel/power/smp.c b/trunk/kernel/power/smp.c index 911fc62b8225..bbe23079c62c 100644 --- a/trunk/kernel/power/smp.c +++ b/trunk/kernel/power/smp.c @@ -38,7 +38,7 @@ void disable_nonboot_cpus(void) } printk("Error taking cpu %d down: %d\n", cpu, error); } - BUG_ON(raw_smp_processor_id() != 0); + BUG_ON(smp_processor_id() != 0); if (error) panic("cpus not sleeping"); } diff --git a/trunk/kernel/sys.c b/trunk/kernel/sys.c index 8f255259ef9e..a74039036fb4 100644 --- a/trunk/kernel/sys.c +++ b/trunk/kernel/sys.c @@ -371,6 +371,7 @@ void kernel_restart(char *cmd) { notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd); system_state = SYSTEM_RESTART; + device_suspend(PMSG_FREEZE); device_shutdown(); if (!cmd) { printk(KERN_EMERG "Restarting system.\n"); diff --git a/trunk/kernel/sysctl.c b/trunk/kernel/sysctl.c index 3e0bbee549ea..e60b9c36f1f0 100644 --- a/trunk/kernel/sysctl.c +++ b/trunk/kernel/sysctl.c @@ -114,7 +114,6 @@ extern int unaligned_enabled; extern int sysctl_ieee_emulation_warnings; #endif extern int sysctl_userprocess_debug; -extern int spin_retry; #endif extern int sysctl_hz_timer; @@ -648,16 +647,7 @@ static ctl_table kern_table[] = { .mode = 0644, .proc_handler = &proc_dointvec, }, -#if defined(CONFIG_ARCH_S390) - { - .ctl_name = KERN_SPIN_RETRY, - .procname = "spin_retry", - .data = &spin_retry, - .maxlen = sizeof (int), - .mode = 0644, - .proc_handler = &proc_dointvec, - }, -#endif + { .ctl_name = 0 } }; diff --git a/trunk/kernel/time.c b/trunk/kernel/time.c index dd5ae1162a8f..d4335c1c884c 100644 --- a/trunk/kernel/time.c +++ b/trunk/kernel/time.c @@ -128,7 +128,7 @@ asmlinkage long sys_gettimeofday(struct timeval __user *tv, struct timezone __us * as real UNIX machines always do it. This avoids all headaches about * daylight saving times and warping kernel clocks. */ -static inline void warp_clock(void) +inline static void warp_clock(void) { write_seqlock_irq(&xtime_lock); wall_to_monotonic.tv_sec -= sys_tz.tz_minuteswest * 60; diff --git a/trunk/lib/Makefile b/trunk/lib/Makefile index f28d9031303c..beed1585294c 100644 --- a/trunk/lib/Makefile +++ b/trunk/lib/Makefile @@ -5,11 +5,11 @@ lib-y := errno.o ctype.o string.o vsprintf.o cmdline.o \ bust_spinlocks.o rbtree.o radix-tree.o dump_stack.o \ idr.o div64.o int_sqrt.o bitmap.o extable.o prio_tree.o \ - sha1.o + sha1.o halfmd4.o lib-y += kobject.o kref.o kobject_uevent.o klist.o -obj-y += sort.o parser.o halfmd4.o +obj-y += sort.o parser.o ifeq ($(CONFIG_DEBUG_KOBJECT),y) CFLAGS_kobject.o += -DDEBUG diff --git a/trunk/mm/madvise.c b/trunk/mm/madvise.c index c8c01a12fea4..73180a22877e 100644 --- a/trunk/mm/madvise.c +++ b/trunk/mm/madvise.c @@ -83,6 +83,9 @@ static long madvise_willneed(struct vm_area_struct * vma, { struct file *file = vma->vm_file; + if (!file) + return -EBADF; + if (file->f_mapping->a_ops->get_xip_page) { /* no bad return value, but ignore advice */ return 0; @@ -137,16 +140,11 @@ static long madvise_dontneed(struct vm_area_struct * vma, return 0; } -static long -madvise_vma(struct vm_area_struct *vma, struct vm_area_struct **prev, - unsigned long start, unsigned long end, int behavior) +static long madvise_vma(struct vm_area_struct *vma, struct vm_area_struct **prev, + unsigned long start, unsigned long end, int behavior) { - struct file *filp = vma->vm_file; long error = -EBADF; - if (!filp) - goto out; - switch (behavior) { case MADV_NORMAL: case MADV_SEQUENTIAL: @@ -167,7 +165,6 @@ madvise_vma(struct vm_area_struct *vma, struct vm_area_struct **prev, break; } -out: return error; } diff --git a/trunk/mm/memory.c b/trunk/mm/memory.c index 6fe77acbc1cd..beabdefa6254 100644 --- a/trunk/mm/memory.c +++ b/trunk/mm/memory.c @@ -776,8 +776,8 @@ unsigned long zap_page_range(struct vm_area_struct *vma, unsigned long address, * Do a quick page-table lookup for a single page. * mm->page_table_lock must be held. */ -static struct page *__follow_page(struct mm_struct *mm, unsigned long address, - int read, int write, int accessed) +static struct page * +__follow_page(struct mm_struct *mm, unsigned long address, int read, int write) { pgd_t *pgd; pud_t *pud; @@ -818,11 +818,9 @@ static struct page *__follow_page(struct mm_struct *mm, unsigned long address, pfn = pte_pfn(pte); if (pfn_valid(pfn)) { page = pfn_to_page(pfn); - if (accessed) { - if (write && !pte_dirty(pte) &&!PageDirty(page)) - set_page_dirty(page); - mark_page_accessed(page); - } + if (write && !pte_dirty(pte) && !PageDirty(page)) + set_page_dirty(page); + mark_page_accessed(page); return page; } } @@ -831,19 +829,16 @@ static struct page *__follow_page(struct mm_struct *mm, unsigned long address, return NULL; } -inline struct page * +struct page * follow_page(struct mm_struct *mm, unsigned long address, int write) { - return __follow_page(mm, address, 0, write, 1); + return __follow_page(mm, address, /*read*/0, write); } -/* - * check_user_page_readable() can be called frm niterrupt context by oprofile, - * so we need to avoid taking any non-irq-safe locks - */ -int check_user_page_readable(struct mm_struct *mm, unsigned long address) +int +check_user_page_readable(struct mm_struct *mm, unsigned long address) { - return __follow_page(mm, address, 1, 0, 0) != NULL; + return __follow_page(mm, address, /*read*/1, /*write*/0) != NULL; } EXPORT_SYMBOL(check_user_page_readable); diff --git a/trunk/mm/mempolicy.c b/trunk/mm/mempolicy.c index 1694845526be..cb41c31e7c87 100644 --- a/trunk/mm/mempolicy.c +++ b/trunk/mm/mempolicy.c @@ -1138,11 +1138,11 @@ void mpol_free_shared_policy(struct shared_policy *p) while (next) { n = rb_entry(next, struct sp_node, nd); next = rb_next(&n->nd); - rb_erase(&n->nd, &p->root); mpol_free(n->policy); kmem_cache_free(sn_cache, n); } spin_unlock(&p->lock); + p->root = RB_ROOT; } /* assumes fs == KERNEL_DS */ diff --git a/trunk/mm/page_alloc.c b/trunk/mm/page_alloc.c index 42bccfb8464d..1d6ba6a4b594 100644 --- a/trunk/mm/page_alloc.c +++ b/trunk/mm/page_alloc.c @@ -1861,6 +1861,7 @@ static void __init free_area_init_core(struct pglist_data *pgdat, unsigned long *zones_size, unsigned long *zholes_size) { unsigned long i, j; + const unsigned long zone_required_alignment = 1UL << (MAX_ORDER-1); int cpu, nid = pgdat->node_id; unsigned long zone_start_pfn = pgdat->node_start_pfn; @@ -1933,6 +1934,9 @@ static void __init free_area_init_core(struct pglist_data *pgdat, zone->zone_mem_map = pfn_to_page(zone_start_pfn); zone->zone_start_pfn = zone_start_pfn; + if ((zone_start_pfn) & (zone_required_alignment-1)) + printk(KERN_CRIT "BUG: wrong zone alignment, it will crash\n"); + memmap_init(size, nid, j, zone_start_pfn); zonetable_add(zone, nid, j, zone_start_pfn, size); diff --git a/trunk/net/core/pktgen.c b/trunk/net/core/pktgen.c index 8eb083b6041a..975d651312dc 100644 --- a/trunk/net/core/pktgen.c +++ b/trunk/net/core/pktgen.c @@ -363,7 +363,7 @@ struct pktgen_thread { * All Rights Reserved. * */ -static inline s64 divremdi3(s64 x, s64 y, int type) +inline static s64 divremdi3(s64 x, s64 y, int type) { u64 a = (x < 0) ? -x : x; u64 b = (y < 0) ? -y : y; diff --git a/trunk/net/core/sock.c b/trunk/net/core/sock.c index 12f6d9a2a522..8b35ccdc2b3b 100644 --- a/trunk/net/core/sock.c +++ b/trunk/net/core/sock.c @@ -206,14 +206,13 @@ int sock_setsockopt(struct socket *sock, int level, int optname, */ #ifdef SO_DONTLINGER /* Compatibility item... */ - if (optname == SO_DONTLINGER) { - lock_sock(sk); - sock_reset_flag(sk, SOCK_LINGER); - release_sock(sk); - return 0; + switch (optname) { + case SO_DONTLINGER: + sock_reset_flag(sk, SOCK_LINGER); + return 0; } -#endif - +#endif + if(optlen #include -#include #include #include + /* This is a maximally equidistributed combined Tausworthe generator based on code from GNU Scientific Library 1.5 (30 Jun 2004) @@ -153,38 +153,3 @@ int net_ratelimit(void) EXPORT_SYMBOL(net_random); EXPORT_SYMBOL(net_ratelimit); EXPORT_SYMBOL(net_srandom); - -/* - * Convert an ASCII string to binary IP. - * This is outside of net/ipv4/ because various code that uses IP addresses - * is otherwise not dependent on the TCP/IP stack. - */ - -__u32 in_aton(const char *str) -{ - unsigned long l; - unsigned int val; - int i; - - l = 0; - for (i = 0; i < 4; i++) - { - l <<= 8; - if (*str != '\0') - { - val = 0; - while (*str != '\0' && *str != '.') - { - val *= 10; - val += *str - '0'; - str++; - } - l |= val; - if (*str != '\0') - str++; - } - } - return(htonl(l)); -} - -EXPORT_SYMBOL(in_aton); diff --git a/trunk/net/ipv4/Kconfig b/trunk/net/ipv4/Kconfig index 0b3d9f1d8069..fc561c0ae8e2 100644 --- a/trunk/net/ipv4/Kconfig +++ b/trunk/net/ipv4/Kconfig @@ -124,7 +124,7 @@ config IP_ROUTE_MULTIPATH config IP_ROUTE_MULTIPATH_CACHED bool "IP: equal cost multipath with caching support (EXPERIMENTAL)" - depends on IP_ROUTE_MULTIPATH + depends on: IP_ROUTE_MULTIPATH help Normally, equal cost multipath routing is not supported by the routing cache. If you say Y here, alternative routes are cached diff --git a/trunk/net/ipv4/Makefile b/trunk/net/ipv4/Makefile index 55dc6cca1e7b..5718cdb3a61e 100644 --- a/trunk/net/ipv4/Makefile +++ b/trunk/net/ipv4/Makefile @@ -2,7 +2,7 @@ # Makefile for the Linux TCP/IP (INET) layer. # -obj-y := route.o inetpeer.o protocol.o \ +obj-y := utils.o route.o inetpeer.o protocol.o \ ip_input.o ip_fragment.o ip_forward.o ip_options.o \ ip_output.o ip_sockglue.o \ tcp.o tcp_input.o tcp_output.o tcp_timer.o tcp_ipv4.o \ diff --git a/trunk/net/ipv4/netfilter/ip_conntrack_core.c b/trunk/net/ipv4/netfilter/ip_conntrack_core.c index 86f04e41dd8e..63bf88264980 100644 --- a/trunk/net/ipv4/netfilter/ip_conntrack_core.c +++ b/trunk/net/ipv4/netfilter/ip_conntrack_core.c @@ -510,7 +510,7 @@ init_conntrack(const struct ip_conntrack_tuple *tuple, /* Welcome, Mr. Bond. We've been expecting you... */ __set_bit(IPS_EXPECTED_BIT, &conntrack->status); conntrack->master = exp->master; -#ifdef CONFIG_IP_NF_CONNTRACK_MARK +#if CONFIG_IP_NF_CONNTRACK_MARK conntrack->mark = exp->master->mark; #endif nf_conntrack_get(&conntrack->master->ct_general); diff --git a/trunk/net/ipv4/utils.c b/trunk/net/ipv4/utils.c new file mode 100644 index 000000000000..6aecd7a43534 --- /dev/null +++ b/trunk/net/ipv4/utils.c @@ -0,0 +1,59 @@ +/* + * INET An implementation of the TCP/IP protocol suite for the LINUX + * operating system. INET is implemented using the BSD Socket + * interface as the means of communication with the user level. + * + * Various kernel-resident INET utility functions; mainly + * for format conversion and debugging output. + * + * Version: $Id: utils.c,v 1.8 2000/10/03 07:29:01 anton Exp $ + * + * Author: Fred N. van Kempen, + * + * Fixes: + * Alan Cox : verify_area check. + * Alan Cox : removed old debugging. + * Andi Kleen : add net_ratelimit() + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include + +/* + * Convert an ASCII string to binary IP. + */ + +__u32 in_aton(const char *str) +{ + unsigned long l; + unsigned int val; + int i; + + l = 0; + for (i = 0; i < 4; i++) + { + l <<= 8; + if (*str != '\0') + { + val = 0; + while (*str != '\0' && *str != '.') + { + val *= 10; + val += *str - '0'; + str++; + } + l |= val; + if (*str != '\0') + str++; + } + } + return(htonl(l)); +} + +EXPORT_SYMBOL(in_aton); diff --git a/trunk/net/ipv6/ip6_output.c b/trunk/net/ipv6/ip6_output.c index ae652ca14bc9..1f2c2f9e353f 100644 --- a/trunk/net/ipv6/ip6_output.c +++ b/trunk/net/ipv6/ip6_output.c @@ -792,8 +792,13 @@ int ip6_dst_lookup(struct sock *sk, struct dst_entry **dst, struct flowi *fl) if (ipv6_addr_any(&fl->fl6_src)) { err = ipv6_get_saddr(*dst, &fl->fl6_dst, &fl->fl6_src); - if (err) + if (err) { +#if IP6_DEBUG >= 2 + printk(KERN_DEBUG "ip6_dst_lookup: " + "no available source address\n"); +#endif goto out_err_release; + } } return 0; diff --git a/trunk/sound/core/seq/oss/seq_oss_device.h b/trunk/sound/core/seq/oss/seq_oss_device.h index 973786758c55..da23c4db8dd5 100644 --- a/trunk/sound/core/seq/oss/seq_oss_device.h +++ b/trunk/sound/core/seq/oss/seq_oss_device.h @@ -158,21 +158,21 @@ void snd_seq_oss_readq_info_read(seq_oss_readq_t *q, snd_info_buffer_t *buf); #define is_nonblock_mode(mode) ((mode) & SNDRV_SEQ_OSS_FILE_NONBLOCK) /* dispatch event */ -static inline int +inline static int snd_seq_oss_dispatch(seq_oss_devinfo_t *dp, snd_seq_event_t *ev, int atomic, int hop) { return snd_seq_kernel_client_dispatch(dp->cseq, ev, atomic, hop); } /* ioctl */ -static inline int +inline static int snd_seq_oss_control(seq_oss_devinfo_t *dp, unsigned int type, void *arg) { return snd_seq_kernel_client_ctl(dp->cseq, type, arg); } /* fill the addresses in header */ -static inline void +inline static void snd_seq_oss_fill_addr(seq_oss_devinfo_t *dp, snd_seq_event_t *ev, int dest_client, int dest_port) { diff --git a/trunk/sound/core/seq/seq_memory.c b/trunk/sound/core/seq/seq_memory.c index 03acb2d519ba..00d841e82fbc 100644 --- a/trunk/sound/core/seq/seq_memory.c +++ b/trunk/sound/core/seq/seq_memory.c @@ -36,12 +36,12 @@ #define semaphore_of(fp) ((fp)->f_dentry->d_inode->i_sem) -static inline int snd_seq_pool_available(pool_t *pool) +inline static int snd_seq_pool_available(pool_t *pool) { return pool->total_elements - atomic_read(&pool->counter); } -static inline int snd_seq_output_ok(pool_t *pool) +inline static int snd_seq_output_ok(pool_t *pool) { return snd_seq_pool_available(pool) >= pool->room; } diff --git a/trunk/sound/core/seq/seq_midi_event.c b/trunk/sound/core/seq/seq_midi_event.c index 603b63716db6..df1e2bb39745 100644 --- a/trunk/sound/core/seq/seq_midi_event.c +++ b/trunk/sound/core/seq/seq_midi_event.c @@ -146,7 +146,7 @@ void snd_midi_event_free(snd_midi_event_t *dev) /* * initialize record */ -static inline void reset_encode(snd_midi_event_t *dev) +inline static void reset_encode(snd_midi_event_t *dev) { dev->read = 0; dev->qlen = 0; diff --git a/trunk/sound/drivers/serial-u16550.c b/trunk/sound/drivers/serial-u16550.c index 986df35fb829..964b97e70c84 100644 --- a/trunk/sound/drivers/serial-u16550.c +++ b/trunk/sound/drivers/serial-u16550.c @@ -168,7 +168,7 @@ typedef struct _snd_uart16550 { static snd_card_t *snd_serial_cards[SNDRV_CARDS] = SNDRV_DEFAULT_PTR; -static inline void snd_uart16550_add_timer(snd_uart16550_t *uart) +inline static void snd_uart16550_add_timer(snd_uart16550_t *uart) { if (! uart->timer_running) { /* timer 38600bps * 10bit * 16byte */ @@ -178,7 +178,7 @@ static inline void snd_uart16550_add_timer(snd_uart16550_t *uart) } } -static inline void snd_uart16550_del_timer(snd_uart16550_t *uart) +inline static void snd_uart16550_del_timer(snd_uart16550_t *uart) { if (uart->timer_running) { del_timer(&uart->buffer_timer); @@ -187,7 +187,7 @@ static inline void snd_uart16550_del_timer(snd_uart16550_t *uart) } /* This macro is only used in snd_uart16550_io_loop */ -static inline void snd_uart16550_buffer_output(snd_uart16550_t *uart) +inline static void snd_uart16550_buffer_output(snd_uart16550_t *uart) { unsigned short buff_out = uart->buff_out; if( uart->buff_in_count > 0 ) { @@ -579,7 +579,7 @@ static int snd_uart16550_output_close(snd_rawmidi_substream_t * substream) return 0; }; -static inline int snd_uart16550_buffer_can_write( snd_uart16550_t *uart, int Num ) +inline static int snd_uart16550_buffer_can_write( snd_uart16550_t *uart, int Num ) { if( uart->buff_in_count + Num < TX_BUFF_SIZE ) return 1; @@ -587,7 +587,7 @@ static inline int snd_uart16550_buffer_can_write( snd_uart16550_t *uart, int Num return 0; } -static inline int snd_uart16550_write_buffer(snd_uart16550_t *uart, unsigned char byte) +inline static int snd_uart16550_write_buffer(snd_uart16550_t *uart, unsigned char byte) { unsigned short buff_in = uart->buff_in; if( uart->buff_in_count < TX_BUFF_SIZE ) { diff --git a/trunk/sound/isa/sb/emu8000_patch.c b/trunk/sound/isa/sb/emu8000_patch.c index 26e693078cb3..4afc4a1bc140 100644 --- a/trunk/sound/isa/sb/emu8000_patch.c +++ b/trunk/sound/isa/sb/emu8000_patch.c @@ -128,7 +128,7 @@ snd_emu8000_write_wait(emu8000_t *emu) * This is therefore much slower than need be, but is at least * working. */ -static inline void +inline static void write_word(emu8000_t *emu, int *offset, unsigned short data) { if (emu8000_reset_addr) { diff --git a/trunk/sound/isa/sb/sb_mixer.c b/trunk/sound/isa/sb/sb_mixer.c index ff4b59968027..cc5a2c6dec16 100644 --- a/trunk/sound/isa/sb/sb_mixer.c +++ b/trunk/sound/isa/sb/sb_mixer.c @@ -688,7 +688,7 @@ static struct sbmix_elem snd_als4000_ctl_3d_poweroff_switch = SB_SINGLE("3D PowerOff Switch", SB_ALS4000_3D_TIME_DELAY, 4, 0x01); static struct sbmix_elem snd_als4000_ctl_3d_delay = SB_SINGLE("3D Delay", SB_ALS4000_3D_TIME_DELAY, 0, 0x0f); -#ifdef NOT_AVAILABLE +#if NOT_AVAILABLE static struct sbmix_elem snd_als4000_ctl_fmdac = SB_SINGLE("FMDAC Switch (Option ?)", SB_ALS4000_FMDAC, 0, 0x01); static struct sbmix_elem snd_als4000_ctl_qsound = @@ -723,7 +723,7 @@ static struct sbmix_elem *snd_als4000_controls[] = { &snd_als4000_ctl_3d_output_ratio, &snd_als4000_ctl_3d_delay, &snd_als4000_ctl_3d_poweroff_switch, -#ifdef NOT_AVAILABLE +#if NOT_AVAILABLE &snd_als4000_ctl_fmdac, &snd_als4000_ctl_qsound, #endif diff --git a/trunk/sound/oss/dmasound/dmasound_awacs.c b/trunk/sound/oss/dmasound/dmasound_awacs.c index 2ceb46f1d40f..2704e1598add 100644 --- a/trunk/sound/oss/dmasound/dmasound_awacs.c +++ b/trunk/sound/oss/dmasound/dmasound_awacs.c @@ -1557,7 +1557,7 @@ static int awacs_sleep_notify(struct pmu_sleep_notifier *self, int when) /* All the burgundy functions: */ /* Waits for busy flag to clear */ -static inline void +inline static void awacs_burgundy_busy_wait(void) { int count = 50; /* > 2 samples at 44k1 */ @@ -1565,7 +1565,7 @@ awacs_burgundy_busy_wait(void) udelay(1) ; } -static inline void +inline static void awacs_burgundy_extend_wait(void) { int count = 50 ; /* > 2 samples at 44k1 */ diff --git a/trunk/sound/oss/pss.c b/trunk/sound/oss/pss.c index a617ccb40e00..3ed38765dcc4 100644 --- a/trunk/sound/oss/pss.c +++ b/trunk/sound/oss/pss.c @@ -714,7 +714,7 @@ static int __init attach_pss(struct address_info *hw_config) disable_all_emulations(); -#ifdef YOU_REALLY_WANT_TO_ALLOCATE_THESE_RESOURCES +#if YOU_REALLY_WANT_TO_ALLOCATE_THESE_RESOURCES if (sound_alloc_dma(hw_config->dma, "PSS")) { printk("pss.c: Can't allocate DMA channel.\n"); diff --git a/trunk/sound/pci/cmipci.c b/trunk/sound/pci/cmipci.c index 4725b4a010be..b4503385ea69 100644 --- a/trunk/sound/pci/cmipci.c +++ b/trunk/sound/pci/cmipci.c @@ -488,34 +488,32 @@ struct snd_stru_cmipci { /* read/write operations for dword register */ -static inline void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data) +inline static void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data) { outl(data, cm->iobase + cmd); } - -static inline unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd) +inline static unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd) { return inl(cm->iobase + cmd); } /* read/write operations for word register */ -static inline void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data) +inline static void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data) { outw(data, cm->iobase + cmd); } - -static inline unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd) +inline static unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd) { return inw(cm->iobase + cmd); } /* read/write operations for byte register */ -static inline void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data) +inline static void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data) { outb(data, cm->iobase + cmd); } -static inline unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd) +inline static unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd) { return inb(cm->iobase + cmd); } diff --git a/trunk/sound/pci/cs4281.c b/trunk/sound/pci/cs4281.c index c7a370d4f923..eb3c52b03af3 100644 --- a/trunk/sound/pci/cs4281.c +++ b/trunk/sound/pci/cs4281.c @@ -542,7 +542,7 @@ static void snd_cs4281_delay(unsigned int delay) } } -static inline void snd_cs4281_delay_long(void) +inline static void snd_cs4281_delay_long(void) { set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(1); diff --git a/trunk/sound/pci/emu10k1/memory.c b/trunk/sound/pci/emu10k1/memory.c index 6afeaeab3e13..7a595f0dd7a1 100644 --- a/trunk/sound/pci/emu10k1/memory.c +++ b/trunk/sound/pci/emu10k1/memory.c @@ -495,7 +495,7 @@ static int synth_free_pages(emu10k1_t *emu, emu10k1_memblk_t *blk) } /* calculate buffer pointer from offset address */ -static inline void *offset_ptr(emu10k1_t *emu, int page, int offset) +inline static void *offset_ptr(emu10k1_t *emu, int page, int offset) { char *ptr; snd_assert(page >= 0 && page < emu->max_cache_pages, return NULL); diff --git a/trunk/sound/pci/es1968.c b/trunk/sound/pci/es1968.c index 327a341e276b..ea889b311390 100644 --- a/trunk/sound/pci/es1968.c +++ b/trunk/sound/pci/es1968.c @@ -636,7 +636,7 @@ static void __maestro_write(es1968_t *chip, u16 reg, u16 data) chip->maestro_map[reg] = data; } -static inline void maestro_write(es1968_t *chip, u16 reg, u16 data) +inline static void maestro_write(es1968_t *chip, u16 reg, u16 data) { unsigned long flags; spin_lock_irqsave(&chip->reg_lock, flags); @@ -654,7 +654,7 @@ static u16 __maestro_read(es1968_t *chip, u16 reg) return chip->maestro_map[reg]; } -static inline u16 maestro_read(es1968_t *chip, u16 reg) +inline static u16 maestro_read(es1968_t *chip, u16 reg) { unsigned long flags; u16 result; @@ -755,7 +755,7 @@ static void __apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data) apu_data_set(chip, data); } -static inline void apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data) +inline static void apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data) { unsigned long flags; spin_lock_irqsave(&chip->reg_lock, flags); @@ -771,7 +771,7 @@ static u16 __apu_get_register(es1968_t *chip, u16 channel, u8 reg) return __maestro_read(chip, IDR0_DATA_PORT); } -static inline u16 apu_get_register(es1968_t *chip, u16 channel, u8 reg) +inline static u16 apu_get_register(es1968_t *chip, u16 channel, u8 reg) { unsigned long flags; u16 v; @@ -957,7 +957,7 @@ static u32 snd_es1968_compute_rate(es1968_t *chip, u32 freq) } /* get current pointer */ -static inline unsigned int +inline static unsigned int snd_es1968_get_dma_ptr(es1968_t *chip, esschan_t *es) { unsigned int offset; @@ -978,7 +978,7 @@ static void snd_es1968_apu_set_freq(es1968_t *chip, int apu, int freq) } /* spin lock held */ -static inline void snd_es1968_trigger_apu(es1968_t *esm, int apu, int mode) +inline static void snd_es1968_trigger_apu(es1968_t *esm, int apu, int mode) { /* set the APU mode */ __apu_set_register(esm, apu, 0, diff --git a/trunk/sound/pci/maestro3.c b/trunk/sound/pci/maestro3.c index 52c585901c54..096f15132853 100644 --- a/trunk/sound/pci/maestro3.c +++ b/trunk/sound/pci/maestro3.c @@ -1055,22 +1055,22 @@ static struct m3_hv_quirk m3_hv_quirk_list[] = { schedule_timeout(((msec) * HZ) / 1000);\ } while (0) -static inline void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg) +inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg) { outw(value, chip->iobase + reg); } -static inline u16 snd_m3_inw(m3_t *chip, unsigned long reg) +inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg) { return inw(chip->iobase + reg); } -static inline void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg) +inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg) { outb(value, chip->iobase + reg); } -static inline u8 snd_m3_inb(m3_t *chip, unsigned long reg) +inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg) { return inb(chip->iobase + reg); } diff --git a/trunk/sound/pci/nm256/nm256.c b/trunk/sound/pci/nm256/nm256.c index 7eb20b8f89f6..8a52091f8552 100644 --- a/trunk/sound/pci/nm256/nm256.c +++ b/trunk/sound/pci/nm256/nm256.c @@ -285,43 +285,43 @@ MODULE_DEVICE_TABLE(pci, snd_nm256_ids); * lowlvel stuffs */ -static inline u8 +inline static u8 snd_nm256_readb(nm256_t *chip, int offset) { return readb(chip->cport + offset); } -static inline u16 +inline static u16 snd_nm256_readw(nm256_t *chip, int offset) { return readw(chip->cport + offset); } -static inline u32 +inline static u32 snd_nm256_readl(nm256_t *chip, int offset) { return readl(chip->cport + offset); } -static inline void +inline static void snd_nm256_writeb(nm256_t *chip, int offset, u8 val) { writeb(val, chip->cport + offset); } -static inline void +inline static void snd_nm256_writew(nm256_t *chip, int offset, u16 val) { writew(val, chip->cport + offset); } -static inline void +inline static void snd_nm256_writel(nm256_t *chip, int offset, u32 val) { writel(val, chip->cport + offset); } -static inline void +inline static void snd_nm256_write_buffer(nm256_t *chip, void *src, int offset, int size) { offset -= chip->buffer_start; @@ -926,7 +926,7 @@ snd_nm256_init_chip(nm256_t *chip) } -static inline void +inline static void snd_nm256_intr_check(nm256_t *chip) { if (chip->badintrcount++ > 1000) { diff --git a/trunk/sound/pci/rme9652/rme9652.c b/trunk/sound/pci/rme9652/rme9652.c index 1bc9d0df8516..f3037402d58f 100644 --- a/trunk/sound/pci/rme9652/rme9652.c +++ b/trunk/sound/pci/rme9652/rme9652.c @@ -1470,7 +1470,7 @@ static int snd_rme9652_get_tc_valid(snd_kcontrol_t * kcontrol, snd_ctl_elem_valu return 0; } -#ifdef ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE +#if ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE /* FIXME: this routine needs a port to the new control API --jk */ diff --git a/trunk/sound/pci/trident/trident_main.c b/trunk/sound/pci/trident/trident_main.c index a09b0fb49e81..ccd5ca2ba16f 100644 --- a/trunk/sound/pci/trident/trident_main.c +++ b/trunk/sound/pci/trident/trident_main.c @@ -3204,7 +3204,7 @@ static inline void snd_trident_free_gameport(trident_t *chip) { } /* * delay for 1 tick */ -static inline void do_delay(trident_t *chip) +inline static void do_delay(trident_t *chip) { set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(1); diff --git a/trunk/sound/pci/trident/trident_memory.c b/trunk/sound/pci/trident/trident_memory.c index 333d3790692a..6cc282681e09 100644 --- a/trunk/sound/pci/trident/trident_memory.c +++ b/trunk/sound/pci/trident/trident_memory.c @@ -118,7 +118,7 @@ static inline void set_silent_tlb(trident_t *trident, int page) #endif /* PAGE_SIZE */ /* calculate buffer pointer from offset address */ -static inline void *offset_ptr(trident_t *trident, int offset) +inline static void *offset_ptr(trident_t *trident, int offset) { char *ptr; ptr = page_to_ptr(trident, get_aligned_page(offset)); diff --git a/trunk/sound/pci/vx222/vx222_ops.c b/trunk/sound/pci/vx222/vx222_ops.c index 967bd5e6b23c..683e9799976f 100644 --- a/trunk/sound/pci/vx222/vx222_ops.c +++ b/trunk/sound/pci/vx222/vx222_ops.c @@ -82,7 +82,7 @@ static int vx2_reg_index[VX_REG_MAX] = { [VX_GPIOC] = 0, /* on the PLX */ }; -static inline unsigned long vx2_reg_addr(vx_core_t *_chip, int reg) +inline static unsigned long vx2_reg_addr(vx_core_t *_chip, int reg) { struct snd_vx222 *chip = (struct snd_vx222 *)_chip; return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg]; @@ -235,7 +235,7 @@ static void vx2_setup_pseudo_dma(vx_core_t *chip, int do_write) /* * vx_release_pseudo_dma - disable the pseudo-DMA mode */ -static inline void vx2_release_pseudo_dma(vx_core_t *chip) +inline static void vx2_release_pseudo_dma(vx_core_t *chip) { /* HREQ pin disabled. */ vx_outl(chip, ICR, 0); diff --git a/trunk/sound/pcmcia/vx/vxp_ops.c b/trunk/sound/pcmcia/vx/vxp_ops.c index 6f15c3d03ab5..ef6734271607 100644 --- a/trunk/sound/pcmcia/vx/vxp_ops.c +++ b/trunk/sound/pcmcia/vx/vxp_ops.c @@ -49,7 +49,7 @@ static int vxp_reg_offset[VX_REG_MAX] = { }; -static inline unsigned long vxp_reg_addr(vx_core_t *_chip, int reg) +inline static unsigned long vxp_reg_addr(vx_core_t *_chip, int reg) { struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip; return chip->port + vxp_reg_offset[reg]; diff --git a/trunk/sound/ppc/burgundy.c b/trunk/sound/ppc/burgundy.c index edbc0484e22a..3f837d9f3eb1 100644 --- a/trunk/sound/ppc/burgundy.c +++ b/trunk/sound/ppc/burgundy.c @@ -30,7 +30,7 @@ /* Waits for busy flag to clear */ -static inline void +inline static void snd_pmac_burgundy_busy_wait(pmac_t *chip) { int timeout = 50; @@ -40,7 +40,7 @@ snd_pmac_burgundy_busy_wait(pmac_t *chip) printk(KERN_DEBUG "burgundy_busy_wait: timeout\n"); } -static inline void +inline static void snd_pmac_burgundy_extend_wait(pmac_t *chip) { int timeout; diff --git a/trunk/sound/ppc/pmac.c b/trunk/sound/ppc/pmac.c index 844d76152ea2..75b8b7423036 100644 --- a/trunk/sound/ppc/pmac.c +++ b/trunk/sound/ppc/pmac.c @@ -153,7 +153,7 @@ static pmac_stream_t *snd_pmac_get_stream(pmac_t *chip, int stream) /* * wait while run status is on */ -static inline void +inline static void snd_pmac_wait_ack(pmac_stream_t *rec) { int timeout = 50000; @@ -177,7 +177,7 @@ static void snd_pmac_pcm_set_format(pmac_t *chip) /* * stop the DMA transfer */ -static inline void snd_pmac_dma_stop(pmac_stream_t *rec) +inline static void snd_pmac_dma_stop(pmac_stream_t *rec) { out_le32(&rec->dma->control, (RUN|WAKE|FLUSH|PAUSE) << 16); snd_pmac_wait_ack(rec); @@ -186,7 +186,7 @@ static inline void snd_pmac_dma_stop(pmac_stream_t *rec) /* * set the command pointer address */ -static inline void snd_pmac_dma_set_command(pmac_stream_t *rec, pmac_dbdma_t *cmd) +inline static void snd_pmac_dma_set_command(pmac_stream_t *rec, pmac_dbdma_t *cmd) { out_le32(&rec->dma->cmdptr, cmd->addr); } @@ -194,7 +194,7 @@ static inline void snd_pmac_dma_set_command(pmac_stream_t *rec, pmac_dbdma_t *cm /* * start the DMA */ -static inline void snd_pmac_dma_run(pmac_stream_t *rec, int status) +inline static void snd_pmac_dma_run(pmac_stream_t *rec, int status) { out_le32(&rec->dma->control, status | (status << 16)); } diff --git a/trunk/sound/usb/usbaudio.c b/trunk/sound/usb/usbaudio.c index b5e734d975e0..a75695045f29 100644 --- a/trunk/sound/usb/usbaudio.c +++ b/trunk/sound/usb/usbaudio.c @@ -212,7 +212,7 @@ static snd_usb_audio_t *usb_chip[SNDRV_CARDS]; * convert a sampling rate into our full speed format (fs/1000 in Q16.16) * this will overflow at approx 524 kHz */ -static inline unsigned get_usb_full_speed_rate(unsigned int rate) +inline static unsigned get_usb_full_speed_rate(unsigned int rate) { return ((rate << 13) + 62) / 125; } @@ -221,19 +221,19 @@ static inline unsigned get_usb_full_speed_rate(unsigned int rate) * convert a sampling rate into USB high speed format (fs/8000 in Q16.16) * this will overflow at approx 4 MHz */ -static inline unsigned get_usb_high_speed_rate(unsigned int rate) +inline static unsigned get_usb_high_speed_rate(unsigned int rate) { return ((rate << 10) + 62) / 125; } /* convert our full speed USB rate into sampling rate in Hz */ -static inline unsigned get_full_speed_hz(unsigned int usb_rate) +inline static unsigned get_full_speed_hz(unsigned int usb_rate) { return (usb_rate * 125 + (1 << 12)) >> 13; } /* convert our high speed USB rate into sampling rate in Hz */ -static inline unsigned get_high_speed_hz(unsigned int usb_rate) +inline static unsigned get_high_speed_hz(unsigned int usb_rate) { return (usb_rate * 125 + (1 << 9)) >> 10; } diff --git a/trunk/sound/usb/usbmixer.c b/trunk/sound/usb/usbmixer.c index fa7056f5caaf..e73c1c9d3e73 100644 --- a/trunk/sound/usb/usbmixer.c +++ b/trunk/sound/usb/usbmixer.c @@ -363,7 +363,7 @@ static int get_cur_ctl_value(usb_mixer_elem_info_t *cval, int validx, int *value } /* channel = 0: master, 1 = first channel */ -static inline int get_cur_mix_value(usb_mixer_elem_info_t *cval, int channel, int *value) +inline static int get_cur_mix_value(usb_mixer_elem_info_t *cval, int channel, int *value) { return get_ctl_value(cval, GET_CUR, (cval->control << 8) | channel, value); } @@ -399,7 +399,7 @@ static int set_cur_ctl_value(usb_mixer_elem_info_t *cval, int validx, int value) return set_ctl_value(cval, SET_CUR, validx, value); } -static inline int set_cur_mix_value(usb_mixer_elem_info_t *cval, int channel, int value) +inline static int set_cur_mix_value(usb_mixer_elem_info_t *cval, int channel, int value) { return set_ctl_value(cval, SET_CUR, (cval->control << 8) | channel, value); }