From 10ccfcc2688bb2c421ac03851381854df1e5c5fe Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 3 Sep 2009 20:13:56 +0300 Subject: [PATCH] --- yaml --- r: 163150 b: refs/heads/master c: 6dda2d4b1306c19e39496e9bb305424d1d547013 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-omap/include/mach/sdrc.h | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 925e49c5f839..3533c474d825 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5d113262ee9e074e0d36362d878892819bfdeb47 +refs/heads/master: 6dda2d4b1306c19e39496e9bb305424d1d547013 diff --git a/trunk/arch/arm/plat-omap/include/mach/sdrc.h b/trunk/arch/arm/plat-omap/include/mach/sdrc.h index 93f70d2cbce1..1c09c78a48f2 100644 --- a/trunk/arch/arm/plat-omap/include/mach/sdrc.h +++ b/trunk/arch/arm/plat-omap/include/mach/sdrc.h @@ -21,19 +21,28 @@ /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ #define SDRC_SYSCONFIG 0x010 +#define SDRC_CS_CFG 0x040 +#define SDRC_SHARING 0x044 +#define SDRC_ERR_TYPE 0x04C #define SDRC_DLLA_CTRL 0x060 #define SDRC_DLLA_STATUS 0x064 #define SDRC_DLLB_CTRL 0x068 #define SDRC_DLLB_STATUS 0x06C #define SDRC_POWER 0x070 +#define SDRC_MCFG_0 0x080 #define SDRC_MR_0 0x084 +#define SDRC_EMR2_0 0x08c #define SDRC_ACTIM_CTRL_A_0 0x09c #define SDRC_ACTIM_CTRL_B_0 0x0a0 #define SDRC_RFR_CTRL_0 0x0a4 +#define SDRC_MANUAL_0 0x0a8 +#define SDRC_MCFG_1 0x0B0 #define SDRC_MR_1 0x0B4 +#define SDRC_EMR2_1 0x0BC #define SDRC_ACTIM_CTRL_A_1 0x0C4 #define SDRC_ACTIM_CTRL_B_1 0x0C8 #define SDRC_RFR_CTRL_1 0x0D4 +#define SDRC_MANUAL_1 0x0D8 /* * These values represent the number of memory clock cycles between