From 10dd1d40f99654c0248e026d5f1af66a7c3d2672 Mon Sep 17 00:00:00 2001
From: saeed bishara <saeed@marvell.com>
Date: Mon, 16 May 2011 11:25:21 +0100
Subject: [PATCH] --- yaml --- r: 249948 b: refs/heads/master c:
 31bee4cf0e74e9c962d481a68452debaf45ed4ac h: refs/heads/master v: v3

---
 [refs]                    | 2 +-
 trunk/arch/arm/mm/flush.c | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index ea51a07cdca4..d4b5743bac89 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 5f23188e036aabfe9245f9e61adbb4ea27ed8f35
+refs/heads/master: 31bee4cf0e74e9c962d481a68452debaf45ed4ac
diff --git a/trunk/arch/arm/mm/flush.c b/trunk/arch/arm/mm/flush.c
index 2b269c955524..b7f69800348f 100644
--- a/trunk/arch/arm/mm/flush.c
+++ b/trunk/arch/arm/mm/flush.c
@@ -275,7 +275,8 @@ void __sync_icache_dcache(pte_t pteval)
  *  kernel cache lines for later.  Otherwise, we assume we have
  *  aliasing mappings.
  *
- * Note that we disable the lazy flush for SMP.
+ * Note that we disable the lazy flush for SMP configurations where
+ * the cache maintenance operations are not automatically broadcasted.
  */
 void flush_dcache_page(struct page *page)
 {