From 112536bad72a5d27cca6af9861f4a8b7ecd56f8e Mon Sep 17 00:00:00 2001
From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sat, 20 Oct 2012 20:57:44 +0200
Subject: [PATCH] --- yaml --- r: 345165 b: refs/heads/master c:
 6b3ec1c9fb73cca38842d030b171ffd16a686949 h: refs/heads/master i:   345163:
 8cd745d96a3545594ab70efca29b07b61fb0c9c2 v: v3

---
 [refs]                                | 2 +-
 trunk/drivers/gpu/drm/i915/intel_dp.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 70566886963f..1824ccee781c 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d2acd215cdb75eb39afadbf31a19bdcf84af7eaf
+refs/heads/master: 6b3ec1c9fb73cca38842d030b171ffd16a686949
diff --git a/trunk/drivers/gpu/drm/i915/intel_dp.c b/trunk/drivers/gpu/drm/i915/intel_dp.c
index adfb98cb7ba9..c1ed1aff2750 100644
--- a/trunk/drivers/gpu/drm/i915/intel_dp.c
+++ b/trunk/drivers/gpu/drm/i915/intel_dp.c
@@ -377,7 +377,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		else
 			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 	} else if (HAS_PCH_SPLIT(dev))
-		aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
+		aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 	else
 		aux_clock_divider = intel_hrawclk(dev) / 2;