From 11434dd0a12e5d08a0fa059f0c34cfdc20b61562 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com>
Date: Wed, 28 Mar 2012 08:52:32 +0200
Subject: [PATCH] --- yaml --- r: 296739 b: refs/heads/master c:
 d936622c36273a9ecfbb4aacf26cd29405995159 h: refs/heads/master i:   296737:
 f32cf8f98237bcb1a9450099b260472913b67f62   296735:
 cff0e175dede87590567df1c9af899bb7bfd940a v: v3

---
 [refs]                                       |  2 +-
 trunk/drivers/gpu/drm/radeon/radeon_object.c | 12 +++++++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index edd6f6cdae01..bb43d2ff7c43 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 88f50c80748bf5238c88e70ee26c68ac48b94e68
+refs/heads/master: d936622c36273a9ecfbb4aacf26cd29405995159
diff --git a/trunk/drivers/gpu/drm/radeon/radeon_object.c b/trunk/drivers/gpu/drm/radeon/radeon_object.c
index 91541e63d582..6f70158d34e4 100644
--- a/trunk/drivers/gpu/drm/radeon/radeon_object.c
+++ b/trunk/drivers/gpu/drm/radeon/radeon_object.c
@@ -233,7 +233,17 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 		bo->pin_count++;
 		if (gpu_addr)
 			*gpu_addr = radeon_bo_gpu_offset(bo);
-		WARN_ON_ONCE(max_offset != 0);
+
+		if (max_offset != 0) {
+			u64 domain_start;
+
+			if (domain == RADEON_GEM_DOMAIN_VRAM)
+				domain_start = bo->rdev->mc.vram_start;
+			else
+				domain_start = bo->rdev->mc.gtt_start;
+			WARN_ON_ONCE((*gpu_addr - domain_start) > max_offset);
+		}
+
 		return 0;
 	}
 	radeon_ttm_placement_from_domain(bo, domain);