From 11537a672938f1ebc81a4e0c96594044d9a54360 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 19 Dec 2012 21:38:55 +0000 Subject: [PATCH] --- yaml --- r: 348091 b: refs/heads/master c: fa416ddc0ae5996d894b10f7f49efc2a494b048b h: refs/heads/master i: 348089: f21269e54ede2ddddd22c7bda4b0dd2752c559eb 348087: 589d998db3021f5a48ead34ddd588001c206e214 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/tegra/hdmi.c | 19 +++---------------- 2 files changed, 4 insertions(+), 17 deletions(-) diff --git a/[refs] b/[refs] index 37a59d6864bb..5b073861930f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 83c0bcb694be31dcd6c04bdd935b96a95a0af548 +refs/heads/master: fa416ddc0ae5996d894b10f7f49efc2a494b048b diff --git a/trunk/drivers/gpu/drm/tegra/hdmi.c b/trunk/drivers/gpu/drm/tegra/hdmi.c index 81ea934214f1..e060c7e6434d 100644 --- a/trunk/drivers/gpu/drm/tegra/hdmi.c +++ b/trunk/drivers/gpu/drm/tegra/hdmi.c @@ -149,7 +149,7 @@ struct tmds_config { }; static const struct tmds_config tegra2_tmds_config[] = { - { /* 480p modes */ + { /* slow pixel clock modes */ .pclk = 27000000, .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | @@ -163,21 +163,8 @@ static const struct tmds_config tegra2_tmds_config[] = { DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), - }, { /* 720p modes */ - .pclk = 74250000, - .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | - SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | - SOR_PLL_TX_REG_LOAD(3), - .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, - .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) | - PE_CURRENT1(PE_CURRENT_6_0_mA) | - PE_CURRENT2(PE_CURRENT_6_0_mA) | - PE_CURRENT3(PE_CURRENT_6_0_mA), - .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | - DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | - DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | - DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), - }, { /* 1080p modes */ + }, + { /* high pixel clock modes */ .pclk = UINT_MAX, .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |