From 119ba9e944964de28bfa71856805a6d29179de14 Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Tue, 5 Feb 2013 16:52:03 -0600 Subject: [PATCH] --- yaml --- r: 375190 b: refs/heads/master c: bfd08baae4591eca753afe3c9c63c583c4d4c78a h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mips/include/asm/mipsregs.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 192ed69905e3..7ffc8225a560 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a6a4834cdbef23a7db16e7598c8c6e427ac82531 +refs/heads/master: bfd08baae4591eca753afe3c9c63c583c4d4c78a diff --git a/trunk/arch/mips/include/asm/mipsregs.h b/trunk/arch/mips/include/asm/mipsregs.h index 0da44d422f5b..f64e17fa3e96 100644 --- a/trunk/arch/mips/include/asm/mipsregs.h +++ b/trunk/arch/mips/include/asm/mipsregs.h @@ -622,6 +622,24 @@ #ifndef __ASSEMBLY__ +/* + * Macros for handling the ISA mode bit for microMIPS. + */ +#define get_isa16_mode(x) ((x) & 0x1) +#define msk_isa16_mode(x) ((x) & ~0x1) +#define set_isa16_mode(x) do { (x) |= 0x1; } while(0) + +/* + * microMIPS instructions can be 16-bit or 32-bit in length. This + * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. + */ +static inline int mm_insn_16bit(u16 insn) +{ + u16 opcode = (insn >> 10) & 0x7; + + return (opcode >= 1 && opcode <= 3) ? 1 : 0; +} + /* * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit