From 1397679c4d3263d5c69b1919751edd9c8478c10e Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Wed, 20 Feb 2013 18:21:58 +0100
Subject: [PATCH] --- yaml --- r: 355652 b: refs/heads/master c:
 9cb0d1babfcb1b4ac248c09425f7d5de1e771133 h: refs/heads/master v: v3

---
 [refs]                               |  2 +-
 trunk/arch/arm/mach-prima2/headsmp.S | 40 ----------------------------
 2 files changed, 1 insertion(+), 41 deletions(-)

diff --git a/[refs] b/[refs]
index 0beba2a34174..71820b201f0a 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6e7f7cfce26cabea2965a43b69b4a0c285a7e4c5
+refs/heads/master: 9cb0d1babfcb1b4ac248c09425f7d5de1e771133
diff --git a/trunk/arch/arm/mach-prima2/headsmp.S b/trunk/arch/arm/mach-prima2/headsmp.S
index ada82d0917ef..5b8a408d8921 100644
--- a/trunk/arch/arm/mach-prima2/headsmp.S
+++ b/trunk/arch/arm/mach-prima2/headsmp.S
@@ -11,46 +11,6 @@
 
 	__CPUINIT
 
-/*
- * Cold boot and hardware reset show different behaviour,
- * system will be always panic if we warm-reset the board
- * Here we invalidate L1 of CPU1 to make sure there isn't
- * uninitialized data written into memory later
- */
-ENTRY(v7_invalidate_l1)
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
-	mcr	p15, 2, r0, c0, c0, 0
-	mrc	p15, 1, r0, c0, c0, 0
-
-	ldr	r1, =0x7fff
-	and	r2, r1, r0, lsr #13
-
-	ldr	r1, =0x3ff
-
-	and	r3, r1, r0, lsr #3	@ NumWays - 1
-	add	r2, r2, #1		@ NumSets
-
-	and	r0, r0, #0x7
-	add	r0, r0, #4	@ SetShift
-
-	clz	r1, r3		@ WayShift
-	add	r4, r3, #1	@ NumWays
-1:	sub	r2, r2, #1	@ NumSets--
-	mov	r3, r4		@ Temp = NumWays
-2:	subs	r3, r3, #1	@ Temp--
-	mov	r5, r3, lsl r1
-	mov	r6, r2, lsl r0
-	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-	mcr	p15, 0, r5, c7, c6, 2
-	bgt	2b
-	cmp	r2, #0
-	bgt	1b
-	dsb
-	isb
-	mov	pc, lr
-ENDPROC(v7_invalidate_l1)
-
 /*
  * SIRFSOC specific entry point for secondary CPUs.  This provides
  * a "holding pen" into which all secondary cores are held until we're