diff --git a/[refs] b/[refs]
index 1f4502b2f0bf..279b7fcef79c 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 660b73e356a63d67231aab49d23e83b1a5a9ec87
+refs/heads/master: a45f56b272e59527e41d7fbfc9b49dac9b90644c
diff --git a/trunk/arch/m68k/include/asm/m5206sim.h b/trunk/arch/m68k/include/asm/m5206sim.h
index 02a91f489cbf..c78ff10c0153 100644
--- a/trunk/arch/m68k/include/asm/m5206sim.h
+++ b/trunk/arch/m68k/include/asm/m5206sim.h
@@ -85,9 +85,9 @@
 #define	MCFSIM_DMCR		0xc6		/* Default control */
 
 #ifdef CONFIG_M5206e
-#define	MCFSIM_PAR		0xca		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0xca)	/* Pin Assignment */
 #else
-#define	MCFSIM_PAR		0xcb		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0xcb)	/* Pin Assignment */
 #endif
 
 #define	MCFTIMER_BASE1		(MCF_MBAR + 0x100)	/* Base of TIMER1 */
diff --git a/trunk/arch/m68k/include/asm/m5249sim.h b/trunk/arch/m68k/include/asm/m5249sim.h
index 7229fd872348..6e2bb0c57197 100644
--- a/trunk/arch/m68k/include/asm/m5249sim.h
+++ b/trunk/arch/m68k/include/asm/m5249sim.h
@@ -29,7 +29,7 @@
 #define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
 #define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog srv */
-#define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
 #define	MCFSIM_IRQPAR		0x06		/* Interrupt Assignment reg (r/w) */
 #define	MCFSIM_MPARK		0x0C		/* BUS Master Control Reg*/
 #define	MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */
diff --git a/trunk/arch/m68k/include/asm/m5307sim.h b/trunk/arch/m68k/include/asm/m5307sim.h
index a328e1806feb..7d89d86144af 100644
--- a/trunk/arch/m68k/include/asm/m5307sim.h
+++ b/trunk/arch/m68k/include/asm/m5307sim.h
@@ -27,7 +27,7 @@
 #define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
 #define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog service*/
-#define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
 #define	MCFSIM_IRQPAR		0x06		/* Interrupt Assignment reg (r/w) */
 #define	MCFSIM_PLLCR		0x08		/* PLL Control Reg*/
 #define	MCFSIM_MPARK		0x0C		/* BUS Master Control Reg*/
diff --git a/trunk/arch/m68k/include/asm/m5407sim.h b/trunk/arch/m68k/include/asm/m5407sim.h
index 023f5f64ccd5..51111afc7926 100644
--- a/trunk/arch/m68k/include/asm/m5407sim.h
+++ b/trunk/arch/m68k/include/asm/m5407sim.h
@@ -27,7 +27,7 @@
 #define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
 #define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog service*/
-#define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */
+#define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
 #define	MCFSIM_IRQPAR		0x06		/* Interrupt Assignment reg (r/w) */
 #define	MCFSIM_PLLCR		0x08		/* PLL Control Reg*/
 #define	MCFSIM_MPARK		0x0C		/* BUS Master Control Reg*/