From 14a1cc67351d27710af862830410c8f762f8bef1 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Date: Sat, 9 Mar 2013 14:59:08 +0100
Subject: [PATCH] --- yaml --- r: 370459 b: refs/heads/master c:
 a15ac4a640264c94e56603159147244c1e75feda h: refs/heads/master i:   370457:
 a97e8420a2d8015e9538ef354f443a990b1911f9   370455:
 e0f970d908d85490cd9cca42446a2228d074b620 v: v3

---
 [refs]                             |  2 +-
 trunk/arch/arm/boot/dts/imx51.dtsi | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 264216272683..2e826d791a3b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: e910b45c9d6413c057fc0aaf8616683446bdda7d
+refs/heads/master: a15ac4a640264c94e56603159147244c1e75feda
diff --git a/trunk/arch/arm/boot/dts/imx51.dtsi b/trunk/arch/arm/boot/dts/imx51.dtsi
index 6e14b7574343..7e09ccfd0b29 100644
--- a/trunk/arch/arm/boot/dts/imx51.dtsi
+++ b/trunk/arch/arm/boot/dts/imx51.dtsi
@@ -317,6 +317,16 @@
 					};
 				};
 
+				ecspi2 {
+					pinctrl_ecspi2_1: ecspi2grp-1 {
+						fsl,pins = <
+							MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
+							MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
+							MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
+						>;
+					};
+				};
+
 				esdhc1 {
 					pinctrl_esdhc1_1: esdhc1grp-1 {
 						fsl,pins = <