From 14d4fd0f2c704bbfd94524292c7a7ee2759301be Mon Sep 17 00:00:00 2001
From: Michael Chan <mchan@broadcom.com>
Date: Mon, 4 Jun 2007 21:23:06 -0700
Subject: [PATCH] --- yaml --- r: 57419 b: refs/heads/master c:
 0aa38df7cd5b6c5b89f5146f4a2286434bc4a8f3 h: refs/heads/master i:   57417:
 b7c40c2c90e8542629baa10f8bf70733fa98dd4d   57415:
 ec145e9811a2c80469fef0e539ee3f3d53a125f1 v: v3

---
 [refs]                   | 2 +-
 trunk/drivers/net/bnx2.c | 5 +++++
 trunk/drivers/net/bnx2.h | 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 3286edb27779..9d238fe69571 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 641bdcd56c8bb2110a31da846b2752b11a644050
+refs/heads/master: 0aa38df7cd5b6c5b89f5146f4a2286434bc4a8f3
diff --git a/trunk/drivers/net/bnx2.c b/trunk/drivers/net/bnx2.c
index 9eba7a2635ad..3b7ca2a455b4 100644
--- a/trunk/drivers/net/bnx2.c
+++ b/trunk/drivers/net/bnx2.c
@@ -3815,6 +3815,11 @@ bnx2_init_chip(struct bnx2 *bp)
 	/* Initialize the receive filter. */
 	bnx2_set_rx_mode(bp->dev);
 
+	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+		val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
+		val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
+		REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
+	}
 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
 			  0);
 
diff --git a/trunk/drivers/net/bnx2.h b/trunk/drivers/net/bnx2.h
index bd6288d6350f..49a5de253b17 100644
--- a/trunk/drivers/net/bnx2.h
+++ b/trunk/drivers/net/bnx2.h
@@ -1373,6 +1373,7 @@ struct l2_fhdr {
 #define BNX2_MISC_NEW_CORE_CTL				0x000008c8
 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS	 (1L<<0)
 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ		 (1L<<1)
+#define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE		 (1L<<16)
 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN		 (0x3fffL<<2)
 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC		 (0xffffL<<16)