From 1536cb7e06855e1a0cabc29f561e8de75d0b86e0 Mon Sep 17 00:00:00 2001
From: Bjorn Helgaas <bjorn.helgaas@hp.com>
Date: Mon, 27 Apr 2009 16:33:36 -0600
Subject: [PATCH] --- yaml --- r: 154166 b: refs/heads/master c:
 b9417f84e17b93a6976a8a88b38bf9567975cb38 h: refs/heads/master v: v3

---
 [refs]                              |  2 +-
 trunk/arch/x86/kernel/acpi/cstate.c | 16 +++-------------
 trunk/drivers/acpi/processor_idle.c |  7 ++-----
 trunk/include/acpi/acpi_drivers.h   |  2 +-
 4 files changed, 7 insertions(+), 20 deletions(-)

diff --git a/[refs] b/[refs]
index bdba56a87546..5ece1ad85da1 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ee1ca48fae7e575d5e399d4fdcfe0afc1212a64c
+refs/heads/master: b9417f84e17b93a6976a8a88b38bf9567975cb38
diff --git a/trunk/arch/x86/kernel/acpi/cstate.c b/trunk/arch/x86/kernel/acpi/cstate.c
index 8c44c232efcb..bbbe4bbb6f34 100644
--- a/trunk/arch/x86/kernel/acpi/cstate.c
+++ b/trunk/arch/x86/kernel/acpi/cstate.c
@@ -34,22 +34,12 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 		flags->bm_check = 1;
 	else if (c->x86_vendor == X86_VENDOR_INTEL) {
 		/*
-		 * Today all MP CPUs that support C3 share cache.
-		 * And caches should not be flushed by software while
-		 * entering C3 type state.
+		 * Today all CPUs that support C3 share cache.
+		 * TBD: This needs to look at cache shared map, once
+		 * multi-core detection patch makes to the base.
 		 */
 		flags->bm_check = 1;
 	}
-
-	/*
-	 * On all recent Intel platforms, ARB_DISABLE is a nop.
-	 * So, set bm_control to zero to indicate that ARB_DISABLE
-	 * is not required while entering C3 type state on
-	 * P4, Core and beyond CPUs
-	 */
-	if (c->x86_vendor == X86_VENDOR_INTEL &&
-	    (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14)))
-			flags->bm_control = 0;
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
diff --git a/trunk/drivers/acpi/processor_idle.c b/trunk/drivers/acpi/processor_idle.c
index 4840c79fd8e0..72069ba5f1ed 100644
--- a/trunk/drivers/acpi/processor_idle.c
+++ b/trunk/drivers/acpi/processor_idle.c
@@ -512,8 +512,7 @@ static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx)
 static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
 					   struct acpi_processor_cx *cx)
 {
-	static int bm_check_flag = -1;
-	static int bm_control_flag = -1;
+	static int bm_check_flag;
 
 
 	if (!cx->address)
@@ -543,14 +542,12 @@ static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
 	}
 
 	/* All the logic here assumes flags.bm_check is same across all CPUs */
-	if (bm_check_flag == -1) {
+	if (!bm_check_flag) {
 		/* Determine whether bm_check is needed based on CPU  */
 		acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
 		bm_check_flag = pr->flags.bm_check;
-		bm_control_flag = pr->flags.bm_control;
 	} else {
 		pr->flags.bm_check = bm_check_flag;
-		pr->flags.bm_control = bm_control_flag;
 	}
 
 	if (pr->flags.bm_check) {
diff --git a/trunk/include/acpi/acpi_drivers.h b/trunk/include/acpi/acpi_drivers.h
index 0352c8f0b05b..c9922b362005 100644
--- a/trunk/include/acpi/acpi_drivers.h
+++ b/trunk/include/acpi/acpi_drivers.h
@@ -57,7 +57,7 @@
  */
 
 #define ACPI_POWER_HID			"LNXPOWER"
-#define ACPI_PROCESSOR_OBJECT_HID	"ACPI_CPU"
+#define ACPI_PROCESSOR_OBJECT_HID	"LNXCPU"
 #define ACPI_PROCESSOR_HID		"ACPI0007"
 #define ACPI_SYSTEM_HID			"LNXSYSTM"
 #define ACPI_THERMAL_HID		"LNXTHERM"