From 15cf2237c0f7573e6cf3fb7b701631a48f380a69 Mon Sep 17 00:00:00 2001 From: Albert Lee Date: Tue, 3 Jul 2007 22:28:36 +0200 Subject: [PATCH] --- yaml --- r: 58188 b: refs/heads/master c: 8006bf56e360a4db71d304df778870a371a9e930 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/ide/pci/pdc202xx_new.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 810eccea71f2..4c9de8cad730 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 52374f890c1d0d64148d55a20d995a0b3e0ae987 +refs/heads/master: 8006bf56e360a4db71d304df778870a371a9e930 diff --git a/trunk/drivers/ide/pci/pdc202xx_new.c b/trunk/drivers/ide/pci/pdc202xx_new.c index cc0bfdcf1f19..0765dce6948e 100644 --- a/trunk/drivers/ide/pci/pdc202xx_new.c +++ b/trunk/drivers/ide/pci/pdc202xx_new.c @@ -306,11 +306,13 @@ static long __devinit read_counter(u32 dma_base) */ static long __devinit detect_pll_input_clock(unsigned long dma_base) { + struct timeval start_time, end_time; long start_count, end_count; - long pll_input; + long pll_input, usec_elapsed; u8 scr1; start_count = read_counter(dma_base); + do_gettimeofday(&start_time); /* Start the test mode */ outb(0x01, dma_base + 0x01); @@ -322,6 +324,7 @@ static long __devinit detect_pll_input_clock(unsigned long dma_base) mdelay(10); end_count = read_counter(dma_base); + do_gettimeofday(&end_time); /* Stop the test mode */ outb(0x01, dma_base + 0x01); @@ -333,7 +336,10 @@ static long __devinit detect_pll_input_clock(unsigned long dma_base) * Calculate the input clock in Hz * (the clock counter is 30 bit wide and counts down) */ - pll_input = ((start_count - end_count) & 0x3ffffff) * 100; + usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 + + (end_time.tv_usec - start_time.tv_usec); + pll_input = ((start_count - end_count) & 0x3ffffff) / 10 * + (10000000 / usec_elapsed); DBG("start[%ld] end[%ld]\n", start_count, end_count);