From 15e0d46d5e3239e3f7f7094b5e86dfb85d5dfcf3 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Fri, 4 May 2012 17:18:25 -0300 Subject: [PATCH] --- yaml --- r: 307416 b: refs/heads/master c: 4dc20c0d185132077522dd92a72db79274e13f65 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_hdmi.c | 8 +------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/[refs] b/[refs] index 9f11484defaf..7da956c233e7 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fdf1250aaae12625ee2abaf2ef22def0a4cdf71b +refs/heads/master: 4dc20c0d185132077522dd92a72db79274e13f65 diff --git a/trunk/drivers/gpu/drm/i915/intel_hdmi.c b/trunk/drivers/gpu/drm/i915/intel_hdmi.c index e65ebc2d3ad9..539073ec56bd 100644 --- a/trunk/drivers/gpu/drm/i915/intel_hdmi.c +++ b/trunk/drivers/gpu/drm/i915/intel_hdmi.c @@ -187,13 +187,7 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= intel_infoframe_index(frame); - /* The DIP control register spec says that we need to update the AVI - * infoframe without clearing its enable bit */ - if (frame->type == DIP_TYPE_AVI) - val |= VIDEO_DIP_ENABLE_AVI; - else - val &= ~intel_infoframe_enable(frame); - + val &= ~intel_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val);