From 15f4d92167eb93c029004d0b95daf97a7268c98b Mon Sep 17 00:00:00 2001 From: Matt Carlson Date: Mon, 25 Apr 2011 12:42:45 +0000 Subject: [PATCH] --- yaml --- r: 246980 b: refs/heads/master c: 0aebff4871d26410ae485b521870bb0ffe1736f0 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/net/tg3.c | 3 +++ trunk/drivers/net/tg3.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 60945c099511..4b7204e3e4c3 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bf734843120b905bacc3d24c88d7455ae70bf6e1 +refs/heads/master: 0aebff4871d26410ae485b521870bb0ffe1736f0 diff --git a/trunk/drivers/net/tg3.c b/trunk/drivers/net/tg3.c index 693f36e94dab..a72d0314ca78 100644 --- a/trunk/drivers/net/tg3.c +++ b/trunk/drivers/net/tg3.c @@ -8198,6 +8198,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; + if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) + val |= DMA_RWCTRL_TAGGED_STAT_WA; tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { diff --git a/trunk/drivers/net/tg3.h b/trunk/drivers/net/tg3.h index eaa76694efb5..6f37d2a23544 100644 --- a/trunk/drivers/net/tg3.h +++ b/trunk/drivers/net/tg3.h @@ -188,6 +188,7 @@ #define METAL_REV_B2 0x02 #define TG3PCI_DMA_RW_CTRL 0x0000006c #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 +#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080 #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000