From 16688af67e0ee762b97a955d64b22b70da5d6e80 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 22 Mar 2013 19:25:59 +0100
Subject: [PATCH] --- yaml --- r: 375140 b: refs/heads/master c:
 6ac8579b96e3bc3581c3a42b326647594e5bbb03 h: refs/heads/master v: v3

---
 [refs]                          |  2 +-
 trunk/arch/mips/ralink/rt305x.c | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 5616ce597c67..ede617676824 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: bb19fea238daead66ab3630ad09fba50aa563048
+refs/heads/master: 6ac8579b96e3bc3581c3a42b326647594e5bbb03
diff --git a/trunk/arch/mips/ralink/rt305x.c b/trunk/arch/mips/ralink/rt305x.c
index 0a4bbdcf59d9..5d49a54ba8fa 100644
--- a/trunk/arch/mips/ralink/rt305x.c
+++ b/trunk/arch/mips/ralink/rt305x.c
@@ -124,6 +124,8 @@ struct ralink_pinmux gpio_pinmux = {
 void __init ralink_clk_init(void)
 {
 	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
+	unsigned long wmac_rate = 40000000;
+
 	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
 
 	if (soc_is_rt305x() || soc_is_rt3350()) {
@@ -176,11 +178,21 @@ void __init ralink_clk_init(void)
 		BUG();
 	}
 
+	if (soc_is_rt3352() || soc_is_rt5350()) {
+		u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
+
+		if (!(val & RT3352_CLKCFG0_XTAL_SEL))
+			wmac_rate = 20000000;
+	}
+
 	ralink_clk_add("cpu", cpu_rate);
 	ralink_clk_add("10000b00.spi", sys_rate);
 	ralink_clk_add("10000100.timer", wdt_rate);
+	ralink_clk_add("10000120.watchdog", wdt_rate);
 	ralink_clk_add("10000500.uart", uart_rate);
 	ralink_clk_add("10000c00.uartlite", uart_rate);
+	ralink_clk_add("10100000.ethernet", sys_rate);
+	ralink_clk_add("10180000.wmac", wmac_rate);
 }
 
 void __init ralink_of_remap(void)