From 168ed6b596ffd888b3c918e35ee2158ece230096 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 13:56:12 +0100 Subject: [PATCH] --- yaml --- r: 149302 b: refs/heads/master c: 412b400278ed0f71712387d0b9b31cbdd8a18efc h: refs/heads/master v: v3 --- [refs] | 2 +- .../arm/Samsung-S3C24XX/GPIO.txt | 10 +- trunk/Documentation/hwmon/sysfs-interface | 6 - .../input/multi-touch-protocol.txt | 103 +- trunk/Documentation/kernel-parameters.txt | 4 - .../sound/alsa/HD-Audio-Models.txt | 1 - trunk/Documentation/sound/alsa/Procfile.txt | 5 - trunk/MAINTAINERS | 110 +- trunk/Makefile | 2 +- trunk/arch/arm/Kconfig | 199 +- trunk/arch/arm/Makefile | 117 +- trunk/arch/arm/common/Kconfig | 8 - trunk/arch/arm/common/clkdev.c | 18 - trunk/arch/arm/common/vic.c | 221 +- trunk/arch/arm/configs/davinci_all_defconfig | 21 +- trunk/arch/arm/configs/ep93xx_defconfig | 853 +++----- trunk/arch/arm/configs/kirkwood_defconfig | 5 +- trunk/arch/arm/configs/mx21_defconfig | 1170 ----------- trunk/arch/arm/configs/omap3_evm_defconfig | 1528 -------------- trunk/arch/arm/configs/omap_4430sdp_defconfig | 866 -------- trunk/arch/arm/configs/omap_zoom2_defconfig | 1211 ----------- trunk/arch/arm/configs/orion5x_defconfig | 3 +- trunk/arch/arm/configs/rx51_defconfig | 2 +- trunk/arch/arm/configs/w90p910_defconfig | 423 +--- trunk/arch/arm/include/asm/assembler.h | 13 - trunk/arch/arm/include/asm/atomic.h | 61 +- trunk/arch/arm/include/asm/flat.h | 3 + trunk/arch/arm/include/asm/hardware/arm_twd.h | 21 + trunk/arch/arm/include/asm/hardware/pl080.h | 138 -- trunk/arch/arm/include/asm/hardware/vic.h | 2 +- trunk/arch/arm/include/asm/localtimer.h | 63 - trunk/arch/arm/include/asm/mach/map.h | 8 - trunk/arch/arm/include/asm/pgtable.h | 2 +- trunk/arch/arm/include/asm/sizes.h | 1 - trunk/arch/arm/include/asm/smp.h | 42 +- trunk/arch/arm/include/asm/smp_scu.h | 7 - trunk/arch/arm/include/asm/smp_twd.h | 12 - trunk/arch/arm/include/asm/system.h | 176 -- trunk/arch/arm/kernel/Makefile | 2 - trunk/arch/arm/kernel/elf.c | 9 - trunk/arch/arm/kernel/entry-armv.S | 5 +- trunk/arch/arm/kernel/smp.c | 62 +- trunk/arch/arm/kernel/smp_scu.c | 48 - trunk/arch/arm/kernel/smp_twd.c | 175 -- trunk/arch/arm/lib/bitops.h | 2 - trunk/arch/arm/mach-at91/board-afeb-9260v1.c | 6 - trunk/arch/arm/mach-at91/board-sam9g20ek.c | 9 +- trunk/arch/arm/mach-at91/clock.c | 151 +- .../arm/mach-at91/include/mach/at91_pmc.h | 26 +- trunk/arch/arm/mach-davinci/Kconfig | 43 - trunk/arch/arm/mach-davinci/Makefile | 13 +- trunk/arch/arm/mach-davinci/board-dm355-evm.c | 298 --- .../arm/mach-davinci/board-dm355-leopard.c | 296 --- .../arch/arm/mach-davinci/board-dm644x-evm.c | 68 +- .../arch/arm/mach-davinci/board-dm646x-evm.c | 262 --- trunk/arch/arm/mach-davinci/board-sffsdr.c | 189 -- trunk/arch/arm/mach-davinci/clock.c | 10 +- trunk/arch/arm/mach-davinci/clock.h | 4 - trunk/arch/arm/mach-davinci/common.c | 108 - trunk/arch/arm/mach-davinci/cp_intc.c | 161 -- trunk/arch/arm/mach-davinci/devices.c | 211 -- trunk/arch/arm/mach-davinci/dm355.c | 730 ------- trunk/arch/arm/mach-davinci/dm644x.c | 204 +- trunk/arch/arm/mach-davinci/dm646x.c | 636 ------ trunk/arch/arm/mach-davinci/gpio.c | 63 +- trunk/arch/arm/mach-davinci/id.c | 116 + .../include/mach/board-dm6446evm.h | 20 + .../arm/mach-davinci/include/mach/common.h | 55 +- .../arm/mach-davinci/include/mach/cp_intc.h | 57 - .../arm/mach-davinci/include/mach/cputype.h | 29 +- .../mach-davinci/include/mach/debug-macro.S | 31 +- .../arm/mach-davinci/include/mach/dm355.h | 22 - .../arm/mach-davinci/include/mach/dm644x.h | 1 - .../arm/mach-davinci/include/mach/dm646x.h | 26 - .../arch/arm/mach-davinci/include/mach/edma.h | 4 + .../arch/arm/mach-davinci/include/mach/emac.h | 36 - .../mach-davinci/include/mach/entry-macro.S | 25 +- .../arch/arm/mach-davinci/include/mach/gpio.h | 14 +- .../arch/arm/mach-davinci/include/mach/irqs.h | 3 - .../arm/mach-davinci/include/mach/memory.h | 1 + .../arch/arm/mach-davinci/include/mach/mmc.h | 33 - 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.../arch/arm/mach-imx/include/mach/imx-regs.h | 376 ++++ .../arch/arm/mach-imx/include/mach/imx-uart.h | 12 + .../include/mach/io.h} | 17 +- trunk/arch/arm/mach-imx/include/mach/irqs.h | 121 ++ trunk/arch/arm/mach-imx/include/mach/memory.h | 26 + trunk/arch/arm/mach-imx/include/mach/mmc.h | 15 + trunk/arch/arm/mach-imx/include/mach/mx1ads.h | 36 + .../arch/arm/mach-imx/include/mach/spi_imx.h | 72 + trunk/arch/arm/mach-imx/include/mach/system.h | 40 + .../include/mach/timex.h} | 15 +- .../arm/mach-imx/include/mach/uncompress.h | 71 + .../arch/arm/mach-imx/include/mach/vmalloc.h | 20 + trunk/arch/arm/mach-imx/irq.c | 311 +++ trunk/arch/arm/mach-imx/leds-mx1ads.c | 53 + trunk/arch/arm/mach-imx/leds.c | 31 + trunk/arch/arm/mach-imx/leds.h | 9 + trunk/arch/arm/mach-imx/mx1ads.c | 180 ++ trunk/arch/arm/mach-imx/time.c | 220 ++ trunk/arch/arm/mach-ixp4xx/Kconfig | 6 - trunk/arch/arm/mach-ixp4xx/Makefile | 1 - trunk/arch/arm/mach-ixp4xx/goramo_mlr.c | 507 ----- trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h | 7 +- .../arch/arm/mach-ixp4xx/include/mach/qmgr.h | 69 +- trunk/arch/arm/mach-ixp4xx/ixp4xx_npe.c | 9 + trunk/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c | 135 +- trunk/arch/arm/mach-kirkwood/Kconfig | 6 - trunk/arch/arm/mach-kirkwood/Makefile | 3 - trunk/arch/arm/mach-kirkwood/addr-map.c | 14 +- trunk/arch/arm/mach-kirkwood/common.c | 167 +- trunk/arch/arm/mach-kirkwood/common.h | 4 +- trunk/arch/arm/mach-kirkwood/cpuidle.c | 96 - .../arm/mach-kirkwood/db88f6281-bp-setup.c | 31 +- .../mach-kirkwood/include/mach/bridge-regs.h | 21 - .../arch/arm/mach-kirkwood/include/mach/io.h | 25 - .../arm/mach-kirkwood/include/mach/kirkwood.h | 18 +- trunk/arch/arm/mach-kirkwood/mpp.c | 3 - .../arm/mach-kirkwood/mv88f6281gtw_ge-setup.c | 173 -- trunk/arch/arm/mach-kirkwood/pcie.c | 4 - .../arm/mach-kirkwood/rd88f6192-nas-setup.c | 2 + .../arch/arm/mach-kirkwood/rd88f6281-setup.c | 31 +- .../arch/arm/mach-kirkwood/sheevaplug-setup.c | 32 +- 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trunk/arch/arm/mach-omap2/prcm-common.h | 2 - trunk/arch/arm/mach-omap2/prm.h | 207 +- .../mach-omap2/sdram-micron-mt46h32m32lf-6.h | 55 - .../sdram-qimonda-hyb18m512160af-6.h | 54 - trunk/arch/arm/mach-omap2/sdrc.c | 24 +- trunk/arch/arm/mach-omap2/sdrc2xxx.c | 5 +- trunk/arch/arm/mach-omap2/serial.c | 465 +--- trunk/arch/arm/mach-omap2/sleep24xx.S | 1 + trunk/arch/arm/mach-omap2/sleep34xx.S | 436 ---- trunk/arch/arm/mach-omap2/sram242x.S | 10 +- trunk/arch/arm/mach-omap2/sram243x.S | 10 +- trunk/arch/arm/mach-omap2/sram34xx.S | 129 +- trunk/arch/arm/mach-omap2/timer-gp.c | 13 +- trunk/arch/arm/mach-omap2/timer-mpu.c | 34 - trunk/arch/arm/mach-omap2/usb-musb.c | 21 +- trunk/arch/arm/mach-orion5x/addr-map.c | 14 +- trunk/arch/arm/mach-orion5x/common.c | 47 +- trunk/arch/arm/mach-orion5x/common.h | 2 - .../mach-orion5x/include/mach/bridge-regs.h | 4 +- .../arm/mach-orion5x/include/mach/orion5x.h | 6 - .../arm/mach-orion5x/include/mach/system.h | 2 +- trunk/arch/arm/mach-orion5x/mpp.c | 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trunk/drivers/video/mx3fb.c | 4 +- trunk/drivers/video/omap/hwa742.c | 26 +- trunk/drivers/video/s3c-fb.c | 12 +- trunk/drivers/watchdog/Kconfig | 10 +- trunk/drivers/watchdog/Makefile | 2 +- .../watchdog/{orion_wdt.c => orion5x_wdt.c} | 120 +- trunk/firmware/cis/.gitignore | 1 - trunk/fs/binfmt_flat.c | 46 +- trunk/fs/cachefiles/internal.h | 18 +- trunk/fs/fscache/internal.h | 18 +- trunk/fs/jffs2/erase.c | 7 + trunk/fs/nfs/nfs4proc.c | 9 +- trunk/fs/nfs/nfsroot.c | 2 +- trunk/fs/nfsd/vfs.c | 6 +- trunk/fs/nilfs2/cpfile.c | 6 +- trunk/fs/proc/base.c | 2 +- trunk/fs/sysfs/file.c | 2 +- trunk/fs/xfs/linux-2.6/kmem.h | 2 +- trunk/fs/xfs/xfs_dfrag.c | 8 +- trunk/fs/xfs/xfs_fsops.c | 2 +- trunk/include/drm/drmP.h | 24 - trunk/include/linux/amba/pl022.h | 264 --- trunk/include/linux/amba/serial.h | 3 - trunk/include/linux/auto_fs.h | 3 +- trunk/include/linux/clk.h | 13 - trunk/include/linux/cred.h | 1 - trunk/include/linux/i7300_idle.h | 20 +- trunk/include/linux/input.h | 1 - trunk/include/linux/net_dropmon.h | 1 - .../linux/netfilter/nf_conntrack_tcp.h | 4 - trunk/include/linux/parport.h | 4 - trunk/include/linux/swap.h | 5 - trunk/init/main.c | 3 +- trunk/kernel/async.c | 20 +- trunk/kernel/kexec.c | 2 + trunk/kernel/kmod.c | 4 +- trunk/kernel/power/disk.c | 21 +- trunk/kernel/power/main.c | 7 +- trunk/mm/filemap.c | 6 +- trunk/mm/hugetlb.c | 26 +- trunk/mm/memcontrol.c | 14 +- trunk/mm/oom_kill.c | 24 +- trunk/mm/swap_state.c | 4 +- trunk/mm/truncate.c | 1 - trunk/mm/vmscan.c | 2 - trunk/net/bluetooth/hci_sysfs.c | 6 + trunk/net/core/pktgen.c | 2 +- trunk/net/ipv4/fib_trie.c | 6 +- trunk/net/ipv4/route.c | 60 +- trunk/net/ipv4/tcp_vegas.c | 11 +- trunk/net/ipv6/route.c | 3 - trunk/net/netfilter/nf_conntrack_proto_dccp.c | 4 - trunk/net/netfilter/nf_conntrack_proto_tcp.c | 18 - trunk/net/netfilter/nfnetlink_log.c | 6 - trunk/net/netfilter/xt_hashlimit.c | 2 +- trunk/net/rxrpc/ar-connection.c | 12 +- trunk/net/sched/cls_api.c | 23 +- trunk/net/sched/cls_cgroup.c | 22 +- trunk/net/sunrpc/svcsock.c | 35 +- trunk/net/sunrpc/xprtrdma/svc_rdma_sendto.c | 12 +- .../net/sunrpc/xprtrdma/svc_rdma_transport.c | 10 +- trunk/net/sunrpc/xprtrdma/verbs.c | 3 +- trunk/net/wireless/reg.c | 7 - trunk/net/wireless/wext.c | 7 - trunk/security/tomoyo/tomoyo.c | 6 - trunk/sound/core/pcm_lib.c | 10 +- trunk/sound/core/pcm_native.c | 6 - trunk/sound/pci/hda/hda_intel.c | 1 - trunk/sound/pci/hda/patch_conexant.c | 1 - trunk/sound/pci/hda/patch_realtek.c | 6 - trunk/sound/pci/hda/patch_sigmatel.c | 10 - trunk/sound/soc/s3c24xx/s3c2412-i2s.c | 1 - trunk/sound/soc/s3c24xx/s3c2443-ac97.c | 1 - trunk/sound/soc/s3c24xx/s3c24xx-i2s.c | 2 - trunk/sound/soc/s3c24xx/s3c24xx-pcm.c | 21 +- trunk/sound/usb/usbaudio.c | 2 +- trunk/sound/usb/usbaudio.h | 2 +- trunk/sound/usb/usbmidi.c | 12 +- trunk/sound/usb/usbquirks.h | 2 +- 727 files changed, 10674 insertions(+), 37118 deletions(-) delete mode 100644 trunk/arch/arm/configs/mx21_defconfig delete mode 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create mode 100644 trunk/arch/arm/mach-realview/include/mach/scu.h delete mode 100644 trunk/arch/arm/mach-s3c2410/include/mach/gpio-fns.h delete mode 100644 trunk/arch/arm/mach-s3c6400/include/mach/regs-clock.h delete mode 100644 trunk/arch/arm/mach-s3c6400/mach-smdk6400.c delete mode 100644 trunk/arch/arm/mach-s3c6400/s3c6400.c delete mode 100644 trunk/arch/arm/mach-s3c6400/setup-sdhci.c delete mode 100644 trunk/arch/arm/mach-s3c6410/mach-anw6410.c delete mode 100644 trunk/arch/arm/mach-s3c6410/mach-ncp.c delete mode 100644 trunk/arch/arm/mach-w90x900/clock.c delete mode 100644 trunk/arch/arm/mach-w90x900/clock.h delete mode 100644 trunk/arch/arm/mach-w90x900/gpio.c delete mode 100644 trunk/arch/arm/mach-w90x900/include/mach/clkdev.h delete mode 100644 trunk/arch/arm/mach-w90x900/include/mach/gpio.h delete mode 100644 trunk/arch/arm/mach-w90x900/include/mach/regs-clock.h delete mode 100644 trunk/arch/arm/mach-w90x900/include/mach/regs-usb.h delete mode 100644 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trunk/arch/arm/plat-omap/include/mach/omap44xx.h rename trunk/arch/arm/{mach-omap1 => plat-omap/include/mach}/pm.h (76%) delete mode 100644 trunk/arch/arm/plat-omap/include/mach/smp.h delete mode 100644 trunk/arch/arm/plat-omap/iommu.c delete mode 100644 trunk/arch/arm/plat-omap/iopgtable.h delete mode 100644 trunk/arch/arm/plat-omap/iovmm.c rename trunk/arch/arm/plat-orion/include/plat/{orion_wdt.h => orion5x_wdt.h} (64%) delete mode 100644 trunk/arch/arm/plat-s3c/dev-usb-hsotg.c delete mode 100644 trunk/arch/arm/plat-s3c/dev-usb.c delete mode 100644 trunk/arch/arm/plat-s3c/dma.c delete mode 100644 trunk/arch/arm/plat-s3c/include/plat/dma-core.h delete mode 100644 trunk/arch/arm/plat-s3c/include/plat/dma.h delete mode 100644 trunk/arch/arm/plat-s3c/include/plat/udc-hs.h delete mode 100644 trunk/arch/arm/plat-s3c/include/plat/watchdog-reset.h delete mode 100644 trunk/arch/arm/plat-s3c/pm-gpio.c rename trunk/arch/arm/plat-s3c24xx/include/plat/{dma-plat.h => dma.h} (86%) delete mode 100644 trunk/arch/arm/plat-s3c24xx/include/plat/regs-dma.h delete mode 100644 trunk/arch/arm/plat-s3c64xx/dma.c delete mode 100644 trunk/arch/arm/plat-s3c64xx/include/plat/dma-plat.h delete mode 100644 trunk/arch/arm/plat-s3c64xx/include/plat/pm-core.h delete mode 100644 trunk/arch/arm/plat-s3c64xx/irq-pm.c delete mode 100644 trunk/arch/arm/plat-s3c64xx/pm.c delete mode 100644 trunk/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c delete mode 100644 trunk/arch/arm/plat-s3c64xx/sleep.S create mode 100644 trunk/arch/blackfin/include/asm/.gitignore delete mode 100644 trunk/arch/blackfin/kernel/.gitignore create mode 100644 trunk/arch/powerpc/lib/dma-noncoherent.c delete mode 100644 trunk/arch/powerpc/mm/dma-noncoherent.c delete mode 100644 trunk/drivers/ata/pata_palmld.c delete mode 100644 trunk/drivers/char/hw_random/mxc-rnga.c delete mode 100644 trunk/drivers/spi/amba-pl022.c rename trunk/drivers/watchdog/{orion_wdt.c => orion5x_wdt.c} (64%) delete mode 100644 trunk/firmware/cis/.gitignore delete mode 100644 trunk/include/linux/amba/pl022.h diff --git a/[refs] b/[refs] index 1aeea3f1a8d3..09912fe8084d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2631182bf93919577730e6a6c4345308db590057 +refs/heads/master: 412b400278ed0f71712387d0b9b31cbdd8a18efc diff --git a/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt b/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt index 948c8718d967..ea7ccfc4b274 100644 --- a/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt +++ b/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt @@ -51,7 +51,7 @@ PIN Numbers ----------- Each pin has an unique number associated with it in regs-gpio.h, - eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell + eg S3C2410_GPA0 or S3C2410_GPF1. These defines are used to tell the GPIO functions which pin is to be used. @@ -65,11 +65,11 @@ Configuring a pin Eg: - s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0); - s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); + s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); + s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); - which would turn GPA(0) into the lowest Address line A0, and set - GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line. + which would turn GPA0 into the lowest Address line A0, and set + GPE8 to be connected to the SDIO/MMC controller's SDDAT1 line. Reading the current configuration diff --git a/trunk/Documentation/hwmon/sysfs-interface b/trunk/Documentation/hwmon/sysfs-interface index 004ee161721e..2f10ce6a879f 100644 --- a/trunk/Documentation/hwmon/sysfs-interface +++ b/trunk/Documentation/hwmon/sysfs-interface @@ -150,11 +150,6 @@ fan[1-*]_min Fan minimum value Unit: revolution/min (RPM) RW -fan[1-*]_max Fan maximum value - Unit: revolution/min (RPM) - Only rarely supported by the hardware. - RW - fan[1-*]_input Fan input value. Unit: revolution/min (RPM) RO @@ -395,7 +390,6 @@ OR in[0-*]_min_alarm in[0-*]_max_alarm fan[1-*]_min_alarm -fan[1-*]_max_alarm temp[1-*]_min_alarm temp[1-*]_max_alarm temp[1-*]_crit_alarm diff --git a/trunk/Documentation/input/multi-touch-protocol.txt b/trunk/Documentation/input/multi-touch-protocol.txt index a12ea3b586e6..9f09557aea39 100644 --- a/trunk/Documentation/input/multi-touch-protocol.txt +++ b/trunk/Documentation/input/multi-touch-protocol.txt @@ -18,12 +18,8 @@ Usage Anonymous finger details are sent sequentially as separate packets of ABS events. Only the ABS_MT events are recognized as part of a finger packet. The end of a packet is marked by calling the input_mt_sync() -function, which generates a SYN_MT_REPORT event. This instructs the -receiver to accept the data for the current finger and prepare to receive -another. The end of a multi-touch transfer is marked by calling the usual -input_sync() function. This instructs the receiver to act upon events -accumulated since last EV_SYN/SYN_REPORT and prepare to receive a new -set of events/packets. +function, which generates a SYN_MT_REPORT event. The end of multi-touch +transfer is marked by calling the usual input_sync() function. A set of ABS_MT events with the desired properties is defined. The events are divided into categories, to allow for partial implementation. The @@ -31,26 +27,11 @@ minimum set consists of ABS_MT_TOUCH_MAJOR, ABS_MT_POSITION_X and ABS_MT_POSITION_Y, which allows for multiple fingers to be tracked. If the device supports it, the ABS_MT_WIDTH_MAJOR may be used to provide the size of the approaching finger. Anisotropy and direction may be specified with -ABS_MT_TOUCH_MINOR, ABS_MT_WIDTH_MINOR and ABS_MT_ORIENTATION. The -ABS_MT_TOOL_TYPE may be used to specify whether the touching tool is a -finger or a pen or something else. Devices with more granular information -may specify general shapes as blobs, i.e., as a sequence of rectangular -shapes grouped together by an ABS_MT_BLOB_ID. Finally, for the few devices -that currently support it, the ABS_MT_TRACKING_ID event may be used to -report finger tracking from hardware [5]. - -Here is what a minimal event sequence for a two-finger touch would look -like: - - ABS_MT_TOUCH_MAJOR - ABS_MT_POSITION_X - ABS_MT_POSITION_Y - SYN_MT_REPORT - ABS_MT_TOUCH_MAJOR - ABS_MT_POSITION_X - ABS_MT_POSITION_Y - SYN_MT_REPORT - SYN_REPORT +ABS_MT_TOUCH_MINOR, ABS_MT_WIDTH_MINOR and ABS_MT_ORIENTATION. Devices with +more granular information may specify general shapes as blobs, i.e., as a +sequence of rectangular shapes grouped together by an +ABS_MT_BLOB_ID. Finally, the ABS_MT_TOOL_TYPE may be used to specify +whether the touching tool is a finger or a pen or something else. Event Semantics @@ -63,24 +44,24 @@ ABS_MT_TOUCH_MAJOR The length of the major axis of the contact. The length should be given in surface units. If the surface has an X times Y resolution, the largest -possible value of ABS_MT_TOUCH_MAJOR is sqrt(X^2 + Y^2), the diagonal [4]. +possible value of ABS_MT_TOUCH_MAJOR is sqrt(X^2 + Y^2), the diagonal. ABS_MT_TOUCH_MINOR The length, in surface units, of the minor axis of the contact. If the -contact is circular, this event can be omitted [4]. +contact is circular, this event can be omitted. ABS_MT_WIDTH_MAJOR The length, in surface units, of the major axis of the approaching tool. This should be understood as the size of the tool itself. The orientation of the contact and the approaching tool are assumed to be the -same [4]. +same. ABS_MT_WIDTH_MINOR The length, in surface units, of the minor axis of the approaching -tool. Omit if circular [4]. +tool. Omit if circular. The above four values can be used to derive additional information about the contact. The ratio ABS_MT_TOUCH_MAJOR / ABS_MT_WIDTH_MAJOR approximates @@ -89,17 +70,14 @@ different characteristic widths [1]. ABS_MT_ORIENTATION -The orientation of the ellipse. The value should describe a signed quarter -of a revolution clockwise around the touch center. The signed value range -is arbitrary, but zero should be returned for a finger aligned along the Y -axis of the surface, a negative value when finger is turned to the left, and -a positive value when finger turned to the right. When completely aligned with -the X axis, the range max should be returned. Orientation can be omitted -if the touching object is circular, or if the information is not available -in the kernel driver. Partial orientation support is possible if the device -can distinguish between the two axis, but not (uniquely) any values in -between. In such cases, the range of ABS_MT_ORIENTATION should be [0, 1] -[4]. +The orientation of the ellipse. The value should describe half a revolution +clockwise around the touch center. The scale of the value is arbitrary, but +zero should be returned for an ellipse aligned along the Y axis of the +surface. As an example, an index finger placed straight onto the axis could +return zero orientation, something negative when twisted to the left, and +something positive when twisted to the right. This value can be omitted if +the touching object is circular, or if the information is not available in +the kernel driver. ABS_MT_POSITION_X @@ -120,35 +98,8 @@ ABS_MT_BLOB_ID The BLOB_ID groups several packets together into one arbitrarily shaped contact. This is a low-level anonymous grouping, and should not be confused -with the high-level trackingID [5]. Most kernel drivers will not have blob -capability, and can safely omit the event. - -ABS_MT_TRACKING_ID - -The TRACKING_ID identifies an initiated contact throughout its life cycle -[5]. There are currently only a few devices that support it, so this event -should normally be omitted. - - -Event Computation ------------------ - -The flora of different hardware unavoidably leads to some devices fitting -better to the MT protocol than others. To simplify and unify the mapping, -this section gives recipes for how to compute certain events. - -For devices reporting contacts as rectangular shapes, signed orientation -cannot be obtained. Assuming X and Y are the lengths of the sides of the -touching rectangle, here is a simple formula that retains the most -information possible: - - ABS_MT_TOUCH_MAJOR := max(X, Y) - ABS_MT_TOUCH_MINOR := min(X, Y) - ABS_MT_ORIENTATION := bool(X > Y) - -The range of ABS_MT_ORIENTATION should be set to [0, 1], to indicate that -the device can distinguish between a finger along the Y axis (0) and a -finger along the X axis (1). +with the high-level contactID, explained below. Most kernel drivers will +not have this capability, and can safely omit the event. Finger Tracking @@ -158,18 +109,14 @@ The kernel driver should generate an arbitrary enumeration of the set of anonymous contacts currently on the surface. The order in which the packets appear in the event stream is not important. -The process of finger tracking, i.e., to assign a unique trackingID to each +The process of finger tracking, i.e., to assign a unique contactID to each initiated contact on the surface, is left to user space; preferably the -multi-touch X driver [3]. In that driver, the trackingID stays the same and +multi-touch X driver [3]. In that driver, the contactID stays the same and unique until the contact vanishes (when the finger leaves the surface). The problem of assigning a set of anonymous fingers to a set of identified fingers is a euclidian bipartite matching problem at each event update, and relies on a sufficiently rapid update rate. -There are a few devices that support trackingID in hardware. User space can -make use of these native identifiers to reduce bandwidth and cpu usage. - - Notes ----- @@ -189,7 +136,5 @@ could be used to derive tilt. time of writing (April 2009), the MT protocol is not yet merged, and the prototype implements finger matching, basic mouse support and two-finger scrolling. The project aims at improving the quality of current multi-touch -functionality available in the Synaptics X driver, and in addition +functionality available in the synaptics X driver, and in addition implement more advanced gestures. -[4] See the section on event computation. -[5] See the section on finger tracking. diff --git a/trunk/Documentation/kernel-parameters.txt b/trunk/Documentation/kernel-parameters.txt index fd5cac013037..e87bdbfbcc75 100644 --- a/trunk/Documentation/kernel-parameters.txt +++ b/trunk/Documentation/kernel-parameters.txt @@ -1535,10 +1535,6 @@ and is between 256 and 4096 characters. It is defined in the file register save and restore. The kernel will only save legacy floating-point registers on task switch. - noxsave [BUGS=X86] Disables x86 extended register state save - and restore using xsave. The kernel will fallback to - enabling legacy floating-point and sse state. - nohlt [BUGS=ARM,SH] Tells the kernel that the sleep(SH) or wfi(ARM) instruction doesn't work correctly and not to use it. This is also useful when using JTAG debugger. diff --git a/trunk/Documentation/sound/alsa/HD-Audio-Models.txt b/trunk/Documentation/sound/alsa/HD-Audio-Models.txt index 322869fc8a9e..8eec05bc079e 100644 --- a/trunk/Documentation/sound/alsa/HD-Audio-Models.txt +++ b/trunk/Documentation/sound/alsa/HD-Audio-Models.txt @@ -334,7 +334,6 @@ STAC9227/9228/9229/927x ref-no-jd Reference board without HP/Mic jack detection 3stack D965 3stack 5stack D965 5stack + SPDIF - 5stack-no-fp D965 5stack without front panel dell-3stack Dell Dimension E520 dell-bios Fixes with Dell BIOS setup auto BIOS setup (default) diff --git a/trunk/Documentation/sound/alsa/Procfile.txt b/trunk/Documentation/sound/alsa/Procfile.txt index cfac20cf9e33..bba2dbb79d81 100644 --- a/trunk/Documentation/sound/alsa/Procfile.txt +++ b/trunk/Documentation/sound/alsa/Procfile.txt @@ -104,11 +104,6 @@ card*/pcm*/xrun_debug When this value is greater than 1, the driver will show the stack trace additionally. This may help the debugging. - Since 2.6.30, this option also enables the hwptr check using - jiffies. This detects spontaneous invalid pointer callback - values, but can be lead to too much corrections for a (mostly - buggy) hardware that doesn't give smooth pointer updates. - card*/pcm*/sub*/info The general information of this PCM sub-stream. diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 581fedcce2b5..77cbfb1a696c 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -434,7 +434,7 @@ F: arch/alpha/ AMD GEODE CS5536 USB DEVICE CONTROLLER DRIVER P: Thomas Dahlmann -M: dahlmann.thomas@arcor.de +M: thomas.dahlmann@amd.com L: linux-geode@lists.infradead.org (moderated for non-subscribers) S: Supported F: drivers/usb/gadget/amd5536udc.* @@ -624,7 +624,6 @@ M: paulius.zaleckas@teltonika.lt L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) T: git git://gitorious.org/linux-gemini/mainline.git S: Maintained -F: arch/arm/mach-gemini/ ARM/EBSA110 MACHINE SUPPORT P: Russell King @@ -651,7 +650,6 @@ P: Paulius Zaleckas M: paulius.zaleckas@teltonika.lt L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) S: Maintained -F: arch/arm/mm/*-fa* ARM/FOOTBRIDGE ARCHITECTURE P: Russell King @@ -1134,17 +1132,17 @@ F: fs/bfs/ F: include/linux/bfs_fs.h BLACKFIN ARCHITECTURE -P: Mike Frysinger -M: vapier@gentoo.org +P: Bryan Wu +M: cooloney@kernel.org L: uclinux-dist-devel@blackfin.uclinux.org W: http://blackfin.uclinux.org S: Supported F: arch/blackfin/ BLACKFIN EMAC DRIVER -P: Michael Hennerich -M: michael.hennerich@analog.com -L: uclinux-dist-devel@blackfin.uclinux.org +P: Bryan Wu +M: cooloney@kernel.org +L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) W: http://blackfin.uclinux.org S: Supported F: drivers/net/bfin_mac.* @@ -1152,7 +1150,7 @@ F: drivers/net/bfin_mac.* BLACKFIN RTC DRIVER P: Mike Frysinger M: vapier.adi@gmail.com -L: uclinux-dist-devel@blackfin.uclinux.org +L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) W: http://blackfin.uclinux.org S: Supported F: drivers/rtc/rtc-bfin.c @@ -1160,7 +1158,7 @@ F: drivers/rtc/rtc-bfin.c BLACKFIN SERIAL DRIVER P: Sonic Zhang M: sonic.zhang@analog.com -L: uclinux-dist-devel@blackfin.uclinux.org +L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) W: http://blackfin.uclinux.org S: Supported F: drivers/serial/bfin_5xx.c @@ -1168,7 +1166,7 @@ F: drivers/serial/bfin_5xx.c BLACKFIN WATCHDOG DRIVER P: Mike Frysinger M: vapier.adi@gmail.com -L: uclinux-dist-devel@blackfin.uclinux.org +L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) W: http://blackfin.uclinux.org S: Supported F: drivers/watchdog/bfin_wdt.c @@ -1176,7 +1174,7 @@ F: drivers/watchdog/bfin_wdt.c BLACKFIN I2C TWI DRIVER P: Sonic Zhang M: sonic.zhang@analog.com -L: uclinux-dist-devel@blackfin.uclinux.org +L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) W: http://blackfin.uclinux.org/ S: Supported F: drivers/i2c/busses/i2c-bfin-twi.c @@ -1542,13 +1540,6 @@ W: http://www.fi.muni.cz/~kas/cosa/ S: Maintained F: drivers/net/wan/cosa* -CPMAC ETHERNET DRIVER -P: Florian Fainelli -M: florian@openwrt.org -L: netdev@vger.kernel.org -S: Maintained -F: drivers/net/cpmac.c - CPU FREQUENCY DRIVERS P: Dave Jones M: davej@redhat.com @@ -1980,8 +1971,8 @@ F: include/linux/edac.h EDAC-E752X P: Mark Gross -M: mark.gross@intel.com P: Doug Thompson +M: mark.gross@intel.com M: dougthompson@xmission.com L: bluesmoke-devel@lists.sourceforge.net (moderated for non-subscribers) W: bluesmoke.sourceforge.net @@ -2258,7 +2249,7 @@ P: Li Yang M: leoli@freescale.com P: Zhang Wei M: zw@zh-kernel.org -L: linuxppc-dev@ozlabs.org +L: linuxppc-embedded@ozlabs.org L: linux-kernel@vger.kernel.org S: Maintained F: drivers/dma/fsldma.* @@ -4136,69 +4127,6 @@ S: Maintained F: drivers/video/riva/ F: drivers/video/nvidia/ -OMAP SUPPORT -P: Tony Lindgren -M: tony@atomide.com -L: linux-omap@vger.kernel.org -W: http://www.muru.com/linux/omap/ -W: http://linux.omap.com/ -T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git -S: Maintained -F: arch/arm/*omap* - -OMAP CLOCK FRAMEWORK SUPPORT -P: Paul Walmsley -M: paul@pwsan.com -L: linux-omap@vger.kernel.org -S: Maintained -F: arch/arm/*omap*/*clock* - -OMAP POWER MANAGEMENT SUPPORT -P: Kevin Hilman -M: khilman@deeprootsystems.com -L: linux-omap@vger.kernel.org -S: Maintained -F: arch/arm/*omap*/*pm* - -OMAP AUDIO SUPPORT -P: Jarkko Nikula -M: jhnikula@gmail.com -L: alsa-devel@alsa-project.org (subscribers-only) -L: linux-omap@vger.kernel.org -S: Maintained -F: sound/soc/omap/ - -OMAP FRAMEBUFFER SUPPORT -P: Imre Deak -M: imre.deak@nokia.com -L: linux-fbdev-devel@lists.sourceforge.net (moderated for non-subscribers) -L: linux-omap@vger.kernel.org -S: Maintained -F: drivers/video/omap/ - -OMAP MMC SUPPORT -P: Jarkko Lavinen -M: jarkko.lavinen@nokia.com -L: linux-kernel@vger.kernel.org -L: linux-omap@vger.kernel.org -S: Maintained -F: drivers/mmc/host/*omap* - -OMAP RANDOM NUMBER GENERATOR SUPPORT -P: Deepak Saxena -M: dsaxena@plexity.net -S: Maintained -F: drivers/char/hw_random/omap-rng.c - -OMAP USB SUPPORT -P: Felipe Balbi -M: felipe.balbi@nokia.com -P: David Brownell -M: dbrownell@users.sourceforge.net -L: linux-usb@vger.kernel.org -L: linux-omap@vger.kernel.org -S: Maintained - OMFS FILESYSTEM P: Bob Copeland M: me@bobcopeland.com @@ -5587,6 +5515,20 @@ F: drivers/misc/tifm* F: drivers/mmc/host/tifm_sd.c F: include/linux/tifm.h +TI OMAP MMC INTERFACE DRIVER +P: Carlos Aguiar, Anderson Briglia and Syed Khasim +M: linux-omap@vger.kernel.org +W: http://linux.omap.com +W: http://www.muru.com/linux/omap/ +S: Maintained +F: drivers/mmc/host/omap.c + +TI OMAP RANDOM NUMBER GENERATOR SUPPORT +P: Deepak Saxena +M: dsaxena@plexity.net +S: Maintained +F: drivers/char/hw_random/omap-rng.c + TIPC NETWORK LAYER P: Per Liden M: per.liden@ericsson.com diff --git a/trunk/Makefile b/trunk/Makefile index 610d1c332c45..739fd34a72a2 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 6 SUBLEVEL = 30 -EXTRAVERSION = -rc8 +EXTRAVERSION = -rc7 NAME = Man-Eating Seals of Antiquity # *DOCUMENTATION* diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 430d2b756165..a8d88af7fe88 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -34,12 +34,15 @@ config SYS_SUPPORTS_APM_EMULATION config GENERIC_GPIO bool + default n config GENERIC_TIME bool + default n config GENERIC_CLOCKEVENTS bool + default n config GENERIC_CLOCKEVENTS_BROADCAST bool @@ -52,6 +55,7 @@ config MMU config NO_IOPORT bool + default n config EISA bool @@ -122,9 +126,11 @@ config RWSEM_XCHGADD_ALGORITHM config ARCH_HAS_ILOG2_U32 bool + default n config ARCH_HAS_ILOG2_U64 bool + default n config GENERIC_HWEIGHT bool @@ -247,14 +253,6 @@ config ARCH_CLPS711X help Support for Cirrus Logic 711x/721x based boards. -config ARCH_GEMINI - bool "Cortina Systems Gemini" - select CPU_FA526 - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - help - Support for the Cortina Systems Gemini family SoCs - config ARCH_EBSA110 bool "EBSA-110" select CPU_SA110 @@ -279,6 +277,14 @@ config ARCH_EP93XX help This enables support for the Cirrus EP93xx series of CPUs. +config ARCH_GEMINI + bool "Cortina Systems Gemini" + select CPU_FA526 + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + Support for the Cortina Systems Gemini family SoCs + config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 @@ -287,17 +293,6 @@ config ARCH_FOOTBRIDGE Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. -config ARCH_MXC - bool "Freescale MXC/iMX-based" - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - select ARCH_MTD_XIP - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK - help - Support for Freescale MXC/iMX-based family of processors - config ARCH_NETX bool "Hilscher NetX based" select CPU_ARM926T @@ -314,6 +309,15 @@ config ARCH_H720X help This enables support for systems based on the Hynix HMS720x +config ARCH_IMX + bool "IMX" + select CPU_ARM920T + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + help + Support for Motorola's i.MX family of processors (MX1, MXL). + config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU @@ -394,7 +398,6 @@ config ARCH_KIRKWOOD select CPU_FEROCEON select PCI select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION @@ -402,6 +405,28 @@ config ARCH_KIRKWOOD Support for the following Marvell Kirkwood series SoCs: 88F6180, 88F6192 and 88F6281. +config ARCH_KS8695 + bool "Micrel/Kendin KS8695" + select CPU_ARM922T + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based + System-on-Chip devices. + +config ARCH_NS9XXX + bool "NetSilicon NS9xxx" + select CPU_ARM926T + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select HAVE_CLK + help + Say Y here if you intend to run this kernel on a NetSilicon NS9xxx + System. + + + config ARCH_LOKI bool "Marvell Loki (88RC8480)" select CPU_FEROCEON @@ -416,7 +441,6 @@ config ARCH_MV78XX0 select CPU_FEROCEON select PCI select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION @@ -424,13 +448,23 @@ config ARCH_MV78XX0 Support for the following Marvell MV78xx0 series SoCs: MV781x0, MV782x0. +config ARCH_MXC + bool "Freescale MXC/iMX-based" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select ARCH_MTD_XIP + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK + help + Support for Freescale MXC/iMX-based family of processors + config ARCH_ORION5X bool "Marvell Orion" depends on MMU select CPU_FEROCEON select PCI select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION @@ -439,52 +473,6 @@ config ARCH_ORION5X Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), Orion-2 (5281), Orion-1-90 (6183). -config ARCH_MMP - bool "Marvell PXA168/910" - depends on MMU - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK - select COMMON_CLKDEV - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - select TICK_ONESHOT - select PLAT_PXA - help - Support for Marvell's PXA168/910 processor line. - -config ARCH_KS8695 - bool "Micrel/Kendin KS8695" - select CPU_ARM922T - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - help - Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based - System-on-Chip devices. - -config ARCH_NS9XXX - bool "NetSilicon NS9xxx" - select CPU_ARM926T - select GENERIC_GPIO - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - select HAVE_CLK - help - Say Y here if you intend to run this kernel on a NetSilicon NS9xxx - System. - - - -config ARCH_W90X900 - bool "Nuvoton W90X900 CPU" - select CPU_ARM926T - select ARCH_REQUIRE_GPIOLIB - select GENERIC_GPIO - select COMMON_CLKDEV - help - Support for Nuvoton (Winbond logic dept.) ARM9 processor,You - can login www.mcuos.com or www.nuvoton.com to know more. - config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" select CPU_ARM926T @@ -507,16 +495,19 @@ config ARCH_PXA help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. -config ARCH_MSM - bool "Qualcomm MSM" - select CPU_V6 +config ARCH_MMP + bool "Marvell PXA168/910" + depends on MMU + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK + select COMMON_CLKDEV select GENERIC_TIME select GENERIC_CLOCKEVENTS + select TICK_ONESHOT + select PLAT_PXA help - Support for Qualcomm MSM7K based systems. This runs on the ARM11 - apps processor of the MSM7K and depends on a shared memory - interface to the ARM9 modem processor which runs the baseband stack - and controls some vital subsystems (clock and power control, etc). + Support for Marvell's PXA168/910 processor line. config ARCH_RPC bool "RiscPC" @@ -596,7 +587,6 @@ config ARCH_DAVINCI select ZONE_DMA select HAVE_IDE select COMMON_CLKDEV - select GENERIC_ALLOCATOR help Support for TI's DaVinci platform. @@ -610,6 +600,24 @@ config ARCH_OMAP help Support for TI's OMAP platform (OMAP1 and OMAP2). +config ARCH_MSM + bool "Qualcomm MSM" + select CPU_V6 + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + help + Support for Qualcomm MSM7K based systems. This runs on the ARM11 + apps processor of the MSM7K and depends on a shared memory + interface to the ARM9 modem processor which runs the baseband stack + and controls some vital subsystems (clock and power control, etc). + +config ARCH_W90X900 + bool "Nuvoton W90X900 CPU" + select CPU_ARM926T + help + Support for Nuvoton (Winbond logic dept.) ARM9 processor,You + can login www.mcuos.com or www.nuvoton.com to know more. + endchoice source "arch/arm/mach-clps711x/Kconfig" @@ -675,6 +683,8 @@ endif source "arch/arm/mach-lh7a40x/Kconfig" +source "arch/arm/mach-imx/Kconfig" + source "arch/arm/mach-h720x/Kconfig" source "arch/arm/mach-versatile/Kconfig" @@ -849,10 +859,8 @@ source "kernel/time/Kconfig" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP ||ARCH_OMAP4) - depends on GENERIC_CLOCKEVENTS + depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || MACH_REALVIEW_PB11MP) select USE_GENERIC_SMP_HELPERS - select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4) help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -870,18 +878,6 @@ config SMP If you don't know what to do here, say N. -config HAVE_ARM_SCU - bool - depends on SMP - help - This option enables support for the ARM system coherency unit - -config HAVE_ARM_TWD - bool - depends on SMP - help - This options enables support for the ARM timer and watchdog unit - choice prompt "Memory split" default VMSPLIT_3G @@ -920,9 +916,8 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" - depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP || ARCH_OMAP4) + depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP) default y - select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4) help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system @@ -984,6 +979,7 @@ config OABI_COMPAT config ARCH_HAS_HOLES_MEMORYMODEL bool + default n # Discontigmem is deprecated config ARCH_DISCONTIGMEM_ENABLE @@ -1026,7 +1022,7 @@ source "mm/Kconfig" config LEDS bool "Timer and CPU usage LEDs" depends on ARCH_CDB89712 || ARCH_EBSA110 || \ - ARCH_EBSA285 || ARCH_INTEGRATOR || \ + ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \ ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ @@ -1192,7 +1188,7 @@ endmenu menu "CPU Power Management" -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA) +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) source "drivers/cpufreq/Kconfig" @@ -1217,11 +1213,14 @@ config CPU_FREQ_INTEGRATOR If in doubt, say Y. -config CPU_FREQ_PXA - bool - depends on CPU_FREQ && ARCH_PXA && PXA25x - default y - select CPU_FREQ_DEFAULT_GOV_USERSPACE +config CPU_FREQ_IMX + tristate "CPUfreq driver for i.MX CPUs" + depends on ARCH_IMX && CPU_FREQ + default n + help + This enables the CPUfreq driver for i.MX CPUs. + + If in doubt, say N. endif diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index e8ab87750e9b..e84729bf13d4 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -99,69 +99,64 @@ CHECKFLAGS += -D__arm__ #Default value head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o textofs-y := 0x00008000 -textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 -# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory + + machine-$(CONFIG_ARCH_RPC) := rpc + machine-$(CONFIG_ARCH_EBSA110) := ebsa110 + machine-$(CONFIG_FOOTBRIDGE) := footbridge + machine-$(CONFIG_ARCH_SHARK) := shark + machine-$(CONFIG_ARCH_SA1100) := sa1100 ifeq ($(CONFIG_ARCH_SA1100),y) -textofs-$(CONFIG_SA1111) := 0x00208000 +# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory + textofs-$(CONFIG_SA1111) := 0x00208000 endif - -# Machine directory name. This list is sorted alphanumerically -# by CONFIG_* macro name. -machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 -machine-$(CONFIG_ARCH_AT91) := at91 -machine-$(CONFIG_ARCH_CLPS711X) := clps711x -machine-$(CONFIG_ARCH_DAVINCI) := davinci -machine-$(CONFIG_ARCH_EBSA110) := ebsa110 -machine-$(CONFIG_ARCH_EP93XX) := ep93xx -machine-$(CONFIG_ARCH_GEMINI) := gemini -machine-$(CONFIG_ARCH_H720X) := h720x -machine-$(CONFIG_ARCH_INTEGRATOR) := integrator -machine-$(CONFIG_ARCH_IOP13XX) := iop13xx -machine-$(CONFIG_ARCH_IOP32X) := iop32x -machine-$(CONFIG_ARCH_IOP33X) := iop33x -machine-$(CONFIG_ARCH_IXP2000) := ixp2000 -machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx -machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx -machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood -machine-$(CONFIG_ARCH_KS8695) := ks8695 -machine-$(CONFIG_ARCH_L7200) := l7200 -machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x -machine-$(CONFIG_ARCH_LOKI) := loki -machine-$(CONFIG_ARCH_MMP) := mmp -machine-$(CONFIG_ARCH_MSM) := msm -machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 -machine-$(CONFIG_ARCH_MX1) := mx1 -machine-$(CONFIG_ARCH_MX2) := mx2 -machine-$(CONFIG_ARCH_MX3) := mx3 -machine-$(CONFIG_ARCH_NETX) := netx -machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx -machine-$(CONFIG_ARCH_OMAP1) := omap1 -machine-$(CONFIG_ARCH_OMAP2) := omap2 -machine-$(CONFIG_ARCH_OMAP3) := omap2 -machine-$(CONFIG_ARCH_OMAP4) := omap2 -machine-$(CONFIG_ARCH_ORION5X) := orion5x -machine-$(CONFIG_ARCH_PNX4008) := pnx4008 -machine-$(CONFIG_ARCH_PXA) := pxa -machine-$(CONFIG_ARCH_REALVIEW) := realview -machine-$(CONFIG_ARCH_RPC) := rpc -machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 -machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 -machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 -machine-$(CONFIG_ARCH_SA1100) := sa1100 -machine-$(CONFIG_ARCH_SHARK) := shark -machine-$(CONFIG_ARCH_VERSATILE) := versatile -machine-$(CONFIG_ARCH_W90X900) := w90x900 -machine-$(CONFIG_FOOTBRIDGE) := footbridge - -# Platform directory name. This list is sorted alphanumerically -# by CONFIG_* macro name. -plat-$(CONFIG_ARCH_MXC) := mxc -plat-$(CONFIG_ARCH_OMAP) := omap -plat-$(CONFIG_PLAT_IOP) := iop -plat-$(CONFIG_PLAT_ORION) := orion -plat-$(CONFIG_PLAT_PXA) := pxa -plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c -plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c + machine-$(CONFIG_ARCH_PXA) := pxa + machine-$(CONFIG_ARCH_MMP) := mmp + plat-$(CONFIG_PLAT_PXA) := pxa + machine-$(CONFIG_ARCH_L7200) := l7200 + machine-$(CONFIG_ARCH_INTEGRATOR) := integrator + machine-$(CONFIG_ARCH_GEMINI) := gemini + textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 + machine-$(CONFIG_ARCH_CLPS711X) := clps711x + machine-$(CONFIG_ARCH_IOP32X) := iop32x + machine-$(CONFIG_ARCH_IOP33X) := iop33x + machine-$(CONFIG_ARCH_IOP13XX) := iop13xx + plat-$(CONFIG_PLAT_IOP) := iop + machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx + machine-$(CONFIG_ARCH_IXP2000) := ixp2000 + machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx + machine-$(CONFIG_ARCH_OMAP1) := omap1 + machine-$(CONFIG_ARCH_OMAP2) := omap2 + machine-$(CONFIG_ARCH_OMAP3) := omap2 + plat-$(CONFIG_ARCH_OMAP) := omap + machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 + machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 + plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c + machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 + plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c + machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x + machine-$(CONFIG_ARCH_VERSATILE) := versatile + machine-$(CONFIG_ARCH_IMX) := imx + machine-$(CONFIG_ARCH_H720X) := h720x + machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 + machine-$(CONFIG_ARCH_REALVIEW) := realview + machine-$(CONFIG_ARCH_AT91) := at91 + machine-$(CONFIG_ARCH_EP93XX) := ep93xx + machine-$(CONFIG_ARCH_PNX4008) := pnx4008 + machine-$(CONFIG_ARCH_NETX) := netx + machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx + machine-$(CONFIG_ARCH_DAVINCI) := davinci + machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood + machine-$(CONFIG_ARCH_KS8695) := ks8695 + plat-$(CONFIG_ARCH_MXC) := mxc + machine-$(CONFIG_ARCH_MX2) := mx2 + machine-$(CONFIG_ARCH_MX3) := mx3 + machine-$(CONFIG_ARCH_MX1) := mx1 + machine-$(CONFIG_ARCH_ORION5X) := orion5x + plat-$(CONFIG_PLAT_ORION) := orion + machine-$(CONFIG_ARCH_MSM) := msm + machine-$(CONFIG_ARCH_LOKI) := loki + machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 + machine-$(CONFIG_ARCH_W90X900) := w90x900 ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/trunk/arch/arm/common/Kconfig b/trunk/arch/arm/common/Kconfig index 08f27862d09d..a2cd9beaf37d 100644 --- a/trunk/arch/arm/common/Kconfig +++ b/trunk/arch/arm/common/Kconfig @@ -4,14 +4,6 @@ config ARM_GIC config ARM_VIC bool -config ARM_VIC_NR - int - default 2 - depends on ARM_VIC - help - The maximum number of VICs available in the system, for - power management. - config ICST525 bool diff --git a/trunk/arch/arm/common/clkdev.c b/trunk/arch/arm/common/clkdev.c index f37afd9422f3..5589444ff437 100644 --- a/trunk/arch/arm/common/clkdev.c +++ b/trunk/arch/arm/common/clkdev.c @@ -135,24 +135,6 @@ struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id, } EXPORT_SYMBOL(clkdev_alloc); -int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, - struct device *dev) -{ - struct clk *r = clk_get(dev, id); - struct clk_lookup *l; - - if (IS_ERR(r)) - return PTR_ERR(r); - - l = clkdev_alloc(r, alias, alias_dev_name); - clk_put(r); - if (!l) - return -ENODEV; - clkdev_add(l); - return 0; -} -EXPORT_SYMBOL(clk_add_alias); - /* * clkdev_drop - remove a clock dynamically allocated */ diff --git a/trunk/arch/arm/common/vic.c b/trunk/arch/arm/common/vic.c index 887c6eb3a18a..b2a781d9ce05 100644 --- a/trunk/arch/arm/common/vic.c +++ b/trunk/arch/arm/common/vic.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include @@ -40,219 +39,11 @@ static void vic_unmask_irq(unsigned int irq) writel(1 << irq, base + VIC_INT_ENABLE); } -/** - * vic_init2 - common initialisation code - * @base: Base of the VIC. - * - * Common initialisation code for registeration - * and resume. -*/ -static void vic_init2(void __iomem *base) -{ - int i; - - for (i = 0; i < 16; i++) { - void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); - writel(VIC_VECT_CNTL_ENABLE | i, reg); - } - - writel(32, base + VIC_PL190_DEF_VECT_ADDR); -} - -#if defined(CONFIG_PM) -/** - * struct vic_device - VIC PM device - * @sysdev: The system device which is registered. - * @irq: The IRQ number for the base of the VIC. - * @base: The register base for the VIC. - * @resume_sources: A bitmask of interrupts for resume. - * @resume_irqs: The IRQs enabled for resume. - * @int_select: Save for VIC_INT_SELECT. - * @int_enable: Save for VIC_INT_ENABLE. - * @soft_int: Save for VIC_INT_SOFT. - * @protect: Save for VIC_PROTECT. - */ -struct vic_device { - struct sys_device sysdev; - - void __iomem *base; - int irq; - u32 resume_sources; - u32 resume_irqs; - u32 int_select; - u32 int_enable; - u32 soft_int; - u32 protect; -}; - -/* we cannot allocate memory when VICs are initially registered */ -static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; - -static inline struct vic_device *to_vic(struct sys_device *sys) -{ - return container_of(sys, struct vic_device, sysdev); -} - -static int vic_id; - -static int vic_class_resume(struct sys_device *dev) -{ - struct vic_device *vic = to_vic(dev); - void __iomem *base = vic->base; - - printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); - - /* re-initialise static settings */ - vic_init2(base); - - writel(vic->int_select, base + VIC_INT_SELECT); - writel(vic->protect, base + VIC_PROTECT); - - /* set the enabled ints and then clear the non-enabled */ - writel(vic->int_enable, base + VIC_INT_ENABLE); - writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); - - /* and the same for the soft-int register */ - - writel(vic->soft_int, base + VIC_INT_SOFT); - writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); - - return 0; -} - -static int vic_class_suspend(struct sys_device *dev, pm_message_t state) -{ - struct vic_device *vic = to_vic(dev); - void __iomem *base = vic->base; - - printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); - - vic->int_select = readl(base + VIC_INT_SELECT); - vic->int_enable = readl(base + VIC_INT_ENABLE); - vic->soft_int = readl(base + VIC_INT_SOFT); - vic->protect = readl(base + VIC_PROTECT); - - /* set the interrupts (if any) that are used for - * resuming the system */ - - writel(vic->resume_irqs, base + VIC_INT_ENABLE); - writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); - - return 0; -} - -struct sysdev_class vic_class = { - .name = "vic", - .suspend = vic_class_suspend, - .resume = vic_class_resume, -}; - -/** - * vic_pm_register - Register a VIC for later power management control - * @base: The base address of the VIC. - * @irq: The base IRQ for the VIC. - * @resume_sources: bitmask of interrupts allowed for resume sources. - * - * Register the VIC with the system device tree so that it can be notified - * of suspend and resume requests and ensure that the correct actions are - * taken to re-instate the settings on resume. - */ -static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources) -{ - struct vic_device *v; - - if (vic_id >= ARRAY_SIZE(vic_devices)) - printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); - else { - v = &vic_devices[vic_id]; - v->base = base; - v->resume_sources = resume_sources; - v->irq = irq; - vic_id++; - } -} - -/** - * vic_pm_init - initicall to register VIC pm - * - * This is called via late_initcall() to register - * the resources for the VICs due to the early - * nature of the VIC's registration. -*/ -static int __init vic_pm_init(void) -{ - struct vic_device *dev = vic_devices; - int err; - int id; - - if (vic_id == 0) - return 0; - - err = sysdev_class_register(&vic_class); - if (err) { - printk(KERN_ERR "%s: cannot register class\n", __func__); - return err; - } - - for (id = 0; id < vic_id; id++, dev++) { - dev->sysdev.id = id; - dev->sysdev.cls = &vic_class; - - err = sysdev_register(&dev->sysdev); - if (err) { - printk(KERN_ERR "%s: failed to register device\n", - __func__); - return err; - } - } - - return 0; -} - -late_initcall(vic_pm_init); - -static struct vic_device *vic_from_irq(unsigned int irq) -{ - struct vic_device *v = vic_devices; - unsigned int base_irq = irq & ~31; - int id; - - for (id = 0; id < vic_id; id++, v++) { - if (v->irq == base_irq) - return v; - } - - return NULL; -} - -static int vic_set_wake(unsigned int irq, unsigned int on) -{ - struct vic_device *v = vic_from_irq(irq); - unsigned int off = irq & 31; - - if (!v) - return -EINVAL; - - if (on) - v->resume_irqs |= 1 << off; - else - v->resume_irqs &= ~(1 << off); - - return 0; -} - -#else -static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { } - -#define vic_set_wake NULL -#endif /* CONFIG_PM */ - static struct irq_chip vic_chip = { .name = "VIC", .ack = vic_mask_irq, .mask = vic_mask_irq, .unmask = vic_unmask_irq, - .set_wake = vic_set_wake, }; /** @@ -260,10 +51,9 @@ static struct irq_chip vic_chip = { * @base: iomem base address * @irq_start: starting interrupt number, must be muliple of 32 * @vic_sources: bitmask of interrupt sources to allow - * @resume_sources: bitmask of interrupt sources to allow for resume */ void __init vic_init(void __iomem *base, unsigned int irq_start, - u32 vic_sources, u32 resume_sources) + u32 vic_sources) { unsigned int i; @@ -287,7 +77,12 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, writel(value, base + VIC_PL190_VECT_ADDR); } - vic_init2(base); + for (i = 0; i < 16; i++) { + void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); + writel(VIC_VECT_CNTL_ENABLE | i, reg); + } + + writel(32, base + VIC_PL190_DEF_VECT_ADDR); for (i = 0; i < 32; i++) { if (vic_sources & (1 << i)) { @@ -299,6 +94,4 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } - - vic_pm_register(base, irq_start, resume_sources); } diff --git a/trunk/arch/arm/configs/davinci_all_defconfig b/trunk/arch/arm/configs/davinci_all_defconfig index ac18662f38cc..eb2738b5be5f 100644 --- a/trunk/arch/arm/configs/davinci_all_defconfig +++ b/trunk/arch/arm/configs/davinci_all_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc7 -# Tue May 26 07:24:28 2009 +# Linux kernel version: 2.6.30-rc2 +# Wed Apr 15 08:16:53 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -179,7 +179,6 @@ CONFIG_ARCH_DAVINCI=y # CONFIG_ARCH_OMAP is not set # CONFIG_ARCH_MSM is not set # CONFIG_ARCH_W90X900 is not set -CONFIG_AINTC=y # # TI DaVinci Implementations @@ -189,17 +188,11 @@ CONFIG_AINTC=y # DaVinci Core Type # CONFIG_ARCH_DAVINCI_DM644x=y -CONFIG_ARCH_DAVINCI_DM355=y -CONFIG_ARCH_DAVINCI_DM646x=y # # DaVinci Board Type # CONFIG_MACH_DAVINCI_EVM=y -CONFIG_MACH_SFFSDR=y -CONFIG_MACH_DAVINCI_DM355_EVM=y -CONFIG_MACH_DM355_LEOPARD=y -CONFIG_MACH_DAVINCI_DM6467_EVM=y CONFIG_DAVINCI_MUX=y CONFIG_DAVINCI_MUX_DEBUG=y CONFIG_DAVINCI_MUX_WARNINGS=y @@ -252,7 +245,7 @@ CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set @@ -668,10 +661,7 @@ CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_AX88796 is not set # CONFIG_SMC91X is not set -CONFIG_TI_DAVINCI_EMAC=y -CONFIG_DM9000=y -CONFIG_DM9000_DEBUGLEVEL=4 -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set +# CONFIG_DM9000 is not set # CONFIG_ETHOC is not set # CONFIG_SMC911X is not set # CONFIG_SMSC911X is not set @@ -973,7 +963,6 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set -# CONFIG_MFD_DM355EVM_MSP is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_TPS65010 is not set @@ -1328,7 +1317,6 @@ CONFIG_MMC_BLOCK=m # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_DAVINCI is not set # CONFIG_MEMSTICK is not set # CONFIG_ACCESSIBILITY is not set CONFIG_NEW_LEDS=y @@ -1790,7 +1778,6 @@ CONFIG_CRC32=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m CONFIG_DECOMPRESS_GZIP=y -CONFIG_GENERIC_ALLOCATOR=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y diff --git a/trunk/arch/arm/configs/ep93xx_defconfig b/trunk/arch/arm/configs/ep93xx_defconfig index 3fb083b81b0a..3f89d5f25bce 100644 --- a/trunk/arch/arm/configs/ep93xx_defconfig +++ b/trunk/arch/arm/configs/ep93xx_defconfig @@ -1,19 +1,12 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc3 -# Tue May 19 12:26:49 2009 +# Linux kernel version: 2.6.20-rc1 +# Sat Dec 16 06:05:24 2006 # CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y # CONFIG_GENERIC_TIME is not set -# CONFIG_GENERIC_CLOCKEVENTS is not set CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y @@ -22,54 +15,42 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# General setup +# Code maturity level options # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_IPC_NS is not set # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -# CONFIG_BLK_DEV_INITRD is not set +CONFIG_INITRAMFS_SOURCE="" CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -77,38 +58,31 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y +CONFIG_VM_EVENT_COUNTERS=y CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# CONFIG_BLOCK=y # CONFIG_LBD is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # # IO Schedulers @@ -122,7 +96,6 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" -# CONFIG_FREEZER is not set # # System Type @@ -132,40 +105,29 @@ CONFIG_DEFAULT_IOSCHED="deadline" # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set CONFIG_ARCH_EP93XX=y # CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set # CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP23XX is not set # CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set # @@ -176,24 +138,14 @@ CONFIG_CRUNCH=y # # EP93xx Platforms # -# CONFIG_EP93XX_SDCE0_PHYS_OFFSET is not set -CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET=y CONFIG_MACH_ADSSPHERE=y -CONFIG_MACH_EDB93XX=y -CONFIG_MACH_EDB9301=y CONFIG_MACH_EDB9302=y -CONFIG_MACH_EDB9307=y +CONFIG_MACH_EDB9302A=y CONFIG_MACH_EDB9312=y CONFIG_MACH_EDB9315=y +CONFIG_MACH_EDB9315A=y CONFIG_MACH_GESBC9312=y -CONFIG_MACH_MICRO9=y -CONFIG_MACH_MICRO9H=y -CONFIG_MACH_MICRO9M=y -CONFIG_MACH_MICRO9L=y CONFIG_MACH_TS72XX=y -CONFIG_EP93XX_EARLY_UART1=y -# CONFIG_EP93XX_EARLY_UART2 is not set -# CONFIG_EP93XX_EARLY_UART3 is not set # # Processor Type @@ -202,7 +154,6 @@ CONFIG_CPU_32=y CONFIG_CPU_ARM920T=y CONFIG_CPU_32v4T=y CONFIG_CPU_ABRT_EV4T=y -CONFIG_CPU_PABRT_NOIFAR=y CONFIG_CPU_CACHE_V4WT=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_COPY_V4WB=y @@ -217,47 +168,34 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_OUTER_CACHE is not set CONFIG_ARM_VIC=y -CONFIG_COMMON_CLKDEV=y # # Bus support # CONFIG_ARM_AMBA=y -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# # CONFIG_PCCARD is not set # # Kernel Features # -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 # CONFIG_PREEMPT is not set CONFIG_HZ=100 -CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y -CONFIG_ARCH_FLATMEM_HAS_HOLES=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set +# CONFIG_AEABI is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_RESOURCES_64BIT is not set CONFIG_ALIGNMENT_TRAP=y # @@ -267,12 +205,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/nfs ip=bootp" # CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -# CONFIG_CPU_IDLE is not set # # Floating point emulation @@ -289,31 +221,32 @@ CONFIG_FPE_NWFPE_XP=y # Userspace binary formats # CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y # CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set # # Power management options # # CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_APM is not set + +# +# Networking +# CONFIG_NET=y # # Networking options # +# CONFIG_NETDEBUG is not set CONFIG_PACKET=y CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set @@ -334,7 +267,6 @@ CONFIG_SYN_COOKIES=y CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set @@ -344,7 +276,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_IPV6=y # CONFIG_IPV6_PRIVACY is not set # CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set # CONFIG_INET6_AH is not set # CONFIG_INET6_ESP is not set # CONFIG_INET6_IPCOMP is not set @@ -358,15 +289,25 @@ CONFIG_IPV6=y # CONFIG_IPV6_SIT is not set # CONFIG_IPV6_TUNNEL is not set # CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# # CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# # CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -376,28 +317,20 @@ CONFIG_IPV6=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set + +# +# QoS and/or fair queueing +# # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_OLD_REGULATORY is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_LIB80211 is not set -# CONFIG_MAC80211 is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set +# CONFIG_IEEE80211 is not set # # Device Drivers @@ -406,39 +339,41 @@ CONFIG_WIRELESS=y # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# # CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set CONFIG_MTD_CONCAT=y CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 # CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set # CONFIG_MTD_REDBOOT_PARTS_READONLY is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers # CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -469,13 +404,16 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set CONFIG_MTD_ROM=y # CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_PLATRAM is not set @@ -493,58 +431,49 @@ CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# CONFIG_MTD_NAND=y CONFIG_MTD_NAND_VERIFY_WRITE=y # CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_TS7250 is not set +CONFIG_MTD_NAND_TS7250=y CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set # -# LPDDR flash memory drivers +# OneNAND Flash Device Drivers # -# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_ONENAND is not set # -# UBI - Unsorted block images +# Parallel port support # -# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y + +# +# Plug and Play support +# + +# +# Block devices +# # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set CONFIG_BLK_DEV_NBD=y # CONFIG_BLK_DEV_UB is not set # CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -CONFIG_MISC_DEVICES=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_ISL29003 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -CONFIG_EEPROM_LEGACY=y -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y -CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_SCSI_PROC_FS is not set @@ -566,7 +495,6 @@ CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports @@ -574,71 +502,92 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y + +# +# SCSI low-level drivers +# # CONFIG_ISCSI_TCP is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set + +# +# Serial ATA (prod) and Parallel ATA (experimental) drivers +# # CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# # CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_VETH is not set + +# +# PHY device support +# # CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# CONFIG_NET_ETHERNET=y CONFIG_MII=y CONFIG_EP93XX_ETH=y -# CONFIG_AX88796 is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y # -# Wireless LAN +# Ethernet (1000 Mbit) # -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set # -# Enable WiMAX (Networking options) to see the WiMAX drivers +# Ethernet (10000 Mbit) # # -# USB Network Adapters +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces # -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -CONFIG_USB_RTL8150=y -# CONFIG_USB_USBNET is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# # CONFIG_ISDN is not set # @@ -656,7 +605,6 @@ CONFIG_USB_RTL8150=y # Character devices # # CONFIG_VT is not set -CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # @@ -673,101 +621,104 @@ CONFIG_SERIAL_AMBA_PL010_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set + +# +# IPMI +# # CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_EP93XX_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set # CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y # -# I2C Hardware Bus support +# TPM devices # +# CONFIG_TCG_TPM is not set # -# I2C system bus drivers (mostly embedded / system-on-chip) +# I2C support # -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y # -# External I2C/SMBus adapter drivers +# I2C Algorithms # -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set # -# Other I2C/SMBus bus drivers +# I2C Hardware Bus support # -# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_STUB is not set +# CONFIG_I2C_PCA_ISA is not set # # Miscellaneous I2C Chip support # -# CONFIG_DS1682 is not set +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +CONFIG_EEPROM_LEGACY=y # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set CONFIG_I2C_DEBUG_CORE=y CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y CONFIG_I2C_DEBUG_CHIP=y -# CONFIG_SPI is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# # -# I2C GPIO expanders: +# SPI support # -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set # -# PCI GPIO expanders: +# Dallas's 1-wire bus # +# CONFIG_W1 is not set # -# SPI GPIO expanders: +# Hardware Monitoring support # -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set @@ -781,188 +732,158 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set # CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set # -# Watchdog Device Drivers +# Misc devices # -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_EP93XX_WATCHDOG=y +# CONFIG_TIFM_CORE is not set # -# USB-based Watchdog Cards +# LED devices # -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y +# CONFIG_NEW_LEDS is not set # -# Sonics Silicon Backplane +# LED drivers # -# CONFIG_SSB is not set # -# Multifunction device drivers +# LED Triggers # -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set # -# Multimedia drivers +# Digital Video Broadcasting Devices # -# CONFIG_DAB is not set +# CONFIG_DVB is not set +# CONFIG_USB_DABUSB is not set # # Graphics support # -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FIRMWARE_EDID is not set # CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # -# Display device support +# Sound # -# CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set -CONFIG_USB_SUPPORT=y + +# +# USB support +# CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_USB_ARCH_HAS_EHCI is not set CONFIG_USB=y CONFIG_USB_DEBUG=y -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_BANDWIDTH is not set CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_MULTITHREAD_PROBE is not set # CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_OHCI_BIG_ENDIAN is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -# CONFIG_USB_MUSB_HDRC is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # -# also be needed; see USB_STORAGE Help for more info +# may also be needed; see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set +# +# USB Input Devices +# + +# +# USB HID Boot Protocol drivers +# + # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +CONFIG_USB_RTL8150=y +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_MON is not set + # # USB port drivers # + +# +# USB Serial Converter support +# CONFIG_USB_SERIAL=y CONFIG_USB_SERIAL_CONSOLE=y -# CONFIG_USB_EZUSB is not set # CONFIG_USB_SERIAL_GENERIC is not set # CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_AIRPRIME is not set # CONFIG_USB_SERIAL_ARK3116 is not set # CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set # CONFIG_USB_SERIAL_WHITEHEAT is not set # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CP2101 is not set # CONFIG_USB_SERIAL_CYPRESS_M8 is not set # CONFIG_USB_SERIAL_EMPEG is not set # CONFIG_USB_SERIAL_FTDI_SIO is not set @@ -974,7 +895,6 @@ CONFIG_USB_SERIAL_CONSOLE=y # CONFIG_USB_SERIAL_EDGEPORT_TI is not set # CONFIG_USB_SERIAL_GARMIN is not set # CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IUU is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set # CONFIG_USB_SERIAL_KEYSPAN is not set # CONFIG_USB_SERIAL_KLSI is not set @@ -982,23 +902,16 @@ CONFIG_USB_SERIAL_CONSOLE=y # CONFIG_USB_SERIAL_MCT_U232 is not set # CONFIG_USB_SERIAL_MOS7720 is not set # CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set # CONFIG_USB_SERIAL_NAVMAN is not set CONFIG_USB_SERIAL_PL2303=y -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set # CONFIG_USB_SERIAL_HP4X is not set # CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SYMBOL is not set # CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -1007,34 +920,38 @@ CONFIG_USB_SERIAL_PL2303=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_AUERSWALD is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# # CONFIG_USB_GADGET is not set # -# OTG and related infrastructure +# MMC/SD Card support # -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set # CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_NEW_LEDS is not set + +# +# Real Time Clock +# CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y @@ -1048,55 +965,24 @@ CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set # -# I2C RTC drivers +# RTC drivers # +# CONFIG_RTC_DRV_X1205 is not set CONFIG_RTC_DRV_DS1307=y -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_RS5C372 is not set CONFIG_RTC_DRV_M48T86=y -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# CONFIG_RTC_DRV_EP93XX=y -# CONFIG_RTC_DRV_PL030 is not set # CONFIG_RTC_DRV_PL031 is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_REGULATOR is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set +# CONFIG_RTC_DRV_TEST is not set +# CONFIG_RTC_DRV_V3020 is not set # # File systems @@ -1105,30 +991,26 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set -CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_DNOTIFY=y +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -1150,13 +1032,16 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1164,35 +1049,33 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set # CONFIG_JFFS2_FS_XATTR is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y + +# +# Network File Systems +# CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -CONFIG_ROOT_NFS=y +# CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y @@ -1204,6 +1087,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -1225,7 +1109,10 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SUN_PARTITION is not set # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -1266,83 +1153,49 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# # CONFIG_DLM is not set +# +# Profiling support +# +# CONFIG_PROFILING is not set + # # Kernel hacking # # CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set CONFIG_DEBUG_SLAB=y # CONFIG_DEBUG_SLAB_LEAK is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RWSEMS is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y # CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y # CONFIG_DEBUG_ICEDCC is not set @@ -1351,115 +1204,21 @@ CONFIG_DEBUG_LL=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set # -# Random Number Generation +# Cryptographic options # -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set +# CONFIG_CRYPTO is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -# CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y +CONFIG_PLIST=y +CONFIG_IOMAP_COPY=y diff --git a/trunk/arch/arm/configs/kirkwood_defconfig b/trunk/arch/arm/configs/kirkwood_defconfig index 0a1abb978d7e..dcf8153a947d 100644 --- a/trunk/arch/arm/configs/kirkwood_defconfig +++ b/trunk/arch/arm/configs/kirkwood_defconfig @@ -182,7 +182,6 @@ CONFIG_ARCH_KIRKWOOD=y CONFIG_MACH_DB88F6281_BP=y CONFIG_MACH_RD88F6192_NAS=y CONFIG_MACH_RD88F6281=y -CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y CONFIG_MACH_TS219=y CONFIG_PLAT_ORION=y @@ -271,9 +270,7 @@ CONFIG_CMDLINE="" # # CPU Power Management # -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE is not set # # Floating point emulation diff --git a/trunk/arch/arm/configs/mx21_defconfig b/trunk/arch/arm/configs/mx21_defconfig deleted file mode 100644 index 4b04290d8e81..000000000000 --- a/trunk/arch/arm/configs/mx21_defconfig +++ /dev/null @@ -1,1170 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc1 -# Tue Apr 14 16:58:09 2009 -# -CONFIG_ARM=y -CONFIG_HAVE_PWM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_MTD_XIP=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_DEFAULT_IOSCHED="noop" -# CONFIG_FREEZER is not set - -# -# System Type -# -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -CONFIG_ARCH_MXC=y -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_W90X900 is not set - -# -# Freescale MXC Implementations -# -# CONFIG_ARCH_MX1 is not set -CONFIG_ARCH_MX2=y -# CONFIG_ARCH_MX3 is not set -CONFIG_MACH_MX21=y -# CONFIG_MACH_MX27 is not set - -# -# MX2 platforms: -# -CONFIG_MACH_MX21ADS=y -# CONFIG_MXC_IRQ_PRIOR is not set -CONFIG_MXC_PWM=y - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_ARM926T=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_PABRT_NOIFAR=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -# CONFIG_OUTER_CACHE is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PREEMPT=y -CONFIG_HZ=100 -CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y -CONFIG_ARCH_FLATMEM_HAS_HOLES=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -# CONFIG_FPE_NWFPE is not set -# CONFIG_FPE_FASTFPE is not set -# CONFIG_VFP is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -# CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_UNIX is not set -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_OLD_REGULATORY is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_LIB80211 is not set -# CONFIG_MAC80211 is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_DEBUG_VERBOSE=3 -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set -# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_XIP is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -CONFIG_MTD_NAND_MXC=y -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -CONFIG_MISC_DEVICES=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_ISL29003 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -CONFIG_CS89x0=y -CONFIG_CS89x0_NONISA_IRQ=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -# CONFIG_CONSOLE_TRANSLATIONS is not set -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_GPIO is not set -CONFIG_I2C_IMX=y -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -CONFIG_FB_IMX=y -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -# CONFIG_FONT_8x16 is not set -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_SOUND is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_MXC=y -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_NEW_LEDS is not set -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_REGULATOR is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -CONFIG_FILE_LOCKING=y -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_VFAT_FS is not set -CONFIG_FAT_DEFAULT_CODEPAGE=437 -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_LATENCYTOP is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/arm/configs/omap3_evm_defconfig b/trunk/arch/arm/configs/omap3_evm_defconfig deleted file mode 100644 index 28be17fbc157..000000000000 --- a/trunk/arch/arm/configs/omap3_evm_defconfig +++ /dev/null @@ -1,1528 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc5 -# Mon May 18 14:01:52 2009 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -CONFIG_FREEZER=y - -# -# System Type -# -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_W90X900 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y - -# -# OMAP Feature Selections -# -# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set -# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y -# CONFIG_OMAP_MCBSP is not set -# CONFIG_OMAP_MBOX_FWK is not set -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -CONFIG_OMAP_LL_DEBUG_UART1=y -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -# CONFIG_OMAP_LL_DEBUG_UART3 is not set -CONFIG_OMAP_SERIAL_WAKE=y -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -CONFIG_MACH_OMAP3EVM=y -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_IFAR=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -# CONFIG_OUTER_CACHE is not set -# CONFIG_ARM_ERRATA_430973 is not set -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT is not set -CONFIG_HZ=128 -CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y -CONFIG_ARCH_FLATMEM_HAS_HOLES=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -# CONFIG_CPU_FREQ is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -# CONFIG_FPE_FASTFPE is not set -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_OLD_REGULATORY is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_LIB80211 is not set -# CONFIG_MAC80211 is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_OMAP_NOR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -# CONFIG_MTD_ONENAND_GENERIC is not set -CONFIG_MTD_ONENAND_OMAP2=y -# CONFIG_MTD_ONENAND_OTP is not set -# CONFIG_MTD_ONENAND_2X_PROGRAM is not set -# CONFIG_MTD_ONENAND_SIM is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -CONFIG_SMC911X=y -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -CONFIG_DAB=y -# CONFIG_USB_DABUSB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_SOUND is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_DRAGONRISE_FF is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_GREENASIA_FF is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_THRUSTMASTER_FF is not set -# CONFIG_ZEROPLUS_FF is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=y -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_ZERO=m -# CONFIG_USB_ZERO_HNPTEST is not set -# CONFIG_USB_ETH is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_ISP1301_OMAP is not set -CONFIG_TWL4030_USB=y -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=m -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_NEW_LEDS is not set -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_UIO is not set -# CONFIG_STAGING is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -CONFIG_FILE_LOCKING=y -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_CMODE_NONE is not set -CONFIG_JFFS2_CMODE_PRIORITY=y -# CONFIG_JFFS2_CMODE_SIZE is not set -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_LL=y -# CONFIG_DEBUG_ICEDCC is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/arm/configs/omap_4430sdp_defconfig b/trunk/arch/arm/configs/omap_4430sdp_defconfig deleted file mode 100644 index 23e43ea4efa1..000000000000 --- a/trunk/arch/arm/configs/omap_4430sdp_defconfig +++ /dev/null @@ -1,866 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc7 -# Tue Jun 9 12:36:23 2009 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y -CONFIG_COMPAT_BRK=y -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_USE_GENERIC_SMP_HELPERS=y -CONFIG_HAVE_CLK=y -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_STOP_MACHINE=y -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -# CONFIG_FREEZER is not set - -# -# System Type -# -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y - -# -# TI OMAP Implementations -# -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -# CONFIG_ARCH_OMAP3 is not set -CONFIG_ARCH_OMAP4=y - -# -# OMAP Feature Selections -# -# CONFIG_OMAP_RESET_CLOCKS is not set -# CONFIG_OMAP_MUX is not set -# CONFIG_OMAP_MCBSP is not set -# CONFIG_OMAP_MBOX_FWK is not set -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -CONFIG_OMAP_LL_DEBUG_UART1=y -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -# CONFIG_OMAP_LL_DEBUG_UART3 is not set - -# -# OMAP Board Type -# -CONFIG_MACH_OMAP_4430SDP=y - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_IFAR=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -# CONFIG_ARM_THUMB is not set -# CONFIG_ARM_THUMBEE is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_DCACHE_DISABLE=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -# CONFIG_ARM_ERRATA_430973 is not set -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_ARM_GIC=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_SMP=y -CONFIG_HAVE_ARM_SCU=y -CONFIG_HAVE_ARM_TWD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_NR_CPUS=2 -# CONFIG_HOTPLUG_CPU is not set -CONFIG_LOCAL_TIMERS=y -# CONFIG_PREEMPT is not set -CONFIG_HZ=128 -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_UNEVICTABLE_LRU is not set -CONFIG_HAVE_MLOCK=y -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -# CONFIG_CPU_FREQ is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -# CONFIG_NEON is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -# CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_NET is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_MTD is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -CONFIG_DAB=y - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_SOUND is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_NEW_LEDS is not set -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_REGULATOR is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -CONFIG_FILE_LOCKING=y -# CONFIG_XFS_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -CONFIG_FRAME_POINTER=y -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_ARM_UNWIND is not set -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -CONFIG_CRC_T10DIF=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y diff --git a/trunk/arch/arm/configs/omap_zoom2_defconfig b/trunk/arch/arm/configs/omap_zoom2_defconfig deleted file mode 100644 index 213fe9c5eaae..000000000000 --- a/trunk/arch/arm/configs/omap_zoom2_defconfig +++ /dev/null @@ -1,1211 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc5 -# Fri Oct 10 11:49:41 2008 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_SUPPORTS_AOUT=y -CONFIG_ZONE_DMA=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_COMPAT_BRK=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_ANON_INODES=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -CONFIG_CLASSIC_RCU=y - -# -# System Type -# -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_MSM7X00A is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y - -# -# OMAP Feature Selections -# -# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set -# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set -# CONFIG_OMAP_RESET_CLOCKS is not set -CONFIG_OMAP_MUX=y -CONFIG_OMAP_MUX_DEBUG=y -CONFIG_OMAP_MUX_WARNINGS=y -CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -CONFIG_OMAP_SERIAL_WAKE=y -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -CONFIG_MACH_OMAP_ZOOM2=y -# CONFIG_MACH_OVERO is not set - -# -# Boot options -# - -# -# Power management -# - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_IFAR=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -# CONFIG_OUTER_CACHE is not set - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_PREEMPT is not set -CONFIG_HZ=128 -CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y -CONFIG_ARCH_FLATMEM_HAS_HOLES=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y -CONFIG_VIRT_TO_BUS=y -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Frequency scaling -# -# CONFIG_CPU_FREQ is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -# CONFIG_FPE_FASTFPE is not set -CONFIG_VFP=y -CONFIG_VFPv3=y -# CONFIG_NEON is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -# CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_PHONET is not set -# CONFIG_WIRELESS is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y -# CONFIG_MTD is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -CONFIG_MISC_DEVICES=y -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -CONFIG_SMSC_PHY=y -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_SMC911X is not set -CONFIG_SMSC911X=y -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI_LEDS is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_UCB1400 is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_NVRAM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_ISP1301_OMAP is not set -# CONFIG_TPS65010 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -CONFIG_SPI_OMAP24XX=y - -# -# SPI Protocol Masters -# -# CONFIG_EEPROM_AT25 is not set -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -CONFIG_W1=y - -# -# 1-wire Bus Masters -# -# CONFIG_W1_MASTER_DS2482 is not set -# CONFIG_W1_MASTER_DS1WM is not set -# CONFIG_W1_MASTER_GPIO is not set - -# -# 1-wire Slaves -# -# CONFIG_W1_SLAVE_THERM is not set -# CONFIG_W1_SLAVE_SMEM is not set -# CONFIG_W1_SLAVE_DS2433 is not set -# CONFIG_W1_SLAVE_DS2760 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set - -# -# Sonics Silicon Backplane -# -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -CONFIG_DAB=y - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_SOUND=y -CONFIG_SND=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -CONFIG_SND_ARM=y -CONFIG_SND_SPI=y -# CONFIG_SND_SOC is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set -# CONFIG_HIDRAW is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -# CONFIG_MMC_SPI is not set -# CONFIG_NEW_LEDS is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set - -# -# Voltage and Current regulators -# -# CONFIG_REGULATOR is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_UIO is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -CONFIG_PRINT_QUOTA_WARNING=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_REGISTER_V4 is not set -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -CONFIG_FRAME_POINTER=y -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_LL=y -# CONFIG_DEBUG_ICEDCC is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_MANAGER=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_LZO is not set -CONFIG_CRYPTO_HW=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -CONFIG_CRC_T10DIF=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y diff --git a/trunk/arch/arm/configs/orion5x_defconfig b/trunk/arch/arm/configs/orion5x_defconfig index 9e2385293ecb..5b98f7645119 100644 --- a/trunk/arch/arm/configs/orion5x_defconfig +++ b/trunk/arch/arm/configs/orion5x_defconfig @@ -903,8 +903,7 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=m -CONFIG_HW_RANDOM_TIMERIOMEM=m +# CONFIG_HW_RANDOM is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set diff --git a/trunk/arch/arm/configs/rx51_defconfig b/trunk/arch/arm/configs/rx51_defconfig index eb2cb31825c0..593102da8cd7 100644 --- a/trunk/arch/arm/configs/rx51_defconfig +++ b/trunk/arch/arm/configs/rx51_defconfig @@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0" +CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs rw console=ttyMTD5" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set diff --git a/trunk/arch/arm/configs/w90p910_defconfig b/trunk/arch/arm/configs/w90p910_defconfig index 5245655a0ad3..56bda7c6d670 100644 --- a/trunk/arch/arm/configs/w90p910_defconfig +++ b/trunk/arch/arm/configs/w90p910_defconfig @@ -1,11 +1,11 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30 -# Wed Jun 10 22:09:25 2009 +# Linux kernel version: 2.6.27-rc8-git8 +# Sat Nov 15 10:05:00 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_GPIO is not set # CONFIG_GENERIC_TIME is not set # CONFIG_GENERIC_CLOCKEVENTS is not set CONFIG_MMU=y @@ -22,6 +22,8 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -40,19 +42,10 @@ CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y @@ -63,53 +56,52 @@ CONFIG_USER_NS=y # CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -# CONFIG_INITRAMFS_COMPRESSION_NONE is not set -# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set -# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set -# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_EXTRA_PASS=y -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -CONFIG_TRACEPOINTS=y # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_HAVE_CLK is not set +CONFIG_PROC_PAGE_MONITOR=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 # CONFIG_MODULES is not set CONFIG_BLOCK=y CONFIG_LBD=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_LSF=y CONFIG_BLK_DEV_BSG=y # CONFIG_BLK_DEV_INTEGRITY is not set @@ -125,7 +117,7 @@ CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_FREEZER is not set +CONFIG_CLASSIC_RCU=y # # System Type @@ -135,10 +127,10 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set @@ -159,17 +151,23 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_ARCH_ORION5X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MMP is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_MSM7X00A is not set CONFIG_ARCH_W90X900=y + +# +# Boot options +# + +# +# Power management +# CONFIG_CPU_W90P910=y # @@ -200,7 +198,6 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_CPU_CACHE_ROUND_ROBIN is not set # CONFIG_OUTER_CACHE is not set -CONFIG_COMMON_CLKDEV=y # # Bus support @@ -212,32 +209,27 @@ CONFIG_COMMON_CLKDEV=y # # Kernel Features # -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_TICK_ONESHOT is not set CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y CONFIG_OABI_COMPAT=y -# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y CONFIG_ALIGNMENT_TRAP=y # @@ -245,16 +237,11 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M" +CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 initrd=0xa00000,4000000 mem=64M" # CONFIG_XIP_KERNEL is not set CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y -# -# CPU Power Management -# -# CONFIG_CPU_IDLE is not set - # # Floating point emulation # @@ -271,8 +258,6 @@ CONFIG_FPE_NWFPE=y # Userspace binary formats # CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y # CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_MISC is not set @@ -297,93 +282,11 @@ CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -# CONFIG_MTD_NAND is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set +# CONFIG_MTD is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 @@ -397,41 +300,9 @@ CONFIG_HAVE_IDE=y # SCSI device support # # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_PROC_FS is not set - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set # CONFIG_MD is not set @@ -483,57 +354,38 @@ CONFIG_HW_CONSOLE=y # # Serial drivers # -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # +CONFIG_SERIAL_W90X900=y +# CONFIG_SERIAL_W90X900_PORT1 is not set +# CONFIG_SERIAL_W90X900_PORT2 is not set +# CONFIG_SERIAL_W90X900_PORT3 is not set +# CONFIG_SERIAL_W90X900_PORT4 is not set +CONFIG_SERIAL_W90X900_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set # CONFIG_SPI is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # +CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -541,11 +393,10 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set -# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set # # Multimedia devices @@ -582,131 +433,33 @@ CONFIG_SSB_POSSIBLE=y CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -# CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_NEW_LEDS is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set + +# +# Voltage and Current regulators +# # CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # CONFIG_UIO is not set -# CONFIG_STAGING is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set -# CONFIG_BTRFS_FS is not set # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY is not set # CONFIG_QUOTA is not set @@ -715,11 +468,6 @@ CONFIG_FILE_LOCKING=y # CONFIG_FUSE_FS is not set CONFIG_GENERIC_ACL=y -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -738,13 +486,15 @@ CONFIG_GENERIC_ACL=y # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -752,22 +502,15 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set CONFIG_ROMFS_FS=y -CONFIG_ROMFS_BACKED_BY_BLOCK=y -# CONFIG_ROMFS_BACKED_BY_MTD is not set -# CONFIG_ROMFS_BACKED_BY_BOTH is not set -CONFIG_ROMFS_ON_BLOCK=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set # # Partition Types @@ -843,36 +586,18 @@ CONFIG_FRAME_WARN=1024 CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_STACKTRACE=y CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_FRAME_POINTER=y # CONFIG_LATENCYTOP is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -CONFIG_BLK_DEV_IO_TRACE=y -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -CONFIG_ARM_UNWIND=y # CONFIG_DEBUG_USER is not set # @@ -880,15 +605,14 @@ CONFIG_ARM_UNWIND=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set -CONFIG_BINARY_PRINTF=y # # Library routines # -CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -896,10 +620,7 @@ CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC32 is not set # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y diff --git a/trunk/arch/arm/include/asm/assembler.h b/trunk/arch/arm/include/asm/assembler.h index 15f8a092b700..6116e4893c0a 100644 --- a/trunk/arch/arm/include/asm/assembler.h +++ b/trunk/arch/arm/include/asm/assembler.h @@ -114,16 +114,3 @@ .align 3; \ .long 9999b,9001f; \ .previous - -/* - * SMP data memory barrier - */ - .macro smp_dmb -#ifdef CONFIG_SMP -#if __LINUX_ARM_ARCH__ >= 7 - dmb -#elif __LINUX_ARM_ARCH__ == 6 - mcr p15, 0, r0, c7, c10, 5 @ dmb -#endif -#endif - .endm diff --git a/trunk/arch/arm/include/asm/atomic.h b/trunk/arch/arm/include/asm/atomic.h index 16b52f397983..ee99723b3a6c 100644 --- a/trunk/arch/arm/include/asm/atomic.h +++ b/trunk/arch/arm/include/asm/atomic.h @@ -44,29 +44,11 @@ static inline void atomic_set(atomic_t *v, int i) : "cc"); } -static inline void atomic_add(int i, atomic_t *v) -{ - unsigned long tmp; - int result; - - __asm__ __volatile__("@ atomic_add\n" -"1: ldrex %0, [%2]\n" -" add %0, %0, %3\n" -" strex %1, %0, [%2]\n" -" teq %1, #0\n" -" bne 1b" - : "=&r" (result), "=&r" (tmp) - : "r" (&v->counter), "Ir" (i) - : "cc"); -} - static inline int atomic_add_return(int i, atomic_t *v) { unsigned long tmp; int result; - smp_mb(); - __asm__ __volatile__("@ atomic_add_return\n" "1: ldrex %0, [%2]\n" " add %0, %0, %3\n" @@ -77,34 +59,14 @@ static inline int atomic_add_return(int i, atomic_t *v) : "r" (&v->counter), "Ir" (i) : "cc"); - smp_mb(); - return result; } -static inline void atomic_sub(int i, atomic_t *v) -{ - unsigned long tmp; - int result; - - __asm__ __volatile__("@ atomic_sub\n" -"1: ldrex %0, [%2]\n" -" sub %0, %0, %3\n" -" strex %1, %0, [%2]\n" -" teq %1, #0\n" -" bne 1b" - : "=&r" (result), "=&r" (tmp) - : "r" (&v->counter), "Ir" (i) - : "cc"); -} - static inline int atomic_sub_return(int i, atomic_t *v) { unsigned long tmp; int result; - smp_mb(); - __asm__ __volatile__("@ atomic_sub_return\n" "1: ldrex %0, [%2]\n" " sub %0, %0, %3\n" @@ -115,8 +77,6 @@ static inline int atomic_sub_return(int i, atomic_t *v) : "r" (&v->counter), "Ir" (i) : "cc"); - smp_mb(); - return result; } @@ -124,8 +84,6 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) { unsigned long oldval, res; - smp_mb(); - do { __asm__ __volatile__("@ atomic_cmpxchg\n" "ldrex %1, [%2]\n" @@ -137,8 +95,6 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) : "cc"); } while (res); - smp_mb(); - return oldval; } @@ -179,7 +135,6 @@ static inline int atomic_add_return(int i, atomic_t *v) return val; } -#define atomic_add(i, v) (void) atomic_add_return(i, v) static inline int atomic_sub_return(int i, atomic_t *v) { @@ -193,7 +148,6 @@ static inline int atomic_sub_return(int i, atomic_t *v) return val; } -#define atomic_sub(i, v) (void) atomic_sub_return(i, v) static inline int atomic_cmpxchg(atomic_t *v, int old, int new) { @@ -233,8 +187,10 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) -#define atomic_inc(v) atomic_add(1, v) -#define atomic_dec(v) atomic_sub(1, v) +#define atomic_add(i, v) (void) atomic_add_return(i, v) +#define atomic_inc(v) (void) atomic_add_return(1, v) +#define atomic_sub(i, v) (void) atomic_sub_return(i, v) +#define atomic_dec(v) (void) atomic_sub_return(1, v) #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0) #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0) @@ -244,10 +200,11 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0) -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() +/* Atomic operations are already serializing on ARM */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() #include #endif diff --git a/trunk/arch/arm/include/asm/flat.h b/trunk/arch/arm/include/asm/flat.h index 59426a4595c9..1d77e51907f6 100644 --- a/trunk/arch/arm/include/asm/flat.h +++ b/trunk/arch/arm/include/asm/flat.h @@ -5,6 +5,9 @@ #ifndef __ARM_FLAT_H__ #define __ARM_FLAT_H__ +/* An odd number of words will be pushed after this alignment, so + deliberately misalign the value. */ +#define flat_stack_align(sp) sp = (void *)(((unsigned long)(sp) - 4) | 4) #define flat_argvp_envp_on_stack() 1 #define flat_old_ram_flag(flags) (flags) #define flat_reloc_valid(reloc, size) ((reloc) <= (size)) diff --git a/trunk/arch/arm/include/asm/hardware/arm_twd.h b/trunk/arch/arm/include/asm/hardware/arm_twd.h new file mode 100644 index 000000000000..e521b70713c8 --- /dev/null +++ b/trunk/arch/arm/include/asm/hardware/arm_twd.h @@ -0,0 +1,21 @@ +#ifndef __ASM_HARDWARE_TWD_H +#define __ASM_HARDWARE_TWD_H + +#define TWD_TIMER_LOAD 0x00 +#define TWD_TIMER_COUNTER 0x04 +#define TWD_TIMER_CONTROL 0x08 +#define TWD_TIMER_INTSTAT 0x0C + +#define TWD_WDOG_LOAD 0x20 +#define TWD_WDOG_COUNTER 0x24 +#define TWD_WDOG_CONTROL 0x28 +#define TWD_WDOG_INTSTAT 0x2C +#define TWD_WDOG_RESETSTAT 0x30 +#define TWD_WDOG_DISABLE 0x34 + +#define TWD_TIMER_CONTROL_ENABLE (1 << 0) +#define TWD_TIMER_CONTROL_ONESHOT (0 << 1) +#define TWD_TIMER_CONTROL_PERIODIC (1 << 1) +#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) + +#endif diff --git a/trunk/arch/arm/include/asm/hardware/pl080.h b/trunk/arch/arm/include/asm/hardware/pl080.h deleted file mode 100644 index 6a6c66be7f65..000000000000 --- a/trunk/arch/arm/include/asm/hardware/pl080.h +++ /dev/null @@ -1,138 +0,0 @@ -/* arch/arm/include/asm/hardware/pl080.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * ARM PrimeCell PL080 DMA controller - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* Note, there are some Samsung updates to this controller block which - * make it not entierly compatible with the PL080 specification from - * ARM. When in doubt, check the Samsung documentation first. - * - * The Samsung defines are PL080S, and add an extra controll register, - * the ability to move more than 2^11 counts of data and some extra - * OneNAND features. -*/ - -#define PL080_INT_STATUS (0x00) -#define PL080_TC_STATUS (0x04) -#define PL080_TC_CLEAR (0x08) -#define PL080_ERR_STATUS (0x0C) -#define PL080_ERR_CLEAR (0x10) -#define PL080_RAW_TC_STATUS (0x14) -#define PL080_RAW_ERR_STATUS (0x18) -#define PL080_EN_CHAN (0x1c) -#define PL080_SOFT_BREQ (0x20) -#define PL080_SOFT_SREQ (0x24) -#define PL080_SOFT_LBREQ (0x28) -#define PL080_SOFT_LSREQ (0x2C) - -#define PL080_CONFIG (0x30) -#define PL080_CONFIG_M2_BE (1 << 2) -#define PL080_CONFIG_M1_BE (1 << 1) -#define PL080_CONFIG_ENABLE (1 << 0) - -#define PL080_SYNC (0x34) - -/* Per channel configuration registers */ - -#define PL008_Cx_STRIDE (0x20) -#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) -#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20))) -#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20))) -#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20))) -#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20))) -#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20))) -#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20))) -#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20))) - -#define PL080_CH_SRC_ADDR (0x00) -#define PL080_CH_DST_ADDR (0x04) -#define PL080_CH_LLI (0x08) -#define PL080_CH_CONTROL (0x0C) -#define PL080_CH_CONFIG (0x10) -#define PL080S_CH_CONTROL2 (0x10) -#define PL080S_CH_CONFIG (0x14) - -#define PL080_LLI_ADDR_MASK (0x3fffffff << 2) -#define PL080_LLI_ADDR_SHIFT (2) -#define PL080_LLI_LM_AHB2 (1 << 0) - -#define PL080_CONTROL_TC_IRQ_EN (1 << 31) -#define PL080_CONTROL_PROT_MASK (0x7 << 28) -#define PL080_CONTROL_PROT_SHIFT (28) -#define PL080_CONTROL_PROT_SYS (1 << 28) -#define PL080_CONTROL_DST_INCR (1 << 27) -#define PL080_CONTROL_SRC_INCR (1 << 26) -#define PL080_CONTROL_DST_AHB2 (1 << 25) -#define PL080_CONTROL_SRC_AHB2 (1 << 24) -#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21) -#define PL080_CONTROL_DWIDTH_SHIFT (21) -#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18) -#define PL080_CONTROL_SWIDTH_SHIFT (18) -#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15) -#define PL080_CONTROL_DB_SIZE_SHIFT (15) -#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12) -#define PL080_CONTROL_SB_SIZE_SHIFT (12) -#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0) -#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0) - -#define PL080_BSIZE_1 (0x0) -#define PL080_BSIZE_4 (0x1) -#define PL080_BSIZE_8 (0x2) -#define PL080_BSIZE_16 (0x3) -#define PL080_BSIZE_32 (0x4) -#define PL080_BSIZE_64 (0x5) -#define PL080_BSIZE_128 (0x6) -#define PL080_BSIZE_256 (0x7) - -#define PL080_WIDTH_8BIT (0x0) -#define PL080_WIDTH_16BIT (0x1) -#define PL080_WIDTH_32BIT (0x2) - -#define PL080_CONFIG_HALT (1 << 18) -#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */ -#define PL080_CONFIG_LOCK (1 << 16) -#define PL080_CONFIG_TC_IRQ_MASK (1 << 15) -#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14) -#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11) -#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11) -#define PL080_CONFIG_DST_SEL_MASK (0xf << 6) -#define PL080_CONFIG_DST_SEL_SHIFT (6) -#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1) -#define PL080_CONFIG_SRC_SEL_SHIFT (1) -#define PL080_CONFIG_ENABLE (1 << 0) - -#define PL080_FLOW_MEM2MEM (0x0) -#define PL080_FLOW_MEM2PER (0x1) -#define PL080_FLOW_PER2MEM (0x2) -#define PL080_FLOW_SRC2DST (0x3) -#define PL080_FLOW_SRC2DST_DST (0x4) -#define PL080_FLOW_MEM2PER_PER (0x5) -#define PL080_FLOW_PER2MEM_PER (0x6) -#define PL080_FLOW_SRC2DST_SRC (0x7) - -/* DMA linked list chain structure */ - -struct pl080_lli { - u32 src_addr; - u32 dst_addr; - u32 next_lli; - u32 control0; -}; - -struct pl080s_lli { - u32 src_addr; - u32 dst_addr; - u32 next_lli; - u32 control0; - u32 control1; -}; - diff --git a/trunk/arch/arm/include/asm/hardware/vic.h b/trunk/arch/arm/include/asm/hardware/vic.h index 5d72550a8097..f87328d4a180 100644 --- a/trunk/arch/arm/include/asm/hardware/vic.h +++ b/trunk/arch/arm/include/asm/hardware/vic.h @@ -41,7 +41,7 @@ #define VIC_PL192_VECT_ADDR 0xF00 #ifndef __ASSEMBLY__ -void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources); +void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); #endif #endif diff --git a/trunk/arch/arm/include/asm/localtimer.h b/trunk/arch/arm/include/asm/localtimer.h deleted file mode 100644 index 50c7e7cfd670..000000000000 --- a/trunk/arch/arm/include/asm/localtimer.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * arch/arm/include/asm/localtimer.h - * - * Copyright (C) 2004-2005 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_ARM_LOCALTIMER_H -#define __ASM_ARM_LOCALTIMER_H - -struct clock_event_device; - -/* - * Setup a per-cpu timer, whether it be a local timer or dummy broadcast - */ -void percpu_timer_setup(void); - -/* - * Called from assembly, this is the local timer IRQ handler - */ -asmlinkage void do_local_timer(struct pt_regs *); - - -#ifdef CONFIG_LOCAL_TIMERS - -#ifdef CONFIG_HAVE_ARM_TWD - -#include "smp_twd.h" - -#define local_timer_ack() twd_timer_ack() -#define local_timer_stop() twd_timer_stop() - -#else - -/* - * Platform provides this to acknowledge a local timer IRQ. - * Returns true if the local timer IRQ is to be processed. - */ -int local_timer_ack(void); - -/* - * Stop a local timer interrupt. - */ -void local_timer_stop(void); - -#endif - -/* - * Setup a local timer interrupt for a CPU. - */ -void local_timer_setup(struct clock_event_device *); - -#else - -static inline void local_timer_stop(void) -{ -} - -#endif - -#endif diff --git a/trunk/arch/arm/include/asm/mach/map.h b/trunk/arch/arm/include/asm/mach/map.h index 742c2aaeb020..58cf91f38e6f 100644 --- a/trunk/arch/arm/include/asm/mach/map.h +++ b/trunk/arch/arm/include/asm/mach/map.h @@ -30,14 +30,6 @@ struct map_desc { #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); - -struct mem_type; -extern const struct mem_type *get_mem_type(unsigned int type); -/* - * external interface to remap single page with appropriate type - */ -extern int ioremap_page(unsigned long virt, unsigned long phys, - const struct mem_type *mtype); #else #define iotable_init(map,num) do { } while (0) #endif diff --git a/trunk/arch/arm/include/asm/pgtable.h b/trunk/arch/arm/include/asm/pgtable.h index 1cd2d6416bda..110295c5461d 100644 --- a/trunk/arch/arm/include/asm/pgtable.h +++ b/trunk/arch/arm/include/asm/pgtable.h @@ -342,7 +342,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) return __va(ptr); } -#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) +#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd))) /* * Conversion functions: convert a page and protection to a page entry, diff --git a/trunk/arch/arm/include/asm/sizes.h b/trunk/arch/arm/include/asm/sizes.h index 4fc1565e4f93..ada93a8fc2ef 100644 --- a/trunk/arch/arm/include/asm/sizes.h +++ b/trunk/arch/arm/include/asm/sizes.h @@ -29,7 +29,6 @@ #define SZ_512 0x00000200 #define SZ_1K 0x00000400 -#define SZ_2K 0x00000800 #define SZ_4K 0x00001000 #define SZ_8K 0x00002000 #define SZ_16K 0x00004000 diff --git a/trunk/arch/arm/include/asm/smp.h b/trunk/arch/arm/include/asm/smp.h index a06e735b262a..5995935338e1 100644 --- a/trunk/arch/arm/include/asm/smp.h +++ b/trunk/arch/arm/include/asm/smp.h @@ -41,7 +41,7 @@ extern void show_ipi_list(struct seq_file *p); asmlinkage void do_IPI(struct pt_regs *regs); /* - * Setup the set of possible CPUs (via set_cpu_possible) + * Setup the SMP cpu_possible_map */ extern void smp_init_cpus(void); @@ -55,6 +55,11 @@ extern void smp_store_cpu_info(unsigned int cpuid); */ extern void smp_cross_call(const struct cpumask *mask); +/* + * Broadcast a clock event to other CPUs. + */ +extern void smp_timer_broadcast(const struct cpumask *mask); + /* * Boot a secondary CPU, and assign it the specified idle task. * This also gives us the initial stack to use for this CPU. @@ -95,9 +100,44 @@ extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); #define arch_send_call_function_ipi_mask arch_send_call_function_ipi_mask +/* + * Local timer interrupt handling function (can be IPI'ed). + */ +extern void local_timer_interrupt(void); + +#ifdef CONFIG_LOCAL_TIMERS + +/* + * Stop a local timer interrupt. + */ +extern void local_timer_stop(void); + +/* + * Platform provides this to acknowledge a local timer IRQ + */ +extern int local_timer_ack(void); + +#else + +static inline void local_timer_stop(void) +{ +} + +#endif + +/* + * Setup a local timer interrupt for a CPU. + */ +extern void local_timer_setup(void); + /* * show local interrupt info */ extern void show_local_irqs(struct seq_file *); +/* + * Called from assembly, this is the local timer IRQ handler + */ +asmlinkage void do_local_timer(struct pt_regs *); + #endif /* ifndef __ASM_ARM_SMP_H */ diff --git a/trunk/arch/arm/include/asm/smp_scu.h b/trunk/arch/arm/include/asm/smp_scu.h deleted file mode 100644 index 2376835015d6..000000000000 --- a/trunk/arch/arm/include/asm/smp_scu.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASMARM_ARCH_SCU_H -#define __ASMARM_ARCH_SCU_H - -unsigned int scu_get_core_count(void __iomem *); -void scu_enable(void __iomem *); - -#endif diff --git a/trunk/arch/arm/include/asm/smp_twd.h b/trunk/arch/arm/include/asm/smp_twd.h deleted file mode 100644 index 7be0978b2625..000000000000 --- a/trunk/arch/arm/include/asm/smp_twd.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __ASMARM_SMP_TWD_H -#define __ASMARM_SMP_TWD_H - -struct clock_event_device; - -extern void __iomem *twd_base; - -void twd_timer_stop(void); -int twd_timer_ack(void); -void twd_timer_setup(struct clock_event_device *); - -#endif diff --git a/trunk/arch/arm/include/asm/system.h b/trunk/arch/arm/include/asm/system.h index d65b2f5bf41f..bd4dc8ed53d5 100644 --- a/trunk/arch/arm/include/asm/system.h +++ b/trunk/arch/arm/include/asm/system.h @@ -248,8 +248,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size unsigned int tmp; #endif - smp_mb(); - switch (size) { #if __LINUX_ARM_ARCH__ >= 6 case 1: @@ -309,7 +307,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size __bad_xchg(ptr, size), ret = 0; break; } - smp_mb(); return ret; } @@ -319,12 +316,6 @@ extern void enable_hlt(void); #include -#if __LINUX_ARM_ARCH__ < 6 - -#ifdef CONFIG_SMP -#error "SMP is not supported on this platform" -#endif - /* * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make * them available. @@ -338,173 +329,6 @@ extern void enable_hlt(void); #include #endif -#else /* __LINUX_ARM_ARCH__ >= 6 */ - -extern void __bad_cmpxchg(volatile void *ptr, int size); - -/* - * cmpxchg only support 32-bits operands on ARMv6. - */ - -static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, - unsigned long new, int size) -{ - unsigned long oldval, res; - - switch (size) { -#ifdef CONFIG_CPU_32v6K - case 1: - do { - asm volatile("@ __cmpxchg1\n" - " ldrexb %1, [%2]\n" - " mov %0, #0\n" - " teq %1, %3\n" - " strexbeq %0, %4, [%2]\n" - : "=&r" (res), "=&r" (oldval) - : "r" (ptr), "Ir" (old), "r" (new) - : "memory", "cc"); - } while (res); - break; - case 2: - do { - asm volatile("@ __cmpxchg1\n" - " ldrexh %1, [%2]\n" - " mov %0, #0\n" - " teq %1, %3\n" - " strexheq %0, %4, [%2]\n" - : "=&r" (res), "=&r" (oldval) - : "r" (ptr), "Ir" (old), "r" (new) - : "memory", "cc"); - } while (res); - break; -#endif /* CONFIG_CPU_32v6K */ - case 4: - do { - asm volatile("@ __cmpxchg4\n" - " ldrex %1, [%2]\n" - " mov %0, #0\n" - " teq %1, %3\n" - " strexeq %0, %4, [%2]\n" - : "=&r" (res), "=&r" (oldval) - : "r" (ptr), "Ir" (old), "r" (new) - : "memory", "cc"); - } while (res); - break; - default: - __bad_cmpxchg(ptr, size); - oldval = 0; - } - - return oldval; -} - -static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old, - unsigned long new, int size) -{ - unsigned long ret; - - smp_mb(); - ret = __cmpxchg(ptr, old, new, size); - smp_mb(); - - return ret; -} - -#define cmpxchg(ptr,o,n) \ - ((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \ - (unsigned long)(o), \ - (unsigned long)(n), \ - sizeof(*(ptr)))) - -static inline unsigned long __cmpxchg_local(volatile void *ptr, - unsigned long old, - unsigned long new, int size) -{ - unsigned long ret; - - switch (size) { -#ifndef CONFIG_CPU_32v6K - case 1: - case 2: - ret = __cmpxchg_local_generic(ptr, old, new, size); - break; -#endif /* !CONFIG_CPU_32v6K */ - default: - ret = __cmpxchg(ptr, old, new, size); - } - - return ret; -} - -#define cmpxchg_local(ptr,o,n) \ - ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \ - (unsigned long)(o), \ - (unsigned long)(n), \ - sizeof(*(ptr)))) - -#ifdef CONFIG_CPU_32v6K - -/* - * Note : ARMv7-M (currently unsupported by Linux) does not support - * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should - * not be allowed to use __cmpxchg64. - */ -static inline unsigned long long __cmpxchg64(volatile void *ptr, - unsigned long long old, - unsigned long long new) -{ - register unsigned long long oldval asm("r0"); - register unsigned long long __old asm("r2") = old; - register unsigned long long __new asm("r4") = new; - unsigned long res; - - do { - asm volatile( - " @ __cmpxchg8\n" - " ldrexd %1, %H1, [%2]\n" - " mov %0, #0\n" - " teq %1, %3\n" - " teqeq %H1, %H3\n" - " strexdeq %0, %4, %H4, [%2]\n" - : "=&r" (res), "=&r" (oldval) - : "r" (ptr), "Ir" (__old), "r" (__new) - : "memory", "cc"); - } while (res); - - return oldval; -} - -static inline unsigned long long __cmpxchg64_mb(volatile void *ptr, - unsigned long long old, - unsigned long long new) -{ - unsigned long long ret; - - smp_mb(); - ret = __cmpxchg64(ptr, old, new); - smp_mb(); - - return ret; -} - -#define cmpxchg64(ptr,o,n) \ - ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \ - (unsigned long long)(o), \ - (unsigned long long)(n))) - -#define cmpxchg64_local(ptr,o,n) \ - ((__typeof__(*(ptr)))__cmpxchg64((ptr), \ - (unsigned long long)(o), \ - (unsigned long long)(n))) - -#else /* !CONFIG_CPU_32v6K */ - -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#endif /* CONFIG_CPU_32v6K */ - -#endif /* __LINUX_ARM_ARCH__ >= 6 */ - #endif /* __ASSEMBLY__ */ #define arch_align_stack(x) (x) diff --git a/trunk/arch/arm/kernel/Makefile b/trunk/arch/arm/kernel/Makefile index ff89d0b3abc5..11a5197a221f 100644 --- a/trunk/arch/arm/kernel/Makefile +++ b/trunk/arch/arm/kernel/Makefile @@ -22,8 +22,6 @@ obj-$(CONFIG_ARTHUR) += arthur.o obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o -obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o diff --git a/trunk/arch/arm/kernel/elf.c b/trunk/arch/arm/kernel/elf.c index 950391f194c4..d4a0da1e48f4 100644 --- a/trunk/arch/arm/kernel/elf.c +++ b/trunk/arch/arm/kernel/elf.c @@ -78,15 +78,6 @@ int arm_elf_read_implies_exec(const struct elf32_hdr *x, int executable_stack) return 1; if (cpu_architecture() < CPU_ARCH_ARMv6) return 1; -#if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT) - /* - * If we have support for OABI programs, we can never allow NX - * support - our signal syscall restart mechanism relies upon - * being able to execute code placed on the user stack. - */ - return 1; -#else return 0; -#endif } EXPORT_SYMBOL(arm_elf_read_implies_exec); diff --git a/trunk/arch/arm/kernel/entry-armv.S b/trunk/arch/arm/kernel/entry-armv.S index 83b1da6b7baa..d662a2f1fd85 100644 --- a/trunk/arch/arm/kernel/entry-armv.S +++ b/trunk/arch/arm/kernel/entry-armv.S @@ -815,7 +815,10 @@ __kuser_helper_start: */ __kuser_memory_barrier: @ 0xffff0fa0 - smp_dmb + +#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) + mcr p15, 0, r0, c7, c10, 5 @ dmb +#endif usr_ret lr .align 5 diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c index 0d8097fa4ca5..6014dfd22af4 100644 --- a/trunk/arch/arm/kernel/smp.c +++ b/trunk/arch/arm/kernel/smp.c @@ -22,8 +22,6 @@ #include #include #include -#include -#include #include #include @@ -34,7 +32,6 @@ #include #include #include -#include /* * as from 2.5, kernels no longer have an init_tasks structure @@ -166,7 +163,7 @@ int __cpuexit __cpu_disable(void) * Take this CPU offline. Once we clear this, we can't return, * and we must not schedule until we're ready to give up the cpu. */ - set_cpu_online(cpu, false); + cpu_clear(cpu, cpu_online_map); /* * OK - migrate IRQs away from this CPU @@ -277,9 +274,9 @@ asmlinkage void __cpuinit secondary_start_kernel(void) local_fiq_enable(); /* - * Setup the percpu timer for this CPU. + * Setup local timer for this CPU. */ - percpu_timer_setup(); + local_timer_setup(); calibrate_delay(); @@ -288,7 +285,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void) /* * OK, now it's safe to let the boot CPU continue */ - set_cpu_online(cpu, true); + cpu_set(cpu, cpu_online_map); /* * OK, it's off to the idle thread for us @@ -386,16 +383,10 @@ void show_local_irqs(struct seq_file *p) seq_putc(p, '\n'); } -/* - * Timer (local or broadcast) support - */ -static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent); - static void ipi_timer(void) { - struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent); irq_enter(); - evt->event_handler(evt); + local_timer_interrupt(); irq_exit(); } @@ -414,42 +405,6 @@ asmlinkage void __exception do_local_timer(struct pt_regs *regs) } #endif -#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST -static void smp_timer_broadcast(const struct cpumask *mask) -{ - send_ipi_message(mask, IPI_TIMER); -} - -static void broadcast_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ -} - -static void local_timer_setup(struct clock_event_device *evt) -{ - evt->name = "dummy_timer"; - evt->features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DUMMY; - evt->rating = 400; - evt->mult = 1; - evt->set_mode = broadcast_timer_set_mode; - evt->broadcast = smp_timer_broadcast; - - clockevents_register_device(evt); -} -#endif - -void __cpuinit percpu_timer_setup(void) -{ - unsigned int cpu = smp_processor_id(); - struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); - - evt->cpumask = cpumask_of(cpu); - - local_timer_setup(evt); -} - static DEFINE_SPINLOCK(stop_lock); /* @@ -462,7 +417,7 @@ static void ipi_cpu_stop(unsigned int cpu) dump_stack(); spin_unlock(&stop_lock); - set_cpu_online(cpu, false); + cpu_clear(cpu, cpu_online_map); local_fiq_disable(); local_irq_disable(); @@ -546,6 +501,11 @@ void smp_send_reschedule(int cpu) send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE); } +void smp_timer_broadcast(const struct cpumask *mask) +{ + send_ipi_message(mask, IPI_TIMER); +} + void smp_send_stop(void) { cpumask_t mask = cpu_online_map; diff --git a/trunk/arch/arm/kernel/smp_scu.c b/trunk/arch/arm/kernel/smp_scu.c deleted file mode 100644 index d3831f616ee9..000000000000 --- a/trunk/arch/arm/kernel/smp_scu.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/arm/kernel/smp_scu.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include - -#include -#include - -#define SCU_CTRL 0x00 -#define SCU_CONFIG 0x04 -#define SCU_CPU_STATUS 0x08 -#define SCU_INVALIDATE 0x0c -#define SCU_FPGA_REVISION 0x10 - -/* - * Get the number of CPU cores from the SCU configuration - */ -unsigned int __init scu_get_core_count(void __iomem *scu_base) -{ - unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG); - return (ncores & 0x03) + 1; -} - -/* - * Enable the SCU - */ -void __init scu_enable(void __iomem *scu_base) -{ - u32 scu_ctrl; - - scu_ctrl = __raw_readl(scu_base + SCU_CTRL); - scu_ctrl |= 1; - __raw_writel(scu_ctrl, scu_base + SCU_CTRL); - - /* - * Ensure that the data accessed by CPU0 before the SCU was - * initialised is visible to the other CPUs. - */ - flush_cache_all(); -} diff --git a/trunk/arch/arm/kernel/smp_twd.c b/trunk/arch/arm/kernel/smp_twd.c deleted file mode 100644 index d8c88c633c6f..000000000000 --- a/trunk/arch/arm/kernel/smp_twd.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * linux/arch/arm/kernel/smp_twd.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define TWD_TIMER_LOAD 0x00 -#define TWD_TIMER_COUNTER 0x04 -#define TWD_TIMER_CONTROL 0x08 -#define TWD_TIMER_INTSTAT 0x0C - -#define TWD_WDOG_LOAD 0x20 -#define TWD_WDOG_COUNTER 0x24 -#define TWD_WDOG_CONTROL 0x28 -#define TWD_WDOG_INTSTAT 0x2C -#define TWD_WDOG_RESETSTAT 0x30 -#define TWD_WDOG_DISABLE 0x34 - -#define TWD_TIMER_CONTROL_ENABLE (1 << 0) -#define TWD_TIMER_CONTROL_ONESHOT (0 << 1) -#define TWD_TIMER_CONTROL_PERIODIC (1 << 1) -#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) - -/* set up by the platform code */ -void __iomem *twd_base; - -static unsigned long twd_timer_rate; - -static void twd_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk) -{ - unsigned long ctrl; - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - /* timer load already set up */ - ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE - | TWD_TIMER_CONTROL_PERIODIC; - break; - case CLOCK_EVT_MODE_ONESHOT: - /* period set, and timer enabled in 'next_event' hook */ - ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT; - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - default: - ctrl = 0; - } - - __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL); -} - -static int twd_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL); - - ctrl |= TWD_TIMER_CONTROL_ENABLE; - - __raw_writel(evt, twd_base + TWD_TIMER_COUNTER); - __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL); - - return 0; -} - -/* - * local_timer_ack: checks for a local timer interrupt. - * - * If a local timer interrupt has occurred, acknowledge and return 1. - * Otherwise, return 0. - */ -int twd_timer_ack(void) -{ - if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) { - __raw_writel(1, twd_base + TWD_TIMER_INTSTAT); - return 1; - } - - return 0; -} - -static void __cpuinit twd_calibrate_rate(void) -{ - unsigned long load, count; - u64 waitjiffies; - - /* - * If this is the first time round, we need to work out how fast - * the timer ticks - */ - if (twd_timer_rate == 0) { - printk(KERN_INFO "Calibrating local timer... "); - - /* Wait for a tick to start */ - waitjiffies = get_jiffies_64() + 1; - - while (get_jiffies_64() < waitjiffies) - udelay(10); - - /* OK, now the tick has started, let's get the timer going */ - waitjiffies += 5; - - /* enable, no interrupt or reload */ - __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL); - - /* maximum value */ - __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); - - while (get_jiffies_64() < waitjiffies) - udelay(10); - - count = __raw_readl(twd_base + TWD_TIMER_COUNTER); - - twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); - - printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000, - (twd_timer_rate / 100000) % 100); - } - - load = twd_timer_rate / HZ; - - __raw_writel(load, twd_base + TWD_TIMER_LOAD); -} - -/* - * Setup the local clock events for a CPU. - */ -void __cpuinit twd_timer_setup(struct clock_event_device *clk) -{ - unsigned long flags; - - twd_calibrate_rate(); - - clk->name = "local_timer"; - clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - clk->rating = 350; - clk->set_mode = twd_set_mode; - clk->set_next_event = twd_set_next_event; - clk->shift = 20; - clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift); - clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); - clk->min_delta_ns = clockevent_delta2ns(0xf, clk); - - /* Make sure our local interrupt controller has this enabled */ - local_irq_save(flags); - get_irq_chip(clk->irq)->unmask(clk->irq); - local_irq_restore(flags); - - clockevents_register_device(clk); -} - -/* - * take a local timer down - */ -void __cpuexit twd_timer_stop(void) -{ - __raw_writel(0, twd_base + TWD_TIMER_CONTROL); -} diff --git a/trunk/arch/arm/lib/bitops.h b/trunk/arch/arm/lib/bitops.h index c7f2627385e7..2e787d40d599 100644 --- a/trunk/arch/arm/lib/bitops.h +++ b/trunk/arch/arm/lib/bitops.h @@ -18,14 +18,12 @@ mov r2, #1 add r1, r1, r0, lsr #3 @ Get byte offset mov r3, r2, lsl r3 @ create mask - smp_dmb 1: ldrexb r2, [r1] ands r0, r2, r3 @ save old value of bit \instr r2, r2, r3 @ toggle bit strexb ip, r2, [r1] cmp ip, #0 bne 1b - smp_dmb cmp r0, #0 movne r0, #1 2: mov pc, lr diff --git a/trunk/arch/arm/mach-at91/board-afeb-9260v1.c b/trunk/arch/arm/mach-at91/board-afeb-9260v1.c index 970fd6b6753e..e263fda3e2d1 100644 --- a/trunk/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/trunk/arch/arm/mach-at91/board-afeb-9260v1.c @@ -156,8 +156,6 @@ static struct atmel_nand_data __initdata afeb9260_nand_data = { * MCI (SD/MMC) */ static struct at91_mmc_data __initdata afeb9260_mmc_data = { - .det_pin = AT91_PIN_PC9, - .wp_pin = AT91_PIN_PC4, .slot_b = 1, .wire4 = 1, }; @@ -166,8 +164,6 @@ static struct at91_mmc_data __initdata afeb9260_mmc_data = { static struct i2c_board_info __initdata afeb9260_i2c_devices[] = { { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, { I2C_BOARD_INFO("fm3130", 0x68), }, { I2C_BOARD_INFO("24c64", 0x50), @@ -200,8 +196,6 @@ static void __init afeb9260_board_init(void) /* I2C */ at91_add_device_i2c(afeb9260_i2c_devices, ARRAY_SIZE(afeb9260_i2c_devices)); - /* Audio */ - at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); } MACHINE_START(AFEB9260, "Custom afeb9260 board") diff --git a/trunk/arch/arm/mach-at91/board-sam9g20ek.c b/trunk/arch/arm/mach-at91/board-sam9g20ek.c index cc270beadd5d..438efbb17482 100644 --- a/trunk/arch/arm/mach-at91/board-sam9g20ek.c +++ b/trunk/arch/arm/mach-at91/board-sam9g20ek.c @@ -218,13 +218,6 @@ static struct gpio_led ek_leds[] = { } }; -static struct i2c_board_info __initdata ek_i2c_devices[] = { - { - I2C_BOARD_INFO("24c512", 0x50), - }, -}; - - static void __init ek_board_init(void) { /* Serial */ @@ -242,7 +235,7 @@ static void __init ek_board_init(void) /* MMC */ at91_add_device_mmc(0, &ek_mmc_data); /* I2C */ - at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); + at91_add_device_i2c(NULL, 0); /* LEDs */ at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); /* PCK0 provides MCLK to the WM8731 */ diff --git a/trunk/arch/arm/mach-at91/clock.c b/trunk/arch/arm/mach-at91/clock.c index bac578fe0d3d..e4345106ee57 100644 --- a/trunk/arch/arm/mach-at91/clock.c +++ b/trunk/arch/arm/mach-at91/clock.c @@ -43,25 +43,6 @@ #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) -/* - * Chips have some kind of clocks : group them by functionality - */ -#define cpu_has_utmi() ( cpu_is_at91cap9() \ - || cpu_is_at91sam9rl()) - -#define cpu_has_800M_plla() (cpu_is_at91sam9g20()) - -#define cpu_has_pllb() (!cpu_is_at91sam9rl()) - -#define cpu_has_upll() (0) - -/* USB host HS & FS */ -#define cpu_has_uhp() (!cpu_is_at91sam9rl()) - -/* USB device FS only */ -#define cpu_has_udpfs() (!cpu_is_at91sam9rl()) - - static LIST_HEAD(clocks); static DEFINE_SPINLOCK(clk_lock); @@ -159,7 +140,7 @@ static struct clk utmi_clk = { }; static struct clk uhpck = { .name = "uhpck", - /*.parent = ... we choose parent at runtime */ + .parent = &pllb, .mode = pmc_sys_mode, }; @@ -192,11 +173,7 @@ static struct clk __init *at91_css_to_clk(unsigned long css) case AT91_PMC_CSS_PLLA: return &plla; case AT91_PMC_CSS_PLLB: - if (cpu_has_upll()) - /* CSS_PLLB == CSS_UPLL */ - return &utmi_clk; - else if (cpu_has_pllb()) - return &pllb; + return &pllb; } return NULL; @@ -345,7 +322,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) u32 pckr; pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); - pckr &= AT91_PMC_CSS; /* clock selection */ + pckr &= AT91_PMC_CSS_PLLB; /* clock selection */ pckr |= prescale << 2; at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); clk->rate_hz = actual; @@ -384,7 +361,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) } EXPORT_SYMBOL(clk_set_parent); -/* establish PCK0..PCKN parentage and rate */ +/* establish PCK0..PCK3 parentage and rate */ static void __init init_programmable_clock(struct clk *clk) { struct clk *parent; @@ -412,13 +389,11 @@ static int at91_clk_show(struct seq_file *s, void *unused) seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); - if (cpu_has_pllb()) + if (!cpu_is_at91sam9rl()) seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); - if (cpu_has_utmi()) + if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); - if (cpu_has_upll()) - seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB)); seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); seq_printf(s, "\n"); @@ -579,60 +554,16 @@ static struct clk *const standard_pmc_clocks[] __initdata = { &clk32k, &main_clk, &plla, + &pllb, + + /* PLLB children (USB) */ + &udpck, + &uhpck, /* MCK */ &mck }; -/* PLLB generated USB full speed clock init */ -static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) -{ - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - uhpck.parent = &pllb; - - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - if (cpu_is_at91rm9200()) { - uhpck.pmc_mask = AT91RM9200_PMC_UHP; - udpck.pmc_mask = AT91RM9200_PMC_UDP; - at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); - } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { - uhpck.pmc_mask = AT91SAM926x_PMC_UHP; - udpck.pmc_mask = AT91SAM926x_PMC_UDP; - } else if (cpu_is_at91cap9()) { - uhpck.pmc_mask = AT91CAP9_PMC_UHP; - } - at91_sys_write(AT91_CKGR_PLLBR, 0); - - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); -} - -/* UPLL generated USB full speed clock init */ -static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) -{ - /* - * USB clock init: choose 480 MHz from UPLL, - */ - unsigned int usbr = AT91_PMC_USBS_UPLL; - - /* Setup divider by 10 to reach 48 MHz */ - usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; - - at91_sys_write(AT91_PMC_USB, usbr); - - /* Now set uhpck values */ - uhpck.parent = &utmi_clk; - uhpck.pmc_mask = AT91SAM926x_PMC_UHP; - uhpck.rate_hz = utmi_clk.parent->rate_hz; - uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); -} - int __init at91_clock_init(unsigned long main_clock) { unsigned tmp, freq, mckr; @@ -654,37 +585,43 @@ int __init at91_clock_init(unsigned long main_clock) /* report if PLLA is more than mildly overclocked */ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000) - || (cpu_has_800M_plla() && plla.rate_hz > 800000000)) + if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000) + || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000)) pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - - if (cpu_has_upll() && !cpu_has_pllb()) { - /* setup UTMI clock as the fourth primary clock - * (instead of pllb) */ - utmi_clk.type |= CLK_TYPE_PRIMARY; - utmi_clk.id = 3; + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); + if (cpu_is_at91rm9200()) { + uhpck.pmc_mask = AT91RM9200_PMC_UHP; + udpck.pmc_mask = AT91RM9200_PMC_UDP; + at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); + } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { + uhpck.pmc_mask = AT91SAM926x_PMC_UHP; + udpck.pmc_mask = AT91SAM926x_PMC_UDP; + } else if (cpu_is_at91cap9()) { + uhpck.pmc_mask = AT91CAP9_PMC_UHP; } + at91_sys_write(AT91_CKGR_PLLBR, 0); + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); /* * USB HS clock init */ - if (cpu_has_utmi()) + if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) { /* * multiplier is hard-wired to 40 * (obtain the USB High Speed 480 MHz when input is 12 MHz) */ utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; - - /* - * USB FS clock init - */ - if (cpu_has_pllb()) - at91_pllb_usbfs_clock_init(main_clock); - if (cpu_has_upll()) - /* assumes that we choose UPLL for USB and not PLLA */ - at91_upll_usbfs_clock_init(main_clock); + } /* * MCK and CPU derive from one of those primary clocks. @@ -694,31 +631,21 @@ int __init at91_clock_init(unsigned long main_clock) mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); freq = mck.parent->rate_hz; freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - if (cpu_is_at91rm9200()) { + if (cpu_is_at91rm9200()) mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - } else if (cpu_is_at91sam9g20()) { + else if (cpu_is_at91sam9g20()) { mck.rate_hz = (mckr & AT91_PMC_MDIV) ? freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ if (mckr & AT91_PMC_PDIV) freq /= 2; /* processor clock division */ - } else { + } else mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - } /* Register the PMC's standard clocks */ for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) list_add_tail(&standard_pmc_clocks[i]->node, &clocks); - if (cpu_has_pllb()) - list_add_tail(&pllb.node, &clocks); - - if (cpu_has_uhp()) - list_add_tail(&uhpck.node, &clocks); - - if (cpu_has_udpfs()) - list_add_tail(&udpck.node, &clocks); - - if (cpu_has_utmi()) + if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) list_add_tail(&utmi_clk.node, &clocks); /* MCK and CPU clock are "always on" */ diff --git a/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h b/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h index 64589eaaaee8..9561e33b8a9a 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -23,7 +23,7 @@ #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ @@ -39,11 +39,11 @@ #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ +#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ @@ -72,7 +72,6 @@ #define AT91_PMC_CSS_MAIN (1 << 0) #define AT91_PMC_CSS_PLLA (2 << 0) #define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ #define AT91_PMC_PRES_1 (0 << 2) #define AT91_PMC_PRES_2 (1 << 2) @@ -89,25 +88,12 @@ #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ #define AT91SAM9_PMC_MDIV_2 (1 << 8) #define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ +#define AT91SAM9_PMC_MDIV_6 (3 << 8) #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ #define AT91_PMC_PDIV_1 (0 << 12) #define AT91_PMC_PDIV_2 (1 << 12) -#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ -#define AT91_PMC_PLLADIV2_OFF (0 << 12) -#define AT91_PMC_PLLADIV2_ON (1 << 12) -#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ -#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ -#define AT91_PMC_USBS_PLLA (0 << 0) -#define AT91_PMC_USBS_UPLL (1 << 0) -#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ - -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ -#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ -#define AT91_PMC_CSSMCK_CSS (0 << 8) -#define AT91_PMC_CSSMCK_MCK (1 << 8) +#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ @@ -116,7 +102,7 @@ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ #define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ diff --git a/trunk/arch/arm/mach-davinci/Kconfig b/trunk/arch/arm/mach-davinci/Kconfig index be747f5c6cd8..a9c78bc72b84 100644 --- a/trunk/arch/arm/mach-davinci/Kconfig +++ b/trunk/arch/arm/mach-davinci/Kconfig @@ -1,26 +1,11 @@ if ARCH_DAVINCI -config AINTC - bool - -config CP_INTC - bool - menu "TI DaVinci Implementations" comment "DaVinci Core Type" config ARCH_DAVINCI_DM644x bool "DaVinci 644x based system" - select AINTC - -config ARCH_DAVINCI_DM355 - bool "DaVinci 355 based system" - select AINTC - -config ARCH_DAVINCI_DM646x - bool "DaVinci 646x based system" - select AINTC comment "DaVinci Board Type" @@ -32,34 +17,6 @@ config MACH_DAVINCI_EVM Configure this option to specify the whether the board used for development is a DM644x EVM -config MACH_SFFSDR - bool "Lyrtech SFFSDR" - depends on ARCH_DAVINCI_DM644x - help - Say Y here to select the Lyrtech Small Form Factor - Software Defined Radio (SFFSDR) board. - -config MACH_DAVINCI_DM355_EVM - bool "TI DM355 EVM" - depends on ARCH_DAVINCI_DM355 - help - Configure this option to specify the whether the board used - for development is a DM355 EVM - -config MACH_DM355_LEOPARD - bool "DM355 Leopard board" - depends on ARCH_DAVINCI_DM355 - help - Configure this option to specify the whether the board used - for development is a DM355 Leopard board. - -config MACH_DAVINCI_DM6467_EVM - bool "TI DM6467 EVM" - depends on ARCH_DAVINCI_DM646x - help - Configure this option to specify the whether the board used - for development is a DM6467 EVM - config DAVINCI_MUX bool "DAVINCI multiplexing support" diff --git a/trunk/arch/arm/mach-davinci/Makefile b/trunk/arch/arm/mach-davinci/Makefile index 059ab78084ba..1674661942f3 100644 --- a/trunk/arch/arm/mach-davinci/Makefile +++ b/trunk/arch/arm/mach-davinci/Makefile @@ -4,22 +4,13 @@ # # Common objects -obj-y := time.o clock.o serial.o io.o psc.o \ - gpio.o devices.o dma.o usb.o common.o sram.o +obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ + gpio.o devices.o dma.o usb.o obj-$(CONFIG_DAVINCI_MUX) += mux.o # Chip specific obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o -obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o -obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o - -obj-$(CONFIG_AINTC) += irq.o -obj-$(CONFIG_CP_INTC) += cp_intc.o # Board specific obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o -obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o -obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o -obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o -obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o diff --git a/trunk/arch/arm/mach-davinci/board-dm355-evm.c b/trunk/arch/arm/mach-davinci/board-dm355-evm.c deleted file mode 100644 index 5ac2f565d860..000000000000 --- a/trunk/arch/arm/mach-davinci/board-dm355-evm.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * TI DaVinci EVM board support - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips, maybe with a different block size, partitioning may - * need to be changed. - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW_SYNDROME, - .options = NAND_USE_FLASH_BBT, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, - .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, - - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - - .dev = { - .platform_data = &davinci_nand_data, - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -static int dm355evm_mmc_gpios = -EINVAL; - -static void dm355evm_mmcsd_gpios(unsigned gpio) -{ - gpio_request(gpio + 0, "mmc0_ro"); - gpio_request(gpio + 1, "mmc0_cd"); - gpio_request(gpio + 2, "mmc1_ro"); - gpio_request(gpio + 3, "mmc1_cd"); - - /* we "know" these are input-only so we don't - * need to call gpio_direction_input() - */ - - dm355evm_mmc_gpios = gpio; -} - -static struct i2c_board_info dm355evm_i2c_info[] = { - { I2C_BOARD_INFO("dm355evm_msp", 0x25), - .platform_data = dm355evm_mmcsd_gpios, - /* plus irq */ }, - /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ - /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ -}; - -static void __init evm_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - - gpio_request(5, "dm355evm_msp"); - gpio_direction_input(5); - dm355evm_i2c_info[0].irq = gpio_to_irq(5); - - i2c_register_board_info(1, dm355evm_i2c_info, - ARRAY_SIZE(dm355evm_i2c_info)); -} - -static struct resource dm355evm_dm9000_rsrc[] = { - { - /* addr */ - .start = 0x04014000, - .end = 0x04014001, - .flags = IORESOURCE_MEM, - }, { - /* data */ - .start = 0x04014002, - .end = 0x04014003, - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ - | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, - }, -}; - -static struct platform_device dm355evm_dm9000 = { - .name = "dm9000", - .id = -1, - .resource = dm355evm_dm9000_rsrc, - .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc), -}; - -static struct platform_device *davinci_evm_devices[] __initdata = { - &dm355evm_dm9000, - &davinci_nand_device, -}; - -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - -static void __init dm355_evm_map_io(void) -{ - dm355_init(); -} - -static int dm355evm_mmc_get_cd(int module) -{ - if (!gpio_is_valid(dm355evm_mmc_gpios)) - return -ENXIO; - /* low == card present */ - return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1); -} - -static int dm355evm_mmc_get_ro(int module) -{ - if (!gpio_is_valid(dm355evm_mmc_gpios)) - return -ENXIO; - /* high == card's write protect switch active */ - return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0); -} - -static struct davinci_mmc_config dm355evm_mmc_config = { - .get_cd = dm355evm_mmc_get_cd, - .get_ro = dm355evm_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, - .version = MMC_CTLR_VERSION_1, -}; - -/* Don't connect anything to J10 unless you're only using USB host - * mode *and* have to do so with some kind of gender-bender. If - * you have proper Mini-B or Mini-A cables (or Mini-A adapters) - * the ID pin won't need any help. - */ -#ifdef CONFIG_USB_MUSB_PERIPHERAL -#define USB_ID_VALUE 0 /* ID pulled high; *should* float */ -#else -#define USB_ID_VALUE 1 /* ID pulled low */ -#endif - -static struct spi_eeprom at25640a = { - .byte_len = SZ_64K / 8, - .name = "at25640a", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static struct spi_board_info dm355_evm_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640a, - .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm355_evm_init(void) -{ - struct clk *aemif; - - gpio_request(1, "dm9000"); - gpio_direction_input(1); - dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1); - - aemif = clk_get(&dm355evm_dm9000.dev, "aemif"); - if (IS_ERR(aemif)) - WARN("%s: unable to get AEMIF clock\n", __func__); - else - clk_enable(aemif); - - platform_add_devices(davinci_evm_devices, - ARRAY_SIZE(davinci_evm_devices)); - evm_init_i2c(); - davinci_serial_init(&uart_config); - - /* NOTE: NAND flash timings set by the UBL are slower than - * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 - * but could be 0x0400008c for about 25% faster page reads. - */ - - gpio_request(2, "usb_id_toggle"); - gpio_direction_output(2, USB_ID_VALUE); - /* irlml6401 switches over 1A in under 8 msec */ - setup_usb(500, 8); - - davinci_setup_mmc(0, &dm355evm_mmc_config); - davinci_setup_mmc(1, &dm355evm_mmc_config); - - dm355_init_spi0(BIT(0), dm355_evm_spi_info, - ARRAY_SIZE(dm355_evm_spi_info)); -} - -static __init void dm355_evm_irq_init(void) -{ - davinci_irq_init(); -} - -MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") - .phys_io = IO_PHYS, - .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, - .boot_params = (0x80000100), - .map_io = dm355_evm_map_io, - .init_irq = dm355_evm_irq_init, - .timer = &davinci_timer, - .init_machine = dm355_evm_init, -MACHINE_END diff --git a/trunk/arch/arm/mach-davinci/board-dm355-leopard.c b/trunk/arch/arm/mach-davinci/board-dm355-leopard.c deleted file mode 100644 index 28c9008df4f4..000000000000 --- a/trunk/arch/arm/mach-davinci/board-dm355-leopard.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * DM355 leopard board support - * - * Based on board-dm355-evm.c - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips, maybe with a different block size, partitioning may - * need to be changed. - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW_SYNDROME, - .options = NAND_USE_FLASH_BBT, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, - .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, - - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - - .dev = { - .platform_data = &davinci_nand_data, - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -static int leopard_mmc_gpio = -EINVAL; - -static void dm355leopard_mmcsd_gpios(unsigned gpio) -{ - gpio_request(gpio + 0, "mmc0_ro"); - gpio_request(gpio + 1, "mmc0_cd"); - gpio_request(gpio + 2, "mmc1_ro"); - gpio_request(gpio + 3, "mmc1_cd"); - - /* we "know" these are input-only so we don't - * need to call gpio_direction_input() - */ - - leopard_mmc_gpio = gpio; -} - -static struct i2c_board_info dm355leopard_i2c_info[] = { - { I2C_BOARD_INFO("dm355leopard_msp", 0x25), - .platform_data = dm355leopard_mmcsd_gpios, - /* plus irq */ }, - /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ - /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ -}; - -static void __init leopard_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - - gpio_request(5, "dm355leopard_msp"); - gpio_direction_input(5); - dm355leopard_i2c_info[0].irq = gpio_to_irq(5); - - i2c_register_board_info(1, dm355leopard_i2c_info, - ARRAY_SIZE(dm355leopard_i2c_info)); -} - -static struct resource dm355leopard_dm9000_rsrc[] = { - { - /* addr */ - .start = 0x04000000, - .end = 0x04000001, - .flags = IORESOURCE_MEM, - }, { - /* data */ - .start = 0x04000016, - .end = 0x04000017, - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ - | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, - }, -}; - -static struct platform_device dm355leopard_dm9000 = { - .name = "dm9000", - .id = -1, - .resource = dm355leopard_dm9000_rsrc, - .num_resources = ARRAY_SIZE(dm355leopard_dm9000_rsrc), -}; - -static struct platform_device *davinci_leopard_devices[] __initdata = { - &dm355leopard_dm9000, - &davinci_nand_device, -}; - -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - -static void __init dm355_leopard_map_io(void) -{ - dm355_init(); -} - -static int dm355leopard_mmc_get_cd(int module) -{ - if (!gpio_is_valid(leopard_mmc_gpio)) - return -ENXIO; - /* low == card present */ - return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1); -} - -static int dm355leopard_mmc_get_ro(int module) -{ - if (!gpio_is_valid(leopard_mmc_gpio)) - return -ENXIO; - /* high == card's write protect switch active */ - return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0); -} - -static struct davinci_mmc_config dm355leopard_mmc_config = { - .get_cd = dm355leopard_mmc_get_cd, - .get_ro = dm355leopard_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -/* Don't connect anything to J10 unless you're only using USB host - * mode *and* have to do so with some kind of gender-bender. If - * you have proper Mini-B or Mini-A cables (or Mini-A adapters) - * the ID pin won't need any help. - */ -#ifdef CONFIG_USB_MUSB_PERIPHERAL -#define USB_ID_VALUE 0 /* ID pulled high; *should* float */ -#else -#define USB_ID_VALUE 1 /* ID pulled low */ -#endif - -static struct spi_eeprom at25640a = { - .byte_len = SZ_64K / 8, - .name = "at25640a", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static struct spi_board_info dm355_leopard_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640a, - .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm355_leopard_init(void) -{ - struct clk *aemif; - - gpio_request(9, "dm9000"); - gpio_direction_input(9); - dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9); - - aemif = clk_get(&dm355leopard_dm9000.dev, "aemif"); - if (IS_ERR(aemif)) - WARN("%s: unable to get AEMIF clock\n", __func__); - else - clk_enable(aemif); - - platform_add_devices(davinci_leopard_devices, - ARRAY_SIZE(davinci_leopard_devices)); - leopard_init_i2c(); - davinci_serial_init(&uart_config); - - /* NOTE: NAND flash timings set by the UBL are slower than - * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 - * but could be 0x0400008c for about 25% faster page reads. - */ - - gpio_request(2, "usb_id_toggle"); - gpio_direction_output(2, USB_ID_VALUE); - /* irlml6401 switches over 1A in under 8 msec */ - setup_usb(500, 8); - - davinci_setup_mmc(0, &dm355leopard_mmc_config); - davinci_setup_mmc(1, &dm355leopard_mmc_config); - - dm355_init_spi0(BIT(0), dm355_leopard_spi_info, - ARRAY_SIZE(dm355_leopard_spi_info)); -} - -static __init void dm355_leopard_irq_init(void) -{ - davinci_irq_init(); -} - -MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") - .phys_io = IO_PHYS, - .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, - .boot_params = (0x80000100), - .map_io = dm355_leopard_map_io, - .init_irq = dm355_leopard_irq_init, - .timer = &davinci_timer, - .init_machine = dm355_leopard_init, -MACHINE_END diff --git a/trunk/arch/arm/mach-davinci/board-dm644x-evm.c b/trunk/arch/arm/mach-davinci/board-dm644x-evm.c index d9d40450bdc5..b2e7f9c63bc5 100644 --- a/trunk/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/trunk/arch/arm/mach-davinci/board-dm644x-evm.c @@ -16,11 +16,12 @@ #include #include #include +#include #include #include #include -#include + #include #include #include @@ -43,9 +44,6 @@ #include #include #include -#include -#include -#include #define DM644X_EVM_PHY_MASK (0x2) #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ @@ -438,15 +436,45 @@ static struct pcf857x_platform_data pcf_data_u35 = { * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) * - ... newer boards may have more */ +static struct memory_accessor *at24_mem_acc; + +static void at24_setup(struct memory_accessor *mem_acc, void *context) +{ + DECLARE_MAC_BUF(mac_str); + char mac_addr[6]; + + at24_mem_acc = mem_acc; + + /* Read MAC addr from EEPROM */ + if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) { + printk(KERN_INFO "Read MAC addr from EEPROM: %s\n", + print_mac(mac_str, mac_addr)); + } +} static struct at24_platform_data eeprom_info = { .byte_len = (256*1024) / 8, .page_size = 64, .flags = AT24_FLAG_ADDR16, - .setup = davinci_get_mac_addr, - .context = (void *)0x7f00, + .setup = at24_setup, }; +int dm6446evm_eeprom_read(void *buf, off_t off, size_t count) +{ + if (at24_mem_acc) + return at24_mem_acc->read(at24_mem_acc, buf, off, count); + return -ENODEV; +} +EXPORT_SYMBOL(dm6446evm_eeprom_read); + +int dm6446evm_eeprom_write(void *buf, off_t off, size_t count) +{ + if (at24_mem_acc) + return at24_mem_acc->write(at24_mem_acc, buf, off, count); + return -ENODEV; +} +EXPORT_SYMBOL(dm6446evm_eeprom_write); + /* * MSP430 supports RTC, card detection, input from IR remote, and * a bit more. It triggers interrupts on GPIO(7) from pressing @@ -517,27 +545,6 @@ static int dm6444evm_msp430_get_pins(void) return (buf[3] << 8) | buf[2]; } -static int dm6444evm_mmc_get_cd(int module) -{ - int status = dm6444evm_msp430_get_pins(); - - return (status < 0) ? status : !(status & BIT(1)); -} - -static int dm6444evm_mmc_get_ro(int module) -{ - int status = dm6444evm_msp430_get_pins(); - - return (status < 0) ? status : status & BIT(6 + 8); -} - -static struct davinci_mmc_config dm6446evm_mmc_config = { - .get_cd = dm6444evm_mmc_get_cd, - .get_ro = dm6444evm_mmc_get_ro, - .wires = 4, - .version = MMC_CTLR_VERSION_1 -}; - static struct i2c_board_info __initdata i2c_info[] = { { I2C_BOARD_INFO("dm6446evm_msp", 0x23), @@ -591,6 +598,7 @@ static struct davinci_uart_config uart_config __initdata = { static void __init davinci_evm_map_io(void) { + davinci_map_common_io(); dm644x_init(); } @@ -631,7 +639,6 @@ static int davinci_phy_fixup(struct phy_device *phydev) static __init void davinci_evm_init(void) { struct clk *aemif_clk; - struct davinci_soc_info *soc_info = &davinci_soc_info; aemif_clk = clk_get(NULL, "aemif"); clk_enable(aemif_clk); @@ -664,13 +671,8 @@ static __init void davinci_evm_init(void) ARRAY_SIZE(davinci_evm_devices)); evm_init_i2c(); - davinci_setup_mmc(0, &dm6446evm_mmc_config); - davinci_serial_init(&uart_config); - soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY; - /* Register the fixup for PHY on DaVinci */ phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, davinci_phy_fixup); diff --git a/trunk/arch/arm/mach-davinci/board-dm646x-evm.c b/trunk/arch/arm/mach-davinci/board-dm646x-evm.c deleted file mode 100644 index e17de6352624..000000000000 --- a/trunk/arch/arm/mach-davinci/board-dm646x-evm.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * TI DaVinci DM646X EVM board - * - * Derived from: arch/arm/mach-davinci/board-evm.c - * Copyright (C) 2006 Texas Instruments. - * - * (C) 2007-2008, MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - * - */ - -/************************************************************************** - * Included Files - **************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#define DM646X_EVM_PHY_MASK (0x2) -#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - -/* LEDS */ - -static struct gpio_led evm_leds[] = { - { .name = "DS1", .active_low = 1, }, - { .name = "DS2", .active_low = 1, }, - { .name = "DS3", .active_low = 1, }, - { .name = "DS4", .active_low = 1, }, -}; - -static __initconst struct gpio_led_platform_data evm_led_data = { - .num_leds = ARRAY_SIZE(evm_leds), - .leds = evm_leds, -}; - -static struct platform_device *evm_led_dev; - -static int evm_led_setup(struct i2c_client *client, int gpio, - unsigned int ngpio, void *c) -{ - struct gpio_led *leds = evm_leds; - int status; - - while (ngpio--) { - leds->gpio = gpio++; - leds++; - }; - - evm_led_dev = platform_device_alloc("leds-gpio", 0); - platform_device_add_data(evm_led_dev, &evm_led_data, - sizeof(evm_led_data)); - - evm_led_dev->dev.parent = &client->dev; - status = platform_device_add(evm_led_dev); - if (status < 0) { - platform_device_put(evm_led_dev); - evm_led_dev = NULL; - } - return status; -} - -static int evm_led_teardown(struct i2c_client *client, int gpio, - unsigned ngpio, void *c) -{ - if (evm_led_dev) { - platform_device_unregister(evm_led_dev); - evm_led_dev = NULL; - } - return 0; -} - -static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL }; - -static int evm_sw_setup(struct i2c_client *client, int gpio, - unsigned ngpio, void *c) -{ - int status; - int i; - char label[10]; - - for (i = 0; i < 4; ++i) { - snprintf(label, 10, "user_sw%d", i); - status = gpio_request(gpio, label); - if (status) - goto out_free; - evm_sw_gpio[i] = gpio++; - - status = gpio_direction_input(evm_sw_gpio[i]); - if (status) { - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; - goto out_free; - } - - status = gpio_export(evm_sw_gpio[i], 0); - if (status) { - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; - goto out_free; - } - } - return status; -out_free: - for (i = 0; i < 4; ++i) { - if (evm_sw_gpio[i] != -EINVAL) { - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; - } - } - return status; -} - -static int evm_sw_teardown(struct i2c_client *client, int gpio, - unsigned ngpio, void *c) -{ - int i; - - for (i = 0; i < 4; ++i) { - if (evm_sw_gpio[i] != -EINVAL) { - gpio_unexport(evm_sw_gpio[i]); - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; - } - } - return 0; -} - -static int evm_pcf_setup(struct i2c_client *client, int gpio, - unsigned int ngpio, void *c) -{ - int status; - - if (ngpio < 8) - return -EINVAL; - - status = evm_sw_setup(client, gpio, 4, c); - if (status) - return status; - - return evm_led_setup(client, gpio+4, 4, c); -} - -static int evm_pcf_teardown(struct i2c_client *client, int gpio, - unsigned int ngpio, void *c) -{ - BUG_ON(ngpio < 8); - - evm_sw_teardown(client, gpio, 4, c); - evm_led_teardown(client, gpio+4, 4, c); - - return 0; -} - -static struct pcf857x_platform_data pcf_data = { - .gpio_base = DAVINCI_N_GPIO+1, - .setup = evm_pcf_setup, - .teardown = evm_pcf_teardown, -}; - -/* Most of this EEPROM is unused, but U-Boot uses some data: - * - 0x7f00, 6 bytes Ethernet Address - * - ... newer boards may have more - */ - -static struct at24_platform_data eeprom_info = { - .byte_len = (256*1024) / 8, - .page_size = 64, - .flags = AT24_FLAG_ADDR16, - .setup = davinci_get_mac_addr, - .context = (void *)0x7f00, -}; - -static struct i2c_board_info __initdata i2c_info[] = { - { - I2C_BOARD_INFO("24c256", 0x50), - .platform_data = &eeprom_info, - }, - { - I2C_BOARD_INFO("pcf8574a", 0x38), - .platform_data = &pcf_data, - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 100 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -static void __init evm_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); -} - -static void __init davinci_map_io(void) -{ - dm646x_init(); -} - -static __init void evm_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - - evm_init_i2c(); - davinci_serial_init(&uart_config); - - soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; -} - -static __init void davinci_dm646x_evm_irq_init(void) -{ - davinci_irq_init(); -} - -MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") - .phys_io = IO_PHYS, - .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, - .boot_params = (0x80000100), - .map_io = davinci_map_io, - .init_irq = davinci_dm646x_evm_irq_init, - .timer = &davinci_timer, - .init_machine = evm_init, -MACHINE_END - diff --git a/trunk/arch/arm/mach-davinci/board-sffsdr.c b/trunk/arch/arm/mach-davinci/board-sffsdr.c deleted file mode 100644 index 748a8e48541e..000000000000 --- a/trunk/arch/arm/mach-davinci/board-sffsdr.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Lyrtech SFFSDR board support. - * - * Copyright (C) 2008 Philip Balister, OpenSDR - * Copyright (C) 2008 Lyrtech - * - * Based on DV-EVM platform, original copyright follows: - * - * Copyright (C) 2007 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define SFFSDR_PHY_MASK (0x2) -#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - -#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 - -struct mtd_partition davinci_sffsdr_nandflash_partition[] = { - /* U-Boot Environment: Block 0 - * UBL: Block 1 - * U-Boot: Blocks 6-7 (256 kb) - * Integrity Kernel: Blocks 8-31 (3 Mb) - * Integrity Data: Blocks 100-END - */ - { - .name = "Linux Kernel", - .offset = 32 * SZ_128K, - .size = 16 * SZ_128K, /* 2 Mb */ - .mask_flags = MTD_WRITEABLE, /* Force read-only */ - }, - { - .name = "Linux ROOT", - .offset = MTDPART_OFS_APPEND, - .size = 256 * SZ_128K, /* 32 Mb */ - .mask_flags = 0, /* R/W */ - }, -}; - -static struct flash_platform_data davinci_sffsdr_nandflash_data = { - .parts = davinci_sffsdr_nandflash_partition, - .nr_parts = ARRAY_SIZE(davinci_sffsdr_nandflash_partition), -}; - -static struct resource davinci_sffsdr_nandflash_resource[] = { - { - .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, - .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, - .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_sffsdr_nandflash_device = { - .name = "davinci_nand", /* Name of driver */ - .id = 0, - .dev = { - .platform_data = &davinci_sffsdr_nandflash_data, - }, - .num_resources = ARRAY_SIZE(davinci_sffsdr_nandflash_resource), - .resource = davinci_sffsdr_nandflash_resource, -}; - -static struct emac_platform_data sffsdr_emac_pdata = { - .phy_mask = SFFSDR_PHY_MASK, - .mdio_max_freq = SFFSDR_MDIO_FREQUENCY, -}; - -static struct at24_platform_data eeprom_info = { - .byte_len = (64*1024) / 8, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info __initdata i2c_info[] = { - { - I2C_BOARD_INFO("24lc64", 0x50), - .platform_data = &eeprom_info, - }, - /* Other I2C devices: - * MSP430, addr 0x23 (not used) - * PCA9543, addr 0x70 (setup done by U-Boot) - * ADS7828, addr 0x48 (ADC for voltage monitoring.) - */ -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 20 /* kHz */, - .bus_delay = 100 /* usec */, -}; - -static void __init sffsdr_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); -} - -static struct platform_device *davinci_sffsdr_devices[] __initdata = { - &davinci_sffsdr_nandflash_device, -}; - -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - -static void __init davinci_sffsdr_map_io(void) -{ - dm644x_init(); -} - -static __init void davinci_sffsdr_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - - platform_add_devices(davinci_sffsdr_devices, - ARRAY_SIZE(davinci_sffsdr_devices)); - sffsdr_init_i2c(); - davinci_serial_init(&uart_config); - soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY; - setup_usb(0, 0); /* We support only peripheral mode. */ - - /* mux VLYNQ pins */ - davinci_cfg_reg(DM644X_VLYNQEN); - davinci_cfg_reg(DM644X_VLYNQWD); -} - -static __init void davinci_sffsdr_irq_init(void) -{ - davinci_irq_init(); -} - -MACHINE_START(SFFSDR, "Lyrtech SFFSDR") - /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */ - .phys_io = IO_PHYS, - .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, - .boot_params = (DAVINCI_DDR_BASE + 0x100), - .map_io = davinci_sffsdr_map_io, - .init_irq = davinci_sffsdr_irq_init, - .timer = &davinci_timer, - .init_machine = davinci_sffsdr_init, -MACHINE_END diff --git a/trunk/arch/arm/mach-davinci/clock.c b/trunk/arch/arm/mach-davinci/clock.c index 39bf321d70a2..f0baaa15a57e 100644 --- a/trunk/arch/arm/mach-davinci/clock.c +++ b/trunk/arch/arm/mach-davinci/clock.c @@ -42,8 +42,7 @@ static void __clk_enable(struct clk *clk) if (clk->parent) __clk_enable(clk->parent); if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) - davinci_psc_config(psc_domain(clk), clk->psc_ctlr, - clk->lpsc, 1); + davinci_psc_config(psc_domain(clk), clk->lpsc, 1); } static void __clk_disable(struct clk *clk) @@ -51,8 +50,7 @@ static void __clk_disable(struct clk *clk) if (WARN_ON(clk->usecount == 0)) return; if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) - davinci_psc_config(psc_domain(clk), clk->psc_ctlr, - clk->lpsc, 0); + davinci_psc_config(psc_domain(clk), clk->lpsc, 0); if (clk->parent) __clk_disable(clk->parent); } @@ -166,11 +164,11 @@ static int __init clk_disable_unused(void) continue; /* ignore if in Disabled or SwRstDisable states */ - if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc)) + if (!davinci_psc_is_clk_active(ck->lpsc)) continue; pr_info("Clocks: disable unused %s\n", ck->name); - davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0); + davinci_psc_config(psc_domain(ck), ck->lpsc, 0); } spin_unlock_irq(&clockfw_lock); diff --git a/trunk/arch/arm/mach-davinci/clock.h b/trunk/arch/arm/mach-davinci/clock.h index 27233cb4a2fb..35736ec202f8 100644 --- a/trunk/arch/arm/mach-davinci/clock.h +++ b/trunk/arch/arm/mach-davinci/clock.h @@ -67,7 +67,6 @@ struct clk { u8 usecount; u8 flags; u8 lpsc; - u8 psc_ctlr; struct clk *parent; struct pll_data *pll_data; u32 div_reg; @@ -94,7 +93,4 @@ struct davinci_clk { } int davinci_clk_init(struct davinci_clk *clocks); - -extern struct platform_device davinci_wdt_device; - #endif diff --git a/trunk/arch/arm/mach-davinci/common.c b/trunk/arch/arm/mach-davinci/common.c deleted file mode 100644 index 61ede19c6b54..000000000000 --- a/trunk/arch/arm/mach-davinci/common.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Code commons to all DaVinci SoCs. - * - * Author: Mark A. Greer - * - * 2009 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "clock.h" - -struct davinci_soc_info davinci_soc_info; -EXPORT_SYMBOL(davinci_soc_info); - -void __iomem *davinci_intc_base; -int davinci_intc_type; - -void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context) -{ - char *mac_addr = davinci_soc_info.emac_pdata->mac_addr; - off_t offset = (off_t)context; - - /* Read MAC addr from EEPROM */ - if (mem_acc->read(mem_acc, mac_addr, offset, ETH_ALEN) == ETH_ALEN) - pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr); -} - -static struct davinci_id * __init davinci_get_id(u32 jtag_id) -{ - int i; - struct davinci_id *dip; - u8 variant = (jtag_id & 0xf0000000) >> 28; - u16 part_no = (jtag_id & 0x0ffff000) >> 12; - - for (i = 0, dip = davinci_soc_info.ids; i < davinci_soc_info.ids_num; - i++, dip++) - /* Don't care about the manufacturer right now */ - if ((dip->part_no == part_no) && (dip->variant == variant)) - return dip; - - return NULL; -} - -void __init davinci_common_init(struct davinci_soc_info *soc_info) -{ - int ret; - struct davinci_id *dip; - - if (!soc_info) { - ret = -EINVAL; - goto err; - } - - memcpy(&davinci_soc_info, soc_info, sizeof(struct davinci_soc_info)); - - if (davinci_soc_info.io_desc && (davinci_soc_info.io_desc_num > 0)) - iotable_init(davinci_soc_info.io_desc, - davinci_soc_info.io_desc_num); - - /* - * Normally devicemaps_init() would flush caches and tlb after - * mdesc->map_io(), but we must also do it here because of the CPU - * revision check below. - */ - local_flush_tlb_all(); - flush_cache_all(); - - /* - * We want to check CPU revision early for cpu_is_xxxx() macros. - * IO space mapping must be initialized before we can do that. - */ - davinci_soc_info.jtag_id = __raw_readl(davinci_soc_info.jtag_id_base); - - dip = davinci_get_id(davinci_soc_info.jtag_id); - if (!dip) { - ret = -EINVAL; - goto err; - } - - davinci_soc_info.cpu_id = dip->cpu_id; - pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant); - - if (davinci_soc_info.cpu_clks) { - ret = davinci_clk_init(davinci_soc_info.cpu_clks); - - if (ret != 0) - goto err; - } - - davinci_intc_base = davinci_soc_info.intc_base; - davinci_intc_type = davinci_soc_info.intc_type; - return; - -err: - pr_err("davinci_common_init: SoC Initialization failed\n"); -} diff --git a/trunk/arch/arm/mach-davinci/cp_intc.c b/trunk/arch/arm/mach-davinci/cp_intc.c deleted file mode 100644 index 96c8e97a7deb..000000000000 --- a/trunk/arch/arm/mach-davinci/cp_intc.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * TI Common Platform Interrupt Controller (cp_intc) driver - * - * Author: Steve Chen - * Copyright (C) 2008-2009, MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include - -#include - -static void __iomem *cp_intc_base; - -static inline unsigned int cp_intc_read(unsigned offset) -{ - return __raw_readl(cp_intc_base + offset); -} - -static inline void cp_intc_write(unsigned long value, unsigned offset) -{ - __raw_writel(value, cp_intc_base + offset); -} - -static void cp_intc_ack_irq(unsigned int irq) -{ - cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR); -} - -/* Disable interrupt */ -static void cp_intc_mask_irq(unsigned int irq) -{ - /* XXX don't know why we need to disable nIRQ here... */ - cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); - cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR); - cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); -} - -/* Enable interrupt */ -static void cp_intc_unmask_irq(unsigned int irq) -{ - cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET); -} - -static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type) -{ - unsigned reg = BIT_WORD(irq); - unsigned mask = BIT_MASK(irq); - unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); - unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); - - switch (flow_type) { - case IRQ_TYPE_EDGE_RISING: - polarity |= mask; - type |= mask; - break; - case IRQ_TYPE_EDGE_FALLING: - polarity &= ~mask; - type |= mask; - break; - case IRQ_TYPE_LEVEL_HIGH: - polarity |= mask; - type &= ~mask; - break; - case IRQ_TYPE_LEVEL_LOW: - polarity &= ~mask; - type &= ~mask; - break; - default: - return -EINVAL; - } - - cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg)); - cp_intc_write(type, CP_INTC_SYS_TYPE(reg)); - - return 0; -} - -static struct irq_chip cp_intc_irq_chip = { - .name = "cp_intc", - .ack = cp_intc_ack_irq, - .mask = cp_intc_mask_irq, - .unmask = cp_intc_unmask_irq, - .set_type = cp_intc_set_irq_type, -}; - -void __init cp_intc_init(void __iomem *base, unsigned short num_irq, - u8 *irq_prio) -{ - unsigned num_reg = BITS_TO_LONGS(num_irq); - int i; - - cp_intc_base = base; - - cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); - - /* Disable all host interrupts */ - cp_intc_write(0, CP_INTC_HOST_ENABLE(0)); - - /* Disable system interrupts */ - for (i = 0; i < num_reg; i++) - cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i)); - - /* Set to normal mode, no nesting, no priority hold */ - cp_intc_write(0, CP_INTC_CTRL); - cp_intc_write(0, CP_INTC_HOST_CTRL); - - /* Clear system interrupt status */ - for (i = 0; i < num_reg; i++) - cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i)); - - /* Enable nIRQ (what about nFIQ?) */ - cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); - - /* - * Priority is determined by host channel: lower channel number has - * higher priority i.e. channel 0 has highest priority and channel 31 - * had the lowest priority. - */ - num_reg = (num_irq + 3) >> 2; /* 4 channels per register */ - if (irq_prio) { - unsigned j, k; - u32 val; - - for (k = i = 0; i < num_reg; i++) { - for (val = j = 0; j < 4; j++, k++) { - val >>= 8; - if (k < num_irq) - val |= irq_prio[k] << 24; - } - - cp_intc_write(val, CP_INTC_CHAN_MAP(i)); - } - } else { - /* - * Default everything to channel 15 if priority not specified. - * Note that channel 0-1 are mapped to nFIQ and channels 2-31 - * are mapped to nIRQ. - */ - for (i = 0; i < num_reg; i++) - cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i)); - } - - /* Set up genirq dispatching for cp_intc */ - for (i = 0; i < num_irq; i++) { - set_irq_chip(i, &cp_intc_irq_chip); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - set_irq_handler(i, handle_edge_irq); - } - - /* Enable global interrupt */ - cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); -} diff --git a/trunk/arch/arm/mach-davinci/devices.c b/trunk/arch/arm/mach-davinci/devices.c index de16f347566a..a31370b93dd2 100644 --- a/trunk/arch/arm/mach-davinci/devices.c +++ b/trunk/arch/arm/mach-davinci/devices.c @@ -23,14 +23,8 @@ #include #include #include -#include -#include -#include #define DAVINCI_I2C_BASE 0x01C21000 -#define DAVINCI_MMCSD0_BASE 0x01E10000 -#define DM355_MMCSD0_BASE 0x01E11000 -#define DM355_MMCSD1_BASE 0x01E00000 static struct resource i2c_resources[] = { { @@ -60,208 +54,3 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) (void) platform_device_register(&davinci_i2c_device); } -#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE) - -static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); - -static struct resource mmcsd0_resources[] = { - { - /* different on dm355 */ - .start = DAVINCI_MMCSD0_BASE, - .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - /* IRQs: MMC/SD, then SDIO */ - { - .start = IRQ_MMCINT, - .flags = IORESOURCE_IRQ, - }, { - /* different on dm355 */ - .start = IRQ_SDIOINT, - .flags = IORESOURCE_IRQ, - }, - /* DMA channels: RX, then TX */ - { - .start = DAVINCI_DMA_MMCRXEVT, - .flags = IORESOURCE_DMA, - }, { - .start = DAVINCI_DMA_MMCTXEVT, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device davinci_mmcsd0_device = { - .name = "davinci_mmc", - .id = 0, - .dev = { - .dma_mask = &mmcsd0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmcsd0_resources), - .resource = mmcsd0_resources, -}; - -static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32); - -static struct resource mmcsd1_resources[] = { - { - .start = DM355_MMCSD1_BASE, - .end = DM355_MMCSD1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - /* IRQs: MMC/SD, then SDIO */ - { - .start = IRQ_DM355_MMCINT1, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_DM355_SDIOINT1, - .flags = IORESOURCE_IRQ, - }, - /* DMA channels: RX, then TX */ - { - .start = 30, /* rx */ - .flags = IORESOURCE_DMA, - }, { - .start = 31, /* tx */ - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device davinci_mmcsd1_device = { - .name = "davinci_mmc", - .id = 1, - .dev = { - .dma_mask = &mmcsd1_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmcsd1_resources), - .resource = mmcsd1_resources, -}; - - -void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) -{ - struct platform_device *pdev = NULL; - - if (WARN_ON(cpu_is_davinci_dm646x())) - return; - - /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too; - * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused. - * - * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are - * not handled right here ... - */ - switch (module) { - case 1: - if (!cpu_is_davinci_dm355()) - break; - - /* REVISIT we may not need all these pins if e.g. this - * is a hard-wired SDIO device... - */ - davinci_cfg_reg(DM355_SD1_CMD); - davinci_cfg_reg(DM355_SD1_CLK); - davinci_cfg_reg(DM355_SD1_DATA0); - davinci_cfg_reg(DM355_SD1_DATA1); - davinci_cfg_reg(DM355_SD1_DATA2); - davinci_cfg_reg(DM355_SD1_DATA3); - - pdev = &davinci_mmcsd1_device; - break; - case 0: - if (cpu_is_davinci_dm355()) { - mmcsd0_resources[0].start = DM355_MMCSD0_BASE; - mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1; - mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0; - - /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */ - davinci_cfg_reg(DM355_MMCSD0); - - /* enable RX EDMA */ - davinci_cfg_reg(DM355_EVT26_MMC0_RX); - } - - else if (cpu_is_davinci_dm644x()) { - /* REVISIT: should this be in board-init code? */ - void __iomem *base = - IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); - - /* Power-on 3.3V IO cells */ - __raw_writel(0, base + DM64XX_VDD3P3V_PWDN); - /*Set up the pull regiter for MMC */ - davinci_cfg_reg(DM644X_MSTK); - } - - pdev = &davinci_mmcsd0_device; - break; - } - - if (WARN_ON(!pdev)) - return; - - pdev->dev.platform_data = config; - platform_device_register(pdev); -} - -#else - -void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) -{ -} - -#endif - -/*-------------------------------------------------------------------------*/ - -static struct resource wdt_resources[] = { - { - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device davinci_wdt_device = { - .name = "watchdog", - .id = -1, - .num_resources = ARRAY_SIZE(wdt_resources), - .resource = wdt_resources, -}; - -static void davinci_init_wdt(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - - wdt_resources[0].start = (resource_size_t)soc_info->wdt_base; - wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1; - - platform_device_register(&davinci_wdt_device); -} - -/*-------------------------------------------------------------------------*/ - -struct davinci_timer_instance davinci_timer_instance[2] = { - { - .base = IO_ADDRESS(DAVINCI_TIMER0_BASE), - .bottom_irq = IRQ_TINT0_TINT12, - .top_irq = IRQ_TINT0_TINT34, - }, - { - .base = IO_ADDRESS(DAVINCI_TIMER1_BASE), - .bottom_irq = IRQ_TINT1_TINT12, - .top_irq = IRQ_TINT1_TINT34, - }, -}; - -/*-------------------------------------------------------------------------*/ - -static int __init davinci_init_devices(void) -{ - /* please keep these calls, and their implementations above, - * in alphabetical order so they're easier to sort through. - */ - davinci_init_wdt(); - - return 0; -} -arch_initcall(davinci_init_devices); - diff --git a/trunk/arch/arm/mach-davinci/dm355.c b/trunk/arch/arm/mach-davinci/dm355.c deleted file mode 100644 index baaaf328de2e..000000000000 --- a/trunk/arch/arm/mach-davinci/dm355.c +++ /dev/null @@ -1,730 +0,0 @@ -/* - * TI DaVinci DM355 chip specific setup - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clock.h" -#include "mux.h" - -#define DM355_UART2_BASE (IO_PHYS + 0x206000) - -/* - * Device specific clocks - */ -#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */ - -static struct pll_data pll1_data = { - .num = 1, - .phys_base = DAVINCI_PLL1_BASE, - .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, -}; - -static struct pll_data pll2_data = { - .num = 2, - .phys_base = DAVINCI_PLL2_BASE, - .flags = PLL_HAS_PREDIV, -}; - -static struct clk ref_clk = { - .name = "ref_clk", - /* FIXME -- crystal rate is board-specific */ - .rate = DM355_REF_FREQ, -}; - -static struct clk pll1_clk = { - .name = "pll1", - .parent = &ref_clk, - .flags = CLK_PLL, - .pll_data = &pll1_data, -}; - -static struct clk pll1_aux_clk = { - .name = "pll1_aux_clk", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll1_sysclk1 = { - .name = "pll1_sysclk1", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll1_sysclk2 = { - .name = "pll1_sysclk2", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll1_sysclk3 = { - .name = "pll1_sysclk3", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, -}; - -static struct clk pll1_sysclk4 = { - .name = "pll1_sysclk4", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV4, -}; - -static struct clk pll1_sysclkbp = { - .name = "pll1_sysclkbp", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, - .div_reg = BPDIV -}; - -static struct clk vpss_dac_clk = { - .name = "vpss_dac", - .parent = &pll1_sysclk3, - .lpsc = DM355_LPSC_VPSS_DAC, -}; - -static struct clk vpss_master_clk = { - .name = "vpss_master", - .parent = &pll1_sysclk4, - .lpsc = DAVINCI_LPSC_VPSSMSTR, - .flags = CLK_PSC, -}; - -static struct clk vpss_slave_clk = { - .name = "vpss_slave", - .parent = &pll1_sysclk4, - .lpsc = DAVINCI_LPSC_VPSSSLV, -}; - - -static struct clk clkout1_clk = { - .name = "clkout1", - .parent = &pll1_aux_clk, - /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */ -}; - -static struct clk clkout2_clk = { - .name = "clkout2", - .parent = &pll1_sysclkbp, -}; - -static struct clk pll2_clk = { - .name = "pll2", - .parent = &ref_clk, - .flags = CLK_PLL, - .pll_data = &pll2_data, -}; - -static struct clk pll2_sysclk1 = { - .name = "pll2_sysclk1", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll2_sysclkbp = { - .name = "pll2_sysclkbp", - .parent = &pll2_clk, - .flags = CLK_PLL | PRE_PLL, - .div_reg = BPDIV -}; - -static struct clk clkout3_clk = { - .name = "clkout3", - .parent = &pll2_sysclkbp, - /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */ -}; - -static struct clk arm_clk = { - .name = "arm_clk", - .parent = &pll1_sysclk1, - .lpsc = DAVINCI_LPSC_ARM, - .flags = ALWAYS_ENABLED, -}; - -/* - * NOT LISTED below, and not touched by Linux - * - in SyncReset state by default - * .lpsc = DAVINCI_LPSC_TPCC, - * .lpsc = DAVINCI_LPSC_TPTC0, - * .lpsc = DAVINCI_LPSC_TPTC1, - * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk, - * .lpsc = DAVINCI_LPSC_MEMSTICK, - * - in Enabled state by default - * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS, - * .lpsc = DAVINCI_LPSC_SCR2, // "bus" - * .lpsc = DAVINCI_LPSC_SCR3, // "bus" - * .lpsc = DAVINCI_LPSC_SCR4, // "bus" - * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation" - * .lpsc = DAVINCI_LPSC_CFG27, // "test" - * .lpsc = DAVINCI_LPSC_CFG3, // "test" - * .lpsc = DAVINCI_LPSC_CFG5, // "test" - */ - -static struct clk mjcp_clk = { - .name = "mjcp", - .parent = &pll1_sysclk1, - .lpsc = DAVINCI_LPSC_IMCOP, -}; - -static struct clk uart0_clk = { - .name = "uart0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_UART0, -}; - -static struct clk uart1_clk = { - .name = "uart1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_UART1, -}; - -static struct clk uart2_clk = { - .name = "uart2", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_UART2, -}; - -static struct clk i2c_clk = { - .name = "i2c", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_I2C, -}; - -static struct clk asp0_clk = { - .name = "asp0", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_McBSP, -}; - -static struct clk asp1_clk = { - .name = "asp1", - .parent = &pll1_sysclk2, - .lpsc = DM355_LPSC_McBSP1, -}; - -static struct clk mmcsd0_clk = { - .name = "mmcsd0", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_MMC_SD, -}; - -static struct clk mmcsd1_clk = { - .name = "mmcsd1", - .parent = &pll1_sysclk2, - .lpsc = DM355_LPSC_MMC_SD1, -}; - -static struct clk spi0_clk = { - .name = "spi0", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_SPI, -}; - -static struct clk spi1_clk = { - .name = "spi1", - .parent = &pll1_sysclk2, - .lpsc = DM355_LPSC_SPI1, -}; - -static struct clk spi2_clk = { - .name = "spi2", - .parent = &pll1_sysclk2, - .lpsc = DM355_LPSC_SPI2, -}; - -static struct clk gpio_clk = { - .name = "gpio", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_GPIO, -}; - -static struct clk aemif_clk = { - .name = "aemif", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_AEMIF, -}; - -static struct clk pwm0_clk = { - .name = "pwm0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM0, -}; - -static struct clk pwm1_clk = { - .name = "pwm1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM1, -}; - -static struct clk pwm2_clk = { - .name = "pwm2", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM2, -}; - -static struct clk pwm3_clk = { - .name = "pwm3", - .parent = &pll1_aux_clk, - .lpsc = DM355_LPSC_PWM3, -}; - -static struct clk timer0_clk = { - .name = "timer0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER0, -}; - -static struct clk timer1_clk = { - .name = "timer1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER1, -}; - -static struct clk timer2_clk = { - .name = "timer2", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, /* REVISIT: why cant' this be disabled? */ -}; - -static struct clk timer3_clk = { - .name = "timer3", - .parent = &pll1_aux_clk, - .lpsc = DM355_LPSC_TIMER3, -}; - -static struct clk rto_clk = { - .name = "rto", - .parent = &pll1_aux_clk, - .lpsc = DM355_LPSC_RTO, -}; - -static struct clk usb_clk = { - .name = "usb", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_USB, -}; - -static struct davinci_clk dm355_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), - CLK(NULL, "vpss_dac", &vpss_dac_clk), - CLK(NULL, "vpss_master", &vpss_master_clk), - CLK(NULL, "vpss_slave", &vpss_slave_clk), - CLK(NULL, "clkout1", &clkout1_clk), - CLK(NULL, "clkout2", &clkout2_clk), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), - CLK(NULL, "clkout3", &clkout3_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "mjcp", &mjcp_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), - CLK(NULL, "uart2", &uart2_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("soc-audio.0", NULL, &asp0_clk), - CLK("soc-audio.1", NULL, &asp1_clk), - CLK("davinci_mmc.0", NULL, &mmcsd0_clk), - CLK("davinci_mmc.1", NULL, &mmcsd1_clk), - CLK(NULL, "spi0", &spi0_clk), - CLK(NULL, "spi1", &spi1_clk), - CLK(NULL, "spi2", &spi2_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "pwm2", &pwm2_clk), - CLK(NULL, "pwm3", &pwm3_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("watchdog", NULL, &timer2_clk), - CLK(NULL, "timer3", &timer3_clk), - CLK(NULL, "rto", &rto_clk), - CLK(NULL, "usb", &usb_clk), - CLK(NULL, NULL, NULL), -}; - -/*----------------------------------------------------------------------*/ - -static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32); - -static struct resource dm355_spi0_resources[] = { - { - .start = 0x01c66000, - .end = 0x01c667ff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_DM355_SPINT0_1, - .flags = IORESOURCE_IRQ, - }, - /* Not yet used, so not included: - * IORESOURCE_IRQ: - * - IRQ_DM355_SPINT0_0 - * IORESOURCE_DMA: - * - DAVINCI_DMA_SPI_SPIX - * - DAVINCI_DMA_SPI_SPIR - */ -}; - -static struct platform_device dm355_spi0_device = { - .name = "spi_davinci", - .id = 0, - .dev = { - .dma_mask = &dm355_spi0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(dm355_spi0_resources), - .resource = dm355_spi0_resources, -}; - -void __init dm355_init_spi0(unsigned chipselect_mask, - struct spi_board_info *info, unsigned len) -{ - /* for now, assume we need MISO */ - davinci_cfg_reg(DM355_SPI0_SDI); - - /* not all slaves will be wired up */ - if (chipselect_mask & BIT(0)) - davinci_cfg_reg(DM355_SPI0_SDENA0); - if (chipselect_mask & BIT(1)) - davinci_cfg_reg(DM355_SPI0_SDENA1); - - spi_register_board_info(info, len); - - platform_device_register(&dm355_spi0_device); -} - -/*----------------------------------------------------------------------*/ - -#define PINMUX0 0x00 -#define PINMUX1 0x04 -#define PINMUX2 0x08 -#define PINMUX3 0x0c -#define PINMUX4 0x10 -#define INTMUX 0x18 -#define EVTMUX 0x1c - -/* - * Device specific mux setup - * - * soc description mux mode mode mux dbg - * reg offset mask mode - */ -static const struct mux_config dm355_pins[] = { -#ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false) - -MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false) -MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false) -MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false) -MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false) -MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false) -MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false) - -MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false) -MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false) - -MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false) -MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false) -MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false) -MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false) -MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false) -MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false) - -MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false) -MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false) -MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false) - -INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false) -INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false) -INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false) - -EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) -EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) -EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) -#endif -}; - -static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM355_CCDC_VDINT0] = 2, - [IRQ_DM355_CCDC_VDINT1] = 6, - [IRQ_DM355_CCDC_VDINT2] = 6, - [IRQ_DM355_IPIPE_HST] = 6, - [IRQ_DM355_H3AINT] = 6, - [IRQ_DM355_IPIPE_SDR] = 6, - [IRQ_DM355_IPIPEIFINT] = 6, - [IRQ_DM355_OSDINT] = 7, - [IRQ_DM355_VENCINT] = 6, - [IRQ_ASQINT] = 6, - [IRQ_IMXINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_DM355_RTOINT] = 4, - [IRQ_DM355_UARTINT2] = 7, - [IRQ_DM355_TINT6] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_CCERRINT] = 5, /* dma */ - [IRQ_TCERRINT0] = 5, /* dma */ - [IRQ_TCERRINT] = 5, /* dma */ - [IRQ_DM355_SPINT2_1] = 7, - [IRQ_DM355_TINT7] = 4, - [IRQ_DM355_SDIOINT0] = 7, - [IRQ_MBXINT] = 7, - [IRQ_MBRINT] = 7, - [IRQ_MMCINT] = 7, - [IRQ_DM355_MMCINT1] = 7, - [IRQ_DM355_PWMINT3] = 7, - [IRQ_DDRINT] = 7, - [IRQ_AEMIFINT] = 7, - [IRQ_DM355_SDIOINT1] = 4, - [IRQ_TINT0_TINT12] = 2, /* clockevent */ - [IRQ_TINT0_TINT34] = 2, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_PWMINT2] = 7, - [IRQ_I2C] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_DM355_SPINT0_0] = 3, - [IRQ_DM355_SPINT0_1] = 3, - [IRQ_DM355_GPIO0] = 3, - [IRQ_DM355_GPIO1] = 7, - [IRQ_DM355_GPIO2] = 4, - [IRQ_DM355_GPIO3] = 4, - [IRQ_DM355_GPIO4] = 7, - [IRQ_DM355_GPIO5] = 7, - [IRQ_DM355_GPIO6] = 7, - [IRQ_DM355_GPIO7] = 7, - [IRQ_DM355_GPIO8] = 7, - [IRQ_DM355_GPIO9] = 7, - [IRQ_DM355_GPIOBNK0] = 7, - [IRQ_DM355_GPIOBNK1] = 7, - [IRQ_DM355_GPIOBNK2] = 7, - [IRQ_DM355_GPIOBNK3] = 7, - [IRQ_DM355_GPIOBNK4] = 7, - [IRQ_DM355_GPIOBNK5] = 7, - [IRQ_DM355_GPIOBNK6] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; - -/*----------------------------------------------------------------------*/ - -static const s8 dma_chan_dm355_no_event[] = { - 12, 13, 24, 56, 57, - 58, 59, 60, 61, 62, - 63, - -1 -}; - -static struct edma_soc_info dm355_edma_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .noevent = dma_chan_dm355_no_event, -}; - -static struct resource edma_resources[] = { - { - .name = "edma_cc", - .start = 0x01c00000, - .end = 0x01c00000 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc0", - .start = 0x01c10000, - .end = 0x01c10000 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc1", - .start = 0x01c10400, - .end = 0x01c10400 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CCINT0, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CCERRINT, - .flags = IORESOURCE_IRQ, - }, - /* not using (or muxing) TC*_ERR */ -}; - -static struct platform_device dm355_edma_device = { - .name = "edma", - .id = -1, - .dev.platform_data = &dm355_edma_info, - .num_resources = ARRAY_SIZE(edma_resources), - .resource = edma_resources, -}; - -/*----------------------------------------------------------------------*/ - -static struct map_desc dm355_io_desc[] = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, - { - .virtual = SRAM_VIRT, - .pfn = __phys_to_pfn(0x00010000), - .length = SZ_32K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, - }, -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id dm355_ids[] = { - { - .variant = 0x0, - .part_no = 0xb73b, - .manufacturer = 0x00f, - .cpu_id = DAVINCI_CPU_ID_DM355, - .name = "dm355", - }, -}; - -static void __iomem *dm355_psc_bases[] = { - IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), -}; - -/* - * T0_BOT: Timer 0, bottom: clockevent source for hrtimers - * T0_TOP: Timer 0, top : clocksource for generic timekeeping - * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) - * T1_TOP: Timer 1, top : - */ -struct davinci_timer_info dm355_timer_info = { - .timers = davinci_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, -}; - -static struct plat_serial8250_port dm355_serial_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = IRQ_UARTINT0, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .mapbase = DAVINCI_UART1_BASE, - .irq = IRQ_UARTINT1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .mapbase = DM355_UART2_BASE, - .irq = IRQ_DM355_UARTINT2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0 - }, -}; - -static struct platform_device dm355_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm355_serial_platform_data, - }, -}; - -static struct davinci_soc_info davinci_soc_info_dm355 = { - .io_desc = dm355_io_desc, - .io_desc_num = ARRAY_SIZE(dm355_io_desc), - .jtag_id_base = IO_ADDRESS(0x01c40028), - .ids = dm355_ids, - .ids_num = ARRAY_SIZE(dm355_ids), - .cpu_clks = dm355_clks, - .psc_bases = dm355_psc_bases, - .psc_bases_num = ARRAY_SIZE(dm355_psc_bases), - .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), - .pinmux_pins = dm355_pins, - .pinmux_pins_num = ARRAY_SIZE(dm355_pins), - .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), - .intc_type = DAVINCI_INTC_TYPE_AINTC, - .intc_irq_prios = dm355_default_priorities, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, - .timer_info = &dm355_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), - .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), - .gpio_num = 104, - .gpio_irq = IRQ_DM355_GPIOBNK0, - .serial_dev = &dm355_serial_device, - .sram_dma = 0x00010000, - .sram_len = SZ_32K, -}; - -void __init dm355_init(void) -{ - davinci_common_init(&davinci_soc_info_dm355); -} - -static int __init dm355_init_devices(void) -{ - if (!cpu_is_davinci_dm355()) - return 0; - - davinci_cfg_reg(DM355_INT_EDMA_CC); - platform_device_register(&dm355_edma_device); - return 0; -} -postcore_initcall(dm355_init_devices); diff --git a/trunk/arch/arm/mach-davinci/dm644x.c b/trunk/arch/arm/mach-davinci/dm644x.c index fb5449b3c97b..d428ef192eac 100644 --- a/trunk/arch/arm/mach-davinci/dm644x.c +++ b/trunk/arch/arm/mach-davinci/dm644x.c @@ -11,11 +11,7 @@ #include #include #include -#include #include -#include - -#include #include #include @@ -24,9 +20,6 @@ #include #include #include -#include -#include -#include #include "clock.h" #include "mux.h" @@ -319,14 +312,7 @@ struct davinci_clk dm644x_clks[] = { CLK(NULL, NULL, NULL), }; -static struct emac_platform_data dm644x_emac_pdata = { - .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, - .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, - .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, - .mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET, - .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, - .version = EMAC_VERSION_1, -}; +#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) static struct resource dm644x_emac_resources[] = { { @@ -344,15 +330,11 @@ static struct resource dm644x_emac_resources[] = { static struct platform_device dm644x_emac_device = { .name = "davinci_emac", .id = 1, - .dev = { - .platform_data = &dm644x_emac_pdata, - }, .num_resources = ARRAY_SIZE(dm644x_emac_resources), .resource = dm644x_emac_resources, }; -#define PINMUX0 0x00 -#define PINMUX1 0x04 +#endif /* * Device specific mux setup @@ -361,7 +343,6 @@ static struct platform_device dm644x_emac_device = { * reg offset mask mode */ static const struct mux_config dm644x_pins[] = { -#ifdef CONFIG_DAVINCI_MUX MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) @@ -402,76 +383,8 @@ MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) -#endif }; -/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ -static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_VDINT0] = 2, - [IRQ_VDINT1] = 6, - [IRQ_VDINT2] = 6, - [IRQ_HISTINT] = 6, - [IRQ_H3AINT] = 6, - [IRQ_PRVUINT] = 6, - [IRQ_RSZINT] = 6, - [7] = 7, - [IRQ_VENCINT] = 6, - [IRQ_ASQINT] = 6, - [IRQ_IMXINT] = 6, - [IRQ_VLCDINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_EMACINT] = 4, - [14] = 7, - [15] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_CCERRINT] = 5, /* dma */ - [IRQ_TCERRINT0] = 5, /* dma */ - [IRQ_TCERRINT] = 5, /* dma */ - [IRQ_PSCIN] = 7, - [21] = 7, - [IRQ_IDE] = 4, - [23] = 7, - [IRQ_MBXINT] = 7, - [IRQ_MBRINT] = 7, - [IRQ_MMCINT] = 7, - [IRQ_SDIOINT] = 7, - [28] = 7, - [IRQ_DDRINT] = 7, - [IRQ_AEMIFINT] = 7, - [IRQ_VLQINT] = 4, - [IRQ_TINT0_TINT12] = 2, /* clockevent */ - [IRQ_TINT0_TINT34] = 2, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_PWMINT2] = 7, - [IRQ_I2C] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_UARTINT2] = 3, - [IRQ_SPINT0] = 3, - [IRQ_SPINT1] = 3, - [45] = 7, - [IRQ_DSP2ARM0] = 4, - [IRQ_DSP2ARM1] = 4, - [IRQ_GPIO0] = 7, - [IRQ_GPIO1] = 7, - [IRQ_GPIO2] = 7, - [IRQ_GPIO3] = 7, - [IRQ_GPIO4] = 7, - [IRQ_GPIO5] = 7, - [IRQ_GPIO6] = 7, - [IRQ_GPIO7] = 7, - [IRQ_GPIOBNK0] = 7, - [IRQ_GPIOBNK1] = 7, - [IRQ_GPIOBNK2] = 7, - [IRQ_GPIOBNK3] = 7, - [IRQ_GPIOBNK4] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; /*----------------------------------------------------------------------*/ @@ -531,118 +444,10 @@ static struct platform_device dm644x_edma_device = { }; /*----------------------------------------------------------------------*/ - -static struct map_desc dm644x_io_desc[] = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, - { - .virtual = SRAM_VIRT, - .pfn = __phys_to_pfn(0x00008000), - .length = SZ_16K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, - }, -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id dm644x_ids[] = { - { - .variant = 0x0, - .part_no = 0xb700, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM6446, - .name = "dm6446", - }, -}; - -static void __iomem *dm644x_psc_bases[] = { - IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), -}; - -/* - * T0_BOT: Timer 0, bottom: clockevent source for hrtimers - * T0_TOP: Timer 0, top : clocksource for generic timekeeping - * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) - * T1_TOP: Timer 1, top : - */ -struct davinci_timer_info dm644x_timer_info = { - .timers = davinci_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, -}; - -static struct plat_serial8250_port dm644x_serial_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = IRQ_UARTINT0, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .mapbase = DAVINCI_UART1_BASE, - .irq = IRQ_UARTINT1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .mapbase = DAVINCI_UART2_BASE, - .irq = IRQ_UARTINT2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0 - }, -}; - -static struct platform_device dm644x_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm644x_serial_platform_data, - }, -}; - -static struct davinci_soc_info davinci_soc_info_dm644x = { - .io_desc = dm644x_io_desc, - .io_desc_num = ARRAY_SIZE(dm644x_io_desc), - .jtag_id_base = IO_ADDRESS(0x01c40028), - .ids = dm644x_ids, - .ids_num = ARRAY_SIZE(dm644x_ids), - .cpu_clks = dm644x_clks, - .psc_bases = dm644x_psc_bases, - .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), - .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), - .pinmux_pins = dm644x_pins, - .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), - .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), - .intc_type = DAVINCI_INTC_TYPE_AINTC, - .intc_irq_prios = dm644x_default_priorities, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, - .timer_info = &dm644x_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), - .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), - .gpio_num = 71, - .gpio_irq = IRQ_GPIOBNK0, - .serial_dev = &dm644x_serial_device, - .emac_pdata = &dm644x_emac_pdata, - .sram_dma = 0x00008000, - .sram_len = SZ_16K, -}; - void __init dm644x_init(void) { - davinci_common_init(&davinci_soc_info_dm644x); + davinci_clk_init(dm644x_clks); + davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins)); } static int __init dm644x_init_devices(void) @@ -651,7 +456,6 @@ static int __init dm644x_init_devices(void) return 0; platform_device_register(&dm644x_edma_device); - platform_device_register(&dm644x_emac_device); return 0; } postcore_initcall(dm644x_init_devices); diff --git a/trunk/arch/arm/mach-davinci/dm646x.c b/trunk/arch/arm/mach-davinci/dm646x.c deleted file mode 100644 index 334f0711e0f5..000000000000 --- a/trunk/arch/arm/mach-davinci/dm646x.c +++ /dev/null @@ -1,636 +0,0 @@ -/* - * TI DaVinci DM644x chip specific setup - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clock.h" -#include "mux.h" - -/* - * Device specific clocks - */ -#define DM646X_REF_FREQ 27000000 -#define DM646X_AUX_FREQ 24000000 - -static struct pll_data pll1_data = { - .num = 1, - .phys_base = DAVINCI_PLL1_BASE, -}; - -static struct pll_data pll2_data = { - .num = 2, - .phys_base = DAVINCI_PLL2_BASE, -}; - -static struct clk ref_clk = { - .name = "ref_clk", - .rate = DM646X_REF_FREQ, -}; - -static struct clk aux_clkin = { - .name = "aux_clkin", - .rate = DM646X_AUX_FREQ, -}; - -static struct clk pll1_clk = { - .name = "pll1", - .parent = &ref_clk, - .pll_data = &pll1_data, - .flags = CLK_PLL, -}; - -static struct clk pll1_sysclk1 = { - .name = "pll1_sysclk1", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll1_sysclk2 = { - .name = "pll1_sysclk2", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll1_sysclk3 = { - .name = "pll1_sysclk3", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, -}; - -static struct clk pll1_sysclk4 = { - .name = "pll1_sysclk4", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV4, -}; - -static struct clk pll1_sysclk5 = { - .name = "pll1_sysclk5", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV5, -}; - -static struct clk pll1_sysclk6 = { - .name = "pll1_sysclk6", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV6, -}; - -static struct clk pll1_sysclk8 = { - .name = "pll1_sysclk8", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV8, -}; - -static struct clk pll1_sysclk9 = { - .name = "pll1_sysclk9", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV9, -}; - -static struct clk pll1_sysclkbp = { - .name = "pll1_sysclkbp", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, - .div_reg = BPDIV, -}; - -static struct clk pll1_aux_clk = { - .name = "pll1_aux_clk", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll2_clk = { - .name = "pll2_clk", - .parent = &ref_clk, - .pll_data = &pll2_data, - .flags = CLK_PLL, -}; - -static struct clk pll2_sysclk1 = { - .name = "pll2_sysclk1", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk dsp_clk = { - .name = "dsp", - .parent = &pll1_sysclk1, - .lpsc = DM646X_LPSC_C64X_CPU, - .flags = PSC_DSP, - .usecount = 1, /* REVISIT how to disable? */ -}; - -static struct clk arm_clk = { - .name = "arm", - .parent = &pll1_sysclk2, - .lpsc = DM646X_LPSC_ARM, - .flags = ALWAYS_ENABLED, -}; - -static struct clk uart0_clk = { - .name = "uart0", - .parent = &aux_clkin, - .lpsc = DM646X_LPSC_UART0, -}; - -static struct clk uart1_clk = { - .name = "uart1", - .parent = &aux_clkin, - .lpsc = DM646X_LPSC_UART1, -}; - -static struct clk uart2_clk = { - .name = "uart2", - .parent = &aux_clkin, - .lpsc = DM646X_LPSC_UART2, -}; - -static struct clk i2c_clk = { - .name = "I2CCLK", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_I2C, -}; - -static struct clk gpio_clk = { - .name = "gpio", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_GPIO, -}; - -static struct clk aemif_clk = { - .name = "aemif", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_AEMIF, - .flags = ALWAYS_ENABLED, -}; - -static struct clk emac_clk = { - .name = "emac", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_EMAC, -}; - -static struct clk pwm0_clk = { - .name = "pwm0", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_PWM0, - .usecount = 1, /* REVIST: disabling hangs system */ -}; - -static struct clk pwm1_clk = { - .name = "pwm1", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_PWM1, - .usecount = 1, /* REVIST: disabling hangs system */ -}; - -static struct clk timer0_clk = { - .name = "timer0", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_TIMER0, -}; - -static struct clk timer1_clk = { - .name = "timer1", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_TIMER1, -}; - -static struct clk timer2_clk = { - .name = "timer2", - .parent = &pll1_sysclk3, - .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ -}; - -static struct clk vpif0_clk = { - .name = "vpif0", - .parent = &ref_clk, - .lpsc = DM646X_LPSC_VPSSMSTR, - .flags = ALWAYS_ENABLED, -}; - -static struct clk vpif1_clk = { - .name = "vpif1", - .parent = &ref_clk, - .lpsc = DM646X_LPSC_VPSSSLV, - .flags = ALWAYS_ENABLED, -}; - -struct davinci_clk dm646x_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "aux", &aux_clkin), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_sysclk", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk", &pll1_sysclk4), - CLK(NULL, "pll1_sysclk", &pll1_sysclk5), - CLK(NULL, "pll1_sysclk", &pll1_sysclk6), - CLK(NULL, "pll1_sysclk", &pll1_sysclk8), - CLK(NULL, "pll1_sysclk", &pll1_sysclk9), - CLK(NULL, "pll1_sysclk", &pll1_sysclkbp), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "dsp", &dsp_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), - CLK(NULL, "uart2", &uart2_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("watchdog", NULL, &timer2_clk), - CLK(NULL, "vpif0", &vpif0_clk), - CLK(NULL, "vpif1", &vpif1_clk), - CLK(NULL, NULL, NULL), -}; - -static struct emac_platform_data dm646x_emac_pdata = { - .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, - .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, - .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, - .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET, - .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, - .version = EMAC_VERSION_2, -}; - -static struct resource dm646x_emac_resources[] = { - { - .start = DM646X_EMAC_BASE, - .end = DM646X_EMAC_BASE + 0x47ff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_DM646X_EMACRXTHINT, - .end = IRQ_DM646X_EMACRXTHINT, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_DM646X_EMACRXINT, - .end = IRQ_DM646X_EMACRXINT, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_DM646X_EMACTXINT, - .end = IRQ_DM646X_EMACTXINT, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_DM646X_EMACMISCINT, - .end = IRQ_DM646X_EMACMISCINT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm646x_emac_device = { - .name = "davinci_emac", - .id = 1, - .dev = { - .platform_data = &dm646x_emac_pdata, - }, - .num_resources = ARRAY_SIZE(dm646x_emac_resources), - .resource = dm646x_emac_resources, -}; - -#define PINMUX0 0x00 -#define PINMUX1 0x04 - -/* - * Device specific mux setup - * - * soc description mux mode mode mux dbg - * reg offset mask mode - */ -static const struct mux_config dm646x_pins[] = { -#ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true) - -MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) - -MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) - -MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true) - -MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true) - -MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true) - -MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true) - -MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true) - -MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true) - -MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true) - -MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true) - -MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true) - -MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) - -MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) -#endif -}; - -static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM646X_VP_VERTINT0] = 7, - [IRQ_DM646X_VP_VERTINT1] = 7, - [IRQ_DM646X_VP_VERTINT2] = 7, - [IRQ_DM646X_VP_VERTINT3] = 7, - [IRQ_DM646X_VP_ERRINT] = 7, - [IRQ_DM646X_RESERVED_1] = 7, - [IRQ_DM646X_RESERVED_2] = 7, - [IRQ_DM646X_WDINT] = 7, - [IRQ_DM646X_CRGENINT0] = 7, - [IRQ_DM646X_CRGENINT1] = 7, - [IRQ_DM646X_TSIFINT0] = 7, - [IRQ_DM646X_TSIFINT1] = 7, - [IRQ_DM646X_VDCEINT] = 7, - [IRQ_DM646X_USBINT] = 7, - [IRQ_DM646X_USBDMAINT] = 7, - [IRQ_DM646X_PCIINT] = 7, - [IRQ_CCINT0] = 7, /* dma */ - [IRQ_CCERRINT] = 7, /* dma */ - [IRQ_TCERRINT0] = 7, /* dma */ - [IRQ_TCERRINT] = 7, /* dma */ - [IRQ_DM646X_TCERRINT2] = 7, - [IRQ_DM646X_TCERRINT3] = 7, - [IRQ_DM646X_IDE] = 7, - [IRQ_DM646X_HPIINT] = 7, - [IRQ_DM646X_EMACRXTHINT] = 7, - [IRQ_DM646X_EMACRXINT] = 7, - [IRQ_DM646X_EMACTXINT] = 7, - [IRQ_DM646X_EMACMISCINT] = 7, - [IRQ_DM646X_MCASP0TXINT] = 7, - [IRQ_DM646X_MCASP0RXINT] = 7, - [IRQ_AEMIFINT] = 7, - [IRQ_DM646X_RESERVED_3] = 7, - [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ - [IRQ_TINT0_TINT34] = 7, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_DM646X_VLQINT] = 7, - [IRQ_I2C] = 7, - [IRQ_UARTINT0] = 7, - [IRQ_UARTINT1] = 7, - [IRQ_DM646X_UARTINT2] = 7, - [IRQ_DM646X_SPINT0] = 7, - [IRQ_DM646X_SPINT1] = 7, - [IRQ_DM646X_DSP2ARMINT] = 7, - [IRQ_DM646X_RESERVED_4] = 7, - [IRQ_DM646X_PSCINT] = 7, - [IRQ_DM646X_GPIO0] = 7, - [IRQ_DM646X_GPIO1] = 7, - [IRQ_DM646X_GPIO2] = 7, - [IRQ_DM646X_GPIO3] = 7, - [IRQ_DM646X_GPIO4] = 7, - [IRQ_DM646X_GPIO5] = 7, - [IRQ_DM646X_GPIO6] = 7, - [IRQ_DM646X_GPIO7] = 7, - [IRQ_DM646X_GPIOBNK0] = 7, - [IRQ_DM646X_GPIOBNK1] = 7, - [IRQ_DM646X_GPIOBNK2] = 7, - [IRQ_DM646X_DDRINT] = 7, - [IRQ_DM646X_AEMIFINT] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; - -/*----------------------------------------------------------------------*/ - -static const s8 dma_chan_dm646x_no_event[] = { - 0, 1, 2, 3, 13, - 14, 15, 24, 25, 26, - 27, 30, 31, 54, 55, - 56, - -1 -}; - -static struct edma_soc_info dm646x_edma_info = { - .n_channel = 64, - .n_region = 6, /* 0-1, 4-7 */ - .n_slot = 512, - .n_tc = 4, - .noevent = dma_chan_dm646x_no_event, -}; - -static struct resource edma_resources[] = { - { - .name = "edma_cc", - .start = 0x01c00000, - .end = 0x01c00000 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc0", - .start = 0x01c10000, - .end = 0x01c10000 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc1", - .start = 0x01c10400, - .end = 0x01c10400 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc2", - .start = 0x01c10800, - .end = 0x01c10800 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc3", - .start = 0x01c10c00, - .end = 0x01c10c00 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CCINT0, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CCERRINT, - .flags = IORESOURCE_IRQ, - }, - /* not using TC*_ERR */ -}; - -static struct platform_device dm646x_edma_device = { - .name = "edma", - .id = -1, - .dev.platform_data = &dm646x_edma_info, - .num_resources = ARRAY_SIZE(edma_resources), - .resource = edma_resources, -}; - -/*----------------------------------------------------------------------*/ - -static struct map_desc dm646x_io_desc[] = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, - { - .virtual = SRAM_VIRT, - .pfn = __phys_to_pfn(0x00010000), - .length = SZ_32K, - /* MT_MEMORY_NONCACHED requires supersection alignment */ - .type = MT_DEVICE, - }, -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id dm646x_ids[] = { - { - .variant = 0x0, - .part_no = 0xb770, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM6467, - .name = "dm6467", - }, -}; - -static void __iomem *dm646x_psc_bases[] = { - IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), -}; - -/* - * T0_BOT: Timer 0, bottom: clockevent source for hrtimers - * T0_TOP: Timer 0, top : clocksource for generic timekeeping - * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) - * T1_TOP: Timer 1, top : - */ -struct davinci_timer_info dm646x_timer_info = { - .timers = davinci_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, -}; - -static struct plat_serial8250_port dm646x_serial_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = IRQ_UARTINT0, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .mapbase = DAVINCI_UART1_BASE, - .irq = IRQ_UARTINT1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .mapbase = DAVINCI_UART2_BASE, - .irq = IRQ_DM646X_UARTINT2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0 - }, -}; - -static struct platform_device dm646x_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm646x_serial_platform_data, - }, -}; - -static struct davinci_soc_info davinci_soc_info_dm646x = { - .io_desc = dm646x_io_desc, - .io_desc_num = ARRAY_SIZE(dm646x_io_desc), - .jtag_id_base = IO_ADDRESS(0x01c40028), - .ids = dm646x_ids, - .ids_num = ARRAY_SIZE(dm646x_ids), - .cpu_clks = dm646x_clks, - .psc_bases = dm646x_psc_bases, - .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), - .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), - .pinmux_pins = dm646x_pins, - .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), - .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), - .intc_type = DAVINCI_INTC_TYPE_AINTC, - .intc_irq_prios = dm646x_default_priorities, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, - .timer_info = &dm646x_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), - .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), - .gpio_num = 43, /* Only 33 usable */ - .gpio_irq = IRQ_DM646X_GPIOBNK0, - .serial_dev = &dm646x_serial_device, - .emac_pdata = &dm646x_emac_pdata, - .sram_dma = 0x10010000, - .sram_len = SZ_32K, -}; - -void __init dm646x_init(void) -{ - davinci_common_init(&davinci_soc_info_dm646x); -} - -static int __init dm646x_init_devices(void) -{ - if (!cpu_is_davinci_dm646x()) - return 0; - - platform_device_register(&dm646x_edma_device); - platform_device_register(&dm646x_emac_device); - return 0; -} -postcore_initcall(dm646x_init_devices); diff --git a/trunk/arch/arm/mach-davinci/gpio.c b/trunk/arch/arm/mach-davinci/gpio.c index 1b6532159c58..1aba41c6351e 100644 --- a/trunk/arch/arm/mach-davinci/gpio.c +++ b/trunk/arch/arm/mach-davinci/gpio.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -38,13 +37,14 @@ struct davinci_gpio { static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; +static unsigned __initdata ngpio; + /* create a non-inlined version */ static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) { return __gpio_to_controller(gpio); } -static int __init davinci_gpio_irq_setup(void); /*--------------------------------------------------------------------------*/ @@ -115,16 +115,23 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static int __init davinci_gpio_setup(void) { int i, base; - unsigned ngpio; - struct davinci_soc_info *soc_info = &davinci_soc_info; - /* - * The gpio banks conceptually expose a segmented bitmap, + /* The gpio banks conceptually expose a segmented bitmap, * and "ngpio" is one more than the largest zero-based * bit index that's valid. */ - ngpio = soc_info->gpio_num; - if (ngpio == 0) { + if (cpu_is_davinci_dm355()) { /* or dm335() */ + ngpio = 104; + } else if (cpu_is_davinci_dm644x()) { /* or dm337() */ + ngpio = 71; + } else if (cpu_is_davinci_dm646x()) { + /* NOTE: each bank has several "reserved" bits, + * unusable as GPIOs. Only 33 of the GPIO numbers + * are usable, and we're not rejecting the others. + */ + ngpio = 43; + } else { + /* if cpu_is_davinci_dm643x() ngpio = 111 */ pr_err("GPIO setup: how many GPIOs?\n"); return -EINVAL; } @@ -150,7 +157,6 @@ static int __init davinci_gpio_setup(void) gpiochip_add(&chips[i].chip); } - davinci_gpio_irq_setup(); return 0; } pure_initcall(davinci_gpio_setup); @@ -181,15 +187,10 @@ static void gpio_irq_enable(unsigned irq) { struct gpio_controller *__iomem g = get_irq_chip_data(irq); u32 mask = __gpio_mask(irq_to_gpio(irq)); - unsigned status = irq_desc[irq].status; - - status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; - if (!status) - status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; - if (status & IRQ_TYPE_EDGE_FALLING) + if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING) __raw_writel(mask, &g->set_falling); - if (status & IRQ_TYPE_EDGE_RISING) + if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING) __raw_writel(mask, &g->set_rising); } @@ -204,13 +205,10 @@ static int gpio_irq_type(unsigned irq, unsigned trigger) irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; irq_desc[irq].status |= trigger; - /* don't enable the IRQ if it's currently disabled */ - if (irq_desc[irq].depth == 0) { - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) - ? &g->set_falling : &g->clr_falling); - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) - ? &g->set_rising : &g->clr_rising); - } + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) + ? &g->set_falling : &g->clr_falling); + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) + ? &g->set_rising : &g->clr_rising); return 0; } @@ -232,7 +230,6 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) mask <<= 16; /* temporarily mask (level sensitive) parent IRQ */ - desc->chip->mask(irq); desc->chip->ack(irq); while (1) { u32 status; @@ -271,15 +268,17 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) static int __init davinci_gpio_irq_setup(void) { unsigned gpio, irq, bank; + unsigned bank_irq; struct clk *clk; u32 binten = 0; - unsigned ngpio, bank_irq; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - ngpio = soc_info->gpio_num; - bank_irq = soc_info->gpio_irq; - if (bank_irq == 0) { + if (cpu_is_davinci_dm355()) { /* or dm335() */ + bank_irq = IRQ_DM355_GPIOBNK0; + } else if (cpu_is_davinci_dm644x()) { + bank_irq = IRQ_GPIOBNK0; + } else if (cpu_is_davinci_dm646x()) { + bank_irq = IRQ_DM646X_GPIOBNK0; + } else { printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); return -EINVAL; } @@ -319,9 +318,11 @@ static int __init davinci_gpio_irq_setup(void) /* BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ - __raw_writel(binten, soc_info->gpio_base + 0x08); + __raw_writel(binten, (void *__iomem) + IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); return 0; } +arch_initcall(davinci_gpio_irq_setup); diff --git a/trunk/arch/arm/mach-davinci/id.c b/trunk/arch/arm/mach-davinci/id.c new file mode 100644 index 000000000000..018b994cd794 --- /dev/null +++ b/trunk/arch/arm/mach-davinci/id.c @@ -0,0 +1,116 @@ +/* + * Davinci CPU identification code + * + * Copyright (C) 2006 Komal Shah + * + * Derived from OMAP1 CPU identification code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#define JTAG_ID_BASE IO_ADDRESS(0x01c40028) + +static unsigned int davinci_revision; + +struct davinci_id { + u8 variant; /* JTAG ID bits 31:28 */ + u16 part_no; /* JTAG ID bits 27:12 */ + u32 manufacturer; /* JTAG ID bits 11:1 */ + u32 type; /* Cpu id bits [31:8], cpu class bits [7:0] */ +}; + +/* Register values to detect the DaVinci version */ +static struct davinci_id davinci_ids[] __initdata = { + { + /* DM6446 */ + .part_no = 0xb700, + .variant = 0x0, + .manufacturer = 0x017, + .type = 0x64460000, + }, + { + /* DM646X */ + .part_no = 0xb770, + .variant = 0x0, + .manufacturer = 0x017, + .type = 0x64670000, + }, + { + /* DM355 */ + .part_no = 0xb73b, + .variant = 0x0, + .manufacturer = 0x00f, + .type = 0x03550000, + }, +}; + +/* + * Get Device Part No. from JTAG ID register + */ +static u16 __init davinci_get_part_no(void) +{ + u32 dev_id, part_no; + + dev_id = __raw_readl(JTAG_ID_BASE); + + part_no = ((dev_id >> 12) & 0xffff); + + return part_no; +} + +/* + * Get Device Revision from JTAG ID register + */ +static u8 __init davinci_get_variant(void) +{ + u32 variant; + + variant = __raw_readl(JTAG_ID_BASE); + + variant = (variant >> 28) & 0xf; + + return variant; +} + +unsigned int davinci_rev(void) +{ + return davinci_revision >> 16; +} +EXPORT_SYMBOL(davinci_rev); + +void __init davinci_check_revision(void) +{ + int i; + u16 part_no; + u8 variant; + + part_no = davinci_get_part_no(); + variant = davinci_get_variant(); + + /* First check only the major version in a safe way */ + for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { + if (part_no == (davinci_ids[i].part_no)) { + davinci_revision = davinci_ids[i].type; + break; + } + } + + /* Check if we can find the dev revision */ + for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { + if (part_no == davinci_ids[i].part_no && + variant == davinci_ids[i].variant) { + davinci_revision = davinci_ids[i].type; + break; + } + } + + printk(KERN_INFO "DaVinci DM%04x variant 0x%x\n", + davinci_rev(), variant); +} diff --git a/trunk/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/trunk/arch/arm/mach-davinci/include/mach/board-dm6446evm.h new file mode 100644 index 000000000000..3216f21c1238 --- /dev/null +++ b/trunk/arch/arm/mach-davinci/include/mach/board-dm6446evm.h @@ -0,0 +1,20 @@ +/* + * DaVinci DM6446 EVM board specific headers + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or ifndef. + */ + +#ifndef _MACH_DAVINCI_DM6446EVM_H +#define _MACH_DAVINCI_DM6446EVM_H + +#include + +int dm6446evm_eeprom_read(char *buf, off_t off, size_t count); +int dm6446evm_eeprom_write(char *buf, off_t off, size_t count); + +#endif diff --git a/trunk/arch/arm/mach-davinci/include/mach/common.h b/trunk/arch/arm/mach-davinci/include/mach/common.h index a1f03b606d8f..191770976250 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/common.h +++ b/trunk/arch/arm/mach-davinci/include/mach/common.h @@ -17,8 +17,7 @@ struct sys_timer; extern struct sys_timer davinci_timer; extern void davinci_irq_init(void); -extern void __iomem *davinci_intc_base; -extern int davinci_intc_type; +extern void davinci_map_common_io(void); /* parameters describe VBUS sourcing for host mode */ extern void setup_usb(unsigned mA, unsigned potpgt_msec); @@ -26,56 +25,4 @@ extern void setup_usb(unsigned mA, unsigned potpgt_msec); /* parameters describe VBUS sourcing for host mode */ extern void setup_usb(unsigned mA, unsigned potpgt_msec); -struct davinci_timer_instance { - void __iomem *base; - u32 bottom_irq; - u32 top_irq; - unsigned long cmp_off; - unsigned int cmp_irq; -}; - -struct davinci_timer_info { - struct davinci_timer_instance *timers; - unsigned int clockevent_id; - unsigned int clocksource_id; -}; - -/* SoC specific init support */ -struct davinci_soc_info { - struct map_desc *io_desc; - unsigned long io_desc_num; - u32 cpu_id; - u32 jtag_id; - void __iomem *jtag_id_base; - struct davinci_id *ids; - unsigned long ids_num; - struct davinci_clk *cpu_clks; - void __iomem **psc_bases; - unsigned long psc_bases_num; - void __iomem *pinmux_base; - const struct mux_config *pinmux_pins; - unsigned long pinmux_pins_num; - void __iomem *intc_base; - int intc_type; - u8 *intc_irq_prios; - unsigned long intc_irq_num; - struct davinci_timer_info *timer_info; - void __iomem *wdt_base; - void __iomem *gpio_base; - unsigned gpio_num; - unsigned gpio_irq; - struct platform_device *serial_dev; - struct emac_platform_data *emac_pdata; - dma_addr_t sram_dma; - unsigned sram_len; -}; - -extern struct davinci_soc_info davinci_soc_info; - -extern void davinci_common_init(struct davinci_soc_info *soc_info); - -/* standard place to map on-chip SRAMs; they *may* support DMA */ -#define SRAM_VIRT 0xfffe0000 -#define SRAM_SIZE SZ_128K - #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/cp_intc.h b/trunk/arch/arm/mach-davinci/include/mach/cp_intc.h deleted file mode 100644 index c4d27eec8064..000000000000 --- a/trunk/arch/arm/mach-davinci/include/mach/cp_intc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * TI Common Platform Interrupt Controller (cp_intc) definitions - * - * Author: Steve Chen - * Copyright (C) 2008-2009, MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ -#ifndef __ASM_HARDWARE_CP_INTC_H -#define __ASM_HARDWARE_CP_INTC_H - -#define CP_INTC_REV 0x00 -#define CP_INTC_CTRL 0x04 -#define CP_INTC_HOST_CTRL 0x0C -#define CP_INTC_GLOBAL_ENABLE 0x10 -#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C -#define CP_INTC_SYS_STAT_IDX_SET 0x20 -#define CP_INTC_SYS_STAT_IDX_CLR 0x24 -#define CP_INTC_SYS_ENABLE_IDX_SET 0x28 -#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C -#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30 -#define CP_INTC_HOST_ENABLE_IDX_SET 0x34 -#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38 -#define CP_INTC_PACING_PRESCALE 0x40 -#define CP_INTC_VECTOR_BASE 0x50 -#define CP_INTC_VECTOR_SIZE 0x54 -#define CP_INTC_VECTOR_NULL 0x58 -#define CP_INTC_PRIO_IDX 0x80 -#define CP_INTC_PRIO_VECTOR 0x84 -#define CP_INTC_SECURE_ENABLE 0x90 -#define CP_INTC_SECURE_PRIO_IDX 0x94 -#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4)) -#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4)) -#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4)) -#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2)) -#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2)) -#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2)) -#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2)) -#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2)) -#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2)) -#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2)) -#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2)) -#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2)) -#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2)) -#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2)) -#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2)) -#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2)) -#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2)) -#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2)) -#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) - -void __init cp_intc_init(void __iomem *base, unsigned short num_irq, - u8 *irq_prio); - -#endif /* __ASM_HARDWARE_CP_INTC_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/cputype.h b/trunk/arch/arm/mach-davinci/include/mach/cputype.h index d12a5ed2959a..27cfb1b3a662 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/cputype.h +++ b/trunk/arch/arm/mach-davinci/include/mach/cputype.h @@ -16,30 +16,17 @@ #ifndef _ASM_ARCH_CPU_H #define _ASM_ARCH_CPU_H -#include +extern unsigned int davinci_rev(void); -struct davinci_id { - u8 variant; /* JTAG ID bits 31:28 */ - u16 part_no; /* JTAG ID bits 27:12 */ - u16 manufacturer; /* JTAG ID bits 11:1 */ - u32 cpu_id; - char *name; -}; - -/* Can use lower 16 bits of cpu id for a variant when required */ -#define DAVINCI_CPU_ID_DM6446 0x64460000 -#define DAVINCI_CPU_ID_DM6467 0x64670000 -#define DAVINCI_CPU_ID_DM355 0x03550000 - -#define IS_DAVINCI_CPU(type, id) \ -static inline int is_davinci_ ##type(void) \ -{ \ - return (davinci_soc_info.cpu_id == (id)); \ +#define IS_DAVINCI_CPU(type, id) \ +static inline int is_davinci_dm ##type(void) \ +{ \ + return (davinci_rev() == (id)) ? 1 : 0; \ } -IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) -IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) -IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) +IS_DAVINCI_CPU(644x, 0x6446) +IS_DAVINCI_CPU(646x, 0x6467) +IS_DAVINCI_CPU(355, 0x355) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() diff --git a/trunk/arch/arm/mach-davinci/include/mach/debug-macro.S b/trunk/arch/arm/mach-davinci/include/mach/debug-macro.S index de3fc2182b47..e6c0f0d5d062 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/trunk/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -9,16 +9,6 @@ * or implied. */ -/* Modifications - * Jan 2009 Chaithrika U S Added senduart, busyuart, waituart - * macros, based on debug-8250.S file - * but using 32-bit accesses required for - * some davinci devices. - */ - -#include -#define UART_SHIFT 2 - .macro addruart, rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? @@ -27,22 +17,5 @@ orr \rx, \rx, #0x00c20000 @ UART 0 .endm - .macro senduart,rd,rx - str \rd, [\rx, #UART_TX << UART_SHIFT] - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE - bne 1002b - .endm - - .macro waituart,rd,rx -#ifdef FLOW_CONTROL -1001: ldr \rd, [\rx, #UART_MSR << UART_SHIFT] - tst \rd, #UART_MSR_CTS - beq 1001b -#endif - .endm - +#define UART_SHIFT 2 +#include diff --git a/trunk/arch/arm/mach-davinci/include/mach/dm355.h b/trunk/arch/arm/mach-davinci/include/mach/dm355.h deleted file mode 100644 index 54903b72438e..000000000000 --- a/trunk/arch/arm/mach-davinci/include/mach/dm355.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Chip specific defines for DM355 SoC - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_ARCH_DM355_H -#define __ASM_ARCH_DM355_H - -#include - -struct spi_board_info; - -void __init dm355_init(void); -void dm355_init_spi0(unsigned chipselect_mask, - struct spi_board_info *info, unsigned len); - -#endif /* __ASM_ARCH_DM355_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/dm644x.h b/trunk/arch/arm/mach-davinci/include/mach/dm644x.h index 15d42b92a8c9..3dcb9f4e58b4 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/trunk/arch/arm/mach-davinci/include/mach/dm644x.h @@ -24,7 +24,6 @@ #include #include -#include #define DM644X_EMAC_BASE (0x01C80000) #define DM644X_EMAC_CNTRL_OFFSET (0x0000) diff --git a/trunk/arch/arm/mach-davinci/include/mach/dm646x.h b/trunk/arch/arm/mach-davinci/include/mach/dm646x.h deleted file mode 100644 index 1fc764c8646e..000000000000 --- a/trunk/arch/arm/mach-davinci/include/mach/dm646x.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Chip specific defines for DM646x SoC - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_ARCH_DM646X_H -#define __ASM_ARCH_DM646X_H - -#include -#include - -#define DM646X_EMAC_BASE (0x01C80000) -#define DM646X_EMAC_CNTRL_OFFSET (0x0000) -#define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000) -#define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000) -#define DM646X_EMAC_MDIO_OFFSET (0x4000) -#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) - -void __init dm646x_init(void); - -#endif /* __ASM_ARCH_DM646X_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/edma.h b/trunk/arch/arm/mach-davinci/include/mach/edma.h index 24a379239d7f..f6fc5396dafc 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/edma.h +++ b/trunk/arch/arm/mach-davinci/include/mach/edma.h @@ -208,6 +208,10 @@ void edma_clear_event(unsigned channel); void edma_pause(unsigned channel); void edma_resume(unsigned channel); +/* UNRELATED TO DMA */ +int davinci_alloc_iram(unsigned size); +void davinci_free_iram(unsigned addr, unsigned size); + /* platform_data for EDMA driver */ struct edma_soc_info { diff --git a/trunk/arch/arm/mach-davinci/include/mach/emac.h b/trunk/arch/arm/mach-davinci/include/mach/emac.h deleted file mode 100644 index beff4fb7c845..000000000000 --- a/trunk/arch/arm/mach-davinci/include/mach/emac.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * TI DaVinci EMAC platform support - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef _MACH_DAVINCI_EMAC_H -#define _MACH_DAVINCI_EMAC_H - -#include -#include - -struct emac_platform_data { - char mac_addr[ETH_ALEN]; - u32 ctrl_reg_offset; - u32 ctrl_mod_reg_offset; - u32 ctrl_ram_offset; - u32 mdio_reg_offset; - u32 ctrl_ram_size; - u32 phy_mask; - u32 mdio_max_freq; - u8 rmii_en; - u8 version; -}; - -enum { - EMAC_VERSION_1, /* DM644x */ - EMAC_VERSION_2, /* DM646x */ -}; - -void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context); -#endif diff --git a/trunk/arch/arm/mach-davinci/include/mach/entry-macro.S b/trunk/arch/arm/mach-davinci/include/mach/entry-macro.S index fbdebc7cb409..039b84f933b3 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/entry-macro.S +++ b/trunk/arch/arm/mach-davinci/include/mach/entry-macro.S @@ -15,36 +15,17 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =davinci_intc_base - ldr \base, [\base] + ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC) - ldr \tmp, =davinci_intc_type - ldr \tmp, [\tmp] - cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC - beq 1001f -#endif -#if defined(CONFIG_AINTC) ldr \tmp, [\base, #0x14] - movs \tmp, \tmp, lsr #2 + mov \tmp, \tmp, lsr #2 sub \irqnr, \tmp, #1 - b 1002f -#endif -#if defined(CONFIG_CP_INTC) -1001: ldr \irqnr, [\base, #0x80] /* get irq number */ - and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */ - mov \tmp, \irqnr, lsr #3 - and \tmp, \tmp, #0xfc - add \tmp, \tmp, #0x280 /* get the register offset */ - ldr \irqstat, [\base, \tmp] /* get the intc status */ - cmp \irqstat, #0x0 -#endif -1002: + cmp \tmp, #0 .endm .macro irq_prio_table diff --git a/trunk/arch/arm/mach-davinci/include/mach/gpio.h b/trunk/arch/arm/mach-davinci/include/mach/gpio.h index ae0745568316..efe3281364e6 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/gpio.h +++ b/trunk/arch/arm/mach-davinci/include/mach/gpio.h @@ -17,7 +17,6 @@ #include #include -#include #define DAVINCI_GPIO_BASE 0x01C67000 @@ -68,16 +67,15 @@ static inline struct gpio_controller *__iomem __gpio_to_controller(unsigned gpio) { void *__iomem ptr; - void __iomem *base = davinci_soc_info.gpio_base; if (gpio < 32 * 1) - ptr = base + 0x10; + ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); else if (gpio < 32 * 2) - ptr = base + 0x38; + ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); else if (gpio < 32 * 3) - ptr = base + 0x60; + ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); else if (gpio < 32 * 4) - ptr = base + 0x88; + ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88); else ptr = NULL; return ptr; @@ -144,13 +142,13 @@ static inline int gpio_to_irq(unsigned gpio) { if (gpio >= DAVINCI_N_GPIO) return -EINVAL; - return davinci_soc_info.intc_irq_num + gpio; + return DAVINCI_N_AINTC_IRQ + gpio; } static inline int irq_to_gpio(unsigned irq) { /* caller guarantees gpio_to_irq() succeeded */ - return irq - davinci_soc_info.intc_irq_num; + return irq - DAVINCI_N_AINTC_IRQ; } #endif /* __DAVINCI_GPIO_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/irqs.h b/trunk/arch/arm/mach-davinci/include/mach/irqs.h index bc5d6aaa69a3..18066074c995 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/irqs.h +++ b/trunk/arch/arm/mach-davinci/include/mach/irqs.h @@ -30,9 +30,6 @@ /* Base address */ #define DAVINCI_ARM_INTC_BASE 0x01C48000 -#define DAVINCI_INTC_TYPE_AINTC 0 -#define DAVINCI_INTC_TYPE_CP_INTC 1 - /* Interrupt lines */ #define IRQ_VDINT0 0 #define IRQ_VDINT1 1 diff --git a/trunk/arch/arm/mach-davinci/include/mach/memory.h b/trunk/arch/arm/mach-davinci/include/mach/memory.h index c712c7cdf38f..86c25c7f3ce3 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/memory.h +++ b/trunk/arch/arm/mach-davinci/include/mach/memory.h @@ -21,6 +21,7 @@ * Definitions **************************************************************************/ #define DAVINCI_DDR_BASE 0x80000000 +#define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ #define PHYS_OFFSET DAVINCI_DDR_BASE diff --git a/trunk/arch/arm/mach-davinci/include/mach/mmc.h b/trunk/arch/arm/mach-davinci/include/mach/mmc.h deleted file mode 100644 index 5a85e24f3673..000000000000 --- a/trunk/arch/arm/mach-davinci/include/mach/mmc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Board-specific MMC configuration - */ - -#ifndef _DAVINCI_MMC_H -#define _DAVINCI_MMC_H - -#include -#include - -struct davinci_mmc_config { - /* get_cd()/get_wp() may sleep */ - int (*get_cd)(int module); - int (*get_ro)(int module); - /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */ - u8 wires; - - u32 max_freq; - - /* any additional host capabilities: OR'd in to mmc->f_caps */ - u32 caps; - - /* Version of the MMC/SD controller */ - u8 version; -}; -void davinci_setup_mmc(int module, struct davinci_mmc_config *config); - -enum { - MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */ - MMC_CTLR_VERSION_2, /* DA830 */ -}; - -#endif diff --git a/trunk/arch/arm/mach-davinci/include/mach/mux.h b/trunk/arch/arm/mach-davinci/include/mach/mux.h index 27378458542f..bae22cb3e27b 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/mux.h +++ b/trunk/arch/arm/mach-davinci/include/mach/mux.h @@ -19,6 +19,16 @@ #ifndef __INC_MACH_MUX_H #define __INC_MACH_MUX_H +/* System module registers */ +#define PINMUX0 0x00 +#define PINMUX1 0x04 +/* dm355 only */ +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define INTMUX 0x18 +#define EVTMUX 0x1c + struct mux_config { const char *name; const char *mux_reg_name; @@ -158,9 +168,15 @@ enum davinci_dm355_index { #ifdef CONFIG_DAVINCI_MUX /* setup pin muxing */ +extern void davinci_mux_init(void); +extern int davinci_mux_register(const struct mux_config *pins, + unsigned long size); extern int davinci_cfg_reg(unsigned long reg_cfg); #else /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ +static inline void davinci_mux_init(void) {} +static inline int davinci_mux_register(const struct mux_config *pins, + unsigned long size) { return 0; } static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } #endif diff --git a/trunk/arch/arm/mach-davinci/include/mach/psc.h b/trunk/arch/arm/mach-davinci/include/mach/psc.h index ab8a2586d1cc..55a90d419fac 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/psc.h +++ b/trunk/arch/arm/mach-davinci/include/mach/psc.h @@ -27,8 +27,6 @@ #ifndef __ASM_ARCH_PSC_H #define __ASM_ARCH_PSC_H -#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 - /* Power and Sleep Controller (PSC) Domains */ #define DAVINCI_GPSC_ARMDOMAIN 0 #define DAVINCI_GPSC_DSPDOMAIN 1 @@ -118,8 +116,8 @@ #define DM646X_LPSC_TIMER1 35 #define DM646X_LPSC_ARM_INTC 45 -extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); -extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, - unsigned int id, char enable); +extern int davinci_psc_is_clk_active(unsigned int id); +extern void davinci_psc_config(unsigned int domain, unsigned int id, + char enable); #endif /* __ASM_ARCH_PSC_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/serial.h b/trunk/arch/arm/mach-davinci/include/mach/serial.h index 794fa5cf93c1..632847d74a1c 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/serial.h +++ b/trunk/arch/arm/mach-davinci/include/mach/serial.h @@ -18,6 +18,8 @@ #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) +#define DM355_UART2_BASE (IO_PHYS + 0x206000) + /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c #define UART_DM646X_SCR 0x10 @@ -28,6 +30,6 @@ struct davinci_uart_config { unsigned int enabled_uarts; }; -extern int davinci_serial_init(struct davinci_uart_config *); +extern void davinci_serial_init(struct davinci_uart_config *); #endif /* __ASM_ARCH_SERIAL_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/sram.h b/trunk/arch/arm/mach-davinci/include/mach/sram.h deleted file mode 100644 index 111f7cc71e07..000000000000 --- a/trunk/arch/arm/mach-davinci/include/mach/sram.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * mach/sram.h - DaVinci simple SRAM allocator - * - * Copyright (C) 2009 David Brownell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MACH_SRAM_H -#define __MACH_SRAM_H - -/* ARBITRARY: SRAM allocations are multiples of this 2^N size */ -#define SRAM_GRANULARITY 512 - -/* - * SRAM allocations return a CPU virtual address, or NULL on error. - * If a DMA address is requested and the SRAM supports DMA, its - * mapped address is also returned. - * - * Errors include SRAM memory not being available, and requesting - * DMA mapped SRAM on systems which don't allow that. - */ -extern void *sram_alloc(size_t len, dma_addr_t *dma); -extern void sram_free(void *addr, size_t len); - -#endif /* __MACH_SRAM_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/time.h b/trunk/arch/arm/mach-davinci/include/mach/time.h deleted file mode 100644 index 1c971d8d8ba8..000000000000 --- a/trunk/arch/arm/mach-davinci/include/mach/time.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Local header file for DaVinci time code. - * - * Author: Kevin Hilman, MontaVista Software, Inc. - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H -#define __ARCH_ARM_MACH_DAVINCI_TIME_H - -#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) -#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) -#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) - -enum { - T0_BOT, - T0_TOP, - T1_BOT, - T1_TOP, - NUM_TIMERS -}; - -#define IS_TIMER1(id) (id & 0x2) -#define IS_TIMER0(id) (!IS_TIMER1(id)) -#define IS_TIMER_TOP(id) ((id & 0x1)) -#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) - -#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0) - -extern struct davinci_timer_instance davinci_timer_instance[]; - -#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/uncompress.h b/trunk/arch/arm/mach-davinci/include/mach/uncompress.h index 1e27475f9a23..8c165def37b6 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-davinci/include/mach/uncompress.h @@ -13,24 +13,11 @@ #include #include -#include - -extern unsigned int __machine_arch_type; - -static u32 *uart; - -static u32 *get_uart_base(void) -{ - /* Add logic here for new platforms, using __macine_arch_type */ - return (u32 *)DAVINCI_UART0_BASE; -} - /* PORT_16C550A, in polled non-fifo mode */ static void putc(char c) { - if (!uart) - uart = get_uart_base(); + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; while (!(uart[UART_LSR] & UART_LSR_THRE)) barrier(); @@ -39,9 +26,7 @@ static void putc(char c) static inline void flush(void) { - if (!uart) - uart = get_uart_base(); - + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; while (!(uart[UART_LSR] & UART_LSR_THRE)) barrier(); } diff --git a/trunk/arch/arm/mach-davinci/io.c b/trunk/arch/arm/mach-davinci/io.c index 49912b48b1b0..a548abb513e2 100644 --- a/trunk/arch/arm/mach-davinci/io.c +++ b/trunk/arch/arm/mach-davinci/io.c @@ -9,9 +9,47 @@ */ #include +#include +#include #include #include +#include + +#include +#include + +extern void davinci_check_revision(void); + +/* + * The machine specific code may provide the extra mapping besides the + * default mapping provided here. + */ +static struct map_desc davinci_io_desc[] __initdata = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, +}; + +void __init davinci_map_common_io(void) +{ + iotable_init(davinci_io_desc, ARRAY_SIZE(davinci_io_desc)); + + /* Normally devicemaps_init() would flush caches and tlb after + * mdesc->map_io(), but we must also do it here because of the CPU + * revision check below. + */ + local_flush_tlb_all(); + flush_cache_all(); + + /* We want to check CPU revision early for cpu_is_xxxx() macros. + * IO space mapping must be initialized before we can do that. + */ + davinci_check_revision(); +} #define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) #define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst))) diff --git a/trunk/arch/arm/mach-davinci/irq.c b/trunk/arch/arm/mach-davinci/irq.c index af92ffee8471..5a324c90e291 100644 --- a/trunk/arch/arm/mach-davinci/irq.c +++ b/trunk/arch/arm/mach-davinci/irq.c @@ -26,7 +26,6 @@ #include #include -#include #include #define IRQ_BIT(irq) ((irq) & 0x1f) @@ -42,14 +41,18 @@ #define IRQ_INTPRI0_REG_OFFSET 0x0030 #define IRQ_INTPRI7_REG_OFFSET 0x004C +const u8 *davinci_def_priorities; + +#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE) + static inline unsigned int davinci_irq_readl(int offset) { - return __raw_readl(davinci_intc_base + offset); + return __raw_readl(INTC_BASE + offset); } static inline void davinci_irq_writel(unsigned long value, int offset) { - __raw_writel(value, davinci_intc_base + offset); + __raw_writel(value, INTC_BASE + offset); } /* Disable interrupt */ @@ -110,11 +113,217 @@ static struct irq_chip davinci_irq_chip_0 = { .unmask = davinci_unmask_irq, }; +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { + [IRQ_VDINT0] = 2, + [IRQ_VDINT1] = 6, + [IRQ_VDINT2] = 6, + [IRQ_HISTINT] = 6, + [IRQ_H3AINT] = 6, + [IRQ_PRVUINT] = 6, + [IRQ_RSZINT] = 6, + [7] = 7, + [IRQ_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_VLCDINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_EMACINT] = 4, + [14] = 7, + [15] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_CCERRINT] = 5, /* dma */ + [IRQ_TCERRINT0] = 5, /* dma */ + [IRQ_TCERRINT] = 5, /* dma */ + [IRQ_PSCIN] = 7, + [21] = 7, + [IRQ_IDE] = 4, + [23] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_SDIOINT] = 7, + [28] = 7, + [IRQ_DDRINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_VLQINT] = 4, + [IRQ_TINT0_TINT12] = 2, /* clockevent */ + [IRQ_TINT0_TINT34] = 2, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_PWMINT2] = 7, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_UARTINT2] = 3, + [IRQ_SPINT0] = 3, + [IRQ_SPINT1] = 3, + [45] = 7, + [IRQ_DSP2ARM0] = 4, + [IRQ_DSP2ARM1] = 4, + [IRQ_GPIO0] = 7, + [IRQ_GPIO1] = 7, + [IRQ_GPIO2] = 7, + [IRQ_GPIO3] = 7, + [IRQ_GPIO4] = 7, + [IRQ_GPIO5] = 7, + [IRQ_GPIO6] = 7, + [IRQ_GPIO7] = 7, + [IRQ_GPIOBNK0] = 7, + [IRQ_GPIOBNK1] = 7, + [IRQ_GPIOBNK2] = 7, + [IRQ_GPIOBNK3] = 7, + [IRQ_GPIOBNK4] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + +static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_DM646X_VP_VERTINT0] = 7, + [IRQ_DM646X_VP_VERTINT1] = 7, + [IRQ_DM646X_VP_VERTINT2] = 7, + [IRQ_DM646X_VP_VERTINT3] = 7, + [IRQ_DM646X_VP_ERRINT] = 7, + [IRQ_DM646X_RESERVED_1] = 7, + [IRQ_DM646X_RESERVED_2] = 7, + [IRQ_DM646X_WDINT] = 7, + [IRQ_DM646X_CRGENINT0] = 7, + [IRQ_DM646X_CRGENINT1] = 7, + [IRQ_DM646X_TSIFINT0] = 7, + [IRQ_DM646X_TSIFINT1] = 7, + [IRQ_DM646X_VDCEINT] = 7, + [IRQ_DM646X_USBINT] = 7, + [IRQ_DM646X_USBDMAINT] = 7, + [IRQ_DM646X_PCIINT] = 7, + [IRQ_CCINT0] = 7, /* dma */ + [IRQ_CCERRINT] = 7, /* dma */ + [IRQ_TCERRINT0] = 7, /* dma */ + [IRQ_TCERRINT] = 7, /* dma */ + [IRQ_DM646X_TCERRINT2] = 7, + [IRQ_DM646X_TCERRINT3] = 7, + [IRQ_DM646X_IDE] = 7, + [IRQ_DM646X_HPIINT] = 7, + [IRQ_DM646X_EMACRXTHINT] = 7, + [IRQ_DM646X_EMACRXINT] = 7, + [IRQ_DM646X_EMACTXINT] = 7, + [IRQ_DM646X_EMACMISCINT] = 7, + [IRQ_DM646X_MCASP0TXINT] = 7, + [IRQ_DM646X_MCASP0RXINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_DM646X_RESERVED_3] = 7, + [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ + [IRQ_TINT0_TINT34] = 7, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_DM646X_VLQINT] = 7, + [IRQ_I2C] = 7, + [IRQ_UARTINT0] = 7, + [IRQ_UARTINT1] = 7, + [IRQ_DM646X_UARTINT2] = 7, + [IRQ_DM646X_SPINT0] = 7, + [IRQ_DM646X_SPINT1] = 7, + [IRQ_DM646X_DSP2ARMINT] = 7, + [IRQ_DM646X_RESERVED_4] = 7, + [IRQ_DM646X_PSCINT] = 7, + [IRQ_DM646X_GPIO0] = 7, + [IRQ_DM646X_GPIO1] = 7, + [IRQ_DM646X_GPIO2] = 7, + [IRQ_DM646X_GPIO3] = 7, + [IRQ_DM646X_GPIO4] = 7, + [IRQ_DM646X_GPIO5] = 7, + [IRQ_DM646X_GPIO6] = 7, + [IRQ_DM646X_GPIO7] = 7, + [IRQ_DM646X_GPIOBNK0] = 7, + [IRQ_DM646X_GPIOBNK1] = 7, + [IRQ_DM646X_GPIOBNK2] = 7, + [IRQ_DM646X_DDRINT] = 7, + [IRQ_DM646X_AEMIFINT] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + +static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_DM355_CCDC_VDINT0] = 2, + [IRQ_DM355_CCDC_VDINT1] = 6, + [IRQ_DM355_CCDC_VDINT2] = 6, + [IRQ_DM355_IPIPE_HST] = 6, + [IRQ_DM355_H3AINT] = 6, + [IRQ_DM355_IPIPE_SDR] = 6, + [IRQ_DM355_IPIPEIFINT] = 6, + [IRQ_DM355_OSDINT] = 7, + [IRQ_DM355_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_DM355_RTOINT] = 4, + [IRQ_DM355_UARTINT2] = 7, + [IRQ_DM355_TINT6] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_CCERRINT] = 5, /* dma */ + [IRQ_TCERRINT0] = 5, /* dma */ + [IRQ_TCERRINT] = 5, /* dma */ + [IRQ_DM355_SPINT2_1] = 7, + [IRQ_DM355_TINT7] = 4, + [IRQ_DM355_SDIOINT0] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_DM355_MMCINT1] = 7, + [IRQ_DM355_PWMINT3] = 7, + [IRQ_DDRINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_DM355_SDIOINT1] = 4, + [IRQ_TINT0_TINT12] = 2, /* clockevent */ + [IRQ_TINT0_TINT34] = 2, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_PWMINT2] = 7, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_DM355_SPINT0_0] = 3, + [IRQ_DM355_SPINT0_1] = 3, + [IRQ_DM355_GPIO0] = 3, + [IRQ_DM355_GPIO1] = 7, + [IRQ_DM355_GPIO2] = 4, + [IRQ_DM355_GPIO3] = 4, + [IRQ_DM355_GPIO4] = 7, + [IRQ_DM355_GPIO5] = 7, + [IRQ_DM355_GPIO6] = 7, + [IRQ_DM355_GPIO7] = 7, + [IRQ_DM355_GPIO8] = 7, + [IRQ_DM355_GPIO9] = 7, + [IRQ_DM355_GPIOBNK0] = 7, + [IRQ_DM355_GPIOBNK1] = 7, + [IRQ_DM355_GPIOBNK2] = 7, + [IRQ_DM355_GPIOBNK3] = 7, + [IRQ_DM355_GPIOBNK4] = 7, + [IRQ_DM355_GPIOBNK5] = 7, + [IRQ_DM355_GPIOBNK6] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + /* ARM Interrupt Controller Initialization */ void __init davinci_irq_init(void) { unsigned i; - const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; + + if (cpu_is_davinci_dm644x()) + davinci_def_priorities = dm644x_default_priorities; + else if (cpu_is_davinci_dm646x()) + davinci_def_priorities = dm646x_default_priorities; + else if (cpu_is_davinci_dm355()) + davinci_def_priorities = dm355_default_priorities; /* Clear all interrupt requests */ davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); diff --git a/trunk/arch/arm/mach-davinci/mux.c b/trunk/arch/arm/mach-davinci/mux.c index d310f579aa85..bbba0b247a44 100644 --- a/trunk/arch/arm/mach-davinci/mux.c +++ b/trunk/arch/arm/mach-davinci/mux.c @@ -21,7 +21,18 @@ #include #include -#include + +static const struct mux_config *mux_table; +static unsigned long pin_table_sz; + +int __init davinci_mux_register(const struct mux_config *pins, + unsigned long size) +{ + mux_table = pins; + pin_table_sz = size; + + return 0; +} /* * Sets the DAVINCI MUX register based on the table @@ -29,24 +40,23 @@ int __init_or_module davinci_cfg_reg(const unsigned long index) { static DEFINE_SPINLOCK(mux_spin_lock); - struct davinci_soc_info *soc_info = &davinci_soc_info; - void __iomem *base = soc_info->pinmux_base; + void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); unsigned long flags; const struct mux_config *cfg; unsigned int reg_orig = 0, reg = 0; unsigned int mask, warn = 0; - if (!soc_info->pinmux_pins) + if (!mux_table) BUG(); - if (index >= soc_info->pinmux_pins_num) { + if (index >= pin_table_sz) { printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", - index, soc_info->pinmux_pins_num); + index, pin_table_sz); dump_stack(); return -ENODEV; } - cfg = &soc_info->pinmux_pins[index]; + cfg = &mux_table[index]; if (cfg->name == NULL) { printk(KERN_ERR "No entry for the specified index\n"); diff --git a/trunk/arch/arm/mach-davinci/psc.c b/trunk/arch/arm/mach-davinci/psc.c index a78b657e916e..84171abf5f7b 100644 --- a/trunk/arch/arm/mach-davinci/psc.c +++ b/trunk/arch/arm/mach-davinci/psc.c @@ -28,6 +28,8 @@ #include #include +#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 + /* PSC register offsets */ #define EPCPR 0x070 #define PTCMD 0x120 @@ -40,42 +42,22 @@ #define MDSTAT_STATE_MASK 0x1f /* Return nonzero iff the domain's clock is active */ -int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) +int __init davinci_psc_is_clk_active(unsigned int id) { - void __iomem *psc_base; - u32 mdstat; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { - pr_warning("PSC: Bad psc data: 0x%x[%d]\n", - (int)soc_info->psc_bases, ctlr); - return 0; - } - - psc_base = soc_info->psc_bases[ctlr]; - mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); + void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); + u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); /* if clocked, state can be "Enable" or "SyncReset" */ return mdstat & BIT(12); } /* Enable or disable a PSC domain */ -void davinci_psc_config(unsigned int domain, unsigned int ctlr, - unsigned int id, char enable) +void davinci_psc_config(unsigned int domain, unsigned int id, char enable) { u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; - void __iomem *psc_base; - struct davinci_soc_info *soc_info = &davinci_soc_info; + void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */ - if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { - pr_warning("PSC: Bad psc data: 0x%x[%d]\n", - (int)soc_info->psc_bases, ctlr); - return; - } - - psc_base = soc_info->psc_bases[ctlr]; - mdctl = __raw_readl(psc_base + MDCTL + 4 * id); mdctl &= ~MDSTAT_STATE_MASK; mdctl |= next_state; diff --git a/trunk/arch/arm/mach-davinci/serial.c b/trunk/arch/arm/mach-davinci/serial.c index c530c7333d0a..695075796522 100644 --- a/trunk/arch/arm/mach-davinci/serial.c +++ b/trunk/arch/arm/mach-davinci/serial.c @@ -33,8 +33,6 @@ #include #include #include -#include - #include "clock.h" static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, @@ -51,6 +49,44 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, __raw_writel(value, IO_ADDRESS(p->mapbase) + offset); } +static struct plat_serial8250_port serial_platform_data[] = { + { + .mapbase = DAVINCI_UART0_BASE, + .irq = IRQ_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART1_BASE, + .irq = IRQ_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART2_BASE, + .irq = IRQ_UARTINT2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .flags = 0 + }, +}; + +static struct platform_device serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data, + }, +}; + static void __init davinci_serial_reset(struct plat_serial8250_port *p) { unsigned int pwremu = 0; @@ -70,22 +106,35 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p) UART_DM646X_SCR_TX_WATERMARK); } -int __init davinci_serial_init(struct davinci_uart_config *info) +void __init davinci_serial_init(struct davinci_uart_config *info) { int i; char name[16]; struct clk *uart_clk; - struct davinci_soc_info *soc_info = &davinci_soc_info; - struct device *dev = &soc_info->serial_dev->dev; - struct plat_serial8250_port *p = dev->platform_data; + struct device *dev = &serial_device.dev; /* * Make sure the serial ports are muxed on at this point. - * You have to mux them off in device drivers later on if not needed. + * You have to mux them off in device drivers later on + * if not needed. */ - for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) { - if (!(info->enabled_uarts & (1 << i))) + for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) { + struct plat_serial8250_port *p = serial_platform_data + i; + + if (!(info->enabled_uarts & (1 << i))) { + p->flags = 0; continue; + } + + if (cpu_is_davinci_dm646x()) + p->iotype = UPIO_MEM32; + + if (cpu_is_davinci_dm355()) { + if (i == 2) { + p->mapbase = (unsigned long)DM355_UART2_BASE; + p->irq = IRQ_DM355_UARTINT2; + } + } sprintf(name, "uart%d", i); uart_clk = clk_get(dev, name); @@ -98,6 +147,11 @@ int __init davinci_serial_init(struct davinci_uart_config *info) davinci_serial_reset(p); } } +} - return platform_device_register(soc_info->serial_dev); +static int __init davinci_init(void) +{ + return platform_device_register(&serial_device); } + +arch_initcall(davinci_init); diff --git a/trunk/arch/arm/mach-davinci/sram.c b/trunk/arch/arm/mach-davinci/sram.c deleted file mode 100644 index db54b2a66b4d..000000000000 --- a/trunk/arch/arm/mach-davinci/sram.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * mach-davinci/sram.c - DaVinci simple SRAM allocator - * - * Copyright (C) 2009 David Brownell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#include -#include -#include -#include - -#include -#include -#include - - -static struct gen_pool *sram_pool; - -void *sram_alloc(size_t len, dma_addr_t *dma) -{ - unsigned long vaddr; - dma_addr_t dma_base = davinci_soc_info.sram_dma; - - if (dma) - *dma = 0; - if (!sram_pool || (dma && !dma_base)) - return NULL; - - vaddr = gen_pool_alloc(sram_pool, len); - if (!vaddr) - return NULL; - - if (dma) - *dma = dma_base + (vaddr - SRAM_VIRT); - return (void *)vaddr; - -} -EXPORT_SYMBOL(sram_alloc); - -void sram_free(void *addr, size_t len) -{ - gen_pool_free(sram_pool, (unsigned long) addr, len); -} -EXPORT_SYMBOL(sram_free); - - -/* - * REVISIT This supports CPU and DMA access to/from SRAM, but it - * doesn't (yet?) support some other notable uses of SRAM: as TCM - * for data and/or instructions; and holding code needed to enter - * and exit suspend states (while DRAM can't be used). - */ -static int __init sram_init(void) -{ - unsigned len = davinci_soc_info.sram_len; - int status = 0; - - if (len) { - len = min(len, SRAM_SIZE); - sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1); - if (!sram_pool) - status = -ENOMEM; - } - if (sram_pool) - status = gen_pool_add(sram_pool, SRAM_VIRT, len, -1); - WARN_ON(status < 0); - return status; -} -core_initcall(sram_init); - diff --git a/trunk/arch/arm/mach-davinci/time.c b/trunk/arch/arm/mach-davinci/time.c index 0884ca57bfb0..494e01bff5c3 100644 --- a/trunk/arch/arm/mach-davinci/time.c +++ b/trunk/arch/arm/mach-davinci/time.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -29,41 +28,52 @@ #include #include #include -#include #include "clock.h" static struct clock_event_device clockevent_davinci; static unsigned int davinci_clock_tick_rate; +#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) +#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) +#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) + +enum { + T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS, +}; + +#define IS_TIMER1(id) (id & 0x2) +#define IS_TIMER0(id) (!IS_TIMER1(id)) +#define IS_TIMER_TOP(id) ((id & 0x1)) +#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) + +static int timer_irqs[NUM_TIMERS] = { + IRQ_TINT0_TINT12, + IRQ_TINT0_TINT34, + IRQ_TINT1_TINT12, + IRQ_TINT1_TINT34, +}; + /* * This driver configures the 2 64-bit count-up timers as 4 independent * 32-bit count-up timers used as follows: + * + * T0_BOT: Timer 0, bottom: clockevent source for hrtimers + * T0_TOP: Timer 0, top : clocksource for generic timekeeping + * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) + * T1_TOP: Timer 1, top : */ - -enum { - TID_CLOCKEVENT, - TID_CLOCKSOURCE, -}; +#define TID_CLOCKEVENT T0_BOT +#define TID_CLOCKSOURCE T0_TOP /* Timer register offsets */ -#define PID12 0x0 -#define TIM12 0x10 -#define TIM34 0x14 -#define PRD12 0x18 -#define PRD34 0x1c -#define TCR 0x20 -#define TGCR 0x24 -#define WDTCR 0x28 - -/* Offsets of the 8 compare registers */ -#define CMP12_0 0x60 -#define CMP12_1 0x64 -#define CMP12_2 0x68 -#define CMP12_3 0x6c -#define CMP12_4 0x70 -#define CMP12_5 0x74 -#define CMP12_6 0x78 -#define CMP12_7 0x7c +#define PID12 0x0 +#define TIM12 0x10 +#define TIM34 0x14 +#define PRD12 0x18 +#define PRD34 0x1c +#define TCR 0x20 +#define TGCR 0x24 +#define WDTCR 0x28 /* Timer register bitfields */ #define TCR_ENAMODE_DISABLE 0x0 @@ -95,7 +105,6 @@ struct timer_s { unsigned int id; unsigned long period; unsigned long opts; - unsigned long flags; void __iomem *base; unsigned long tim_off; unsigned long prd_off; @@ -105,58 +114,30 @@ struct timer_s { static struct timer_s timers[]; /* values for 'opts' field of struct timer_s */ -#define TIMER_OPTS_DISABLED 0x01 -#define TIMER_OPTS_ONESHOT 0x02 -#define TIMER_OPTS_PERIODIC 0x04 -#define TIMER_OPTS_STATE_MASK 0x07 - -#define TIMER_OPTS_USE_COMPARE 0x80000000 -#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE) - -static char *id_to_name[] = { - [T0_BOT] = "timer0_0", - [T0_TOP] = "timer0_1", - [T1_BOT] = "timer1_0", - [T1_TOP] = "timer1_1", -}; +#define TIMER_OPTS_DISABLED 0x00 +#define TIMER_OPTS_ONESHOT 0x01 +#define TIMER_OPTS_PERIODIC 0x02 static int timer32_config(struct timer_s *t) { - u32 tcr; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - if (USING_COMPARE(t)) { - struct davinci_timer_instance *dtip = - soc_info->timer_info->timers; - int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id); - - /* - * Next interrupt should be the current time reg value plus - * the new period (using 32-bit unsigned addition/wrapping - * to 0 on overflow). This assumes that the clocksource - * is setup to count to 2^32-1 before wrapping around to 0. - */ - __raw_writel(__raw_readl(t->base + t->tim_off) + t->period, - t->base + dtip[event_timer].cmp_off); - } else { - tcr = __raw_readl(t->base + TCR); - - /* disable timer */ - tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); - __raw_writel(tcr, t->base + TCR); - - /* reset counter to zero, set new period */ - __raw_writel(0, t->base + t->tim_off); - __raw_writel(t->period, t->base + t->prd_off); - - /* Set enable mode */ - if (t->opts & TIMER_OPTS_ONESHOT) - tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; - else if (t->opts & TIMER_OPTS_PERIODIC) - tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; - - __raw_writel(tcr, t->base + TCR); + u32 tcr = __raw_readl(t->base + TCR); + + /* disable timer */ + tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); + __raw_writel(tcr, t->base + TCR); + + /* reset counter to zero, set new period */ + __raw_writel(0, t->base + t->tim_off); + __raw_writel(t->period, t->base + t->prd_off); + + /* Set enable mode */ + if (t->opts & TIMER_OPTS_ONESHOT) { + tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; + } else if (t->opts & TIMER_OPTS_PERIODIC) { + tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; } + + __raw_writel(tcr, t->base + TCR); return 0; } @@ -201,14 +182,13 @@ static struct timer_s timers[] = { static void __init timer_init(void) { - struct davinci_soc_info *soc_info = &davinci_soc_info; - struct davinci_timer_instance *dtip = soc_info->timer_info->timers; + u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; int i; /* Global init of each 64-bit timer as a whole */ for(i=0; i<2; i++) { u32 tgcr; - void __iomem *base = dtip[i].base; + void __iomem *base = IO_ADDRESS(phys_bases[i]); /* Disabled, Internal clock source */ __raw_writel(0, base + TCR); @@ -234,33 +214,33 @@ static void __init timer_init(void) /* Init of each timer as a 32-bit timer */ for (i=0; i< ARRAY_SIZE(timers); i++) { struct timer_s *t = &timers[i]; - int timer = ID_TO_TIMER(t->id); - u32 irq; - - t->base = dtip[timer].base; - - if (IS_TIMER_BOT(t->id)) { - t->enamode_shift = 6; - t->tim_off = TIM12; - t->prd_off = PRD12; - irq = dtip[timer].bottom_irq; - } else { - t->enamode_shift = 22; - t->tim_off = TIM34; - t->prd_off = PRD34; - irq = dtip[timer].top_irq; - } - - /* Register interrupt */ - t->irqaction.name = t->name; - t->irqaction.dev_id = (void *)t; - - if (t->irqaction.handler != NULL) { - irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq; - setup_irq(irq, &t->irqaction); + u32 phys_base; + + if (t->name) { + t->id = i; + phys_base = (IS_TIMER1(t->id) ? + DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); + t->base = IO_ADDRESS(phys_base); + + if (IS_TIMER_BOT(t->id)) { + t->enamode_shift = 6; + t->tim_off = TIM12; + t->prd_off = PRD12; + } else { + t->enamode_shift = 22; + t->tim_off = TIM34; + t->prd_off = PRD34; + } + + /* Register interrupt */ + t->irqaction.name = t->name; + t->irqaction.dev_id = (void *)t; + if (t->irqaction.handler != NULL) { + setup_irq(timer_irqs[t->id], &t->irqaction); + } + + timer32_config(&timers[i]); } - - timer32_config(&timers[i]); } } @@ -275,6 +255,7 @@ static cycle_t read_cycles(struct clocksource *cs) } static struct clocksource clocksource_davinci = { + .name = "timer0_1", .rating = 300, .read = read_cycles, .mask = CLOCKSOURCE_MASK(32), @@ -303,18 +284,15 @@ static void davinci_set_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: t->period = davinci_clock_tick_rate / (HZ); - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_PERIODIC; + t->opts = TIMER_OPTS_PERIODIC; timer32_config(t); break; case CLOCK_EVT_MODE_ONESHOT: - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_ONESHOT; + t->opts = TIMER_OPTS_ONESHOT; break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_DISABLED; + t->opts = TIMER_OPTS_DISABLED; break; case CLOCK_EVT_MODE_RESUME: break; @@ -322,6 +300,7 @@ static void davinci_set_mode(enum clock_event_mode mode, } static struct clock_event_device clockevent_davinci = { + .name = "timer0_0", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .shift = 32, .set_next_event = davinci_set_next_event, @@ -332,42 +311,10 @@ static struct clock_event_device clockevent_davinci = { static void __init davinci_timer_init(void) { struct clk *timer_clk; - struct davinci_soc_info *soc_info = &davinci_soc_info; - unsigned int clockevent_id; - unsigned int clocksource_id; + static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; - clockevent_id = soc_info->timer_info->clockevent_id; - clocksource_id = soc_info->timer_info->clocksource_id; - - timers[TID_CLOCKEVENT].id = clockevent_id; - timers[TID_CLOCKSOURCE].id = clocksource_id; - - /* - * If using same timer for both clock events & clocksource, - * a compare register must be used to generate an event interrupt. - * This is equivalent to a oneshot timer only (not periodic). - */ - if (clockevent_id == clocksource_id) { - struct davinci_timer_instance *dtip = - soc_info->timer_info->timers; - int event_timer = ID_TO_TIMER(clockevent_id); - - /* Only bottom timers can use compare regs */ - if (IS_TIMER_TOP(clockevent_id)) - pr_warning("davinci_timer_init: Invalid use" - " of system timers. Results unpredictable.\n"); - else if ((dtip[event_timer].cmp_off == 0) - || (dtip[event_timer].cmp_irq == 0)) - pr_warning("davinci_timer_init: Invalid timer instance" - " setup. Results unpredictable.\n"); - else { - timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE; - clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT; - } - } - /* init timer hw */ timer_init(); @@ -378,7 +325,6 @@ static void __init davinci_timer_init(void) davinci_clock_tick_rate = clk_get_rate(timer_clk); /* setup clocksource */ - clocksource_davinci.name = id_to_name[clocksource_id]; clocksource_davinci.mult = clocksource_khz2mult(davinci_clock_tick_rate/1000, clocksource_davinci.shift); @@ -386,12 +332,12 @@ static void __init davinci_timer_init(void) printk(err, clocksource_davinci.name); /* setup clockevent */ - clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id]; clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC, clockevent_davinci.shift); clockevent_davinci.max_delta_ns = clockevent_delta2ns(0xfffffffe, &clockevent_davinci); - clockevent_davinci.min_delta_ns = 50000; /* 50 usec */ + clockevent_davinci.min_delta_ns = + clockevent_delta2ns(1, &clockevent_davinci); clockevent_davinci.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_davinci); @@ -403,14 +349,15 @@ struct sys_timer davinci_timer = { /* reset board using watchdog timer */ -void davinci_watchdog_reset(void) -{ +void davinci_watchdog_reset(void) { u32 tgcr, wdtcr; - struct davinci_soc_info *soc_info = &davinci_soc_info; - void __iomem *base = soc_info->wdt_base; + void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE); + struct device dev; struct clk *wd_clk; + char *name = "watchdog"; - wd_clk = clk_get(&davinci_wdt_device.dev, NULL); + dev_set_name(&dev, name); + wd_clk = clk_get(&dev, NULL); if (WARN_ON(IS_ERR(wd_clk))) return; clk_enable(wd_clk); diff --git a/trunk/arch/arm/mach-ep93xx/Kconfig b/trunk/arch/arm/mach-ep93xx/Kconfig index d7291c682a64..56bddcef6905 100644 --- a/trunk/arch/arm/mach-ep93xx/Kconfig +++ b/trunk/arch/arm/mach-ep93xx/Kconfig @@ -9,135 +9,87 @@ config CRUNCH comment "EP93xx Platforms" -choice - prompt "EP93xx first SDRAM bank selection" - default EP93XX_SDCE3_SYNC_PHYS_OFFSET - -config EP93XX_SDCE3_SYNC_PHYS_OFFSET - bool "0x00000000 - SDCE3/SyncBoot" - help - Select this option if you want support for EP93xx boards with the - first SDRAM bank at 0x00000000 - -config EP93XX_SDCE0_PHYS_OFFSET - bool "0xc0000000 - SDCEO" - help - Select this option if you want support for EP93xx boards with the - first SDRAM bank at 0xc0000000 - -endchoice - config MACH_ADSSPHERE bool "Support ADS Sphere" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET help Say 'Y' here if you want your kernel to support the ADS Sphere board. -config MACH_EDB93XX - bool - -config MACH_EDB9301 - bool "Support Cirrus Logic EDB9301" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET - select MACH_EDB93XX - help - Say 'Y' here if you want your kernel to support the Cirrus - Logic EDB9301 Evaluation Board. - config MACH_EDB9302 bool "Support Cirrus Logic EDB9302" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET - select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9302 Evaluation Board. config MACH_EDB9302A bool "Support Cirrus Logic EDB9302A" - depends on EP93XX_SDCE0_PHYS_OFFSET - select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9302A Evaluation Board. config MACH_EDB9307 bool "Support Cirrus Logic EDB9307" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET - select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9307 Evaluation Board. config MACH_EDB9307A bool "Support Cirrus Logic EDB9307A" - depends on EP93XX_SDCE0_PHYS_OFFSET - select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9307A Evaluation Board. config MACH_EDB9312 bool "Support Cirrus Logic EDB9312" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET - select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9312 Evaluation Board. config MACH_EDB9315 bool "Support Cirrus Logic EDB9315" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET - select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9315 Evaluation Board. config MACH_EDB9315A bool "Support Cirrus Logic EDB9315A" - depends on EP93XX_SDCE0_PHYS_OFFSET - select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9315A Evaluation Board. config MACH_GESBC9312 - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET bool "Support Glomation GESBC-9312-sx" help Say 'Y' here if you want your kernel to support the Glomation GESBC-9312-sx board. config MACH_MICRO9 - bool + bool + default n config MACH_MICRO9H - bool "Support Contec Hypercontrol Micro9-H" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET - select MACH_MICRO9 - help - Say 'Y' here if you want your kernel to support the - Contec Hypercontrol Micro9-H board. + bool "Support Contec Hypercontrol Micro9-H" + select MACH_MICRO9 + help + Say 'Y' here if you want your kernel to support the + Contec Hypercontrol Micro9-H board. config MACH_MICRO9M - bool "Support Contec Hypercontrol Micro9-M" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET - select MACH_MICRO9 - help - Say 'Y' here if you want your kernel to support the - Contec Hypercontrol Micro9-M board. + bool "Support Contec Hypercontrol Micro9-M" + select MACH_MICRO9 + help + Say 'Y' here if you want your kernel to support the + Contec Hypercontrol Micro9-M board. config MACH_MICRO9L - bool "Support Contec Hypercontrol Micro9-L" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET - select MACH_MICRO9 - help - Say 'Y' here if you want your kernel to support the - Contec Hypercontrol Micro9-L board. + bool "Support Contec Hypercontrol Micro9-L" + select MACH_MICRO9 + help + Say 'Y' here if you want your kernel to support the + Contec Hypercontrol Micro9-L board. config MACH_TS72XX bool "Support Technologic Systems TS-72xx SBC" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET help Say 'Y' here if you want your kernel to support the Technologic Systems TS-72xx board. diff --git a/trunk/arch/arm/mach-ep93xx/Makefile b/trunk/arch/arm/mach-ep93xx/Makefile index eae6199a9891..9522e205b73f 100644 --- a/trunk/arch/arm/mach-ep93xx/Makefile +++ b/trunk/arch/arm/mach-ep93xx/Makefile @@ -7,7 +7,13 @@ obj-n := obj- := obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o -obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o +obj-$(CONFIG_MACH_EDB9302) += edb9302.o +obj-$(CONFIG_MACH_EDB9302A) += edb9302a.o +obj-$(CONFIG_MACH_EDB9307) += edb9307.o +obj-$(CONFIG_MACH_EDB9307A) += edb9307a.o +obj-$(CONFIG_MACH_EDB9312) += edb9312.o +obj-$(CONFIG_MACH_EDB9315) += edb9315.o +obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o obj-$(CONFIG_MACH_MICRO9) += micro9.o obj-$(CONFIG_MACH_TS72XX) += ts72xx.o diff --git a/trunk/arch/arm/mach-ep93xx/Makefile.boot b/trunk/arch/arm/mach-ep93xx/Makefile.boot index 27a085a8f12a..d5561ad15bad 100644 --- a/trunk/arch/arm/mach-ep93xx/Makefile.boot +++ b/trunk/arch/arm/mach-ep93xx/Makefile.boot @@ -1,5 +1,2 @@ - zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) := 0x00008000 -params_phys-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) := 0x00000100 - - zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) := 0xc0008000 -params_phys-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) := 0xc0000100 + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 diff --git a/trunk/arch/arm/mach-ep93xx/clock.c b/trunk/arch/arm/mach-ep93xx/clock.c index 755e981968b7..b2eede5531c8 100644 --- a/trunk/arch/arm/mach-ep93xx/clock.c +++ b/trunk/arch/arm/mach-ep93xx/clock.c @@ -72,58 +72,58 @@ static struct clk clk_h; static struct clk clk_p; static struct clk clk_pll2; static struct clk clk_usb_host = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, }; /* DMA Clocks */ static struct clk clk_m2p0 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x00020000, }; static struct clk clk_m2p1 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x00010000, }; static struct clk clk_m2p2 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x00080000, }; static struct clk clk_m2p3 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x00040000, }; static struct clk clk_m2p4 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x00200000, }; static struct clk clk_m2p5 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x00100000, }; static struct clk clk_m2p6 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x00800000, }; static struct clk clk_m2p7 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x00400000, }; static struct clk clk_m2p8 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x02000000, }; static struct clk clk_m2p9 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x01000000, }; static struct clk clk_m2m0 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x04000000, }; static struct clk clk_m2m1 = { - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1, + .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, + .enable_mask = 0x08000000, }; #define INIT_CK(dev,con,ck) \ @@ -138,7 +138,7 @@ static struct clk_lookup clocks[] = { INIT_CK(NULL, "hclk", &clk_h), INIT_CK(NULL, "pclk", &clk_p), INIT_CK(NULL, "pll2", &clk_pll2), - INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), + INIT_CK(NULL, "usb_host", &clk_usb_host), INIT_CK(NULL, "m2p0", &clk_m2p0), INIT_CK(NULL, "m2p1", &clk_m2p1), INIT_CK(NULL, "m2p2", &clk_m2p2), diff --git a/trunk/arch/arm/mach-ep93xx/core.c b/trunk/arch/arm/mach-ep93xx/core.c index 204dc5cbd0b8..ae24486f858a 100644 --- a/trunk/arch/arm/mach-ep93xx/core.c +++ b/trunk/arch/arm/mach-ep93xx/core.c @@ -155,7 +155,7 @@ static unsigned char gpio_int_unmasked[3]; static unsigned char gpio_int_enabled[3]; static unsigned char gpio_int_type1[3]; static unsigned char gpio_int_type2[3]; -static unsigned char gpio_int_debounce[3]; +static unsigned char gpio_int_debouce[3]; /* Port ordering is: A B F */ static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; @@ -192,11 +192,11 @@ void ep93xx_gpio_int_debounce(unsigned int irq, int enable) int port_mask = 1 << (line & 7); if (enable) - gpio_int_debounce[port] |= port_mask; + gpio_int_debouce[port] |= port_mask; else - gpio_int_debounce[port] &= ~port_mask; + gpio_int_debouce[port] &= ~port_mask; - __raw_writeb(gpio_int_debounce[port], + __raw_writeb(gpio_int_debouce[port], EP93XX_GPIO_REG(int_debounce_register_offset[port])); } EXPORT_SYMBOL(ep93xx_gpio_int_debounce); @@ -362,8 +362,8 @@ void __init ep93xx_init_irq(void) { int gpio_irq; - vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); - vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); + vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK); + vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK); for (gpio_irq = gpio_to_irq(0); gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { @@ -450,19 +450,10 @@ static struct amba_device uart3_device = { }; -static struct resource ep93xx_rtc_resource[] = { - { - .start = EP93XX_RTC_PHYS_BASE, - .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1, - .flags = IORESOURCE_MEM, - }, -}; - static struct platform_device ep93xx_rtc_device = { - .name = "ep93xx-rtc", - .id = -1, - .num_resources = ARRAY_SIZE(ep93xx_rtc_resource), - .resource = ep93xx_rtc_resource, + .name = "ep93xx-rtc", + .id = -1, + .num_resources = 0, }; diff --git a/trunk/arch/arm/mach-ep93xx/edb9302.c b/trunk/arch/arm/mach-ep93xx/edb9302.c new file mode 100644 index 000000000000..8bf8d7c78f1a --- /dev/null +++ b/trunk/arch/arm/mach-ep93xx/edb9302.c @@ -0,0 +1,68 @@ +/* + * arch/arm/mach-ep93xx/edb9302.c + * Cirrus Logic EDB9302 support. + * + * Copyright (C) 2006 George Kashperko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct physmap_flash_data edb9302_flash_data = { + .width = 2, +}; + +static struct resource edb9302_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9302_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9302_flash_data, + }, + .num_resources = 1, + .resource = &edb9302_flash_resource, +}; + +static struct ep93xx_eth_data edb9302_eth_data = { + .phy_id = 1, +}; + +static void __init edb9302_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9302_flash); + + ep93xx_register_eth(&edb9302_eth_data, 1); +} + +MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") + /* Maintainer: George Kashperko */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9302_init_machine, +MACHINE_END diff --git a/trunk/arch/arm/mach-ep93xx/edb9302a.c b/trunk/arch/arm/mach-ep93xx/edb9302a.c new file mode 100644 index 000000000000..a352c57c7b46 --- /dev/null +++ b/trunk/arch/arm/mach-ep93xx/edb9302a.c @@ -0,0 +1,68 @@ +/* + * arch/arm/mach-ep93xx/edb9302a.c + * Cirrus Logic EDB9302A support. + * + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct physmap_flash_data edb9302a_flash_data = { + .width = 2, +}; + +static struct resource edb9302a_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9302a_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9302a_flash_data, + }, + .num_resources = 1, + .resource = &edb9302a_flash_resource, +}; + +static struct ep93xx_eth_data edb9302a_eth_data = { + .phy_id = 1, +}; + +static void __init edb9302a_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9302a_flash); + + ep93xx_register_eth(&edb9302a_eth_data, 1); +} + +MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") + /* Maintainer: Lennert Buytenhek */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9302a_init_machine, +MACHINE_END diff --git a/trunk/arch/arm/mach-ep93xx/edb9307.c b/trunk/arch/arm/mach-ep93xx/edb9307.c new file mode 100644 index 000000000000..5ab22f63a4eb --- /dev/null +++ b/trunk/arch/arm/mach-ep93xx/edb9307.c @@ -0,0 +1,68 @@ +/* + * arch/arm/mach-ep93xx/edb9307.c + * Cirrus Logic EDB9307 support. + * + * Copyright (C) 2007 Herbert Valerio Riedel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct physmap_flash_data edb9307_flash_data = { + .width = 4, +}; + +static struct resource edb9307_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9307_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9307_flash_data, + }, + .num_resources = 1, + .resource = &edb9307_flash_resource, +}; + +static struct ep93xx_eth_data edb9307_eth_data = { + .phy_id = 1, +}; + +static void __init edb9307_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9307_flash); + + ep93xx_register_eth(&edb9307_eth_data, 1); +} + +MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") + /* Maintainer: Herbert Valerio Riedel */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9307_init_machine, +MACHINE_END diff --git a/trunk/arch/arm/mach-ep93xx/edb9307a.c b/trunk/arch/arm/mach-ep93xx/edb9307a.c new file mode 100644 index 000000000000..6171167d3315 --- /dev/null +++ b/trunk/arch/arm/mach-ep93xx/edb9307a.c @@ -0,0 +1,80 @@ +/* + * arch/arm/mach-ep93xx/edb9307a.c + * Cirrus Logic EDB9307A support. + * + * Copyright (C) 2008 H Hartley Sweeten + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct physmap_flash_data edb9307a_flash_data = { + .width = 2, +}; + +static struct resource edb9307a_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9307a_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9307a_flash_data, + }, + .num_resources = 1, + .resource = &edb9307a_flash_resource, +}; + +static struct ep93xx_eth_data edb9307a_eth_data = { + .phy_id = 1, +}; + +static struct i2c_board_info __initdata edb9307a_i2c_data[] = { + { + /* On-board battery backed RTC */ + I2C_BOARD_INFO("isl1208", 0x6f), + }, + /* + * The I2C signals are also routed to the Expansion Connector (J4) + */ +}; + +static void __init edb9307a_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9307a_flash); + + ep93xx_register_eth(&edb9307a_eth_data, 1); + + ep93xx_init_i2c(edb9307a_i2c_data, ARRAY_SIZE(edb9307a_i2c_data)); +} + +MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") + /* Maintainer: H Hartley Sweeten */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9307a_init_machine, +MACHINE_END diff --git a/trunk/arch/arm/mach-ep93xx/edb9312.c b/trunk/arch/arm/mach-ep93xx/edb9312.c new file mode 100644 index 000000000000..d7179f66d804 --- /dev/null +++ b/trunk/arch/arm/mach-ep93xx/edb9312.c @@ -0,0 +1,69 @@ +/* + * arch/arm/mach-ep93xx/edb9312.c + * Cirrus Logic EDB9312 support. + * + * Copyright (C) 2006 Infosys Technologies Limited + * Toufeeq Hussain + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct physmap_flash_data edb9312_flash_data = { + .width = 4, +}; + +static struct resource edb9312_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9312_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9312_flash_data, + }, + .num_resources = 1, + .resource = &edb9312_flash_resource, +}; + +static struct ep93xx_eth_data edb9312_eth_data = { + .phy_id = 1, +}; + +static void __init edb9312_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9312_flash); + + ep93xx_register_eth(&edb9312_eth_data, 1); +} + +MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") + /* Maintainer: Toufeeq Hussain */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9312_init_machine, +MACHINE_END diff --git a/trunk/arch/arm/mach-ep93xx/edb9315.c b/trunk/arch/arm/mach-ep93xx/edb9315.c new file mode 100644 index 000000000000..025af6eaca10 --- /dev/null +++ b/trunk/arch/arm/mach-ep93xx/edb9315.c @@ -0,0 +1,68 @@ +/* + * arch/arm/mach-ep93xx/edb9315.c + * Cirrus Logic EDB9315 support. + * + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct physmap_flash_data edb9315_flash_data = { + .width = 4, +}; + +static struct resource edb9315_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9315_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9315_flash_data, + }, + .num_resources = 1, + .resource = &edb9315_flash_resource, +}; + +static struct ep93xx_eth_data edb9315_eth_data = { + .phy_id = 1, +}; + +static void __init edb9315_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9315_flash); + + ep93xx_register_eth(&edb9315_eth_data, 1); +} + +MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") + /* Maintainer: Lennert Buytenhek */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9315_init_machine, +MACHINE_END diff --git a/trunk/arch/arm/mach-ep93xx/edb9315a.c b/trunk/arch/arm/mach-ep93xx/edb9315a.c new file mode 100644 index 000000000000..4c9cc8a39f5c --- /dev/null +++ b/trunk/arch/arm/mach-ep93xx/edb9315a.c @@ -0,0 +1,68 @@ +/* + * arch/arm/mach-ep93xx/edb9315a.c + * Cirrus Logic EDB9315A support. + * + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct physmap_flash_data edb9315a_flash_data = { + .width = 2, +}; + +static struct resource edb9315a_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9315a_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9315a_flash_data, + }, + .num_resources = 1, + .resource = &edb9315a_flash_resource, +}; + +static struct ep93xx_eth_data edb9315a_eth_data = { + .phy_id = 1, +}; + +static void __init edb9315a_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9315a_flash); + + ep93xx_register_eth(&edb9315a_eth_data, 1); +} + +MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") + /* Maintainer: Lennert Buytenhek */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9315a_init_machine, +MACHINE_END diff --git a/trunk/arch/arm/mach-ep93xx/edb93xx.c b/trunk/arch/arm/mach-ep93xx/edb93xx.c deleted file mode 100644 index e9e45b92457e..000000000000 --- a/trunk/arch/arm/mach-ep93xx/edb93xx.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * arch/arm/mach-ep93xx/edb93xx.c - * Cirrus Logic EDB93xx Development Board support. - * - * EDB93XX, EDB9301, EDB9307A - * Copyright (C) 2008-2009 H Hartley Sweeten - * - * EDB9302 - * Copyright (C) 2006 George Kashperko - * - * EDB9302A, EDB9315, EDB9315A - * Copyright (C) 2006 Lennert Buytenhek - * - * EDB9307 - * Copyright (C) 2007 Herbert Valerio Riedel - * - * EDB9312 - * Copyright (C) 2006 Infosys Technologies Limited - * Toufeeq Hussain - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or (at - * your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct physmap_flash_data edb93xx_flash_data; - -static struct resource edb93xx_flash_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device edb93xx_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &edb93xx_flash_data, - }, - .num_resources = 1, - .resource = &edb93xx_flash_resource, -}; - -static void __init __edb93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size) -{ - edb93xx_flash_data.width = width; - edb93xx_flash_resource.start = start; - edb93xx_flash_resource.end = start + size - 1; - - platform_device_register(&edb93xx_flash); -} - -static void __init edb93xx_register_flash(void) -{ - if (machine_is_edb9307() || machine_is_edb9312() || - machine_is_edb9315()) { - __edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); - } else { - __edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); - } -} - -static struct ep93xx_eth_data edb93xx_eth_data = { - .phy_id = 1, -}; - -static struct i2c_board_info __initdata edb93xxa_i2c_data[] = { - { - I2C_BOARD_INFO("isl1208", 0x6f), - }, -}; - -static struct i2c_board_info __initdata edb93xx_i2c_data[] = { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static void __init edb93xx_register_i2c(void) -{ - if (machine_is_edb9302a() || machine_is_edb9307a() || - machine_is_edb9315a()) { - ep93xx_register_i2c(edb93xxa_i2c_data, - ARRAY_SIZE(edb93xxa_i2c_data)); - } else if (machine_is_edb9307() || machine_is_edb9312() || - machine_is_edb9315()) { - ep93xx_register_i2c(edb93xx_i2c_data, - ARRAY_SIZE(edb93xx_i2c_data)); - } -} - -static void __init edb93xx_init_machine(void) -{ - ep93xx_init_devices(); - edb93xx_register_flash(); - ep93xx_register_eth(&edb93xx_eth_data, 1); - edb93xx_register_i2c(); -} - - -#ifdef CONFIG_MACH_EDB9301 -MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") - /* Maintainer: H Hartley Sweeten */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = edb93xx_init_machine, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9302 -MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") - /* Maintainer: George Kashperko */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = edb93xx_init_machine, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9302A -MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = edb93xx_init_machine, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9307 -MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") - /* Maintainer: Herbert Valerio Riedel */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = edb93xx_init_machine, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9307A -MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") - /* Maintainer: H Hartley Sweeten */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = edb93xx_init_machine, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9312 -MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") - /* Maintainer: Toufeeq Hussain */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = edb93xx_init_machine, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9315 -MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = edb93xx_init_machine, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9315A -MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = edb93xx_init_machine, -MACHINE_END -#endif diff --git a/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index 967c079180db..1732de7629a5 100644 --- a/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h @@ -147,27 +147,13 @@ #define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) #define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000) -#define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000) #define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) -#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) -#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31) -#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29) -#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28) -#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27) -#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16) +#define EP93XX_SYSCON_CLOCK_CONTROL EP93XX_SYSCON_REG(0x04) +#define EP93XX_SYSCON_CLOCK_UARTBAUD 0x20000000 +#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) diff --git a/trunk/arch/arm/mach-ep93xx/include/mach/memory.h b/trunk/arch/arm/mach-ep93xx/include/mach/memory.h index 925b12ea0990..5c80c3c8158d 100644 --- a/trunk/arch/arm/mach-ep93xx/include/mach/memory.h +++ b/trunk/arch/arm/mach-ep93xx/include/mach/memory.h @@ -5,12 +5,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#if defined(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) #define PHYS_OFFSET UL(0x00000000) -#elif defined(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) -#define PHYS_OFFSET UL(0xc0000000) -#else -#error "Kconfig bug: No EP93xx PHYS_OFFSET set" -#endif #endif diff --git a/trunk/arch/arm/mach-gemini/include/mach/hardware.h b/trunk/arch/arm/mach-gemini/include/mach/hardware.h index 213a4fcfeb1c..de6752674c05 100644 --- a/trunk/arch/arm/mach-gemini/include/mach/hardware.h +++ b/trunk/arch/arm/mach-gemini/include/mach/hardware.h @@ -15,9 +15,10 @@ /* * Memory Map definitions */ +/* FIXME: Does it really swap SRAM like this? */ #ifdef CONFIG_GEMINI_MEM_SWAP # define GEMINI_DRAM_BASE 0x00000000 -# define GEMINI_SRAM_BASE 0x70000000 +# define GEMINI_SRAM_BASE 0x20000000 #else # define GEMINI_SRAM_BASE 0x00000000 # define GEMINI_DRAM_BASE 0x10000000 diff --git a/trunk/arch/arm/mach-imx/Kconfig b/trunk/arch/arm/mach-imx/Kconfig new file mode 100644 index 000000000000..cddd194ac6eb --- /dev/null +++ b/trunk/arch/arm/mach-imx/Kconfig @@ -0,0 +1,11 @@ +menu "IMX Implementations" + depends on ARCH_IMX + +config ARCH_MX1ADS + bool "mx1ads" + depends on ARCH_IMX + select ISA + help + Say Y here if you are using the Motorola MX1ADS board + +endmenu diff --git a/trunk/arch/arm/mach-imx/Makefile b/trunk/arch/arm/mach-imx/Makefile new file mode 100644 index 000000000000..b047c7e795a9 --- /dev/null +++ b/trunk/arch/arm/mach-imx/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y += irq.o time.o dma.o generic.o clock.o + +obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o + +# Specific board support +obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o + +# Support for blinky lights +led-y := leds.o + +obj-$(CONFIG_LEDS) += $(led-y) +led-$(CONFIG_ARCH_MX1ADS) += leds-mx1ads.o diff --git a/trunk/arch/arm/mach-imx/Makefile.boot b/trunk/arch/arm/mach-imx/Makefile.boot new file mode 100644 index 000000000000..fd72ce5b8081 --- /dev/null +++ b/trunk/arch/arm/mach-imx/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-$(CONFIG_ARCH_MX1ADS) := 0x08008000 + diff --git a/trunk/arch/arm/mach-imx/clock.c b/trunk/arch/arm/mach-imx/clock.c new file mode 100644 index 000000000000..cf332aeb942e --- /dev/null +++ b/trunk/arch/arm/mach-imx/clock.c @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2008 Sascha Hauer , Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* + * Very simple approach: We can't disable clocks, so we do + * not need refcounting + */ + +struct clk { + struct list_head node; + const char *name; + unsigned long (*get_rate)(void); +}; + +/* + * get the system pll clock in Hz + * + * mfi + mfn / (mfd +1) + * f = 2 * f_ref * -------------------- + * pd + 1 + */ +static unsigned long imx_decode_pll(unsigned int pll, u32 f_ref) +{ + unsigned long long ll; + unsigned long quot; + + u32 mfi = (pll >> 10) & 0xf; + u32 mfn = pll & 0x3ff; + u32 mfd = (pll >> 16) & 0x3ff; + u32 pd = (pll >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + + ll = 2 * (unsigned long long)f_ref * + ((mfi << 16) + (mfn << 16) / (mfd + 1)); + quot = (pd + 1) * (1 << 16); + ll += quot / 2; + do_div(ll, quot); + return (unsigned long)ll; +} + +static unsigned long imx_get_system_clk(void) +{ + u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512); + + return imx_decode_pll(SPCTL0, f_ref); +} + +static unsigned long imx_get_mcu_clk(void) +{ + return imx_decode_pll(MPCTL0, CLK32 * 512); +} + +/* + * get peripheral clock 1 ( UART[12], Timer[12], PWM ) + */ +static unsigned long imx_get_perclk1(void) +{ + return imx_get_system_clk() / (((PCDR) & 0xf)+1); +} + +/* + * get peripheral clock 2 ( LCD, SD, SPI[12] ) + */ +static unsigned long imx_get_perclk2(void) +{ + return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1); +} + +/* + * get peripheral clock 3 ( SSI ) + */ +static unsigned long imx_get_perclk3(void) +{ + return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1); +} + +/* + * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA ) + */ +static unsigned long imx_get_hclk(void) +{ + return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1); +} + +static struct clk clk_system_clk = { + .name = "system_clk", + .get_rate = imx_get_system_clk, +}; + +static struct clk clk_hclk = { + .name = "hclk", + .get_rate = imx_get_hclk, +}; + +static struct clk clk_mcu_clk = { + .name = "mcu_clk", + .get_rate = imx_get_mcu_clk, +}; + +static struct clk clk_perclk1 = { + .name = "perclk1", + .get_rate = imx_get_perclk1, +}; + +static struct clk clk_uart_clk = { + .name = "uart_clk", + .get_rate = imx_get_perclk1, +}; + +static struct clk clk_perclk2 = { + .name = "perclk2", + .get_rate = imx_get_perclk2, +}; + +static struct clk clk_perclk3 = { + .name = "perclk3", + .get_rate = imx_get_perclk3, +}; + +static struct clk *clks[] = { + &clk_perclk1, + &clk_perclk2, + &clk_perclk3, + &clk_system_clk, + &clk_hclk, + &clk_mcu_clk, + &clk_uart_clk, +}; + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); + +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *p, *clk = ERR_PTR(-ENOENT); + + mutex_lock(&clocks_mutex); + list_for_each_entry(p, &clocks, node) { + if (!strcmp(p->name, id)) { + clk = p; + goto found; + } + } + +found: + mutex_unlock(&clocks_mutex); + + return clk; +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->get_rate(); +} +EXPORT_SYMBOL(clk_get_rate); + +int imx_clocks_init(void) +{ + int i; + + mutex_lock(&clocks_mutex); + for (i = 0; i < ARRAY_SIZE(clks); i++) + list_add(&clks[i]->node, &clocks); + mutex_unlock(&clocks_mutex); + + return 0; +} + diff --git a/trunk/arch/arm/mach-imx/cpufreq.c b/trunk/arch/arm/mach-imx/cpufreq.c new file mode 100644 index 000000000000..434b4ca0af67 --- /dev/null +++ b/trunk/arch/arm/mach-imx/cpufreq.c @@ -0,0 +1,315 @@ +/* + * cpu.c: clock scaling for the iMX + * + * Copyright (C) 2000 2001, The Delft University of Technology + * Copyright (c) 2004 Sascha Hauer + * Copyright (C) 2006 Inky Lung + * Copyright (C) 2006 Pavel Pisa, PiKRON + * + * Based on SA1100 version written by: + * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version + * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl): + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/*#define DEBUG*/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "generic.h" + +#ifndef __val2mfld +#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask)) +#endif +#ifndef __mfld2val +#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1))) +#endif + +#define CR_920T_CLOCK_MODE 0xC0000000 +#define CR_920T_FASTBUS_MODE 0x00000000 +#define CR_920T_ASYNC_MODE 0xC0000000 + +static u32 mpctl0_at_boot; +static u32 bclk_div_at_boot; + +static struct clk *system_clk, *mcu_clk; + +static void imx_set_async_mode(void) +{ + adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE); +} + +static void imx_set_fastbus_mode(void) +{ + adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE); +} + +static void imx_set_mpctl0(u32 mpctl0) +{ + unsigned long flags; + + if (mpctl0 == 0) { + local_irq_save(flags); + CSCR &= ~CSCR_MPEN; + local_irq_restore(flags); + return; + } + + local_irq_save(flags); + MPCTL0 = mpctl0; + CSCR |= CSCR_MPEN; + local_irq_restore(flags); +} + +/** + * imx_compute_mpctl - compute new PLL parameters + * @new_mpctl: pointer to location assigned by new PLL control register value + * @cur_mpctl: current PLL control register parameters + * @f_ref: reference source frequency Hz + * @freq: required frequency in Hz + * @relation: is one of %CPUFREQ_RELATION_L (supremum) + * and %CPUFREQ_RELATION_H (infimum) + */ +long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, u32 f_ref, unsigned long freq, int relation) +{ + u32 mfi; + u32 mfn; + u32 mfd; + u32 pd; + unsigned long long ll; + long l; + long quot; + + /* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */ + /* PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */ + + if (cur_mpctl) { + mfd = ((cur_mpctl >> 16) & 0x3ff) + 1; + pd = ((cur_mpctl >> 26) & 0xf) + 1; + } else { + pd=2; mfd=313; + } + + /* pd=2; mfd=313; mfi=8; mfn=183; */ + /* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */ + + quot = (f_ref + (1 << 9)) >> 10; + l = (freq * pd + quot) / (2 * quot); + mfi = l >> 10; + mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10; + + mfd -= 1; + pd -= 1; + + *new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16) + | ((pd & 0xf) << 26); + + ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) ); + quot = (pd+1) * (1<<16); + ll += quot / 2; + do_div(ll, quot); + freq = ll; + + pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n", + pd, mfd, mfi, mfn, freq); + + return freq; +} + + +static int imx_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); + + return 0; +} + +static unsigned int imx_get_speed(unsigned int cpu) +{ + unsigned int freq; + unsigned int cr; + unsigned int cscr; + unsigned int bclk_div; + + if (cpu) + return 0; + + cscr = CSCR; + bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1; + cr = get_cr(); + + if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) { + freq = clk_get_rate(system_clk); + freq = (freq + bclk_div/2) / bclk_div; + } else { + freq = clk_get_rate(mcu_clk); + if (cscr & CSCR_MPU_PRESC) + freq /= 2; + } + + freq = (freq + 500) / 1000; + + return freq; +} + +static int imx_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpufreq_freqs freqs; + u32 mpctl0 = 0; + u32 cscr; + unsigned long flags; + long freq; + long sysclk; + unsigned int bclk_div = bclk_div_at_boot; + + /* + * Some governors do not respects CPU and policy lower limits + * which leads to bad things (division by zero etc), ensure + * that such things do not happen. + */ + if(target_freq < policy->cpuinfo.min_freq) + target_freq = policy->cpuinfo.min_freq; + + if(target_freq < policy->min) + target_freq = policy->min; + + freq = target_freq * 1000; + + pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n", + freq, mpctl0_at_boot); + + sysclk = clk_get_rate(system_clk); + + if (freq > sysclk / bclk_div_at_boot + 1000000) { + freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation); + if (freq < 0) { + printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq); + return -EINVAL; + } + } else { + if(freq + 1000 < sysclk) { + if (relation == CPUFREQ_RELATION_L) + bclk_div = (sysclk - 1000) / freq; + else + bclk_div = (sysclk + freq + 1000) / freq; + + if(bclk_div > 16) + bclk_div = 16; + if(bclk_div < bclk_div_at_boot) + bclk_div = bclk_div_at_boot; + } + freq = (sysclk + bclk_div / 2) / bclk_div; + } + + freqs.old = imx_get_speed(0); + freqs.new = (freq + 500) / 1000; + freqs.cpu = 0; + freqs.flags = 0; + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + local_irq_save(flags); + + imx_set_fastbus_mode(); + + imx_set_mpctl0(mpctl0); + + cscr = CSCR; + cscr &= ~CSCR_BCLK_DIV; + cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1); + CSCR = cscr; + + if(mpctl0) { + CSCR |= CSCR_MPLL_RESTART; + + /* Wait until MPLL is stabilized */ + while( CSCR & CSCR_MPLL_RESTART ); + + imx_set_async_mode(); + } + + local_irq_restore(flags); + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n", + freq, mpctl0? "MPLL": "SPLL"); + + return 0; +} + +static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy) +{ + printk(KERN_INFO "i.MX cpu freq change driver v1.0\n"); + + if (policy->cpu != 0) + return -EINVAL; + + policy->cur = policy->min = policy->max = imx_get_speed(0); + policy->cpuinfo.min_freq = 8000; + policy->cpuinfo.max_freq = 200000; + /* Manual states, that PLL stabilizes in two CLK32 periods */ + policy->cpuinfo.transition_latency = 4 * 1000000000LL / CLK32; + return 0; +} + +static struct cpufreq_driver imx_driver = { + .flags = CPUFREQ_STICKY, + .verify = imx_verify_speed, + .target = imx_set_target, + .get = imx_get_speed, + .init = imx_cpufreq_driver_init, + .name = "imx", +}; + +static int __init imx_cpufreq_init(void) +{ + bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1; + mpctl0_at_boot = 0; + + system_clk = clk_get(NULL, "system_clk"); + if (IS_ERR(system_clk)) + return PTR_ERR(system_clk); + + mcu_clk = clk_get(NULL, "mcu_clk"); + if (IS_ERR(mcu_clk)) { + clk_put(system_clk); + return PTR_ERR(mcu_clk); + } + + if((CSCR & CSCR_MPEN) && + ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE)) + mpctl0_at_boot = MPCTL0; + + return cpufreq_register_driver(&imx_driver); +} + +arch_initcall(imx_cpufreq_init); + diff --git a/trunk/arch/arm/mach-imx/dma.c b/trunk/arch/arm/mach-imx/dma.c new file mode 100644 index 000000000000..1536583eece0 --- /dev/null +++ b/trunk/arch/arm/mach-imx/dma.c @@ -0,0 +1,597 @@ +/* + * linux/arch/arm/mach-imx/dma.c + * + * imx DMA registration and IRQ dispatching + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * 2004-03-03 Sascha Hauer + * initial version heavily inspired by + * linux/arch/arm/mach-pxa/dma.c + * + * 2005-04-17 Pavel Pisa + * Changed to support scatter gather DMA + * by taking Russell's code from RiscPC + * + * 2006-05-31 Pavel Pisa + * Corrected error handling code. + * + */ + +#undef DEBUG + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; + +/* + * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation + * @dma_ch: i.MX DMA channel number + * @lastcount: number of bytes transferred during last transfer + * + * Functions prepares DMA controller for next sg data chunk transfer. + * The @lastcount argument informs function about number of bytes transferred + * during last block. Zero value can be used for @lastcount to setup DMA + * for the first chunk. + */ +static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + unsigned int nextcount; + unsigned int nextaddr; + + if (!imxdma->name) { + printk(KERN_CRIT "%s: called for not allocated channel %d\n", + __func__, dma_ch); + return 0; + } + + imxdma->resbytes -= lastcount; + + if (!imxdma->sg) { + pr_debug("imxdma%d: no sg data\n", dma_ch); + return 0; + } + + imxdma->sgbc += lastcount; + if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) { + if ((imxdma->sgcount <= 1) || !imxdma->resbytes) { + pr_debug("imxdma%d: sg transfer limit reached\n", + dma_ch); + imxdma->sgcount=0; + imxdma->sg = NULL; + return 0; + } else { + imxdma->sgcount--; + imxdma->sg++; + imxdma->sgbc = 0; + } + } + nextcount = imxdma->sg->length - imxdma->sgbc; + nextaddr = imxdma->sg->dma_address + imxdma->sgbc; + + if(imxdma->resbytes < nextcount) + nextcount = imxdma->resbytes; + + if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) + DAR(dma_ch) = nextaddr; + else + SAR(dma_ch) = nextaddr; + + CNTR(dma_ch) = nextcount; + pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n", + dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch)); + + return nextcount; +} + +/* + * imx_dma_setup_sg_base - scatter-gather DMA emulation + * @dma_ch: i.MX DMA channel number + * @sg: pointer to the scatter-gather list/vector + * @sgcount: scatter-gather list hungs count + * + * Functions sets up i.MX DMA state for emulated scatter-gather transfer + * and sets up channel registers to be ready for the first chunk + */ +static int +imx_dma_setup_sg_base(imx_dmach_t dma_ch, + struct scatterlist *sg, unsigned int sgcount) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + + imxdma->sg = sg; + imxdma->sgcount = sgcount; + imxdma->sgbc = 0; + return imx_dma_sg_next(dma_ch, 0); +} + +/** + * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer + * @dma_ch: i.MX DMA channel number + * @dma_address: the DMA/physical memory address of the linear data block + * to transfer + * @dma_length: length of the data block in bytes + * @dev_addr: physical device port address + * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory + * or %DMA_MODE_WRITE from memory to the device + * + * The function setups DMA channel source and destination addresses for transfer + * specified by provided parameters. The scatter-gather emulation is disabled, + * because linear data block + * form the physical address range is transferred. + * Return value: if incorrect parameters are provided -%EINVAL. + * Zero indicates success. + */ +int +imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, + unsigned int dma_length, unsigned int dev_addr, + unsigned int dmamode) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + + imxdma->sg = NULL; + imxdma->sgcount = 0; + imxdma->dma_mode = dmamode; + imxdma->resbytes = dma_length; + + if (!dma_address) { + printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n", + dma_ch); + return -EINVAL; + } + + if (!dma_length) { + printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n", + dma_ch); + return -EINVAL; + } + + if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { + pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n", + dma_ch, (unsigned int)dma_address, dma_length, + dev_addr); + SAR(dma_ch) = dev_addr; + DAR(dma_ch) = (unsigned int)dma_address; + } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { + pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n", + dma_ch, (unsigned int)dma_address, dma_length, + dev_addr); + SAR(dma_ch) = (unsigned int)dma_address; + DAR(dma_ch) = dev_addr; + } else { + printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", + dma_ch); + return -EINVAL; + } + + CNTR(dma_ch) = dma_length; + + return 0; +} + +/** + * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer + * @dma_ch: i.MX DMA channel number + * @sg: pointer to the scatter-gather list/vector + * @sgcount: scatter-gather list hungs count + * @dma_length: total length of the transfer request in bytes + * @dev_addr: physical device port address + * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory + * or %DMA_MODE_WRITE from memory to the device + * + * The function sets up DMA channel state and registers to be ready for transfer + * specified by provided parameters. The scatter-gather emulation is set up + * according to the parameters. + * + * The full preparation of the transfer requires setup of more register + * by the caller before imx_dma_enable() can be called. + * + * %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes + * + * %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx + * + * %CCR(dma_ch) has to specify transfer parameters, the next settings is typical + * for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified + * + * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x + * + * The typical setup for %DMA_MODE_WRITE is specified by next options combination + * + * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x + * + * Be careful here and do not mistakenly mix source and target device + * port sizes constants, they are really different: + * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, + * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 + * + * Return value: if incorrect parameters are provided -%EINVAL. + * Zero indicates success. + */ +int +imx_dma_setup_sg(imx_dmach_t dma_ch, + struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, + unsigned int dev_addr, unsigned int dmamode) +{ + int res; + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + + imxdma->sg = NULL; + imxdma->sgcount = 0; + imxdma->dma_mode = dmamode; + imxdma->resbytes = dma_length; + + if (!sg || !sgcount) { + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n", + dma_ch); + return -EINVAL; + } + + if (!sg->length) { + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n", + dma_ch); + return -EINVAL; + } + + if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { + pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n", + dma_ch, sg, sgcount, dma_length, dev_addr); + SAR(dma_ch) = dev_addr; + } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { + pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n", + dma_ch, sg, sgcount, dma_length, dev_addr); + DAR(dma_ch) = dev_addr; + } else { + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", + dma_ch); + return -EINVAL; + } + + res = imx_dma_setup_sg_base(dma_ch, sg, sgcount); + if (res <= 0) { + printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch); + return -EINVAL; + } + + return 0; +} + +/** + * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers + * @dma_ch: i.MX DMA channel number + * @irq_handler: the pointer to the function called if the transfer + * ends successfully + * @err_handler: the pointer to the function called if the premature + * end caused by error occurs + * @data: user specified value to be passed to the handlers + */ +int +imx_dma_setup_handlers(imx_dmach_t dma_ch, + void (*irq_handler) (int, void *), + void (*err_handler) (int, void *, int), + void *data) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + unsigned long flags; + + if (!imxdma->name) { + printk(KERN_CRIT "%s: called for not allocated channel %d\n", + __func__, dma_ch); + return -ENODEV; + } + + local_irq_save(flags); + DISR = (1 << dma_ch); + imxdma->irq_handler = irq_handler; + imxdma->err_handler = err_handler; + imxdma->data = data; + local_irq_restore(flags); + return 0; +} + +/** + * imx_dma_enable - function to start i.MX DMA channel operation + * @dma_ch: i.MX DMA channel number + * + * The channel has to be allocated by driver through imx_dma_request() + * or imx_dma_request_by_prio() function. + * The transfer parameters has to be set to the channel registers through + * call of the imx_dma_setup_single() or imx_dma_setup_sg() function + * and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to + * be set prior this function call by the channel user. + */ +void imx_dma_enable(imx_dmach_t dma_ch) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + unsigned long flags; + + pr_debug("imxdma%d: imx_dma_enable\n", dma_ch); + + if (!imxdma->name) { + printk(KERN_CRIT "%s: called for not allocated channel %d\n", + __func__, dma_ch); + return; + } + + local_irq_save(flags); + DISR = (1 << dma_ch); + DIMR &= ~(1 << dma_ch); + CCR(dma_ch) |= CCR_CEN; + local_irq_restore(flags); +} + +/** + * imx_dma_disable - stop, finish i.MX DMA channel operatin + * @dma_ch: i.MX DMA channel number + */ +void imx_dma_disable(imx_dmach_t dma_ch) +{ + unsigned long flags; + + pr_debug("imxdma%d: imx_dma_disable\n", dma_ch); + + local_irq_save(flags); + DIMR |= (1 << dma_ch); + CCR(dma_ch) &= ~CCR_CEN; + DISR = (1 << dma_ch); + local_irq_restore(flags); +} + +/** + * imx_dma_request - request/allocate specified channel number + * @dma_ch: i.MX DMA channel number + * @name: the driver/caller own non-%NULL identification + */ +int imx_dma_request(imx_dmach_t dma_ch, const char *name) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + unsigned long flags; + + /* basic sanity checks */ + if (!name) + return -EINVAL; + + if (dma_ch >= IMX_DMA_CHANNELS) { + printk(KERN_CRIT "%s: called for non-existed channel %d\n", + __func__, dma_ch); + return -EINVAL; + } + + local_irq_save(flags); + if (imxdma->name) { + local_irq_restore(flags); + return -ENODEV; + } + + imxdma->name = name; + imxdma->irq_handler = NULL; + imxdma->err_handler = NULL; + imxdma->data = NULL; + imxdma->sg = NULL; + local_irq_restore(flags); + return 0; +} + +/** + * imx_dma_free - release previously acquired channel + * @dma_ch: i.MX DMA channel number + */ +void imx_dma_free(imx_dmach_t dma_ch) +{ + unsigned long flags; + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + + if (!imxdma->name) { + printk(KERN_CRIT + "%s: trying to free channel %d which is already freed\n", + __func__, dma_ch); + return; + } + + local_irq_save(flags); + /* Disable interrupts */ + DIMR |= (1 << dma_ch); + CCR(dma_ch) &= ~CCR_CEN; + imxdma->name = NULL; + local_irq_restore(flags); +} + +/** + * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority + * @name: the driver/caller own non-%NULL identification + * @prio: one of the hardware distinguished priority level: + * %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW + * + * This function tries to find free channel in the specified priority group + * if the priority cannot be achieved it tries to look for free channel + * in the higher and then even lower priority groups. + * + * Return value: If there is no free channel to allocate, -%ENODEV is returned. + * On successful allocation channel is returned. + */ +imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio) +{ + int i; + int best; + + switch (prio) { + case (DMA_PRIO_HIGH): + best = 8; + break; + case (DMA_PRIO_MEDIUM): + best = 4; + break; + case (DMA_PRIO_LOW): + default: + best = 0; + break; + } + + for (i = best; i < IMX_DMA_CHANNELS; i++) { + if (!imx_dma_request(i, name)) { + return i; + } + } + + for (i = best - 1; i >= 0; i--) { + if (!imx_dma_request(i, name)) { + return i; + } + } + + printk(KERN_ERR "%s: no free DMA channel found\n", __func__); + + return -ENODEV; +} + +static irqreturn_t dma_err_handler(int irq, void *dev_id) +{ + int i, disr = DISR; + struct imx_dma_channel *channel; + unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR; + int errcode; + + DISR = disr & err_mask; + for (i = 0; i < IMX_DMA_CHANNELS; i++) { + if(!(err_mask & (1 << i))) + continue; + channel = &imx_dma_channels[i]; + errcode = 0; + + if (DBTOSR & (1 << i)) { + DBTOSR = (1 << i); + errcode |= IMX_DMA_ERR_BURST; + } + if (DRTOSR & (1 << i)) { + DRTOSR = (1 << i); + errcode |= IMX_DMA_ERR_REQUEST; + } + if (DSESR & (1 << i)) { + DSESR = (1 << i); + errcode |= IMX_DMA_ERR_TRANSFER; + } + if (DBOSR & (1 << i)) { + DBOSR = (1 << i); + errcode |= IMX_DMA_ERR_BUFFER; + } + + /* + * The cleaning of @sg field would be questionable + * there, because its value can help to compute + * remaining/transferred bytes count in the handler + */ + /*imx_dma_channels[i].sg = NULL;*/ + + if (channel->name && channel->err_handler) { + channel->err_handler(i, channel->data, errcode); + continue; + } + + imx_dma_channels[i].sg = NULL; + + printk(KERN_WARNING + "DMA timeout on channel %d (%s) -%s%s%s%s\n", + i, channel->name, + errcode&IMX_DMA_ERR_BURST? " burst":"", + errcode&IMX_DMA_ERR_REQUEST? " request":"", + errcode&IMX_DMA_ERR_TRANSFER? " transfer":"", + errcode&IMX_DMA_ERR_BUFFER? " buffer":""); + } + return IRQ_HANDLED; +} + +static irqreturn_t dma_irq_handler(int irq, void *dev_id) +{ + int i, disr = DISR; + + pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", + disr); + + DISR = disr; + for (i = 0; i < IMX_DMA_CHANNELS; i++) { + if (disr & (1 << i)) { + struct imx_dma_channel *channel = &imx_dma_channels[i]; + if (channel->name) { + if (imx_dma_sg_next(i, CNTR(i))) { + CCR(i) &= ~CCR_CEN; + mb(); + CCR(i) |= CCR_CEN; + } else { + if (channel->irq_handler) + channel->irq_handler(i, + channel->data); + } + } else { + /* + * IRQ for an unregistered DMA channel: + * let's clear the interrupts and disable it. + */ + printk(KERN_WARNING + "spurious IRQ for DMA channel %d\n", i); + } + } + } + return IRQ_HANDLED; +} + +static int __init imx_dma_init(void) +{ + int ret; + int i; + + /* reset DMA module */ + DCR = DCR_DRST; + + ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); + if (ret) { + printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); + return ret; + } + + ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL); + if (ret) { + printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n"); + free_irq(DMA_INT, NULL); + } + + /* enable DMA module */ + DCR = DCR_DEN; + + /* clear all interrupts */ + DISR = (1 << IMX_DMA_CHANNELS) - 1; + + /* enable interrupts */ + DIMR = (1 << IMX_DMA_CHANNELS) - 1; + + for (i = 0; i < IMX_DMA_CHANNELS; i++) { + imx_dma_channels[i].sg = NULL; + imx_dma_channels[i].dma_num = i; + } + + return ret; +} + +arch_initcall(imx_dma_init); + +EXPORT_SYMBOL(imx_dma_setup_single); +EXPORT_SYMBOL(imx_dma_setup_sg); +EXPORT_SYMBOL(imx_dma_setup_handlers); +EXPORT_SYMBOL(imx_dma_enable); +EXPORT_SYMBOL(imx_dma_disable); +EXPORT_SYMBOL(imx_dma_request); +EXPORT_SYMBOL(imx_dma_free); +EXPORT_SYMBOL(imx_dma_request_by_prio); +EXPORT_SYMBOL(imx_dma_channels); diff --git a/trunk/arch/arm/mach-imx/generic.c b/trunk/arch/arm/mach-imx/generic.c new file mode 100644 index 000000000000..05f1739ee127 --- /dev/null +++ b/trunk/arch/arm/mach-imx/generic.c @@ -0,0 +1,271 @@ +/* + * arch/arm/mach-imx/generic.c + * + * author: Sascha Hauer + * Created: april 20th, 2004 + * Copyright: Synertronixx GmbH + * + * Common code for i.MX machines + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +unsigned long imx_gpio_alloc_map[(GPIO_PORT_MAX + 1) * 32 / BITS_PER_LONG]; + +void imx_gpio_mode(int gpio_mode) +{ + unsigned int pin = gpio_mode & GPIO_PIN_MASK; + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; + unsigned int tmp; + + /* Pullup enable */ + if(gpio_mode & GPIO_PUEN) + PUEN(port) |= (1<> GPIO_AOUT_SHIFT) & 3) << (pin * 2); + ICONFB1(port) &= ~( 3<<(pin*2)); + ICONFB1(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2); + } else { + tmp = OCR2(port); + tmp &= ~( 3<<((pin-16)*2)); + tmp |= (ocr << ((pin-16)*2)); + OCR2(port) = tmp; + + ICONFA2(port) &= ~( 3<<((pin-16)*2)); + ICONFA2(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << ((pin-16) * 2); + ICONFB2(port) &= ~( 3<<((pin-16)*2)); + ICONFB2(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << ((pin-16) * 2); + } +} + +EXPORT_SYMBOL(imx_gpio_mode); + +int imx_gpio_request(unsigned gpio, const char *label) +{ + if(gpio >= (GPIO_PORT_MAX + 1) * 32) { + printk(KERN_ERR "imx_gpio: Attempt to request nonexistent GPIO %d for \"%s\"\n", + gpio, label ? label : "?"); + return -EINVAL; + } + + if(test_and_set_bit(gpio, imx_gpio_alloc_map)) { + printk(KERN_ERR "imx_gpio: GPIO %d already used. Allocation for \"%s\" failed\n", + gpio, label ? label : "?"); + return -EBUSY; + } + + return 0; +} + +EXPORT_SYMBOL(imx_gpio_request); + +void imx_gpio_free(unsigned gpio) +{ + if(gpio >= (GPIO_PORT_MAX + 1) * 32) + return; + + clear_bit(gpio, imx_gpio_alloc_map); +} + +EXPORT_SYMBOL(imx_gpio_free); + +int imx_gpio_direction_input(unsigned gpio) +{ + imx_gpio_mode(gpio | GPIO_IN | GPIO_GIUS | GPIO_DR); + return 0; +} + +EXPORT_SYMBOL(imx_gpio_direction_input); + +int imx_gpio_direction_output(unsigned gpio, int value) +{ + imx_gpio_set_value(gpio, value); + imx_gpio_mode(gpio | GPIO_OUT | GPIO_GIUS | GPIO_DR); + return 0; +} + +EXPORT_SYMBOL(imx_gpio_direction_output); + +int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + int alloc_mode, const char *label) +{ + const int *p = pin_list; + int i; + unsigned gpio; + unsigned mode; + + for (i = 0; i < count; i++) { + gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); + mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK); + + if (gpio >= (GPIO_PORT_MAX + 1) * 32) + goto setup_error; + + if (alloc_mode & IMX_GPIO_ALLOC_MODE_RELEASE) + imx_gpio_free(gpio); + else if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_NO_ALLOC)) + if (imx_gpio_request(gpio, label)) + if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) + goto setup_error; + + if (!(alloc_mode & (IMX_GPIO_ALLOC_MODE_ALLOC_ONLY | + IMX_GPIO_ALLOC_MODE_RELEASE))) + imx_gpio_mode(gpio | mode); + + p++; + } + return 0; + +setup_error: + if(alloc_mode & (IMX_GPIO_ALLOC_MODE_NO_ALLOC | + IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) + return -EINVAL; + + while (p != pin_list) { + p--; + gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); + imx_gpio_free(gpio); + } + + return -EINVAL; +} + +EXPORT_SYMBOL(imx_gpio_setup_multiple_pins); + +void __imx_gpio_set_value(unsigned gpio, int value) +{ + imx_gpio_set_value_inline(gpio, value); +} + +EXPORT_SYMBOL(__imx_gpio_set_value); + +int imx_gpio_to_irq(unsigned gpio) +{ + return IRQ_GPIOA(0) + gpio; +} + +EXPORT_SYMBOL(imx_gpio_to_irq); + +int imx_irq_to_gpio(unsigned irq) +{ + if (irq < IRQ_GPIOA(0)) + return -EINVAL; + return irq - IRQ_GPIOA(0); +} + +EXPORT_SYMBOL(imx_irq_to_gpio); + +static struct resource imx_mmc_resources[] = { + [0] = { + .start = 0x00214000, + .end = 0x002140FF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = (SDHC_INT), + .end = (SDHC_INT), + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 imxmmmc_dmamask = 0xffffffffUL; + +static struct platform_device imx_mmc_device = { + .name = "imx-mmc", + .id = 0, + .dev = { + .dma_mask = &imxmmmc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(imx_mmc_resources), + .resource = imx_mmc_resources, +}; + +void __init imx_set_mmc_info(struct imxmmc_platform_data *info) +{ + imx_mmc_device.dev.platform_data = info; +} + +static struct platform_device *devices[] __initdata = { + &imx_mmc_device, +}; + +static struct map_desc imx_io_desc[] __initdata = { + { + .virtual = IMX_IO_BASE, + .pfn = __phys_to_pfn(IMX_IO_PHYS), + .length = IMX_IO_SIZE, + .type = MT_DEVICE + } +}; + +void __init +imx_map_io(void) +{ + iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); +} + +static int __init imx_init(void) +{ + return platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +subsys_initcall(imx_init); diff --git a/trunk/arch/arm/mach-imx/generic.h b/trunk/arch/arm/mach-imx/generic.h new file mode 100644 index 000000000000..e91003e4bef3 --- /dev/null +++ b/trunk/arch/arm/mach-imx/generic.h @@ -0,0 +1,16 @@ +/* + * linux/arch/arm/mach-imx/generic.h + * + * Author: Sascha Hauer + * Copyright: Synertronixx GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +extern void __init imx_map_io(void); +extern void __init imx_init_irq(void); + +struct sys_timer; +extern struct sys_timer imx_timer; diff --git a/trunk/arch/arm/mach-imx/include/mach/debug-macro.S b/trunk/arch/arm/mach-imx/include/mach/debug-macro.S new file mode 100644 index 000000000000..87802bbfe633 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/debug-macro.S @@ -0,0 +1,34 @@ +/* arch/arm/mach-imx/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x00000000 @ physical + movne \rx, #0xe0000000 @ virtual + orreq \rx, \rx, #0x00200000 @ physical + orr \rx, \rx, #0x00006000 @ UART1 offset + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #0x40] @ TXDATA + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #0x98] @ SR2 + tst \rd, #1 << 3 @ TXDC + beq 1002b @ wait until transmit done + .endm diff --git a/trunk/arch/arm/mach-imx/include/mach/dma.h b/trunk/arch/arm/mach-imx/include/mach/dma.h new file mode 100644 index 000000000000..621ff2c730f2 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/dma.h @@ -0,0 +1,56 @@ +/* + * linux/include/asm-arm/imxads/dma.h + * + * Copyright (C) 1997,1998 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +typedef enum { + DMA_PRIO_HIGH = 0, + DMA_PRIO_MEDIUM = 1, + DMA_PRIO_LOW = 2 +} imx_dma_prio; + +#define DMA_REQ_UART3_T 2 +#define DMA_REQ_UART3_R 3 +#define DMA_REQ_SSI2_T 4 +#define DMA_REQ_SSI2_R 5 +#define DMA_REQ_CSI_STAT 6 +#define DMA_REQ_CSI_R 7 +#define DMA_REQ_MSHC 8 +#define DMA_REQ_DSPA_DCT_DOUT 9 +#define DMA_REQ_DSPA_DCT_DIN 10 +#define DMA_REQ_DSPA_MAC 11 +#define DMA_REQ_EXT 12 +#define DMA_REQ_SDHC 13 +#define DMA_REQ_SPI1_R 14 +#define DMA_REQ_SPI1_T 15 +#define DMA_REQ_SSI_T 16 +#define DMA_REQ_SSI_R 17 +#define DMA_REQ_ASP_DAC 18 +#define DMA_REQ_ASP_ADC 19 +#define DMA_REQ_USP_EP(x) (20+(x)) +#define DMA_REQ_SPI2_R 26 +#define DMA_REQ_SPI2_T 27 +#define DMA_REQ_UART2_T 28 +#define DMA_REQ_UART2_R 29 +#define DMA_REQ_UART1_T 30 +#define DMA_REQ_UART1_R 31 + +#endif /* _ASM_ARCH_DMA_H */ diff --git a/trunk/arch/arm/mach-imx/include/mach/entry-macro.S b/trunk/arch/arm/mach-imx/include/mach/entry-macro.S new file mode 100644 index 000000000000..e4db679f7766 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/entry-macro.S @@ -0,0 +1,32 @@ +/* + * arch/arm/mach-imx/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for iMX-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + +#define AITC_NIVECSR 0x40 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =IO_ADDRESS(IMX_AITC_BASE) + @ Load offset & priority of the highest priority + @ interrupt pending. + ldr \irqstat, [\base, #AITC_NIVECSR] + @ Shift off the priority leaving the offset or + @ "interrupt number", use arithmetic shift to + @ transform illegal source (0xffff) as -1 + mov \irqnr, \irqstat, asr #16 + adds \tmp, \irqnr, #1 + .endm diff --git a/trunk/arch/arm/mach-imx/include/mach/gpio.h b/trunk/arch/arm/mach-imx/include/mach/gpio.h new file mode 100644 index 000000000000..6c2942f82922 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/gpio.h @@ -0,0 +1,106 @@ +#ifndef _IMX_GPIO_H + +#include +#include +#include + +#define IMX_GPIO_ALLOC_MODE_NORMAL 0 +#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1 +#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2 +#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4 +#define IMX_GPIO_ALLOC_MODE_RELEASE 8 + +extern int imx_gpio_request(unsigned gpio, const char *label); + +extern void imx_gpio_free(unsigned gpio); + +extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + int alloc_mode, const char *label); + +extern int imx_gpio_direction_input(unsigned gpio); + +extern int imx_gpio_direction_output(unsigned gpio, int value); + +extern void __imx_gpio_set_value(unsigned gpio, int value); + +static inline int imx_gpio_get_value(unsigned gpio) +{ + return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK)); +} + +static inline void imx_gpio_set_value_inline(unsigned gpio, int value) +{ + unsigned long flags; + + raw_local_irq_save(flags); + if(value) + DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK)); + else + DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK)); + raw_local_irq_restore(flags); +} + +static inline void imx_gpio_set_value(unsigned gpio, int value) +{ + if(__builtin_constant_p(gpio)) + imx_gpio_set_value_inline(gpio, value); + else + __imx_gpio_set_value(gpio, value); +} + +extern int imx_gpio_to_irq(unsigned gpio); + +extern int imx_irq_to_gpio(unsigned irq); + +/*-------------------------------------------------------------------------*/ + +/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions + * to allow future extension of GPIO logic. + */ + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return imx_gpio_request(gpio, label); +} + +static inline void gpio_free(unsigned gpio) +{ + might_sleep(); + + imx_gpio_free(gpio); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return imx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return imx_gpio_direction_output(gpio, value); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return imx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + imx_gpio_set_value(gpio, value); +} + +#include /* cansleep wrappers */ + +static inline int gpio_to_irq(unsigned gpio) +{ + return imx_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + return imx_irq_to_gpio(irq); +} + + +#endif diff --git a/trunk/arch/arm/mach-imx/include/mach/hardware.h b/trunk/arch/arm/mach-imx/include/mach/hardware.h new file mode 100644 index 000000000000..c73e9e724c75 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/hardware.h @@ -0,0 +1,91 @@ +/* + * arch/arm/mach-imx/include/mach/hardware.h + * + * Copyright (C) 1999 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include +#include "imx-regs.h" + +#ifndef __ASSEMBLY__ +# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) + +# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) +#endif + +/* + * Memory map + */ + +#define IMX_IO_PHYS 0x00200000 +#define IMX_IO_SIZE 0x00100000 +#define IMX_IO_BASE 0xe0000000 + +#define IMX_CS0_PHYS 0x10000000 +#define IMX_CS0_SIZE 0x02000000 +#define IMX_CS0_VIRT 0xe8000000 + +#define IMX_CS1_PHYS 0x12000000 +#define IMX_CS1_SIZE 0x01000000 +#define IMX_CS1_VIRT 0xea000000 + +#define IMX_CS2_PHYS 0x13000000 +#define IMX_CS2_SIZE 0x01000000 +#define IMX_CS2_VIRT 0xeb000000 + +#define IMX_CS3_PHYS 0x14000000 +#define IMX_CS3_SIZE 0x01000000 +#define IMX_CS3_VIRT 0xec000000 + +#define IMX_CS4_PHYS 0x15000000 +#define IMX_CS4_SIZE 0x01000000 +#define IMX_CS4_VIRT 0xed000000 + +#define IMX_CS5_PHYS 0x16000000 +#define IMX_CS5_SIZE 0x01000000 +#define IMX_CS5_VIRT 0xee000000 + +#define IMX_FB_VIRT 0xF1000000 +#define IMX_FB_SIZE (256*1024) + +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) ((x) | IMX_IO_BASE) + +#ifndef __ASSEMBLY__ +/* + * Handy routine to set GPIO functions + */ +extern void imx_gpio_mode( int gpio_mode ); + +#endif + +#define MAXIRQNUM 62 +#define MAXFIQNUM 62 +#define MAXSWINUM 62 + +/* + * Use SDRAM for memory + */ +#define MEM_SIZE 0x01000000 + +#ifdef CONFIG_ARCH_MX1ADS +#include "mx1ads.h" +#endif + +#endif diff --git a/trunk/arch/arm/mach-imx/include/mach/imx-dma.h b/trunk/arch/arm/mach-imx/include/mach/imx-dma.h new file mode 100644 index 000000000000..bbe54df7f0de --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/imx-dma.h @@ -0,0 +1,98 @@ +/* + * linux/include/asm-arm/imxads/dma.h + * + * Copyright (C) 1997,1998 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include + +#ifndef __ASM_ARCH_IMX_DMA_H +#define __ASM_ARCH_IMX_DMA_H + +#define IMX_DMA_CHANNELS 11 + +/* + * struct imx_dma_channel - i.MX specific DMA extension + * @name: name specified by DMA client + * @irq_handler: client callback for end of transfer + * @err_handler: client callback for error condition + * @data: clients context data for callbacks + * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE + * @sg: pointer to the actual read/written chunk for scatter-gather emulation + * @sgbc: counter of processed bytes in the actual read/written chunk + * @resbytes: total residual number of bytes to transfer + * (it can be lower or same as sum of SG mapped chunk sizes) + * @sgcount: number of chunks to be read/written + * + * Structure is used for IMX DMA processing. It would be probably good + * @struct dma_struct in the future for external interfacing and use + * @struct imx_dma_channel only as extension to it. + */ + +struct imx_dma_channel { + const char *name; + void (*irq_handler) (int, void *); + void (*err_handler) (int, void *, int errcode); + void *data; + unsigned int dma_mode; + struct scatterlist *sg; + unsigned int sgbc; + unsigned int sgcount; + unsigned int resbytes; + int dma_num; +}; + +extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; + +#define IMX_DMA_ERR_BURST 1 +#define IMX_DMA_ERR_REQUEST 2 +#define IMX_DMA_ERR_TRANSFER 4 +#define IMX_DMA_ERR_BUFFER 8 + +/* The type to distinguish channel numbers parameter from ordinal int type */ +typedef int imx_dmach_t; + +#define DMA_MODE_READ 0 +#define DMA_MODE_WRITE 1 +#define DMA_MODE_MASK 1 + +int +imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, + unsigned int dma_length, unsigned int dev_addr, unsigned int dmamode); + +int +imx_dma_setup_sg(imx_dmach_t dma_ch, + struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, + unsigned int dev_addr, unsigned int dmamode); + +int +imx_dma_setup_handlers(imx_dmach_t dma_ch, + void (*irq_handler) (int, void *), + void (*err_handler) (int, void *, int), void *data); + +void imx_dma_enable(imx_dmach_t dma_ch); + +void imx_dma_disable(imx_dmach_t dma_ch); + +int imx_dma_request(imx_dmach_t dma_ch, const char *name); + +void imx_dma_free(imx_dmach_t dma_ch); + +imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio); + + +#endif /* _ASM_ARCH_IMX_DMA_H */ diff --git a/trunk/arch/arm/mach-imx/include/mach/imx-regs.h b/trunk/arch/arm/mach-imx/include/mach/imx-regs.h new file mode 100644 index 000000000000..490297fc0e38 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/imx-regs.h @@ -0,0 +1,376 @@ +#ifndef _IMX_REGS_H +#define _IMX_REGS_H +/* ------------------------------------------------------------------------ + * Motorola IMX system registers + * ------------------------------------------------------------------------ + * + */ + +/* + * Register BASEs, based on OFFSETs + * + */ +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) +#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) +#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) +#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) +#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) +#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) +#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) +#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) +#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) +#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) +#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) +#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) +#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) +#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) +#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) +#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) +#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) +#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) +#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) +#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) +#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) +#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) + +/* PLL registers */ +#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ +#define CSCR_SPLL_RESTART (1<<22) +#define CSCR_MPLL_RESTART (1<<21) +#define CSCR_SYSTEM_SEL (1<<16) +#define CSCR_BCLK_DIV (0xf<<10) +#define CSCR_MPU_PRESC (1<<15) +#define CSCR_SPEN (1<<1) +#define CSCR_MPEN (1<<0) + +#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ +#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ +#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ + +/* + * GPIO Module and I/O Multiplexer + * x = 0..3 for reg_A, reg_B, reg_C, reg_D + */ +#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) +#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) +#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) +#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) +#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) +#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) +#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) +#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) +#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) +#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) +#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) +#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) +#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) +#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) +#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) +#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) +#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) + +#define GPIO_PORT_MAX 3 + +#define GPIO_PIN_MASK 0x1f +#define GPIO_PORT_MASK (0x3 << 5) + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORTA (0<<5) +#define GPIO_PORTB (1<<5) +#define GPIO_PORTC (2<<5) +#define GPIO_PORTD (3<<5) + +#define GPIO_OUT (1<<7) +#define GPIO_IN (0<<7) +#define GPIO_PUEN (1<<8) + +#define GPIO_PF (0<<9) +#define GPIO_AF (1<<9) + +#define GPIO_OCR_SHIFT 10 +#define GPIO_OCR_MASK (3<<10) +#define GPIO_AIN (0<<10) +#define GPIO_BIN (1<<10) +#define GPIO_CIN (2<<10) +#define GPIO_DR (3<<10) + +#define GPIO_AOUT_SHIFT 12 +#define GPIO_AOUT_MASK (3<<12) +#define GPIO_AOUT (0<<12) +#define GPIO_AOUT_ISR (1<<12) +#define GPIO_AOUT_0 (2<<12) +#define GPIO_AOUT_1 (3<<12) + +#define GPIO_BOUT_SHIFT 14 +#define GPIO_BOUT_MASK (3<<14) +#define GPIO_BOUT (0<<14) +#define GPIO_BOUT_ISR (1<<14) +#define GPIO_BOUT_0 (2<<14) +#define GPIO_BOUT_1 (3<<14) + +#define GPIO_GIUS (1<<16) + +/* assignements for GPIO alternate/primary functions */ + +/* FIXME: This list is not completed. The correct directions are + * missing on some (many) pins + */ +#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) +#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) +#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) +#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) +#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) +#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) +#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) +#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) +#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) +#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) +#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) +#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) +#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) +#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) +#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) +#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) +#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) +#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) +#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) +#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) +#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) +#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) +#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) +#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) +#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) +#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) +#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) +#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) +#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) +#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) +#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) +#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) +#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) +#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) +#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) +#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) +#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) +#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) +#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) +#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) +#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) +#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) +#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) +#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) +#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) +#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) +#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) +#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) +#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) +#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) +#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) +#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) +#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) +#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) +#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) +#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) +#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) +#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) +#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) +#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) +#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) +#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) +#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) +#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) +#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) +#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) +#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) +#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) +#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) +#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) +#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) +#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) +#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) +#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) +#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) +#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) +#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) +#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) +#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) +#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) +#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) +#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) +#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) +#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) +#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) +#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) +#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) +#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) +#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) +#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) +#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) +#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) +#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) +#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) +#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) +#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) +#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) +#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) +#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) +#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) +#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) +#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) +#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) +#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) +#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) +#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) +#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) +#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) +#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) +#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) +#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) +#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) +#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) +#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) +#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) +#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) +#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) +#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) +#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) +#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) +#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) +#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) +#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) +#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) +#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) +#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) +#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) +#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) +#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) +#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) +#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) + +/* + * PWM controller + */ +#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ +#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ +#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ +#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ + +#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ +#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ +#define PWMC_SWR (0x01<<16) /* Software Reset */ +#define PWMC_CLKSRC (0x01<<15) /* Clock Source */ +#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ +#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ +#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ +#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ +#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ +#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ +#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ + +#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ +#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ +#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ + +/* + * DMA Controller + */ +#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ +#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ +#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ +#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ +#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ +#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ +#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ +#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ +#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ +#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ +#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ +#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ +#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ +#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ +#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ +#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ +#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ +#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ +#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ +#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ +#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ +#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ + +#define DCR_DRST (1<<1) +#define DCR_DEN (1<<0) +#define DBTOCR_EN (1<<15) +#define DBTOCR_CNT(x) ((x) & 0x7fff ) +#define CNTR_CNT(x) ((x) & 0xffffff ) +#define CCR_DMOD_LINEAR ( 0x0 << 12 ) +#define CCR_DMOD_2D ( 0x1 << 12 ) +#define CCR_DMOD_FIFO ( 0x2 << 12 ) +#define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) +#define CCR_SMOD_LINEAR ( 0x0 << 10 ) +#define CCR_SMOD_2D ( 0x1 << 10 ) +#define CCR_SMOD_FIFO ( 0x2 << 10 ) +#define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) +#define CCR_MDIR_DEC (1<<9) +#define CCR_MSEL_B (1<<8) +#define CCR_DSIZ_32 ( 0x0 << 6 ) +#define CCR_DSIZ_8 ( 0x1 << 6 ) +#define CCR_DSIZ_16 ( 0x2 << 6 ) +#define CCR_SSIZ_32 ( 0x0 << 4 ) +#define CCR_SSIZ_8 ( 0x1 << 4 ) +#define CCR_SSIZ_16 ( 0x2 << 4 ) +#define CCR_REN (1<<3) +#define CCR_RPT (1<<2) +#define CCR_FRC (1<<1) +#define CCR_CEN (1<<0) +#define RTOR_EN (1<<15) +#define RTOR_CLK (1<<14) +#define RTOR_PSC (1<<13) + +/* + * Interrupt controller + */ + +#define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00) +#define INTCNTL_FIAD (1<<19) +#define INTCNTL_NIAD (1<<20) + +#define IMX_NIMASK __REG(IMX_AITC_BASE+0x04) +#define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08) +#define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c) +#define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10) +#define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14) + +/* + * General purpose timers + */ +#define IMX_TCTL(x) __REG( 0x00 + (x)) +#define TCTL_SWR (1<<15) +#define TCTL_FRR (1<<8) +#define TCTL_CAP_RIS (1<<6) +#define TCTL_CAP_FAL (2<<6) +#define TCTL_CAP_RIS_FAL (3<<6) +#define TCTL_OM (1<<5) +#define TCTL_IRQEN (1<<4) +#define TCTL_CLK_PCLK1 (1<<1) +#define TCTL_CLK_PCLK1_16 (2<<1) +#define TCTL_CLK_TIN (3<<1) +#define TCTL_CLK_32 (4<<1) +#define TCTL_TEN (1<<0) + +#define IMX_TPRER(x) __REG( 0x04 + (x)) +#define IMX_TCMP(x) __REG( 0x08 + (x)) +#define IMX_TCR(x) __REG( 0x0C + (x)) +#define IMX_TCN(x) __REG( 0x10 + (x)) +#define IMX_TSTAT(x) __REG( 0x14 + (x)) +#define TSTAT_CAPT (1<<1) +#define TSTAT_COMP (1<<0) + +#endif // _IMX_REGS_H diff --git a/trunk/arch/arm/mach-imx/include/mach/imx-uart.h b/trunk/arch/arm/mach-imx/include/mach/imx-uart.h new file mode 100644 index 000000000000..d54eb1d48026 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/imx-uart.h @@ -0,0 +1,12 @@ +#ifndef ASMARM_ARCH_UART_H +#define ASMARM_ARCH_UART_H + +#define IMXUART_HAVE_RTSCTS (1<<0) + +struct imxuart_platform_data { + int (*init)(struct platform_device *pdev); + void (*exit)(struct platform_device *pdev); + unsigned int flags; +}; + +#endif diff --git a/trunk/arch/arm/plat-mxc/include/mach/board-pcm043.h b/trunk/arch/arm/mach-imx/include/mach/io.h similarity index 69% rename from trunk/arch/arm/plat-mxc/include/mach/board-pcm043.h rename to trunk/arch/arm/mach-imx/include/mach/io.h index 15fbdf16abcd..9e197ae4590f 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/board-pcm043.h +++ b/trunk/arch/arm/mach-imx/include/mach/io.h @@ -1,5 +1,7 @@ /* - * Copyright (C) 2008 Sascha Hauer, Pengutronix + * arch/arm/mach-imxads/include/mach/io.h + * + * Copyright (C) 1999 ARM Limited * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,13 +17,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H -#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__ -#define __ASM_ARCH_MXC_BOARD_PCM043_H__ - -/* mandatory for CONFIG_LL_DEBUG */ +#define IO_SPACE_LIMIT 0xffffffff -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) -#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */ +#endif diff --git a/trunk/arch/arm/mach-imx/include/mach/irqs.h b/trunk/arch/arm/mach-imx/include/mach/irqs.h new file mode 100644 index 000000000000..67812c5ac1f9 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/irqs.h @@ -0,0 +1,121 @@ +/* + * arch/arm/mach-imxads/include/mach/irqs.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARM_IRQS_H__ +#define __ARM_IRQS_H__ + +/* Use the imx definitions */ +#include + +/* + * IMX Interrupt numbers + * + */ +#define INT_SOFTINT 0 +#define CSI_INT 6 +#define DSPA_MAC_INT 7 +#define DSPA_INT 8 +#define COMP_INT 9 +#define MSHC_XINT 10 +#define GPIO_INT_PORTA 11 +#define GPIO_INT_PORTB 12 +#define GPIO_INT_PORTC 13 +#define LCDC_INT 14 +#define SIM_INT 15 +#define SIM_DATA_INT 16 +#define RTC_INT 17 +#define RTC_SAMINT 18 +#define UART2_MINT_PFERR 19 +#define UART2_MINT_RTS 20 +#define UART2_MINT_DTR 21 +#define UART2_MINT_UARTC 22 +#define UART2_MINT_TX 23 +#define UART2_MINT_RX 24 +#define UART1_MINT_PFERR 25 +#define UART1_MINT_RTS 26 +#define UART1_MINT_DTR 27 +#define UART1_MINT_UARTC 28 +#define UART1_MINT_TX 29 +#define UART1_MINT_RX 30 +#define VOICE_DAC_INT 31 +#define VOICE_ADC_INT 32 +#define PEN_DATA_INT 33 +#define PWM_INT 34 +#define SDHC_INT 35 +#define I2C_INT 39 +#define CSPI_INT 41 +#define SSI_TX_INT 42 +#define SSI_TX_ERR_INT 43 +#define SSI_RX_INT 44 +#define SSI_RX_ERR_INT 45 +#define TOUCH_INT 46 +#define USBD_INT0 47 +#define USBD_INT1 48 +#define USBD_INT2 49 +#define USBD_INT3 50 +#define USBD_INT4 51 +#define USBD_INT5 52 +#define USBD_INT6 53 +#define BTSYS_INT 55 +#define BTTIM_INT 56 +#define BTWUI_INT 57 +#define TIM2_INT 58 +#define TIM1_INT 59 +#define DMA_ERR 60 +#define DMA_INT 61 +#define GPIO_INT_PORTD 62 + +#define IMX_IRQS (64) + +/* note: the IMX has four gpio ports (A-D), but only + * the following pins are connected to the outside + * world: + * + * PORT A: bits 0-31 + * PORT B: bits 8-31 + * PORT C: bits 3-17 + * PORT D: bits 6-31 + * + * We map these interrupts straight on. As a result we have + * several holes in the interrupt mapping. We do this for two + * reasons: + * - mapping the interrupts without holes would get + * far more complicated + * - Motorola could well decide to bring some processor + * with more pins connected + */ + +#define IRQ_GPIOA(x) (IMX_IRQS + x) +#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) +#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) +#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) + +/* decode irq number to use with IMR(x), ISR(x) and friends */ +#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5) + +/* all normal IRQs can be FIQs */ +#define FIQ_START 0 +/* switch betwean IRQ and FIQ */ +extern int imx_set_irq_fiq(unsigned int irq, unsigned int type); + +#define NR_IRQS (IRQ_GPIOD(32) + 1) +#define IRQ_GPIO(x) +#endif diff --git a/trunk/arch/arm/mach-imx/include/mach/memory.h b/trunk/arch/arm/mach-imx/include/mach/memory.h new file mode 100644 index 000000000000..a93df7cba694 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/memory.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-imx/include/mach/memory.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MMU_H +#define __ASM_ARCH_MMU_H + +#define PHYS_OFFSET UL(0x08000000) + +#endif diff --git a/trunk/arch/arm/mach-imx/include/mach/mmc.h b/trunk/arch/arm/mach-imx/include/mach/mmc.h new file mode 100644 index 000000000000..4712f354dcca --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/mmc.h @@ -0,0 +1,15 @@ +#ifndef ASMARM_ARCH_MMC_H +#define ASMARM_ARCH_MMC_H + +#include + +struct device; + +struct imxmmc_platform_data { + int (*card_present)(struct device *); + int (*get_ro)(struct device *); +}; + +extern void imx_set_mmc_info(struct imxmmc_platform_data *info); + +#endif diff --git a/trunk/arch/arm/mach-imx/include/mach/mx1ads.h b/trunk/arch/arm/mach-imx/include/mach/mx1ads.h new file mode 100644 index 000000000000..def05d510eb3 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/mx1ads.h @@ -0,0 +1,36 @@ +/* + * arch/arm/mach-imx/include/mach/mx1ads.h + * + * Copyright (C) 2004 Robert Schwebel, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_MX1ADS_H +#define __ASM_ARCH_MX1ADS_H + +/* ------------------------------------------------------------------------ */ +/* Memory Map for the M9328MX1ADS (MX1ADS) Board */ +/* ------------------------------------------------------------------------ */ + +#define MX1ADS_FLASH_PHYS 0x10000000 +#define MX1ADS_FLASH_SIZE (16*1024*1024) + +#define IMX_FB_PHYS (0x0C000000 - 0x40000) + +#define CLK32 32000 + +#endif /* __ASM_ARCH_MX1ADS_H */ diff --git a/trunk/arch/arm/mach-imx/include/mach/spi_imx.h b/trunk/arch/arm/mach-imx/include/mach/spi_imx.h new file mode 100644 index 000000000000..4186430feecf --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/spi_imx.h @@ -0,0 +1,72 @@ +/* + * arch/arm/mach-imx/include/mach/spi_imx.h + * + * Copyright (C) 2006 SWAPP + * Andrea Paterniani + * + * Initial version inspired by: + * linux-2.6.17-rc3-mm1/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef SPI_IMX_H_ +#define SPI_IMX_H_ + + +/*-------------------------------------------------------------------------*/ +/** + * struct spi_imx_master - device.platform_data for SPI controller devices. + * @num_chipselect: chipselects are used to distinguish individual + * SPI slaves, and are numbered from zero to num_chipselects - 1. + * each slave has a chipselect signal, but it's common that not + * every chipselect is connected to a slave. + * @enable_dma: if true enables DMA driven transfers. +*/ +struct spi_imx_master { + u8 num_chipselect; + u8 enable_dma:1; +}; +/*-------------------------------------------------------------------------*/ + + +/*-------------------------------------------------------------------------*/ +/** + * struct spi_imx_chip - spi_board_info.controller_data for SPI + * slave devices, copied to spi_device.controller_data. + * @enable_loopback : used for test purpouse to internally connect RX and TX + * sections. + * @enable_dma : enables dma transfer (provided that controller driver has + * dma enabled too). + * @ins_ss_pulse : enable /SS pulse insertion between SPI burst. + * @bclk_wait : number of bclk waits between each bits_per_word SPI burst. + * @cs_control : function pointer to board-specific function to assert/deassert + * I/O port to control HW generation of devices chip-select. +*/ +struct spi_imx_chip { + u8 enable_loopback:1; + u8 enable_dma:1; + u8 ins_ss_pulse:1; + u16 bclk_wait:15; + void (*cs_control)(u32 control); +}; + +/* Chip-select state */ +#define SPI_CS_ASSERT (1 << 0) +#define SPI_CS_DEASSERT (1 << 1) +/*-------------------------------------------------------------------------*/ + + +#endif /* SPI_IMX_H_*/ diff --git a/trunk/arch/arm/mach-imx/include/mach/system.h b/trunk/arch/arm/mach-imx/include/mach/system.h new file mode 100644 index 000000000000..46d4ca91af79 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/system.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-imxads/include/mach/system.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static void +arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void +arch_reset(char mode, const char *cmd) +{ + cpu_reset(0); +} + +#endif diff --git a/trunk/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/trunk/arch/arm/mach-imx/include/mach/timex.h similarity index 68% rename from trunk/arch/arm/plat-mxc/include/mach/board-mx35pdk.h rename to trunk/arch/arm/mach-imx/include/mach/timex.h index 1111037d6d9d..e22ba789546c 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/board-mx35pdk.h +++ b/trunk/arch/arm/mach-imx/include/mach/timex.h @@ -1,5 +1,7 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved + * linux/include/asm-arm/imx/timex.h + * + * Copyright (C) 1999 ARM Limited * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,12 +18,9 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ -#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ - -/* mandatory for CONFIG_DEBUG_LL */ +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +#define CLOCK_TICK_RATE (16000000) -#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ +#endif diff --git a/trunk/arch/arm/mach-imx/include/mach/uncompress.h b/trunk/arch/arm/mach-imx/include/mach/uncompress.h new file mode 100644 index 000000000000..70523e67a8f6 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/uncompress.h @@ -0,0 +1,71 @@ +/* + * arch/arm/mach-imxads/include/mach/uncompress.h + * + * + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) Shane Nay (shane@minirl.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) + +#define UART1_BASE 0x206000 +#define UART2_BASE 0x207000 +#define USR2 0x98 +#define USR2_TXFE (1<<14) +#define TXR 0x40 +#define UCR1 0x80 +#define UCR1_UARTEN 1 + +/* + * The following code assumes the serial port has already been + * initialized by the bootloader. We search for the first enabled + * port in the most probable order. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * + * This does not append a newline + */ +static void putc(int c) +{ + unsigned long serial_port; + + do { + serial_port = UART1_BASE; + if ( UART(UCR1) & UCR1_UARTEN ) + break; + serial_port = UART2_BASE; + if ( UART(UCR1) & UCR1_UARTEN ) + break; + return; + } while(0); + + while (!(UART(USR2) & USR2_TXFE)) + barrier(); + + UART(TXR) = c; +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() diff --git a/trunk/arch/arm/mach-imx/include/mach/vmalloc.h b/trunk/arch/arm/mach-imx/include/mach/vmalloc.h new file mode 100644 index 000000000000..7d7cb0bde3e8 --- /dev/null +++ b/trunk/arch/arm/mach-imx/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-imx/include/mach/vmalloc.h + * + * Copyright (C) 2000 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/trunk/arch/arm/mach-imx/irq.c b/trunk/arch/arm/mach-imx/irq.c new file mode 100644 index 000000000000..531b95deadc0 --- /dev/null +++ b/trunk/arch/arm/mach-imx/irq.c @@ -0,0 +1,311 @@ +/* + * linux/arch/arm/mach-imx/irq.c + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * 03/03/2004 Sascha Hauer + * Copied from the motorola bsp package and added gpio demux + * interrupt handler + */ + +#include +#include +#include +#include + +#include +#include + +#include + +/* + * + * We simply use the ENABLE DISABLE registers inside of the IMX + * to turn on/off specific interrupts. + * + */ + +#define INTCNTL_OFF 0x00 +#define NIMASK_OFF 0x04 +#define INTENNUM_OFF 0x08 +#define INTDISNUM_OFF 0x0C +#define INTENABLEH_OFF 0x10 +#define INTENABLEL_OFF 0x14 +#define INTTYPEH_OFF 0x18 +#define INTTYPEL_OFF 0x1C +#define NIPRIORITY_OFF(x) (0x20+4*(7-(x))) +#define NIVECSR_OFF 0x40 +#define FIVECSR_OFF 0x44 +#define INTSRCH_OFF 0x48 +#define INTSRCL_OFF 0x4C +#define INTFRCH_OFF 0x50 +#define INTFRCL_OFF 0x54 +#define NIPNDH_OFF 0x58 +#define NIPNDL_OFF 0x5C +#define FIPNDH_OFF 0x60 +#define FIPNDL_OFF 0x64 + +#define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE) +#define IMX_AITC_INTCNTL (VA_AITC_BASE + INTCNTL_OFF) +#define IMX_AITC_NIMASK (VA_AITC_BASE + NIMASK_OFF) +#define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF) +#define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF) +#define IMX_AITC_INTENABLEH (VA_AITC_BASE + INTENABLEH_OFF) +#define IMX_AITC_INTENABLEL (VA_AITC_BASE + INTENABLEL_OFF) +#define IMX_AITC_INTTYPEH (VA_AITC_BASE + INTTYPEH_OFF) +#define IMX_AITC_INTTYPEL (VA_AITC_BASE + INTTYPEL_OFF) +#define IMX_AITC_NIPRIORITY(x) (VA_AITC_BASE + NIPRIORITY_OFF(x)) +#define IMX_AITC_NIVECSR (VA_AITC_BASE + NIVECSR_OFF) +#define IMX_AITC_FIVECSR (VA_AITC_BASE + FIVECSR_OFF) +#define IMX_AITC_INTSRCH (VA_AITC_BASE + INTSRCH_OFF) +#define IMX_AITC_INTSRCL (VA_AITC_BASE + INTSRCL_OFF) +#define IMX_AITC_INTFRCH (VA_AITC_BASE + INTFRCH_OFF) +#define IMX_AITC_INTFRCL (VA_AITC_BASE + INTFRCL_OFF) +#define IMX_AITC_NIPNDH (VA_AITC_BASE + NIPNDH_OFF) +#define IMX_AITC_NIPNDL (VA_AITC_BASE + NIPNDL_OFF) +#define IMX_AITC_FIPNDH (VA_AITC_BASE + FIPNDH_OFF) +#define IMX_AITC_FIPNDL (VA_AITC_BASE + FIPNDL_OFF) + +#if 0 +#define DEBUG_IRQ(fmt...) printk(fmt) +#else +#define DEBUG_IRQ(fmt...) do { } while (0) +#endif + +static void +imx_mask_irq(unsigned int irq) +{ + __raw_writel(irq, IMX_AITC_INTDISNUM); +} + +static void +imx_unmask_irq(unsigned int irq) +{ + __raw_writel(irq, IMX_AITC_INTENNUM); +} + +#ifdef CONFIG_FIQ +int imx_set_irq_fiq(unsigned int irq, unsigned int type) +{ + unsigned int irqt; + + if (irq >= IMX_IRQS) + return -EINVAL; + + if (irq < IMX_IRQS / 2) { + irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL); + } else { + irq -= IMX_IRQS / 2; + irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH); + } + + return 0; +} +EXPORT_SYMBOL(imx_set_irq_fiq); +#endif /* CONFIG_FIQ */ + +static int +imx_gpio_irq_type(unsigned int _irq, unsigned int type) +{ + unsigned int irq_type = 0, irq, reg, bit; + + irq = _irq - IRQ_GPIOA(0); + reg = irq >> 5; + bit = 1 << (irq % 32); + + if (type == IRQ_TYPE_PROBE) { + /* Don't mess with enabled GPIOs using preconfigured edges or + GPIOs set to alternate function during probe */ + /* TODO: support probe */ +// if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) & +// GPIO_bit(gpio)) +// return 0; +// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) +// return 0; +// type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + } + + GIUS(reg) |= bit; + DDIR(reg) &= ~(bit); + + DEBUG_IRQ("setting type of irq %d to ", _irq); + + if (type & IRQ_TYPE_EDGE_RISING) { + DEBUG_IRQ("rising edges\n"); + irq_type = 0x0; + } + if (type & IRQ_TYPE_EDGE_FALLING) { + DEBUG_IRQ("falling edges\n"); + irq_type = 0x1; + } + if (type & IRQ_TYPE_LEVEL_LOW) { + DEBUG_IRQ("low level\n"); + irq_type = 0x3; + } + if (type & IRQ_TYPE_LEVEL_HIGH) { + DEBUG_IRQ("high level\n"); + irq_type = 0x2; + } + + if (irq % 32 < 16) { + ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) | + (irq_type << ((irq % 16) * 2)); + } else { + ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) | + (irq_type << ((irq % 16) * 2)); + } + + return 0; + +} + +static void +imx_gpio_ack_irq(unsigned int irq) +{ + DEBUG_IRQ("%s: irq %d\n", __func__, irq); + ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32); +} + +static void +imx_gpio_mask_irq(unsigned int irq) +{ + DEBUG_IRQ("%s: irq %d\n", __func__, irq); + IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32)); +} + +static void +imx_gpio_unmask_irq(unsigned int irq) +{ + DEBUG_IRQ("%s: irq %d\n", __func__, irq); + IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32); +} + +static void +imx_gpio_handler(unsigned int mask, unsigned int irq, + struct irq_desc *desc) +{ + while (mask) { + if (mask & 1) { + DEBUG_IRQ("handling irq %d\n", irq); + generic_handle_irq(irq); + } + irq++; + mask >>= 1; + } +} + +static void +imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc) +{ + unsigned int mask, irq; + + mask = ISR(0); + irq = IRQ_GPIOA(0); + imx_gpio_handler(mask, irq, desc); +} + +static void +imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc) +{ + unsigned int mask, irq; + + mask = ISR(1); + irq = IRQ_GPIOB(0); + imx_gpio_handler(mask, irq, desc); +} + +static void +imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc) +{ + unsigned int mask, irq; + + mask = ISR(2); + irq = IRQ_GPIOC(0); + imx_gpio_handler(mask, irq, desc); +} + +static void +imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc) +{ + unsigned int mask, irq; + + mask = ISR(3); + irq = IRQ_GPIOD(0); + imx_gpio_handler(mask, irq, desc); +} + +static struct irq_chip imx_internal_chip = { + .name = "MPU", + .ack = imx_mask_irq, + .mask = imx_mask_irq, + .unmask = imx_unmask_irq, +}; + +static struct irq_chip imx_gpio_chip = { + .name = "GPIO", + .ack = imx_gpio_ack_irq, + .mask = imx_gpio_mask_irq, + .unmask = imx_gpio_unmask_irq, + .set_type = imx_gpio_irq_type, +}; + +void __init +imx_init_irq(void) +{ + unsigned int irq; + + DEBUG_IRQ("Initializing imx interrupts\n"); + + /* Disable all interrupts initially. */ + /* Do not rely on the bootloader. */ + __raw_writel(0, IMX_AITC_INTENABLEH); + __raw_writel(0, IMX_AITC_INTENABLEL); + + /* Mask all GPIO interrupts as well */ + IMR(0) = 0; + IMR(1) = 0; + IMR(2) = 0; + IMR(3) = 0; + + for (irq = 0; irq < IMX_IRQS; irq++) { + set_irq_chip(irq, &imx_internal_chip); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) { + set_irq_chip(irq, &imx_gpio_chip); + set_irq_handler(irq, handle_edge_irq); + set_irq_flags(irq, IRQF_VALID); + } + + set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler); + set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler); + set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler); + set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler); + + /* Release masking of interrupts according to priority */ + __raw_writel(-1, IMX_AITC_NIMASK); + +#ifdef CONFIG_FIQ + /* Initialize FIQ */ + init_FIQ(); +#endif +} diff --git a/trunk/arch/arm/mach-imx/leds-mx1ads.c b/trunk/arch/arm/mach-imx/leds-mx1ads.c new file mode 100644 index 000000000000..1d48f2762cbc --- /dev/null +++ b/trunk/arch/arm/mach-imx/leds-mx1ads.c @@ -0,0 +1,53 @@ +/* + * linux/arch/arm/mach-imx/leds-mx1ads.c + * + * Copyright (c) 2004 Sascha Hauer + * + * Original (leds-footbridge.c) by Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include "leds.h" + +/* + * The MX1ADS Board has only one usable LED, + * so select only the timer led or the + * cpu usage led + */ +void +mx1ads_leds_event(led_event_t ledevt) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (ledevt) { +#ifdef CONFIG_LEDS_CPU + case led_idle_start: + DR(0) &= ~(1<<2); + break; + + case led_idle_end: + DR(0) |= 1<<2; + break; +#endif + +#ifdef CONFIG_LEDS_TIMER + case led_timer: + DR(0) ^= 1<<2; +#endif + default: + break; + } + local_irq_restore(flags); +} diff --git a/trunk/arch/arm/mach-imx/leds.c b/trunk/arch/arm/mach-imx/leds.c new file mode 100644 index 000000000000..cf30803e019b --- /dev/null +++ b/trunk/arch/arm/mach-imx/leds.c @@ -0,0 +1,31 @@ +/* + * linux/arch/arm/mach-imx/leds.c + * + * Copyright (C) 2004 Sascha Hauer + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include + +#include +#include + +#include "leds.h" + +static int __init +leds_init(void) +{ + if (machine_is_mx1ads()) { + leds_event = mx1ads_leds_event; + } + + return 0; +} + +__initcall(leds_init); diff --git a/trunk/arch/arm/mach-imx/leds.h b/trunk/arch/arm/mach-imx/leds.h new file mode 100644 index 000000000000..49dc1c1da338 --- /dev/null +++ b/trunk/arch/arm/mach-imx/leds.h @@ -0,0 +1,9 @@ +/* + * arch/arm/mach-imx/leds.h + * + * Copyright (c) 2004 Sascha Hauer + * + * blinky lights for IMX-based systems + * + */ +extern void mx1ads_leds_event(led_event_t evt); diff --git a/trunk/arch/arm/mach-imx/mx1ads.c b/trunk/arch/arm/mach-imx/mx1ads.c new file mode 100644 index 000000000000..87fa1ff43b0b --- /dev/null +++ b/trunk/arch/arm/mach-imx/mx1ads.c @@ -0,0 +1,180 @@ +/* + * arch/arm/mach-imx/mx1ads.c + * + * Initially based on: + * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c + * Copyright (c) 2004 Sascha Hauer + * + * 2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include "generic.h" + +static struct resource cs89x0_resources[] = { + [0] = { + .start = IMX_CS4_PHYS + 0x300, + .end = IMX_CS4_PHYS + 0x300 + 16, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_GPIOC(17), + .end = IRQ_GPIOC(17), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cs89x0_device = { + .name = "cirrus-cs89x0", + .num_resources = ARRAY_SIZE(cs89x0_resources), + .resource = cs89x0_resources, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct resource imx_uart1_resources[] = { + [0] = { + .start = 0x00206000, + .end = 0x002060FF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = (UART1_MINT_RX), + .end = (UART1_MINT_RX), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = (UART1_MINT_TX), + .end = (UART1_MINT_TX), + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = UART1_MINT_RTS, + .end = UART1_MINT_RTS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device imx_uart1_device = { + .name = "imx-uart", + .id = 0, + .num_resources = ARRAY_SIZE(imx_uart1_resources), + .resource = imx_uart1_resources, + .dev = { + .platform_data = &uart_pdata, + } +}; + +static struct resource imx_uart2_resources[] = { + [0] = { + .start = 0x00207000, + .end = 0x002070FF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = (UART2_MINT_RX), + .end = (UART2_MINT_RX), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = (UART2_MINT_TX), + .end = (UART2_MINT_TX), + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = UART2_MINT_RTS, + .end = UART2_MINT_RTS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device imx_uart2_device = { + .name = "imx-uart", + .id = 1, + .num_resources = ARRAY_SIZE(imx_uart2_resources), + .resource = imx_uart2_resources, + .dev = { + .platform_data = &uart_pdata, + } +}; + +static struct platform_device *devices[] __initdata = { + &cs89x0_device, + &imx_uart1_device, + &imx_uart2_device, +}; + +#if defined(CONFIG_MMC_IMX) || defined(CONFIG_MMC_IMX_MODULE) +static int mx1ads_mmc_card_present(struct device *dev) +{ + /* MMC/SD Card Detect is PB 20 on MX1ADS V1.0.7 */ + return (SSR(1) & (1 << 20) ? 0 : 1); +} + +static struct imxmmc_platform_data mx1ads_mmc_info = { + .card_present = mx1ads_mmc_card_present, +}; +#endif + +static void __init +mx1ads_init(void) +{ +#ifdef CONFIG_LEDS + imx_gpio_mode(GPIO_PORTA | GPIO_OUT | 2); +#endif +#if defined(CONFIG_MMC_IMX) || defined(CONFIG_MMC_IMX_MODULE) + /* SD/MMC card detect */ + imx_gpio_mode(GPIO_PORTB | GPIO_GIUS | GPIO_IN | 20); + imx_set_mmc_info(&mx1ads_mmc_info); +#endif + + imx_gpio_mode(PC9_PF_UART1_CTS); + imx_gpio_mode(PC10_PF_UART1_RTS); + imx_gpio_mode(PC11_PF_UART1_TXD); + imx_gpio_mode(PC12_PF_UART1_RXD); + + imx_gpio_mode(PB28_PF_UART2_CTS); + imx_gpio_mode(PB29_PF_UART2_RTS); + imx_gpio_mode(PB30_PF_UART2_TXD); + imx_gpio_mode(PB31_PF_UART2_RXD); + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init +mx1ads_map_io(void) +{ + imx_map_io(); +} + +MACHINE_START(MX1ADS, "Motorola MX1ADS") + /* Maintainer: Sascha Hauer, Pengutronix */ + .phys_io = 0x00200000, + .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc, + .boot_params = 0x08000100, + .map_io = mx1ads_map_io, + .init_irq = imx_init_irq, + .timer = &imx_timer, + .init_machine = mx1ads_init, +MACHINE_END diff --git a/trunk/arch/arm/mach-imx/time.c b/trunk/arch/arm/mach-imx/time.c new file mode 100644 index 000000000000..5aef18b599e5 --- /dev/null +++ b/trunk/arch/arm/mach-imx/time.c @@ -0,0 +1,220 @@ +/* + * linux/arch/arm/mach-imx/time.c + * + * Copyright (C) 2000-2001 Deep Blue Solutions + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Use timer 1 as system timer */ +#define TIMER_BASE IMX_TIM1_BASE + +static struct clock_event_device clockevent_imx; +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; + +/* + * IRQ handler for the timer + */ +static irqreturn_t +imx_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_imx; + uint32_t tstat; + irqreturn_t ret = IRQ_NONE; + + /* clear the interrupt */ + tstat = IMX_TSTAT(TIMER_BASE); + IMX_TSTAT(TIMER_BASE) = 0; + + if (tstat & TSTAT_COMP) { + evt->event_handler(evt); + ret = IRQ_HANDLED; + } + + return ret; +} + +static struct irqaction imx_timer_irq = { + .name = "i.MX Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = imx_timer_interrupt, +}; + +/* + * Set up timer hardware into expected mode and state. + */ +static void __init imx_timer_hardware_init(void) +{ + /* + * Initialise to a known state (all timers off, and timing reset) + */ + IMX_TCTL(TIMER_BASE) = 0; + IMX_TPRER(TIMER_BASE) = 0; + + IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_TEN; +} + +cycle_t imx_get_cycles(struct clocksource *cs) +{ + return IMX_TCN(TIMER_BASE); +} + +static struct clocksource clocksource_imx = { + .name = "imx_timer1", + .rating = 200, + .read = imx_get_cycles, + .mask = 0xFFFFFFFF, + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init imx_clocksource_init(unsigned long rate) +{ + clocksource_imx.mult = + clocksource_hz2mult(rate, clocksource_imx.shift); + clocksource_register(&clocksource_imx); + + return 0; +} + +static int imx_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long tcmp; + + tcmp = IMX_TCN(TIMER_BASE) + evt; + IMX_TCMP(TIMER_BASE) = tcmp; + + return (int32_t)(tcmp - IMX_TCN(TIMER_BASE)) < 0 ? -ETIME : 0; +} + +#ifdef DEBUG +static const char *clock_event_mode_label[]={ + [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", + [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", + [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", + [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED" +}; +#endif /*DEBUG*/ + +static void imx_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) +{ + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call imx_set_next_event() + */ + local_irq_save(flags); + /* Disable interrupt in GPT module */ + IMX_TCTL(TIMER_BASE) &= ~TCTL_IRQEN; + if (mode != clockevent_mode) { + /* Set event time into far-far future */ + IMX_TCMP(TIMER_BASE) = IMX_TCN(TIMER_BASE) - 3; + /* Clear pending interrupt */ + IMX_TSTAT(TIMER_BASE) &= ~TSTAT_COMP; + } + +#ifdef DEBUG + printk(KERN_INFO "imx_set_mode: changing mode from %s to %s\n", + clock_event_mode_label[clockevent_mode], clock_event_mode_label[mode]); +#endif /*DEBUG*/ + + /* Remember timer mode */ + clockevent_mode = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + printk(KERN_ERR "imx_set_mode: Periodic mode is not supported for i.MX\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* + * Do not put overhead of interrupt enable/disable into + * imx_set_next_event(), the core has about 4 minutes + * to call imx_set_next_event() or shutdown clock after + * mode switching + */ + local_irq_save(flags); + IMX_TCTL(TIMER_BASE) |= TCTL_IRQEN; + local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appears */ + break; + } +} + +static struct clock_event_device clockevent_imx = { + .name = "imx_timer1", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_mode = imx_set_mode, + .set_next_event = imx_set_next_event, + .rating = 200, +}; + +static int __init imx_clockevent_init(unsigned long rate) +{ + clockevent_imx.mult = div_sc(rate, NSEC_PER_SEC, + clockevent_imx.shift); + clockevent_imx.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_imx); + clockevent_imx.min_delta_ns = + clockevent_delta2ns(0xf, &clockevent_imx); + + clockevent_imx.cpumask = cpumask_of(0); + + clockevents_register_device(&clockevent_imx); + + return 0; +} + +extern int imx_clocks_init(void); + +static void __init imx_timer_init(void) +{ + struct clk *clk; + unsigned long rate; + + imx_clocks_init(); + + clk = clk_get(NULL, "perclk1"); + clk_enable(clk); + rate = clk_get_rate(clk); + + imx_timer_hardware_init(); + imx_clocksource_init(rate); + + imx_clockevent_init(rate); + + /* + * Make irqs happen for the system timer + */ + setup_irq(TIM1_INT, &imx_timer_irq); +} + +struct sys_timer imx_timer = { + .init = imx_timer_init, +}; diff --git a/trunk/arch/arm/mach-ixp4xx/Kconfig b/trunk/arch/arm/mach-ixp4xx/Kconfig index 264f4d59f898..2c5a02b8520e 100644 --- a/trunk/arch/arm/mach-ixp4xx/Kconfig +++ b/trunk/arch/arm/mach-ixp4xx/Kconfig @@ -78,12 +78,6 @@ config MACH_IXDP465 IXDP465 Development Platform (Also known as BMP). For more information on this platform, see . -config MACH_GORAMO_MLR - bool "GORAMO Multi Link Router" - help - Say 'Y' here if you want your kernel to support GORAMO - MultiLink router. - config MACH_KIXRP435 bool "KIXRP435" help diff --git a/trunk/arch/arm/mach-ixp4xx/Makefile b/trunk/arch/arm/mach-ixp4xx/Makefile index 47d1f60d23fa..2e6bbf927a74 100644 --- a/trunk/arch/arm/mach-ixp4xx/Makefile +++ b/trunk/arch/arm/mach-ixp4xx/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o obj-$(CONFIG_MACH_FSG) += fsg-setup.o -obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o diff --git a/trunk/arch/arm/mach-ixp4xx/goramo_mlr.c b/trunk/arch/arm/mach-ixp4xx/goramo_mlr.c deleted file mode 100644 index a733b8ff3cec..000000000000 --- a/trunk/arch/arm/mach-ixp4xx/goramo_mlr.c +++ /dev/null @@ -1,507 +0,0 @@ -/* - * Goramo MultiLink router platform code - * Copyright (C) 2006-2009 Krzysztof Halasa - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n) -#define gpio_irq(n) xgpio_irq(n) - -#define SLOT_ETHA 0x0B /* IDSEL = AD21 */ -#define SLOT_ETHB 0x0C /* IDSEL = AD20 */ -#define SLOT_MPCI 0x0D /* IDSEL = AD19 */ -#define SLOT_NEC 0x0E /* IDSEL = AD18 */ - -#define IRQ_ETHA IRQ_IXP4XX_GPIO4 -#define IRQ_ETHB IRQ_IXP4XX_GPIO5 -#define IRQ_NEC IRQ_IXP4XX_GPIO3 -#define IRQ_MPCI IRQ_IXP4XX_GPIO12 - -/* GPIO lines */ -#define GPIO_SCL 0 -#define GPIO_SDA 1 -#define GPIO_STR 2 -#define GPIO_HSS0_DCD_N 6 -#define GPIO_HSS1_DCD_N 7 -#define GPIO_HSS0_CTS_N 10 -#define GPIO_HSS1_CTS_N 11 -#define GPIO_HSS1_RTS_N 13 -#define GPIO_HSS0_RTS_N 14 - -/* Control outputs from 74HC4094 */ -#define CONTROL_HSS0_CLK_INT 0 -#define CONTROL_HSS1_CLK_INT 1 -#define CONTROL_HSS0_DTR_N 2 -#define CONTROL_HSS1_DTR_N 3 -#define CONTROL_EXT 4 -#define CONTROL_AUTO_RESET 5 -#define CONTROL_PCI_RESET_N 6 -#define CONTROL_EEPROM_WC_N 7 - -/* offsets from start of flash ROM = 0x50000000 */ -#define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */ -#define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */ -#define CFG_REV 0x4C /* u32 */ -#define CFG_SDRAM_SIZE 0x50 /* u32 */ -#define CFG_SDRAM_CONF 0x54 /* u32 */ -#define CFG_SDRAM_MODE 0x58 /* u32 */ -#define CFG_SDRAM_REFRESH 0x5C /* u32 */ - -#define CFG_HW_BITS 0x60 /* u32 */ -#define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */ -#define CFG_HW_HAS_PCI_SLOT 0x00000008 -#define CFG_HW_HAS_ETH0 0x00000010 -#define CFG_HW_HAS_ETH1 0x00000020 -#define CFG_HW_HAS_HSS0 0x00000040 -#define CFG_HW_HAS_HSS1 0x00000080 -#define CFG_HW_HAS_UART0 0x00000100 -#define CFG_HW_HAS_UART1 0x00000200 -#define CFG_HW_HAS_EEPROM 0x00000400 - -#define FLASH_CMD_READ_ARRAY 0xFF -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */ - -static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */; -static u8 control_value; - -static void set_scl(u8 value) -{ - gpio_line_set(GPIO_SCL, !!value); - udelay(3); -} - -static void set_sda(u8 value) -{ - gpio_line_set(GPIO_SDA, !!value); - udelay(3); -} - -static void set_str(u8 value) -{ - gpio_line_set(GPIO_STR, !!value); - udelay(3); -} - -static inline void set_control(int line, int value) -{ - if (value) - control_value |= (1 << line); - else - control_value &= ~(1 << line); -} - - -static void output_control(void) -{ - int i; - - gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT); - gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT); - - for (i = 0; i < 8; i++) { - set_scl(0); - set_sda(control_value & (0x80 >> i)); /* MSB first */ - set_scl(1); /* active edge */ - } - - set_str(1); - set_str(0); - - set_scl(0); - set_sda(1); /* Be ready for START */ - set_scl(1); -} - - -static void (*set_carrier_cb_tab[2])(void *pdev, int carrier); - -static int hss_set_clock(int port, unsigned int clock_type) -{ - int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT; - - switch (clock_type) { - case CLOCK_DEFAULT: - case CLOCK_EXT: - set_control(ctrl_int, 0); - output_control(); - return CLOCK_EXT; - - case CLOCK_INT: - set_control(ctrl_int, 1); - output_control(); - return CLOCK_INT; - - default: - return -EINVAL; - } -} - -static irqreturn_t hss_dcd_irq(int irq, void *pdev) -{ - int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N)); - gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); - set_carrier_cb_tab[port](pdev, !i); - return IRQ_HANDLED; -} - - -static int hss_open(int port, void *pdev, - void (*set_carrier_cb)(void *pdev, int carrier)) -{ - int i, irq; - - if (!port) - irq = gpio_irq(GPIO_HSS0_DCD_N); - else - irq = gpio_irq(GPIO_HSS1_DCD_N); - - gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); - set_carrier_cb(pdev, !i); - - set_carrier_cb_tab[!!port] = set_carrier_cb; - - if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) { - printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n", - irq, i); - return i; - } - - set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0); - output_control(); - gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0); - return 0; -} - -static void hss_close(int port, void *pdev) -{ - free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N), - pdev); - set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ - - set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); - output_control(); - gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1); -} - - -/* Flash memory */ -static struct flash_platform_data flash_data = { - .map_name = "cfi_probe", - .width = 2, -}; - -static struct resource flash_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device device_flash = { - .name = "IXP4XX-Flash", - .id = 0, - .dev = { .platform_data = &flash_data }, - .num_resources = 1, - .resource = &flash_resource, -}; - - -/* I^2C interface */ -static struct i2c_gpio_platform_data i2c_data = { - .sda_pin = GPIO_SDA, - .scl_pin = GPIO_SCL, -}; - -static struct platform_device device_i2c = { - .name = "i2c-gpio", - .id = 0, - .dev = { .platform_data = &i2c_data }, -}; - - -/* IXP425 2 UART ports */ -static struct resource uart_resources[] = { - { - .start = IXP4XX_UART1_BASE_PHYS, - .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, - .flags = IORESOURCE_MEM, - }, - { - .start = IXP4XX_UART2_BASE_PHYS, - .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, - .flags = IORESOURCE_MEM, - } -}; - -static struct plat_serial8250_port uart_data[] = { - { - .mapbase = IXP4XX_UART1_BASE_PHYS, - .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT + - REG_OFFSET, - .irq = IRQ_IXP4XX_UART1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP4XX_UART_XTAL, - }, - { - .mapbase = IXP4XX_UART2_BASE_PHYS, - .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT + - REG_OFFSET, - .irq = IRQ_IXP4XX_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP4XX_UART_XTAL, - }, - { }, -}; - -static struct platform_device device_uarts = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = uart_data, - .num_resources = 2, - .resource = uart_resources, -}; - - -/* Built-in 10/100 Ethernet MAC interfaces */ -static struct eth_plat_info eth_plat[] = { - { - .phy = 0, - .rxq = 3, - .txreadyq = 32, - }, { - .phy = 1, - .rxq = 4, - .txreadyq = 33, - } -}; - -static struct platform_device device_eth_tab[] = { - { - .name = "ixp4xx_eth", - .id = IXP4XX_ETH_NPEB, - .dev.platform_data = eth_plat, - }, { - .name = "ixp4xx_eth", - .id = IXP4XX_ETH_NPEC, - .dev.platform_data = eth_plat + 1, - } -}; - - -/* IXP425 2 synchronous serial ports */ -static struct hss_plat_info hss_plat[] = { - { - .set_clock = hss_set_clock, - .open = hss_open, - .close = hss_close, - .txreadyq = 34, - }, { - .set_clock = hss_set_clock, - .open = hss_open, - .close = hss_close, - .txreadyq = 35, - } -}; - -static struct platform_device device_hss_tab[] = { - { - .name = "ixp4xx_hss", - .id = 0, - .dev.platform_data = hss_plat, - }, { - .name = "ixp4xx_hss", - .id = 1, - .dev.platform_data = hss_plat + 1, - } -}; - - -static struct platform_device *device_tab[6] __initdata = { - &device_flash, /* index 0 */ -}; - -static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr) -{ -#ifdef __ARMEB__ - return __raw_readb(flash + addr); -#else - return __raw_readb(flash + (addr ^ 3)); -#endif -} - -static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr) -{ -#ifdef __ARMEB__ - return __raw_readw(flash + addr); -#else - return __raw_readw(flash + (addr ^ 2)); -#endif -} - -static void __init gmlr_init(void) -{ - u8 __iomem *flash; - int i, devices = 1; /* flash */ - - ixp4xx_sys_init(); - - if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL) - printk(KERN_ERR "goramo-mlr: unable to access system" - " configuration data\n"); - else { - system_rev = __raw_readl(flash + CFG_REV); - hw_bits = __raw_readl(flash + CFG_HW_BITS); - - for (i = 0; i < ETH_ALEN; i++) { - eth_plat[0].hwaddr[i] = - flash_readb(flash, CFG_ETH0_ADDRESS + i); - eth_plat[1].hwaddr[i] = - flash_readb(flash, CFG_ETH1_ADDRESS + i); - } - - __raw_writew(FLASH_CMD_READ_ID, flash); - system_serial_high = flash_readw(flash, FLASH_SER_OFF); - system_serial_high <<= 16; - system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2); - system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4); - system_serial_low <<= 16; - system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6); - __raw_writew(FLASH_CMD_READ_ARRAY, flash); - - iounmap(flash); - } - - switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) { - case CFG_HW_HAS_UART0: - memset(&uart_data[1], 0, sizeof(uart_data[1])); - device_uarts.num_resources = 1; - break; - - case CFG_HW_HAS_UART1: - device_uarts.dev.platform_data = &uart_data[1]; - device_uarts.resource = &uart_resources[1]; - device_uarts.num_resources = 1; - break; - } - if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) - device_tab[devices++] = &device_uarts; /* max index 1 */ - - if (hw_bits & CFG_HW_HAS_ETH0) - device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */ - if (hw_bits & CFG_HW_HAS_ETH1) - device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */ - - if (hw_bits & CFG_HW_HAS_HSS0) - device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */ - if (hw_bits & CFG_HW_HAS_HSS1) - device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */ - - if (hw_bits & CFG_HW_HAS_EEPROM) - device_tab[devices++] = &device_i2c; /* max index 6 */ - - gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT); - gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT); - gpio_line_config(GPIO_STR, IXP4XX_GPIO_OUT); - gpio_line_config(GPIO_HSS0_RTS_N, IXP4XX_GPIO_OUT); - gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); - gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); - gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); - set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); - set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); - - set_control(CONTROL_HSS0_DTR_N, 1); - set_control(CONTROL_HSS1_DTR_N, 1); - set_control(CONTROL_EEPROM_WC_N, 1); - set_control(CONTROL_PCI_RESET_N, 1); - output_control(); - - msleep(1); /* Wait for PCI devices to initialize */ - - flash_resource.start = IXP4XX_EXP_BUS_BASE(0); - flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; - - platform_add_devices(device_tab, devices); -} - - -#ifdef CONFIG_PCI -static void __init gmlr_pci_preinit(void) -{ - set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW); - ixp4xx_pci_preinit(); -} - -static void __init gmlr_pci_postinit(void) -{ - if ((hw_bits & CFG_HW_USB_PORTS) >= 2 && - (hw_bits & CFG_HW_USB_PORTS) < 5) { - /* need to adjust number of USB ports on NEC chip */ - u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0; - if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) { - value &= ~7; - value |= (hw_bits & CFG_HW_USB_PORTS); - ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value); - } - } -} - -static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - switch(slot) { - case SLOT_ETHA: return IRQ_ETHA; - case SLOT_ETHB: return IRQ_ETHB; - case SLOT_NEC: return IRQ_NEC; - default: return IRQ_MPCI; - } -} - -static struct hw_pci gmlr_hw_pci __initdata = { - .nr_controllers = 1, - .preinit = gmlr_pci_preinit, - .postinit = gmlr_pci_postinit, - .swizzle = pci_std_swizzle, - .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, - .map_irq = gmlr_map_irq, -}; - -static int __init gmlr_pci_init(void) -{ - if (machine_is_goramo_mlr() && - (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT))) - pci_common_init(&gmlr_hw_pci); - return 0; -} - -subsys_initcall(gmlr_pci_init); -#endif /* CONFIG_PCI */ - - -MACHINE_START(GORAMO_MLR, "MultiLink") - /* Maintainer: Krzysztof Halasa */ - .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, - .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC, - .map_io = ixp4xx_map_io, - .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, - .boot_params = 0x0100, - .init_machine = gmlr_init, -MACHINE_END diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h b/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h index b2ef65db0e91..def7773be67c 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h @@ -26,8 +26,6 @@ #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 -#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \ - IXP42X_PROCESSOR_ID_VALUE) #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \ IXP42X_PROCESSOR_ID_VALUE) #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \ @@ -37,11 +35,8 @@ static inline u32 ixp4xx_read_feature_bits(void) { - u32 val = ~*IXP4XX_EXP_CFG2; + unsigned int val = ~*IXP4XX_EXP_CFG2; - if (cpu_is_ixp42x_rev_a0()) - return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | - IXP4XX_FEATURE_AES); if (cpu_is_ixp42x()) return val & IXP42X_FEATURE_MASK; if (cpu_is_ixp43x()) diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/trunk/arch/arm/mach-ixp4xx/include/mach/qmgr.h index 9e7cad2d54cb..0cbe6ceb67c5 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/qmgr.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/qmgr.h @@ -15,7 +15,7 @@ #define DEBUG_QMGR 0 #define HALF_QUEUES 32 -#define QUEUES 64 +#define QUEUES 64 /* only 32 lower queues currently supported */ #define MAX_QUEUE_LENGTH 4 /* in dwords */ #define QUEUE_STAT1_EMPTY 1 /* queue status bits */ @@ -110,95 +110,48 @@ static inline u32 qmgr_get_entry(unsigned int queue) return val; } -static inline int __qmgr_get_stat1(unsigned int queue) +static inline int qmgr_get_stat1(unsigned int queue) { extern struct qmgr_regs __iomem *qmgr_regs; return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) >> ((queue & 7) << 2)) & 0xF; } -static inline int __qmgr_get_stat2(unsigned int queue) +static inline int qmgr_get_stat2(unsigned int queue) { extern struct qmgr_regs __iomem *qmgr_regs; - BUG_ON(queue >= HALF_QUEUES); return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) >> ((queue & 0xF) << 1)) & 0x3; } -/** - * qmgr_stat_empty() - checks if a hardware queue is empty - * @queue: queue number - * - * Returns non-zero value if the queue is empty. - */ static inline int qmgr_stat_empty(unsigned int queue) { - BUG_ON(queue >= HALF_QUEUES); - return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY; + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY); } -/** - * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark - * @queue: queue number - * - * Returns non-zero value if the queue is below low watermark. - */ -static inline int qmgr_stat_below_low_watermark(unsigned int queue) +static inline int qmgr_stat_nearly_empty(unsigned int queue) { - extern struct qmgr_regs __iomem *qmgr_regs; - if (queue >= HALF_QUEUES) - return (__raw_readl(&qmgr_regs->statne_h) >> - (queue - HALF_QUEUES)) & 0x01; - return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY; + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY); } -/** - * qmgr_stat_above_high_watermark() - checks if a queue is above high watermark - * @queue: queue number - * - * Returns non-zero value if the queue is above high watermark - */ -static inline int qmgr_stat_above_high_watermark(unsigned int queue) +static inline int qmgr_stat_nearly_full(unsigned int queue) { - BUG_ON(queue >= HALF_QUEUES); - return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL; + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL); } -/** - * qmgr_stat_full() - checks if a hardware queue is full - * @queue: queue number - * - * Returns non-zero value if the queue is full. - */ static inline int qmgr_stat_full(unsigned int queue) { - extern struct qmgr_regs __iomem *qmgr_regs; - if (queue >= HALF_QUEUES) - return (__raw_readl(&qmgr_regs->statf_h) >> - (queue - HALF_QUEUES)) & 0x01; - return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL; + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL); } -/** - * qmgr_stat_underflow() - checks if a hardware queue experienced underflow - * @queue: queue number - * - * Returns non-zero value if the queue experienced underflow. - */ static inline int qmgr_stat_underflow(unsigned int queue) { - return __qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW; + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW); } -/** - * qmgr_stat_overflow() - checks if a hardware queue experienced overflow - * @queue: queue number - * - * Returns non-zero value if the queue experienced overflow. - */ static inline int qmgr_stat_overflow(unsigned int queue) { - return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW; + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW); } #endif diff --git a/trunk/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/trunk/arch/arm/mach-ixp4xx/ixp4xx_npe.c index 47ac69c7ec78..7bb8e778e4b6 100644 --- a/trunk/arch/arm/mach-ixp4xx/ixp4xx_npe.c +++ b/trunk/arch/arm/mach-ixp4xx/ixp4xx_npe.c @@ -386,6 +386,15 @@ static int npe_reset(struct npe *npe) /* reset the NPE */ ixp4xx_write_feature_bits(val & ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); + for (i = 0; i < MAX_RETRIES; i++) { + if (!(ixp4xx_read_feature_bits() & + (IXP4XX_FEATURE_RESET_NPEA << npe->id))) + break; /* reset completed */ + udelay(1); + } + if (i == MAX_RETRIES) + return -ETIMEDOUT; + /* deassert reset */ ixp4xx_write_feature_bits(val | (IXP4XX_FEATURE_RESET_NPEA << npe->id)); diff --git a/trunk/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/trunk/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c index bfdbe4b5a3cc..bfddc73d0a20 100644 --- a/trunk/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c +++ b/trunk/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c @@ -18,8 +18,8 @@ struct qmgr_regs __iomem *qmgr_regs; static struct resource *mem_res; static spinlock_t qmgr_lock; static u32 used_sram_bitmap[4]; /* 128 16-dword pages */ -static void (*irq_handlers[QUEUES])(void *pdev); -static void *irq_pdevs[QUEUES]; +static void (*irq_handlers[HALF_QUEUES])(void *pdev); +static void *irq_pdevs[HALF_QUEUES]; #if DEBUG_QMGR char qmgr_queue_descs[QUEUES][32]; @@ -28,112 +28,51 @@ char qmgr_queue_descs[QUEUES][32]; void qmgr_set_irq(unsigned int queue, int src, void (*handler)(void *pdev), void *pdev) { + u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */ + int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */ unsigned long flags; + src &= 7; spin_lock_irqsave(&qmgr_lock, flags); - if (queue < HALF_QUEUES) { - u32 __iomem *reg; - int bit; - BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL); - reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */ - bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */ - __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), - reg); - } else - /* IRQ source for queues 32-63 is fixed */ - BUG_ON(src != QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY); - + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg); irq_handlers[queue] = handler; irq_pdevs[queue] = pdev; spin_unlock_irqrestore(&qmgr_lock, flags); } -static irqreturn_t qmgr_irq1_a0(int irq, void *pdev) -{ - int i, ret = 0; - u32 en_bitmap, src, stat; - - /* ACK - it may clear any bits so don't rely on it */ - __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]); - - en_bitmap = qmgr_regs->irqen[0]; - while (en_bitmap) { - i = __fls(en_bitmap); /* number of the last "low" queue */ - en_bitmap &= ~BIT(i); - src = qmgr_regs->irqsrc[i >> 3]; - stat = qmgr_regs->stat1[i >> 3]; - if (src & 4) /* the IRQ condition is inverted */ - stat = ~stat; - if (stat & BIT(src & 3)) { - irq_handlers[i](irq_pdevs[i]); - ret = IRQ_HANDLED; - } - } - return ret; -} - - -static irqreturn_t qmgr_irq2_a0(int irq, void *pdev) +static irqreturn_t qmgr_irq1(int irq, void *pdev) { - int i, ret = 0; - u32 req_bitmap; - - /* ACK - it may clear any bits so don't rely on it */ - __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]); - - req_bitmap = qmgr_regs->irqen[1] & qmgr_regs->statne_h; - while (req_bitmap) { - i = __fls(req_bitmap); /* number of the last "high" queue */ - req_bitmap &= ~BIT(i); - irq_handlers[HALF_QUEUES + i](irq_pdevs[HALF_QUEUES + i]); - ret = IRQ_HANDLED; - } - return ret; -} + int i; + u32 val = __raw_readl(&qmgr_regs->irqstat[0]); + __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */ + for (i = 0; i < HALF_QUEUES; i++) + if (val & (1 << i)) + irq_handlers[i](irq_pdevs[i]); -static irqreturn_t qmgr_irq(int irq, void *pdev) -{ - int i, half = (irq == IRQ_IXP4XX_QM1 ? 0 : 1); - u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]); - - if (!req_bitmap) - return 0; - __raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */ - - while (req_bitmap) { - i = __fls(req_bitmap); /* number of the last queue */ - req_bitmap &= ~BIT(i); - i += half * HALF_QUEUES; - irq_handlers[i](irq_pdevs[i]); - } - return IRQ_HANDLED; + return val ? IRQ_HANDLED : 0; } void qmgr_enable_irq(unsigned int queue) { unsigned long flags; - int half = queue / 32; - u32 mask = 1 << (queue & (HALF_QUEUES - 1)); spin_lock_irqsave(&qmgr_lock, flags); - __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, - &qmgr_regs->irqen[half]); + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue), + &qmgr_regs->irqen[0]); spin_unlock_irqrestore(&qmgr_lock, flags); } void qmgr_disable_irq(unsigned int queue) { unsigned long flags; - int half = queue / 32; - u32 mask = 1 << (queue & (HALF_QUEUES - 1)); spin_lock_irqsave(&qmgr_lock, flags); - __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, - &qmgr_regs->irqen[half]); - __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */ + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue), + &qmgr_regs->irqen[0]); + __raw_writel(1 << queue, &qmgr_regs->irqstat[0]); /* clear */ spin_unlock_irqrestore(&qmgr_lock, flags); } @@ -159,7 +98,8 @@ int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ int err; - BUG_ON(queue >= QUEUES); + if (queue >= HALF_QUEUES) + return -ERANGE; if ((nearly_empty_watermark | nearly_full_watermark) & ~7) return -EINVAL; @@ -240,7 +180,7 @@ void qmgr_release_queue(unsigned int queue) { u32 cfg, addr, mask[4]; - BUG_ON(queue >= QUEUES); /* not in valid range */ + BUG_ON(queue >= HALF_QUEUES); /* not in valid range */ spin_lock_irq(&qmgr_lock); cfg = __raw_readl(&qmgr_regs->sram[queue]); @@ -284,8 +224,6 @@ void qmgr_release_queue(unsigned int queue) static int qmgr_init(void) { int i, err; - irq_handler_t handler1, handler2; - mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE, "IXP4xx Queue Manager"); @@ -309,42 +247,23 @@ static int qmgr_init(void) __raw_writel(0, &qmgr_regs->irqen[i]); } - __raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h); - __raw_writel(0, &qmgr_regs->statf_h); - for (i = 0; i < QUEUES; i++) __raw_writel(0, &qmgr_regs->sram[i]); - if (cpu_is_ixp42x_rev_a0()) { - handler1 = qmgr_irq1_a0; - handler2 = qmgr_irq2_a0; - } else - handler1 = handler2 = qmgr_irq; - - err = request_irq(IRQ_IXP4XX_QM1, handler1, 0, "IXP4xx Queue Manager", - NULL); + err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0, + "IXP4xx Queue Manager", NULL); if (err) { - printk(KERN_ERR "qmgr: failed to request IRQ%i (%i)\n", - IRQ_IXP4XX_QM1, err); + printk(KERN_ERR "qmgr: failed to request IRQ%i\n", + IRQ_IXP4XX_QM1); goto error_irq; } - err = request_irq(IRQ_IXP4XX_QM2, handler2, 0, "IXP4xx Queue Manager", - NULL); - if (err) { - printk(KERN_ERR "qmgr: failed to request IRQ%i (%i)\n", - IRQ_IXP4XX_QM2, err); - goto error_irq2; - } - used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */ spin_lock_init(&qmgr_lock); printk(KERN_INFO "IXP4xx Queue Manager initialized.\n"); return 0; -error_irq2: - free_irq(IRQ_IXP4XX_QM1, NULL); error_irq: iounmap(qmgr_regs); error_map: @@ -355,9 +274,7 @@ static int qmgr_init(void) static void qmgr_remove(void) { free_irq(IRQ_IXP4XX_QM1, NULL); - free_irq(IRQ_IXP4XX_QM2, NULL); synchronize_irq(IRQ_IXP4XX_QM1); - synchronize_irq(IRQ_IXP4XX_QM2); iounmap(qmgr_regs); release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); } diff --git a/trunk/arch/arm/mach-kirkwood/Kconfig b/trunk/arch/arm/mach-kirkwood/Kconfig index 25100f7acf4c..b5421cccd7e1 100644 --- a/trunk/arch/arm/mach-kirkwood/Kconfig +++ b/trunk/arch/arm/mach-kirkwood/Kconfig @@ -20,12 +20,6 @@ config MACH_RD88F6281 Say 'Y' here if you want your kernel to support the Marvell RD-88F6281 Reference Board. -config MACH_MV88F6281GTW_GE - bool "Marvell 88F6281 GTW GE Board" - help - Say 'Y' here if you want your kernel to support the - Marvell 88F6281 GTW GE Board. - config MACH_SHEEVAPLUG bool "Marvell SheevaPlug Reference Board" help diff --git a/trunk/arch/arm/mach-kirkwood/Makefile b/trunk/arch/arm/mach-kirkwood/Makefile index 9dd680e964d6..8f03c9b9bdd9 100644 --- a/trunk/arch/arm/mach-kirkwood/Makefile +++ b/trunk/arch/arm/mach-kirkwood/Makefile @@ -3,8 +3,5 @@ obj-y += common.o addr-map.o irq.o pcie.o mpp.o obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o -obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o - -obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/trunk/arch/arm/mach-kirkwood/addr-map.c b/trunk/arch/arm/mach-kirkwood/addr-map.c index 1da5d1c18ecb..5db4f0bbe5ee 100644 --- a/trunk/arch/arm/mach-kirkwood/addr-map.c +++ b/trunk/arch/arm/mach-kirkwood/addr-map.c @@ -20,7 +20,6 @@ */ #define TARGET_DDR 0 #define TARGET_DEV_BUS 1 -#define TARGET_SRAM 3 #define TARGET_PCIE 4 #define ATTR_DEV_SPI_ROM 0x1e #define ATTR_DEV_BOOT 0x1d @@ -31,7 +30,6 @@ #define ATTR_DEV_CS0 0x3e #define ATTR_PCIE_IO 0xe0 #define ATTR_PCIE_MEM 0xe8 -#define ATTR_SRAM 0x01 /* * Helpers to get DDR bank info @@ -50,6 +48,7 @@ struct mbus_dram_target_info kirkwood_mbus_dram_info; +static int __initdata win_alloc_count; static int __init cpu_win_can_remap(int win) { @@ -113,11 +112,7 @@ void __init kirkwood_setup_cpu_mbus(void) setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, TARGET_DEV_BUS, ATTR_DEV_NAND, -1); - /* - * Setup window for SRAM. - */ - setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, - TARGET_SRAM, ATTR_SRAM, -1); + win_alloc_count = 3; /* * Setup MBUS dram target info. @@ -145,3 +140,8 @@ void __init kirkwood_setup_cpu_mbus(void) } kirkwood_mbus_dram_info.num_cs = cs; } + +void __init kirkwood_setup_sram_win(u32 base, u32 size) +{ + setup_cpu_win(win_alloc_count++, base, size, 0x03, 0x00, -1); +} diff --git a/trunk/arch/arm/mach-kirkwood/common.c b/trunk/arch/arm/mach-kirkwood/common.c index 0f6919838011..eeb00240d784 100644 --- a/trunk/arch/arm/mach-kirkwood/common.c +++ b/trunk/arch/arm/mach-kirkwood/common.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -30,7 +29,6 @@ #include #include #include -#include #include #include "common.h" @@ -56,13 +54,6 @@ void __init kirkwood_map_io(void) iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); } -/* - * Default clock control bits. Any bit _not_ set in this variable - * will be cleared from the hardware after platform devices have been - * registered. Some reserved bits must be set to 1. - */ -unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; - /***************************************************************************** * EHCI @@ -104,7 +95,6 @@ static struct platform_device kirkwood_ehci = { void __init kirkwood_ehci_init(void) { - kirkwood_clk_ctrl |= CGC_USB0; platform_device_register(&kirkwood_ehci); } @@ -154,14 +144,10 @@ static struct platform_device kirkwood_ge00 = { .id = 0, .num_resources = 1, .resource = kirkwood_ge00_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, }; void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - kirkwood_clk_ctrl |= CGC_GE0; eth_data->shared = &kirkwood_ge00_shared; kirkwood_ge00.dev.platform_data = eth_data; @@ -216,14 +202,10 @@ static struct platform_device kirkwood_ge01 = { .id = 1, .num_resources = 1, .resource = kirkwood_ge01_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, }; void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) { - kirkwood_clk_ctrl |= CGC_GE1; eth_data->shared = &kirkwood_ge01_shared; kirkwood_ge01.dev.platform_data = eth_data; @@ -269,43 +251,6 @@ void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) } -/***************************************************************************** - * NAND flash - ****************************************************************************/ -static struct resource kirkwood_nand_resource = { - .flags = IORESOURCE_MEM, - .start = KIRKWOOD_NAND_MEM_PHYS_BASE, - .end = KIRKWOOD_NAND_MEM_PHYS_BASE + - KIRKWOOD_NAND_MEM_SIZE - 1, -}; - -static struct orion_nand_data kirkwood_nand_data = { - .cle = 0, - .ale = 1, - .width = 8, -}; - -static struct platform_device kirkwood_nand_flash = { - .name = "orion_nand", - .id = -1, - .dev = { - .platform_data = &kirkwood_nand_data, - }, - .resource = &kirkwood_nand_resource, - .num_resources = 1, -}; - -void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, - int chip_delay) -{ - kirkwood_clk_ctrl |= CGC_RUNIT; - kirkwood_nand_data.parts = parts; - kirkwood_nand_data.nr_parts = nr_parts; - kirkwood_nand_data.chip_delay = chip_delay; - platform_device_register(&kirkwood_nand_flash); -} - - /***************************************************************************** * SoC RTC ****************************************************************************/ @@ -350,9 +295,6 @@ static struct platform_device kirkwood_sata = { void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) { - kirkwood_clk_ctrl |= CGC_SATA0; - if (sata_data->n_ports > 1) - kirkwood_clk_ctrl |= CGC_SATA1; sata_data->dram = &kirkwood_mbus_dram_info; kirkwood_sata.dev.platform_data = sata_data; platform_device_register(&kirkwood_sata); @@ -398,7 +340,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) else mvsdio_data->clock = 200000000; mvsdio_data->dram = &kirkwood_mbus_dram_info; - kirkwood_clk_ctrl |= CGC_SDIO; kirkwood_sdio.dev.platform_data = mvsdio_data; platform_device_register(&kirkwood_sdio); } @@ -430,7 +371,6 @@ static struct platform_device kirkwood_spi = { void __init kirkwood_spi_init() { - kirkwood_clk_ctrl |= CGC_RUNIT; platform_device_register(&kirkwood_spi); } @@ -446,10 +386,12 @@ static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = { static struct resource kirkwood_i2c_resources[] = { { + .name = "i2c", .start = I2C_PHYS_BASE, .end = I2C_PHYS_BASE + 0x1f, .flags = IORESOURCE_MEM, }, { + .name = "i2c", .start = IRQ_KIRKWOOD_TWSI, .end = IRQ_KIRKWOOD_TWSI, .flags = IORESOURCE_IRQ, @@ -560,43 +502,6 @@ void __init kirkwood_uart1_init(void) } -/***************************************************************************** - * Cryptographic Engines and Security Accelerator (CESA) - ****************************************************************************/ - -static struct resource kirkwood_crypto_res[] = { - { - .name = "regs", - .start = CRYPTO_PHYS_BASE, - .end = CRYPTO_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, - }, { - .name = "sram", - .start = KIRKWOOD_SRAM_PHYS_BASE, - .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "crypto interrupt", - .start = IRQ_KIRKWOOD_CRYPTO, - .end = IRQ_KIRKWOOD_CRYPTO, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_crypto_device = { - .name = "mv_crypto", - .id = -1, - .num_resources = ARRAY_SIZE(kirkwood_crypto_res), - .resource = kirkwood_crypto_res, -}; - -void __init kirkwood_crypto_init(void) -{ - kirkwood_clk_ctrl |= CGC_CRYPTO; - platform_device_register(&kirkwood_crypto_device); -} - - /***************************************************************************** * XOR ****************************************************************************/ @@ -688,7 +593,6 @@ static struct platform_device kirkwood_xor01_channel = { static void __init kirkwood_xor0_init(void) { - kirkwood_clk_ctrl |= CGC_XOR0; platform_device_register(&kirkwood_xor0_shared); /* @@ -787,7 +691,6 @@ static struct platform_device kirkwood_xor11_channel = { static void __init kirkwood_xor1_init(void) { - kirkwood_clk_ctrl |= CGC_XOR1; platform_device_register(&kirkwood_xor1_shared); /* @@ -805,29 +708,6 @@ static void __init kirkwood_xor1_init(void) } -/***************************************************************************** - * Watchdog - ****************************************************************************/ -static struct orion_wdt_platform_data kirkwood_wdt_data = { - .tclk = 0, -}; - -static struct platform_device kirkwood_wdt_device = { - .name = "orion_wdt", - .id = -1, - .dev = { - .platform_data = &kirkwood_wdt_data, - }, - .num_resources = 0, -}; - -static void __init kirkwood_wdt_init(void) -{ - kirkwood_wdt_data.tclk = kirkwood_tclk; - platform_device_register(&kirkwood_wdt_device); -} - - /***************************************************************************** * Time handling ****************************************************************************/ @@ -920,49 +800,6 @@ void __init kirkwood_init(void) /* internal devices that every board has */ kirkwood_rtc_init(); - kirkwood_wdt_init(); kirkwood_xor0_init(); kirkwood_xor1_init(); - kirkwood_crypto_init(); -} - -static int __init kirkwood_clock_gate(void) -{ - unsigned int curr = readl(CLOCK_GATING_CTRL); - - printk(KERN_DEBUG "Gating clock of unused units\n"); - printk(KERN_DEBUG "before: 0x%08x\n", curr); - - /* Make sure those units are accessible */ - writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL); - - /* For SATA: first shutdown the phy */ - if (!(kirkwood_clk_ctrl & CGC_SATA0)) { - /* Disable PLL and IVREF */ - writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2); - /* Disable PHY */ - writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL); - } - if (!(kirkwood_clk_ctrl & CGC_SATA1)) { - /* Disable PLL and IVREF */ - writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2); - /* Disable PHY */ - writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL); - } - - /* For PCIe: first shutdown the phy */ - if (!(kirkwood_clk_ctrl & CGC_PEX0)) { - writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL); - while (1) - if (readl(PCIE_STATUS) & 0x1) - break; - writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); - } - - /* Now gate clock the required units */ - writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL); - printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL)); - - return 0; } -late_initcall(kirkwood_clock_gate); diff --git a/trunk/arch/arm/mach-kirkwood/common.h b/trunk/arch/arm/mach-kirkwood/common.h index d7de43464358..6ee88406f381 100644 --- a/trunk/arch/arm/mach-kirkwood/common.h +++ b/trunk/arch/arm/mach-kirkwood/common.h @@ -15,7 +15,6 @@ struct dsa_platform_data; struct mv643xx_eth_platform_data; struct mv_sata_platform_data; struct mvsdio_platform_data; -struct mtd_partition; /* * Basic Kirkwood init functions used early by machine-setup. @@ -26,6 +25,7 @@ void kirkwood_init_irq(void); extern struct mbus_dram_target_info kirkwood_mbus_dram_info; void kirkwood_setup_cpu_mbus(void); +void kirkwood_setup_sram_win(u32 base, u32 size); void kirkwood_pcie_id(u32 *dev, u32 *rev); @@ -40,11 +40,9 @@ void kirkwood_spi_init(void); void kirkwood_i2c_init(void); void kirkwood_uart0_init(void); void kirkwood_uart1_init(void); -void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay); extern int kirkwood_tclk; extern struct sys_timer kirkwood_timer; -#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) #endif diff --git a/trunk/arch/arm/mach-kirkwood/cpuidle.c b/trunk/arch/arm/mach-kirkwood/cpuidle.c deleted file mode 100644 index f68d33f1f396..000000000000 --- a/trunk/arch/arm/mach-kirkwood/cpuidle.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/arm/mach-kirkwood/cpuidle.c - * - * CPU idle Marvell Kirkwood SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * The cpu idle uses wait-for-interrupt and DDR self refresh in order - * to implement two idle states - - * #1 wait-for-interrupt - * #2 wait-for-interrupt and DDR self refresh - */ - -#include -#include -#include -#include -#include -#include -#include - -#define KIRKWOOD_MAX_STATES 2 - -static struct cpuidle_driver kirkwood_idle_driver = { - .name = "kirkwood_idle", - .owner = THIS_MODULE, -}; - -static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device); - -/* Actual code that puts the SoC in different idle states */ -static int kirkwood_enter_idle(struct cpuidle_device *dev, - struct cpuidle_state *state) -{ - struct timeval before, after; - int idle_time; - - local_irq_disable(); - do_gettimeofday(&before); - if (state == &dev->states[0]) - /* Wait for interrupt state */ - cpu_do_idle(); - else if (state == &dev->states[1]) { - /* - * Following write will put DDR in self refresh. - * Note that we have 256 cycles before DDR puts it - * self in self-refresh, so the wait-for-interrupt - * call afterwards won't get the DDR from self refresh - * mode. - */ - writel(0x7, DDR_OPERATION_BASE); - cpu_do_idle(); - } - do_gettimeofday(&after); - local_irq_enable(); - idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + - (after.tv_usec - before.tv_usec); - return idle_time; -} - -/* Initialize CPU idle by registering the idle states */ -static int kirkwood_init_cpuidle(void) -{ - struct cpuidle_device *device; - - cpuidle_register_driver(&kirkwood_idle_driver); - - device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id()); - device->state_count = KIRKWOOD_MAX_STATES; - - /* Wait for interrupt state */ - device->states[0].enter = kirkwood_enter_idle; - device->states[0].exit_latency = 1; - device->states[0].target_residency = 10000; - device->states[0].flags = CPUIDLE_FLAG_TIME_VALID; - strcpy(device->states[0].name, "WFI"); - strcpy(device->states[0].desc, "Wait for interrupt"); - - /* Wait for interrupt and DDR self refresh state */ - device->states[1].enter = kirkwood_enter_idle; - device->states[1].exit_latency = 10; - device->states[1].target_residency = 10000; - device->states[1].flags = CPUIDLE_FLAG_TIME_VALID; - strcpy(device->states[1].name, "DDR SR"); - strcpy(device->states[1].desc, "WFI and DDR Self Refresh"); - - if (cpuidle_register_device(device)) { - printk(KERN_ERR "kirkwood_init_cpuidle: Failed registering\n"); - return -EIO; - } - return 0; -} - -device_initcall(kirkwood_init_cpuidle); diff --git a/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c index 39bdf4bcace9..5505d5837752 100644 --- a/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ b/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c @@ -11,12 +11,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include "common.h" #include "mpp.h" @@ -37,6 +39,32 @@ static struct mtd_partition db88f6281_nand_parts[] = { }, }; +static struct resource db88f6281_nand_resource = { + .flags = IORESOURCE_MEM, + .start = KIRKWOOD_NAND_MEM_PHYS_BASE, + .end = KIRKWOOD_NAND_MEM_PHYS_BASE + + KIRKWOOD_NAND_MEM_SIZE - 1, +}; + +static struct orion_nand_data db88f6281_nand_data = { + .parts = db88f6281_nand_parts, + .nr_parts = ARRAY_SIZE(db88f6281_nand_parts), + .cle = 0, + .ale = 1, + .width = 8, + .chip_delay = 25, +}; + +static struct platform_device db88f6281_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &db88f6281_nand_data, + }, + .resource = &db88f6281_nand_resource, + .num_resources = 1, +}; + static struct mv643xx_eth_platform_data db88f6281_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; @@ -64,12 +92,13 @@ static void __init db88f6281_init(void) kirkwood_init(); kirkwood_mpp_conf(db88f6281_mpp_config); - kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25); kirkwood_ehci_init(); kirkwood_ge00_init(&db88f6281_ge00_data); kirkwood_sata_init(&db88f6281_sata_data); kirkwood_uart0_init(); kirkwood_sdio_init(&db88f6281_mvsdio_data); + + platform_device_register(&db88f6281_nand_flash); } static int __init db88f6281_pci_init(void) diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/trunk/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 9e80d9232c83..4f7029f521cc 100644 --- a/trunk/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/trunk/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -17,15 +17,12 @@ #define CPU_RESET 0x00000002 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) -#define WDT_RESET_OUT_EN 0x00000002 #define SOFT_RESET_OUT_EN 0x00000004 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) #define SOFT_RESET 0x00000001 #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) -#define WDT_INT_REQ 0x0008 - #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) #define BRIDGE_INT_TIMER0 0x0002 #define BRIDGE_INT_TIMER1 0x0004 @@ -42,22 +39,4 @@ #define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) #define L2_WRITETHROUGH 0x00000010 -#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) -#define CGC_GE0 (1 << 0) -#define CGC_PEX0 (1 << 2) -#define CGC_USB0 (1 << 3) -#define CGC_SDIO (1 << 4) -#define CGC_TSU (1 << 5) -#define CGC_DUNIT (1 << 6) -#define CGC_RUNIT (1 << 7) -#define CGC_XOR0 (1 << 8) -#define CGC_AUDIO (1 << 9) -#define CGC_SATA0 (1 << 14) -#define CGC_SATA1 (1 << 15) -#define CGC_XOR1 (1 << 16) -#define CGC_CRYPTO (1 << 17) -#define CGC_GE1 (1 << 19) -#define CGC_TDM (1 << 20) -#define CGC_RESERVED ((1 << 18) | (0x6 << 21)) - #endif diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/io.h b/trunk/arch/arm/mach-kirkwood/include/mach/io.h index a643a846d5fb..be07be0ef522 100644 --- a/trunk/arch/arm/mach-kirkwood/include/mach/io.h +++ b/trunk/arch/arm/mach-kirkwood/include/mach/io.h @@ -19,31 +19,6 @@ static inline void __iomem *__io(unsigned long addr) + KIRKWOOD_PCIE_IO_VIRT_BASE); } -static inline void __iomem * -__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) -{ - void __iomem *retval; - unsigned long offs = paddr - KIRKWOOD_REGS_PHYS_BASE; - if (mtype == MT_DEVICE && size && offs < KIRKWOOD_REGS_SIZE && - size <= KIRKWOOD_REGS_SIZE && offs + size <= KIRKWOOD_REGS_SIZE) { - retval = (void __iomem *)KIRKWOOD_REGS_VIRT_BASE + offs; - } else { - retval = __arm_ioremap(paddr, size, mtype); - } - - return retval; -} - -static inline void -__arch_iounmap(void __iomem *addr) -{ - if (addr < (void __iomem *)KIRKWOOD_REGS_VIRT_BASE || - addr >= (void __iomem *)(KIRKWOOD_REGS_VIRT_BASE + KIRKWOOD_REGS_SIZE)) - __iounmap(addr); -} - -#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) -#define __arch_iounmap(a) __arch_iounmap(a) #define __io(a) __io(a) #define __mem_pci(a) (a) diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h index 07af858814a0..b3e13958821d 100644 --- a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -20,18 +20,16 @@ * f1000000 on-chip peripheral registers * f2000000 PCIe I/O space * f3000000 NAND controller address window - * f4000000 Security Accelerator SRAM * * virt phys size * fee00000 f1000000 1M on-chip peripheral registers * fef00000 f2000000 1M PCIe I/O space */ -#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000 -#define KIRKWOOD_SRAM_SIZE SZ_2K - #define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 -#define KIRKWOOD_NAND_MEM_SIZE SZ_1K +#define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K + * is the minimal window size + */ #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 #define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 @@ -50,7 +48,6 @@ */ #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418) #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) @@ -66,11 +63,7 @@ #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) -#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000) - #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) -#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) -#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) @@ -87,11 +80,6 @@ #define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) -#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000) -#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050) -#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330) -#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050) -#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330) #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) diff --git a/trunk/arch/arm/mach-kirkwood/mpp.c b/trunk/arch/arm/mach-kirkwood/mpp.c index a5900f64e38c..63c44934391a 100644 --- a/trunk/arch/arm/mach-kirkwood/mpp.c +++ b/trunk/arch/arm/mach-kirkwood/mpp.c @@ -48,9 +48,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list) if (!variant_mask) return; - /* Initialize gpiolib. */ - orion_gpio_init(); - printk(KERN_DEBUG "initial MPP regs:"); for (i = 0; i < MPP_NR_REGS; i++) { mpp_ctrl[i] = readl(MPP_CTRL(i)); diff --git a/trunk/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/trunk/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c deleted file mode 100644 index 0358f45766cb..000000000000 --- a/trunk/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c - * - * Marvell 88F6281 GTW GE Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" - -static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = { - .port_names[0] = "lan1", - .port_names[1] = "lan2", - .port_names[2] = "lan3", - .port_names[3] = "lan4", - .port_names[4] = "wan", - .port_names[5] = "cpu", -}; - -static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = { - .nr_chips = 1, - .chip = &mv88f6281gtw_ge_switch_chip_data, -}; - -static const struct flash_platform_data mv88f6281gtw_ge_spi_slave_data = { - .type = "mx25l12805d", -}; - -static struct spi_board_info __initdata mv88f6281gtw_ge_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &mv88f6281gtw_ge_spi_slave_data, - .irq = -1, - .max_speed_hz = 50000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static struct gpio_keys_button mv88f6281gtw_ge_button_pins[] = { - { - .code = KEY_RESTART, - .gpio = 47, - .desc = "SWR Button", - .active_low = 1, - }, { - .code = KEY_F1, - .gpio = 46, - .desc = "WPS Button(F1)", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data mv88f6281gtw_ge_button_data = { - .buttons = mv88f6281gtw_ge_button_pins, - .nbuttons = ARRAY_SIZE(mv88f6281gtw_ge_button_pins), -}; - -static struct platform_device mv88f6281gtw_ge_buttons = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &mv88f6281gtw_ge_button_data, - }, -}; - -static struct gpio_led mv88f6281gtw_ge_led_pins[] = { - { - .name = "gtw:green:Status", - .gpio = 20, - .active_low = 0, - }, { - .name = "gtw:red:Status", - .gpio = 21, - .active_low = 0, - }, { - .name = "gtw:green:USB", - .gpio = 12, - .active_low = 0, - }, -}; - -static struct gpio_led_platform_data mv88f6281gtw_ge_led_data = { - .leds = mv88f6281gtw_ge_led_pins, - .num_leds = ARRAY_SIZE(mv88f6281gtw_ge_led_pins), -}; - -static struct platform_device mv88f6281gtw_ge_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &mv88f6281gtw_ge_led_data, - }, -}; - -static unsigned int mv88f6281gtw_ge_mpp_config[] __initdata = { - MPP12_GPO, /* Status#_USB pin */ - MPP20_GPIO, /* Status#_GLED pin */ - MPP21_GPIO, /* Status#_RLED pin */ - MPP46_GPIO, /* WPS_Switch pin */ - MPP47_GPIO, /* SW_Init pin */ - 0 -}; - -static void __init mv88f6281gtw_ge_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(mv88f6281gtw_ge_mpp_config); - - kirkwood_ehci_init(); - kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data); - kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ); - spi_register_board_info(mv88f6281gtw_ge_spi_slave_info, - ARRAY_SIZE(mv88f6281gtw_ge_spi_slave_info)); - kirkwood_spi_init(); - kirkwood_uart0_init(); - platform_device_register(&mv88f6281gtw_ge_leds); - platform_device_register(&mv88f6281gtw_ge_buttons); -} - -static int __init mv88f6281gtw_ge_pci_init(void) -{ - if (machine_is_mv88f6281gtw_ge()) - kirkwood_pcie_init(); - - return 0; -} -subsys_initcall(mv88f6281gtw_ge_pci_init); - -MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board") - /* Maintainer: Lennert Buytenhek */ - .phys_io = KIRKWOOD_REGS_PHYS_BASE, - .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = mv88f6281gtw_ge_init, - .map_io = kirkwood_map_io, - .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-kirkwood/pcie.c b/trunk/arch/arm/mach-kirkwood/pcie.c index d90b9aae308d..73fccacd1a73 100644 --- a/trunk/arch/arm/mach-kirkwood/pcie.c +++ b/trunk/arch/arm/mach-kirkwood/pcie.c @@ -14,7 +14,6 @@ #include #include #include -#include #include "common.h" @@ -96,7 +95,6 @@ static struct pci_ops pcie_ops = { static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) { struct resource *res; - extern unsigned int kirkwood_clk_ctrl; /* * Generic PCIe unit setup. @@ -135,8 +133,6 @@ static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) sys->resource[2] = NULL; sys->io_offset = 0; - kirkwood_clk_ctrl |= CGC_PEX0; - return 1; } diff --git a/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c index 8bf4153d0840..2f0e4ef3db0f 100644 --- a/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c +++ b/trunk/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include #include diff --git a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c index 31708ddbc83e..31e996d65fc4 100644 --- a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -21,6 +22,7 @@ #include #include #include +#include #include "common.h" #include "mpp.h" @@ -40,6 +42,32 @@ static struct mtd_partition rd88f6281_nand_parts[] = { }, }; +static struct resource rd88f6281_nand_resource = { + .flags = IORESOURCE_MEM, + .start = KIRKWOOD_NAND_MEM_PHYS_BASE, + .end = KIRKWOOD_NAND_MEM_PHYS_BASE + + KIRKWOOD_NAND_MEM_SIZE - 1, +}; + +static struct orion_nand_data rd88f6281_nand_data = { + .parts = rd88f6281_nand_parts, + .nr_parts = ARRAY_SIZE(rd88f6281_nand_parts), + .cle = 0, + .ale = 1, + .width = 8, + .chip_delay = 25, +}; + +static struct platform_device rd88f6281_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &rd88f6281_nand_data, + }, + .resource = &rd88f6281_nand_resource, + .num_resources = 1, +}; + static struct mv643xx_eth_platform_data rd88f6281_ge00_data = { .phy_addr = MV643XX_ETH_PHY_NONE, .speed = SPEED_1000, @@ -86,7 +114,6 @@ static void __init rd88f6281_init(void) kirkwood_init(); kirkwood_mpp_conf(rd88f6281_mpp_config); - kirkwood_nand_init(ARRAY_AND_SIZE(rd88f6281_nand_parts), 25); kirkwood_ehci_init(); kirkwood_ge00_init(&rd88f6281_ge00_data); @@ -102,6 +129,8 @@ static void __init rd88f6281_init(void) kirkwood_sata_init(&rd88f6281_sata_data); kirkwood_sdio_init(&rd88f6281_mvsdio_data); kirkwood_uart0_init(); + + platform_device_register(&rd88f6281_nand_flash); } static int __init rd88f6281_pci_init(void) diff --git a/trunk/arch/arm/mach-kirkwood/sheevaplug-setup.c b/trunk/arch/arm/mach-kirkwood/sheevaplug-setup.c index c7319eeac8bb..831e4a56cae1 100644 --- a/trunk/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/trunk/arch/arm/mach-kirkwood/sheevaplug-setup.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include "common.h" #include "mpp.h" @@ -38,12 +40,38 @@ static struct mtd_partition sheevaplug_nand_parts[] = { }, }; +static struct resource sheevaplug_nand_resource = { + .flags = IORESOURCE_MEM, + .start = KIRKWOOD_NAND_MEM_PHYS_BASE, + .end = KIRKWOOD_NAND_MEM_PHYS_BASE + + KIRKWOOD_NAND_MEM_SIZE - 1, +}; + +static struct orion_nand_data sheevaplug_nand_data = { + .parts = sheevaplug_nand_parts, + .nr_parts = ARRAY_SIZE(sheevaplug_nand_parts), + .cle = 0, + .ale = 1, + .width = 8, + .chip_delay = 25, +}; + +static struct platform_device sheevaplug_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &sheevaplug_nand_data, + }, + .resource = &sheevaplug_nand_resource, + .num_resources = 1, +}; + static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; static struct mvsdio_platform_data sheevaplug_mvsdio_data = { - /* unfortunately the CD signal has not been connected */ + // unfortunately the CD signal has not been connected */ }; static struct gpio_led sheevaplug_led_pins[] = { @@ -83,7 +111,6 @@ static void __init sheevaplug_init(void) kirkwood_mpp_conf(sheevaplug_mpp_config); kirkwood_uart0_init(); - kirkwood_nand_init(ARRAY_AND_SIZE(sheevaplug_nand_parts), 25); if (gpio_request(29, "USB Power Enable") != 0 || gpio_direction_output(29, 1) != 0) @@ -93,6 +120,7 @@ static void __init sheevaplug_init(void) kirkwood_ge00_init(&sheevaplug_ge00_data); kirkwood_sdio_init(&sheevaplug_mvsdio_data); + platform_device_register(&sheevaplug_nand_flash); platform_device_register(&sheevaplug_leds); } diff --git a/trunk/arch/arm/mach-kirkwood/ts219-setup.c b/trunk/arch/arm/mach-kirkwood/ts219-setup.c index 01aa213c0a6f..dda5743cf3e0 100644 --- a/trunk/arch/arm/mach-kirkwood/ts219-setup.c +++ b/trunk/arch/arm/mach-kirkwood/ts219-setup.c @@ -142,8 +142,6 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP1_SPI_MOSI, MPP2_SPI_SCK, MPP3_SPI_MISO, - MPP4_SATA1_ACTn, - MPP5_SATA0_ACTn, MPP8_TW_SDA, MPP9_TW_SCK, MPP10_UART0_TXD, @@ -152,6 +150,10 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP14_UART1_RXD, /* PIC controller */ MPP15_GPIO, /* USB Copy button */ MPP16_GPIO, /* Reset button */ + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_SATA1_PRESENTn, + MPP23_SATA0_PRESENTn, 0 }; diff --git a/trunk/arch/arm/mach-loki/common.c b/trunk/arch/arm/mach-loki/common.c index 818f19d7ab1f..c0d2d9d12e74 100644 --- a/trunk/arch/arm/mach-loki/common.c +++ b/trunk/arch/arm/mach-loki/common.c @@ -82,9 +82,6 @@ static struct platform_device loki_ge0 = { .id = 0, .num_resources = 1, .resource = loki_ge0_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, }; void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data) @@ -139,9 +136,6 @@ static struct platform_device loki_ge1 = { .id = 1, .num_resources = 1, .resource = loki_ge1_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, }; void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data) diff --git a/trunk/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/trunk/arch/arm/mach-mmp/include/mach/mfp-pxa168.h index 2e914649b9e4..d0bdb6e3682b 100644 --- a/trunk/arch/arm/mach-mmp/include/mach/mfp-pxa168.h +++ b/trunk/arch/arm/mach-mmp/include/mach/mfp-pxa168.h @@ -3,11 +3,6 @@ #include -#define MFP_DRIVE_VERY_SLOW (0x0 << 13) -#define MFP_DRIVE_SLOW (0x1 << 13) -#define MFP_DRIVE_MEDIUM (0x2 << 13) -#define MFP_DRIVE_FAST (0x3 << 13) - /* GPIO */ #define GPIO0_GPIO MFP_CFG(GPIO0, AF5) #define GPIO1_GPIO MFP_CFG(GPIO1, AF5) diff --git a/trunk/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/trunk/arch/arm/mach-mmp/include/mach/mfp-pxa910.h index d97de36c50ad..48a1cbc7c56b 100644 --- a/trunk/arch/arm/mach-mmp/include/mach/mfp-pxa910.h +++ b/trunk/arch/arm/mach-mmp/include/mach/mfp-pxa910.h @@ -3,11 +3,6 @@ #include -#define MFP_DRIVE_VERY_SLOW (0x0 << 13) -#define MFP_DRIVE_SLOW (0x2 << 13) -#define MFP_DRIVE_MEDIUM (0x4 << 13) -#define MFP_DRIVE_FAST (0x8 << 13) - /* UART2 */ #define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) #define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6) diff --git a/trunk/arch/arm/mach-mmp/include/mach/mfp.h b/trunk/arch/arm/mach-mmp/include/mach/mfp.h index 62e510e80a58..277ea4cd0f9f 100644 --- a/trunk/arch/arm/mach-mmp/include/mach/mfp.h +++ b/trunk/arch/arm/mach-mmp/include/mach/mfp.h @@ -12,13 +12,16 @@ * possible, we make the following compromise: * * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT) - * 2. DRIVE strength definitions redefined to include the reserved bit - * - the reserved bit differs between pxa168 and pxa910, and the - * MFP_DRIVE_* macros are individually defined in mfp-pxa{168,910}.h + * 2. DRIVE strength definitions redefined to include the reserved bit10 * 3. Override MFP_CFG() and MFP_CFG_DRV() * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X() */ +#define MFP_DRIVE_VERY_SLOW (0x0 << 13) +#define MFP_DRIVE_SLOW (0x2 << 13) +#define MFP_DRIVE_MEDIUM (0x4 << 13) +#define MFP_DRIVE_FAST (0x8 << 13) + #undef MFP_CFG #undef MFP_CFG_DRV #undef MFP_CFG_LPM diff --git a/trunk/arch/arm/mach-mmp/time.c b/trunk/arch/arm/mach-mmp/time.c index a8400bb891e7..b03a6eda7419 100644 --- a/trunk/arch/arm/mach-mmp/time.c +++ b/trunk/arch/arm/mach-mmp/time.c @@ -136,7 +136,7 @@ static struct clock_event_device ckevt = { .set_mode = timer_set_mode, }; -static cycle_t clksrc_read(struct clocksource *cs) +static cycle_t clksrc_read(void) { return timer_read(); } diff --git a/trunk/arch/arm/mach-mv78xx0/common.c b/trunk/arch/arm/mach-mv78xx0/common.c index 1b22e4af8791..9ba595083dab 100644 --- a/trunk/arch/arm/mach-mv78xx0/common.c +++ b/trunk/arch/arm/mach-mv78xx0/common.c @@ -321,9 +321,6 @@ static struct platform_device mv78xx0_ge00 = { .id = 0, .num_resources = 1, .resource = mv78xx0_ge00_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, }; void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) @@ -378,9 +375,6 @@ static struct platform_device mv78xx0_ge01 = { .id = 1, .num_resources = 1, .resource = mv78xx0_ge01_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, }; void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) @@ -435,9 +429,6 @@ static struct platform_device mv78xx0_ge10 = { .id = 2, .num_resources = 1, .resource = mv78xx0_ge10_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, }; void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) @@ -505,9 +496,6 @@ static struct platform_device mv78xx0_ge11 = { .id = 3, .num_resources = 1, .resource = mv78xx0_ge11_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, }; void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) @@ -544,10 +532,12 @@ static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = { static struct resource mv78xx0_i2c_0_resources[] = { { + .name = "i2c 0 base", .start = I2C_0_PHYS_BASE, .end = I2C_0_PHYS_BASE + 0x1f, .flags = IORESOURCE_MEM, }, { + .name = "i2c 0 irq", .start = IRQ_MV78XX0_I2C_0, .end = IRQ_MV78XX0_I2C_0, .flags = IORESOURCE_IRQ, @@ -577,10 +567,12 @@ static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = { static struct resource mv78xx0_i2c_1_resources[] = { { + .name = "i2c 1 base", .start = I2C_1_PHYS_BASE, .end = I2C_1_PHYS_BASE + 0x1f, .flags = IORESOURCE_MEM, }, { + .name = "i2c 1 irq", .start = IRQ_MV78XX0_I2C_1, .end = IRQ_MV78XX0_I2C_1, .flags = IORESOURCE_IRQ, diff --git a/trunk/arch/arm/mach-mv78xx0/irq.c b/trunk/arch/arm/mach-mv78xx0/irq.c index 22b4ff893b3c..f289b0ea7dcf 100644 --- a/trunk/arch/arm/mach-mv78xx0/irq.c +++ b/trunk/arch/arm/mach-mv78xx0/irq.c @@ -28,9 +28,6 @@ void __init mv78xx0_init_irq(void) { int i; - /* Initialize gpiolib. */ - orion_gpio_init(); - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); diff --git a/trunk/arch/arm/mach-mx1/generic.c b/trunk/arch/arm/mach-mx1/generic.c index 7622c9b38c97..0dec6f300ffc 100644 --- a/trunk/arch/arm/mach-mx1/generic.c +++ b/trunk/arch/arm/mach-mx1/generic.c @@ -26,7 +26,6 @@ #include -#include #include static struct map_desc imx_io_desc[] __initdata = { @@ -38,9 +37,7 @@ static struct map_desc imx_io_desc[] __initdata = { } }; -void __init mx1_map_io(void) +void __init mxc_map_io(void) { - mxc_set_cpu_type(MXC_CPU_MX1); - iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); } diff --git a/trunk/arch/arm/mach-mx1/mx1ads.c b/trunk/arch/arm/mach-mx1/mx1ads.c index e5b0c0a83c3b..e54057fb855b 100644 --- a/trunk/arch/arm/mach-mx1/mx1ads.c +++ b/trunk/arch/arm/mach-mx1/mx1ads.c @@ -12,56 +12,77 @@ * warranty of any kind, whether express or implied. */ -#include -#include -#include #include +#include #include #include +#include +#include #include #include #include -#include +#include #include -#include +#include #include -#include #include - +#include +#include #include "devices.h" -static int mx1ads_pins[] = { - /* UART1 */ +/* + * UARTs platform data + */ +static int mxc_uart1_pins[] = { PC9_PF_UART1_CTS, PC10_PF_UART1_RTS, PC11_PF_UART1_TXD, PC12_PF_UART1_RXD, - /* UART2 */ +}; + +static int uart1_mxc_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins), "UART1"); +} + +static int uart1_mxc_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins)); + return 0; +} + +static int mxc_uart2_pins[] = { PB28_PF_UART2_CTS, PB29_PF_UART2_RTS, PB30_PF_UART2_TXD, PB31_PF_UART2_RXD, - /* I2C */ - PA15_PF_I2C_SDA, - PA16_PF_I2C_SCL, - /* SPI */ - PC13_PF_SPI1_SPI_RDY, - PC14_PF_SPI1_SCLK, - PC15_PF_SPI1_SS, - PC16_PF_SPI1_MISO, - PC17_PF_SPI1_MOSI, }; -/* - * UARTs platform data - */ +static int uart2_mxc_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins), "UART2"); +} + +static int uart2_mxc_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins)); + return 0; +} static struct imxuart_platform_data uart_pdata[] = { { + .init = uart1_mxc_init, + .exit = uart1_mxc_exit, .flags = IMXUART_HAVE_RTSCTS, }, { + .init = uart2_mxc_init, + .exit = uart2_mxc_exit, .flags = IMXUART_HAVE_RTSCTS, }, }; @@ -90,6 +111,24 @@ static struct platform_device flash_device = { /* * I2C */ + +static int i2c_pins[] = { + PA15_PF_I2C_SDA, + PA16_PF_I2C_SCL, +}; + +static int i2c_init(struct device *dev) +{ + return mxc_gpio_setup_multiple_pins(i2c_pins, + ARRAY_SIZE(i2c_pins), "I2C"); +} + +static void i2c_exit(struct device *dev) +{ + mxc_gpio_release_multiple_pins(i2c_pins, + ARRAY_SIZE(i2c_pins)); +} + static struct pcf857x_platform_data pcf857x_data[] = { { .gpio_base = 4 * 32, @@ -100,6 +139,8 @@ static struct pcf857x_platform_data pcf857x_data[] = { static struct imxi2c_platform_data mx1ads_i2c_data = { .bitrate = 100000, + .init = i2c_init, + .exit = i2c_exit, }; static struct i2c_board_info mx1ads_i2c_devices[] = { @@ -119,9 +160,6 @@ static struct i2c_board_info mx1ads_i2c_devices[] = { */ static void __init mx1ads_init(void) { - mxc_gpio_setup_multiple_pins(mx1ads_pins, - ARRAY_SIZE(mx1ads_pins), "mx1ads"); - /* UART */ mxc_register_device(&imx_uart1_device, &uart_pdata[0]); mxc_register_device(&imx_uart2_device, &uart_pdata[1]); @@ -150,7 +188,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx1_map_io, + .map_io = mxc_map_io, .init_irq = mxc_init_irq, .timer = &mx1ads_timer, .init_machine = mx1ads_init, @@ -160,7 +198,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS") .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx1_map_io, + .map_io = mxc_map_io, .init_irq = mxc_init_irq, .timer = &mx1ads_timer, .init_machine = mx1ads_init, diff --git a/trunk/arch/arm/mach-mx1/scb9328.c b/trunk/arch/arm/mach-mx1/scb9328.c index 20e0b5bcdffc..0e71f3fa28bf 100644 --- a/trunk/arch/arm/mach-mx1/scb9328.c +++ b/trunk/arch/arm/mach-mx1/scb9328.c @@ -153,7 +153,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328") .phys_io = 0x00200000, .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc, .boot_params = 0x08000100, - .map_io = mx1_map_io, + .map_io = mxc_map_io, .init_irq = mxc_init_irq, .timer = &scb9328_timer, .init_machine = scb9328_init, diff --git a/trunk/arch/arm/mach-mx2/Kconfig b/trunk/arch/arm/mach-mx2/Kconfig index c77da586b71d..42a788842f49 100644 --- a/trunk/arch/arm/mach-mx2/Kconfig +++ b/trunk/arch/arm/mach-mx2/Kconfig @@ -18,13 +18,6 @@ endchoice comment "MX2 platforms:" -config MACH_MX21ADS - bool "MX21ADS platform" - depends on MACH_MX21 - help - Include support for MX21ADS platform. This includes specific - configurations for the board and its peripherals. - config MACH_MX27ADS bool "MX27ADS platform" depends on MACH_MX27 @@ -53,18 +46,4 @@ config MACH_PCM970_BASEBOARD endchoice -config MACH_MX27_3DS - bool "MX27PDK platform" - depends on MACH_MX27 - help - Include support for MX27PDK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX27LITE - bool "LogicPD MX27 LITEKIT platform" - depends on MACH_MX27 - help - Include support for MX27 LITEKIT platform. This includes specific - configurations for the board and its peripherals. - endif diff --git a/trunk/arch/arm/mach-mx2/Makefile b/trunk/arch/arm/mach-mx2/Makefile index b9b1cca4e9bc..950649a91540 100644 --- a/trunk/arch/arm/mach-mx2/Makefile +++ b/trunk/arch/arm/mach-mx2/Makefile @@ -11,10 +11,6 @@ obj-$(CONFIG_MACH_MX21) += clock_imx21.o obj-$(CONFIG_MACH_MX27) += cpu_imx27.o obj-$(CONFIG_MACH_MX27) += clock_imx27.o -obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o obj-$(CONFIG_MACH_PCM038) += pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o -obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o -obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o - diff --git a/trunk/arch/arm/mach-mx2/clock_imx21.c b/trunk/arch/arm/mach-mx2/clock_imx21.c index fa2b292d7b3c..999d013e06e3 100644 --- a/trunk/arch/arm/mach-mx2/clock_imx21.c +++ b/trunk/arch/arm/mach-mx2/clock_imx21.c @@ -48,25 +48,6 @@ static void _clk_disable(struct clk *clk) __raw_writel(reg, clk->enable_reg); } -static unsigned long _clk_generic_round_rate(struct clk *clk, - unsigned long rate, - u32 max_divisor) -{ - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (parent_rate % rate) - div++; - - if (div > max_divisor) - div = max_divisor; - - return parent_rate / div; -} - static int _clk_spll_enable(struct clk *clk) { u32 reg; @@ -97,7 +78,19 @@ static void _clk_spll_disable(struct clk *clk) static unsigned long _clk_perclkx_round_rate(struct clk *clk, unsigned long rate) { - return _clk_generic_round_rate(clk, rate, 64); + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div > 64) + div = 64; + + return parent_rate / div; } static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) @@ -137,32 +130,6 @@ static unsigned long _clk_usb_recalc(struct clk *clk) return parent_rate / (usb_pdf + 1U); } -static unsigned long _clk_usb_round_rate(struct clk *clk, - unsigned long rate) -{ - return _clk_generic_round_rate(clk, rate, 8); -} - -static int _clk_usb_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg; - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (div > 8 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - div--; - - reg = CSCR() & ~CCM_CSCR_USB_MASK; - reg |= div << CCM_CSCR_USB_OFFSET; - __raw_writel(reg, CCM_CSCR); - - return 0; -} - static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf) { unsigned long parent_rate; @@ -628,14 +595,11 @@ static struct clk csi_clk[] = { static struct clk usb_clk[] = { { .parent = &spll_clk, - .secondary = &usb_clk[1], .get_rate = _clk_usb_recalc, .enable = _clk_enable, .enable_reg = CCM_PCCR_USBOTG_REG, .enable_shift = CCM_PCCR_USBOTG_OFFSET, .disable = _clk_disable, - .round_rate = _clk_usb_round_rate, - .set_rate = _clk_usb_set_rate, }, { .parent = &hclk_clk, .enable = _clk_enable, @@ -804,7 +768,18 @@ static struct clk rtc_clk = { static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) { - return _clk_generic_round_rate(clk, rate, 8); + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; } static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) @@ -946,7 +921,7 @@ static struct clk_lookup lookups[] __initdata = { _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2]) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0]) _REGISTER_CLOCK(NULL, "csi", csi_clk[0]) - _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0]) + _REGISTER_CLOCK(NULL, "usb", usb_clk[0]) _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0]) _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1]) _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) diff --git a/trunk/arch/arm/mach-mx2/generic.c b/trunk/arch/arm/mach-mx2/generic.c index 169372f69d8f..bd51dd04948e 100644 --- a/trunk/arch/arm/mach-mx2/generic.c +++ b/trunk/arch/arm/mach-mx2/generic.c @@ -69,17 +69,7 @@ static struct map_desc mxc_io_desc[] __initdata = { * system startup to create static physical to virtual * memory map for the IO modules. */ -void __init mx21_map_io(void) +void __init mxc_map_io(void) { - mxc_set_cpu_type(MXC_CPU_MX21); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } - -void __init mx27_map_io(void) -{ - mxc_set_cpu_type(MXC_CPU_MX27); - - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); -} - diff --git a/trunk/arch/arm/mach-mx2/mx21ads.c b/trunk/arch/arm/mach-mx2/mx21ads.c deleted file mode 100644 index a5ee461cb405..000000000000 --- a/trunk/arch/arm/mach-mx2/mx21ads.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -static unsigned int mx21ads_pins[] = { - - /* CS8900A */ - (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11), - - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - - /* UART3 (IrDA) - only TXD and RXD */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - - /* UART4 */ - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, - - /* LCDC */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA24_PF_REV, /* Sharp panel dedicated signal */ - PA25_PF_CLS, /* Sharp panel dedicated signal */ - PA26_PF_PS, /* Sharp panel dedicated signal */ - PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */ - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - - /* MMC/SDHC */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - - /* NFC */ - PF0_PF_NRFB, - PF1_PF_NFCE, - PF2_PF_NFWP, - PF3_PF_NFCLE, - PF4_PF_NFALE, - PF5_PF_NFRE, - PF6_PF_NFWE, - PF7_PF_NFIO0, - PF8_PF_NFIO1, - PF9_PF_NFIO2, - PF10_PF_NFIO3, - PF11_PF_NFIO4, - PF12_PF_NFIO5, - PF13_PF_NFIO6, - PF14_PF_NFIO7, -}; - -/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */ -static struct physmap_flash_data mx21ads_flash_data = { - .width = 4, -}; - -static struct resource mx21ads_flash_resource = { - .start = CS0_BASE_ADDR, - .end = CS0_BASE_ADDR + 0x02000000 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx21ads_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx21ads_flash_data, - }, - .num_resources = 1, - .resource = &mx21ads_flash_resource, -}; - -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct imxuart_platform_data uart_norts_pdata = { -}; - - -static int mx21ads_fb_init(struct platform_device *pdev) -{ - u16 tmp; - - tmp = __raw_readw(MX21ADS_IO_REG); - tmp |= MX21ADS_IO_LCDON; - __raw_writew(tmp, MX21ADS_IO_REG); - return 0; -} - -static void mx21ads_fb_exit(struct platform_device *pdev) -{ - u16 tmp; - - tmp = __raw_readw(MX21ADS_IO_REG); - tmp &= ~MX21ADS_IO_LCDON; - __raw_writew(tmp, MX21ADS_IO_REG); -} - -/* - * Connected is a portrait Sharp-QVGA display - * of type: LQ035Q7DB02 - */ -static struct imx_fb_platform_data mx21ads_fb_data = { - .pixclock = 188679, /* in ps */ - .xres = 240, - .yres = 320, - - .bpp = 16, - .hsync_len = 2, - .left_margin = 6, - .right_margin = 16, - - .vsync_len = 1, - .upper_margin = 8, - .lower_margin = 10, - .fixed_screen_cpu = 0, - - .pcr = 0xFB108BC7, - .pwmr = 0x00A901ff, - .lscr1 = 0x00120300, - .dmacr = 0x00020008, - - .init = mx21ads_fb_init, - .exit = mx21ads_fb_exit, -}; - -static int mx21ads_sdhc_get_ro(struct device *dev) -{ - return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0; -} - -static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = request_irq(IRQ_GPIOD(25), detect_irq, - IRQF_TRIGGER_FALLING, "mmc-detect", data); - if (ret) - goto out; - return 0; -out: - return ret; -} - -static void mx21ads_sdhc_exit(struct device *dev, void *data) -{ - free_irq(IRQ_GPIOD(25), data); -} - -static struct imxmmc_platform_data mx21ads_sdhc_pdata = { - .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ - .get_ro = mx21ads_sdhc_get_ro, - .init = mx21ads_sdhc_init, - .exit = mx21ads_sdhc_exit, -}; - -static struct mxc_nand_platform_data mx21ads_nand_board_info = { - .width = 1, - .hw_ecc = 1, -}; - -static struct map_desc mx21ads_io_desc[] __initdata = { - /* - * Memory-mapped I/O on MX21ADS Base board: - * - CS8900A Ethernet controller - * - ST16C2552CJ UART - * - CPU and Base board version - * - Base board I/O register - */ - { - .virtual = MX21ADS_MMIO_BASE_ADDR, - .pfn = __phys_to_pfn(CS1_BASE_ADDR), - .length = MX21ADS_MMIO_SIZE, - .type = MT_DEVICE, - }, -}; - -static void __init mx21ads_map_io(void) -{ - mx21_map_io(); - iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc)); -} - -static struct platform_device *platform_devices[] __initdata = { - &mx21ads_nor_mtd_device, -}; - -static void __init mx21ads_board_init(void) -{ - mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), - "mx21ads"); - - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_norts_pdata); - mxc_register_device(&mxc_uart_device3, &uart_pdata); - mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); - mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); - mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); -} - -static void __init mx21ads_timer_init(void) -{ - mx21_clocks_init(32768, 26000000); -} - -static struct sys_timer mx21ads_timer = { - .init = mx21ads_timer_init, -}; - -MACHINE_START(MX21ADS, "Freescale i.MX21ADS") - /* maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx21ads_map_io, - .init_irq = mxc_init_irq, - .init_machine = mx21ads_board_init, - .timer = &mx21ads_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-mx2/mx27ads.c b/trunk/arch/arm/mach-mx2/mx27ads.c index 02daddac6995..4a3b097adc12 100644 --- a/trunk/arch/arm/mach-mx2/mx27ads.c +++ b/trunk/arch/arm/mach-mx2/mx27ads.c @@ -23,8 +23,6 @@ #include #include #include -#include -#include #include #include #include @@ -35,117 +33,9 @@ #include #include #include -#include -#include -#include -#include #include "devices.h" -static unsigned int mx27ads_pins[] = { - /* UART0 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART1 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART2 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* UART3 */ - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, - /* UART4 */ - PB18_AF_UART5_TXD, - PB19_AF_UART5_RXD, - PB20_AF_UART5_CTS, - PB21_AF_UART5_RTS, - /* UART5 */ - PB10_AF_UART6_TXD, - PB12_AF_UART6_CTS, - PB11_AF_UART6_RXD, - PB13_AF_UART6_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* FB */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* OWIRE */ - PE16_AF_OWIRE, - /* SDHC1*/ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* SDHC2*/ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, -}; - -static struct mxc_nand_platform_data mx27ads_nand_board_info = { - .width = 1, - .hw_ecc = 1, -}; - /* ADS's NOR flash */ static struct physmap_flash_data mx27ads_flash_data = { .width = 2, @@ -168,113 +58,189 @@ static struct platform_device mx27ads_nor_mtd_device = { .resource = &mx27ads_flash_resource, }; -static struct imxi2c_platform_data mx27ads_i2c_data = { - .bitrate = 100000, +static int mxc_uart0_pins[] = { + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS }; -static struct i2c_board_info mx27ads_i2c_devices[] = { +static int uart_mxc_port0_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, + ARRAY_SIZE(mxc_uart0_pins), "UART0"); +} + +static int uart_mxc_port0_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart0_pins, + ARRAY_SIZE(mxc_uart0_pins)); + return 0; +} + +static int mxc_uart1_pins[] = { + PE3_PF_UART2_CTS, + PE4_PF_UART2_RTS, + PE6_PF_UART2_TXD, + PE7_PF_UART2_RXD }; -void lcd_power(int on) +static int uart_mxc_port1_init(struct platform_device *pdev) { - if (on) - __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); - else - __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); + return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins), "UART1"); } -static struct imx_fb_platform_data mx27ads_fb_data = { - .pixclock = 188679, - .xres = 240, - .yres = 320, - - .bpp = 16, - .hsync_len = 1, - .left_margin = 9, - .right_margin = 16, - - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 9, - .fixed_screen_cpu = 0, - - /* - * - HSYNC active high - * - VSYNC active high - * - clk notenabled while idle - * - clock inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pcr = 0xFB008BC0, - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, - - .lcd_power = lcd_power, +static int uart_mxc_port1_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins)); + return 0; +} + +static int mxc_uart2_pins[] = { + PE8_PF_UART3_TXD, + PE9_PF_UART3_RXD, + PE10_PF_UART3_CTS, + PE11_PF_UART3_RTS }; -static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) +static int uart_mxc_port2_init(struct platform_device *pdev) { - return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING, - "sdhc1-card-detect", data); + return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins), "UART2"); } -static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) +static int uart_mxc_port2_exit(struct platform_device *pdev) { - return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING, - "sdhc2-card-detect", data); + mxc_gpio_release_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins)); + return 0; } -static void mx27ads_sdhc1_exit(struct device *dev, void *data) +static int mxc_uart3_pins[] = { + PB26_AF_UART4_RTS, + PB28_AF_UART4_TXD, + PB29_AF_UART4_CTS, + PB31_AF_UART4_RXD +}; + +static int uart_mxc_port3_init(struct platform_device *pdev) { - free_irq(IRQ_GPIOE(21), data); + return mxc_gpio_setup_multiple_pins(mxc_uart3_pins, + ARRAY_SIZE(mxc_uart3_pins), "UART3"); } -static void mx27ads_sdhc2_exit(struct device *dev, void *data) +static int uart_mxc_port3_exit(struct platform_device *pdev) { - free_irq(IRQ_GPIOB(7), data); + mxc_gpio_release_multiple_pins(mxc_uart3_pins, + ARRAY_SIZE(mxc_uart3_pins)); + return 0; } -static struct imxmmc_platform_data sdhc1_pdata = { - .init = mx27ads_sdhc1_init, - .exit = mx27ads_sdhc1_exit, +static int mxc_uart4_pins[] = { + PB18_AF_UART5_TXD, + PB19_AF_UART5_RXD, + PB20_AF_UART5_CTS, + PB21_AF_UART5_RTS }; -static struct imxmmc_platform_data sdhc2_pdata = { - .init = mx27ads_sdhc2_init, - .exit = mx27ads_sdhc2_exit, +static int uart_mxc_port4_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart4_pins, + ARRAY_SIZE(mxc_uart4_pins), "UART4"); +} + +static int uart_mxc_port4_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart4_pins, + ARRAY_SIZE(mxc_uart4_pins)); + return 0; +} + +static int mxc_uart5_pins[] = { + PB10_AF_UART6_TXD, + PB12_AF_UART6_CTS, + PB11_AF_UART6_RXD, + PB13_AF_UART6_RTS }; +static int uart_mxc_port5_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart5_pins, + ARRAY_SIZE(mxc_uart5_pins), "UART5"); +} + +static int uart_mxc_port5_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart5_pins, + ARRAY_SIZE(mxc_uart5_pins)); + return 0; +} + static struct platform_device *platform_devices[] __initdata = { &mx27ads_nor_mtd_device, &mxc_fec_device, - &mxc_w1_master_device, }; +static int mxc_fec_pins[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN +}; + +static void gpio_fec_active(void) +{ + mxc_gpio_setup_multiple_pins(mxc_fec_pins, + ARRAY_SIZE(mxc_fec_pins), "FEC"); +} + static struct imxuart_platform_data uart_pdata[] = { { + .init = uart_mxc_port0_init, + .exit = uart_mxc_port0_exit, .flags = IMXUART_HAVE_RTSCTS, }, { + .init = uart_mxc_port1_init, + .exit = uart_mxc_port1_exit, .flags = IMXUART_HAVE_RTSCTS, }, { + .init = uart_mxc_port2_init, + .exit = uart_mxc_port2_exit, .flags = IMXUART_HAVE_RTSCTS, }, { + .init = uart_mxc_port3_init, + .exit = uart_mxc_port3_exit, .flags = IMXUART_HAVE_RTSCTS, }, { + .init = uart_mxc_port4_init, + .exit = uart_mxc_port4_exit, .flags = IMXUART_HAVE_RTSCTS, }, { + .init = uart_mxc_port5_init, + .exit = uart_mxc_port5_exit, .flags = IMXUART_HAVE_RTSCTS, }, }; static void __init mx27ads_board_init(void) { - mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), - "mx27ads"); + gpio_fec_active(); mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); @@ -282,15 +248,6 @@ static void __init mx27ads_board_init(void) mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); - mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info); - - /* only the i2c master 1 is used on this CPU card */ - i2c_register_board_info(1, mx27ads_i2c_devices, - ARRAY_SIZE(mx27ads_i2c_devices)); - mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data); - mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); - mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); - mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } @@ -320,7 +277,7 @@ static struct map_desc mx27ads_io_desc[] __initdata = { static void __init mx27ads_map_io(void) { - mx27_map_io(); + mxc_map_io(); iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); } diff --git a/trunk/arch/arm/mach-mx2/mx27lite.c b/trunk/arch/arm/mach-mx2/mx27lite.c deleted file mode 100644 index 3ae11cb8c04b..000000000000 --- a/trunk/arch/arm/mach-mx2/mx27lite.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2007 Robert Schwebel , Pengutronix - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -static unsigned int mx27lite_pins[] = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, -}; - -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *platform_devices[] __initdata = { - &mxc_fec_device, -}; - -static void __init mx27lite_init(void) -{ - mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), - "imx27lite"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); -} - -static void __init mx27lite_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -static struct sys_timer mx27lite_timer = { - .init = mx27lite_timer_init, -}; - -MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mxc_init_irq, - .init_machine = mx27lite_init, - .timer = &mx27lite_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-mx2/mx27pdk.c b/trunk/arch/arm/mach-mx2/mx27pdk.c deleted file mode 100644 index 1d9238c7a6c3..000000000000 --- a/trunk/arch/arm/mach-mx2/mx27pdk.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -static unsigned int mx27pdk_pins[] = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, -}; - -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *platform_devices[] __initdata = { - &mxc_fec_device, -}; - -static void __init mx27pdk_init(void) -{ - mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), - "mx27pdk"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); -} - -static void __init mx27pdk_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -static struct sys_timer mx27pdk_timer = { - .init = mx27pdk_timer_init, -}; - -MACHINE_START(MX27_3DS, "Freescale MX27PDK") - /* maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, - .init_irq = mxc_init_irq, - .init_machine = mx27pdk_init, - .timer = &mx27pdk_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-mx2/pcm038.c b/trunk/arch/arm/mach-mx2/pcm038.c index a4628d004343..aa4eaa61d1b5 100644 --- a/trunk/arch/arm/mach-mx2/pcm038.c +++ b/trunk/arch/arm/mach-mx2/pcm038.c @@ -17,84 +17,28 @@ * MA 02110-1301, USA. */ +#include +#include +#include +#include #include #include -#include -#include -#include -#include -#include #include -#include - -#include +#include #include #include -#include #include +#ifdef CONFIG_I2C_IMX +#include +#endif +#include #include +#include #include #include "devices.h" -static int pcm038_pins[] = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART2 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART3 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* SPI1 */ - PD25_PF_CSPI1_RDY, - PD27_PF_CSPI1_SS1, - PD28_PF_CSPI1_SS0, - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, - /* SSI1 */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - /* SSI4 */ - PC16_PF_SSI4_FS, - PC17_PF_SSI4_RXD, - PC18_PF_SSI4_TXD, - PC19_PF_SSI4_CLK, -}; - /* * Phytec's PCM038 comes with 2MiB battery buffered SRAM, * 16 bit width @@ -144,16 +88,107 @@ static struct platform_device pcm038_nor_mtd_device = { .resource = &pcm038_flash_resource, }; +static int mxc_uart0_pins[] = { + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS +}; + +static int uart_mxc_port0_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, + ARRAY_SIZE(mxc_uart0_pins), "UART0"); +} + +static int uart_mxc_port0_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart0_pins, + ARRAY_SIZE(mxc_uart0_pins)); + return 0; +} + +static int mxc_uart1_pins[] = { + PE3_PF_UART2_CTS, + PE4_PF_UART2_RTS, + PE6_PF_UART2_TXD, + PE7_PF_UART2_RXD +}; + +static int uart_mxc_port1_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins), "UART1"); +} + +static int uart_mxc_port1_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins)); + return 0; +} + +static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD, + PE9_PF_UART3_RXD, + PE10_PF_UART3_CTS, + PE11_PF_UART3_RTS }; + +static int uart_mxc_port2_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins), "UART2"); +} + +static int uart_mxc_port2_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins)); + return 0; +} + static struct imxuart_platform_data uart_pdata[] = { { + .init = uart_mxc_port0_init, + .exit = uart_mxc_port0_exit, .flags = IMXUART_HAVE_RTSCTS, }, { + .init = uart_mxc_port1_init, + .exit = uart_mxc_port1_exit, .flags = IMXUART_HAVE_RTSCTS, }, { + .init = uart_mxc_port2_init, + .exit = uart_mxc_port2_exit, .flags = IMXUART_HAVE_RTSCTS, }, }; +static int mxc_fec_pins[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN +}; + +static void gpio_fec_active(void) +{ + mxc_gpio_setup_multiple_pins(mxc_fec_pins, + ARRAY_SIZE(mxc_fec_pins), "FEC"); +} + static struct mxc_nand_platform_data pcm038_nand_board_info = { .width = 1, .hw_ecc = 1, @@ -175,8 +210,27 @@ static void __init pcm038_init_sram(void) __raw_writel(0x22220a00, CSCR_A(1)); } +#ifdef CONFIG_I2C_IMX +static int mxc_i2c1_pins[] = { + PC5_PF_I2C2_SDA, + PC6_PF_I2C2_SCL +}; + +static int pcm038_i2c_1_init(struct device *dev) +{ + return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins), + "I2C1"); +} + +static void pcm038_i2c_1_exit(struct device *dev) +{ + mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins)); +} + static struct imxi2c_platform_data pcm038_i2c_1_data = { .bitrate = 100000, + .init = pcm038_i2c_1_init, + .exit = pcm038_i2c_1_exit, }; static struct at24_platform_data board_eeprom = { @@ -199,12 +253,11 @@ static struct i2c_board_info pcm038_i2c_devices[] = { .type = "lm75" } }; +#endif static void __init pcm038_init(void) { - mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins), - "PCM038"); - + gpio_fec_active(); pcm038_init_sram(); mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); @@ -214,11 +267,13 @@ static void __init pcm038_init(void) mxc_gpio_mode(PE16_AF_OWIRE); mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); +#ifdef CONFIG_I2C_IMX /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pcm038_i2c_devices, ARRAY_SIZE(pcm038_i2c_devices)); mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); +#endif platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); @@ -240,7 +295,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27") .phys_io = AIPI_BASE_ADDR, .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx27_map_io, + .map_io = mxc_map_io, .init_irq = mxc_init_irq, .init_machine = pcm038_init, .timer = &pcm038_timer, diff --git a/trunk/arch/arm/mach-mx2/pcm970-baseboard.c b/trunk/arch/arm/mach-mx2/pcm970-baseboard.c index 6a3acaf57dd4..bf4e520bc1bc 100644 --- a/trunk/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/trunk/arch/arm/mach-mx2/pcm970-baseboard.c @@ -16,107 +16,71 @@ * MA 02110-1301, USA. */ +#include #include #include -#include #include -#include -#include -#include #include +#include #include +#include +#include #include "devices.h" -static int pcm970_pins[] = { - /* SDHC */ +static int pcm970_sdhc2_get_ro(struct device *dev) +{ + return gpio_get_value(GPIO_PORTC + 28); +} + +static int pcm970_sdhc2_pins[] = { PB4_PF_SD2_D0, PB5_PF_SD2_D1, PB6_PF_SD2_D2, PB7_PF_SD2_D3, PB8_PF_SD2_CMD, PB9_PF_SD2_CLK, - GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN, /* card detect */ - /* display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* - * it seems the data line misses a pullup, so we must enable - * the internal pullup as a local workaround - */ - PD17_PF_I2C_DATA | GPIO_PUEN, - PD18_PF_I2C_CLK, - /* Camera */ - PB10_PF_CSI_D0, - PB11_PF_CSI_D1, - PB12_PF_CSI_D2, - PB13_PF_CSI_D3, - PB14_PF_CSI_D4, - PB15_PF_CSI_MCLK, - PB16_PF_CSI_PIXCLK, - PB17_PF_CSI_D5, - PB18_PF_CSI_D6, - PB19_PF_CSI_D7, - PB20_PF_CSI_VSYNC, - PB21_PF_CSI_HSYNC, }; -static int pcm970_sdhc2_get_ro(struct device *dev) -{ - return gpio_get_value(GPIO_PORTC + 28); -} - static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data) { int ret; - ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING, + ret = mxc_gpio_setup_multiple_pins(pcm970_sdhc2_pins, + ARRAY_SIZE(pcm970_sdhc2_pins), "sdhc2"); + if(ret) + return ret; + + ret = request_irq(IRQ_GPIOC(29), detect_irq, 0, "imx-mmc-detect", data); if (ret) - return ret; + goto out_release_gpio; + + set_irq_type(IRQ_GPIOC(29), IRQF_TRIGGER_FALLING); ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro"); - if (ret) { - free_irq(IRQ_GPIOC(29), data); - return ret; - } + if (ret) + goto out_release_gpio; + mxc_gpio_mode((GPIO_PORTC | 28) | GPIO_GPIO | GPIO_IN); gpio_direction_input(GPIO_PORTC + 28); return 0; + +out_release_gpio: + mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins, + ARRAY_SIZE(pcm970_sdhc2_pins)); + return ret; } static void pcm970_sdhc2_exit(struct device *dev, void *data) { free_irq(IRQ_GPIOC(29), data); gpio_free(GPIO_PORTC + 28); + mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins, + ARRAY_SIZE(pcm970_sdhc2_pins)); } static struct imxmmc_platform_data sdhc_pdata = { @@ -125,6 +89,29 @@ static struct imxmmc_platform_data sdhc_pdata = { .exit = pcm970_sdhc2_exit, }; +static int mxc_fb_pins[] = { + PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2, + PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6, + PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10, + PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14, + PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA24_PF_REV, + PA25_PF_CLS, PA26_PF_PS, PA27_PF_SPL_SPR, PA28_PF_HSYNC, + PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD +}; + +static int pcm038_fb_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_fb_pins, + ARRAY_SIZE(mxc_fb_pins), "FB"); +} + +static int pcm038_fb_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_fb_pins, ARRAY_SIZE(mxc_fb_pins)); + + return 0; +} + /* * Connected is a portrait Sharp-QVGA display * of type: LQ035Q7DH06 @@ -157,6 +144,9 @@ static struct imx_fb_platform_data pcm038_fb_data = { .pwmr = 0x00A903FF, .lscr1 = 0x00120300, .dmacr = 0x00020010, + + .init = pcm038_fb_init, + .exit = pcm038_fb_exit, }; /* @@ -167,9 +157,6 @@ static struct imx_fb_platform_data pcm038_fb_data = { */ void __init pcm970_baseboard_init(void) { - mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins), - "PCM970"); - mxc_register_device(&mxc_fb_device, &pcm038_fb_data); mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); } diff --git a/trunk/arch/arm/mach-mx3/Kconfig b/trunk/arch/arm/mach-mx3/Kconfig index 17a21a291e2f..194b8428bba4 100644 --- a/trunk/arch/arm/mach-mx3/Kconfig +++ b/trunk/arch/arm/mach-mx3/Kconfig @@ -1,12 +1,10 @@ if ARCH_MX3 config ARCH_MX31 - select ARCH_HAS_RNGA bool config ARCH_MX35 bool - select ARCH_MXC_IOMUX_V3 comment "MX3 platforms:" @@ -39,6 +37,7 @@ config MACH_PCM037 config MACH_MX31LITE bool "Support MX31 LITEKIT (LogicPD)" select ARCH_MX31 + default n help Include support for MX31 LITEKIT platform. This includes specific configurations for the board and its peripherals. @@ -46,6 +45,7 @@ config MACH_MX31LITE config MACH_MX31_3DS bool "Support MX31PDK (3DS)" select ARCH_MX31 + default n help Include support for MX31PDK (3DS) platform. This includes specific configurations for the board and its peripherals. @@ -53,43 +53,17 @@ config MACH_MX31_3DS config MACH_MX31MOBOARD bool "Support mx31moboard platforms (EPFL Mobots group)" select ARCH_MX31 + default n help Include support for mx31moboard platform. This includes specific configurations for the board and its peripherals. -config MACH_MX31LILLY - bool "Support MX31 LILLY-1131 platforms (INCO startec)" - select ARCH_MX31 - help - Include support for mx31 based LILLY1131 modules. This includes - specific configurations for the board and its peripherals. - config MACH_QONG bool "Support Dave/DENX QongEVB-LITE platform" select ARCH_MX31 + default n help Include support for Dave/DENX QongEVB-LITE platform. This includes specific configurations for the board and its peripherals. -config MACH_PCM043 - bool "Support Phytec pcm043 (i.MX35) platforms" - select ARCH_MX35 - help - Include support for Phytec pcm043 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_ARMADILLO5X0 - bool "Support Atmark Armadillo-500 Development Base Board" - select ARCH_MX31 - help - Include support for Atmark Armadillo-500 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_MX35_3DS - bool "Support MX35PDK platform" - select ARCH_MX35 - default n - help - Include support for MX35PDK platform. This includes specific - configurations for the board and its peripherals. endif diff --git a/trunk/arch/arm/mach-mx3/Makefile b/trunk/arch/arm/mach-mx3/Makefile index 0322696bd11a..272c8a953b30 100644 --- a/trunk/arch/arm/mach-mx3/Makefile +++ b/trunk/arch/arm/mach-mx3/Makefile @@ -8,13 +8,9 @@ obj-y := mm.o devices.o obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o -obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o obj-$(CONFIG_MACH_PCM037) += pcm037.o obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \ mx31moboard-marxbot.o obj-$(CONFIG_MACH_QONG) += qong.o -obj-$(CONFIG_MACH_PCM043) += pcm043.o -obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o -obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o diff --git a/trunk/arch/arm/mach-mx3/armadillo5x0.c b/trunk/arch/arm/mach-mx3/armadillo5x0.c deleted file mode 100644 index 541181090b37..000000000000 --- a/trunk/arch/arm/mach-mx3/armadillo5x0.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * armadillo5x0.c - * - * Copyright 2009 Alberto Panizzo - * updates in http://alberdroid.blogspot.com/ - * - * Based on Atmark Techno, Inc. armadillo 500 BSP 2008 - * Based on mx31ads.c and pcm037.c Great Work! - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -static int armadillo5x0_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - /* UART2 */ - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - /* LAN9118_IRQ */ - IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/ - -}; - -/* - * FB support - */ -static const struct fb_videomode fb_modedb[] = { - { /* 640x480 @ 60 Hz */ - .name = "CRT-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, - .left_margin = 35, - .right_margin = 115, - .upper_margin = 43, - .lower_margin = 1, - .hsync_len = 10, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, {/* 800x600 @ 56 Hz */ - .name = "CRT-SVGA", - .refresh = 56, - .xres = 800, - .yres = 600, - .pixclock = 30000, - .left_margin = 30, - .right_margin = 108, - .upper_margin = 13, - .lower_margin = 10, - .hsync_len = 10, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct ipu_platform_data mx3_ipu_data = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct mx3fb_platform_data mx3fb_pdata = { - .dma_dev = &mx3_ipu.dev, - .name = "CRT-VGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -/* - * SDHC 1 - * MMC support - */ -static int armadillo5x0_sdhc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); -} - -static int armadillo5x0_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - int gpio_det, gpio_wp; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B); - - ret = gpio_request(gpio_det, "sdhc-card-detect"); - if (ret) - return ret; - - gpio_direction_input(gpio_det); - - ret = gpio_request(gpio_wp, "sdhc-write-protect"); - if (ret) - goto err_gpio_free; - - gpio_direction_input(gpio_wp); - - /* When supported the trigger type have to be BOTH */ - ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "sdhc-detect", data); - - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(gpio_wp); - -err_gpio_free: - gpio_free(gpio_det); - - return ret; - -} - -static void armadillo5x0_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data); - gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)); - gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); -} - -static struct imxmmc_platform_data sdhc_pdata = { - .get_ro = armadillo5x0_sdhc1_get_ro, - .init = armadillo5x0_sdhc1_init, - .exit = armadillo5x0_sdhc1_exit, -}; - -/* - * SMSC 9118 - * Network support - */ -static struct resource armadillo5x0_smc911x_resources[] = { - { - .start = CS3_BASE_ADDR, - .end = CS3_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), - .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_32BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, -}; - -static struct platform_device armadillo5x0_smc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(armadillo5x0_smc911x_resources), - .resource = armadillo5x0_smc911x_resources, - .dev = { - .platform_data = &smsc911x_info, - }, -}; - -/* UART device data */ -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *devices[] __initdata = { - &armadillo5x0_smc911x_device, -}; - -/* - * Perform board specific initializations - */ -static void __init armadillo5x0_init(void) -{ - mxc_iomux_setup_multiple_pins(armadillo5x0_pins, - ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - /* Register UART */ - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - - /* SMSC9118 IRQ pin */ - gpio_direction_input(MX31_PIN_GPIO1_0); - - /* Register SDHC */ - mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); - - /* Register FB */ - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - mxc_register_device(&mx3_fb, &mx3fb_pdata); -} - -static void __init armadillo5x0_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static struct sys_timer armadillo5x0_timer = { - .init = armadillo5x0_timer_init, -}; - -MACHINE_START(ARMADILLO5X0, "Armadillo-500") - /* Maintainer: Alberto Panizzo */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x00000100, - .map_io = mx31_map_io, - .init_irq = mxc_init_irq, - .timer = &armadillo5x0_timer, - .init_machine = armadillo5x0_init, -MACHINE_END diff --git a/trunk/arch/arm/mach-mx3/clock-imx35.c b/trunk/arch/arm/mach-mx3/clock-imx35.c index 0d76521cb491..53a112d4e04a 100644 --- a/trunk/arch/arm/mach-mx3/clock-imx35.c +++ b/trunk/arch/arm/mach-mx3/clock-imx35.c @@ -147,16 +147,34 @@ static struct arm_ahb_div clk_consumer[] = { { .arm = 0, .ahb = 0, .sel = 0}, }; +static struct arm_ahb_div clk_automotive[] = { + { .arm = 1, .ahb = 3, .sel = 0}, + { .arm = 1, .ahb = 2, .sel = 1}, + { .arm = 2, .ahb = 1, .sel = 1}, + { .arm = 0, .ahb = 0, .sel = 0}, + { .arm = 1, .ahb = 6, .sel = 0}, + { .arm = 1, .ahb = 4, .sel = 1}, + { .arm = 2, .ahb = 2, .sel = 1}, + { .arm = 0, .ahb = 0, .sel = 0}, +}; + static unsigned long get_rate_arm(void) { unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); struct arm_ahb_div *aad; unsigned long fref = get_rate_mpll(); - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; - if (aad->sel) - fref = fref * 2 / 3; - + if (pdr0 & 1) { + /* consumer path */ + aad = &clk_consumer[(pdr0 >> 16) & 0xf]; + if (aad->sel) + fref = fref * 2 / 3; + } else { + /* auto path */ + aad = &clk_automotive[(pdr0 >> 9) & 0x7]; + if (aad->sel) + fref = fref * 3 / 4; + } return fref / aad->arm; } @@ -166,7 +184,12 @@ static unsigned long get_rate_ahb(struct clk *clk) struct arm_ahb_div *aad; unsigned long fref = get_rate_mpll(); - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; + if (pdr0 & 1) + /* consumer path */ + aad = &clk_consumer[(pdr0 >> 16) & 0xf]; + else + /* auto path */ + aad = &clk_automotive[(pdr0 >> 9) & 0x7]; return fref / aad->ahb; } @@ -407,8 +430,7 @@ static struct clk_lookup lookups[] __initdata = { _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk) _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk) - _REGISTER_CLOCK("ipu-core", NULL, ipu_clk) - _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk) + _REGISTER_CLOCK(NULL, "ipu", ipu_clk) _REGISTER_CLOCK(NULL, "kpp", kpp_clk) _REGISTER_CLOCK(NULL, "mlb", mlb_clk) _REGISTER_CLOCK(NULL, "mshc", mshc_clk) @@ -440,6 +462,8 @@ int __init mx35_clocks_init() int i; unsigned int ll = 0; + mxc_set_cpu_type(MXC_CPU_MX35); + #ifdef CONFIG_DEBUG_LL_CONSOLE ll = (3 << 16); #endif diff --git a/trunk/arch/arm/mach-mx3/clock.c b/trunk/arch/arm/mach-mx3/clock.c index 217d114b177a..9957a11533a4 100644 --- a/trunk/arch/arm/mach-mx3/clock.c +++ b/trunk/arch/arm/mach-mx3/clock.c @@ -483,7 +483,7 @@ DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk); DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk); DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk); DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk); -DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk); +DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &ahb_clk); DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk); DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk); DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk); @@ -566,18 +566,13 @@ int __init mx31_clocks_init(unsigned long fref) u32 reg; int i; + mxc_set_cpu_type(MXC_CPU_MX31); + ckih_rate = fref; for (i = 0; i < ARRAY_SIZE(lookups); i++) clkdev_add(&lookups[i]); - /* change the csi_clk parent if necessary */ - reg = __raw_readl(MXC_CCM_CCMR); - if (!(reg & MXC_CCM_CCMR_CSCS)) - if (clk_set_parent(&csi_clk, &usb_pll_clk)) - pr_err("%s: error changing csi_clk parent\n", __func__); - - /* Turn off all possible clocks */ __raw_writel((3 << 4), MXC_CCM_CGR0); __raw_writel(0, MXC_CCM_CGR1); @@ -586,12 +581,6 @@ int __init mx31_clocks_init(unsigned long fref) MX32, but still required to be set */ MXC_CCM_CGR2); - /* - * Before turning off usb_pll make sure ipg_per_clk is generated - * by ipg_clk and not usb_pll. - */ - __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR); - usb_pll_disable(&usb_pll_clk); pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); diff --git a/trunk/arch/arm/mach-mx3/devices.c b/trunk/arch/arm/mach-mx3/devices.c index d927eddcad46..380be0c9b213 100644 --- a/trunk/arch/arm/mach-mx3/devices.c +++ b/trunk/arch/arm/mach-mx3/devices.c @@ -17,17 +17,13 @@ * Boston, MA 02110-1301, USA. */ -#include #include #include #include #include -#include #include #include -#include #include -#include #include "devices.h" @@ -287,21 +283,6 @@ struct platform_device mxcsdhc_device1 = { .num_resources = ARRAY_SIZE(mxcsdhc1_resources), .resource = mxcsdhc1_resources, }; - -static struct resource rnga_resources[] = { - { - .start = RNGA_BASE_ADDR, - .end = RNGA_BASE_ADDR + 0x28, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_rnga_device = { - .name = "mxc_rnga", - .id = -1, - .num_resources = 1, - .resource = rnga_resources, -}; #endif /* CONFIG_ARCH_MX31 */ /* i.MX31 Image Processing Unit */ @@ -348,54 +329,10 @@ struct platform_device mx3_fb = { .num_resources = ARRAY_SIZE(fb_resources), .resource = fb_resources, .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), + .coherent_dma_mask = 0xffffffff, }, }; -static struct resource camera_resources[] = { - { - .start = IPU_CTRL_BASE_ADDR + 0x60, - .end = IPU_CTRL_BASE_ADDR + 0x87, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mx3_camera = { - .name = "mx3-camera", - .id = 0, - .num_resources = ARRAY_SIZE(camera_resources), - .resource = camera_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource otg_resources[] = { - { - .start = OTG_BASE_ADDR, - .end = OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_USB3, - .end = MXC_INT_USB3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 otg_dmamask = DMA_BIT_MASK(32); - -/* OTG gadget device */ -struct platform_device mxc_otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), -}; - #ifdef CONFIG_ARCH_MX35 static struct resource mxc_fec_resources[] = { { @@ -422,7 +359,6 @@ static int mx3_devices_init(void) if (cpu_is_mx31()) { mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR; mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff; - mxc_register_device(&mxc_rnga_device, NULL); } if (cpu_is_mx35()) { mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; diff --git a/trunk/arch/arm/mach-mx3/devices.h b/trunk/arch/arm/mach-mx3/devices.h index ffd494ddd4ac..88c04b296fab 100644 --- a/trunk/arch/arm/mach-mx3/devices.h +++ b/trunk/arch/arm/mach-mx3/devices.h @@ -11,10 +11,6 @@ extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_i2c_device2; extern struct platform_device mx3_ipu; extern struct platform_device mx3_fb; -extern struct platform_device mx3_camera; extern struct platform_device mxc_fec_device; extern struct platform_device mxcsdhc_device0; extern struct platform_device mxcsdhc_device1; -extern struct platform_device mxc_otg_udc_device; -extern struct platform_device mxc_rnga_device; - diff --git a/trunk/arch/arm/mach-mx3/iomux.c b/trunk/arch/arm/mach-mx3/iomux.c index c66ccbcdc11b..40ffc5a664d9 100644 --- a/trunk/arch/arm/mach-mx3/iomux.c +++ b/trunk/arch/arm/mach-mx3/iomux.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -93,13 +94,15 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) EXPORT_SYMBOL(mxc_iomux_set_pad); /* - * allocs a single pin: + * setups a single pin: * - reserves the pin so that it is not claimed by another driver * - setups the iomux according to the configuration + * - if the pin is configured as a GPIO, we claim it through kernel gpiolib */ -int mxc_iomux_alloc_pin(const unsigned int pin, const char *label) +int mxc_iomux_setup_pin(const unsigned int pin, const char *label) { unsigned pad = pin & IOMUX_PADNUM_MASK; + unsigned gpio; if (pad >= (PIN_MAX + 1)) { printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", @@ -110,13 +113,19 @@ int mxc_iomux_alloc_pin(const unsigned int pin, const char *label) if (test_and_set_bit(pad, mxc_pin_alloc_map)) { printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", pad, label ? label : "?"); - return -EBUSY; + return -EINVAL; } mxc_iomux_mode(pin); + /* if we have a gpio, we can allocate it */ + gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT; + if (gpio < (GPIO_PORT_MAX + 1) * 32) + if (gpio_request(gpio, label)) + return -EINVAL; + return 0; } -EXPORT_SYMBOL(mxc_iomux_alloc_pin); +EXPORT_SYMBOL(mxc_iomux_setup_pin); int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, const char *label) @@ -126,8 +135,7 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, int ret = -EINVAL; for (i = 0; i < count; i++) { - ret = mxc_iomux_alloc_pin(*p, label); - if (ret) + if (mxc_iomux_setup_pin(*p, label)) goto setup_error; p++; } @@ -142,9 +150,14 @@ EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); void mxc_iomux_release_pin(const unsigned int pin) { unsigned pad = pin & IOMUX_PADNUM_MASK; + unsigned gpio; if (pad < (PIN_MAX + 1)) clear_bit(pad, mxc_pin_alloc_map); + + gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT; + if (gpio < (GPIO_PORT_MAX + 1) * 32) + gpio_free(gpio); } EXPORT_SYMBOL(mxc_iomux_release_pin); diff --git a/trunk/arch/arm/mach-mx3/mm.c b/trunk/arch/arm/mach-mx3/mm.c index 1f5fdd456cb9..9e1459cb4b74 100644 --- a/trunk/arch/arm/mach-mx3/mm.c +++ b/trunk/arch/arm/mach-mx3/mm.c @@ -72,17 +72,8 @@ static struct map_desc mxc_io_desc[] __initdata = { * system startup to create static physical to virtual memory mappings * for the IO modules. */ -void __init mx31_map_io(void) +void __init mxc_map_io(void) { - mxc_set_cpu_type(MXC_CPU_MX31); - - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); -} - -void __init mx35_map_io(void) -{ - mxc_set_cpu_type(MXC_CPU_MX35); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } diff --git a/trunk/arch/arm/mach-mx3/mx31ads.c b/trunk/arch/arm/mach-mx3/mx31ads.c index 30e2767a78ae..a6d6efefa6aa 100644 --- a/trunk/arch/arm/mach-mx3/mx31ads.c +++ b/trunk/arch/arm/mach-mx3/mx31ads.c @@ -187,7 +187,7 @@ static void __init mx31ads_init_expio(void) /* * Configure INT line as GPIO input */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); + mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); /* disable the interrupt and clear the status */ __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); @@ -511,7 +511,7 @@ static struct map_desc mx31ads_io_desc[] __initdata = { */ static void __init mx31ads_map_io(void) { - mx31_map_io(); + mxc_map_io(); iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); } diff --git a/trunk/arch/arm/mach-mx3/mx31lilly-db.c b/trunk/arch/arm/mach-mx3/mx31lilly-db.c deleted file mode 100644 index 3b3a78f49c23..000000000000 --- a/trunk/arch/arm/mach-mx3/mx31lilly-db.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * LILLY-1131 development board support - * - * Copyright (c) 2009 Daniel Mack - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -/* - * This file contains board-specific initialization routines for the - * LILLY-1131 development board. If you design an own baseboard for the - * module, use this file as base for support code. - */ - -static unsigned int lilly_db_board_pins[] __initdata = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - MX31_PIN_CONTRAST__CONTRAST, -}; - -/* UART */ -static struct imxuart_platform_data uart_pdata __initdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* MMC support */ - -static int mxc_mmc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); -} - -static int gpio_det, gpio_wp; - -static int mxc_mmc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0); - - ret = gpio_request(gpio_det, "MMC detect"); - if (ret) - return ret; - - ret = gpio_request(gpio_wp, "MMC w/p"); - if (ret) - goto exit_free_det; - - gpio_direction_input(gpio_det); - gpio_direction_input(gpio_wp); - - ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "MMC detect", data); - if (ret) - goto exit_free_wp; - - return 0; - -exit_free_wp: - gpio_free(gpio_wp); - -exit_free_det: - gpio_free(gpio_det); - - return ret; -} - -static void mxc_mmc1_exit(struct device *dev, void *data) -{ - gpio_free(gpio_det); - gpio_free(gpio_wp); - free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); -} - -static struct imxmmc_platform_data mmc_pdata = { - .get_ro = mxc_mmc1_get_ro, - .init = mxc_mmc1_init, - .exit = mxc_mmc1_exit, -}; - -/* Framebuffer support */ -static struct ipu_platform_data ipu_data __initdata = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static const struct fb_videomode fb_modedb = { - /* 640x480 TFT panel (IPS-056T) */ - .name = "CRT-VGA", - .refresh = 64, - .xres = 640, - .yres = 480, - .pixclock = 30000, - .left_margin = 200, - .right_margin = 2, - .upper_margin = 2, - .lower_margin = 2, - .hsync_len = 3, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, -}; - -static struct mx3fb_platform_data fb_pdata __initdata = { - .dma_dev = &mx3_ipu.dev, - .name = "CRT-VGA", - .mode = &fb_modedb, - .num_modes = 1, -}; - -#define LCD_VCC_EN_GPIO (7) - -static void __init mx31lilly_init_fb(void) -{ - if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) { - printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n"); - return; - } - - mxc_register_device(&mx3_ipu, &ipu_data); - mxc_register_device(&mx3_fb, &fb_pdata); - gpio_direction_output(LCD_VCC_EN_GPIO, 1); -} - -void __init mx31lilly_db_init(void) -{ - mxc_iomux_setup_multiple_pins(lilly_db_board_pins, - ARRAY_SIZE(lilly_db_board_pins), - "development board pins"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_pdata); - mxc_register_device(&mxcsdhc_device0, &mmc_pdata); - mx31lilly_init_fb(); -} - diff --git a/trunk/arch/arm/mach-mx3/mx31lilly.c b/trunk/arch/arm/mach-mx3/mx31lilly.c deleted file mode 100644 index 6ab2f163cb95..000000000000 --- a/trunk/arch/arm/mach-mx3/mx31lilly.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * LILLY-1131 module support - * - * Copyright (c) 2009 Daniel Mack - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "devices.h" - -/* - * This file contains module-specific initialization routines for LILLY-1131. - * Initialization of peripherals found on the baseboard is implemented in the - * appropriate baseboard support code. - */ - -/* SMSC ethernet support */ - -static struct resource smsc91x_resources[] = { - { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 0xffff, - .flags = IORESOURCE_MEM, - }, - { - .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), - .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, - } -}; - -static struct smsc911x_platform_config smsc911x_config = { - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .flags = SMSC911X_USE_32BIT | - SMSC911X_SAVE_MAC_ADDRESS | - SMSC911X_FORCE_INTERNAL_PHY, -}; - -static struct platform_device smsc91x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc91x_resources), - .resource = smsc91x_resources, - .dev = { - .platform_data = &smsc911x_config, - } -}; - -/* NOR flash */ -static struct physmap_flash_data nor_flash_data = { - .width = 2, -}; - -static struct resource nor_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device physmap_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_flash_data, - }, - .resource = &nor_flash_resource, - .num_resources = 1, -}; - -static struct platform_device *devices[] __initdata = { - &smsc91x_device, - &physmap_flash_device, - &mxc_i2c_device1, -}; - -static int mx31lilly_baseboard; -core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444); - -static void __init mx31lilly_board_init(void) -{ - switch (mx31lilly_baseboard) { - case MX31LILLY_NOBOARD: - break; - case MX31LILLY_DB: - mx31lilly_db_init(); - break; - default: - printk(KERN_ERR "Illegal mx31lilly_baseboard type %d\n", - mx31lilly_baseboard); - } - - mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__SCL, "I2C SCL"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__SDA, "I2C SDA"); - - platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -static void __init mx31lilly_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static struct sys_timer mx31lilly_timer = { - .init = mx31lilly_timer_init, -}; - -MACHINE_START(LILLY1131, "INCO startec LILLY-1131") - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, - .init_irq = mxc_init_irq, - .init_machine = mx31lilly_board_init, - .timer = &mx31lilly_timer, -MACHINE_END - diff --git a/trunk/arch/arm/mach-mx3/mx31lite.c b/trunk/arch/arm/mach-mx3/mx31lite.c index 86fe70fa3e13..894d98cd9941 100644 --- a/trunk/arch/arm/mach-mx3/mx31lite.c +++ b/trunk/arch/arm/mach-mx3/mx31lite.c @@ -22,9 +22,6 @@ #include #include #include -#include -#include -#include #include #include @@ -35,64 +32,11 @@ #include #include #include -#include -#include -#include -#include -#include "devices.h" /* * This file contains the board-specific initialization routines. */ -static unsigned int mx31lite_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - /* LAN9117 IRQ pin */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), -}; - -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct mxc_nand_platform_data mx31lite_nand_board_info = { - .width = 1, - .hw_ecc = 1, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT, -}; - -static struct resource smsc911x_resources[] = { - [0] = { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IOMUX_TO_IRQ(MX31_PIN_SFS6), - .end = IOMUX_TO_IRQ(MX31_PIN_SFS6), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; - /* * This structure defines the MX31 memory map. */ @@ -115,7 +59,7 @@ static struct map_desc mx31lite_io_desc[] __initdata = { */ void __init mx31lite_map_io(void) { - mx31_map_io(); + mxc_map_io(); iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); } @@ -124,22 +68,6 @@ void __init mx31lite_map_io(void) */ static void __init mxc_board_init(void) { - int ret; - - mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), - "mx31lite"); - - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); - - /* SMSC9117 IRQ pin */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else { - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6)); - platform_device_register(&smsc911x_device); - } } static void __init mx31lite_timer_init(void) diff --git a/trunk/arch/arm/mach-mx3/mx31moboard-devboard.c b/trunk/arch/arm/mach-mx3/mx31moboard-devboard.c index 4704405165a1..d080b4add79c 100644 --- a/trunk/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/trunk/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -16,142 +16,33 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include -#include +#include #include -#include + #include -#include +#include #include #include #include -#include -#include #include "devices.h" -static unsigned int devboard_pins[] = { - /* UART1 */ - MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, - /* SDHC2 */ - MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, - MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, - MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, - MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, - /* USB OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, - MX31_PIN_USB_OC__GPIO1_30, -}; - static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) -#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) - -static int devboard_sdhc2_get_ro(struct device *dev) -{ - return gpio_get_value(SDHC2_WP); -} - -static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC2_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC2_CD); - - ret = gpio_request(SDHC2_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC2_WP); - - ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc2-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC2_WP); -err_gpio_free: - gpio_free(SDHC2_CD); - - return ret; -} - -static void devboard_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC2_CD), data); - gpio_free(SDHC2_WP); - gpio_free(SDHC2_CD); -} - -static struct imxmmc_platform_data sdhc2_pdata = { - .get_ro = devboard_sdhc2_get_ro, - .init = devboard_sdhc2_init, - .exit = devboard_sdhc2_exit, -}; - -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, +static int mxc_uart1_pins[] = { + MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, + MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, }; -#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST) -#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) - -static void devboard_usbotg_init(void) -{ - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG); - - gpio_request(OTG_EN_B, "usb-udc-en"); - gpio_direction_output(OTG_EN_B, 0); -} - /* * system init for baseboard usage. Will be called by mx31moboard init. */ void __init mx31moboard_devboard_init(void) { printk(KERN_INFO "Initializing mx31devboard peripherals\n"); - - mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins), - "devboard"); - + mxc_iomux_setup_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins), "uart1"); mxc_register_device(&mxc_uart_device1, &uart_pdata); - - mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); - - devboard_usbotg_init(); - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } diff --git a/trunk/arch/arm/mach-mx3/mx31moboard-marxbot.c b/trunk/arch/arm/mach-mx3/mx31moboard-marxbot.c index 641c3d6153ae..9ef9566823fb 100644 --- a/trunk/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/trunk/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -16,144 +16,22 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include -#include +#include #include -#include + #include -#include -#include #include +#include #include #include -#include #include "devices.h" -static unsigned int marxbot_pins[] = { - /* SDHC2 */ - MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, - MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, - MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, - MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, - /* CSI */ - MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5, - MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, - MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, - MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, - MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13, - MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, - MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, - MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, - MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, - MX31_PIN_TXD2__GPIO1_28, - /* USB OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, - MX31_PIN_USB_OC__GPIO1_30, -}; - -#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) -#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) - -static int marxbot_sdhc2_get_ro(struct device *dev) -{ - return gpio_get_value(SDHC2_WP); -} - -static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC2_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC2_CD); - - ret = gpio_request(SDHC2_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC2_WP); - - ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc2-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC2_WP); -err_gpio_free: - gpio_free(SDHC2_CD); - - return ret; -} - -static void marxbot_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC2_CD), data); - gpio_free(SDHC2_WP); - gpio_free(SDHC2_CD); -} - -static struct imxmmc_platform_data sdhc2_pdata = { - .get_ro = marxbot_sdhc2_get_ro, - .init = marxbot_sdhc2_init, - .exit = marxbot_sdhc2_exit, -}; - -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST) -#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) - -static void marxbot_usbotg_init(void) -{ - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG); - - gpio_request(OTG_EN_B, "usb-udc-en"); - gpio_direction_output(OTG_EN_B, 0); -} - /* * system init for baseboard usage. Will be called by mx31moboard init. */ void __init mx31moboard_marxbot_init(void) { printk(KERN_INFO "Initializing mx31marxbot peripherals\n"); - - mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), - "marxbot"); - - mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); - - marxbot_usbotg_init(); - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } diff --git a/trunk/arch/arm/mach-mx3/mx31moboard.c b/trunk/arch/arm/mach-mx3/mx31moboard.c index a17f2e411609..34c2a1b99d4f 100644 --- a/trunk/arch/arm/mach-mx3/mx31moboard.c +++ b/trunk/arch/arm/mach-mx3/mx31moboard.c @@ -16,47 +16,26 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include +#include #include -#include -#include + +#include #include #include -#include -#include +#include +#include #include #include #include #include -#include #include -#include #include #include -#include -#include +#include #include "devices.h" -static unsigned int moboard_pins[] = { - /* UART0 */ - MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, - /* UART4 */ - MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, - MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, - /* I2C0 */ - MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL, - /* I2C1 */ - MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27, -}; - static struct physmap_flash_data mx31moboard_flash_data = { .width = 2, }; @@ -81,69 +60,17 @@ static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct imxi2c_platform_data moboard_i2c0_pdata = { - .bitrate = 400000, -}; - -static struct imxi2c_platform_data moboard_i2c1_pdata = { - .bitrate = 100000, +static struct platform_device *devices[] __initdata = { + &mx31moboard_flash, }; -#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) -#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) - -static int moboard_sdhc1_get_ro(struct device *dev) -{ - return gpio_get_value(SDHC1_WP); -} - -static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC1_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC1_CD); - - ret = gpio_request(SDHC1_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC1_WP); - - ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc1-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC1_WP); -err_gpio_free: - gpio_free(SDHC1_CD); - - return ret; -} - -static void moboard_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC1_CD), data); - gpio_free(SDHC1_WP); - gpio_free(SDHC1_CD); -} - -static struct imxmmc_platform_data sdhc1_pdata = { - .get_ro = moboard_sdhc1_get_ro, - .init = moboard_sdhc1_init, - .exit = moboard_sdhc1_exit, +static int mxc_uart0_pins[] = { + MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1, + MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, }; - -static struct platform_device *devices[] __initdata = { - &mx31moboard_flash, +static int mxc_uart4_pins[] = { + MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, + MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, }; static int mx31moboard_baseboard; @@ -154,18 +81,13 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); */ static void __init mxc_board_init(void) { - mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins), - "moboard"); - platform_add_devices(devices, ARRAY_SIZE(devices)); + mxc_iomux_setup_multiple_pins(mxc_uart0_pins, ARRAY_SIZE(mxc_uart0_pins), "uart0"); mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device4, &uart_pdata); - - mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); - mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); - mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); + mxc_iomux_setup_multiple_pins(mxc_uart4_pins, ARRAY_SIZE(mxc_uart4_pins), "uart4"); + mxc_register_device(&mxc_uart_device4, &uart_pdata); switch (mx31moboard_baseboard) { case MX31NOBOARD: @@ -177,8 +99,7 @@ static void __init mxc_board_init(void) mx31moboard_marxbot_init(); break; default: - printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", - mx31moboard_baseboard); + printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", mx31moboard_baseboard); } } @@ -196,7 +117,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, + .map_io = mxc_map_io, .init_irq = mxc_init_irq, .init_machine = mxc_board_init, .timer = &mx31moboard_timer, diff --git a/trunk/arch/arm/mach-mx3/mx31pdk.c b/trunk/arch/arm/mach-mx3/mx31pdk.c index c19838d2e369..bc63f1785691 100644 --- a/trunk/arch/arm/mach-mx3/mx31pdk.c +++ b/trunk/arch/arm/mach-mx3/mx31pdk.c @@ -20,9 +20,6 @@ #include #include #include -#include -#include -#include #include #include @@ -44,192 +41,21 @@ * @ingroup System */ -static int mx31pdk_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), -}; - static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -/* - * Support for the SMSC9217 on the Debug board. - */ - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct resource smsc911x_resources[] = { - { - .start = LAN9217_BASE_ADDR, - .end = LAN9217_BASE_ADDR + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = EXPIO_INT_ENET, - .end = EXPIO_INT_ENET, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; - -/* - * Routines for the CPLD on the debug board. It contains a CPLD handling - * LEDs, switches, interrupts for Ethernet. - */ - -static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc) -{ - uint32_t imr_val; - uint32_t int_valid; - uint32_t expio_irq; - - imr_val = __raw_readw(CPLD_INT_MASK_REG); - int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val; - - expio_irq = MXC_EXP_IO_BASE; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - generic_handle_irq(expio_irq); - } -} - -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * @param irq an expio virtual irq number - */ -static void expio_mask_irq(uint32_t irq) -{ - uint16_t reg; - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* mask the interrupt */ - reg = __raw_readw(CPLD_INT_MASK_REG); - reg |= 1 << expio; - __raw_writew(reg, CPLD_INT_MASK_REG); -} - -/* - * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. - * @param irq an expanded io virtual irq number - */ -static void expio_ack_irq(uint32_t irq) -{ - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* clear the interrupt status */ - __raw_writew(1 << expio, CPLD_INT_RESET_REG); - __raw_writew(0, CPLD_INT_RESET_REG); - /* mask the interrupt */ - expio_mask_irq(irq); -} - -/* - * Enable a expio pin's interrupt by clearing the bit in the imr. - * @param irq a expio virtual irq number - */ -static void expio_unmask_irq(uint32_t irq) -{ - uint16_t reg; - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* unmask the interrupt */ - reg = __raw_readw(CPLD_INT_MASK_REG); - reg &= ~(1 << expio); - __raw_writew(reg, CPLD_INT_MASK_REG); -} - -static struct irq_chip expio_irq_chip = { - .ack = expio_ack_irq, - .mask = expio_mask_irq, - .unmask = expio_unmask_irq, -}; - -static int __init mx31pdk_init_expio(void) -{ - int i; - int ret; - - /* Check if there's a debug board connected */ - if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) || - (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) || - (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) { - /* No Debug board found */ - return -ENODEV; - } - - pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n", - __raw_readw(CPLD_CODE_VER_REG)); - - /* - * Configure INT line as GPIO input - */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - - /* Disable the interrupts and clear the status */ - __raw_writew(0, CPLD_INT_MASK_REG); - __raw_writew(0xFFFF, CPLD_INT_RESET_REG); - __raw_writew(0, CPLD_INT_RESET_REG); - __raw_writew(0x1F, CPLD_INT_MASK_REG); - for (i = MXC_EXP_IO_BASE; - i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); - i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler); - - return 0; -} - -/* - * This structure defines the MX31 memory map. - */ -static struct map_desc mx31pdk_io_desc[] __initdata = { - { - .virtual = SPBA0_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), - .length = SPBA0_SIZE, - .type = MT_DEVICE_NONSHARED, - }, { - .virtual = CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS5_BASE_ADDR), - .length = CS5_SIZE, - .type = MT_DEVICE, - }, +static int uart_pins[] = { + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_RXD1__RXD1 }; -/* - * Set up static virtual mappings. - */ -static void __init mx31pdk_map_io(void) +static inline void mxc_init_imx_uart(void) { - mx31_map_io(); - iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc)); + mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); + mxc_register_device(&mxc_uart_device0, &uart_pdata); } /*! @@ -237,13 +63,7 @@ static void __init mx31pdk_map_io(void) */ static void __init mxc_board_init(void) { - mxc_iomux_setup_multiple_pins(mx31pdk_pins, ARRAY_SIZE(mx31pdk_pins), - "mx31pdk"); - - mxc_register_device(&mxc_uart_device0, &uart_pdata); - - if (!mx31pdk_init_expio()) - platform_device_register(&smsc911x_device); + mxc_init_imx_uart(); } static void __init mx31pdk_timer_init(void) @@ -264,7 +84,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx31pdk_map_io, + .map_io = mxc_map_io, .init_irq = mxc_init_irq, .init_machine = mxc_board_init, .timer = &mx31pdk_timer, diff --git a/trunk/arch/arm/mach-mx3/mx35pdk.c b/trunk/arch/arm/mach-mx3/mx35pdk.c deleted file mode 100644 index 6d15374414b9..000000000000 --- a/trunk/arch/arm/mach-mx3/mx35pdk.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "devices.h" - -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *devices[] __initdata = { - &mxc_fec_device, -}; - -static struct pad_desc mx35pdk_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, -}; - -/* - * Board specific initialization. - */ -static void __init mxc_board_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - mxc_register_device(&mxc_uart_device0, &uart_pdata); -} - -static void __init mx35pdk_timer_init(void) -{ - mx35_clocks_init(); -} - -struct sys_timer mx35pdk_timer = { - .init = mx35pdk_timer_init, -}; - -MACHINE_START(MX35_3DS, "Freescale MX35PDK") - /* Maintainer: Freescale Semiconductor, Inc */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx35_map_io, - .init_irq = mxc_init_irq, - .init_machine = mxc_board_init, - .timer = &mx35pdk_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-mx3/pcm037.c b/trunk/arch/arm/mach-mx3/pcm037.c index c6f61a1f06c8..b5227d837b2f 100644 --- a/trunk/arch/arm/mach-mx3/pcm037.c +++ b/trunk/arch/arm/mach-mx3/pcm037.c @@ -28,10 +28,6 @@ #include #include #include -#include -#include -#include -#include #include #include @@ -41,9 +37,7 @@ #include #include #include -#include #include -#include #include #include #ifdef CONFIG_I2C_IMX @@ -52,76 +46,6 @@ #include "devices.h" -static unsigned int pcm037_pins[] = { - /* I2C */ - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ - /* SPI1 */ - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS0__SS0, - MX31_PIN_CSPI1_SS1__SS1, - MX31_PIN_CSPI1_SS2__SS2, - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - /* UART2 */ - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - /* UART3 */ - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, - /* LAN9217 irq pin */ - IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), - /* Onewire */ - MX31_PIN_BATT_LINE__OWIRE, - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - MX31_PIN_D3_REV__D3_REV, - MX31_PIN_CONTRAST__CONTRAST, - MX31_PIN_D3_SPL__D3_SPL, - MX31_PIN_D3_CLS__D3_CLS, - MX31_PIN_LCS0__GPI03_23, -}; - static struct physmap_flash_data pcm037_flash_data = { .width = 2, }; @@ -132,54 +56,6 @@ static struct resource pcm037_flash_resource = { .flags = IORESOURCE_MEM, }; -static int usbotg_pins[] = { - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, -}; - -/* USB OTG HS port */ -static int __init gpio_usbotg_hs_activate(void) -{ - int ret = mxc_iomux_setup_multiple_pins(usbotg_pins, - ARRAY_SIZE(usbotg_pins), "usbotg"); - - if (ret < 0) { - printk(KERN_ERR "Cannot set up OTG pins\n"); - return ret; - } - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - return 0; -} - -/* OTG config */ -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - static struct platform_device pcm037_flash = { .name = "physmap-flash", .id = 0, @@ -251,8 +127,26 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = { }; #ifdef CONFIG_I2C_IMX +static int i2c_1_pins[] = { + MX31_PIN_CSPI2_MOSI__SCL, + MX31_PIN_CSPI2_MISO__SDA, +}; + +static int pcm037_i2c_1_init(struct device *dev) +{ + return mxc_iomux_setup_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins), + "i2c-1"); +} + +static void pcm037_i2c_1_exit(struct device *dev) +{ + mxc_iomux_release_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins)); +} + static struct imxi2c_platform_data pcm037_i2c_1_data = { .bitrate = 100000, + .init = pcm037_i2c_1_init, + .exit = pcm037_i2c_1_exit, }; static struct at24_platform_data board_eeprom = { @@ -272,119 +166,48 @@ static struct i2c_board_info pcm037_i2c_devices[] = { }; #endif -/* Not connected by default */ -#ifdef PCM970_SDHC_RW_SWITCH -static int pcm970_sdhc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6)); -} -#endif - -#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6) -#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6) +static int sdhc1_pins[] = { + MX31_PIN_SD1_DATA3__SD1_DATA3, + MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA1__SD1_DATA1, + MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_CLK__SD1_CLK, + MX31_PIN_SD1_CMD__SD1_CMD, +}; -static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) +static int pcm970_sdhc1_init(struct device *dev, irq_handler_t h, void *data) { - int ret; - - ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC1_GPIO_DET); - -#ifdef PCM970_SDHC_RW_SWITCH - ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC1_GPIO_WP); -#endif - - ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "sdhc-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: -#ifdef PCM970_SDHC_RW_SWITCH - gpio_free(SDHC1_GPIO_WP); -err_gpio_free: -#endif - gpio_free(SDHC1_GPIO_DET); - - return ret; + return mxc_iomux_setup_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins), + "sdhc-1"); } static void pcm970_sdhc1_exit(struct device *dev, void *data) { - free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data); - gpio_free(SDHC1_GPIO_DET); - gpio_free(SDHC1_GPIO_WP); + mxc_iomux_release_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins)); } +/* No card and rw detection at the moment */ static struct imxmmc_platform_data sdhc_pdata = { -#ifdef PCM970_SDHC_RW_SWITCH - .get_ro = pcm970_sdhc1_get_ro, -#endif .init = pcm970_sdhc1_init, .exit = pcm970_sdhc1_exit, }; static struct platform_device *devices[] __initdata = { &pcm037_flash, + &pcm037_eth, &pcm037_sram_device, }; -static struct ipu_platform_data mx3_ipu_data = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static const struct fb_videomode fb_modedb[] = { - { - /* 240x320 @ 60 Hz Sharp */ - .name = "Sharp-LQ035Q7DH06-QVGA", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | - FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, +static int uart0_pins[] = { + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_RXD1__RXD1 }; -static struct mx3fb_platform_data mx3fb_pdata = { - .dma_dev = &mx3_ipu.dev, - .name = "Sharp-LQ035Q7DH06-QVGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), +static int uart2_pins[] = { + MX31_PIN_CSPI3_MOSI__RXD3, + MX31_PIN_CSPI3_MISO__TXD3 }; /* @@ -392,28 +215,21 @@ static struct mx3fb_platform_data mx3fb_pdata = { */ static void __init mxc_board_init(void) { - int ret; - - mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), - "pcm037"); - platform_add_devices(devices, ARRAY_SIZE(devices)); + mxc_iomux_setup_multiple_pins(uart0_pins, ARRAY_SIZE(uart0_pins), "uart-0"); mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); + + mxc_iomux_setup_multiple_pins(uart2_pins, ARRAY_SIZE(uart2_pins), "uart-2"); mxc_register_device(&mxc_uart_device2, &uart_pdata); + mxc_iomux_setup_pin(MX31_PIN_BATT_LINE__OWIRE, "batt-0wire"); mxc_register_device(&mxc_w1_master_device, NULL); /* LAN9217 IRQ pin */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else { + if (!mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), + "pcm037-eth")) gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); - platform_device_register(&pcm037_eth); - } - #ifdef CONFIG_I2C_IMX i2c_register_board_info(1, pcm037_i2c_devices, @@ -423,10 +239,6 @@ static void __init mxc_board_init(void) #endif mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - mxc_register_device(&mx3_fb, &mx3fb_pdata); - if (!gpio_usbotg_hs_activate()) - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } static void __init pcm037_timer_init(void) @@ -443,7 +255,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, + .map_io = mxc_map_io, .init_irq = mxc_init_irq, .init_machine = mxc_board_init, .timer = &pcm037_timer, diff --git a/trunk/arch/arm/mach-mx3/pcm043.c b/trunk/arch/arm/mach-mx3/pcm043.c deleted file mode 100644 index 8d27c324abf2..000000000000 --- a/trunk/arch/arm/mach-mx3/pcm043.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (C) 2009 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE -#include -#endif -#include -#include -#include - -#include "devices.h" - -static const struct fb_videomode fb_modedb[] = { - { - /* 240x320 @ 60 Hz */ - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct ipu_platform_data mx3_ipu_data = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct mx3fb_platform_data mx3fb_pdata = { - .dma_dev = &mx3_ipu.dev, - .name = "Sharp-LQ035Q7", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct physmap_flash_data pcm043_flash_data = { - .width = 2, -}; - -static struct resource pcm043_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm043_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &pcm043_flash_data, - }, - .resource = &pcm043_flash_resource, - .num_resources = 1, -}; - -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE -static struct imxi2c_platform_data pcm043_i2c_1_data = { - .bitrate = 50000, -}; - -static struct at24_platform_data board_eeprom = { - .byte_len = 4096, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info pcm043_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ - .platform_data = &board_eeprom, - }, { - I2C_BOARD_INFO("rtc-pcf8563", 0x51), - .type = "pcf8563", - } -}; -#endif - -static struct platform_device *devices[] __initdata = { - &pcm043_flash, - &mxc_fec_device, -}; - -static struct pad_desc pcm043_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* UART2 */ - MX35_PAD_CTS2__UART2_CTS, - MX35_PAD_RTS2__UART2_RTS, - MX35_PAD_TXD2__UART2_TXD_MUX, - MX35_PAD_RXD2__UART2_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_D3_REV__IPU_DISPB_D3_REV, - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, - MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL -}; - -/* - * Board specific initialization. - */ -static void __init mxc_board_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - mxc_register_device(&mxc_uart_device0, &uart_pdata); - - mxc_register_device(&mxc_uart_device1, &uart_pdata); - -#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE - i2c_register_board_info(0, pcm043_i2c_devices, - ARRAY_SIZE(pcm043_i2c_devices)); - - mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data); -#endif - - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - mxc_register_device(&mx3_fb, &mx3fb_pdata); -} - -static void __init pcm043_timer_init(void) -{ - mx35_clocks_init(); -} - -struct sys_timer pcm043_timer = { - .init = pcm043_timer_init, -}; - -MACHINE_START(PCM043, "Phytec Phycore pcm043") - /* Maintainer: Pengutronix */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx35_map_io, - .init_irq = mxc_init_irq, - .init_machine = mxc_board_init, - .timer = &pcm043_timer, -MACHINE_END - diff --git a/trunk/arch/arm/mach-mx3/qong.c b/trunk/arch/arm/mach-mx3/qong.c index 82b31c4ab11f..5a01e48fd8f1 100644 --- a/trunk/arch/arm/mach-mx3/qong.c +++ b/trunk/arch/arm/mach-mx3/qong.c @@ -279,7 +279,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx31_map_io, + .map_io = mxc_map_io, .init_irq = mxc_init_irq, .init_machine = mxc_board_init, .timer = &qong_timer, diff --git a/trunk/arch/arm/mach-netx/generic.c b/trunk/arch/arm/mach-netx/generic.c index 43da8bb4926b..79df60c20e70 100644 --- a/trunk/arch/arm/mach-netx/generic.c +++ b/trunk/arch/arm/mach-netx/generic.c @@ -168,7 +168,7 @@ void __init netx_init_irq(void) { int irq; - vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); + vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0); for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { set_irq_chip(irq, &netx_hif_chip); diff --git a/trunk/arch/arm/mach-omap1/Kconfig b/trunk/arch/arm/mach-omap1/Kconfig index 55ecc01ea206..cd8de89c5fad 100644 --- a/trunk/arch/arm/mach-omap1/Kconfig +++ b/trunk/arch/arm/mach-omap1/Kconfig @@ -46,6 +46,7 @@ config MACH_OMAP_H2 config MACH_OMAP_H3 bool "TI H3 Support" depends on ARCH_OMAP1 && ARCH_OMAP16XX +# select GPIOEXPANDER_OMAP help TI OMAP 1710 H3 board support. Say Y here if you have such a board. diff --git a/trunk/arch/arm/mach-omap1/Makefile b/trunk/arch/arm/mach-omap1/Makefile index 6867cd3ad0b4..1bda8f5d7546 100644 --- a/trunk/arch/arm/mach-omap1/Makefile +++ b/trunk/arch/arm/mach-omap1/Makefile @@ -13,10 +13,6 @@ obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o # Power Management obj-$(CONFIG_PM) += pm.o sleep.o -# DSP -obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o -mailbox_mach-objs := mailbox.o - led-y := leds.o # Specific board support diff --git a/trunk/arch/arm/mach-omap1/board-nokia770.c b/trunk/arch/arm/mach-omap1/board-nokia770.c index e70fc7c66bbb..d1ed1365319e 100644 --- a/trunk/arch/arm/mach-omap1/board-nokia770.c +++ b/trunk/arch/arm/mach-omap1/board-nokia770.c @@ -33,11 +33,8 @@ #include #include #include -#include #include #include -#include -#include #define ADS7846_PENDOWN_GPIO 15 @@ -165,15 +162,6 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = { }, }; -static struct hwa742_platform_data nokia770_hwa742_platform_data = { - .te_connected = 1, -}; - -static void hwa742_dev_init(void) -{ - clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL); - omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data); -} /* assume no Mini-AB port */ @@ -382,7 +370,6 @@ static void __init omap_nokia770_init(void) omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); omap_dsp_init(); - hwa742_dev_init(); ads7846_dev_init(); mipid_dev_init(); omap_usb_init(&nokia770_usb_config); diff --git a/trunk/arch/arm/mach-omap1/clock.c b/trunk/arch/arm/mach-omap1/clock.c index 436eed22801b..336e51dc6127 100644 --- a/trunk/arch/arm/mach-omap1/clock.c +++ b/trunk/arch/arm/mach-omap1/clock.c @@ -776,7 +776,7 @@ int __init omap1_clk_init(void) arm_idlect1_mask = ~0; for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) - clk_preinit(c->lk.clk); + clk_init_one(c->lk.clk); cpu_mask = 0; if (cpu_is_omap16xx()) diff --git a/trunk/arch/arm/mach-omap1/pm.c b/trunk/arch/arm/mach-omap1/pm.c index 5218943c91c0..9774c1f5311e 100644 --- a/trunk/arch/arm/mach-omap1/pm.c +++ b/trunk/arch/arm/mach-omap1/pm.c @@ -53,12 +53,11 @@ #include #include #include +#include #include #include #include -#include "pm.h" - static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; @@ -102,7 +101,7 @@ static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; * going idle we continue to do idle even if we get * a clock tick interrupt . . */ -void omap1_pm_idle(void) +void omap_pm_idle(void) { extern __u32 arm_idlect1_mask; __u32 use_idlect1 = arm_idlect1_mask; @@ -223,7 +222,7 @@ static void omap_pm_wakeup_setup(void) #define EN_APICK 6 /* ARM_IDLECT2 */ #define DSP_EN 1 /* ARM_RSTCT1 */ -void omap1_pm_suspend(void) +void omap_pm_suspend(void) { unsigned long arg0 = 0, arg1 = 0; @@ -611,7 +610,7 @@ static int omap_pm_enter(suspend_state_t state) { case PM_SUSPEND_STANDBY: case PM_SUSPEND_MEM: - omap1_pm_suspend(); + omap_pm_suspend(); break; default: return -EINVAL; @@ -684,7 +683,7 @@ static int __init omap_pm_init(void) return -ENODEV; } - pm_idle = omap1_pm_idle; + pm_idle = omap_pm_idle; if (cpu_is_omap730()) setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq); diff --git a/trunk/arch/arm/mach-omap1/serial.c b/trunk/arch/arm/mach-omap1/serial.c index f754cee4f3c3..842090b148f1 100644 --- a/trunk/arch/arm/mach-omap1/serial.c +++ b/trunk/arch/arm/mach-omap1/serial.c @@ -26,6 +26,9 @@ #include #include #include +#ifdef CONFIG_PM +#include +#endif static struct clk * uart1_ck; static struct clk * uart2_ck; diff --git a/trunk/arch/arm/mach-omap1/sleep.S b/trunk/arch/arm/mach-omap1/sleep.S index 22e8568339b0..f3eac932092d 100644 --- a/trunk/arch/arm/mach-omap1/sleep.S +++ b/trunk/arch/arm/mach-omap1/sleep.S @@ -35,7 +35,7 @@ #include #include #include -#include "pm.h" +#include .text diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index a755eb5e2361..64ab386a65c7 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -25,7 +25,7 @@ config ARCH_OMAP3430 select ARCH_OMAP_OTG comment "OMAP Board Type" - depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 + depends on ARCH_OMAP2 || ARCH_OMAP3 config MACH_OMAP_GENERIC bool "Generic OMAP board" @@ -56,10 +56,6 @@ config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 && ARCH_OMAP34XX -config MACH_OMAP3EVM - bool "OMAP 3530 EVM board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX - config MACH_OMAP3_PANDORA bool "OMAP3 Pandora" depends on ARCH_OMAP3 && ARCH_OMAP34XX @@ -71,11 +67,3 @@ config MACH_OMAP_3430SDP config MACH_NOKIA_RX51 bool "Nokia RX-51 board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - -config MACH_OMAP_ZOOM2 - bool "OMAP3 Zoom2 board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX - -config MACH_OMAP_4430SDP - bool "OMAP 4430 SDP board" - depends on ARCH_OMAP4 diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index 735bae5b0dec..c49d9bfa3abd 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -3,21 +3,12 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o - -omap-2-3-common = irq.o sdrc.o -prcm-common = prcm.o powerdomain.o -clock-common = clock.o clockdomain.o - -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) -obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) +obj-y := irq.o id.o io.o sdrc.o control.o prcm.o clock.o mux.o \ + devices.o serial.o gpmc.o timer-gp.o powerdomain.o \ + clockdomain.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o -# SMP support ONLY available for OMAP4 -obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o -obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o - # Functions loaded to SRAM obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o @@ -29,21 +20,14 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # Power Management ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o +obj-y += pm.o obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o -obj-$(CONFIG_PM_DEBUG) += pm-debug.o endif # Clock framework obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o -iommu-y += iommu2.o -iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o - -obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) - # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o @@ -56,8 +40,6 @@ obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ mmc-twl4030.o obj-$(CONFIG_MACH_OVERO) += board-overo.o \ mmc-twl4030.o -obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ - mmc-twl4030.o obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ mmc-twl4030.o obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ @@ -66,17 +48,8 @@ obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ board-rx51-peripherals.o \ mmc-twl4030.o -obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ - mmc-twl4030.o \ - board-zoom-debugboard.o - -obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o # Platform specific device init code +ifeq ($(CONFIG_USB_MUSB_SOC),y) obj-y += usb-musb.o - -onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o -obj-y += $(onenand-m) $(onenand-y) - -smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o -obj-y += $(smc91x-m) $(smc91x-y) +endif diff --git a/trunk/arch/arm/mach-omap2/board-2430sdp.c b/trunk/arch/arm/mach-omap2/board-2430sdp.c index 9c3fdcdf76c3..22143651037e 100644 --- a/trunk/arch/arm/mach-omap2/board-2430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-2430sdp.c @@ -36,12 +36,14 @@ #include #include #include -#include #include "mmc-twl4030.h" #define SDP2430_CS0_BASE 0x04000000 -#define SECONDARY_LCD_GPIO 147 +#define SDP2430_FLASH_CS 0 +#define SDP2430_SMC91X_CS 5 + +#define SDP2430_ETHR_GPIO_IRQ 149 static struct mtd_partition sdp2430_partitions[] = { /* bootloader (U-Boot, etc) in first sector */ @@ -97,53 +99,100 @@ static struct platform_device sdp2430_flash_device = { .resource = &sdp2430_flash_resource, }; -static struct platform_device sdp2430_lcd_device = { - .name = "sdp2430_lcd", +static struct resource sdp2430_smc91x_resources[] = { + [0] = { + .start = SDP2430_CS0_BASE, + .end = SDP2430_CS0_BASE + SZ_64M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ), + .end = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, +}; + +static struct platform_device sdp2430_smc91x_device = { + .name = "smc91x", .id = -1, + .num_resources = ARRAY_SIZE(sdp2430_smc91x_resources), + .resource = sdp2430_smc91x_resources, }; static struct platform_device *sdp2430_devices[] __initdata = { + &sdp2430_smc91x_device, &sdp2430_flash_device, - &sdp2430_lcd_device, }; -static struct omap_lcd_config sdp2430_lcd_config __initdata = { - .ctrl_name = "internal", -}; +static inline void __init sdp2430_init_smc91x(void) +{ + int eth_cs; + unsigned long cs_mem_base; + unsigned int rate; + struct clk *gpmc_fck; -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) + eth_cs = SDP2430_SMC91X_CS; -static struct omap_smc91x_platform_data board_smc91x_data = { - .cs = 5, - .gpio_irq = 149, - .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 | - IORESOURCE_IRQ_LOWLEVEL, + gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ + if (IS_ERR(gpmc_fck)) { + WARN_ON(1); + return; + } -}; + clk_enable(gpmc_fck); + rate = clk_get_rate(gpmc_fck); + + /* Make sure CS1 timings are correct, for 2430 always muxed */ + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); + + if (rate >= 160000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else if (rate >= 130000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else { /* rate = 100000000 */ + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); + } -static void __init board_smc91x_init(void) -{ - if (omap_rev() > OMAP3430_REV_ES1_0) - board_smc91x_data.gpio_irq = 6; - else - board_smc91x_data.gpio_irq = 29; + if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); + goto out; + } - gpmc_smc91x_init(&board_smc91x_data); -} + sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300; + sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; + udelay(100); -#else + if (gpio_request(SDP2430_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { + printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", + SDP2430_ETHR_GPIO_IRQ); + gpmc_cs_free(eth_cs); + goto out; + } + gpio_direction_input(SDP2430_ETHR_GPIO_IRQ); -static inline void board_smc91x_init(void) -{ +out: + clk_disable(gpmc_fck); + clk_put(gpmc_fck); } -#endif - static void __init omap_2430sdp_init_irq(void) { omap2_init_common_hw(NULL); omap_init_irq(); omap_gpio_init(); + sdp2430_init_smc91x(); } static struct omap_uart_config sdp2430_uart_config __initdata = { @@ -152,7 +201,6 @@ static struct omap_uart_config sdp2430_uart_config __initdata = { static struct omap_board_config_kernel sdp2430_config[] = { {OMAP_TAG_UART, &sdp2430_uart_config}, - {OMAP_TAG_LCD, &sdp2430_lcd_config}, }; @@ -200,8 +248,6 @@ static struct twl4030_hsmmc_info mmc[] __initdata = { static void __init omap_2430sdp_init(void) { - int ret; - omap2430_i2c_init(); platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); @@ -210,12 +256,6 @@ static void __init omap_2430sdp_init(void) omap_serial_init(); twl4030_mmc_init(mmc); usb_musb_init(); - board_smc91x_init(); - - /* Turn off secondary LCD backlight */ - ret = gpio_request(SECONDARY_LCD_GPIO, "Secondary LCD backlight"); - if (ret == 0) - gpio_direction_output(SECONDARY_LCD_GPIO, 0); } static void __init omap_2430sdp_map_io(void) diff --git a/trunk/arch/arm/mach-omap2/board-3430sdp.c b/trunk/arch/arm/mach-omap2/board-3430sdp.c index 496a90e4ea7a..ed9274972122 100644 --- a/trunk/arch/arm/mach-omap2/board-3430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3430sdp.c @@ -39,13 +39,15 @@ #include #include -#include -#include "sdram-qimonda-hyb18m512160af-6.h" #include "mmc-twl4030.h" #define CONFIG_DISABLE_HFCLK 1 +#define SDP3430_ETHR_GPIO_IRQ_SDPV1 29 +#define SDP3430_ETHR_GPIO_IRQ_SDPV2 6 +#define SDP3430_SMC91X_CS 3 + #define SDP3430_TS_GPIO_IRQ_SDPV1 3 #define SDP3430_TS_GPIO_IRQ_SDPV2 2 @@ -54,6 +56,24 @@ #define TWL4030_MSECURE_GPIO 22 +static struct resource sdp3430_smc91x_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, +}; + +static struct platform_device sdp3430_smc91x_device = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(sdp3430_smc91x_resources), + .resource = sdp3430_smc91x_resources, +}; + static int sdp3430_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_RIGHT), @@ -164,14 +184,48 @@ static struct regulator_consumer_supply sdp3430_vdvi_supply = { }; static struct platform_device *sdp3430_devices[] __initdata = { + &sdp3430_smc91x_device, &sdp3430_lcd_device, }; +static inline void __init sdp3430_init_smc91x(void) +{ + int eth_cs; + unsigned long cs_mem_base; + int eth_gpio = 0; + + eth_cs = SDP3430_SMC91X_CS; + + if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); + return; + } + + sdp3430_smc91x_resources[0].start = cs_mem_base + 0x300; + sdp3430_smc91x_resources[0].end = cs_mem_base + 0x30f; + udelay(100); + + if (omap_rev() > OMAP3430_REV_ES1_0) + eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV2; + else + eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV1; + + sdp3430_smc91x_resources[1].start = gpio_to_irq(eth_gpio); + + if (gpio_request(eth_gpio, "SMC91x irq") < 0) { + printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", + eth_gpio); + return; + } + gpio_direction_input(eth_gpio); +} + static void __init omap_3430sdp_init_irq(void) { - omap2_init_common_hw(hyb18m512160af6_sdrc_params); + omap2_init_common_hw(NULL); omap_init_irq(); omap_gpio_init(); + sdp3430_init_smc91x(); } static struct omap_uart_config sdp3430_uart_config __initdata = { @@ -452,32 +506,6 @@ static int __init omap3430_i2c_init(void) return 0; } -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) - -static struct omap_smc91x_platform_data board_smc91x_data = { - .cs = 3, - .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 | - IORESOURCE_IRQ_LOWLEVEL, -}; - -static void __init board_smc91x_init(void) -{ - if (omap_rev() > OMAP3430_REV_ES1_0) - board_smc91x_data.gpio_irq = 6; - else - board_smc91x_data.gpio_irq = 29; - - gpmc_smc91x_init(&board_smc91x_data); -} - -#else - -static inline void board_smc91x_init(void) -{ -} - -#endif - static void __init omap_3430sdp_init(void) { omap3430_i2c_init(); @@ -494,7 +522,6 @@ static void __init omap_3430sdp_init(void) ads7846_dev_init(); omap_serial_init(); usb_musb_init(); - board_smc91x_init(); } static void __init omap_3430sdp_map_io(void) diff --git a/trunk/arch/arm/mach-omap2/board-4430sdp.c b/trunk/arch/arm/mach-omap2/board-4430sdp.c deleted file mode 100644 index 57e477bd89c6..000000000000 --- a/trunk/arch/arm/mach-omap2/board-4430sdp.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Board support file for OMAP4430 SDP. - * - * Copyright (C) 2009 Texas Instruments - * - * Author: Santosh Shilimkar - * - * Based on mach-omap2/board-3430sdp.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -static struct platform_device sdp4430_lcd_device = { - .name = "sdp4430_lcd", - .id = -1, -}; - -static struct platform_device *sdp4430_devices[] __initdata = { - &sdp4430_lcd_device, -}; - -static struct omap_uart_config sdp4430_uart_config __initdata = { - .enabled_uarts = (1 << 0) | (1 << 1) | (1 << 2), -}; - -static struct omap_lcd_config sdp4430_lcd_config __initdata = { - .ctrl_name = "internal", -}; - -static struct omap_board_config_kernel sdp4430_config[] __initdata = { - { OMAP_TAG_UART, &sdp4430_uart_config }, - { OMAP_TAG_LCD, &sdp4430_lcd_config }, -}; - -static void __init gic_init_irq(void) -{ - gic_dist_init(0, IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29); - gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); -} - -static void __init omap_4430sdp_init_irq(void) -{ - omap2_init_common_hw(NULL); -#ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(1); -#endif - gic_init_irq(); - omap_gpio_init(); -} - - -static void __init omap_4430sdp_init(void) -{ - platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); - omap_board_config = sdp4430_config; - omap_board_config_size = ARRAY_SIZE(sdp4430_config); - omap_serial_init(); -} - -static void __init omap_4430sdp_map_io(void) -{ - omap2_set_globals_443x(); - omap2_map_common_io(); -} - -MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") - /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ - .phys_io = 0x48000000, - .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_4430sdp_map_io, - .init_irq = omap_4430sdp_init_irq, - .init_machine = omap_4430sdp_init, - .timer = &omap_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-ldp.c b/trunk/arch/arm/mach-omap2/board-ldp.c index d8bc0a7dcb8d..da57b0fcda14 100644 --- a/trunk/arch/arm/mach-omap2/board-ldp.c +++ b/trunk/arch/arm/mach-omap2/board-ldp.c @@ -16,13 +16,11 @@ #include #include #include -#include #include #include #include #include #include -#include #include #include #include @@ -41,7 +39,6 @@ #include #include #include -#include #include "mmc-twl4030.h" @@ -80,163 +77,8 @@ static struct platform_device ldp_smsc911x_device = { }, }; -static int ldp_twl4030_keymap[] = { - KEY(0, 0, KEY_1), - KEY(1, 0, KEY_2), - KEY(2, 0, KEY_3), - KEY(0, 1, KEY_4), - KEY(1, 1, KEY_5), - KEY(2, 1, KEY_6), - KEY(3, 1, KEY_F5), - KEY(0, 2, KEY_7), - KEY(1, 2, KEY_8), - KEY(2, 2, KEY_9), - KEY(3, 2, KEY_F6), - KEY(0, 3, KEY_F7), - KEY(1, 3, KEY_0), - KEY(2, 3, KEY_F8), - PERSISTENT_KEY(4, 5), - KEY(4, 4, KEY_VOLUMEUP), - KEY(5, 5, KEY_VOLUMEDOWN), - 0 -}; - -static struct twl4030_keypad_data ldp_kp_twl4030_data = { - .rows = 6, - .cols = 6, - .keymap = ldp_twl4030_keymap, - .keymapsize = ARRAY_SIZE(ldp_twl4030_keymap), - .rep = 1, -}; - -static struct gpio_keys_button ldp_gpio_keys_buttons[] = { - [0] = { - .code = KEY_ENTER, - .gpio = 101, - .desc = "enter sw", - .active_low = 1, - .debounce_interval = 30, - }, - [1] = { - .code = KEY_F1, - .gpio = 102, - .desc = "func 1", - .active_low = 1, - .debounce_interval = 30, - }, - [2] = { - .code = KEY_F2, - .gpio = 103, - .desc = "func 2", - .active_low = 1, - .debounce_interval = 30, - }, - [3] = { - .code = KEY_F3, - .gpio = 104, - .desc = "func 3", - .active_low = 1, - .debounce_interval = 30, - }, - [4] = { - .code = KEY_F4, - .gpio = 105, - .desc = "func 4", - .active_low = 1, - .debounce_interval = 30, - }, - [5] = { - .code = KEY_LEFT, - .gpio = 106, - .desc = "left sw", - .active_low = 1, - .debounce_interval = 30, - }, - [6] = { - .code = KEY_RIGHT, - .gpio = 107, - .desc = "right sw", - .active_low = 1, - .debounce_interval = 30, - }, - [7] = { - .code = KEY_UP, - .gpio = 108, - .desc = "up sw", - .active_low = 1, - .debounce_interval = 30, - }, - [8] = { - .code = KEY_DOWN, - .gpio = 109, - .desc = "down sw", - .active_low = 1, - .debounce_interval = 30, - }, -}; - -static struct gpio_keys_platform_data ldp_gpio_keys = { - .buttons = ldp_gpio_keys_buttons, - .nbuttons = ARRAY_SIZE(ldp_gpio_keys_buttons), - .rep = 1, -}; - -static struct platform_device ldp_gpio_keys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &ldp_gpio_keys, - }, -}; - -static int ts_gpio; - -/** - * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq - * - * @return - void. If request gpio fails then Flag KERN_ERR. - */ -static void ads7846_dev_init(void) -{ - if (gpio_request(ts_gpio, "ads7846 irq") < 0) { - printk(KERN_ERR "can't get ads746 pen down GPIO\n"); - return; - } - - gpio_direction_input(ts_gpio); - omap_set_gpio_debounce(ts_gpio, 1); - omap_set_gpio_debounce_time(ts_gpio, 0xa); -} - -static int ads7846_get_pendown_state(void) -{ - return !gpio_get_value(ts_gpio); -} - -static struct ads7846_platform_data tsc2046_config __initdata = { - .get_pendown_state = ads7846_get_pendown_state, - .keep_vref_on = 1, -}; - -static struct omap2_mcspi_device_config tsc2046_mcspi_config = { - .turbo_mode = 0, - .single_channel = 1, /* 0: slave, 1: master */ -}; - -static struct spi_board_info ldp_spi_board_info[] __initdata = { - [0] = { - /* - * TSC2046 operates at a max freqency of 2MHz, so - * operate slightly below at 1.5MHz - */ - .modalias = "ads7846", - .bus_num = 1, - .chip_select = 0, - .max_speed_hz = 1500000, - .controller_data = &tsc2046_mcspi_config, - .irq = 0, - .platform_data = &tsc2046_config, - }, +static struct platform_device *ldp_devices[] __initdata = { + &ldp_smsc911x_device, }; static inline void __init ldp_init_smsc911x(void) @@ -280,22 +122,8 @@ static struct omap_uart_config ldp_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; -static struct platform_device ldp_lcd_device = { - .name = "ldp_lcd", - .id = -1, -}; - -static struct omap_lcd_config ldp_lcd_config __initdata = { - .ctrl_name = "internal", -}; - static struct omap_board_config_kernel ldp_config[] __initdata = { { OMAP_TAG_UART, &ldp_uart_config }, - { OMAP_TAG_LCD, &ldp_lcd_config }, -}; - -static struct twl4030_usb_data ldp_usb_data = { - .usb_mode = T2_USB_MODE_ULPI, }; static struct twl4030_gpio_platform_data ldp_gpio_data = { @@ -304,39 +132,12 @@ static struct twl4030_gpio_platform_data ldp_gpio_data = { .irq_end = TWL4030_GPIO_IRQ_END, }; -static struct twl4030_madc_platform_data ldp_madc_data = { - .irq_line = 1, -}; - -static struct regulator_consumer_supply ldp_vmmc1_supply = { - .supply = "vmmc", -}; - -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data ldp_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &ldp_vmmc1_supply, -}; - static struct twl4030_platform_data ldp_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, /* platform_data for children goes here */ - .madc = &ldp_madc_data, - .usb = &ldp_usb_data, - .vmmc1 = &ldp_vmmc1, .gpio = &ldp_gpio_data, - .keypad = &ldp_kp_twl4030_data, }; static struct i2c_board_info __initdata ldp_i2c_boardinfo[] = { @@ -367,29 +168,15 @@ static struct twl4030_hsmmc_info mmc[] __initdata = { {} /* Terminator */ }; -static struct platform_device *ldp_devices[] __initdata = { - &ldp_smsc911x_device, - &ldp_lcd_device, - &ldp_gpio_keys_device, -}; - static void __init omap_ldp_init(void) { omap_i2c_init(); platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); omap_board_config = ldp_config; omap_board_config_size = ARRAY_SIZE(ldp_config); - ts_gpio = 54; - ldp_spi_board_info[0].irq = gpio_to_irq(ts_gpio); - spi_register_board_info(ldp_spi_board_info, - ARRAY_SIZE(ldp_spi_board_info)); - ads7846_dev_init(); omap_serial_init(); - usb_musb_init(); - twl4030_mmc_init(mmc); - /* link regulators to MMC adapters */ - ldp_vmmc1_supply.dev = mmc[0].dev; + usb_musb_init(); } static void __init omap_ldp_map_io(void) diff --git a/trunk/arch/arm/mach-omap2/board-omap3beagle.c b/trunk/arch/arm/mach-omap2/board-omap3beagle.c index 991ac9c38032..3a7a29d1f9a7 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3beagle.c +++ b/trunk/arch/arm/mach-omap2/board-omap3beagle.c @@ -28,7 +28,6 @@ #include #include -#include #include #include @@ -106,8 +105,6 @@ static struct platform_device omap3beagle_nand_device = { .resource = &omap3beagle_nand_resource, }; -#include "sdram-micron-mt46h32m32lf-6.h" - static struct omap_uart_config omap3_beagle_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; @@ -121,23 +118,6 @@ static struct twl4030_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct platform_device omap3_beagle_lcd_device = { - .name = "omap3beagle_lcd", - .id = -1, -}; - -static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { - .ctrl_name = "internal", -}; - -static struct regulator_consumer_supply beagle_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply beagle_vsim_supply = { - .supply = "vmmc_aux", -}; - static struct gpio_led gpio_leds[]; static int beagle_twl_gpio_setup(struct device *dev, @@ -148,10 +128,6 @@ static int beagle_twl_gpio_setup(struct device *dev, mmc[0].gpio_cd = gpio + 0; twl4030_mmc_init(mmc); - /* link regulators to MMC adapters */ - beagle_vmmc1_supply.dev = mmc[0].dev; - beagle_vsim_supply.dev = mmc[0].dev; - /* REVISIT: need ehci-omap hooks for external VBUS * power switch and overcurrent detect */ @@ -180,85 +156,12 @@ static struct twl4030_gpio_platform_data beagle_gpio_data = { .setup = beagle_twl_gpio_setup, }; -static struct regulator_consumer_supply beagle_vdac_supply = { - .supply = "vdac", - .dev = &omap3_beagle_lcd_device.dev, -}; - -static struct regulator_consumer_supply beagle_vdvi_supply = { - .supply = "vdvi", - .dev = &omap3_beagle_lcd_device.dev, -}; - -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data beagle_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &beagle_vmmc1_supply, -}; - -/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ -static struct regulator_init_data beagle_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &beagle_vsim_supply, -}; - -/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ -static struct regulator_init_data beagle_vdac = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &beagle_vdac_supply, -}; - -/* VPLL2 for digital video outputs */ -static struct regulator_init_data beagle_vpll2 = { - .constraints = { - .name = "VDVI", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &beagle_vdvi_supply, -}; - static struct twl4030_platform_data beagle_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, /* platform_data for children goes here */ .gpio = &beagle_gpio_data, - .vmmc1 = &beagle_vmmc1, - .vsim = &beagle_vsim, - .vdac = &beagle_vdac, - .vpll2 = &beagle_vpll2, }; static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = { @@ -282,7 +185,7 @@ static int __init omap3_beagle_i2c_init(void) static void __init omap3_beagle_init_irq(void) { - omap2_init_common_hw(mt46h32m32lf6_sdrc_params); + omap2_init_common_hw(NULL); omap_init_irq(); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); @@ -290,6 +193,15 @@ static void __init omap3_beagle_init_irq(void) omap_gpio_init(); } +static struct platform_device omap3_beagle_lcd_device = { + .name = "omap3beagle_lcd", + .id = -1, +}; + +static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { + .ctrl_name = "internal", +}; + static struct gpio_led gpio_leds[] = { { .name = "beagleboard::usr0", diff --git a/trunk/arch/arm/mach-omap2/board-omap3evm.c b/trunk/arch/arm/mach-omap2/board-omap3evm.c deleted file mode 100644 index d3cc145814d0..000000000000 --- a/trunk/arch/arm/mach-omap2/board-omap3evm.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-omap3evm.c - * - * Copyright (C) 2008 Texas Instruments - * - * Modified from mach-omap2/board-3430sdp.c - * - * Initial code: Syed Mohammed Khasim - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "sdram-micron-mt46h32m32lf-6.h" -#include "mmc-twl4030.h" - -#define OMAP3_EVM_TS_GPIO 175 - -#define OMAP3EVM_ETHR_START 0x2c000000 -#define OMAP3EVM_ETHR_SIZE 1024 -#define OMAP3EVM_ETHR_GPIO_IRQ 176 -#define OMAP3EVM_SMC911X_CS 5 - -static struct resource omap3evm_smc911x_resources[] = { - [0] = { - .start = OMAP3EVM_ETHR_START, - .end = (OMAP3EVM_ETHR_START + OMAP3EVM_ETHR_SIZE - 1), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = OMAP_GPIO_IRQ(OMAP3EVM_ETHR_GPIO_IRQ), - .end = OMAP_GPIO_IRQ(OMAP3EVM_ETHR_GPIO_IRQ), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device omap3evm_smc911x_device = { - .name = "smc911x", - .id = -1, - .num_resources = ARRAY_SIZE(omap3evm_smc911x_resources), - .resource = &omap3evm_smc911x_resources[0], -}; - -static inline void __init omap3evm_init_smc911x(void) -{ - int eth_cs; - struct clk *l3ck; - unsigned int rate; - - eth_cs = OMAP3EVM_SMC911X_CS; - - l3ck = clk_get(NULL, "l3_ck"); - if (IS_ERR(l3ck)) - rate = 100000000; - else - rate = clk_get_rate(l3ck); - - if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMC911x irq") < 0) { - printk(KERN_ERR "Failed to request GPIO%d for smc911x IRQ\n", - OMAP3EVM_ETHR_GPIO_IRQ); - return; - } - - gpio_direction_input(OMAP3EVM_ETHR_GPIO_IRQ); -} - -static struct omap_uart_config omap3_evm_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - -static struct twl4030_hsmmc_info mmc[] = { - { - .mmc = 1, - .wires = 4, - .gpio_cd = -EINVAL, - .gpio_wp = 63, - }, - {} /* Terminator */ -}; - -static struct gpio_led gpio_leds[] = { - { - .name = "omap3evm::ledb", - /* normally not visible (board underside) */ - .default_trigger = "default-on", - .gpio = -EINVAL, /* gets replaced */ - .active_low = true, - }, -}; - -static struct gpio_led_platform_data gpio_led_info = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &gpio_led_info, - }, -}; - - -static int omap3evm_twl_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) -{ - /* gpio + 0 is "mmc0_cd" (input/IRQ) */ - omap_cfg_reg(L8_34XX_GPIO63); - mmc[0].gpio_cd = gpio + 0; - twl4030_mmc_init(mmc); - - /* - * Most GPIOs are for USB OTG. Some are mostly sent to - * the P2 connector; notably LEDA for the LCD backlight. - */ - - /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; - - platform_device_register(&leds_gpio); - - return 0; -} - -static struct twl4030_gpio_platform_data omap3evm_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, - .use_leds = true, - .setup = omap3evm_twl_gpio_setup, -}; - -static struct twl4030_usb_data omap3evm_usb_data = { - .usb_mode = T2_USB_MODE_ULPI, -}; - -static int omap3evm_keymap[] = { - KEY(0, 0, KEY_LEFT), - KEY(0, 1, KEY_RIGHT), - KEY(0, 2, KEY_A), - KEY(0, 3, KEY_B), - KEY(1, 0, KEY_DOWN), - KEY(1, 1, KEY_UP), - KEY(1, 2, KEY_E), - KEY(1, 3, KEY_F), - KEY(2, 0, KEY_ENTER), - KEY(2, 1, KEY_I), - KEY(2, 2, KEY_J), - KEY(2, 3, KEY_K), - KEY(3, 0, KEY_M), - KEY(3, 1, KEY_N), - KEY(3, 2, KEY_O), - KEY(3, 3, KEY_P) -}; - -static struct twl4030_keypad_data omap3evm_kp_data = { - .rows = 4, - .cols = 4, - .keymap = omap3evm_keymap, - .keymapsize = ARRAY_SIZE(omap3evm_keymap), - .rep = 1, -}; - -static struct twl4030_madc_platform_data omap3evm_madc_data = { - .irq_line = 1, -}; - -static struct twl4030_platform_data omap3evm_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, - - /* platform_data for children goes here */ - .keypad = &omap3evm_kp_data, - .madc = &omap3evm_madc_data, - .usb = &omap3evm_usb_data, - .gpio = &omap3evm_gpio_data, -}; - -static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = { - { - I2C_BOARD_INFO("twl4030", 0x48), - .flags = I2C_CLIENT_WAKE, - .irq = INT_34XX_SYS_NIRQ, - .platform_data = &omap3evm_twldata, - }, -}; - -static int __init omap3_evm_i2c_init(void) -{ - omap_register_i2c_bus(1, 2600, omap3evm_i2c_boardinfo, - ARRAY_SIZE(omap3evm_i2c_boardinfo)); - omap_register_i2c_bus(2, 400, NULL, 0); - omap_register_i2c_bus(3, 400, NULL, 0); - return 0; -} - -static struct platform_device omap3_evm_lcd_device = { - .name = "omap3evm_lcd", - .id = -1, -}; - -static struct omap_lcd_config omap3_evm_lcd_config __initdata = { - .ctrl_name = "internal", -}; - -static void ads7846_dev_init(void) -{ - if (gpio_request(OMAP3_EVM_TS_GPIO, "ADS7846 pendown") < 0) - printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); - - gpio_direction_input(OMAP3_EVM_TS_GPIO); - - omap_set_gpio_debounce(OMAP3_EVM_TS_GPIO, 1); - omap_set_gpio_debounce_time(OMAP3_EVM_TS_GPIO, 0xa); -} - -static int ads7846_get_pendown_state(void) -{ - return !gpio_get_value(OMAP3_EVM_TS_GPIO); -} - -struct ads7846_platform_data ads7846_config = { - .x_max = 0x0fff, - .y_max = 0x0fff, - .x_plate_ohms = 180, - .pressure_max = 255, - .debounce_max = 10, - .debounce_tol = 3, - .debounce_rep = 1, - .get_pendown_state = ads7846_get_pendown_state, - .keep_vref_on = 1, - .settle_delay_usecs = 150, -}; - -static struct omap2_mcspi_device_config ads7846_mcspi_config = { - .turbo_mode = 0, - .single_channel = 1, /* 0: slave, 1: master */ -}; - -struct spi_board_info omap3evm_spi_board_info[] = { - [0] = { - .modalias = "ads7846", - .bus_num = 1, - .chip_select = 0, - .max_speed_hz = 1500000, - .controller_data = &ads7846_mcspi_config, - .irq = OMAP_GPIO_IRQ(OMAP3_EVM_TS_GPIO), - .platform_data = &ads7846_config, - }, -}; - -static void __init omap3_evm_init_irq(void) -{ - omap2_init_common_hw(mt46h32m32lf6_sdrc_params); - omap_init_irq(); - omap_gpio_init(); - omap3evm_init_smc911x(); -} - -static struct omap_board_config_kernel omap3_evm_config[] __initdata = { - { OMAP_TAG_UART, &omap3_evm_uart_config }, - { OMAP_TAG_LCD, &omap3_evm_lcd_config }, -}; - -static struct platform_device *omap3_evm_devices[] __initdata = { - &omap3_evm_lcd_device, - &omap3evm_smc911x_device, -}; - -static void __init omap3_evm_init(void) -{ - omap3_evm_i2c_init(); - - platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices)); - omap_board_config = omap3_evm_config; - omap_board_config_size = ARRAY_SIZE(omap3_evm_config); - - spi_register_board_info(omap3evm_spi_board_info, - ARRAY_SIZE(omap3evm_spi_board_info)); - - omap_serial_init(); - usb_musb_init(); - ads7846_dev_init(); -} - -static void __init omap3_evm_map_io(void) -{ - omap2_set_globals_343x(); - omap2_map_common_io(); -} - -MACHINE_START(OMAP3EVM, "OMAP3 EVM") - /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ - .phys_io = 0x48000000, - .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap3_evm_map_io, - .init_irq = omap3_evm_init_irq, - .init_machine = omap3_evm_init, - .timer = &omap_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-omap3pandora.c b/trunk/arch/arm/mach-omap2/board-omap3pandora.c index e32aa23ce962..402f09c6cf10 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3pandora.c +++ b/trunk/arch/arm/mach-omap2/board-omap3pandora.c @@ -23,11 +23,7 @@ #include #include -#include #include -#include -#include -#include #include #include @@ -39,154 +35,11 @@ #include #include #include -#include -#include "sdram-micron-mt46h32m32lf-6.h" #include "mmc-twl4030.h" #define OMAP3_PANDORA_TS_GPIO 94 -/* hardware debounce: (value + 1) * 31us */ -#define GPIO_DEBOUNCE_TIME 127 - -static struct gpio_led pandora_gpio_leds[] = { - { - .name = "pandora::sd1", - .default_trigger = "mmc0", - .gpio = 128, - }, { - .name = "pandora::sd2", - .default_trigger = "mmc1", - .gpio = 129, - }, { - .name = "pandora::bluetooth", - .gpio = 158, - }, { - .name = "pandora::wifi", - .gpio = 159, - }, -}; - -static struct gpio_led_platform_data pandora_gpio_led_data = { - .leds = pandora_gpio_leds, - .num_leds = ARRAY_SIZE(pandora_gpio_leds), -}; - -static struct platform_device pandora_leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &pandora_gpio_led_data, - }, -}; - -#define GPIO_BUTTON(gpio_num, ev_type, ev_code, act_low, descr) \ -{ \ - .gpio = gpio_num, \ - .type = ev_type, \ - .code = ev_code, \ - .active_low = act_low, \ - .desc = "btn " descr, \ -} - -#define GPIO_BUTTON_LOW(gpio_num, event_code, description) \ - GPIO_BUTTON(gpio_num, EV_KEY, event_code, 1, description) - -static struct gpio_keys_button pandora_gpio_keys[] = { - GPIO_BUTTON_LOW(110, KEY_UP, "up"), - GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), - GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), - GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), - GPIO_BUTTON_LOW(111, BTN_A, "a"), - GPIO_BUTTON_LOW(106, BTN_B, "b"), - GPIO_BUTTON_LOW(109, BTN_X, "x"), - GPIO_BUTTON_LOW(101, BTN_Y, "y"), - GPIO_BUTTON_LOW(102, BTN_TL, "l"), - GPIO_BUTTON_LOW(97, BTN_TL2, "l2"), - GPIO_BUTTON_LOW(105, BTN_TR, "r"), - GPIO_BUTTON_LOW(107, BTN_TR2, "r2"), - GPIO_BUTTON_LOW(104, KEY_LEFTCTRL, "ctrl"), - GPIO_BUTTON_LOW(99, KEY_MENU, "menu"), - GPIO_BUTTON_LOW(176, KEY_COFFEE, "hold"), - GPIO_BUTTON(100, EV_KEY, KEY_LEFTALT, 0, "alt"), - GPIO_BUTTON(108, EV_SW, SW_LID, 1, "lid"), -}; - -static struct gpio_keys_platform_data pandora_gpio_key_info = { - .buttons = pandora_gpio_keys, - .nbuttons = ARRAY_SIZE(pandora_gpio_keys), -}; - -static struct platform_device pandora_keys_gpio = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &pandora_gpio_key_info, - }, -}; - -static void __init pandora_keys_gpio_init(void) -{ - /* set debounce time for GPIO banks 4 and 6 */ - omap_set_gpio_debounce_time(32 * 3, GPIO_DEBOUNCE_TIME); - omap_set_gpio_debounce_time(32 * 5, GPIO_DEBOUNCE_TIME); -} - -static int pandora_keypad_map[] = { - /* col, row, code */ - KEY(0, 0, KEY_9), - KEY(0, 1, KEY_0), - KEY(0, 2, KEY_BACKSPACE), - KEY(0, 3, KEY_O), - KEY(0, 4, KEY_P), - KEY(0, 5, KEY_K), - KEY(0, 6, KEY_L), - KEY(0, 7, KEY_ENTER), - KEY(1, 0, KEY_8), - KEY(1, 1, KEY_7), - KEY(1, 2, KEY_6), - KEY(1, 3, KEY_5), - KEY(1, 4, KEY_4), - KEY(1, 5, KEY_3), - KEY(1, 6, KEY_2), - KEY(1, 7, KEY_1), - KEY(2, 0, KEY_I), - KEY(2, 1, KEY_U), - KEY(2, 2, KEY_Y), - KEY(2, 3, KEY_T), - KEY(2, 4, KEY_R), - KEY(2, 5, KEY_E), - KEY(2, 6, KEY_W), - KEY(2, 7, KEY_Q), - KEY(3, 0, KEY_J), - KEY(3, 1, KEY_H), - KEY(3, 2, KEY_G), - KEY(3, 3, KEY_F), - KEY(3, 4, KEY_D), - KEY(3, 5, KEY_S), - KEY(3, 6, KEY_A), - KEY(3, 7, KEY_LEFTSHIFT), - KEY(4, 0, KEY_N), - KEY(4, 1, KEY_B), - KEY(4, 2, KEY_V), - KEY(4, 3, KEY_C), - KEY(4, 4, KEY_X), - KEY(4, 5, KEY_Z), - KEY(4, 6, KEY_DOT), - KEY(4, 7, KEY_COMMA), - KEY(5, 0, KEY_M), - KEY(5, 1, KEY_SPACE), - KEY(5, 2, KEY_FN), -}; - -static struct twl4030_keypad_data pandora_kp_data = { - .rows = 8, - .cols = 6, - .keymap = pandora_keypad_map, - .keymapsize = ARRAY_SIZE(pandora_keypad_map), - .rep = 1, -}; - static struct twl4030_hsmmc_info omap3pandora_mmc[] = { { .mmc = 1, @@ -216,14 +69,6 @@ static struct omap_uart_config omap3pandora_uart_config __initdata = { .enabled_uarts = (1 << 2), /* UART3 */ }; -static struct regulator_consumer_supply pandora_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply pandora_vmmc2_supply = { - .supply = "vmmc", -}; - static int omap3pandora_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -232,10 +77,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev, omap3pandora_mmc[1].gpio_cd = gpio + 1; twl4030_mmc_init(omap3pandora_mmc); - /* link regulators to MMC adapters */ - pandora_vmmc1_supply.dev = omap3pandora_mmc[0].dev; - pandora_vmmc2_supply.dev = omap3pandora_mmc[1].dev; - return 0; } @@ -246,36 +87,6 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { .setup = omap3pandora_twl_gpio_setup, }; -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data pandora_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &pandora_vmmc1_supply, -}; - -/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */ -static struct regulator_init_data pandora_vmmc2 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &pandora_vmmc2_supply, -}; - static struct twl4030_usb_data omap3pandora_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; @@ -285,9 +96,6 @@ static struct twl4030_platform_data omap3pandora_twldata = { .irq_end = TWL4030_IRQ_END, .gpio = &omap3pandora_gpio_data, .usb = &omap3pandora_usb_data, - .vmmc1 = &pandora_vmmc1, - .vmmc2 = &pandora_vmmc2, - .keypad = &pandora_kp_data, }; static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = { @@ -310,7 +118,7 @@ static int __init omap3pandora_i2c_init(void) static void __init omap3pandora_init_irq(void) { - omap2_init_common_hw(mt46h32m32lf6_sdrc_params); + omap2_init_common_hw(NULL); omap_init_irq(); omap_gpio_init(); } @@ -380,8 +188,6 @@ static struct omap_board_config_kernel omap3pandora_config[] __initdata = { static struct platform_device *omap3pandora_devices[] __initdata = { &omap3pandora_lcd_device, - &pandora_leds_gpio, - &pandora_keys_gpio, }; static void __init omap3pandora_init(void) @@ -395,7 +201,6 @@ static void __init omap3pandora_init(void) spi_register_board_info(omap3pandora_spi_board_info, ARRAY_SIZE(omap3pandora_spi_board_info)); omap3pandora_ads7846_init(); - pandora_keys_gpio_init(); usb_musb_init(); } diff --git a/trunk/arch/arm/mach-omap2/board-overo.c b/trunk/arch/arm/mach-omap2/board-overo.c index dff5528fbfb5..b1f23bea863f 100644 --- a/trunk/arch/arm/mach-omap2/board-overo.c +++ b/trunk/arch/arm/mach-omap2/board-overo.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -46,7 +45,6 @@ #include #include -#include "sdram-micron-mt46h32m32lf-6.h" #include "mmc-twl4030.h" #define OVERO_GPIO_BT_XGATE 15 @@ -273,76 +271,21 @@ static struct omap_uart_config overo_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; -static struct twl4030_hsmmc_info mmc[] = { - { - .mmc = 1, - .wires = 4, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - }, - { - .mmc = 2, - .wires = 4, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - .transceiver = true, - .ocr_mask = 0x00100000, /* 3.3V */ - }, - {} /* Terminator */ -}; - -static struct regulator_consumer_supply overo_vmmc1_supply = { - .supply = "vmmc", -}; - -static int overo_twl_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) -{ - twl4030_mmc_init(mmc); - - overo_vmmc1_supply.dev = mmc[0].dev; - - return 0; -} - static struct twl4030_gpio_platform_data overo_gpio_data = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, - .setup = overo_twl_gpio_setup, -}; - -static struct twl4030_usb_data overo_usb_data = { - .usb_mode = T2_USB_MODE_ULPI, -}; - -static struct regulator_init_data overo_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &overo_vmmc1_supply, }; -/* mmc2 (WLAN) and Bluetooth don't use twl4030 regulators */ - static struct twl4030_platform_data overo_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, .gpio = &overo_gpio_data, - .usb = &overo_usb_data, - .vmmc1 = &overo_vmmc1, }; static struct i2c_board_info __initdata overo_i2c_boardinfo[] = { { - I2C_BOARD_INFO("tps65950", 0x48), + I2C_BOARD_INFO("twl4030", 0x48), .flags = I2C_CLIENT_WAKE, .irq = INT_34XX_SYS_NIRQ, .platform_data = &overo_twldata, @@ -360,7 +303,7 @@ static int __init overo_i2c_init(void) static void __init overo_init_irq(void) { - omap2_init_common_hw(mt46h32m32lf6_sdrc_params); + omap2_init_common_hw(NULL); omap_init_irq(); omap_gpio_init(); } @@ -383,6 +326,23 @@ static struct platform_device *overo_devices[] __initdata = { &overo_lcd_device, }; +static struct twl4030_hsmmc_info mmc[] __initdata = { + { + .mmc = 1, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + { + .mmc = 2, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + .transceiver = true, + }, + {} /* Terminator */ +}; + static void __init overo_init(void) { overo_i2c_init(); @@ -390,6 +350,7 @@ static void __init overo_init(void) omap_board_config = overo_config; omap_board_config_size = ARRAY_SIZE(overo_config); omap_serial_init(); + twl4030_mmc_init(mmc); overo_flash_init(); usb_musb_init(); overo_ads7846_init(); diff --git a/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c b/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c index da93b86234ed..a7381729645c 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -27,13 +27,30 @@ #include #include #include -#include -#include #include "mmc-twl4030.h" -#define SYSTEM_REV_B_USES_VAUX3 0x1699 -#define SYSTEM_REV_S_USES_VAUX3 0x8 + +#define SMC91X_CS 1 +#define SMC91X_GPIO_IRQ 54 +#define SMC91X_GPIO_RESET 164 +#define SMC91X_GPIO_PWRDWN 86 + +static struct resource rx51_smc91x_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, + [1] = { + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + }, +}; + +static struct platform_device rx51_smc91x_device = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(rx51_smc91x_resources), + .resource = rx51_smc91x_resources, +}; static int rx51_keymap[] = { KEY(0, 0, KEY_Q), @@ -90,6 +107,98 @@ static struct twl4030_keypad_data rx51_kp_data = { .rep = 1, }; +static struct platform_device *rx51_peripherals_devices[] = { + &rx51_smc91x_device, +}; + +/* + * Timings are taken from smsc-lan91c96-ms.pdf + */ +static int smc91x_init_gpmc(int cs) +{ + struct gpmc_timings t; + const int t2_r = 45; /* t2 in Figure 12.10 */ + const int t2_w = 30; /* t2 in Figure 12.11 */ + const int t3 = 15; /* t3 in Figure 12.10 */ + const int t5_r = 0; /* t5 in Figure 12.10 */ + const int t6_r = 45; /* t6 in Figure 12.10 */ + const int t6_w = 0; /* t6 in Figure 12.11 */ + const int t7_w = 15; /* t7 in Figure 12.11 */ + const int t15 = 12; /* t15 in Figure 12.2 */ + const int t20 = 185; /* t20 in Figure 12.2 */ + + memset(&t, 0, sizeof(t)); + + t.cs_on = t15; + t.cs_rd_off = t3 + t2_r + t5_r; /* Figure 12.10 */ + t.cs_wr_off = t3 + t2_w + t6_w; /* Figure 12.11 */ + t.adv_on = t3; /* Figure 12.10 */ + t.adv_rd_off = t3 + t2_r; /* Figure 12.10 */ + t.adv_wr_off = t3 + t2_w; /* Figure 12.11 */ + t.oe_off = t3 + t2_r + t5_r; /* Figure 12.10 */ + t.oe_on = t.oe_off - t6_r; /* Figure 12.10 */ + t.we_off = t3 + t2_w + t6_w; /* Figure 12.11 */ + t.we_on = t.we_off - t7_w; /* Figure 12.11 */ + t.rd_cycle = t20; /* Figure 12.2 */ + t.wr_cycle = t20; /* Figure 12.4 */ + t.access = t3 + t2_r + t5_r; /* Figure 12.10 */ + t.wr_access = t3 + t2_w + t6_w; /* Figure 12.11 */ + + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE_16); + + return gpmc_cs_set_timings(cs, &t); +} + +static void __init rx51_init_smc91x(void) +{ + unsigned long cs_mem_base; + int ret; + + omap_cfg_reg(U8_34XX_GPIO54_DOWN); + omap_cfg_reg(G25_34XX_GPIO86_OUT); + omap_cfg_reg(H19_34XX_GPIO164_OUT); + + if (gpmc_cs_request(SMC91X_CS, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); + return; + } + + rx51_smc91x_resources[0].start = cs_mem_base + 0x300; + rx51_smc91x_resources[0].end = cs_mem_base + 0x30f; + + smc91x_init_gpmc(SMC91X_CS); + + if (gpio_request(SMC91X_GPIO_IRQ, "SMC91X irq") < 0) + goto free1; + + gpio_direction_input(SMC91X_GPIO_IRQ); + rx51_smc91x_resources[1].start = gpio_to_irq(SMC91X_GPIO_IRQ); + + ret = gpio_request(SMC91X_GPIO_PWRDWN, "SMC91X powerdown"); + if (ret) + goto free2; + gpio_direction_output(SMC91X_GPIO_PWRDWN, 0); + + ret = gpio_request(SMC91X_GPIO_RESET, "SMC91X reset"); + if (ret) + goto free3; + gpio_direction_output(SMC91X_GPIO_RESET, 0); + gpio_set_value(SMC91X_GPIO_RESET, 1); + msleep(100); + gpio_set_value(SMC91X_GPIO_RESET, 0); + + return; + +free3: + gpio_free(SMC91X_GPIO_PWRDWN); +free2: + gpio_free(SMC91X_GPIO_IRQ); +free1: + gpmc_cs_free(SMC91X_CS); + + printk(KERN_ERR "Could not initialize smc91x\n"); +} + static struct twl4030_madc_platform_data rx51_madc_data = { .irq_line = 1, }; @@ -150,7 +259,7 @@ static struct regulator_init_data rx51_vaux2 = { }; /* VAUX3 - adds more power to VIO_18 rail */ -static struct regulator_init_data rx51_vaux3_cam = { +static struct regulator_init_data rx51_vaux3 = { .constraints = { .name = "VCAM_DIG_18", .min_uV = 1800000, @@ -163,22 +272,6 @@ static struct regulator_init_data rx51_vaux3_cam = { }, }; -static struct regulator_init_data rx51_vaux3_mmc = { - .constraints = { - .name = "VMMC2_30", - .min_uV = 2800000, - .max_uV = 3000000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &rx51_vmmc2_supply, -}; - static struct regulator_init_data rx51_vaux4 = { .constraints = { .name = "VCAM_ANA_28", @@ -289,8 +382,10 @@ static struct twl4030_platform_data rx51_twldata = { .vaux1 = &rx51_vaux1, .vaux2 = &rx51_vaux2, + .vaux3 = &rx51_vaux3, .vaux4 = &rx51_vaux4, .vmmc1 = &rx51_vmmc1, + .vmmc2 = &rx51_vmmc2, .vsim = &rx51_vsim, .vdac = &rx51_vdac, }; @@ -306,13 +401,6 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { static int __init rx51_i2c_init(void) { - if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) || - system_rev >= SYSTEM_REV_B_USES_VAUX3) - rx51_twldata.vaux3 = &rx51_vaux3_mmc; - else { - rx51_twldata.vaux3 = &rx51_vaux3_cam; - rx51_twldata.vmmc2 = &rx51_vmmc2; - } omap_register_i2c_bus(1, 2600, rx51_peripherals_i2c_board_info_1, ARRAY_SIZE(rx51_peripherals_i2c_board_info_1)); omap_register_i2c_bus(2, 100, NULL, 0); @@ -320,94 +408,12 @@ static int __init rx51_i2c_init(void) return 0; } -#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ - defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) - -static struct mtd_partition onenand_partitions[] = { - { - .name = "bootloader", - .offset = 0, - .size = 0x20000, - .mask_flags = MTD_WRITEABLE, /* Force read-only */ - }, - { - .name = "config", - .offset = MTDPART_OFS_APPEND, - .size = 0x60000, - }, - { - .name = "log", - .offset = MTDPART_OFS_APPEND, - .size = 0x40000, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 0x200000, - }, - { - .name = "initfs", - .offset = MTDPART_OFS_APPEND, - .size = 0x200000, - }, - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct omap_onenand_platform_data board_onenand_data = { - .cs = 0, - .gpio_irq = 65, - .parts = onenand_partitions, - .nr_parts = ARRAY_SIZE(onenand_partitions), -}; - -static void __init board_onenand_init(void) -{ - gpmc_onenand_init(&board_onenand_data); -} - -#else - -static inline void board_onenand_init(void) -{ -} - -#endif - -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) - -static struct omap_smc91x_platform_data board_smc91x_data = { - .cs = 1, - .gpio_irq = 54, - .gpio_pwrdwn = 86, - .gpio_reset = 164, - .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_HIGHLEVEL, -}; - -static void __init board_smc91x_init(void) -{ - omap_cfg_reg(U8_34XX_GPIO54_DOWN); - omap_cfg_reg(G25_34XX_GPIO86_OUT); - omap_cfg_reg(H19_34XX_GPIO164_OUT); - - gpmc_smc91x_init(&board_smc91x_data); -} - -#else - -static inline void board_smc91x_init(void) -{ -} - -#endif void __init rx51_peripherals_init(void) { + platform_add_devices(rx51_peripherals_devices, + ARRAY_SIZE(rx51_peripherals_devices)); rx51_i2c_init(); - board_onenand_init(); - board_smc91x_init(); + rx51_init_smc91x(); } diff --git a/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c b/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c deleted file mode 100644 index bac5c4321ff7..000000000000 --- a/trunk/arch/arm/mach-omap2/board-zoom-debugboard.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Inc. - * Mikkel Christensen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include - -#define ZOOM2_SMSC911X_CS 7 -#define ZOOM2_SMSC911X_GPIO 158 -#define ZOOM2_QUADUART_CS 3 -#define ZOOM2_QUADUART_GPIO 102 -#define QUART_CLK 1843200 -#define DEBUG_BASE 0x08000000 -#define ZOOM2_ETHR_START DEBUG_BASE - -static struct resource zoom2_smsc911x_resources[] = { - [0] = { - .start = ZOOM2_ETHR_START, - .end = ZOOM2_ETHR_START + SZ_4K, - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config zoom2_smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .flags = SMSC911X_USE_32BIT, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device zoom2_smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(zoom2_smsc911x_resources), - .resource = zoom2_smsc911x_resources, - .dev = { - .platform_data = &zoom2_smsc911x_config, - }, -}; - -static inline void __init zoom2_init_smsc911x(void) -{ - int eth_cs; - unsigned long cs_mem_base; - int eth_gpio = 0; - - eth_cs = ZOOM2_SMSC911X_CS; - - if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { - printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n"); - return; - } - - zoom2_smsc911x_resources[0].start = cs_mem_base + 0x0; - zoom2_smsc911x_resources[0].end = cs_mem_base + 0xff; - - eth_gpio = ZOOM2_SMSC911X_GPIO; - - zoom2_smsc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio); - - if (gpio_request(eth_gpio, "smsc911x irq") < 0) { - printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", - eth_gpio); - return; - } - gpio_direction_input(eth_gpio); -} - -static struct plat_serial8250_port serial_platform_data[] = { - { - .mapbase = 0x10000000, - .irq = OMAP_GPIO_IRQ(102), - .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ, - .iotype = UPIO_MEM, - .regshift = 1, - .uartclk = QUART_CLK, - }, { - .flags = 0 - } -}; - -static struct platform_device zoom2_debugboard_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -static inline void __init zoom2_init_quaduart(void) -{ - int quart_cs; - unsigned long cs_mem_base; - int quart_gpio = 0; - - quart_cs = ZOOM2_QUADUART_CS; - - if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) { - printk(KERN_ERR "Failed to request GPMC mem" - "for Quad UART(TL16CP754C)\n"); - return; - } - - quart_gpio = ZOOM2_QUADUART_GPIO; - - if (gpio_request(quart_gpio, "TL16CP754C GPIO") < 0) { - printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n", - quart_gpio); - return; - } - gpio_direction_input(quart_gpio); -} - -static inline int omap_zoom2_debugboard_detect(void) -{ - int debug_board_detect = 0; - - debug_board_detect = ZOOM2_SMSC911X_GPIO; - - if (gpio_request(debug_board_detect, "Zoom2 debug board detect") < 0) { - printk(KERN_ERR "Failed to request GPIO%d for Zoom2 debug" - "board detect\n", debug_board_detect); - return 0; - } - gpio_direction_input(debug_board_detect); - - if (!gpio_get_value(debug_board_detect)) { - gpio_free(debug_board_detect); - return 0; - } - return 1; -} - -static struct platform_device *zoom2_devices[] __initdata = { - &zoom2_smsc911x_device, - &zoom2_debugboard_serial_device, -}; - -int __init omap_zoom2_debugboard_init(void) -{ - if (!omap_zoom2_debugboard_detect()) - return 0; - - zoom2_init_smsc911x(); - zoom2_init_quaduart(); - return platform_add_devices(zoom2_devices, ARRAY_SIZE(zoom2_devices)); -} diff --git a/trunk/arch/arm/mach-omap2/board-zoom2.c b/trunk/arch/arm/mach-omap2/board-zoom2.c deleted file mode 100644 index bcc0f7632dea..000000000000 --- a/trunk/arch/arm/mach-omap2/board-zoom2.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Inc. - * Mikkel Christensen - * - * Modified from mach-omap2/board-ldp.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "mmc-twl4030.h" - -static void __init omap_zoom2_init_irq(void) -{ - omap2_init_common_hw(NULL); - omap_init_irq(); - omap_gpio_init(); -} - -static struct omap_uart_config zoom2_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - -static struct omap_board_config_kernel zoom2_config[] __initdata = { - { OMAP_TAG_UART, &zoom2_uart_config }, -}; - -static struct twl4030_gpio_platform_data zoom2_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, -}; - -static struct twl4030_platform_data zoom2_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, - - /* platform_data for children goes here */ - .gpio = &zoom2_gpio_data, -}; - -static struct i2c_board_info __initdata zoom2_i2c_boardinfo[] = { - { - I2C_BOARD_INFO("twl4030", 0x48), - .flags = I2C_CLIENT_WAKE, - .irq = INT_34XX_SYS_NIRQ, - .platform_data = &zoom2_twldata, - }, -}; - -static int __init omap_i2c_init(void) -{ - omap_register_i2c_bus(1, 2600, zoom2_i2c_boardinfo, - ARRAY_SIZE(zoom2_i2c_boardinfo)); - omap_register_i2c_bus(2, 400, NULL, 0); - omap_register_i2c_bus(3, 400, NULL, 0); - return 0; -} - -static struct twl4030_hsmmc_info mmc[] __initdata = { - { - .mmc = 1, - .wires = 4, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - }, - {} /* Terminator */ -}; - -extern int __init omap_zoom2_debugboard_init(void); - -static void __init omap_zoom2_init(void) -{ - omap_i2c_init(); - omap_board_config = zoom2_config; - omap_board_config_size = ARRAY_SIZE(zoom2_config); - omap_serial_init(); - omap_zoom2_debugboard_init(); - twl4030_mmc_init(mmc); - usb_musb_init(); -} - -static void __init omap_zoom2_map_io(void) -{ - omap2_set_globals_343x(); - omap2_map_common_io(); -} - -MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") - .phys_io = 0x48000000, - .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_zoom2_map_io, - .init_irq = omap_zoom2_init_irq, - .init_machine = omap_zoom2_init, - .timer = &omap_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/clock.c b/trunk/arch/arm/mach-omap2/clock.c index ba528f85749c..4247a1534411 100644 --- a/trunk/arch/arm/mach-omap2/clock.c +++ b/trunk/arch/arm/mach-omap2/clock.c @@ -91,9 +91,9 @@ static void _omap2xxx_clk_commit(struct clk *clk) return; prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, - OMAP2_PRCM_CLKCFG_CTRL_OFFSET); + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); /* OCP barrier */ - prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); + prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); } /* @@ -547,8 +547,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, const struct clksel_rate *clkr; u32 last_div = 0; - pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", - clk->name, target_rate); + printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", + clk->name, target_rate); *new_div = 1; @@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, /* Sanity check */ if (clkr->div <= last_div) - pr_err("clock: clksel_rate table not sorted " + printk(KERN_ERR "clock: clksel_rate table not sorted " "for clock %s", clk->name); last_div = clkr->div; @@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, } if (!clkr->div) { - pr_err("clock: Could not find divisor for target " + printk(KERN_ERR "clock: Could not find divisor for target " "rate %ld for clock %s parent %s\n", target_rate, clk->name, clk->parent->name); return ~0; @@ -582,8 +582,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, *new_div = clkr->div; - pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, - (clk->parent->rate / clkr->div)); + printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, + (clk->parent->rate / clkr->div)); return (clk->parent->rate / clkr->div); } @@ -1035,7 +1035,7 @@ void omap2_clk_disable_unused(struct clk *clk) if ((regval32 & (1 << clk->enable_bit)) == v) return; - printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); + printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); if (cpu_is_omap34xx()) { omap2_clk_enable(clk); omap2_clk_disable(clk); diff --git a/trunk/arch/arm/mach-omap2/clock24xx.c b/trunk/arch/arm/mach-omap2/clock24xx.c index 44de0271fc2f..e4cef333e291 100644 --- a/trunk/arch/arm/mach-omap2/clock24xx.c +++ b/trunk/arch/arm/mach-omap2/clock24xx.c @@ -233,8 +233,6 @@ static struct prcm_config *curr_prcm_set; static struct clk *vclk; static struct clk *sclk; -static void __iomem *prcm_clksrc_ctrl; - /*------------------------------------------------------------------------- * Omap24xx specific clock functions *-------------------------------------------------------------------------*/ @@ -271,9 +269,10 @@ static int omap2_enable_osc_ck(struct clk *clk) { u32 pcc; - pcc = __raw_readl(prcm_clksrc_ctrl); + pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); - __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); + __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, + OMAP24XX_PRCM_CLKSRC_CTRL); return 0; } @@ -282,9 +281,10 @@ static void omap2_disable_osc_ck(struct clk *clk) { u32 pcc; - pcc = __raw_readl(prcm_clksrc_ctrl); + pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); - __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); + __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, + OMAP24XX_PRCM_CLKSRC_CTRL); } static const struct clkops clkops_oscck = { @@ -654,7 +654,7 @@ static u32 omap2_get_sysclkdiv(void) { u32 div; - div = __raw_readl(prcm_clksrc_ctrl); + div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); div &= OMAP_SYSCLKDIV_MASK; div >>= OMAP_SYSCLKDIV_SHIFT; @@ -714,18 +714,15 @@ int __init omap2_clk_init(void) struct omap_clk *c; u32 clkrate; - if (cpu_is_omap242x()) { - prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; + if (cpu_is_omap242x()) cpu_mask = RATE_IN_242X; - } else if (cpu_is_omap2430()) { - prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; + else if (cpu_is_omap2430()) cpu_mask = RATE_IN_243X; - } clk_init(&omap2_clk_functions); for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) - clk_preinit(c->lk.clk); + clk_init_one(c->lk.clk); osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); propagate_rate(&osc_ck); diff --git a/trunk/arch/arm/mach-omap2/clock24xx.h b/trunk/arch/arm/mach-omap2/clock24xx.h index 458f00cdcbea..88c5acb40fcf 100644 --- a/trunk/arch/arm/mach-omap2/clock24xx.h +++ b/trunk/arch/arm/mach-omap2/clock24xx.h @@ -24,17 +24,6 @@ #include "cm-regbits-24xx.h" #include "sdrc.h" -/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ -#ifdef CONFIG_ARCH_OMAP2420 -#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR -#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL -#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL -#else -#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR -#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL -#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL -#endif - static unsigned long omap2_table_mpu_recalc(struct clk *clk); static int omap2_select_table_rate(struct clk *clk, unsigned long rate); static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); diff --git a/trunk/arch/arm/mach-omap2/clock34xx.c b/trunk/arch/arm/mach-omap2/clock34xx.c index 9e43fe5209d3..ba05aa42bd8e 100644 --- a/trunk/arch/arm/mach-omap2/clock34xx.c +++ b/trunk/arch/arm/mach-omap2/clock34xx.c @@ -129,9 +129,6 @@ static struct omap_clk omap34xx_clks[] = { CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), - CLK(NULL, "modem_fck", &modem_fck, CK_343X), - CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), - CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), @@ -284,8 +281,6 @@ static struct omap_clk omap34xx_clks[] = { #define MAX_DPLL_WAIT_TRIES 1000000 -#define MIN_SDRC_DLL_LOCK_FREQ 83000000 - /** * omap3_dpll_recalc - recalculate DPLL rate * @clk: DPLL struct clk @@ -708,7 +703,6 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) { u32 new_div = 0; - u32 unlock_dll = 0; unsigned long validrate, sdrcrate; struct omap_sdrc_params *sp; @@ -735,22 +729,17 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (!sp) return -EINVAL; - if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { - pr_debug("clock: will unlock SDRC DLL\n"); - unlock_dll = 1; - } - - pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, - validrate); - pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", - sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); + pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, + validrate); + pr_info("clock: SDRC timing params used: %08x %08x %08x\n", + sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); /* REVISIT: SRAM code doesn't support other M2 divisors yet */ WARN_ON(new_div != 1 && new_div != 2); /* REVISIT: Add SDRC_MR changing to this code also */ omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, - sp->actim_ctrlb, new_div, unlock_dll); + sp->actim_ctrlb, new_div); return 0; } @@ -967,7 +956,7 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) - clk_preinit(c->lk.clk); + clk_init_one(c->lk.clk); for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) if (c->cpu & cpu_clkflg) { diff --git a/trunk/arch/arm/mach-omap2/clock34xx.h b/trunk/arch/arm/mach-omap2/clock34xx.h index e433aec4efdd..017a30e9aa1d 100644 --- a/trunk/arch/arm/mach-omap2/clock34xx.h +++ b/trunk/arch/arm/mach-omap2/clock34xx.h @@ -27,8 +27,6 @@ #include "prm.h" #include "prm-regbits-34xx.h" -#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR - static unsigned long omap3_dpll_recalc(struct clk *clk); static unsigned long omap3_clkoutx2_recalc(struct clk *clk); static void omap3_dpll_allow_idle(struct clk *clk); @@ -1230,37 +1228,6 @@ static struct clk d2d_26m_fck = { .recalc = &followparent_recalc, }; -static struct clk modem_fck = { - .name = "modem_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MODEM_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk sad2d_ick = { - .name = "sad2d_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SAD2D_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mad2d_ick = { - .name = "mad2d_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP3430_EN_MAD2D_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - static const struct clksel omap343x_gpt_clksel[] = { { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, { .parent = &sys_ck, .rates = gpt_sys_rates }, @@ -1978,6 +1945,8 @@ static struct clk usb_l4_ick = { .recalc = &omap2_clksel_recalc, }; +/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ + /* SECURITY_L4_ICK2 based clocks */ static struct clk security_l4_ick2 = { diff --git a/trunk/arch/arm/mach-omap2/clockdomains.h b/trunk/arch/arm/mach-omap2/clockdomains.h index fe319ae4ca0a..281d5da19188 100644 --- a/trunk/arch/arm/mach-omap2/clockdomains.h +++ b/trunk/arch/arm/mach-omap2/clockdomains.h @@ -195,7 +195,7 @@ static struct clockdomain sgx_clkdm = { static struct clockdomain d2d_clkdm = { .name = "d2d_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_HWSUP, .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; diff --git a/trunk/arch/arm/mach-omap2/cm-regbits-34xx.h b/trunk/arch/arm/mach-omap2/cm-regbits-34xx.h index 6923deb98a28..6f3f5a36aae6 100644 --- a/trunk/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/trunk/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -145,8 +145,6 @@ #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) /* CM_FCLKEN1_CORE specific bits */ -#define OMAP3430_EN_MODEM (1 << 31) -#define OMAP3430_EN_MODEM_SHIFT 31 /* CM_ICLKEN1_CORE specific bits */ #define OMAP3430_EN_ICR (1 << 29) @@ -163,8 +161,6 @@ #define OMAP3430_EN_MAILBOXES_SHIFT 7 #define OMAP3430_EN_OMAPCTRL (1 << 6) #define OMAP3430_EN_OMAPCTRL_SHIFT 6 -#define OMAP3430_EN_SAD2D (1 << 3) -#define OMAP3430_EN_SAD2D_SHIFT 3 #define OMAP3430_EN_SDRC (1 << 1) #define OMAP3430_EN_SDRC_SHIFT 1 @@ -180,10 +176,6 @@ #define OMAP3430_EN_DES1 (1 << 0) #define OMAP3430_EN_DES1_SHIFT 0 -/* CM_ICLKEN3_CORE */ -#define OMAP3430_EN_MAD2D_SHIFT 3 -#define OMAP3430_EN_MAD2D (1 << 3) - /* CM_FCLKEN3_CORE specific bits */ #define OMAP3430ES2_EN_TS_SHIFT 1 #define OMAP3430ES2_EN_TS_MASK (1 << 1) @@ -239,8 +231,6 @@ #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) /* CM_AUTOIDLE1_CORE */ -#define OMAP3430_AUTO_MODEM (1 << 31) -#define OMAP3430_AUTO_MODEM_SHIFT 31 #define OMAP3430ES2_AUTO_MMC3 (1 << 30) #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 #define OMAP3430ES2_AUTO_ICR (1 << 29) @@ -297,8 +287,6 @@ #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 #define OMAP3430ES1_AUTO_D2D (1 << 3) #define OMAP3430ES1_AUTO_D2D_SHIFT 3 -#define OMAP3430_AUTO_SAD2D (1 << 3) -#define OMAP3430_AUTO_SAD2D_SHIFT 3 #define OMAP3430_AUTO_SSI (1 << 0) #define OMAP3430_AUTO_SSI_SHIFT 0 @@ -320,8 +308,6 @@ #define OMAP3430ES2_AUTO_USBTLL (1 << 2) #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) -#define OMAP3430_AUTO_MAD2D_SHIFT 3 -#define OMAP3430_AUTO_MAD2D (1 << 3) /* CM_CLKSEL_CORE */ #define OMAP3430_CLKSEL_SSI_SHIFT 8 diff --git a/trunk/arch/arm/mach-omap2/cm.h b/trunk/arch/arm/mach-omap2/cm.h index 1d3c93bf86d3..65fdf78c91e1 100644 --- a/trunk/arch/arm/mach-omap2/cm.h +++ b/trunk/arch/arm/mach-omap2/cm.h @@ -16,12 +16,17 @@ #include "prcm-common.h" +#ifndef __ASSEMBLER__ +#define OMAP_CM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) +#else #define OMAP2420_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) #define OMAP2430_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) #define OMAP34XX_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) +#endif /* * Architecture-specific global CM registers @@ -33,7 +38,6 @@ #define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) #define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) -#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) /* diff --git a/trunk/arch/arm/mach-omap2/gpmc-onenand.c b/trunk/arch/arm/mach-omap2/gpmc-onenand.c deleted file mode 100644 index 2fd22f9c5f0e..000000000000 --- a/trunk/arch/arm/mach-omap2/gpmc-onenand.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/gpmc-onenand.c - * - * Copyright (C) 2006 - 2009 Nokia Corporation - * Contacts: Juha Yrjola - * Tony Lindgren - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include - -#include -#include -#include - -static struct omap_onenand_platform_data *gpmc_onenand_data; - -static struct platform_device gpmc_onenand_device = { - .name = "omap2-onenand", - .id = -1, -}; - -static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) -{ - struct gpmc_timings t; - - const int t_cer = 15; - const int t_avdp = 12; - const int t_aavdh = 7; - const int t_ce = 76; - const int t_aa = 76; - const int t_oe = 20; - const int t_cez = 20; /* max of t_cez, t_oez */ - const int t_ds = 30; - const int t_wpl = 40; - const int t_wph = 30; - - memset(&t, 0, sizeof(t)); - t.sync_clk = 0; - t.cs_on = 0; - t.adv_on = 0; - - /* Read */ - t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer)); - t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh); - t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa); - t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce)); - t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe)); - t.oe_off = t.access + gpmc_round_ns_to_ticks(1); - t.cs_rd_off = t.oe_off; - t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez); - - /* Write */ - t.adv_wr_off = t.adv_rd_off; - t.we_on = t.oe_on; - if (cpu_is_omap34xx()) { - t.wr_data_mux_bus = t.we_on; - t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds); - } - t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl); - t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph); - t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez); - - /* Configure GPMC for asynchronous read */ - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, - GPMC_CONFIG1_DEVICESIZE_16 | - GPMC_CONFIG1_MUXADDDATA); - - return gpmc_cs_set_timings(cs, &t); -} - -static void set_onenand_cfg(void __iomem *onenand_base, int latency, - int sync_read, int sync_write, int hf) -{ - u32 reg; - - reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); - reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9)); - reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) | - ONENAND_SYS_CFG1_BL_16; - if (sync_read) - reg |= ONENAND_SYS_CFG1_SYNC_READ; - else - reg &= ~ONENAND_SYS_CFG1_SYNC_READ; - if (sync_write) - reg |= ONENAND_SYS_CFG1_SYNC_WRITE; - else - reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE; - if (hf) - reg |= ONENAND_SYS_CFG1_HF; - else - reg &= ~ONENAND_SYS_CFG1_HF; - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); -} - -static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, - void __iomem *onenand_base, - int freq) -{ - struct gpmc_timings t; - const int t_cer = 15; - const int t_avdp = 12; - const int t_cez = 20; /* max of t_cez, t_oez */ - const int t_ds = 30; - const int t_wpl = 40; - const int t_wph = 30; - int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; - int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; - int first_time = 0, hf = 0, sync_read = 0, sync_write = 0; - int err, ticks_cez; - int cs = cfg->cs; - u32 reg; - - if (cfg->flags & ONENAND_SYNC_READ) { - sync_read = 1; - } else if (cfg->flags & ONENAND_SYNC_READWRITE) { - sync_read = 1; - sync_write = 1; - } - - if (!freq) { - /* Very first call freq is not known */ - err = omap2_onenand_set_async_mode(cs, onenand_base); - if (err) - return err; - reg = readw(onenand_base + ONENAND_REG_VERSION_ID); - switch ((reg >> 4) & 0xf) { - case 0: - freq = 40; - break; - case 1: - freq = 54; - break; - case 2: - freq = 66; - break; - case 3: - freq = 83; - break; - case 4: - freq = 104; - break; - default: - freq = 54; - break; - } - first_time = 1; - } - - switch (freq) { - case 83: - min_gpmc_clk_period = 12; /* 83 MHz */ - t_ces = 5; - t_avds = 4; - t_avdh = 2; - t_ach = 6; - t_aavdh = 6; - t_rdyo = 9; - break; - case 66: - min_gpmc_clk_period = 15; /* 66 MHz */ - t_ces = 6; - t_avds = 5; - t_avdh = 2; - t_ach = 6; - t_aavdh = 6; - t_rdyo = 11; - break; - default: - min_gpmc_clk_period = 18; /* 54 MHz */ - t_ces = 7; - t_avds = 7; - t_avdh = 7; - t_ach = 9; - t_aavdh = 7; - t_rdyo = 15; - sync_write = 0; - break; - } - - tick_ns = gpmc_ticks_to_ns(1); - div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period); - gpmc_clk_ns = gpmc_ticks_to_ns(div); - if (gpmc_clk_ns < 15) /* >66Mhz */ - hf = 1; - if (hf) - latency = 6; - else if (gpmc_clk_ns >= 25) /* 40 MHz*/ - latency = 3; - else - latency = 4; - - if (first_time) - set_onenand_cfg(onenand_base, latency, - sync_read, sync_write, hf); - - if (div == 1) { - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); - reg |= (1 << 7); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg); - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3); - reg |= (1 << 7); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg); - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4); - reg |= (1 << 7); - reg |= (1 << 23); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg); - } else { - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); - reg &= ~(1 << 7); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg); - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3); - reg &= ~(1 << 7); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg); - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4); - reg &= ~(1 << 7); - reg &= ~(1 << 23); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg); - } - - /* Set synchronous read timings */ - memset(&t, 0, sizeof(t)); - t.sync_clk = min_gpmc_clk_period; - t.cs_on = 0; - t.adv_on = 0; - fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds)); - fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns); - t.page_burst_access = gpmc_clk_ns; - - /* Read */ - t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh)); - t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach)); - t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div); - t.oe_off = t.access + gpmc_round_ns_to_ticks(1); - t.cs_rd_off = t.oe_off; - ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div; - t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div + - ticks_cez); - - /* Write */ - if (sync_write) { - t.adv_wr_off = t.adv_rd_off; - t.we_on = 0; - t.we_off = t.cs_rd_off; - t.cs_wr_off = t.cs_rd_off; - t.wr_cycle = t.rd_cycle; - if (cpu_is_omap34xx()) { - t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset + - gpmc_ns_to_ticks(min_gpmc_clk_period + - t_rdyo)); - t.wr_access = t.access; - } - } else { - t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int, - t_avdp, t_cer)); - t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh); - t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl); - t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph); - t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez); - if (cpu_is_omap34xx()) { - t.wr_data_mux_bus = t.we_on; - t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds); - } - } - - /* Configure GPMC for synchronous read */ - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, - GPMC_CONFIG1_WRAPBURST_SUPP | - GPMC_CONFIG1_READMULTIPLE_SUPP | - (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) | - (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) | - (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) | - GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) | - GPMC_CONFIG1_PAGE_LEN(2) | - (cpu_is_omap34xx() ? 0 : - (GPMC_CONFIG1_WAIT_READ_MON | - GPMC_CONFIG1_WAIT_PIN_SEL(0))) | - GPMC_CONFIG1_DEVICESIZE_16 | - GPMC_CONFIG1_DEVICETYPE_NOR | - GPMC_CONFIG1_MUXADDDATA); - - err = gpmc_cs_set_timings(cs, &t); - if (err) - return err; - - set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf); - - return 0; -} - -static int gpmc_onenand_setup(void __iomem *onenand_base, int freq) -{ - struct device *dev = &gpmc_onenand_device.dev; - - /* Set sync timings in GPMC */ - if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, - freq) < 0) { - dev_err(dev, "Unable to set synchronous mode\n"); - return -EINVAL; - } - - return 0; -} - -void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) -{ - gpmc_onenand_data = _onenand_data; - gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; - gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; - - if (cpu_is_omap24xx() && - (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) { - printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n"); - gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE; - gpmc_onenand_data->flags |= ONENAND_SYNC_READ; - } - - if (platform_device_register(&gpmc_onenand_device) < 0) { - printk(KERN_ERR "Unable to register OneNAND device\n"); - return; - } -} diff --git a/trunk/arch/arm/mach-omap2/gpmc-smc91x.c b/trunk/arch/arm/mach-omap2/gpmc-smc91x.c deleted file mode 100644 index df99d31d8b64..000000000000 --- a/trunk/arch/arm/mach-omap2/gpmc-smc91x.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/gpmc-smc91x.c - * - * Copyright (C) 2009 Nokia Corporation - * Contact: Tony Lindgren - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static struct omap_smc91x_platform_data *gpmc_cfg; - -static struct resource gpmc_smc91x_resources[] = { - [0] = { - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct smc91x_platdata gpmc_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0, -}; - -static struct platform_device gpmc_smc91x_device = { - .name = "smc91x", - .id = -1, - .num_resources = ARRAY_SIZE(gpmc_smc91x_resources), - .resource = gpmc_smc91x_resources, - .dev = { - .platform_data = &gpmc_smc91x_info, - }, -}; - -/* - * Set the gpmc timings for smc91c96. The timings are taken - * from the data sheet available at: - * http://www.smsc.com/main/catalog/lan91c96.html - * REVISIT: Level shifters can add at least to the access latency. - */ -static int smc91c96_gpmc_retime(void) -{ - struct gpmc_timings t; - const int t3 = 10; /* Figure 12.2 read and 12.4 write */ - const int t4_r = 20; /* Figure 12.2 read */ - const int t4_w = 5; /* Figure 12.4 write */ - const int t5 = 25; /* Figure 12.2 read */ - const int t6 = 15; /* Figure 12.2 read */ - const int t7 = 5; /* Figure 12.4 write */ - const int t8 = 5; /* Figure 12.4 write */ - const int t20 = 185; /* Figure 12.2 read and 12.4 write */ - u32 l; - - memset(&t, 0, sizeof(t)); - - /* Read timings */ - t.cs_on = 0; - t.adv_on = t.cs_on; - t.oe_on = t.adv_on + t3; - t.access = t.oe_on + t5; - t.oe_off = t.access; - t.adv_rd_off = t.oe_off + max(t4_r, t6); - t.cs_rd_off = t.oe_off; - t.rd_cycle = t20 - t.oe_on; - - /* Write timings */ - t.we_on = t.adv_on + t3; - - if (cpu_is_omap34xx() && (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)) { - t.wr_data_mux_bus = t.we_on; - t.we_off = t.wr_data_mux_bus + t7; - } else - t.we_off = t.we_on + t7; - if (cpu_is_omap34xx()) - t.wr_access = t.we_off; - t.adv_wr_off = t.we_off + max(t4_w, t8); - t.cs_wr_off = t.we_off + t4_w; - t.wr_cycle = t20 - t.we_on; - - l = GPMC_CONFIG1_DEVICESIZE_16; - if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA) - l |= GPMC_CONFIG1_MUXADDDATA; - if (gpmc_cfg->flags & GPMC_READ_MON) - l |= GPMC_CONFIG1_WAIT_READ_MON; - if (gpmc_cfg->flags & GPMC_WRITE_MON) - l |= GPMC_CONFIG1_WAIT_WRITE_MON; - if (gpmc_cfg->wait_pin) - l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin); - gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l); - - /* - * FIXME: Calculate the address and data bus muxed timings. - * Note that at least adv_rd_off needs to be changed according - * to omap3430 TRM Figure 11-11. Are the sdp boards using the - * FPGA in between smc91x and omap as the timings are different - * from above? - */ - if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA) - return 0; - - return gpmc_cs_set_timings(gpmc_cfg->cs, &t); -} - -/* - * Initialize smc91x device connected to the GPMC. Note that we - * assume that pin multiplexing is done in the board-*.c file, - * or in the bootloader. - */ -void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data) -{ - unsigned long cs_mem_base; - int ret; - - gpmc_cfg = board_data; - - if (gpmc_cfg->flags & GPMC_TIMINGS_SMC91C96) - gpmc_cfg->retime = smc91c96_gpmc_retime; - - if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) { - printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); - return; - } - - gpmc_smc91x_resources[0].start = cs_mem_base + 0x300; - gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f; - gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK); - - if (gpmc_cfg->retime) { - ret = gpmc_cfg->retime(); - if (ret != 0) - goto free1; - } - - if (gpio_request(gpmc_cfg->gpio_irq, "SMC91X irq") < 0) - goto free1; - - gpio_direction_input(gpmc_cfg->gpio_irq); - gpmc_smc91x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq); - - if (gpmc_cfg->gpio_pwrdwn) { - ret = gpio_request(gpmc_cfg->gpio_pwrdwn, "SMC91X powerdown"); - if (ret) - goto free2; - gpio_direction_output(gpmc_cfg->gpio_pwrdwn, 0); - } - - if (gpmc_cfg->gpio_reset) { - ret = gpio_request(gpmc_cfg->gpio_reset, "SMC91X reset"); - if (ret) - goto free3; - - gpio_direction_output(gpmc_cfg->gpio_reset, 0); - gpio_set_value(gpmc_cfg->gpio_reset, 1); - msleep(100); - gpio_set_value(gpmc_cfg->gpio_reset, 0); - } - - if (platform_device_register(&gpmc_smc91x_device) < 0) { - printk(KERN_ERR "Unable to register smc91x device\n"); - gpio_free(gpmc_cfg->gpio_reset); - goto free3; - } - - return; - -free3: - if (gpmc_cfg->gpio_pwrdwn) - gpio_free(gpmc_cfg->gpio_pwrdwn); -free2: - gpio_free(gpmc_cfg->gpio_irq); -free1: - gpmc_cs_free(gpmc_cfg->cs); - - printk(KERN_ERR "Could not initialize smc91x\n"); -} diff --git a/trunk/arch/arm/mach-omap2/gpmc.c b/trunk/arch/arm/mach-omap2/gpmc.c index f91934b2b092..2249049c1d5a 100644 --- a/trunk/arch/arm/mach-omap2/gpmc.c +++ b/trunk/arch/arm/mach-omap2/gpmc.c @@ -5,9 +5,6 @@ * * Author: Juha Yrjola * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -427,9 +424,6 @@ void __init gpmc_init(void) } else if (cpu_is_omap34xx()) { ck = "gpmc_fck"; l = OMAP34XX_GPMC_BASE; - } else if (cpu_is_omap44xx()) { - ck = "gpmc_fck"; - l = OMAP44XX_GPMC_BASE; } gpmc_l3_clk = clk_get(NULL, ck); diff --git a/trunk/arch/arm/mach-omap2/id.c b/trunk/arch/arm/mach-omap2/id.c index 458990e20c60..34b5914e0f8b 100644 --- a/trunk/arch/arm/mach-omap2/id.c +++ b/trunk/arch/arm/mach-omap2/id.c @@ -6,9 +6,6 @@ * Copyright (C) 2005 Nokia Corporation * Written by Tony Lindgren * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -203,10 +200,7 @@ void __init omap2_check_revision(void) omap24xx_check_revision(); else if (cpu_is_omap34xx()) omap34xx_check_revision(); - else if (cpu_is_omap44xx()) { - printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n"); - return; - } else + else pr_err("OMAP revision unknown, please fix!\n"); /* diff --git a/trunk/arch/arm/mach-omap2/io.c b/trunk/arch/arm/mach-omap2/io.c index 32afd9448216..916fcd3a2328 100644 --- a/trunk/arch/arm/mach-omap2/io.c +++ b/trunk/arch/arm/mach-omap2/io.c @@ -4,14 +4,12 @@ * OMAP2 I/O mapping code * * Copyright (C) 2005 Nokia Corporation - * Copyright (C) 2007-2009 Texas Instruments + * Copyright (C) 2007 Texas Instruments * * Author: * Juha Yrjola * Syed Khasim * - * Added OMAP4 support - Santosh Shilimkar - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -32,7 +30,6 @@ #include #include -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */ #include "clock.h" #include @@ -41,7 +38,7 @@ #include #include "clockdomains.h" -#endif + /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. @@ -169,46 +166,6 @@ static struct map_desc omap34xx_io_desc[] __initdata = { }, }; #endif -#ifdef CONFIG_ARCH_OMAP4 -static struct map_desc omap44xx_io_desc[] __initdata = { - { - .virtual = L3_44XX_VIRT, - .pfn = __phys_to_pfn(L3_44XX_PHYS), - .length = L3_44XX_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = L4_44XX_VIRT, - .pfn = __phys_to_pfn(L4_44XX_PHYS), - .length = L4_44XX_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = L4_WK_44XX_VIRT, - .pfn = __phys_to_pfn(L4_WK_44XX_PHYS), - .length = L4_WK_44XX_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = OMAP44XX_GPMC_VIRT, - .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), - .length = OMAP44XX_GPMC_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = L4_PER_44XX_VIRT, - .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), - .length = L4_PER_44XX_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = L4_EMU_44XX_VIRT, - .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS), - .length = L4_EMU_44XX_SIZE, - .type = MT_DEVICE, - }, -}; -#endif void __init omap2_map_common_io(void) { @@ -226,9 +183,6 @@ void __init omap2_map_common_io(void) iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); #endif -#if defined(CONFIG_ARCH_OMAP4) - iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); -#endif /* Normally devicemaps_init() would flush caches and tlb after * mdesc->map_io(), but we must also do it here because of the CPU * revision check below. @@ -244,11 +198,9 @@ void __init omap2_map_common_io(void) void __init omap2_init_common_hw(struct omap_sdrc_params *sp) { omap2_mux_init(); -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); omap2_clk_init(); omap2_sdrc_init(sp); -#endif gpmc_init(); } diff --git a/trunk/arch/arm/mach-omap2/iommu2.c b/trunk/arch/arm/mach-omap2/iommu2.c deleted file mode 100644 index 015f22a53ead..000000000000 --- a/trunk/arch/arm/mach-omap2/iommu2.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * omap iommu: omap2/3 architecture specific functions - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU , - * Paul Mundt and Toshihiro Kobayashi - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include - -/* - * omap2 architecture specific register bit definitions - */ -#define IOMMU_ARCH_VERSION 0x00000011 - -/* SYSCONF */ -#define MMU_SYS_IDLE_SHIFT 3 -#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT) -#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT) -#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT) -#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT) - -#define MMU_SYS_SOFTRESET (1 << 1) -#define MMU_SYS_AUTOIDLE 1 - -/* SYSSTATUS */ -#define MMU_SYS_RESETDONE 1 - -/* IRQSTATUS & IRQENABLE */ -#define MMU_IRQ_MULTIHITFAULT (1 << 4) -#define MMU_IRQ_TABLEWALKFAULT (1 << 3) -#define MMU_IRQ_EMUMISS (1 << 2) -#define MMU_IRQ_TRANSLATIONFAULT (1 << 1) -#define MMU_IRQ_TLBMISS (1 << 0) -#define MMU_IRQ_MASK \ - (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ - MMU_IRQ_TRANSLATIONFAULT) - -/* MMU_CNTL */ -#define MMU_CNTL_SHIFT 1 -#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) -#define MMU_CNTL_EML_TLB (1 << 3) -#define MMU_CNTL_TWL_EN (1 << 2) -#define MMU_CNTL_MMU_EN (1 << 1) - -#define get_cam_va_mask(pgsz) \ - (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ - ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ - ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ - ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) - -static int omap2_iommu_enable(struct iommu *obj) -{ - u32 l, pa; - unsigned long timeout; - - if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) - return -EINVAL; - - pa = virt_to_phys(obj->iopgd); - if (!IS_ALIGNED(pa, SZ_16K)) - return -EINVAL; - - iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG); - - timeout = jiffies + msecs_to_jiffies(20); - do { - l = iommu_read_reg(obj, MMU_SYSSTATUS); - if (l & MMU_SYS_RESETDONE) - break; - } while (time_after(jiffies, timeout)); - - if (!(l & MMU_SYS_RESETDONE)) { - dev_err(obj->dev, "can't take mmu out of reset\n"); - return -ENODEV; - } - - l = iommu_read_reg(obj, MMU_REVISION); - dev_info(obj->dev, "%s: version %d.%d\n", obj->name, - (l >> 4) & 0xf, l & 0xf); - - l = iommu_read_reg(obj, MMU_SYSCONFIG); - l &= ~MMU_SYS_IDLE_MASK; - l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); - iommu_write_reg(obj, l, MMU_SYSCONFIG); - - iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); - iommu_write_reg(obj, pa, MMU_TTB); - - l = iommu_read_reg(obj, MMU_CNTL); - l &= ~MMU_CNTL_MASK; - l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); - iommu_write_reg(obj, l, MMU_CNTL); - - return 0; -} - -static void omap2_iommu_disable(struct iommu *obj) -{ - u32 l = iommu_read_reg(obj, MMU_CNTL); - - l &= ~MMU_CNTL_MASK; - iommu_write_reg(obj, l, MMU_CNTL); - iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG); - - dev_dbg(obj->dev, "%s is shutting down\n", obj->name); -} - -static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) -{ - int i; - u32 stat, da; - const char *err_msg[] = { - "tlb miss", - "translation fault", - "emulation miss", - "table walk fault", - "multi hit fault", - }; - - stat = iommu_read_reg(obj, MMU_IRQSTATUS); - stat &= MMU_IRQ_MASK; - if (!stat) - return 0; - - da = iommu_read_reg(obj, MMU_FAULT_AD); - *ra = da; - - dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); - - for (i = 0; i < ARRAY_SIZE(err_msg); i++) { - if (stat & (1 << i)) - printk("%s ", err_msg[i]); - } - printk("\n"); - - iommu_write_reg(obj, stat, MMU_IRQSTATUS); - return stat; -} - -static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) -{ - cr->cam = iommu_read_reg(obj, MMU_READ_CAM); - cr->ram = iommu_read_reg(obj, MMU_READ_RAM); -} - -static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr) -{ - iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); - iommu_write_reg(obj, cr->ram, MMU_RAM); -} - -static u32 omap2_cr_to_virt(struct cr_regs *cr) -{ - u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; - u32 mask = get_cam_va_mask(cr->cam & page_size); - - return cr->cam & mask; -} - -static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e) -{ - struct cr_regs *cr; - - if (e->da & ~(get_cam_va_mask(e->pgsz))) { - dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, - e->da); - return ERR_PTR(-EINVAL); - } - - cr = kmalloc(sizeof(*cr), GFP_KERNEL); - if (!cr) - return ERR_PTR(-ENOMEM); - - cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz; - cr->ram = e->pa | e->endian | e->elsz | e->mixed; - - return cr; -} - -static inline int omap2_cr_valid(struct cr_regs *cr) -{ - return cr->cam & MMU_CAM_V; -} - -static u32 omap2_get_pte_attr(struct iotlb_entry *e) -{ - u32 attr; - - attr = e->mixed << 5; - attr |= e->endian; - attr |= e->elsz >> 3; - attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6); - - return attr; -} - -static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) -{ - char *p = buf; - - /* FIXME: Need more detail analysis of cam/ram */ - p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram); - - return p - buf; -} - -#define pr_reg(name) \ - p += sprintf(p, "%20s: %08x\n", \ - __stringify(name), iommu_read_reg(obj, MMU_##name)); - -static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf) -{ - char *p = buf; - - pr_reg(REVISION); - pr_reg(SYSCONFIG); - pr_reg(SYSSTATUS); - pr_reg(IRQSTATUS); - pr_reg(IRQENABLE); - pr_reg(WALKING_ST); - pr_reg(CNTL); - pr_reg(FAULT_AD); - pr_reg(TTB); - pr_reg(LOCK); - pr_reg(LD_TLB); - pr_reg(CAM); - pr_reg(RAM); - pr_reg(GFLUSH); - pr_reg(FLUSH_ENTRY); - pr_reg(READ_CAM); - pr_reg(READ_RAM); - pr_reg(EMU_FAULT_AD); - - return p - buf; -} - -static void omap2_iommu_save_ctx(struct iommu *obj) -{ - int i; - u32 *p = obj->ctx; - - for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { - p[i] = iommu_read_reg(obj, i * sizeof(u32)); - dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); - } - - BUG_ON(p[0] != IOMMU_ARCH_VERSION); -} - -static void omap2_iommu_restore_ctx(struct iommu *obj) -{ - int i; - u32 *p = obj->ctx; - - for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { - iommu_write_reg(obj, p[i], i * sizeof(u32)); - dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); - } - - BUG_ON(p[0] != IOMMU_ARCH_VERSION); -} - -static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) -{ - e->da = cr->cam & MMU_CAM_VATAG_MASK; - e->pa = cr->ram & MMU_RAM_PADDR_MASK; - e->valid = cr->cam & MMU_CAM_V; - e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK; - e->endian = cr->ram & MMU_RAM_ENDIAN_MASK; - e->elsz = cr->ram & MMU_RAM_ELSZ_MASK; - e->mixed = cr->ram & MMU_RAM_MIXED; -} - -static const struct iommu_functions omap2_iommu_ops = { - .version = IOMMU_ARCH_VERSION, - - .enable = omap2_iommu_enable, - .disable = omap2_iommu_disable, - .fault_isr = omap2_iommu_fault_isr, - - .tlb_read_cr = omap2_tlb_read_cr, - .tlb_load_cr = omap2_tlb_load_cr, - - .cr_to_e = omap2_cr_to_e, - .cr_to_virt = omap2_cr_to_virt, - .alloc_cr = omap2_alloc_cr, - .cr_valid = omap2_cr_valid, - .dump_cr = omap2_dump_cr, - - .get_pte_attr = omap2_get_pte_attr, - - .save_ctx = omap2_iommu_save_ctx, - .restore_ctx = omap2_iommu_restore_ctx, - .dump_ctx = omap2_iommu_dump_ctx, -}; - -static int __init omap2_iommu_init(void) -{ - return install_iommu_arch(&omap2_iommu_ops); -} -module_init(omap2_iommu_init); - -static void __exit omap2_iommu_exit(void) -{ - uninstall_iommu_arch(&omap2_iommu_ops); -} -module_exit(omap2_iommu_exit); - -MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); -MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/arch/arm/mach-omap2/irq.c b/trunk/arch/arm/mach-omap2/irq.c index b82863887f10..998c5c45587e 100644 --- a/trunk/arch/arm/mach-omap2/irq.c +++ b/trunk/arch/arm/mach-omap2/irq.c @@ -28,6 +28,7 @@ #define INTC_MIR_CLEAR0 0x0088 #define INTC_MIR_SET0 0x008c #define INTC_PENDING_IRQ0 0x0098 + /* Number of IRQ state bits in each MIR register */ #define IRQ_BITS_PER_REG 32 @@ -133,6 +134,7 @@ static struct irq_chip omap_irq_chip = { .ack = omap_mask_ack_irq, .mask = omap_mask_irq, .unmask = omap_unmask_irq, + .disable = omap_mask_irq, }; static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) @@ -155,22 +157,6 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG); } -int omap_irq_pending(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { - struct omap_irq_bank *bank = irq_banks + i; - int irq; - - for (irq = 0; irq < bank->nr_irqs; irq += 32) - if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 + - ((irq >> 5) << 5))) - return 1; - } - return 0; -} - void __init omap_init_irq(void) { unsigned long nr_of_irqs = 0; diff --git a/trunk/arch/arm/mach-omap2/mmc-twl4030.c b/trunk/arch/arm/mach-omap2/mmc-twl4030.c index 9756a878fd90..dc40b3e72206 100644 --- a/trunk/arch/arm/mach-omap2/mmc-twl4030.c +++ b/trunk/arch/arm/mach-omap2/mmc-twl4030.c @@ -16,8 +16,8 @@ #include #include #include -#include -#include +#include +#include #include #include @@ -26,10 +26,32 @@ #include "mmc-twl4030.h" - -#if defined(CONFIG_REGULATOR) && \ +#if defined(CONFIG_TWL4030_CORE) && \ (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) +#define LDO_CLR 0x00 +#define VSEL_S2_CLR 0x40 + +#define VMMC1_DEV_GRP 0x27 +#define VMMC1_CLR 0x00 +#define VMMC1_315V 0x03 +#define VMMC1_300V 0x02 +#define VMMC1_285V 0x01 +#define VMMC1_185V 0x00 +#define VMMC1_DEDICATED 0x2A + +#define VMMC2_DEV_GRP 0x2B +#define VMMC2_CLR 0x40 +#define VMMC2_315V 0x0c +#define VMMC2_300V 0x0b +#define VMMC2_285V 0x0a +#define VMMC2_280V 0x09 +#define VMMC2_260V 0x08 +#define VMMC2_185V 0x06 +#define VMMC2_DEDICATED 0x2E + +#define VMMC_DEV_GRP_P1 0x20 + static u16 control_pbias_offset; static u16 control_devconf1_offset; @@ -37,16 +59,19 @@ static u16 control_devconf1_offset; static struct twl_mmc_controller { struct omap_mmc_platform_data *mmc; - /* Vcc == configured supply - * Vcc_alt == optional - * - MMC1, supply for DAT4..DAT7 - * - MMC2/MMC2, external level shifter voltage supply, for - * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) - */ - struct regulator *vcc; - struct regulator *vcc_aux; - char name[HSMMC_NAME_LEN + 1]; -} hsmmc[OMAP34XX_NR_MMC]; + u8 twl_vmmc_dev_grp; + u8 twl_mmc_dedicated; + char name[HSMMC_NAME_LEN + 1]; +} hsmmc[OMAP34XX_NR_MMC] = { + { + .twl_vmmc_dev_grp = VMMC1_DEV_GRP, + .twl_mmc_dedicated = VMMC1_DEDICATED, + }, + { + .twl_vmmc_dev_grp = VMMC2_DEV_GRP, + .twl_mmc_dedicated = VMMC2_DEDICATED, + }, +}; static int twl_mmc_card_detect(int irq) { @@ -92,60 +117,16 @@ static int twl_mmc_late_init(struct device *dev) int ret = 0; int i; - /* MMC/SD/SDIO doesn't require a card detect switch */ - if (gpio_is_valid(mmc->slots[0].switch_pin)) { - ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd"); - if (ret) - goto done; - ret = gpio_direction_input(mmc->slots[0].switch_pin); - if (ret) - goto err; - } + ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd"); + if (ret) + goto done; + ret = gpio_direction_input(mmc->slots[0].switch_pin); + if (ret) + goto err; - /* require at least main regulator */ for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { if (hsmmc[i].name == mmc->slots[0].name) { - struct regulator *reg; - hsmmc[i].mmc = mmc; - - reg = regulator_get(dev, "vmmc"); - if (IS_ERR(reg)) { - dev_dbg(dev, "vmmc regulator missing\n"); - /* HACK: until fixed.c regulator is usable, - * we don't require a main regulator - * for MMC2 or MMC3 - */ - if (i != 0) - break; - ret = PTR_ERR(reg); - goto err; - } - hsmmc[i].vcc = reg; - mmc->slots[0].ocr_mask = mmc_regulator_get_ocrmask(reg); - - /* allow an aux regulator */ - reg = regulator_get(dev, "vmmc_aux"); - hsmmc[i].vcc_aux = IS_ERR(reg) ? NULL : reg; - - /* UGLY HACK: workaround regulator framework bugs. - * When the bootloader leaves a supply active, it's - * initialized with zero usecount ... and we can't - * disable it without first enabling it. Until the - * framework is fixed, we need a workaround like this - * (which is safe for MMC, but not in general). - */ - if (regulator_is_enabled(hsmmc[i].vcc) > 0) { - regulator_enable(hsmmc[i].vcc); - regulator_disable(hsmmc[i].vcc); - } - if (hsmmc[i].vcc_aux) { - if (regulator_is_enabled(reg) > 0) { - regulator_enable(reg); - regulator_disable(reg); - } - } - break; } } @@ -192,6 +173,96 @@ static int twl_mmc_resume(struct device *dev, int slot) #define twl_mmc_resume NULL #endif +/* + * Sets the MMC voltage in twl4030 + */ + +#define MMC1_OCR (MMC_VDD_165_195 \ + |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32) +#define MMC2_OCR (MMC_VDD_165_195 \ + |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \ + |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32) + +static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd) +{ + int ret; + u8 vmmc = 0, dev_grp_val; + + if (!vdd) + goto doit; + + if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) { + /* VMMC1: max 220 mA. And for 8-bit mode, + * VSIM: max 50 mA + */ + switch (1 << vdd) { + case MMC_VDD_165_195: + vmmc = VMMC1_185V; + /* and VSIM_180V */ + break; + case MMC_VDD_28_29: + vmmc = VMMC1_285V; + /* and VSIM_280V */ + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + vmmc = VMMC1_300V; + /* and VSIM_300V */ + break; + case MMC_VDD_31_32: + vmmc = VMMC1_315V; + /* error if VSIM needed */ + break; + default: + return -EINVAL; + } + } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) { + /* VMMC2: max 100 mA */ + switch (1 << vdd) { + case MMC_VDD_165_195: + vmmc = VMMC2_185V; + break; + case MMC_VDD_25_26: + case MMC_VDD_26_27: + vmmc = VMMC2_260V; + break; + case MMC_VDD_27_28: + vmmc = VMMC2_280V; + break; + case MMC_VDD_28_29: + vmmc = VMMC2_285V; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + vmmc = VMMC2_300V; + break; + case MMC_VDD_31_32: + vmmc = VMMC2_315V; + break; + default: + return -EINVAL; + } + } else { + return -EINVAL; + } + +doit: + if (vdd) + dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */ + else + dev_grp_val = LDO_CLR; /* Power down */ + + ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, + dev_grp_val, c->twl_vmmc_dev_grp); + if (ret || !vdd) + return ret; + + ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, + vmmc, c->twl_mmc_dedicated); + + return ret; +} + static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, int vdd) { @@ -202,13 +273,11 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, /* * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the - * card with Vcc regulator (from twl4030 or whatever). OMAP has both + * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both * 1.8V and 3.0V modes, controlled by the PBIAS register. * * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which * is most naturally TWL VSIM; those pins also use PBIAS. - * - * FIXME handle VMMC1A as needed ... */ if (power_on) { if (cpu_is_omap2430()) { @@ -231,7 +300,7 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, reg &= ~OMAP2_PBIASLITEPWRDNZ0; omap_ctrl_writel(reg, control_pbias_offset); - ret = mmc_regulator_set_ocr(c->vcc, vdd); + ret = twl_mmc_set_voltage(c, vdd); /* 100ms delay required for PBIAS configuration */ msleep(100); @@ -247,7 +316,7 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, reg &= ~OMAP2_PBIASLITEPWRDNZ0; omap_ctrl_writel(reg, control_pbias_offset); - ret = mmc_regulator_set_ocr(c->vcc, 0); + ret = twl_mmc_set_voltage(c, 0); /* 100ms delay required for PBIAS configuration */ msleep(100); @@ -260,33 +329,19 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, return ret; } -static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd) +static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd) { - int ret = 0; + int ret; struct twl_mmc_controller *c = &hsmmc[1]; struct omap_mmc_platform_data *mmc = dev->platform_data; - /* If we don't see a Vcc regulator, assume it's a fixed - * voltage always-on regulator. - */ - if (!c->vcc) - return 0; - /* - * Assume Vcc regulator is used only to power the card ... OMAP + * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP * VDDS is used to power the pins, optionally with a transceiver to * support cards using voltages other than VDDS (1.8V nominal). When a * transceiver is used, DAT3..7 are muxed as transceiver control pins. - * - * In some cases this regulator won't support enable/disable; - * e.g. it's a fixed rail for a WLAN chip. - * - * In other cases vcc_aux switches interface power. Example, for - * eMMC cards it represents VccQ. Sometimes transceivers or SDIO - * chips/cards need an interface voltage rail too. */ if (power_on) { - /* only MMC2 supports a CLKIN */ if (mmc->slots[0].internal_clock) { u32 reg; @@ -294,23 +349,24 @@ static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int v reg |= OMAP2_MMCSDIO2ADPCLKISEL; omap_ctrl_writel(reg, control_devconf1_offset); } - ret = mmc_regulator_set_ocr(c->vcc, vdd); - /* enable interface voltage rail, if needed */ - if (ret == 0 && c->vcc_aux) { - ret = regulator_enable(c->vcc_aux); - if (ret < 0) - ret = mmc_regulator_set_ocr(c->vcc, 0); - } + ret = twl_mmc_set_voltage(c, vdd); } else { - if (c->vcc_aux && (ret = regulator_is_enabled(c->vcc_aux)) > 0) - ret = regulator_disable(c->vcc_aux); - if (ret == 0) - ret = mmc_regulator_set_ocr(c->vcc, 0); + ret = twl_mmc_set_voltage(c, 0); } return ret; } +static int twl_mmc3_set_power(struct device *dev, int slot, int power_on, + int vdd) +{ + /* + * Assume MMC3 has self-powered device connected, for example on-board + * chip with external power source. + */ + return 0; +} + static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) @@ -356,10 +412,10 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) mmc->slots[0].wires = c->wires; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; - mmc->init = twl_mmc_late_init; - /* note: twl4030 card detect GPIOs can disable VMMCx ... */ + /* note: twl4030 card detect GPIOs normally switch VMMCx ... */ if (gpio_is_valid(c->gpio_cd)) { + mmc->init = twl_mmc_late_init; mmc->cleanup = twl_mmc_cleanup; mmc->suspend = twl_mmc_suspend; mmc->resume = twl_mmc_resume; @@ -383,28 +439,26 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) } else mmc->slots[0].gpio_wp = -EINVAL; - /* NOTE: MMC slots should have a Vcc regulator set up. - * This may be from a TWL4030-family chip, another - * controllable regulator, or a fixed supply. - * - * temporary HACK: ocr_mask instead of fixed supply + /* NOTE: we assume OMAP's MMC1 and MMC2 use + * the TWL4030's VMMC1 and VMMC2, respectively; + * and that MMC3 device has it's own power source. */ - mmc->slots[0].ocr_mask = c->ocr_mask; switch (c->mmc) { case 1: - /* on-chip level shifting via PBIAS0/PBIAS1 */ mmc->slots[0].set_power = twl_mmc1_set_power; + mmc->slots[0].ocr_mask = MMC1_OCR; break; case 2: - if (c->ext_clock) - c->transceiver = 1; - if (c->transceiver && c->wires > 4) - c->wires = 4; - /* FALLTHROUGH */ + mmc->slots[0].set_power = twl_mmc2_set_power; + if (c->transceiver) + mmc->slots[0].ocr_mask = MMC2_OCR; + else + mmc->slots[0].ocr_mask = MMC_VDD_165_195; + break; case 3: - /* off-chip level shifting, or none */ - mmc->slots[0].set_power = twl_mmc23_set_power; + mmc->slots[0].set_power = twl_mmc3_set_power; + mmc->slots[0].ocr_mask = MMC_VDD_165_195; break; default: pr_err("MMC%d configuration not supported!\n", c->mmc); diff --git a/trunk/arch/arm/mach-omap2/mmc-twl4030.h b/trunk/arch/arm/mach-omap2/mmc-twl4030.h index 3807c45c9a6c..ea59e8624290 100644 --- a/trunk/arch/arm/mach-omap2/mmc-twl4030.h +++ b/trunk/arch/arm/mach-omap2/mmc-twl4030.h @@ -16,10 +16,9 @@ struct twl4030_hsmmc_info { int gpio_wp; /* or -EINVAL */ char *name; /* or NULL for default */ struct device *dev; /* returned: pointer to mmc adapter */ - int ocr_mask; /* temporary HACK */ }; -#if defined(CONFIG_REGULATOR) && \ +#if defined(CONFIG_TWL4030_CORE) && \ (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) diff --git a/trunk/arch/arm/mach-omap2/omap-headsmp.S b/trunk/arch/arm/mach-omap2/omap-headsmp.S deleted file mode 100644 index 4afadba09477..000000000000 --- a/trunk/arch/arm/mach-omap2/omap-headsmp.S +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Secondary CPU startup routine source file. - * - * Copyright (C) 2009 Texas Instruments, Inc. - * - * Author: - * Santosh Shilimkar - * - * Interface functions needed for the SMP. This file is based on arm - * realview smp platform. - * Copyright (c) 2003 ARM Limited. - * - * This program is free software,you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - -/* Physical address needed since MMU not enabled yet on secondary core */ -#define OMAP4_AUX_CORE_BOOT1_PA 0x48281804 - - __INIT - -/* - * OMAP4 specific entry point for secondary CPU to jump from ROM - * code. This routine also provides a holding flag into which - * secondary core is held until we're ready for it to initialise. - * The primary core will update the this flag using a hardware - * register AuxCoreBoot1. - */ -ENTRY(omap_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #0x0f -hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1 - ldr r2, [r1] - cmp r2, r0 - bne hold - - /* - * we've been released from the cpu_release,secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup - diff --git a/trunk/arch/arm/mach-omap2/omap-smp.c b/trunk/arch/arm/mach-omap2/omap-smp.c deleted file mode 100644 index 8fe8d230f21b..000000000000 --- a/trunk/arch/arm/mach-omap2/omap-smp.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * OMAP4 SMP source file. It contains platform specific fucntions - * needed for the linux smp kernel. - * - * Copyright (C) 2009 Texas Instruments, Inc. - * - * Author: - * Santosh Shilimkar - * - * Platform file needed for the OMAP4 SMP. This file is based on arm - * realview smp platform. - * * Copyright (c) 2002 ARM Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -/* Registers used for communicating startup information */ -#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) -#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) - -/* SCU base address */ -static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; - -/* - * Use SCU config register to count number of cores - */ -static inline unsigned int get_core_count(void) -{ - if (scu_base) - return scu_get_core_count(scu_base); - return 1; -} - -static DEFINE_SPINLOCK(boot_lock); - -void __cpuinit platform_secondary_init(unsigned int cpu) -{ - trace_hardirqs_off(); - - /* - * If any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - - gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * Set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * Update the AuxCoreBoot1 with boot state for secondary core. - * omap_secondary_startup() routine will hold the secondary core till - * the AuxCoreBoot1 register is updated with cpu state - * A barrier is added to ensure that write buffer is drained - */ - __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); - smp_wmb(); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) - ; - - /* - * Now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return 0; -} - -static void __init wakeup_secondary(void) -{ - /* - * Write the address of secondary startup routine into the - * AuxCoreBoot0 where ROM code will jump and start executing - * on secondary core once out of WFE - * A barrier is added to ensure that write buffer is drained - */ - __raw_writel(virt_to_phys(omap_secondary_startup), \ - OMAP4_AUXCOREBOOT_REG0); - smp_wmb(); - - /* - * Send a 'sev' to wake the secondary core from WFE. - */ - set_event(); - mb(); -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -void __init smp_init_cpus(void) -{ - unsigned int i, ncores = get_core_count(); - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); -} - -void __init smp_prepare_cpus(unsigned int max_cpus) -{ - unsigned int ncores = get_core_count(); - unsigned int cpu = smp_processor_id(); - int i; - - /* sanity check */ - if (ncores == 0) { - printk(KERN_ERR - "OMAP4: strange core count of 0? Default to 1\n"); - ncores = 1; - } - - if (ncores > NR_CPUS) { - printk(KERN_WARNING - "OMAP4: no. of cores (%d) greater than configured " - "maximum of %d - clipping\n", - ncores, NR_CPUS); - ncores = NR_CPUS; - } - smp_store_cpu_info(cpu); - - /* - * are we trying to boot more cores than exist? - */ - if (max_cpus > ncores) - max_cpus = ncores; - - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); - - if (max_cpus > 1) { - /* - * Enable the local timer or broadcast device for the - * boot CPU, but only if we have more than one CPU. - */ - percpu_timer_setup(); - - /* - * Initialise the SCU and wake up the secondary core using - * wakeup_secondary(). - */ - scu_enable(scu_base); - wakeup_secondary(); - } -} diff --git a/trunk/arch/arm/mach-omap2/omap3-iommu.c b/trunk/arch/arm/mach-omap2/omap3-iommu.c deleted file mode 100644 index 194189c746c2..000000000000 --- a/trunk/arch/arm/mach-omap2/omap3-iommu.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * omap iommu: omap3 device registration - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -#include - -#define OMAP3_MMU1_BASE 0x480bd400 -#define OMAP3_MMU2_BASE 0x5d000000 -#define OMAP3_MMU1_IRQ 24 -#define OMAP3_MMU2_IRQ 28 - - -static unsigned long iommu_base[] __initdata = { - OMAP3_MMU1_BASE, - OMAP3_MMU2_BASE, -}; - -static int iommu_irq[] __initdata = { - OMAP3_MMU1_IRQ, - OMAP3_MMU2_IRQ, -}; - -static const struct iommu_platform_data omap3_iommu_pdata[] __initconst = { - { - .name = "isp", - .nr_tlb_entries = 8, - .clk_name = "cam_ick", - }, -#if defined(CONFIG_MPU_BRIDGE_IOMMU) - { - .name = "iva2", - .nr_tlb_entries = 32, - .clk_name = "iva2_ck", - }, -#endif -}; -#define NR_IOMMU_DEVICES ARRAY_SIZE(omap3_iommu_pdata) - -static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES]; - -static int __init omap3_iommu_init(void) -{ - int i, err; - - for (i = 0; i < NR_IOMMU_DEVICES; i++) { - struct platform_device *pdev; - struct resource res[2]; - - pdev = platform_device_alloc("omap-iommu", i); - if (!pdev) { - err = -ENOMEM; - goto err_out; - } - - memset(res, 0, sizeof(res)); - res[0].start = iommu_base[i]; - res[0].end = iommu_base[i] + MMU_REG_SIZE - 1; - res[0].flags = IORESOURCE_MEM; - res[1].start = res[1].end = iommu_irq[i]; - res[1].flags = IORESOURCE_IRQ; - - err = platform_device_add_resources(pdev, res, - ARRAY_SIZE(res)); - if (err) - goto err_out; - err = platform_device_add_data(pdev, &omap3_iommu_pdata[i], - sizeof(omap3_iommu_pdata[0])); - if (err) - goto err_out; - err = platform_device_add(pdev); - if (err) - goto err_out; - omap3_iommu_pdev[i] = pdev; - } - return 0; - -err_out: - while (i--) - platform_device_put(omap3_iommu_pdev[i]); - return err; -} -module_init(omap3_iommu_init); - -static void __exit omap3_iommu_exit(void) -{ - int i; - - for (i = 0; i < NR_IOMMU_DEVICES; i++) - platform_device_unregister(omap3_iommu_pdev[i]); -} -module_exit(omap3_iommu_exit); - -MODULE_AUTHOR("Hiroshi DOYU"); -MODULE_DESCRIPTION("omap iommu: omap3 device registration"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/arch/arm/mach-omap2/pm-debug.c b/trunk/arch/arm/mach-omap2/pm-debug.c deleted file mode 100644 index 6cc375a275be..000000000000 --- a/trunk/arch/arm/mach-omap2/pm-debug.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * OMAP Power Management debug routines - * - * Copyright (C) 2005 Texas Instruments, Inc. - * Copyright (C) 2006-2008 Nokia Corporation - * - * Written by: - * Richard Woodruff - * Tony Lindgren - * Juha Yrjola - * Amit Kucheria - * Igor Stoppa - * Jouni Hogander - * - * Based on pm.c for omap2 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#include "prm.h" -#include "cm.h" -#include "pm.h" - -int omap2_pm_debug; - -#define DUMP_PRM_MOD_REG(mod, reg) \ - regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = prm_read_mod_reg(mod, reg) -#define DUMP_CM_MOD_REG(mod, reg) \ - regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = cm_read_mod_reg(mod, reg) -#define DUMP_PRM_REG(reg) \ - regs[reg_count].name = #reg; \ - regs[reg_count++].val = __raw_readl(reg) -#define DUMP_CM_REG(reg) \ - regs[reg_count].name = #reg; \ - regs[reg_count++].val = __raw_readl(reg) -#define DUMP_INTC_REG(reg, off) \ - regs[reg_count].name = #reg; \ - regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off))) - -void omap2_pm_dump(int mode, int resume, unsigned int us) -{ - struct reg { - const char *name; - u32 val; - } regs[32]; - int reg_count = 0, i; - const char *s1 = NULL, *s2 = NULL; - - if (!resume) { -#if 0 - /* MPU */ - DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); - DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); - DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL); - DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST); - DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); -#endif -#if 0 - /* INTC */ - DUMP_INTC_REG(INTC_MIR0, 0x0084); - DUMP_INTC_REG(INTC_MIR1, 0x00a4); - DUMP_INTC_REG(INTC_MIR2, 0x00c4); -#endif -#if 0 - DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1); - if (cpu_is_omap24xx()) { - DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2); - DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD, - OMAP2_PRCM_CLKEMUL_CTRL_OFFSET); - DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD, - OMAP2_PRCM_CLKSRC_CTRL_OFFSET); - } - DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN); - DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1); - DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2); - DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN); - DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN); - DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE); - DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST); -#endif -#if 0 - /* DSP */ - if (cpu_is_omap24xx()) { - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST); - } -#endif - } else { - DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1); - if (cpu_is_omap24xx()) - DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2); - DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST); - DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); -#if 1 - DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098); - DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8); - DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8); -#endif - } - - switch (mode) { - case 0: - s1 = "full"; - s2 = "retention"; - break; - case 1: - s1 = "MPU"; - s2 = "retention"; - break; - case 2: - s1 = "MPU"; - s2 = "idle"; - break; - } - - if (!resume) -#ifdef CONFIG_NO_HZ - printk(KERN_INFO - "--- Going to %s %s (next timer after %u ms)\n", s1, s2, - jiffies_to_msecs(get_next_timer_interrupt(jiffies) - - jiffies)); -#else - printk(KERN_INFO "--- Going to %s %s\n", s1, s2); -#endif - else - printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n", - us / 1000, us % 1000); - - for (i = 0; i < reg_count; i++) - printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val); -} diff --git a/trunk/arch/arm/mach-omap2/pm.c b/trunk/arch/arm/mach-omap2/pm.c new file mode 100644 index 000000000000..ea8ceaed09cb --- /dev/null +++ b/trunk/arch/arm/mach-omap2/pm.c @@ -0,0 +1,111 @@ +/* + * linux/arch/arm/mach-omap2/pm.c + * + * OMAP2 Power Management Routines + * + * Copyright (C) 2006 Nokia Corporation + * Tony Lindgren + * + * Copyright (C) 2005 Texas Instruments, Inc. + * Richard Woodruff + * + * Based on pm.c for omap1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct clk *vclk; +static void (*omap2_sram_idle)(void); +static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); +static void (*saved_idle)(void); + +extern void __init pmdomain_init(void); +extern void pmdomain_set_autoidle(void); + +static unsigned int omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_SIZE]; + +void omap2_pm_idle(void) +{ + local_irq_disable(); + local_fiq_disable(); + if (need_resched()) { + local_fiq_enable(); + local_irq_enable(); + return; + } + + omap2_sram_idle(); + local_fiq_enable(); + local_irq_enable(); +} + +static int omap2_pm_prepare(void) +{ + /* We cannot sleep in idle until we have resumed */ + saved_idle = pm_idle; + pm_idle = NULL; + return 0; +} + +static int omap2_pm_suspend(void) +{ + return 0; +} + +static int omap2_pm_enter(suspend_state_t state) +{ + int ret = 0; + + switch (state) + { + case PM_SUSPEND_STANDBY: + case PM_SUSPEND_MEM: + ret = omap2_pm_suspend(); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static void omap2_pm_finish(void) +{ + pm_idle = saved_idle; +} + +static struct platform_suspend_ops omap_pm_ops = { + .prepare = omap2_pm_prepare, + .enter = omap2_pm_enter, + .finish = omap2_pm_finish, + .valid = suspend_valid_only_mem, +}; + +static int __init omap2_pm_init(void) +{ + return 0; +} + +__initcall(omap2_pm_init); diff --git a/trunk/arch/arm/mach-omap2/pm.h b/trunk/arch/arm/mach-omap2/pm.h deleted file mode 100644 index f7b3baf76678..000000000000 --- a/trunk/arch/arm/mach-omap2/pm.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * OMAP2/3 Power Management Routines - * - * Copyright (C) 2008 Nokia Corporation - * Jouni Hogander - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ARCH_ARM_MACH_OMAP2_PM_H -#define __ARCH_ARM_MACH_OMAP2_PM_H - -extern int omap2_pm_init(void); -extern int omap3_pm_init(void); - -#ifdef CONFIG_PM_DEBUG -extern void omap2_pm_dump(int mode, int resume, unsigned int us); -extern int omap2_pm_debug; -#else -#define omap2_pm_dump(mode, resume, us) do {} while (0); -#define omap2_pm_debug 0 -#endif /* CONFIG_PM_DEBUG */ - -extern void omap24xx_idle_loop_suspend(void); - -extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, - void __iomem *sdrc_power); -extern void omap34xx_cpu_suspend(u32 *addr, int save_state); -extern void save_secure_ram_context(u32 *addr); - -extern unsigned int omap24xx_idle_loop_suspend_sz; -extern unsigned int omap34xx_suspend_sz; -extern unsigned int save_secure_ram_context_sz; -extern unsigned int omap24xx_cpu_suspend_sz; -extern unsigned int omap34xx_cpu_suspend_sz; - -#endif diff --git a/trunk/arch/arm/mach-omap2/pm24xx.c b/trunk/arch/arm/mach-omap2/pm24xx.c deleted file mode 100644 index db1025562fb0..000000000000 --- a/trunk/arch/arm/mach-omap2/pm24xx.c +++ /dev/null @@ -1,549 +0,0 @@ -/* - * OMAP2 Power Management Routines - * - * Copyright (C) 2005 Texas Instruments, Inc. - * Copyright (C) 2006-2008 Nokia Corporation - * - * Written by: - * Richard Woodruff - * Tony Lindgren - * Juha Yrjola - * Amit Kucheria - * Igor Stoppa - * - * Based on pm.c for omap1 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "prm.h" -#include "prm-regbits-24xx.h" -#include "cm.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "pm.h" - -#include -#include - -static void (*omap2_sram_idle)(void); -static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, - void __iomem *sdrc_power); - -static struct powerdomain *mpu_pwrdm; -static struct powerdomain *core_pwrdm; - -static struct clockdomain *dsp_clkdm; -static struct clockdomain *gfx_clkdm; - -static struct clk *osc_ck, *emul_ck; - -static int omap2_fclks_active(void) -{ - u32 f1, f2; - - f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - - /* Ignore UART clocks. These are handled by UART core (serial.c) */ - f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2); - f2 &= ~OMAP24XX_EN_UART3; - - if (f1 | f2) - return 1; - return 0; -} - -static void omap2_enter_full_retention(void) -{ - u32 l; - struct timespec ts_preidle, ts_postidle, ts_idle; - - /* There is 1 reference hold for all children of the oscillator - * clock, the following will remove it. If no one else uses the - * oscillator itself it will be disabled if/when we enter retention - * mode. - */ - clk_disable(osc_ck); - - /* Clear old wake-up events */ - /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); - - /* - * Set MPU powerdomain's next power state to RETENTION; - * preserve logic state during retention - */ - pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); - pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); - - /* Workaround to kill USB */ - l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; - omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); - - omap2_gpio_prepare_for_retention(); - - if (omap2_pm_debug) { - omap2_pm_dump(0, 0, 0); - getnstimeofday(&ts_preidle); - } - - /* One last check for pending IRQs to avoid extra latency due - * to sleeping unnecessarily. */ - if (omap_irq_pending()) - goto no_sleep; - - omap_uart_prepare_idle(0); - omap_uart_prepare_idle(1); - omap_uart_prepare_idle(2); - - /* Jump to SRAM suspend code */ - omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), - OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), - OMAP_SDRC_REGADDR(SDRC_POWER)); - - omap_uart_resume_idle(2); - omap_uart_resume_idle(1); - omap_uart_resume_idle(0); - -no_sleep: - if (omap2_pm_debug) { - unsigned long long tmp; - - getnstimeofday(&ts_postidle); - ts_idle = timespec_sub(ts_postidle, ts_preidle); - tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; - omap2_pm_dump(0, 1, tmp); - } - omap2_gpio_resume_after_retention(); - - clk_enable(osc_ck); - - /* clear CORE wake-up events */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - - /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ - prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); - - /* MPU domain wake events */ - l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); - if (l & 0x01) - prm_write_mod_reg(0x01, OCP_MOD, - OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); - if (l & 0x20) - prm_write_mod_reg(0x20, OCP_MOD, - OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); - - /* Mask future PRCM-to-MPU interrupts */ - prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); -} - -static int omap2_i2c_active(void) -{ - u32 l; - - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1); -} - -static int sti_console_enabled; - -static int omap2_allow_mpu_retention(void) -{ - u32 l; - - /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 | - OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 | - OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1)) - return 0; - /* Check for UART3. */ - l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - if (l & OMAP24XX_EN_UART3) - return 0; - if (sti_console_enabled) - return 0; - - return 1; -} - -static void omap2_enter_mpu_retention(void) -{ - int only_idle = 0; - struct timespec ts_preidle, ts_postidle, ts_idle; - - /* Putting MPU into the WFI state while a transfer is active - * seems to cause the I2C block to timeout. Why? Good question. */ - if (omap2_i2c_active()) - return; - - /* The peripherals seem not to be able to wake up the MPU when - * it is in retention mode. */ - if (omap2_allow_mpu_retention()) { - /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); - - /* Try to enter MPU retention */ - prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | - OMAP_LOGICRETSTATE, - MPU_MOD, PM_PWSTCTRL); - } else { - /* Block MPU retention */ - - prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL); - only_idle = 1; - } - - if (omap2_pm_debug) { - omap2_pm_dump(only_idle ? 2 : 1, 0, 0); - getnstimeofday(&ts_preidle); - } - - omap2_sram_idle(); - - if (omap2_pm_debug) { - unsigned long long tmp; - - getnstimeofday(&ts_postidle); - ts_idle = timespec_sub(ts_postidle, ts_preidle); - tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; - omap2_pm_dump(only_idle ? 2 : 1, 1, tmp); - } -} - -static int omap2_can_sleep(void) -{ - if (omap2_fclks_active()) - return 0; - if (osc_ck->usecount > 1) - return 0; - if (omap_dma_running()) - return 0; - - return 1; -} - -static void omap2_pm_idle(void) -{ - local_irq_disable(); - local_fiq_disable(); - - if (!omap2_can_sleep()) { - if (omap_irq_pending()) - goto out; - omap2_enter_mpu_retention(); - goto out; - } - - if (omap_irq_pending()) - goto out; - - omap2_enter_full_retention(); - -out: - local_fiq_enable(); - local_irq_enable(); -} - -static int omap2_pm_prepare(void) -{ - /* We cannot sleep in idle until we have resumed */ - disable_hlt(); - return 0; -} - -static int omap2_pm_suspend(void) -{ - u32 wken_wkup, mir1; - - wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); - prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN); - - /* Mask GPT1 */ - mir1 = omap_readl(0x480fe0a4); - omap_writel(1 << 5, 0x480fe0ac); - - omap_uart_prepare_suspend(); - omap2_enter_full_retention(); - - omap_writel(mir1, 0x480fe0a4); - prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); - - return 0; -} - -static int omap2_pm_enter(suspend_state_t state) -{ - int ret = 0; - - switch (state) { - case PM_SUSPEND_STANDBY: - case PM_SUSPEND_MEM: - ret = omap2_pm_suspend(); - break; - default: - ret = -EINVAL; - } - - return ret; -} - -static void omap2_pm_finish(void) -{ - enable_hlt(); -} - -static struct platform_suspend_ops omap_pm_ops = { - .prepare = omap2_pm_prepare, - .enter = omap2_pm_enter, - .finish = omap2_pm_finish, - .valid = suspend_valid_only_mem, -}; - -static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm) -{ - omap2_clkdm_allow_idle(clkdm); - return 0; -} - -static void __init prcm_setup_regs(void) -{ - int i, num_mem_banks; - struct powerdomain *pwrdm; - - /* Enable autoidle */ - prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD, - OMAP2_PRCM_SYSCONFIG_OFFSET); - - /* Set all domain wakeup dependencies */ - prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP); - prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); - prm_write_mod_reg(0, CORE_MOD, PM_WKDEP); - if (cpu_is_omap2430()) - prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP); - - /* - * Set CORE powerdomain memory banks to retain their contents - * during RETENTION - */ - num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm); - for (i = 0; i < num_mem_banks; i++) - pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); - - /* Set CORE powerdomain's next power state to RETENTION */ - pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); - - /* - * Set MPU powerdomain's next power state to RETENTION; - * preserve logic state during retention - */ - pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); - pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); - - /* Force-power down DSP, GFX powerdomains */ - - pwrdm = clkdm_get_pwrdm(dsp_clkdm); - pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); - omap2_clkdm_sleep(dsp_clkdm); - - pwrdm = clkdm_get_pwrdm(gfx_clkdm); - pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); - omap2_clkdm_sleep(gfx_clkdm); - - /* Enable clockdomain hardware-supervised control for all clkdms */ - clkdm_for_each(_pm_clkdm_enable_hwsup); - - /* Enable clock autoidle for all domains */ - cm_write_mod_reg(OMAP24XX_AUTO_CAM | - OMAP24XX_AUTO_MAILBOXES | - OMAP24XX_AUTO_WDT4 | - OMAP2420_AUTO_WDT3 | - OMAP24XX_AUTO_MSPRO | - OMAP2420_AUTO_MMC | - OMAP24XX_AUTO_FAC | - OMAP2420_AUTO_EAC | - OMAP24XX_AUTO_HDQ | - OMAP24XX_AUTO_UART2 | - OMAP24XX_AUTO_UART1 | - OMAP24XX_AUTO_I2C2 | - OMAP24XX_AUTO_I2C1 | - OMAP24XX_AUTO_MCSPI2 | - OMAP24XX_AUTO_MCSPI1 | - OMAP24XX_AUTO_MCBSP2 | - OMAP24XX_AUTO_MCBSP1 | - OMAP24XX_AUTO_GPT12 | - OMAP24XX_AUTO_GPT11 | - OMAP24XX_AUTO_GPT10 | - OMAP24XX_AUTO_GPT9 | - OMAP24XX_AUTO_GPT8 | - OMAP24XX_AUTO_GPT7 | - OMAP24XX_AUTO_GPT6 | - OMAP24XX_AUTO_GPT5 | - OMAP24XX_AUTO_GPT4 | - OMAP24XX_AUTO_GPT3 | - OMAP24XX_AUTO_GPT2 | - OMAP2420_AUTO_VLYNQ | - OMAP24XX_AUTO_DSS, - CORE_MOD, CM_AUTOIDLE1); - cm_write_mod_reg(OMAP24XX_AUTO_UART3 | - OMAP24XX_AUTO_SSI | - OMAP24XX_AUTO_USB, - CORE_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(OMAP24XX_AUTO_SDRC | - OMAP24XX_AUTO_GPMC | - OMAP24XX_AUTO_SDMA, - CORE_MOD, CM_AUTOIDLE3); - cm_write_mod_reg(OMAP24XX_AUTO_PKA | - OMAP24XX_AUTO_AES | - OMAP24XX_AUTO_RNG | - OMAP24XX_AUTO_SHA | - OMAP24XX_AUTO_DES, - CORE_MOD, OMAP24XX_CM_AUTOIDLE4); - - cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE); - - /* Put DPLL and both APLLs into autoidle mode */ - cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | - (0x03 << OMAP24XX_AUTO_96M_SHIFT) | - (0x03 << OMAP24XX_AUTO_54M_SHIFT), - PLL_MOD, CM_AUTOIDLE); - - cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL | - OMAP24XX_AUTO_WDT1 | - OMAP24XX_AUTO_MPU_WDT | - OMAP24XX_AUTO_GPIOS | - OMAP24XX_AUTO_32KSYNC | - OMAP24XX_AUTO_GPT1, - WKUP_MOD, CM_AUTOIDLE); - - /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk - * stabilisation */ - prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP2_PRCM_CLKSSETUP_OFFSET); - - /* Configure automatic voltage transition */ - prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP2_PRCM_VOLTSETUP_OFFSET); - prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT | - (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | - OMAP24XX_MEMRETCTRL | - (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | - (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), - OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); - - /* Enable wake-up events */ - prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1, - WKUP_MOD, PM_WKEN); -} - -int __init omap2_pm_init(void) -{ - u32 l; - - if (!cpu_is_omap24xx()) - return -ENODEV; - - printk(KERN_INFO "Power Management for OMAP2 initializing\n"); - l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); - printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); - - /* Look up important powerdomains, clockdomains */ - - mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); - if (!mpu_pwrdm) - pr_err("PM: mpu_pwrdm not found\n"); - - core_pwrdm = pwrdm_lookup("core_pwrdm"); - if (!core_pwrdm) - pr_err("PM: core_pwrdm not found\n"); - - dsp_clkdm = clkdm_lookup("dsp_clkdm"); - if (!dsp_clkdm) - pr_err("PM: mpu_clkdm not found\n"); - - gfx_clkdm = clkdm_lookup("gfx_clkdm"); - if (!gfx_clkdm) - pr_err("PM: gfx_clkdm not found\n"); - - - osc_ck = clk_get(NULL, "osc_ck"); - if (IS_ERR(osc_ck)) { - printk(KERN_ERR "could not get osc_ck\n"); - return -ENODEV; - } - - if (cpu_is_omap242x()) { - emul_ck = clk_get(NULL, "emul_ck"); - if (IS_ERR(emul_ck)) { - printk(KERN_ERR "could not get emul_ck\n"); - clk_put(osc_ck); - return -ENODEV; - } - } - - prcm_setup_regs(); - - /* Hack to prevent MPU retention when STI console is enabled. */ - { - const struct omap_sti_console_config *sti; - - sti = omap_get_config(OMAP_TAG_STI_CONSOLE, - struct omap_sti_console_config); - if (sti != NULL && sti->enable) - sti_console_enabled = 1; - } - - /* - * We copy the assembler sleep/wakeup routines to SRAM. - * These routines need to be in SRAM as that's the only - * memory the MPU can see when it wakes up. - */ - if (cpu_is_omap24xx()) { - omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend, - omap24xx_idle_loop_suspend_sz); - - omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, - omap24xx_cpu_suspend_sz); - } - - suspend_set_ops(&omap_pm_ops); - pm_idle = omap2_pm_idle; - - return 0; -} - -late_initcall(omap2_pm_init); diff --git a/trunk/arch/arm/mach-omap2/pm34xx.c b/trunk/arch/arm/mach-omap2/pm34xx.c deleted file mode 100644 index 841d4c5ed8be..000000000000 --- a/trunk/arch/arm/mach-omap2/pm34xx.c +++ /dev/null @@ -1,710 +0,0 @@ -/* - * OMAP3 Power Management Routines - * - * Copyright (C) 2006-2008 Nokia Corporation - * Tony Lindgren - * Jouni Hogander - * - * Copyright (C) 2005 Texas Instruments, Inc. - * Richard Woodruff - * - * Based on pm.c for omap1 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "cm.h" -#include "cm-regbits-34xx.h" -#include "prm-regbits-34xx.h" - -#include "prm.h" -#include "pm.h" - -struct power_state { - struct powerdomain *pwrdm; - u32 next_state; - u32 saved_state; - struct list_head node; -}; - -static LIST_HEAD(pwrst_list); - -static void (*_omap_sram_idle)(u32 *addr, int save_state); - -static struct powerdomain *mpu_pwrdm; - -/* PRCM Interrupt Handler for wakeups */ -static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) -{ - u32 wkst, irqstatus_mpu; - u32 fclk, iclk; - - /* WKUP */ - wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST); - if (wkst) { - iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); - fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); - cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN); - cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN); - prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST); - while (prm_read_mod_reg(WKUP_MOD, PM_WKST)) - cpu_relax(); - cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN); - cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN); - } - - /* CORE */ - wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1); - if (wkst) { - iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); - fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1); - cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1); - prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1); - while (prm_read_mod_reg(CORE_MOD, PM_WKST1)) - cpu_relax(); - cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1); - cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1); - } - wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3); - if (wkst) { - iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); - fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); - cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3); - cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3); - prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3); - while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3)) - cpu_relax(); - cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3); - cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3); - } - - /* PER */ - wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST); - if (wkst) { - iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); - fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); - cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN); - cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN); - prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST); - while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST)) - cpu_relax(); - cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN); - cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN); - } - - if (omap_rev() > OMAP3430_REV_ES1_0) { - /* USBHOST */ - wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST); - if (wkst) { - iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - CM_ICLKEN); - fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - CM_FCLKEN); - cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD, - CM_ICLKEN); - cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD, - CM_FCLKEN); - prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD, - PM_WKST); - while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - PM_WKST)) - cpu_relax(); - cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD, - CM_ICLKEN); - cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD, - CM_FCLKEN); - } - } - - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, - OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - prm_write_mod_reg(irqstatus_mpu, OCP_MOD, - OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - - while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)) - cpu_relax(); - - return IRQ_HANDLED; -} - -static void omap_sram_idle(void) -{ - /* Variable to tell what needs to be saved and restored - * in omap_sram_idle*/ - /* save_state = 0 => Nothing to save and restored */ - /* save_state = 1 => Only L1 and logic lost */ - /* save_state = 2 => Only L2 lost */ - /* save_state = 3 => L1, L2 and logic lost */ - int save_state = 0, mpu_next_state; - - if (!_omap_sram_idle) - return; - - mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); - switch (mpu_next_state) { - case PWRDM_POWER_RET: - /* No need to save context */ - save_state = 0; - break; - default: - /* Invalid state */ - printk(KERN_ERR "Invalid mpu state in sram_idle\n"); - return; - } - omap2_gpio_prepare_for_retention(); - omap_uart_prepare_idle(0); - omap_uart_prepare_idle(1); - omap_uart_prepare_idle(2); - - _omap_sram_idle(NULL, save_state); - cpu_init(); - - omap_uart_resume_idle(2); - omap_uart_resume_idle(1); - omap_uart_resume_idle(0); - omap2_gpio_resume_after_retention(); -} - -/* - * Check if functional clocks are enabled before entering - * sleep. This function could be behind CONFIG_PM_DEBUG - * when all drivers are configuring their sysconfig registers - * properly and using their clocks properly. - */ -static int omap3_fclks_active(void) -{ - u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, - fck_cam = 0, fck_per = 0, fck_usbhost = 0; - - fck_core1 = cm_read_mod_reg(CORE_MOD, - CM_FCLKEN1); - if (omap_rev() > OMAP3430_REV_ES1_0) { - fck_core3 = cm_read_mod_reg(CORE_MOD, - OMAP3430ES2_CM_FCLKEN3); - fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, - CM_FCLKEN); - fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - CM_FCLKEN); - } else - fck_sgx = cm_read_mod_reg(GFX_MOD, - OMAP3430ES2_CM_FCLKEN3); - fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, - CM_FCLKEN); - fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, - CM_FCLKEN); - fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, - CM_FCLKEN); - - /* Ignore UART clocks. These are handled by UART core (serial.c) */ - fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); - fck_per &= ~OMAP3430_EN_UART3; - - if (fck_core1 | fck_core3 | fck_sgx | fck_dss | - fck_cam | fck_per | fck_usbhost) - return 1; - return 0; -} - -static int omap3_can_sleep(void) -{ - if (!omap_uart_can_sleep()) - return 0; - if (omap3_fclks_active()) - return 0; - return 1; -} - -/* This sets pwrdm state (other than mpu & core. Currently only ON & - * RET are supported. Function is assuming that clkdm doesn't have - * hw_sup mode enabled. */ -static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) -{ - u32 cur_state; - int sleep_switch = 0; - int ret = 0; - - if (pwrdm == NULL || IS_ERR(pwrdm)) - return -EINVAL; - - while (!(pwrdm->pwrsts & (1 << state))) { - if (state == PWRDM_POWER_OFF) - return ret; - state--; - } - - cur_state = pwrdm_read_next_pwrst(pwrdm); - if (cur_state == state) - return ret; - - if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { - omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); - sleep_switch = 1; - pwrdm_wait_transition(pwrdm); - } - - ret = pwrdm_set_next_pwrst(pwrdm, state); - if (ret) { - printk(KERN_ERR "Unable to set state of powerdomain: %s\n", - pwrdm->name); - goto err; - } - - if (sleep_switch) { - omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); - pwrdm_wait_transition(pwrdm); - } - -err: - return ret; -} - -static void omap3_pm_idle(void) -{ - local_irq_disable(); - local_fiq_disable(); - - if (!omap3_can_sleep()) - goto out; - - if (omap_irq_pending()) - goto out; - - omap_sram_idle(); - -out: - local_fiq_enable(); - local_irq_enable(); -} - -static int omap3_pm_prepare(void) -{ - disable_hlt(); - return 0; -} - -static int omap3_pm_suspend(void) -{ - struct power_state *pwrst; - int state, ret = 0; - - /* Read current next_pwrsts */ - list_for_each_entry(pwrst, &pwrst_list, node) - pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); - /* Set ones wanted by suspend */ - list_for_each_entry(pwrst, &pwrst_list, node) { - if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) - goto restore; - if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) - goto restore; - } - - omap_uart_prepare_suspend(); - omap_sram_idle(); - -restore: - /* Restore next_pwrsts */ - list_for_each_entry(pwrst, &pwrst_list, node) { - set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); - state = pwrdm_read_prev_pwrst(pwrst->pwrdm); - if (state > pwrst->next_state) { - printk(KERN_INFO "Powerdomain (%s) didn't enter " - "target state %d\n", - pwrst->pwrdm->name, pwrst->next_state); - ret = -1; - } - } - if (ret) - printk(KERN_ERR "Could not enter target state in pm_suspend\n"); - else - printk(KERN_INFO "Successfully put all powerdomains " - "to target state\n"); - - return ret; -} - -static int omap3_pm_enter(suspend_state_t state) -{ - int ret = 0; - - switch (state) { - case PM_SUSPEND_STANDBY: - case PM_SUSPEND_MEM: - ret = omap3_pm_suspend(); - break; - default: - ret = -EINVAL; - } - - return ret; -} - -static void omap3_pm_finish(void) -{ - enable_hlt(); -} - -static struct platform_suspend_ops omap_pm_ops = { - .prepare = omap3_pm_prepare, - .enter = omap3_pm_enter, - .finish = omap3_pm_finish, - .valid = suspend_valid_only_mem, -}; - - -/** - * omap3_iva_idle(): ensure IVA is in idle so it can be put into - * retention - * - * In cases where IVA2 is activated by bootcode, it may prevent - * full-chip retention or off-mode because it is not idle. This - * function forces the IVA2 into idle state so it can go - * into retention/off and thus allow full-chip retention/off. - * - **/ -static void __init omap3_iva_idle(void) -{ - /* ensure IVA2 clock is disabled */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); - - /* if no clock activity, nothing else to do */ - if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & - OMAP3430_CLKACTIVITY_IVA2_MASK)) - return; - - /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2 | - OMAP3430_RST2_IVA2 | - OMAP3430_RST3_IVA2, - OMAP3430_IVA2_MOD, RM_RSTCTRL); - - /* Enable IVA2 clock */ - cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, - OMAP3430_IVA2_MOD, CM_FCLKEN); - - /* Set IVA2 boot mode to 'idle' */ - omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, - OMAP343X_CONTROL_IVA2_BOOTMOD); - - /* Un-reset IVA2 */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); - - /* Disable IVA2 clock */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); - - /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2 | - OMAP3430_RST2_IVA2 | - OMAP3430_RST3_IVA2, - OMAP3430_IVA2_MOD, RM_RSTCTRL); -} - -static void __init omap3_d2d_idle(void) -{ - u16 mask, padconf; - - /* In a stand alone OMAP3430 where there is not a stacked - * modem for the D2D Idle Ack and D2D MStandby must be pulled - * high. S CONTROL_PADCONF_SAD2D_IDLEACK and - * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ - mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ - padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); - padconf |= mask; - omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); - - padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); - padconf |= mask; - omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); - - /* reset modem */ - prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | - OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, - CORE_MOD, RM_RSTCTRL); - prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); -} - -static void __init prcm_setup_regs(void) -{ - /* XXX Reset all wkdeps. This should be done when initializing - * powerdomains */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); - prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); - if (omap_rev() > OMAP3430_REV_ES1_0) { - prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); - } else - prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); - - /* - * Enable interface clock autoidle for all modules. - * Note that in the long run this should be done by clockfw - */ - cm_write_mod_reg( - OMAP3430_AUTO_MODEM | - OMAP3430ES2_AUTO_MMC3 | - OMAP3430ES2_AUTO_ICR | - OMAP3430_AUTO_AES2 | - OMAP3430_AUTO_SHA12 | - OMAP3430_AUTO_DES2 | - OMAP3430_AUTO_MMC2 | - OMAP3430_AUTO_MMC1 | - OMAP3430_AUTO_MSPRO | - OMAP3430_AUTO_HDQ | - OMAP3430_AUTO_MCSPI4 | - OMAP3430_AUTO_MCSPI3 | - OMAP3430_AUTO_MCSPI2 | - OMAP3430_AUTO_MCSPI1 | - OMAP3430_AUTO_I2C3 | - OMAP3430_AUTO_I2C2 | - OMAP3430_AUTO_I2C1 | - OMAP3430_AUTO_UART2 | - OMAP3430_AUTO_UART1 | - OMAP3430_AUTO_GPT11 | - OMAP3430_AUTO_GPT10 | - OMAP3430_AUTO_MCBSP5 | - OMAP3430_AUTO_MCBSP1 | - OMAP3430ES1_AUTO_FAC | /* This is es1 only */ - OMAP3430_AUTO_MAILBOXES | - OMAP3430_AUTO_OMAPCTRL | - OMAP3430ES1_AUTO_FSHOSTUSB | - OMAP3430_AUTO_HSOTGUSB | - OMAP3430_AUTO_SAD2D | - OMAP3430_AUTO_SSI, - CORE_MOD, CM_AUTOIDLE1); - - cm_write_mod_reg( - OMAP3430_AUTO_PKA | - OMAP3430_AUTO_AES1 | - OMAP3430_AUTO_RNG | - OMAP3430_AUTO_SHA11 | - OMAP3430_AUTO_DES1, - CORE_MOD, CM_AUTOIDLE2); - - if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( - OMAP3430_AUTO_MAD2D | - OMAP3430ES2_AUTO_USBTLL, - CORE_MOD, CM_AUTOIDLE3); - } - - cm_write_mod_reg( - OMAP3430_AUTO_WDT2 | - OMAP3430_AUTO_WDT1 | - OMAP3430_AUTO_GPIO1 | - OMAP3430_AUTO_32KSYNC | - OMAP3430_AUTO_GPT12 | - OMAP3430_AUTO_GPT1 , - WKUP_MOD, CM_AUTOIDLE); - - cm_write_mod_reg( - OMAP3430_AUTO_DSS, - OMAP3430_DSS_MOD, - CM_AUTOIDLE); - - cm_write_mod_reg( - OMAP3430_AUTO_CAM, - OMAP3430_CAM_MOD, - CM_AUTOIDLE); - - cm_write_mod_reg( - OMAP3430_AUTO_GPIO6 | - OMAP3430_AUTO_GPIO5 | - OMAP3430_AUTO_GPIO4 | - OMAP3430_AUTO_GPIO3 | - OMAP3430_AUTO_GPIO2 | - OMAP3430_AUTO_WDT3 | - OMAP3430_AUTO_UART3 | - OMAP3430_AUTO_GPT9 | - OMAP3430_AUTO_GPT8 | - OMAP3430_AUTO_GPT7 | - OMAP3430_AUTO_GPT6 | - OMAP3430_AUTO_GPT5 | - OMAP3430_AUTO_GPT4 | - OMAP3430_AUTO_GPT3 | - OMAP3430_AUTO_GPT2 | - OMAP3430_AUTO_MCBSP4 | - OMAP3430_AUTO_MCBSP3 | - OMAP3430_AUTO_MCBSP2, - OMAP3430_PER_MOD, - CM_AUTOIDLE); - - if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( - OMAP3430ES2_AUTO_USBHOST, - OMAP3430ES2_USBHOST_MOD, - CM_AUTOIDLE); - } - - /* - * Set all plls to autoidle. This is needed until autoidle is - * enabled by clockfw - */ - cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, - OMAP3430_IVA2_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, - MPU_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | - (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), - PLL_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, - PLL_MOD, - CM_AUTOIDLE2); - - /* - * Enable control of expternal oscillator through - * sys_clkreq. In the long run clock framework should - * take care of this. - */ - prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, - 1 << OMAP_AUTOEXTCLKMODE_SHIFT, - OMAP3430_GR_MOD, - OMAP3_PRM_CLKSRC_CTRL_OFFSET); - - /* setup wakup source */ - prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | - OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, - WKUP_MOD, PM_WKEN); - /* No need to write EN_IO, that is always enabled */ - prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | - OMAP3430_EN_GPT12, - WKUP_MOD, OMAP3430_PM_MPUGRPSEL); - /* For some reason IO doesn't generate wakeup event even if - * it is selected to mpu wakeup goup */ - prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, - OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); - - /* Don't attach IVA interrupts */ - prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); - prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); - prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); - prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); - - /* Clear any pending 'reset' flags */ - prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); - - /* Clear any pending PRCM interrupts */ - prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - - omap3_iva_idle(); - omap3_d2d_idle(); -} - -static int __init pwrdms_setup(struct powerdomain *pwrdm) -{ - struct power_state *pwrst; - - if (!pwrdm->pwrsts) - return 0; - - pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL); - if (!pwrst) - return -ENOMEM; - pwrst->pwrdm = pwrdm; - pwrst->next_state = PWRDM_POWER_RET; - list_add(&pwrst->node, &pwrst_list); - - if (pwrdm_has_hdwr_sar(pwrdm)) - pwrdm_enable_hdwr_sar(pwrdm); - - return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); -} - -/* - * Enable hw supervised mode for all clockdomains if it's - * supported. Initiate sleep transition for other clockdomains, if - * they are not used - */ -static int __init clkdms_setup(struct clockdomain *clkdm) -{ - if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) - omap2_clkdm_allow_idle(clkdm); - else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && - atomic_read(&clkdm->usecount) == 0) - omap2_clkdm_sleep(clkdm); - return 0; -} - -int __init omap3_pm_init(void) -{ - struct power_state *pwrst, *tmp; - int ret; - - if (!cpu_is_omap34xx()) - return -ENODEV; - - printk(KERN_ERR "Power Management for TI OMAP3.\n"); - - /* XXX prcm_setup_regs needs to be before enabling hw - * supervised mode for powerdomains */ - prcm_setup_regs(); - - ret = request_irq(INT_34XX_PRCM_MPU_IRQ, - (irq_handler_t)prcm_interrupt_handler, - IRQF_DISABLED, "prcm", NULL); - if (ret) { - printk(KERN_ERR "request_irq failed to register for 0x%x\n", - INT_34XX_PRCM_MPU_IRQ); - goto err1; - } - - ret = pwrdm_for_each(pwrdms_setup); - if (ret) { - printk(KERN_ERR "Failed to setup powerdomains\n"); - goto err2; - } - - (void) clkdm_for_each(clkdms_setup); - - mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); - if (mpu_pwrdm == NULL) { - printk(KERN_ERR "Failed to get mpu_pwrdm\n"); - goto err2; - } - - _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, - omap34xx_cpu_suspend_sz); - - suspend_set_ops(&omap_pm_ops); - - pm_idle = omap3_pm_idle; - -err1: - return ret; -err2: - free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); - list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { - list_del(&pwrst->node); - kfree(pwrst); - } - return ret; -} - -late_initcall(omap3_pm_init); diff --git a/trunk/arch/arm/mach-omap2/prcm-common.h b/trunk/arch/arm/mach-omap2/prcm-common.h index cb1ae84e0925..812d50ee495d 100644 --- a/trunk/arch/arm/mach-omap2/prcm-common.h +++ b/trunk/arch/arm/mach-omap2/prcm-common.h @@ -276,8 +276,6 @@ /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ #define OMAP3430_EN_GPIO1 (1 << 3) #define OMAP3430_EN_GPIO1_SHIFT 3 -#define OMAP3430_EN_GPT12 (1 << 1) -#define OMAP3430_EN_GPT12_SHIFT 1 #define OMAP3430_EN_GPT1 (1 << 0) #define OMAP3430_EN_GPT1_SHIFT 0 diff --git a/trunk/arch/arm/mach-omap2/prm.h b/trunk/arch/arm/mach-omap2/prm.h index 9937e2814696..826d326b8062 100644 --- a/trunk/arch/arm/mach-omap2/prm.h +++ b/trunk/arch/arm/mach-omap2/prm.h @@ -16,12 +16,17 @@ #include "prcm-common.h" +#ifndef __ASSEMBLER__ +#define OMAP_PRM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) +#else #define OMAP2420_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) #define OMAP2430_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) #define OMAP34XX_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) +#endif /* * Architecture-specific global PRM registers @@ -33,132 +38,80 @@ * */ -#define OMAP2_PRCM_REVISION_OFFSET 0x0000 -#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) -#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 -#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) - -#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c -#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 -#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) -#define OMAP2_PRCM_VOLTST_OFFSET 0x0054 -#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) -#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 -#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) -#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) -#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 -#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 -#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) -#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 -#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) -#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 -#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) -#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 -#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) -#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 -#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) - -#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) -#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) - -#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) -#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) -#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) -#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) -#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) -#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) -#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) -#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) -#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) - -#define OMAP3_PRM_REVISION_OFFSET 0x0004 -#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) -#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 -#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) - -#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c -#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) - - -#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 -#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) -#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 -#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) -#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 -#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) -#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c -#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) -#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 -#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) -#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 -#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) -#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 -#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) -#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c -#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) -#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 -#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) -#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 -#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) -#define OMAP3_PRM_RSTST_OFFSET 0x0058 -#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) -#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 -#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) -#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 -#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) -#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 -#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) -#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 -#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) -#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 -#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) -#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 -#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) -#define OMAP3_PRM_POLCTRL_OFFSET 0x009c -#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) -#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 -#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) -#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 -#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) -#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 -#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) -#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 -#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) -#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc -#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) -#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 -#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) -#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 -#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) -#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 -#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) -#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 -#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) -#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 -#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) -#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc -#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) -#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 -#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) -#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 -#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) - -#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 -#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) -#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) +/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */ +#define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050 +#define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080 + +/* 242x GR_MOD registers, use these only for assembly code */ +#define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_VOLTCTRL_OFFSET) +#define OMAP242X_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) + +/* 243x GR_MOD registers, use these only for assembly code */ +#define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_VOLTCTRL_OFFSET) +#define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) + +/* These will disappear */ +#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098) + +#define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004) +#define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014) + +#define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) + + +#define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) +#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) +#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) +#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) +#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) +#define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) +#define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) +#define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) +#define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) +#define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) +#define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) +#define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) +#define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) +#define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) +#define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) +#define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) +#define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) +#define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) +#define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) +#define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) +#define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) +#define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) +#define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) +#define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) +#define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) +#define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) +#define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) +#define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) +#define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) +#define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) +#define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) + +#define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) +#define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) /* * Module specific PRM registers from PRM_BASE + domain offset @@ -203,11 +156,9 @@ #define OMAP3430_PM_MPUGRPSEL 0x00a4 #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL -#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 #define OMAP3430_PM_IVAGRPSEL 0x00a8 #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL -#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 #define OMAP3430_PM_PREPWSTST 0x00e8 diff --git a/trunk/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/trunk/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h deleted file mode 100644 index 02e1c2d4705f..000000000000 --- a/trunk/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * SDRC register values for the Micron MT46H32M32LF-6 - * - * Copyright (C) 2008 Texas Instruments, Inc. - * Copyright (C) 2008-2009 Nokia Corporation - * - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF -#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF - -#include - -/* Micron MT46H32M32LF-6 */ -/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */ -static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = { - [0] = { - .rate = 166000000, - .actim_ctrla = 0x9a9db4c6, - .actim_ctrlb = 0x00011217, - .rfr_ctrl = 0x0004dc01, - .mr = 0x00000032, - }, - [1] = { - .rate = 165941176, - .actim_ctrla = 0x9a9db4c6, - .actim_ctrlb = 0x00011217, - .rfr_ctrl = 0x0004dc01, - .mr = 0x00000032, - }, - [2] = { - .rate = 83000000, - .actim_ctrla = 0x51512283, - .actim_ctrlb = 0x0001120c, - .rfr_ctrl = 0x00025501, - .mr = 0x00000032, - }, - [3] = { - .rate = 82970588, - .actim_ctrla = 0x51512283, - .actim_ctrlb = 0x0001120c, - .rfr_ctrl = 0x00025501, - .mr = 0x00000032, - }, - [4] = { - .rate = 0 - }, -}; - -#endif diff --git a/trunk/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/trunk/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h deleted file mode 100644 index 3751d293cb1f..000000000000 --- a/trunk/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * SDRC register values for the Qimonda HYB18M512160AF-6 - * - * Copyright (C) 2008-2009 Texas Instruments, Inc. - * Copyright (C) 2008-2009 Nokia Corporation - * - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 -#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 - -#include - -/* Qimonda HYB18M512160AF-6 */ -static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = { - [0] = { - .rate = 166000000, - .actim_ctrla = 0x629db4c6, - .actim_ctrlb = 0x00012214, - .rfr_ctrl = 0x0004dc01, - .mr = 0x00000032, - }, - [1] = { - .rate = 165941176, - .actim_ctrla = 0x629db4c6, - .actim_ctrlb = 0x00012214, - .rfr_ctrl = 0x0004dc01, - .mr = 0x00000032, - }, - [2] = { - .rate = 83000000, - .actim_ctrla = 0x31512283, - .actim_ctrlb = 0x0001220a, - .rfr_ctrl = 0x00025501, - .mr = 0x00000022, - }, - [3] = { - .rate = 82970588, - .actim_ctrla = 0x31512283, - .actim_ctrlb = 0x0001220a, - .rfr_ctrl = 0x00025501, - .mr = 0x00000022, - }, - [4] = { - .rate = 0 - }, -}; - -#endif diff --git a/trunk/arch/arm/mach-omap2/sdrc.c b/trunk/arch/arm/mach-omap2/sdrc.c index 2045441e8385..2a30060cb4b7 100644 --- a/trunk/arch/arm/mach-omap2/sdrc.c +++ b/trunk/arch/arm/mach-omap2/sdrc.c @@ -37,10 +37,6 @@ static struct omap_sdrc_params *sdrc_init_params; void __iomem *omap2_sdrc_base; void __iomem *omap2_sms_base; -/* SDRC_POWER register bits */ -#define SDRC_POWER_EXTCLKDIS_SHIFT 3 -#define SDRC_POWER_PWDENA_SHIFT 2 -#define SDRC_POWER_PAGEPOLICY_SHIFT 0 /** * omap2_sdrc_get_params - return SDRC register values for a given clock rate @@ -60,12 +56,9 @@ struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r) { struct omap_sdrc_params *sp; - if (!sdrc_init_params) - return NULL; - sp = sdrc_init_params; - while (sp->rate && sp->rate != r) + while (sp->rate != r) sp++; if (!sp->rate) @@ -81,14 +74,7 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) omap2_sms_base = omap2_globals->sms; } -/** - * omap2_sdrc_init - initialize SMS, SDRC devices on boot - * @sp: pointer to a null-terminated list of struct omap_sdrc_params - * - * Turn on smart idle modes for SDRAM scheduler and controller. - * Program a known-good configuration for the SDRC to deal with buggy - * bootloaders. - */ +/* turn on smart idle modes for SDRAM scheduler and controller */ void __init omap2_sdrc_init(struct omap_sdrc_params *sp) { u32 l; @@ -104,10 +90,4 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp) sdrc_write_reg(l, SDRC_SYSCONFIG); sdrc_init_params = sp; - - /* XXX Enable SRFRONIDLEREQ here also? */ - l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | - (1 << SDRC_POWER_PWDENA_SHIFT) | - (1 << SDRC_POWER_PAGEPOLICY_SHIFT); - sdrc_write_reg(l, SDRC_POWER); } diff --git a/trunk/arch/arm/mach-omap2/sdrc2xxx.c b/trunk/arch/arm/mach-omap2/sdrc2xxx.c index feaec7eaf6bd..0afdad5ae9fb 100644 --- a/trunk/arch/arm/mach-omap2/sdrc2xxx.c +++ b/trunk/arch/arm/mach-omap2/sdrc2xxx.c @@ -99,10 +99,7 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) m_type = omap2xxx_sdrc_get_type(); local_irq_save(flags); - if (cpu_is_omap2420()) - __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); - else - __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP); + __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); curr_perf_level = level; local_irq_restore(flags); diff --git a/trunk/arch/arm/mach-omap2/serial.c b/trunk/arch/arm/mach-omap2/serial.c index b094c15bfe47..4dcf39c285b9 100644 --- a/trunk/arch/arm/mach-omap2/serial.c +++ b/trunk/arch/arm/mach-omap2/serial.c @@ -6,13 +6,8 @@ * Copyright (C) 2005-2008 Nokia Corporation * Author: Paul Mundt * - * Major rework for PM support by Kevin Hilman - * * Based off of arch/arm/mach-omap/omap1/serial.c * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar #include -#include -#include - -#include "prm.h" -#include "pm.h" -#include "prm-regbits-34xx.h" - -#define UART_OMAP_WER 0x17 /* Wake-up enable register */ - -#define DEFAULT_TIMEOUT (5 * HZ) -struct omap_uart_state { - int num; - int can_sleep; - struct timer_list timer; - u32 timeout; - - void __iomem *wk_st; - void __iomem *wk_en; - u32 wk_mask; - u32 padconf; - - struct clk *ick; - struct clk *fck; - int clocked; - - struct plat_serial8250_port *p; - struct list_head node; - -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) - int context_valid; - - /* Registers to be saved/restored for OFF-mode */ - u16 dll; - u16 dlh; - u16 ier; - u16 sysc; - u16 scr; - u16 wer; -#endif -}; - -static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS]; -static LIST_HEAD(uart_list); +static struct clk *uart_ick[OMAP_MAX_NR_PORTS]; +static struct clk *uart_fck[OMAP_MAX_NR_PORTS]; static struct plat_serial8250_port serial_platform_data[] = { { @@ -120,369 +74,33 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, * properly. Note that the TX watermark initialization may not be needed * once the 8250.c watermark handling code is merged. */ -static inline void __init omap_uart_reset(struct omap_uart_state *uart) +static inline void __init omap_serial_reset(struct plat_serial8250_port *p) { - struct plat_serial8250_port *p = uart->p; - serial_write_reg(p, UART_OMAP_MDR1, 0x07); serial_write_reg(p, UART_OMAP_SCR, 0x08); serial_write_reg(p, UART_OMAP_MDR1, 0x00); serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); } -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) - -static int enable_off_mode; /* to be removed by full off-mode patches */ - -static void omap_uart_save_context(struct omap_uart_state *uart) -{ - u16 lcr = 0; - struct plat_serial8250_port *p = uart->p; - - if (!enable_off_mode) - return; - - lcr = serial_read_reg(p, UART_LCR); - serial_write_reg(p, UART_LCR, 0xBF); - uart->dll = serial_read_reg(p, UART_DLL); - uart->dlh = serial_read_reg(p, UART_DLM); - serial_write_reg(p, UART_LCR, lcr); - uart->ier = serial_read_reg(p, UART_IER); - uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); - uart->scr = serial_read_reg(p, UART_OMAP_SCR); - uart->wer = serial_read_reg(p, UART_OMAP_WER); - - uart->context_valid = 1; -} - -static void omap_uart_restore_context(struct omap_uart_state *uart) +void omap_serial_enable_clocks(int enable) { - u16 efr = 0; - struct plat_serial8250_port *p = uart->p; - - if (!enable_off_mode) - return; - - if (!uart->context_valid) - return; - - uart->context_valid = 0; - - serial_write_reg(p, UART_OMAP_MDR1, 0x7); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - efr = serial_read_reg(p, UART_EFR); - serial_write_reg(p, UART_EFR, UART_EFR_ECB); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, 0x0); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_DLL, uart->dll); - serial_write_reg(p, UART_DLM, uart->dlh); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, uart->ier); - serial_write_reg(p, UART_FCR, 0xA1); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_EFR, efr); - serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); - serial_write_reg(p, UART_OMAP_SCR, uart->scr); - serial_write_reg(p, UART_OMAP_WER, uart->wer); - serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); - serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ -} -#else -static inline void omap_uart_save_context(struct omap_uart_state *uart) {} -static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} -#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ - -static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) -{ - if (uart->clocked) - return; - - clk_enable(uart->ick); - clk_enable(uart->fck); - uart->clocked = 1; - omap_uart_restore_context(uart); -} - -#ifdef CONFIG_PM - -static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) -{ - if (!uart->clocked) - return; - - omap_uart_save_context(uart); - uart->clocked = 0; - clk_disable(uart->ick); - clk_disable(uart->fck); -} - -static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, - int enable) -{ - struct plat_serial8250_port *p = uart->p; - u16 sysc; - - sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; - if (enable) - sysc |= 0x2 << 3; - else - sysc |= 0x1 << 3; - - serial_write_reg(p, UART_OMAP_SYSC, sysc); -} - -static void omap_uart_block_sleep(struct omap_uart_state *uart) -{ - omap_uart_enable_clocks(uart); - - omap_uart_smart_idle_enable(uart, 0); - uart->can_sleep = 0; - if (uart->timeout) - mod_timer(&uart->timer, jiffies + uart->timeout); - else - del_timer(&uart->timer); -} - -static void omap_uart_allow_sleep(struct omap_uart_state *uart) -{ - if (!uart->clocked) - return; - - omap_uart_smart_idle_enable(uart, 1); - uart->can_sleep = 1; - del_timer(&uart->timer); -} - -static void omap_uart_idle_timer(unsigned long data) -{ - struct omap_uart_state *uart = (struct omap_uart_state *)data; - - omap_uart_allow_sleep(uart); -} - -void omap_uart_prepare_idle(int num) -{ - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - if (num == uart->num && uart->can_sleep) { - omap_uart_disable_clocks(uart); - return; - } - } -} - -void omap_uart_resume_idle(int num) -{ - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - if (num == uart->num) { - omap_uart_enable_clocks(uart); - - /* Check for IO pad wakeup */ - if (cpu_is_omap34xx() && uart->padconf) { - u16 p = omap_ctrl_readw(uart->padconf); - - if (p & OMAP3_PADCONF_WAKEUPEVENT0) - omap_uart_block_sleep(uart); + int i; + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { + if (uart_ick[i] && uart_fck[i]) { + if (enable) { + clk_enable(uart_ick[i]); + clk_enable(uart_fck[i]); + } else { + clk_disable(uart_ick[i]); + clk_disable(uart_fck[i]); } - - /* Check for normal UART wakeup */ - if (__raw_readl(uart->wk_st) & uart->wk_mask) - omap_uart_block_sleep(uart); - - return; } } } -void omap_uart_prepare_suspend(void) -{ - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - omap_uart_allow_sleep(uart); - } -} - -int omap_uart_can_sleep(void) -{ - struct omap_uart_state *uart; - int can_sleep = 1; - - list_for_each_entry(uart, &uart_list, node) { - if (!uart->clocked) - continue; - - if (!uart->can_sleep) { - can_sleep = 0; - continue; - } - - /* This UART can now safely sleep. */ - omap_uart_allow_sleep(uart); - } - - return can_sleep; -} - -/** - * omap_uart_interrupt() - * - * This handler is used only to detect that *any* UART interrupt has - * occurred. It does _nothing_ to handle the interrupt. Rather, - * any UART interrupt will trigger the inactivity timer so the - * UART will not idle or sleep for its timeout period. - * - **/ -static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) -{ - struct omap_uart_state *uart = dev_id; - - omap_uart_block_sleep(uart); - - return IRQ_NONE; -} - -static u32 sleep_timeout = DEFAULT_TIMEOUT; - -static void omap_uart_idle_init(struct omap_uart_state *uart) -{ - u32 v; - struct plat_serial8250_port *p = uart->p; - int ret; - - uart->can_sleep = 0; - uart->timeout = sleep_timeout; - setup_timer(&uart->timer, omap_uart_idle_timer, - (unsigned long) uart); - mod_timer(&uart->timer, jiffies + uart->timeout); - omap_uart_smart_idle_enable(uart, 0); - - if (cpu_is_omap34xx()) { - u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; - u32 wk_mask = 0; - u32 padconf = 0; - - uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); - uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); - switch (uart->num) { - case 0: - wk_mask = OMAP3430_ST_UART1_MASK; - padconf = 0x182; - break; - case 1: - wk_mask = OMAP3430_ST_UART2_MASK; - padconf = 0x17a; - break; - case 2: - wk_mask = OMAP3430_ST_UART3_MASK; - padconf = 0x19e; - break; - } - uart->wk_mask = wk_mask; - uart->padconf = padconf; - } else if (cpu_is_omap24xx()) { - u32 wk_mask = 0; - - if (cpu_is_omap2430()) { - uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); - uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); - } else if (cpu_is_omap2420()) { - uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); - uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1); - } - switch (uart->num) { - case 0: - wk_mask = OMAP24XX_ST_UART1_MASK; - break; - case 1: - wk_mask = OMAP24XX_ST_UART2_MASK; - break; - case 2: - wk_mask = OMAP24XX_ST_UART3_MASK; - break; - } - uart->wk_mask = wk_mask; - } else { - uart->wk_en = 0; - uart->wk_st = 0; - uart->wk_mask = 0; - uart->padconf = 0; - } - - /* Set wake-enable bit */ - if (uart->wk_en && uart->wk_mask) { - v = __raw_readl(uart->wk_en); - v |= uart->wk_mask; - __raw_writel(v, uart->wk_en); - } - - /* Ensure IOPAD wake-enables are set */ - if (cpu_is_omap34xx() && uart->padconf) { - u16 v; - - v = omap_ctrl_readw(uart->padconf); - v |= OMAP3_PADCONF_WAKEUPENABLE0; - omap_ctrl_writew(v, uart->padconf); - } - - p->flags |= UPF_SHARE_IRQ; - ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, - "serial idle", (void *)uart); - WARN_ON(ret); -} - -static ssize_t sleep_timeout_show(struct kobject *kobj, - struct kobj_attribute *attr, - char *buf) -{ - return sprintf(buf, "%u\n", sleep_timeout / HZ); -} - -static ssize_t sleep_timeout_store(struct kobject *kobj, - struct kobj_attribute *attr, - const char *buf, size_t n) -{ - struct omap_uart_state *uart; - unsigned int value; - - if (sscanf(buf, "%u", &value) != 1) { - printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); - return -EINVAL; - } - sleep_timeout = value * HZ; - list_for_each_entry(uart, &uart_list, node) { - uart->timeout = sleep_timeout; - if (uart->timeout) - mod_timer(&uart->timer, jiffies + uart->timeout); - else - /* A zero value means disable timeout feature */ - omap_uart_block_sleep(uart); - } - return n; -} - -static struct kobj_attribute sleep_timeout_attr = - __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); - -#else -static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} -#endif /* CONFIG_PM */ - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, -}; - void __init omap_serial_init(void) { - int i, err; + int i; const struct omap_uart_config *info; char name[16]; @@ -496,14 +114,9 @@ void __init omap_serial_init(void) if (info == NULL) return; - if (cpu_is_omap44xx()) { - for (i = 0; i < OMAP_MAX_NR_PORTS; i++) - serial_platform_data[i].irq += 32; - } for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { struct plat_serial8250_port *p = serial_platform_data + i; - struct omap_uart_state *uart = &omap_uart[i]; if (!(info->enabled_uarts & (1 << i))) { p->membase = NULL; @@ -512,39 +125,35 @@ void __init omap_serial_init(void) } sprintf(name, "uart%d_ick", i+1); - uart->ick = clk_get(NULL, name); - if (IS_ERR(uart->ick)) { + uart_ick[i] = clk_get(NULL, name); + if (IS_ERR(uart_ick[i])) { printk(KERN_ERR "Could not get uart%d_ick\n", i+1); - uart->ick = NULL; - } + uart_ick[i] = NULL; + } else + clk_enable(uart_ick[i]); sprintf(name, "uart%d_fck", i+1); - uart->fck = clk_get(NULL, name); - if (IS_ERR(uart->fck)) { + uart_fck[i] = clk_get(NULL, name); + if (IS_ERR(uart_fck[i])) { printk(KERN_ERR "Could not get uart%d_fck\n", i+1); - uart->fck = NULL; - } + uart_fck[i] = NULL; + } else + clk_enable(uart_fck[i]); - if (!uart->ick || !uart->fck) - continue; - - uart->num = i; - p->private_data = uart; - uart->p = p; - list_add(&uart->node, &uart_list); - - omap_uart_enable_clocks(uart); - omap_uart_reset(uart); - omap_uart_idle_init(uart); + omap_serial_reset(p); } +} - err = platform_device_register(&serial_device); - -#ifdef CONFIG_PM - if (!err) - err = sysfs_create_file(&serial_device.dev.kobj, - &sleep_timeout_attr.attr); -#endif +static struct platform_device serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data, + }, +}; +static int __init omap_init(void) +{ + return platform_device_register(&serial_device); } - +arch_initcall(omap_init); diff --git a/trunk/arch/arm/mach-omap2/sleep24xx.S b/trunk/arch/arm/mach-omap2/sleep24xx.S index 130aadbfa083..bf9e96105e11 100644 --- a/trunk/arch/arm/mach-omap2/sleep24xx.S +++ b/trunk/arch/arm/mach-omap2/sleep24xx.S @@ -28,6 +28,7 @@ #include #include #include +#include #include diff --git a/trunk/arch/arm/mach-omap2/sleep34xx.S b/trunk/arch/arm/mach-omap2/sleep34xx.S deleted file mode 100644 index e5e2553e79a6..000000000000 --- a/trunk/arch/arm/mach-omap2/sleep34xx.S +++ /dev/null @@ -1,436 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/sleep.S - * - * (C) Copyright 2007 - * Texas Instruments - * Karthik Dasu - * - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include - -#include "prm.h" -#include "sdrc.h" - -#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ - OMAP3430_PM_PREPWSTST) -#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ - OMAP3430_PM_PREPWSTST) -#define PM_PWSTCTRL_MPU_P OMAP34XX_PRM_REGADDR(MPU_MOD, PM_PWSTCTRL) -#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is - * available */ -#define SCRATCHPAD_BASE_P OMAP343X_CTRL_REGADDR(\ - OMAP343X_CONTROL_MEM_WKUP +\ - SCRATCHPAD_MEM_OFFS) -#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) - - .text -/* Function call to get the restore pointer for resume from OFF */ -ENTRY(get_restore_pointer) - stmfd sp!, {lr} @ save registers on stack - adr r0, restore - ldmfd sp!, {pc} @ restore regs and return -ENTRY(get_restore_pointer_sz) - .word . - get_restore_pointer_sz -/* - * Forces OMAP into idle state - * - * omap34xx_suspend() - This bit of code just executes the WFI - * for normal idles. - * - * Note: This code get's copied to internal SRAM at boot. When the OMAP - * wakes up it continues execution at the point it went to sleep. - */ -ENTRY(omap34xx_cpu_suspend) - stmfd sp!, {r0-r12, lr} @ save registers on stack -loop: - /*b loop*/ @Enable to debug by stepping through code - /* r0 contains restore pointer in sdram */ - /* r1 contains information about saving context */ - ldr r4, sdrc_power @ read the SDRC_POWER register - ldr r5, [r4] @ read the contents of SDRC_POWER - orr r5, r5, #0x40 @ enable self refresh on idle req - str r5, [r4] @ write back to SDRC_POWER register - - cmp r1, #0x0 - /* If context save is required, do that and execute wfi */ - bne save_context_wfi - /* Data memory barrier and Data sync barrier */ - mov r1, #0 - mcr p15, 0, r1, c7, c10, 4 - mcr p15, 0, r1, c7, c10, 5 - - wfi @ wait for interrupt - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - bl i_dll_wait - - ldmfd sp!, {r0-r12, pc} @ restore regs and return -restore: - /* b restore*/ @ Enable to debug restore code - /* Check what was the reason for mpu reset and store the reason in r9*/ - /* 1 - Only L1 and logic lost */ - /* 2 - Only L2 lost - In this case, we wont be here */ - /* 3 - Both L1 and L2 lost */ - ldr r1, pm_pwstctrl_mpu - ldr r2, [r1] - and r2, r2, #0x3 - cmp r2, #0x0 @ Check if target power state was OFF or RET - moveq r9, #0x3 @ MPU OFF => L1 and L2 lost - movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation - bne logic_l1_restore - /* Execute smi to invalidate L2 cache */ - mov r12, #0x1 @ set up to invalide L2 -smi: .word 0xE1600070 @ Call SMI monitor (smieq) -logic_l1_restore: - mov r1, #0 - /* Invalidate all instruction caches to PoU - * and flush branch target cache */ - mcr p15, 0, r1, c7, c5, 0 - - ldr r4, scratchpad_base - ldr r3, [r4,#0xBC] - ldmia r3!, {r4-r6} - mov sp, r4 - msr spsr_cxsf, r5 - mov lr, r6 - - ldmia r3!, {r4-r9} - /* Coprocessor access Control Register */ - mcr p15, 0, r4, c1, c0, 2 - - /* TTBR0 */ - MCR p15, 0, r5, c2, c0, 0 - /* TTBR1 */ - MCR p15, 0, r6, c2, c0, 1 - /* Translation table base control register */ - MCR p15, 0, r7, c2, c0, 2 - /*domain access Control Register */ - MCR p15, 0, r8, c3, c0, 0 - /* data fault status Register */ - MCR p15, 0, r9, c5, c0, 0 - - ldmia r3!,{r4-r8} - /* instruction fault status Register */ - MCR p15, 0, r4, c5, c0, 1 - /*Data Auxiliary Fault Status Register */ - MCR p15, 0, r5, c5, c1, 0 - /*Instruction Auxiliary Fault Status Register*/ - MCR p15, 0, r6, c5, c1, 1 - /*Data Fault Address Register */ - MCR p15, 0, r7, c6, c0, 0 - /*Instruction Fault Address Register*/ - MCR p15, 0, r8, c6, c0, 2 - ldmia r3!,{r4-r7} - - /* user r/w thread and process ID */ - MCR p15, 0, r4, c13, c0, 2 - /* user ro thread and process ID */ - MCR p15, 0, r5, c13, c0, 3 - /*Privileged only thread and process ID */ - MCR p15, 0, r6, c13, c0, 4 - /* cache size selection */ - MCR p15, 2, r7, c0, c0, 0 - ldmia r3!,{r4-r8} - /* Data TLB lockdown registers */ - MCR p15, 0, r4, c10, c0, 0 - /* Instruction TLB lockdown registers */ - MCR p15, 0, r5, c10, c0, 1 - /* Secure or Nonsecure Vector Base Address */ - MCR p15, 0, r6, c12, c0, 0 - /* FCSE PID */ - MCR p15, 0, r7, c13, c0, 0 - /* Context PID */ - MCR p15, 0, r8, c13, c0, 1 - - ldmia r3!,{r4-r5} - /* primary memory remap register */ - MCR p15, 0, r4, c10, c2, 0 - /*normal memory remap register */ - MCR p15, 0, r5, c10, c2, 1 - - /* Restore cpsr */ - ldmia r3!,{r4} /*load CPSR from SDRAM*/ - msr cpsr, r4 /*store cpsr */ - - /* Enabling MMU here */ - mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ - /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ - and r7, #0x7 - cmp r7, #0x0 - beq usettbr0 -ttbr_error: - /* More work needs to be done to support N[0:2] value other than 0 - * So looping here so that the error can be detected - */ - b ttbr_error -usettbr0: - mrc p15, 0, r2, c2, c0, 0 - ldr r5, ttbrbit_mask - and r2, r5 - mov r4, pc - ldr r5, table_index_mask - and r4, r5 /* r4 = 31 to 20 bits of pc */ - /* Extract the value to be written to table entry */ - ldr r1, table_entry - add r1, r1, r4 /* r1 has value to be written to table entry*/ - /* Getting the address of table entry to modify */ - lsr r4, #18 - add r2, r4 /* r2 has the location which needs to be modified */ - /* Storing previous entry of location being modified */ - ldr r5, scratchpad_base - ldr r4, [r2] - str r4, [r5, #0xC0] - /* Modify the table entry */ - str r1, [r2] - /* Storing address of entry being modified - * - will be restored after enabling MMU */ - ldr r5, scratchpad_base - str r2, [r5, #0xC4] - - mov r0, #0 - mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer - mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array - mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB - mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB - /* Restore control register but dont enable caches here*/ - /* Caches will be enabled after restoring MMU table entry */ - ldmia r3!, {r4} - /* Store previous value of control register in scratchpad */ - str r4, [r5, #0xC8] - ldr r2, cache_pred_disable_mask - and r4, r2 - mcr p15, 0, r4, c1, c0, 0 - - ldmfd sp!, {r0-r12, pc} @ restore regs and return -save_context_wfi: - /*b save_context_wfi*/ @ enable to debug save code - mov r8, r0 /* Store SDRAM address in r8 */ - /* Check what that target sleep state is:stored in r1*/ - /* 1 - Only L1 and logic lost */ - /* 2 - Only L2 lost */ - /* 3 - Both L1 and L2 lost */ - cmp r1, #0x2 /* Only L2 lost */ - beq clean_l2 - cmp r1, #0x1 /* L2 retained */ - /* r9 stores whether to clean L2 or not*/ - moveq r9, #0x0 /* Dont Clean L2 */ - movne r9, #0x1 /* Clean L2 */ -l1_logic_lost: - /* Store sp and spsr to SDRAM */ - mov r4, sp - mrs r5, spsr - mov r6, lr - stmia r8!, {r4-r6} - /* Save all ARM registers */ - /* Coprocessor access control register */ - mrc p15, 0, r6, c1, c0, 2 - stmia r8!, {r6} - /* TTBR0, TTBR1 and Translation table base control */ - mrc p15, 0, r4, c2, c0, 0 - mrc p15, 0, r5, c2, c0, 1 - mrc p15, 0, r6, c2, c0, 2 - stmia r8!, {r4-r6} - /* Domain access control register, data fault status register, - and instruction fault status register */ - mrc p15, 0, r4, c3, c0, 0 - mrc p15, 0, r5, c5, c0, 0 - mrc p15, 0, r6, c5, c0, 1 - stmia r8!, {r4-r6} - /* Data aux fault status register, instruction aux fault status, - datat fault address register and instruction fault address register*/ - mrc p15, 0, r4, c5, c1, 0 - mrc p15, 0, r5, c5, c1, 1 - mrc p15, 0, r6, c6, c0, 0 - mrc p15, 0, r7, c6, c0, 2 - stmia r8!, {r4-r7} - /* user r/w thread and process ID, user r/o thread and process ID, - priv only thread and process ID, cache size selection */ - mrc p15, 0, r4, c13, c0, 2 - mrc p15, 0, r5, c13, c0, 3 - mrc p15, 0, r6, c13, c0, 4 - mrc p15, 2, r7, c0, c0, 0 - stmia r8!, {r4-r7} - /* Data TLB lockdown, instruction TLB lockdown registers */ - mrc p15, 0, r5, c10, c0, 0 - mrc p15, 0, r6, c10, c0, 1 - stmia r8!, {r5-r6} - /* Secure or non secure vector base address, FCSE PID, Context PID*/ - mrc p15, 0, r4, c12, c0, 0 - mrc p15, 0, r5, c13, c0, 0 - mrc p15, 0, r6, c13, c0, 1 - stmia r8!, {r4-r6} - /* Primary remap, normal remap registers */ - mrc p15, 0, r4, c10, c2, 0 - mrc p15, 0, r5, c10, c2, 1 - stmia r8!,{r4-r5} - - /* Store current cpsr*/ - mrs r2, cpsr - stmia r8!, {r2} - - mrc p15, 0, r4, c1, c0, 0 - /* save control register */ - stmia r8!, {r4} -clean_caches: - /* Clean Data or unified cache to POU*/ - /* How to invalidate only L1 cache???? - #FIX_ME# */ - /* mcr p15, 0, r11, c7, c11, 1 */ - cmp r9, #1 /* Check whether L2 inval is required or not*/ - bne skip_l2_inval -clean_l2: - /* read clidr */ - mrc p15, 1, r0, c0, c0, 1 - /* extract loc from clidr */ - ands r3, r0, #0x7000000 - /* left align loc bit field */ - mov r3, r3, lsr #23 - /* if loc is 0, then no need to clean */ - beq finished - /* start clean at cache level 0 */ - mov r10, #0 -loop1: - /* work out 3x current cache level */ - add r2, r10, r10, lsr #1 - /* extract cache type bits from clidr*/ - mov r1, r0, lsr r2 - /* mask of the bits for current cache only */ - and r1, r1, #7 - /* see what cache we have at this level */ - cmp r1, #2 - /* skip if no cache, or just i-cache */ - blt skip - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - /* isb to sych the new cssr&csidr */ - isb - /* read the new csidr */ - mrc p15, 1, r1, c0, c0, 0 - /* extract the length of the cache lines */ - and r2, r1, #7 - /* add 4 (line length offset) */ - add r2, r2, #4 - ldr r4, assoc_mask - /* find maximum number on the way size */ - ands r4, r4, r1, lsr #3 - /* find bit position of way size increment */ - clz r5, r4 - ldr r7, numset_mask - /* extract max number of the index size*/ - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 - /* create working copy of max way size*/ -loop3: - /* factor way and cache number into r11 */ - orr r11, r10, r9, lsl r5 - /* factor index number into r11 */ - orr r11, r11, r7, lsl r2 - /*clean & invalidate by set/way */ - mcr p15, 0, r11, c7, c10, 2 - /* decrement the way*/ - subs r9, r9, #1 - bge loop3 - /*decrement the index */ - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - /* increment cache number */ - cmp r3, r10 - bgt loop1 -finished: - /*swith back to cache level 0 */ - mov r10, #0 - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - isb -skip_l2_inval: - /* Data memory barrier and Data sync barrier */ - mov r1, #0 - mcr p15, 0, r1, c7, c10, 4 - mcr p15, 0, r1, c7, c10, 5 - - wfi @ wait for interrupt - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - bl i_dll_wait - /* restore regs and return */ - ldmfd sp!, {r0-r12, pc} - -i_dll_wait: - ldr r4, clk_stabilize_delay - -i_dll_delay: - subs r4, r4, #0x1 - bne i_dll_delay - ldr r4, sdrc_power - ldr r5, [r4] - bic r5, r5, #0x40 - str r5, [r4] - bx lr -pm_prepwstst_core: - .word PM_PREPWSTST_CORE_V -pm_prepwstst_mpu: - .word PM_PREPWSTST_MPU_V -pm_pwstctrl_mpu: - .word PM_PWSTCTRL_MPU_P -scratchpad_base: - .word SCRATCHPAD_BASE_P -sdrc_power: - .word SDRC_POWER_V -context_mem: - .word 0x803E3E14 -clk_stabilize_delay: - .word 0x000001FF -assoc_mask: - .word 0x3ff -numset_mask: - .word 0x7fff -ttbrbit_mask: - .word 0xFFFFC000 -table_index_mask: - .word 0xFFF00000 -table_entry: - .word 0x00000C02 -cache_pred_disable_mask: - .word 0xFFFFE7FB -ENTRY(omap34xx_cpu_suspend_sz) - .word . - omap34xx_cpu_suspend diff --git a/trunk/arch/arm/mach-omap2/sram242x.S b/trunk/arch/arm/mach-omap2/sram242x.S index bb299851116d..af4bd3490227 100644 --- a/trunk/arch/arm/mach-omap2/sram242x.S +++ b/trunk/arch/arm/mach-omap2/sram242x.S @@ -124,11 +124,11 @@ omap242x_sdi_cm_clksel2_pll: omap242x_sdi_sdrc_dlla_ctrl: .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) omap242x_sdi_prcm_voltctrl: - .word OMAP2420_PRCM_VOLTCTRL + .word OMAP242X_PRCM_VOLTCTRL prcm_mask_val: .word 0xFFFF3FFC omap242x_sdi_timer_32ksynct_cr: - .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) + .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) ENTRY(omap242x_sram_ddr_init_sz) .word . - omap242x_sram_ddr_init @@ -220,11 +220,11 @@ omap242x_srs_sdrc_dlla_ctrl: omap242x_srs_sdrc_rfr_ctrl: .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) omap242x_srs_prcm_voltctrl: - .word OMAP2420_PRCM_VOLTCTRL + .word OMAP242X_PRCM_VOLTCTRL ddr_prcm_mask_val: .word 0xFFFF3FFC omap242x_srs_timer_32ksynct: - .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) + .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) ENTRY(omap242x_sram_reprogram_sdrc_sz) .word . - omap242x_sram_reprogram_sdrc @@ -305,7 +305,7 @@ wait_dll_lock: ldmfd sp!, {r0-r12, pc} @ restore regs and return omap242x_ssp_set_config: - .word OMAP2420_PRCM_CLKCFG_CTRL + .word OMAP242X_PRCM_CLKCFG_CTRL omap242x_ssp_pll_ctl: .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN) omap242x_ssp_pll_stat: diff --git a/trunk/arch/arm/mach-omap2/sram243x.S b/trunk/arch/arm/mach-omap2/sram243x.S index 9955abcaeb31..84363e269e8c 100644 --- a/trunk/arch/arm/mach-omap2/sram243x.S +++ b/trunk/arch/arm/mach-omap2/sram243x.S @@ -124,11 +124,11 @@ omap243x_sdi_cm_clksel2_pll: omap243x_sdi_sdrc_dlla_ctrl: .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL) omap243x_sdi_prcm_voltctrl: - .word OMAP2430_PRCM_VOLTCTRL + .word OMAP243X_PRCM_VOLTCTRL prcm_mask_val: .word 0xFFFF3FFC omap243x_sdi_timer_32ksynct_cr: - .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) + .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) ENTRY(omap243x_sram_ddr_init_sz) .word . - omap243x_sram_ddr_init @@ -220,11 +220,11 @@ omap243x_srs_sdrc_dlla_ctrl: omap243x_srs_sdrc_rfr_ctrl: .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0) omap243x_srs_prcm_voltctrl: - .word OMAP2430_PRCM_VOLTCTRL + .word OMAP243X_PRCM_VOLTCTRL ddr_prcm_mask_val: .word 0xFFFF3FFC omap243x_srs_timer_32ksynct: - .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) + .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) ENTRY(omap243x_sram_reprogram_sdrc_sz) .word . - omap243x_sram_reprogram_sdrc @@ -305,7 +305,7 @@ wait_dll_lock: ldmfd sp!, {r0-r12, pc} @ restore regs and return omap243x_ssp_set_config: - .word OMAP2430_PRCM_CLKCFG_CTRL + .word OMAP243X_PRCM_CLKCFG_CTRL omap243x_ssp_pll_ctl: .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN) omap243x_ssp_pll_stat: diff --git a/trunk/arch/arm/mach-omap2/sram34xx.S b/trunk/arch/arm/mach-omap2/sram34xx.S index c080c82521e1..2c7146136342 100644 --- a/trunk/arch/arm/mach-omap2/sram34xx.S +++ b/trunk/arch/arm/mach-omap2/sram34xx.S @@ -40,74 +40,69 @@ /* * Change frequency of core dpll * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 - * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for - * SDRC rates < 83MHz */ ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack - ldr r4, [sp, #52] @ pull extra args off the stack - dsb @ flush buffered writes to interconnect cmp r3, #0x2 blne configure_sdrc - cmp r4, #0x1 - bleq unlock_dll + cmp r3, #0x2 blne lock_dll + cmp r3, #0x1 + blne unlock_dll bl sdram_in_selfrefresh @ put the SDRAM in self refresh bl configure_core_dpll bl enable_sdrc - cmp r4, #0x1 - bleq wait_dll_unlock + cmp r3, #0x1 + blne wait_dll_unlock + cmp r3, #0x2 blne wait_dll_lock cmp r3, #0x1 blne configure_sdrc - isb @ prevent speculative exec past here mov r0, #0 @ return value ldmfd sp!, {r1-r12, pc} @ restore regs and return unlock_dll: - ldr r11, omap3_sdrc_dlla_ctrl - ldr r12, [r11] - orr r12, r12, #0x4 - str r12, [r11] @ (no OCP barrier needed) + ldr r4, omap3_sdrc_dlla_ctrl + ldr r5, [r4] + orr r5, r5, #0x4 + str r5, [r4] bx lr lock_dll: - ldr r11, omap3_sdrc_dlla_ctrl - ldr r12, [r11] - bic r12, r12, #0x4 - str r12, [r11] @ (no OCP barrier needed) + ldr r4, omap3_sdrc_dlla_ctrl + ldr r5, [r4] + bic r5, r5, #0x4 + str r5, [r4] bx lr sdram_in_selfrefresh: - ldr r11, omap3_sdrc_power @ read the SDRC_POWER register - ldr r12, [r11] @ read the contents of SDRC_POWER - mov r9, r12 @ keep a copy of SDRC_POWER bits - orr r12, r12, #0x40 @ enable self refresh on idle req - bic r12, r12, #0x4 @ clear PWDENA - str r12, [r11] @ write back to SDRC_POWER register - ldr r12, [r11] @ posted-write barrier for SDRC - ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg - ldr r12, [r11] - bic r12, r12, #0x2 @ disable iclk bit for SDRC - str r12, [r11] + mov r5, #0x0 @ Move 0 to R5 + mcr p15, 0, r5, c7, c10, 5 @ memory barrier + ldr r4, omap3_sdrc_power @ read the SDRC_POWER register + ldr r5, [r4] @ read the contents of SDRC_POWER + orr r5, r5, #0x40 @ enable self refresh on idle req + str r5, [r4] @ write back to SDRC_POWER register + ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg + ldr r5, [r4] + bic r5, r5, #0x2 @ disable iclk bit for SRDC + str r5, [r4] wait_sdrc_idle: - ldr r11, omap3_cm_idlest1_core - ldr r12, [r11] - and r12, r12, #0x2 @ check for SDRC idle - cmp r12, #2 + ldr r4, omap3_cm_idlest1_core + ldr r5, [r4] + and r5, r5, #0x2 @ check for SDRC idle + cmp r5, #2 bne wait_sdrc_idle bx lr configure_core_dpll: - ldr r11, omap3_cm_clksel1_pll - ldr r12, [r11] - ldr r10, core_m2_mask_val @ modify m2 for core dpll - and r12, r12, r10 - orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val - str r12, [r11] - ldr r12, [r11] @ posted-write barrier for CM - mov r12, #0x800 @ wait for the clock to stabilise + ldr r4, omap3_cm_clksel1_pll + ldr r5, [r4] + ldr r6, core_m2_mask_val @ modify m2 for core dpll + and r5, r5, r6 + orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val + str r5, [r4] + mov r5, #0x800 @ wait for the clock to stabilise cmp r3, #2 bne wait_clk_stable bx lr wait_clk_stable: - subs r12, r12, #1 + subs r5, r5, #1 bne wait_clk_stable nop nop @@ -121,42 +116,42 @@ wait_clk_stable: nop bx lr enable_sdrc: - ldr r11, omap3_cm_iclken1_core - ldr r12, [r11] - orr r12, r12, #0x2 @ enable iclk bit for SDRC - str r12, [r11] + ldr r4, omap3_cm_iclken1_core + ldr r5, [r4] + orr r5, r5, #0x2 @ enable iclk bit for SDRC + str r5, [r4] wait_sdrc_idle1: - ldr r11, omap3_cm_idlest1_core - ldr r12, [r11] - and r12, r12, #0x2 - cmp r12, #0 + ldr r4, omap3_cm_idlest1_core + ldr r5, [r4] + and r5, r5, #0x2 + cmp r5, #0 bne wait_sdrc_idle1 -restore_sdrc_power_val: - ldr r11, omap3_sdrc_power - str r9, [r11] @ restore SDRC_POWER, no barrier needed + ldr r4, omap3_sdrc_power + ldr r5, [r4] + bic r5, r5, #0x40 + str r5, [r4] bx lr wait_dll_lock: - ldr r11, omap3_sdrc_dlla_status - ldr r12, [r11] - and r12, r12, #0x4 - cmp r12, #0x4 + ldr r4, omap3_sdrc_dlla_status + ldr r5, [r4] + and r5, r5, #0x4 + cmp r5, #0x4 bne wait_dll_lock bx lr wait_dll_unlock: - ldr r11, omap3_sdrc_dlla_status - ldr r12, [r11] - and r12, r12, #0x4 - cmp r12, #0x0 + ldr r4, omap3_sdrc_dlla_status + ldr r5, [r4] + and r5, r5, #0x4 + cmp r5, #0x0 bne wait_dll_unlock bx lr configure_sdrc: - ldr r11, omap3_sdrc_rfr_ctrl - str r0, [r11] - ldr r11, omap3_sdrc_actim_ctrla - str r1, [r11] - ldr r11, omap3_sdrc_actim_ctrlb - str r2, [r11] - ldr r2, [r11] @ posted-write barrier for SDRC + ldr r4, omap3_sdrc_rfr_ctrl + str r0, [r4] + ldr r4, omap3_sdrc_actim_ctrla + str r1, [r4] + ldr r4, omap3_sdrc_actim_ctrlb + str r2, [r4] bx lr omap3_sdrc_power: diff --git a/trunk/arch/arm/mach-omap2/timer-gp.c b/trunk/arch/arm/mach-omap2/timer-gp.c index 97eeeebcb066..f36aba12090e 100644 --- a/trunk/arch/arm/mach-omap2/timer-gp.c +++ b/trunk/arch/arm/mach-omap2/timer-gp.c @@ -17,10 +17,9 @@ * * Some parts based off of TI's 24xx code: * - * Copyright (C) 2004-2009 Texas Instruments, Inc. + * Copyright (C) 2004 Texas Instruments, Inc. * * Roughly modelled after the OMAP1 MPU timer code. - * Added OMAP4 support - Santosh Shilimkar * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -38,7 +37,6 @@ #include #include -#include /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12 @@ -84,8 +82,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_PERIODIC: period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; period -= 1; - if (cpu_is_omap44xx()) - period = 0xff; /* FIXME: */ + omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); break; case CLOCK_EVT_MODE_ONESHOT: @@ -148,9 +145,6 @@ static void __init omap2_gp_clockevent_init(void) "timer-gp: omap_dm_timer_set_source() failed\n"); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); - if (cpu_is_omap44xx()) - /* Assuming 32kHz clk is driving GPT1 */ - tick_rate = 32768; /* FIXME: */ pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", gptimer_id, tick_rate); @@ -230,9 +224,6 @@ static void __init omap2_gp_clocksource_init(void) static void __init omap2_gp_timer_init(void) { -#ifdef CONFIG_LOCAL_TIMERS - twd_base = IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE); -#endif omap_dm_timer_init(); omap2_gp_clockevent_init(); diff --git a/trunk/arch/arm/mach-omap2/timer-mpu.c b/trunk/arch/arm/mach-omap2/timer-mpu.c deleted file mode 100644 index c1a650a9910f..000000000000 --- a/trunk/arch/arm/mach-omap2/timer-mpu.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * The MPU local timer source file. In OMAP4, both cortex-a9 cores have - * own timer in it's MPU domain. These timers will be driving the - * linux kernel SMP tick framework when active. These timers are not - * part of the wake up domain. - * - * Copyright (C) 2009 Texas Instruments, Inc. - * - * Author: - * Santosh Shilimkar - * - * This file is based on arm realview smp platform file. - * Copyright (C) 2002 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include - -/* - * Setup the local clock events for a CPU. - */ -void __cpuinit local_timer_setup(struct clock_event_device *evt) -{ - evt->irq = INT_44XX_LOCALTIMER_IRQ; - twd_timer_setup(evt); -} - diff --git a/trunk/arch/arm/mach-omap2/usb-musb.c b/trunk/arch/arm/mach-omap2/usb-musb.c index d85296dc896c..34a56a136efd 100644 --- a/trunk/arch/arm/mach-omap2/usb-musb.c +++ b/trunk/arch/arm/mach-omap2/usb-musb.c @@ -28,20 +28,10 @@ #include #include +#include #include #include -#define OTG_SYSCONFIG (OMAP34XX_HSUSB_OTG_BASE + 0x404) - -static void __init usb_musb_pm_init(void) -{ - /* Ensure force-idle mode for OTG controller */ - if (cpu_is_omap34xx()) - omap_writel(0, OTG_SYSCONFIG); -} - -#ifdef CONFIG_USB_MUSB_SOC - static struct resource musb_resources[] = { [0] = { /* start and end set dynamically */ .flags = IORESOURCE_MEM, @@ -194,13 +184,4 @@ void __init usb_musb_init(void) printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); return; } - - usb_musb_pm_init(); -} - -#else -void __init usb_musb_init(void) -{ - usb_musb_pm_init(); } -#endif /* CONFIG_USB_MUSB_SOC */ diff --git a/trunk/arch/arm/mach-orion5x/addr-map.c b/trunk/arch/arm/mach-orion5x/addr-map.c index 6f3f77d031d0..c14d12137276 100644 --- a/trunk/arch/arm/mach-orion5x/addr-map.c +++ b/trunk/arch/arm/mach-orion5x/addr-map.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include "common.h" @@ -45,7 +44,6 @@ #define TARGET_DEV_BUS 1 #define TARGET_PCI 3 #define TARGET_PCIE 4 -#define TARGET_SRAM 9 #define ATTR_PCIE_MEM 0x59 #define ATTR_PCIE_IO 0x51 #define ATTR_PCIE_WA 0x79 @@ -55,7 +53,6 @@ #define ATTR_DEV_CS1 0x1d #define ATTR_DEV_CS2 0x1b #define ATTR_DEV_BOOT 0xf -#define ATTR_SRAM 0x0 /* * Helpers to get DDR bank info @@ -90,13 +87,13 @@ static int __init orion5x_cpu_win_can_remap(int win) return 0; } -static int __init setup_cpu_win(int win, u32 base, u32 size, +static void __init setup_cpu_win(int win, u32 base, u32 size, u8 target, u8 attr, int remap) { if (win >= 8) { printk(KERN_ERR "setup_cpu_win: trying to allocate " "window %d\n", win); - return -ENOSPC; + return; } writel(base & 0xffff0000, CPU_WIN_BASE(win)); @@ -110,7 +107,6 @@ static int __init setup_cpu_win(int win, u32 base, u32 size, writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); writel(0, CPU_WIN_REMAP_HI(win)); } - return 0; } void __init orion5x_setup_cpu_mbus_bridge(void) @@ -197,9 +193,3 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) setup_cpu_win(win_alloc_count++, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); } - -int __init orion5x_setup_sram_win(void) -{ - return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE, - ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); -} diff --git a/trunk/arch/arm/mach-orion5x/common.c b/trunk/arch/arm/mach-orion5x/common.c index eafcc49009ea..6af99ddabdfb 100644 --- a/trunk/arch/arm/mach-orion5x/common.c +++ b/trunk/arch/arm/mach-orion5x/common.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include "common.h" @@ -188,9 +188,6 @@ static struct platform_device orion5x_eth = { .id = 0, .num_resources = 1, .resource = orion5x_eth_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, }; void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) @@ -251,10 +248,12 @@ static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { static struct resource orion5x_i2c_resources[] = { { + .name = "i2c base", .start = I2C_PHYS_BASE, .end = I2C_PHYS_BASE + 0x1f, .flags = IORESOURCE_MEM, }, { + .name = "i2c irq", .start = IRQ_ORION5X_I2C, .end = IRQ_ORION5X_I2C, .flags = IORESOURCE_IRQ, @@ -536,52 +535,16 @@ void __init orion5x_xor_init(void) platform_device_register(&orion5x_xor1_channel); } -static struct resource orion5x_crypto_res[] = { - { - .name = "regs", - .start = ORION5X_CRYPTO_PHYS_BASE, - .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, - }, { - .name = "sram", - .start = ORION5X_SRAM_PHYS_BASE, - .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "crypto interrupt", - .start = IRQ_ORION5X_CESA, - .end = IRQ_ORION5X_CESA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_crypto_device = { - .name = "mv_crypto", - .id = -1, - .num_resources = ARRAY_SIZE(orion5x_crypto_res), - .resource = orion5x_crypto_res, -}; - -int __init orion5x_crypto_init(void) -{ - int ret; - - ret = orion5x_setup_sram_win(); - if (ret) - return ret; - - return platform_device_register(&orion5x_crypto_device); -} /***************************************************************************** * Watchdog ****************************************************************************/ -static struct orion_wdt_platform_data orion5x_wdt_data = { +static struct orion5x_wdt_platform_data orion5x_wdt_data = { .tclk = 0, }; static struct platform_device orion5x_wdt_device = { - .name = "orion_wdt", + .name = "orion5x_wdt", .id = -1, .dev = { .platform_data = &orion5x_wdt_data, diff --git a/trunk/arch/arm/mach-orion5x/common.h b/trunk/arch/arm/mach-orion5x/common.h index de483e83edd7..798b9a5e3da9 100644 --- a/trunk/arch/arm/mach-orion5x/common.h +++ b/trunk/arch/arm/mach-orion5x/common.h @@ -26,7 +26,6 @@ void orion5x_setup_dev0_win(u32 base, u32 size); void orion5x_setup_dev1_win(u32 base, u32 size); void orion5x_setup_dev2_win(u32 base, u32 size); void orion5x_setup_pcie_wa_win(u32 base, u32 size); -int orion5x_setup_sram_win(void); void orion5x_ehci0_init(void); void orion5x_ehci1_init(void); @@ -38,7 +37,6 @@ void orion5x_spi_init(void); void orion5x_uart0_init(void); void orion5x_uart1_init(void); void orion5x_xor_init(void); -int orion5x_crypto_init(void); /* * PCIe/PCI functions. diff --git a/trunk/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/trunk/arch/arm/mach-orion5x/include/mach/bridge-regs.h index 5c9744cd8ef6..be896e59d3e7 100644 --- a/trunk/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ b/trunk/arch/arm/mach-orion5x/include/mach/bridge-regs.h @@ -17,8 +17,8 @@ #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) -#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) -#define WDT_RESET_OUT_EN 0x0002 +#define CPU_RESET_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) +#define WDT_RESET 0x0002 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) diff --git a/trunk/arch/arm/mach-orion5x/include/mach/orion5x.h b/trunk/arch/arm/mach-orion5x/include/mach/orion5x.h index 2d8766570531..377a773ae53f 100644 --- a/trunk/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/trunk/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -24,7 +24,6 @@ * f1000000 on-chip peripheral registers * f2000000 PCIe I/O space * f2100000 PCI I/O space - * f2200000 SRAM dedicated for the crypto unit * f4000000 device bus mappings (boot) * fa000000 device bus mappings (cs0) * fa800000 device bus mappings (cs2) @@ -50,9 +49,6 @@ #define ORION5X_PCI_IO_BUS_BASE 0x00100000 #define ORION5X_PCI_IO_SIZE SZ_1M -#define ORION5X_SRAM_PHYS_BASE (0xf2200000) -#define ORION5X_SRAM_SIZE SZ_8K - /* Relevant only for Orion-1/Orion-NAS */ #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 #define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 @@ -98,8 +94,6 @@ #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) -#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x90000) - #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) diff --git a/trunk/arch/arm/mach-orion5x/include/mach/system.h b/trunk/arch/arm/mach-orion5x/include/mach/system.h index 60e734c10458..e912490fff23 100644 --- a/trunk/arch/arm/mach-orion5x/include/mach/system.h +++ b/trunk/arch/arm/mach-orion5x/include/mach/system.h @@ -23,7 +23,7 @@ static inline void arch_reset(char mode, const char *cmd) /* * Enable and issue soft reset */ - orion5x_setbits(RSTOUTn_MASK, (1 << 2)); + orion5x_setbits(CPU_RESET_MASK, (1 << 2)); orion5x_setbits(CPU_SOFT_RESET, 1); } diff --git a/trunk/arch/arm/mach-orion5x/mpp.c b/trunk/arch/arm/mach-orion5x/mpp.c index bc4c3b9aaf83..e23a3f91d6c6 100644 --- a/trunk/arch/arm/mach-orion5x/mpp.c +++ b/trunk/arch/arm/mach-orion5x/mpp.c @@ -124,9 +124,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode) u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL); u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL); - /* Initialize gpiolib. */ - orion_gpio_init(); - while (mode->mpp >= 0) { u32 *reg; int num_type; diff --git a/trunk/arch/arm/mach-orion5x/mss2-setup.c b/trunk/arch/arm/mach-orion5x/mss2-setup.c index 61c086b66723..41e6d5033d54 100644 --- a/trunk/arch/arm/mach-orion5x/mss2-setup.c +++ b/trunk/arch/arm/mach-orion5x/mss2-setup.c @@ -181,9 +181,9 @@ static void mss2_power_off(void) /* * Enable and issue soft reset */ - reg = readl(RSTOUTn_MASK); + reg = readl(CPU_RESET_MASK); reg |= 1 << 2; - writel(reg, RSTOUTn_MASK); + writel(reg, CPU_RESET_MASK); reg = readl(CPU_SOFT_RESET); reg |= 1; diff --git a/trunk/arch/arm/mach-orion5x/ts78xx-fpga.h b/trunk/arch/arm/mach-orion5x/ts78xx-fpga.h index 37b3d4875291..0f9cdf458952 100644 --- a/trunk/arch/arm/mach-orion5x/ts78xx-fpga.h +++ b/trunk/arch/arm/mach-orion5x/ts78xx-fpga.h @@ -25,7 +25,6 @@ struct fpga_devices { /* Technologic Systems */ struct fpga_device ts_rtc; struct fpga_device ts_nand; - struct fpga_device ts_rng; }; struct ts78xx_fpga_data { diff --git a/trunk/arch/arm/mach-orion5x/ts78xx-setup.c b/trunk/arch/arm/mach-orion5x/ts78xx-setup.c index 5041d1bc26b1..9a6b397f972d 100644 --- a/trunk/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/trunk/arch/arm/mach-orion5x/ts78xx-setup.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -270,50 +269,6 @@ static void ts78xx_ts_nand_unload(void) platform_device_del(&ts78xx_ts_nand_device); } -/***************************************************************************** - * HW RNG - ****************************************************************************/ -#define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044) - -static struct resource ts78xx_ts_rng_resource = { - .flags = IORESOURCE_MEM, - .start = TS_RNG_DATA, - .end = TS_RNG_DATA + 4 - 1, -}; - -static struct timeriomem_rng_data ts78xx_ts_rng_data = { - .period = 1000000, /* one second */ -}; - -static struct platform_device ts78xx_ts_rng_device = { - .name = "timeriomem_rng", - .id = -1, - .dev = { - .platform_data = &ts78xx_ts_rng_data, - }, - .resource = &ts78xx_ts_rng_resource, - .num_resources = 1, -}; - -static int ts78xx_ts_rng_load(void) -{ - int rc; - - if (ts78xx_fpga.supports.ts_rng.init == 0) { - rc = platform_device_register(&ts78xx_ts_rng_device); - if (!rc) - ts78xx_fpga.supports.ts_rng.init = 1; - } else - rc = platform_device_add(&ts78xx_ts_rng_device); - - return rc; -}; - -static void ts78xx_ts_rng_unload(void) -{ - platform_device_del(&ts78xx_ts_rng_device); -} - /***************************************************************************** * FPGA 'hotplug' support code ****************************************************************************/ @@ -321,7 +276,6 @@ static void ts78xx_fpga_devices_zero_init(void) { ts78xx_fpga.supports.ts_rtc.init = 0; ts78xx_fpga.supports.ts_nand.init = 0; - ts78xx_fpga.supports.ts_rng.init = 0; } static void ts78xx_fpga_supports(void) @@ -335,12 +289,10 @@ static void ts78xx_fpga_supports(void) case TS7800_REV_5: ts78xx_fpga.supports.ts_rtc.present = 1; ts78xx_fpga.supports.ts_nand.present = 1; - ts78xx_fpga.supports.ts_rng.present = 1; break; default: ts78xx_fpga.supports.ts_rtc.present = 0; ts78xx_fpga.supports.ts_nand.present = 0; - ts78xx_fpga.supports.ts_rng.present = 0; } } @@ -364,14 +316,6 @@ static int ts78xx_fpga_load_devices(void) } ret |= tmp; } - if (ts78xx_fpga.supports.ts_rng.present == 1) { - tmp = ts78xx_ts_rng_load(); - if (tmp) { - printk(KERN_INFO "TS-78xx: RNG not registered\n"); - ts78xx_fpga.supports.ts_rng.present = 0; - } - ret |= tmp; - } return ret; } @@ -384,8 +328,6 @@ static int ts78xx_fpga_unload_devices(void) ts78xx_ts_rtc_unload(); if (ts78xx_fpga.supports.ts_nand.present == 1) ts78xx_ts_nand_unload(); - if (ts78xx_fpga.supports.ts_rng.present == 1) - ts78xx_ts_rng_unload(); return ret; } diff --git a/trunk/arch/arm/mach-orion5x/wnr854t-setup.c b/trunk/arch/arm/mach-orion5x/wnr854t-setup.c index 69208217b220..7ddc22c2bb54 100644 --- a/trunk/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/trunk/arch/arm/mach-orion5x/wnr854t-setup.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -98,20 +97,6 @@ static struct mv643xx_eth_platform_data wnr854t_eth_data = { .duplex = DUPLEX_FULL, }; -static struct dsa_chip_data wnr854t_switch_chip_data = { - .port_names[0] = "lan3", - .port_names[1] = "lan4", - .port_names[2] = "wan", - .port_names[3] = "cpu", - .port_names[5] = "lan1", - .port_names[7] = "lan2", -}; - -static struct dsa_platform_data wnr854t_switch_plat_data = { - .nr_chips = 1, - .chip = &wnr854t_switch_chip_data, -}; - static void __init wnr854t_init(void) { /* @@ -125,7 +110,6 @@ static void __init wnr854t_init(void) * Configure peripherals. */ orion5x_eth_init(&wnr854t_eth_data); - orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); orion5x_uart0_init(); orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE, diff --git a/trunk/arch/arm/mach-pxa/clock.c b/trunk/arch/arm/mach-pxa/clock.c index 49ae38292310..db52d2c4791d 100644 --- a/trunk/arch/arm/mach-pxa/clock.c +++ b/trunk/arch/arm/mach-pxa/clock.c @@ -86,3 +86,20 @@ void clks_register(struct clk_lookup *clks, size_t num) for (i = 0; i < num; i++) clkdev_add(&clks[i]); } + +int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, + struct device *dev) +{ + struct clk *r = clk_get(dev, id); + struct clk_lookup *l; + + if (!r) + return -ENODEV; + + l = clkdev_alloc(r, alias, alias_dev_name); + clk_put(r); + if (!l) + return -ENODEV; + clkdev_add(l); + return 0; +} diff --git a/trunk/arch/arm/mach-pxa/ezx.c b/trunk/arch/arm/mach-pxa/ezx.c index 7db966dc29ce..92ba16e1b6fc 100644 --- a/trunk/arch/arm/mach-pxa/ezx.c +++ b/trunk/arch/arm/mach-pxa/ezx.c @@ -111,9 +111,9 @@ static unsigned long ezx_pin_config[] __initdata = { GPIO25_SSP1_TXD, GPIO26_SSP1_RXD, GPIO24_GPIO, /* pcap chip select */ - GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, /* pcap interrupt */ - GPIO4_GPIO | MFP_LPM_DRIVE_HIGH, /* WDI_AP */ - GPIO55_GPIO | MFP_LPM_DRIVE_HIGH, /* SYS_RESTART */ + GPIO1_GPIO, /* pcap interrupt */ + GPIO4_GPIO, /* WDI_AP */ + GPIO55_GPIO, /* SYS_RESTART */ /* MMC */ GPIO32_MMC_CLK, @@ -144,20 +144,20 @@ static unsigned long ezx_pin_config[] __initdata = { #if defined(CONFIG_MACH_EZX_A780) || defined(CONFIG_MACH_EZX_E680) static unsigned long gen1_pin_config[] __initdata = { /* flip / lockswitch */ - GPIO12_GPIO | WAKEUP_ON_EDGE_BOTH, + GPIO12_GPIO, /* bluetooth (bcm2035) */ - GPIO14_GPIO | WAKEUP_ON_EDGE_RISE, /* HOSTWAKE */ + GPIO14_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ GPIO48_GPIO, /* RESET */ GPIO28_GPIO, /* WAKEUP */ /* Neptune handshake */ - GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* BP_RDY */ - GPIO57_GPIO | MFP_LPM_DRIVE_HIGH, /* AP_RDY */ - GPIO13_GPIO | WAKEUP_ON_EDGE_BOTH, /* WDI */ - GPIO3_GPIO | WAKEUP_ON_EDGE_BOTH, /* WDI2 */ - GPIO82_GPIO | MFP_LPM_DRIVE_HIGH, /* RESET */ - GPIO99_GPIO | MFP_LPM_DRIVE_HIGH, /* TC_MM_EN */ + GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* BP_RDY */ + GPIO57_GPIO, /* AP_RDY */ + GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI */ + GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI2 */ + GPIO82_GPIO, /* RESET */ + GPIO99_GPIO, /* TC_MM_EN */ /* sound */ GPIO52_SSP3_SCLK, @@ -199,21 +199,21 @@ static unsigned long gen1_pin_config[] __initdata = { defined(CONFIG_MACH_EZX_E2) || defined(CONFIG_MACH_EZX_E6) static unsigned long gen2_pin_config[] __initdata = { /* flip / lockswitch */ - GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH, + GPIO15_GPIO, /* EOC */ - GPIO10_GPIO | WAKEUP_ON_EDGE_RISE, + GPIO10_GPIO, /* bluetooth (bcm2045) */ - GPIO13_GPIO | WAKEUP_ON_EDGE_RISE, /* HOSTWAKE */ + GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ GPIO37_GPIO, /* RESET */ GPIO57_GPIO, /* WAKEUP */ /* Neptune handshake */ - GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* BP_RDY */ - GPIO96_GPIO | MFP_LPM_DRIVE_HIGH, /* AP_RDY */ - GPIO3_GPIO | WAKEUP_ON_EDGE_FALL, /* WDI */ - GPIO116_GPIO | MFP_LPM_DRIVE_HIGH, /* RESET */ + GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* BP_RDY */ + GPIO96_GPIO, /* AP_RDY */ + GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI */ + GPIO116_GPIO, /* RESET */ GPIO41_GPIO, /* BP_FLASH */ /* sound */ diff --git a/trunk/arch/arm/mach-pxa/include/mach/palmld.h b/trunk/arch/arm/mach-pxa/include/mach/palmld.h index 8721b8010221..fb13c82ad6dc 100644 --- a/trunk/arch/arm/mach-pxa/include/mach/palmld.h +++ b/trunk/arch/arm/mach-pxa/include/mach/palmld.h @@ -56,6 +56,7 @@ #define GPIO_NR_PALMLD_LED_AMBER 94 /* IDE */ +#define GPIO_NR_PALMLD_IDE_IRQ 95 #define GPIO_NR_PALMLD_IDE_RESET 98 #define GPIO_NR_PALMLD_IDE_PWEN 115 diff --git a/trunk/arch/arm/mach-pxa/include/mach/reset.h b/trunk/arch/arm/mach-pxa/include/mach/reset.h index b6c10556fbc7..31e6a7b6ad80 100644 --- a/trunk/arch/arm/mach-pxa/include/mach/reset.h +++ b/trunk/arch/arm/mach-pxa/include/mach/reset.h @@ -13,9 +13,8 @@ extern void clear_reset_status(unsigned int mask); /** * init_gpio_reset() - register GPIO as reset generator * @gpio: gpio nr - * @output: set gpio as output instead of input during normal work - * @level: output level + * @output: set gpio as out/low instead of input during normal work */ -extern int init_gpio_reset(int gpio, int output, int level); +extern int init_gpio_reset(int gpio, int output); #endif /* __ASM_ARCH_RESET_H */ diff --git a/trunk/arch/arm/mach-pxa/mfp-pxa2xx.c b/trunk/arch/arm/mach-pxa/mfp-pxa2xx.c index cf6b720c055f..7ffb91d64c39 100644 --- a/trunk/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/trunk/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -322,7 +322,6 @@ static inline void pxa27x_mfp_init(void) {} #ifdef CONFIG_PM static unsigned long saved_gafr[2][4]; static unsigned long saved_gpdr[4]; -static unsigned long saved_pgsr[4]; static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) { @@ -333,7 +332,6 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) saved_gafr[0][i] = GAFR_L(i); saved_gafr[1][i] = GAFR_U(i); saved_gpdr[i] = GPDR(i * 32); - saved_pgsr[i] = PGSR(i); GPDR(i * 32) = gpdr_lpm[i]; } @@ -348,7 +346,6 @@ static int pxa2xx_mfp_resume(struct sys_device *d) GAFR_L(i) = saved_gafr[0][i]; GAFR_U(i) = saved_gafr[1][i]; GPDR(i * 32) = saved_gpdr[i]; - PGSR(i) = saved_pgsr[i]; } PSSR = PSSR_RDH | PSSR_PH; return 0; @@ -377,9 +374,6 @@ static int __init pxa2xx_mfp_init(void) if (cpu_is_pxa27x()) pxa27x_mfp_init(); - /* clear RDH bit to enable GPIO receivers after reset/sleep exit */ - PSSR = PSSR_RDH; - /* initialize gafr_run[], pgsr_lpm[] from existing values */ for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) gpdr_lpm[i] = GPDR(i * 32); diff --git a/trunk/arch/arm/mach-pxa/palmld.c b/trunk/arch/arm/mach-pxa/palmld.c index 2e65f05d366c..1cec1806f002 100644 --- a/trunk/arch/arm/mach-pxa/palmld.c +++ b/trunk/arch/arm/mach-pxa/palmld.c @@ -62,8 +62,6 @@ static unsigned long palmld_pin_config[] __initdata = { GPIO29_AC97_SDATA_IN_0, GPIO30_AC97_SDATA_OUT, GPIO31_AC97_SYNC, - GPIO89_AC97_SYSCLK, - GPIO95_AC97_nRESET, /* IrDA */ GPIO108_GPIO, /* ir disable */ @@ -129,7 +127,7 @@ static unsigned long palmld_pin_config[] __initdata = { GPIO81_GPIO, /* wifi reset */ /* HDD */ - GPIO98_GPIO, /* HDD reset */ + GPIO95_GPIO, /* HDD irq */ GPIO115_GPIO, /* HDD power */ /* MISC */ @@ -495,14 +493,6 @@ static struct platform_device palmld_asoc = { }, }; -/****************************************************************************** - * HDD - ******************************************************************************/ -static struct platform_device palmld_hdd = { - .name = "pata_palmld", - .id = -1, -}; - /****************************************************************************** * Framebuffer ******************************************************************************/ @@ -567,7 +557,6 @@ static struct platform_device *devices[] __initdata = { &palmld_leds, &power_supply, &palmld_asoc, - &palmld_hdd, }; static struct map_desc palmld_io_desc[] __initdata = { diff --git a/trunk/arch/arm/mach-pxa/palmt5.c b/trunk/arch/arm/mach-pxa/palmt5.c index 05bf979b78a6..30662363907b 100644 --- a/trunk/arch/arm/mach-pxa/palmt5.c +++ b/trunk/arch/arm/mach-pxa/palmt5.c @@ -64,7 +64,6 @@ static unsigned long palmt5_pin_config[] __initdata = { GPIO29_AC97_SDATA_IN_0, GPIO30_AC97_SDATA_OUT, GPIO31_AC97_SYNC, - GPIO89_AC97_SYSCLK, GPIO95_AC97_nRESET, /* IrDA */ diff --git a/trunk/arch/arm/mach-pxa/palmtx.c b/trunk/arch/arm/mach-pxa/palmtx.c index e99a893c58a7..e2d44b1a8a9b 100644 --- a/trunk/arch/arm/mach-pxa/palmtx.c +++ b/trunk/arch/arm/mach-pxa/palmtx.c @@ -65,7 +65,6 @@ static unsigned long palmtx_pin_config[] __initdata = { GPIO29_AC97_SDATA_IN_0, GPIO30_AC97_SDATA_OUT, GPIO31_AC97_SYNC, - GPIO89_AC97_SYSCLK, GPIO95_AC97_nRESET, /* IrDA */ diff --git a/trunk/arch/arm/mach-pxa/reset.c b/trunk/arch/arm/mach-pxa/reset.c index 01e9d643394a..df29d45fb4e7 100644 --- a/trunk/arch/arm/mach-pxa/reset.c +++ b/trunk/arch/arm/mach-pxa/reset.c @@ -20,7 +20,7 @@ static void do_hw_reset(void); static int reset_gpio = -1; -int init_gpio_reset(int gpio, int output, int level) +int init_gpio_reset(int gpio, int output) { int rc; @@ -31,7 +31,7 @@ int init_gpio_reset(int gpio, int output, int level) } if (output) - rc = gpio_direction_output(gpio, level); + rc = gpio_direction_output(gpio, 0); else rc = gpio_direction_input(gpio); if (rc) { diff --git a/trunk/arch/arm/mach-pxa/spitz.c b/trunk/arch/arm/mach-pxa/spitz.c index 5a45fe340a10..c18e34acafcb 100644 --- a/trunk/arch/arm/mach-pxa/spitz.c +++ b/trunk/arch/arm/mach-pxa/spitz.c @@ -531,15 +531,9 @@ static int spitz_ohci_init(struct device *dev) return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1); } -static void spitz_ohci_exit(struct device *dev) -{ - gpio_free(SPITZ_GPIO_USB_HOST); -} - static struct pxaohci_platform_data spitz_ohci_platform_data = { .port_mode = PMM_NPS_MODE, .init = spitz_ohci_init, - .exit = spitz_ohci_exit, .flags = ENABLE_PORT_ALL | NO_OC_PROTECTION, .power_budget = 150, }; @@ -737,7 +731,7 @@ static void spitz_restart(char mode, const char *cmd) static void __init common_init(void) { - init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0); + init_gpio_reset(SPITZ_GPIO_ON_RESET, 1); pm_power_off = spitz_poweroff; arm_pm_restart = spitz_restart; diff --git a/trunk/arch/arm/mach-pxa/tosa.c b/trunk/arch/arm/mach-pxa/tosa.c index a0bd46ef5d30..afac5b6d3d78 100644 --- a/trunk/arch/arm/mach-pxa/tosa.c +++ b/trunk/arch/arm/mach-pxa/tosa.c @@ -897,7 +897,7 @@ static void __init tosa_init(void) gpio_set_wake(MFP_PIN_GPIO1, 1); /* We can't pass to gpio-keys since it will drop the Reset altfunc */ - init_gpio_reset(TOSA_GPIO_ON_RESET, 0, 0); + init_gpio_reset(TOSA_GPIO_ON_RESET, 0); pm_power_off = tosa_poweroff; arm_pm_restart = tosa_restart; diff --git a/trunk/arch/arm/mach-realview/Kconfig b/trunk/arch/arm/mach-realview/Kconfig index bf35cfd89f34..b6ec10627776 100644 --- a/trunk/arch/arm/mach-realview/Kconfig +++ b/trunk/arch/arm/mach-realview/Kconfig @@ -24,6 +24,7 @@ config REALVIEW_EB_ARM11MP config REALVIEW_EB_ARM11MP_REVB bool "Support ARM11MPCore RevB tile" depends on REALVIEW_EB_ARM11MP + default n help Enable support for the ARM11MPCore RevB tile on the Realview platform. Since there are device address differences, a diff --git a/trunk/arch/arm/mach-realview/Makefile b/trunk/arch/arm/mach-realview/Makefile index e13d0947ad0b..7bea8ffc4b59 100644 --- a/trunk/arch/arm/mach-realview/Makefile +++ b/trunk/arch/arm/mach-realview/Makefile @@ -7,6 +7,5 @@ obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/trunk/arch/arm/mach-realview/core.h b/trunk/arch/arm/mach-realview/core.h index 59a337ba4be7..21c08637683b 100644 --- a/trunk/arch/arm/mach-realview/core.h +++ b/trunk/arch/arm/mach-realview/core.h @@ -51,6 +51,9 @@ extern struct mmc_platform_data realview_mmc0_plat_data; extern struct mmc_platform_data realview_mmc1_plat_data; extern struct clcd_board clcd_plat_data; extern void __iomem *gic_cpu_base_addr; +#ifdef CONFIG_LOCAL_TIMERS +extern void __iomem *twd_base; +#endif extern void __iomem *timer0_va_base; extern void __iomem *timer1_va_base; extern void __iomem *timer2_va_base; diff --git a/trunk/arch/arm/mach-realview/include/mach/scu.h b/trunk/arch/arm/mach-realview/include/mach/scu.h new file mode 100644 index 000000000000..d55802d645af --- /dev/null +++ b/trunk/arch/arm/mach-realview/include/mach/scu.h @@ -0,0 +1,13 @@ +#ifndef __ASMARM_ARCH_SCU_H +#define __ASMARM_ARCH_SCU_H + +/* + * SCU registers + */ +#define SCU_CTRL 0x00 +#define SCU_CONFIG 0x04 +#define SCU_CPU_STATUS 0x08 +#define SCU_INVALIDATE 0x0c +#define SCU_FPGA_REVISION 0x10 + +#endif diff --git a/trunk/arch/arm/mach-realview/localtimer.c b/trunk/arch/arm/mach-realview/localtimer.c index 60b4e111f459..1c01d13460f0 100644 --- a/trunk/arch/arm/mach-realview/localtimer.c +++ b/trunk/arch/arm/mach-realview/localtimer.c @@ -9,18 +9,196 @@ * published by the Free Software Foundation. */ #include +#include +#include +#include #include +#include +#include #include +#include +#include +#include +#include +#include #include -#include -#include + +static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); + +/* + * Used on SMP for either the local timer or IPI_TIMER + */ +void local_timer_interrupt(void) +{ + struct clock_event_device *clk = &__get_cpu_var(local_clockevent); + + clk->event_handler(clk); +} + +#ifdef CONFIG_LOCAL_TIMERS + +/* set up by the platform code */ +void __iomem *twd_base; + +static unsigned long mpcore_timer_rate; + +static void local_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + unsigned long ctrl; + + switch(mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* timer load already set up */ + ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE + | TWD_TIMER_CONTROL_PERIODIC; + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT; + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + ctrl = 0; + } + + __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL); +} + +static int local_timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL); + + __raw_writel(evt, twd_base + TWD_TIMER_COUNTER); + __raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, twd_base + TWD_TIMER_CONTROL); + + return 0; +} + +/* + * local_timer_ack: checks for a local timer interrupt. + * + * If a local timer interrupt has occurred, acknowledge and return 1. + * Otherwise, return 0. + */ +int local_timer_ack(void) +{ + if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) { + __raw_writel(1, twd_base + TWD_TIMER_INTSTAT); + return 1; + } + + return 0; +} + +static void __cpuinit twd_calibrate_rate(void) +{ + unsigned long load, count; + u64 waitjiffies; + + /* + * If this is the first time round, we need to work out how fast + * the timer ticks + */ + if (mpcore_timer_rate == 0) { + printk("Calibrating local timer... "); + + /* Wait for a tick to start */ + waitjiffies = get_jiffies_64() + 1; + + while (get_jiffies_64() < waitjiffies) + udelay(10); + + /* OK, now the tick has started, let's get the timer going */ + waitjiffies += 5; + + /* enable, no interrupt or reload */ + __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL); + + /* maximum value */ + __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); + + while (get_jiffies_64() < waitjiffies) + udelay(10); + + count = __raw_readl(twd_base + TWD_TIMER_COUNTER); + + mpcore_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); + + printk("%lu.%02luMHz.\n", mpcore_timer_rate / 1000000, + (mpcore_timer_rate / 100000) % 100); + } + + load = mpcore_timer_rate / HZ; + + __raw_writel(load, twd_base + TWD_TIMER_LOAD); +} /* * Setup the local clock events for a CPU. */ -void __cpuinit local_timer_setup(struct clock_event_device *evt) +void __cpuinit local_timer_setup(void) +{ + unsigned int cpu = smp_processor_id(); + struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); + unsigned long flags; + + twd_calibrate_rate(); + + clk->name = "local_timer"; + clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + clk->rating = 350; + clk->set_mode = local_timer_set_mode; + clk->set_next_event = local_timer_set_next_event; + clk->irq = IRQ_LOCALTIMER; + clk->cpumask = cpumask_of(cpu); + clk->shift = 20; + clk->mult = div_sc(mpcore_timer_rate, NSEC_PER_SEC, clk->shift); + clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); + clk->min_delta_ns = clockevent_delta2ns(0xf, clk); + + /* Make sure our local interrupt controller has this enabled */ + local_irq_save(flags); + get_irq_chip(IRQ_LOCALTIMER)->unmask(IRQ_LOCALTIMER); + local_irq_restore(flags); + + clockevents_register_device(clk); +} + +/* + * take a local timer down + */ +void __cpuexit local_timer_stop(void) { - evt->irq = IRQ_LOCALTIMER; - twd_timer_setup(evt); + __raw_writel(0, twd_base + TWD_TIMER_CONTROL); } + +#else /* CONFIG_LOCAL_TIMERS */ + +static void dummy_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ +} + +void __cpuinit local_timer_setup(void) +{ + unsigned int cpu = smp_processor_id(); + struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); + + clk->name = "dummy_timer"; + clk->features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_DUMMY; + clk->rating = 400; + clk->mult = 1; + clk->set_mode = dummy_timer_set_mode; + clk->broadcast = smp_timer_broadcast; + clk->cpumask = cpumask_of(cpu); + + clockevents_register_device(clk); +} + +#endif /* !CONFIG_LOCAL_TIMERS */ diff --git a/trunk/arch/arm/mach-realview/platsmp.c b/trunk/arch/arm/mach-realview/platsmp.c index ca742172ea78..30a9c68591f6 100644 --- a/trunk/arch/arm/mach-realview/platsmp.c +++ b/trunk/arch/arm/mach-realview/platsmp.c @@ -19,11 +19,10 @@ #include #include #include -#include #include #include -#include +#include #include "core.h" @@ -45,12 +44,31 @@ static void __iomem *scu_base_addr(void) return (void __iomem *)0; } -static inline unsigned int get_core_count(void) +static unsigned int __init get_core_count(void) { + unsigned int ncores; void __iomem *scu_base = scu_base_addr(); - if (scu_base) - return scu_get_core_count(scu_base); - return 1; + + if (scu_base) { + ncores = __raw_readl(scu_base + SCU_CONFIG); + ncores = (ncores & 0x03) + 1; + } else + ncores = 1; + + return ncores; +} + +/* + * Setup the SCU + */ +static void scu_enable(void) +{ + u32 scu_ctrl; + void __iomem *scu_base = scu_base_addr(); + + scu_ctrl = __raw_readl(scu_base + SCU_CTRL); + scu_ctrl |= 1; + __raw_writel(scu_ctrl, scu_base + SCU_CTRL); } static DEFINE_SPINLOCK(boot_lock); @@ -166,7 +184,7 @@ void __init smp_init_cpus(void) unsigned int i, ncores = get_core_count(); for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); + cpu_set(i, cpu_possible_map); } void __init smp_prepare_cpus(unsigned int max_cpus) @@ -199,12 +217,19 @@ void __init smp_prepare_cpus(unsigned int max_cpus) if (max_cpus > ncores) max_cpus = ncores; +#if defined(CONFIG_LOCAL_TIMERS) || defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) + /* + * Enable the local timer or broadcast device for the boot CPU. + */ + local_timer_setup(); +#endif + /* * Initialise the present map, which describes the set of CPUs * actually populated at the present time. */ for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); + cpu_set(i, cpu_present_map); /* * Initialise the SCU if there are more than one CPU and let @@ -214,13 +239,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) * WFI */ if (max_cpus > 1) { - /* - * Enable the local timer or broadcast device for the - * boot CPU, but only if we have more than one CPU. - */ - percpu_timer_setup(); - - scu_enable(scu_base_addr()); + scu_enable(); poke_milo(); } } diff --git a/trunk/arch/arm/mach-realview/realview_eb.c b/trunk/arch/arm/mach-realview/realview_eb.c index 8dfa44e08a94..c20fbef122b3 100644 --- a/trunk/arch/arm/mach-realview/realview_eb.c +++ b/trunk/arch/arm/mach-realview/realview_eb.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include diff --git a/trunk/arch/arm/mach-realview/realview_pb11mp.c b/trunk/arch/arm/mach-realview/realview_pb11mp.c index dc4b16943907..ea1e60eca359 100644 --- a/trunk/arch/arm/mach-realview/realview_pb11mp.c +++ b/trunk/arch/arm/mach-realview/realview_pb11mp.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include diff --git a/trunk/arch/arm/mach-s3c2400/gpio.c b/trunk/arch/arm/mach-s3c2400/gpio.c index 6c68e78f3595..7a7ed4174c8c 100644 --- a/trunk/arch/arm/mach-s3c2400/gpio.c +++ b/trunk/arch/arm/mach-s3c2400/gpio.c @@ -33,10 +33,10 @@ int s3c2400_gpio_getirq(unsigned int pin) { - if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7)) - return -EINVAL; /* not valid interrupts */ + if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7) + return -1; /* not valid interrupts */ - return (pin - S3C2410_GPE(0)) + IRQ_EINT0; + return (pin - S3C2410_GPE0) + IRQ_EINT0; } EXPORT_SYMBOL(s3c2400_gpio_getirq); diff --git a/trunk/arch/arm/mach-s3c2410/Kconfig b/trunk/arch/arm/mach-s3c2410/Kconfig index 41bb65d5b91f..63a30d1dd425 100644 --- a/trunk/arch/arm/mach-s3c2410/Kconfig +++ b/trunk/arch/arm/mach-s3c2410/Kconfig @@ -59,7 +59,6 @@ config ARCH_H1940 bool "IPAQ H1940" select CPU_S3C2410 select PM_H1940 if PM - select S3C_DEV_USB_HOST help Say Y here if you are using the HP IPAQ H1940 @@ -71,7 +70,6 @@ config PM_H1940 config MACH_N30 bool "Acer N30 family" select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you want suppt for the Acer N30, Acer N35, Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. @@ -84,7 +82,6 @@ config ARCH_BAST select MACH_BAST_IDE select S3C24XX_DCLK select ISA - select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec Electronics EB2410ITX development board (also known as BAST) @@ -92,7 +89,6 @@ config ARCH_BAST config MACH_OTOM bool "NexVision OTOM Board" select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you are using the Nex Vision OTOM board @@ -100,7 +96,6 @@ config MACH_AML_M5900 bool "AML M5900 Series" select CPU_S3C2410 select PM_SIMTEC if PM - select S3C_DEV_USB_HOST help Say Y here if you are using the American Microsystems M5900 Series @@ -116,7 +111,6 @@ config BAST_PC104_IRQ config MACH_TCT_HAMMER bool "TCT Hammer Board" select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you are using the TinCanTools Hammer Board @@ -128,14 +122,12 @@ config MACH_VR1000 select SIMTEC_NOR select MACH_BAST_IDE select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you are using the Thorcom VR1000 board. config MACH_QT2410 bool "QT2410" select CPU_S3C2410 - select S3C_DEV_USB_HOST help Say Y here if you are using the Armzone QT2410 diff --git a/trunk/arch/arm/mach-s3c2410/dma.c b/trunk/arch/arm/mach-s3c2410/dma.c index dbf96e60d992..440c014e24b3 100644 --- a/trunk/arch/arm/mach-s3c2410/dma.c +++ b/trunk/arch/arm/mach-s3c2410/dma.c @@ -17,16 +17,14 @@ #include #include -#include #include #include -#include +#include #include #include #include -#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c2410/gpio.c b/trunk/arch/arm/mach-s3c2410/gpio.c index 7974afca297c..36a3132f39e7 100644 --- a/trunk/arch/arm/mach-s3c2410/gpio.c +++ b/trunk/arch/arm/mach-s3c2410/gpio.c @@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, unsigned long flags; unsigned long val; - if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15)) - return -EINVAL; + if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15) + return -1; config &= 0xff; - pin -= S3C2410_GPG(8); + pin -= S3C2410_GPG8; reg += pin & ~3; local_irq_save(flags); diff --git a/trunk/arch/arm/mach-s3c2410/h1940-bluetooth.c b/trunk/arch/arm/mach-s3c2410/h1940-bluetooth.c index 5aabf117cbb0..5a6bc56f186b 100644 --- a/trunk/arch/arm/mach-s3c2410/h1940-bluetooth.c +++ b/trunk/arch/arm/mach-s3c2410/h1940-bluetooth.c @@ -16,8 +16,6 @@ #include #include #include -#include - #include #include #include @@ -43,9 +41,9 @@ static void h1940bt_enable(int on) h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); /* Reset the chip */ mdelay(10); - s3c2410_gpio_setpin(S3C2410_GPH(1), 1); + s3c2410_gpio_setpin(S3C2410_GPH1, 1); mdelay(10); - s3c2410_gpio_setpin(S3C2410_GPH(1), 0); + s3c2410_gpio_setpin(S3C2410_GPH1, 0); state = 1; } @@ -54,9 +52,9 @@ static void h1940bt_enable(int on) led_trigger_event(bt_led_trigger, 0); #endif - s3c2410_gpio_setpin(S3C2410_GPH(1), 1); + s3c2410_gpio_setpin(S3C2410_GPH1, 1); mdelay(10); - s3c2410_gpio_setpin(S3C2410_GPH(1), 0); + s3c2410_gpio_setpin(S3C2410_GPH1, 0); mdelay(10); h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); @@ -89,14 +87,14 @@ static DEVICE_ATTR(enable, 0644, static int __init h1940bt_probe(struct platform_device *pdev) { /* Configures BT serial port GPIOs */ - s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0); - s3c2410_gpio_pullup(S3C2410_GPH(0), 1); - s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_pullup(S3C2410_GPH(1), 1); - s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0); - s3c2410_gpio_pullup(S3C2410_GPH(2), 1); - s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); - s3c2410_gpio_pullup(S3C2410_GPH(3), 1); + s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0); + s3c2410_gpio_pullup(S3C2410_GPH0, 1); + s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP); + s3c2410_gpio_pullup(S3C2410_GPH1, 1); + s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0); + s3c2410_gpio_pullup(S3C2410_GPH2, 1); + s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0); + s3c2410_gpio_pullup(S3C2410_GPH3, 1); #ifdef CONFIG_LEDS_H1940 led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger); diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/dma.h b/trunk/arch/arm/mach-s3c2410/include/mach/dma.h index c3a2629e0ded..13358ce2128c 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/dma.h @@ -3,7 +3,7 @@ * Copyright (C) 2003,2004,2006 Simtec Electronics * Ben Dooks * - * Samsung S3C24XX DMA support + * Samsung S3C241XX DMA support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -13,8 +13,8 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H __FILE__ -#include #include +#include #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ @@ -55,9 +55,9 @@ enum dma_ch { /* we have 4 dma channels */ #ifndef CONFIG_CPU_S3C2443 -#define S3C_DMA_CHANNELS (4) +#define S3C2410_DMA_CHANNELS (4) #else -#define S3C_DMA_CHANNELS (6) +#define S3C2410_DMA_CHANNELS (6) #endif /* types */ @@ -68,6 +68,7 @@ enum s3c2410_dma_state { S3C2410_DMA_PAUSED }; + /* enum s3c2410_dma_loadst * * This represents the state of the DMA engine, wrt to the loaded / running @@ -103,6 +104,32 @@ enum s3c2410_dma_loadst { S3C2410_DMALOAD_1LOADED_1RUNNING, }; +enum s3c2410_dma_buffresult { + S3C2410_RES_OK, + S3C2410_RES_ERR, + S3C2410_RES_ABORT +}; + +enum s3c2410_dmasrc { + S3C2410_DMASRC_HW, /* source is memory */ + S3C2410_DMASRC_MEM /* source is hardware */ +}; + +/* enum s3c2410_chan_op + * + * operation codes passed to the DMA code by the user, and also used + * to inform the current channel owner of any changes to the system state +*/ + +enum s3c2410_chan_op { + S3C2410_DMAOP_START, + S3C2410_DMAOP_STOP, + S3C2410_DMAOP_PAUSE, + S3C2410_DMAOP_RESUME, + S3C2410_DMAOP_FLUSH, + S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ + S3C2410_DMAOP_STARTED, /* indicate channel started */ +}; /* flags */ @@ -112,14 +139,17 @@ enum s3c2410_dma_loadst { /* dma buffer */ -struct s3c2410_dma_buf; +struct s3c2410_dma_client { + char *name; +}; -/* s3c2410_dma_buf +/* s3c2410_dma_buf_s * * internally used buffer structure to describe a queued or running * buffer. */ +struct s3c2410_dma_buf; struct s3c2410_dma_buf { struct s3c2410_dma_buf *next; int magic; /* magic */ @@ -131,6 +161,20 @@ struct s3c2410_dma_buf { /* [1] is this updated for both recv/send modes? */ +struct s3c2410_dma_chan; + +/* s3c2410_dma_cbfn_t + * + * buffer callback routine type +*/ + +typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *, + void *buf, int size, + enum s3c2410_dma_buffresult result); + +typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *, + enum s3c2410_chan_op ); + struct s3c2410_dma_stats { unsigned long loads; unsigned long timeout_longest; @@ -162,10 +206,10 @@ struct s3c2410_dma_chan { /* channel configuration */ enum s3c2410_dmasrc source; - enum dma_ch req_ch; unsigned long dev_addr; unsigned long load_timeout; unsigned int flags; /* channel flags */ + unsigned int hw_cfg; /* last hw config */ struct s3c24xx_dma_map *map; /* channel hw maps */ @@ -192,6 +236,213 @@ struct s3c2410_dma_chan { struct sys_device dev; }; +/* the currently allocated channel information */ +extern struct s3c2410_dma_chan s3c2410_chans[]; + +/* note, we don't really use dma_device_t at the moment */ typedef unsigned long dma_device_t; +/* functions --------------------------------------------------------------- */ + +/* s3c2410_dma_request + * + * request a dma channel exclusivley +*/ + +extern int s3c2410_dma_request(unsigned int channel, + struct s3c2410_dma_client *, void *dev); + + +/* s3c2410_dma_ctrl + * + * change the state of the dma channel +*/ + +extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op); + +/* s3c2410_dma_setflags + * + * set the channel's flags to a given state +*/ + +extern int s3c2410_dma_setflags(unsigned int channel, + unsigned int flags); + +/* s3c2410_dma_free + * + * free the dma channel (will also abort any outstanding operations) +*/ + +extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *); + +/* s3c2410_dma_enqueue + * + * place the given buffer onto the queue of operations for the channel. + * The buffer must be allocated from dma coherent memory, or the Dcache/WB + * drained before the buffer is given to the DMA system. +*/ + +extern int s3c2410_dma_enqueue(unsigned int channel, void *id, + dma_addr_t data, int size); + +/* s3c2410_dma_config + * + * configure the dma channel +*/ + +extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon); + +/* s3c2410_dma_devconfig + * + * configure the device we're talking to +*/ + +extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, + int hwcfg, unsigned long devaddr); + +/* s3c2410_dma_getposition + * + * get the position that the dma transfer is currently at +*/ + +extern int s3c2410_dma_getposition(unsigned int channel, + dma_addr_t *src, dma_addr_t *dest); + +extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn); +extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn); + +/* DMA Register definitions */ + +#define S3C2410_DMA_DISRC (0x00) +#define S3C2410_DMA_DISRCC (0x04) +#define S3C2410_DMA_DIDST (0x08) +#define S3C2410_DMA_DIDSTC (0x0C) +#define S3C2410_DMA_DCON (0x10) +#define S3C2410_DMA_DSTAT (0x14) +#define S3C2410_DMA_DCSRC (0x18) +#define S3C2410_DMA_DCDST (0x1C) +#define S3C2410_DMA_DMASKTRIG (0x20) +#define S3C2412_DMA_DMAREQSEL (0x24) +#define S3C2443_DMA_DMAREQSEL (0x24) + +#define S3C2410_DISRCC_INC (1<<0) +#define S3C2410_DISRCC_APB (1<<1) + +#define S3C2410_DMASKTRIG_STOP (1<<2) +#define S3C2410_DMASKTRIG_ON (1<<1) +#define S3C2410_DMASKTRIG_SWTRIG (1<<0) + +#define S3C2410_DCON_DEMAND (0<<31) +#define S3C2410_DCON_HANDSHAKE (1<<31) +#define S3C2410_DCON_SYNC_PCLK (0<<30) +#define S3C2410_DCON_SYNC_HCLK (1<<30) + +#define S3C2410_DCON_INTREQ (1<<29) + +#define S3C2410_DCON_CH0_XDREQ0 (0<<24) +#define S3C2410_DCON_CH0_UART0 (1<<24) +#define S3C2410_DCON_CH0_SDI (2<<24) +#define S3C2410_DCON_CH0_TIMER (3<<24) +#define S3C2410_DCON_CH0_USBEP1 (4<<24) + +#define S3C2410_DCON_CH1_XDREQ1 (0<<24) +#define S3C2410_DCON_CH1_UART1 (1<<24) +#define S3C2410_DCON_CH1_I2SSDI (2<<24) +#define S3C2410_DCON_CH1_SPI (3<<24) +#define S3C2410_DCON_CH1_USBEP2 (4<<24) + +#define S3C2410_DCON_CH2_I2SSDO (0<<24) +#define S3C2410_DCON_CH2_I2SSDI (1<<24) +#define S3C2410_DCON_CH2_SDI (2<<24) +#define S3C2410_DCON_CH2_TIMER (3<<24) +#define S3C2410_DCON_CH2_USBEP3 (4<<24) + +#define S3C2410_DCON_CH3_UART2 (0<<24) +#define S3C2410_DCON_CH3_SDI (1<<24) +#define S3C2410_DCON_CH3_SPI (2<<24) +#define S3C2410_DCON_CH3_TIMER (3<<24) +#define S3C2410_DCON_CH3_USBEP4 (4<<24) + +#define S3C2410_DCON_SRCSHIFT (24) +#define S3C2410_DCON_SRCMASK (7<<24) + +#define S3C2410_DCON_BYTE (0<<20) +#define S3C2410_DCON_HALFWORD (1<<20) +#define S3C2410_DCON_WORD (2<<20) + +#define S3C2410_DCON_AUTORELOAD (0<<22) +#define S3C2410_DCON_NORELOAD (1<<22) +#define S3C2410_DCON_HWTRIG (1<<23) + +#ifdef CONFIG_CPU_S3C2440 +#define S3C2440_DIDSTC_CHKINT (1<<2) + +#define S3C2440_DCON_CH0_I2SSDO (5<<24) +#define S3C2440_DCON_CH0_PCMIN (6<<24) + +#define S3C2440_DCON_CH1_PCMOUT (5<<24) +#define S3C2440_DCON_CH1_SDI (6<<24) + +#define S3C2440_DCON_CH2_PCMIN (5<<24) +#define S3C2440_DCON_CH2_MICIN (6<<24) + +#define S3C2440_DCON_CH3_MICIN (5<<24) +#define S3C2440_DCON_CH3_PCMOUT (6<<24) +#endif + +#ifdef CONFIG_CPU_S3C2412 + +#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) + +#define S3C2412_DMAREQSEL_HW (1) + +#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0) +#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1) +#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2) +#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3) +#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4) +#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5) +#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9) +#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10) +#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13) +#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14) +#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15) +#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16) +#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17) +#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18) +#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19) +#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20) +#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21) +#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) +#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) +#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) + +#endif + +#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) + +#define S3C2443_DMAREQSEL_HW (1) + +#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0) +#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1) +#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2) +#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3) +#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4) +#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5) +#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9) +#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10) +#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17) +#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18) +#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19) +#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20) +#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21) +#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22) +#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23) +#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24) +#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) +#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) +#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) +#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) +#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) + #endif /* __ASM_ARCH_DMA_H */ diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/trunk/arch/arm/mach-s3c2410/include/mach/gpio-core.h index 8fe192081d3a..6c9fbb99ef14 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/gpio-core.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/gpio-core.h @@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) { struct s3c_gpio_chip *chip; - if (pin > S3C2410_GPG(10)) + if (pin > S3C2410_GPG10) return NULL; chip = &s3c24xx_gpios[pin/32]; diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/trunk/arch/arm/mach-s3c2410/include/mach/gpio-fns.h deleted file mode 100644 index 801dff13858d..000000000000 --- a/trunk/arch/arm/mach-s3c2410/include/mach/gpio-fns.h +++ /dev/null @@ -1,103 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h - * - * Copyright (c) 2003,2009 Simtec Electronics - * Ben Dooks - * - * S3C2410 - hardware - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* These functions are in the to-be-removed category and it is strongly - * encouraged not to use these in new code. They will be marked deprecated - * very soon. - * - * Most of the functionality can be either replaced by the gpiocfg calls - * for the s3c platform or by the generic GPIOlib API. -*/ - -/* external functions for GPIO support - * - * These allow various different clients to access the same GPIO - * registers without conflicting. If your driver only owns the entire - * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. -*/ - -/* s3c2410_gpio_cfgpin - * - * set the configuration of the given pin to the value passed. - * - * eg: - * s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0); - * s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); -*/ - -extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); - -extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); - -/* s3c2410_gpio_getirq - * - * turn the given pin number into the corresponding IRQ number - * - * returns: - * < 0 = no interrupt for this pin - * >=0 = interrupt number for the pin -*/ - -extern int s3c2410_gpio_getirq(unsigned int pin); - -#ifdef CONFIG_CPU_S3C2400 - -extern int s3c2400_gpio_getirq(unsigned int pin); - -#endif /* CONFIG_CPU_S3C2400 */ - -/* s3c2410_gpio_irqfilter - * - * set the irq filtering on the given pin - * - * on = 0 => disable filtering - * 1 => enable filtering - * - * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with - * width of filter (0 through 63) - * - * -*/ - -extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, - unsigned int config); - -/* s3c2410_gpio_pullup - * - * configure the pull-up control on the given pin - * - * to = 1 => disable the pull-up - * 0 => enable the pull-up - * - * eg; - * - * s3c2410_gpio_pullup(S3C2410_GPB(0), 0); - * s3c2410_gpio_pullup(S3C2410_GPE(8), 0); -*/ - -extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); - -/* s3c2410_gpio_getpull - * - * Read the state of the pull-up on a given pin - * - * return: - * < 0 => error code - * 0 => enabled - * 1 => disabled -*/ - -extern int s3c2410_gpio_getpull(unsigned int pin); - -extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); - -extern unsigned int s3c2410_gpio_getpin(unsigned int pin); diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/trunk/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h index 2edbb9c88ab3..ce1ec69806a1 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h @@ -11,9 +11,6 @@ * published by the Free Software Foundation. */ -#ifndef __MACH_GPIONRS_H -#define __MACH_GPIONRS_H - #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) #define S3C2410_GPIO_BANKA (32*0) @@ -24,70 +21,3 @@ #define S3C2410_GPIO_BANKF (32*5) #define S3C2410_GPIO_BANKG (32*6) #define S3C2410_GPIO_BANKH (32*7) - -/* GPIO bank sizes */ -#define S3C2410_GPIO_A_NR (32) -#define S3C2410_GPIO_B_NR (32) -#define S3C2410_GPIO_C_NR (32) -#define S3C2410_GPIO_D_NR (32) -#define S3C2410_GPIO_E_NR (32) -#define S3C2410_GPIO_F_NR (32) -#define S3C2410_GPIO_G_NR (32) -#define S3C2410_GPIO_H_NR (32) - -#if CONFIG_S3C_GPIO_SPACE != 0 -#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment -#endif - -#define S3C2410_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) - -#ifndef __ASSEMBLY__ - -enum s3c_gpio_number { - S3C2410_GPIO_A_START = 0, - S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), - S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), - S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), - S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), - S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), - S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), - S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), -}; - -#endif /* __ASSEMBLY__ */ - -/* S3C2410 GPIO number definitions. */ - -#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) -#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) -#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) -#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) -#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) -#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) -#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) -#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) - -/* compatibility until drivers can be modified */ - -#define S3C2410_GPA0 S3C2410_GPA(0) -#define S3C2410_GPA1 S3C2410_GPA(1) -#define S3C2410_GPA3 S3C2410_GPA(3) -#define S3C2410_GPA7 S3C2410_GPA(7) - -#define S3C2410_GPE0 S3C2410_GPE(0) -#define S3C2410_GPE1 S3C2410_GPE(1) -#define S3C2410_GPE2 S3C2410_GPE(2) -#define S3C2410_GPE3 S3C2410_GPE(3) -#define S3C2410_GPE4 S3C2410_GPE(4) -#define S3C2410_GPE5 S3C2410_GPE(5) -#define S3C2410_GPE6 S3C2410_GPE(6) -#define S3C2410_GPE7 S3C2410_GPE(7) -#define S3C2410_GPE8 S3C2410_GPE(8) -#define S3C2410_GPE9 S3C2410_GPE(9) -#define S3C2410_GPE10 S3C2410_GPE(10) - -#define S3C2410_GPH10 S3C2410_GPH(10) - -#endif /* __MACH_GPIONRS_H */ - diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/gpio.h b/trunk/arch/arm/mach-s3c2410/include/mach/gpio.h index 15f0b3e7ce69..51a88cf9526b 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/gpio.h @@ -24,6 +24,5 @@ #include #include -#include #define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/hardware.h b/trunk/arch/arm/mach-s3c2410/include/mach/hardware.h index aef5631eac58..74d5a1a4024c 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/hardware.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/hardware.h @@ -15,6 +15,101 @@ #ifndef __ASSEMBLY__ +/* external functions for GPIO support + * + * These allow various different clients to access the same GPIO + * registers without conflicting. If your driver only owns the entire + * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. +*/ + +/* s3c2410_gpio_cfgpin + * + * set the configuration of the given pin to the value passed. + * + * eg: + * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); + * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); +*/ + +extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); + +extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); + +/* s3c2410_gpio_getirq + * + * turn the given pin number into the corresponding IRQ number + * + * returns: + * < 0 = no interrupt for this pin + * >=0 = interrupt number for the pin +*/ + +extern int s3c2410_gpio_getirq(unsigned int pin); + +/* s3c2410_gpio_irq2pin + * + * turn the given irq number into the corresponding GPIO number + * + * returns: + * < 0 = no pin + * >=0 = gpio pin number +*/ + +extern int s3c2410_gpio_irq2pin(unsigned int irq); + +#ifdef CONFIG_CPU_S3C2400 + +extern int s3c2400_gpio_getirq(unsigned int pin); + +#endif /* CONFIG_CPU_S3C2400 */ + +/* s3c2410_gpio_irqfilter + * + * set the irq filtering on the given pin + * + * on = 0 => disable filtering + * 1 => enable filtering + * + * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with + * width of filter (0 through 63) + * + * +*/ + +extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, + unsigned int config); + +/* s3c2410_gpio_pullup + * + * configure the pull-up control on the given pin + * + * to = 1 => disable the pull-up + * 0 => enable the pull-up + * + * eg; + * + * s3c2410_gpio_pullup(S3C2410_GPB0, 0); + * s3c2410_gpio_pullup(S3C2410_GPE8, 0); +*/ + +extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); + +/* s3c2410_gpio_getpull + * + * Read the state of the pull-up on a given pin + * + * return: + * < 0 => error code + * 0 => enabled + * 1 => disabled +*/ + +extern int s3c2410_gpio_getpull(unsigned int pin); + +extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); + +extern unsigned int s3c2410_gpio_getpin(unsigned int pin); + extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); #ifdef CONFIG_CPU_S3C2440 diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/map.h b/trunk/arch/arm/mach-s3c2410/include/mach/map.h index e99b212cb1ca..255fdfeaf957 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/map.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/map.h @@ -84,6 +84,7 @@ #define S3C24XX_PA_IRQ S3C2410_PA_IRQ #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL +#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST #define S3C24XX_PA_DMA S3C2410_PA_DMA #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR #define S3C24XX_PA_LCD S3C2410_PA_LCD @@ -101,7 +102,6 @@ #define S3C_PA_IIC S3C2410_PA_IIC #define S3C_PA_UART S3C24XX_PA_UART -#define S3C_PA_USBHOST S3C2410_PA_USBHOST #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC #endif /* __ASM_ARCH_MAP_H */ diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/trunk/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index b278d0c45ccf..35a03df473fc 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -69,58 +69,104 @@ #define S3C2400_GPACON S3C2410_GPIOREG(0x00) #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) +#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) +#define S3C2410_GPA0_OUT (0<<0) #define S3C2410_GPA0_ADDR0 (1<<0) +#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1) +#define S3C2410_GPA1_OUT (0<<1) #define S3C2410_GPA1_ADDR16 (1<<1) +#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2) +#define S3C2410_GPA2_OUT (0<<2) #define S3C2410_GPA2_ADDR17 (1<<2) +#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3) +#define S3C2410_GPA3_OUT (0<<3) #define S3C2410_GPA3_ADDR18 (1<<3) +#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4) +#define S3C2410_GPA4_OUT (0<<4) #define S3C2410_GPA4_ADDR19 (1<<4) +#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5) +#define S3C2410_GPA5_OUT (0<<5) #define S3C2410_GPA5_ADDR20 (1<<5) +#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6) +#define S3C2410_GPA6_OUT (0<<6) #define S3C2410_GPA6_ADDR21 (1<<6) +#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7) +#define S3C2410_GPA7_OUT (0<<7) #define S3C2410_GPA7_ADDR22 (1<<7) +#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8) +#define S3C2410_GPA8_OUT (0<<8) #define S3C2410_GPA8_ADDR23 (1<<8) +#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9) +#define S3C2410_GPA9_OUT (0<<9) #define S3C2410_GPA9_ADDR24 (1<<9) +#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) +#define S3C2410_GPA10_OUT (0<<10) #define S3C2410_GPA10_ADDR25 (1<<10) #define S3C2400_GPA10_SCKE (1<<10) +#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) +#define S3C2410_GPA11_OUT (0<<11) #define S3C2410_GPA11_ADDR26 (1<<11) #define S3C2400_GPA11_nCAS0 (1<<11) +#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) +#define S3C2410_GPA12_OUT (0<<12) #define S3C2410_GPA12_nGCS1 (1<<12) #define S3C2400_GPA12_nCAS1 (1<<12) +#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) +#define S3C2410_GPA13_OUT (0<<13) #define S3C2410_GPA13_nGCS2 (1<<13) #define S3C2400_GPA13_nGCS1 (1<<13) +#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) +#define S3C2410_GPA14_OUT (0<<14) #define S3C2410_GPA14_nGCS3 (1<<14) #define S3C2400_GPA14_nGCS2 (1<<14) +#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) +#define S3C2410_GPA15_OUT (0<<15) #define S3C2410_GPA15_nGCS4 (1<<15) #define S3C2400_GPA15_nGCS3 (1<<15) +#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) +#define S3C2410_GPA16_OUT (0<<16) #define S3C2410_GPA16_nGCS5 (1<<16) #define S3C2400_GPA16_nGCS4 (1<<16) +#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) +#define S3C2410_GPA17_OUT (0<<17) #define S3C2410_GPA17_CLE (1<<17) #define S3C2400_GPA17_nGCS5 (1<<17) +#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) +#define S3C2410_GPA18_OUT (0<<18) #define S3C2410_GPA18_ALE (1<<18) +#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19) +#define S3C2410_GPA19_OUT (0<<19) #define S3C2410_GPA19_nFWE (1<<19) +#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20) +#define S3C2410_GPA20_OUT (0<<20) #define S3C2410_GPA20_nFRE (1<<20) +#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21) +#define S3C2410_GPA21_OUT (0<<21) #define S3C2410_GPA21_nRSTOUT (1<<21) +#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22) +#define S3C2410_GPA22_OUT (0<<22) #define S3C2410_GPA22_nFCE (1<<22) /* 0x08 and 0x0c are reserved on S3C2410 */ @@ -148,69 +194,107 @@ /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ +#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) +#define S3C2410_GPB0_INP (0x00 << 0) +#define S3C2410_GPB0_OUTP (0x01 << 0) #define S3C2410_GPB0_TOUT0 (0x02 << 0) #define S3C2400_GPB0_DATA16 (0x02 << 0) +#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) +#define S3C2410_GPB1_INP (0x00 << 2) +#define S3C2410_GPB1_OUTP (0x01 << 2) #define S3C2410_GPB1_TOUT1 (0x02 << 2) #define S3C2400_GPB1_DATA17 (0x02 << 2) +#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) +#define S3C2410_GPB2_INP (0x00 << 4) +#define S3C2410_GPB2_OUTP (0x01 << 4) #define S3C2410_GPB2_TOUT2 (0x02 << 4) #define S3C2400_GPB2_DATA18 (0x02 << 4) #define S3C2400_GPB2_TCLK1 (0x03 << 4) +#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) +#define S3C2410_GPB3_INP (0x00 << 6) +#define S3C2410_GPB3_OUTP (0x01 << 6) #define S3C2410_GPB3_TOUT3 (0x02 << 6) #define S3C2400_GPB3_DATA19 (0x02 << 6) #define S3C2400_GPB3_TXD1 (0x03 << 6) +#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) +#define S3C2410_GPB4_INP (0x00 << 8) +#define S3C2410_GPB4_OUTP (0x01 << 8) #define S3C2410_GPB4_TCLK0 (0x02 << 8) #define S3C2400_GPB4_DATA20 (0x02 << 8) #define S3C2410_GPB4_MASK (0x03 << 8) #define S3C2400_GPB4_RXD1 (0x03 << 8) #define S3C2400_GPB4_MASK (0x03 << 8) +#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) +#define S3C2410_GPB5_INP (0x00 << 10) +#define S3C2410_GPB5_OUTP (0x01 << 10) #define S3C2410_GPB5_nXBACK (0x02 << 10) #define S3C2443_GPB5_XBACK (0x03 << 10) #define S3C2400_GPB5_DATA21 (0x02 << 10) #define S3C2400_GPB5_nCTS1 (0x03 << 10) +#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) +#define S3C2410_GPB6_INP (0x00 << 12) +#define S3C2410_GPB6_OUTP (0x01 << 12) #define S3C2410_GPB6_nXBREQ (0x02 << 12) #define S3C2443_GPB6_XBREQ (0x03 << 12) #define S3C2400_GPB6_DATA22 (0x02 << 12) #define S3C2400_GPB6_nRTS1 (0x03 << 12) +#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) +#define S3C2410_GPB7_INP (0x00 << 14) +#define S3C2410_GPB7_OUTP (0x01 << 14) #define S3C2410_GPB7_nXDACK1 (0x02 << 14) #define S3C2443_GPB7_XDACK1 (0x03 << 14) #define S3C2400_GPB7_DATA23 (0x02 << 14) +#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) +#define S3C2410_GPB8_INP (0x00 << 16) +#define S3C2410_GPB8_OUTP (0x01 << 16) #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) #define S3C2400_GPB8_DATA24 (0x02 << 16) +#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) +#define S3C2410_GPB9_INP (0x00 << 18) +#define S3C2410_GPB9_OUTP (0x01 << 18) #define S3C2410_GPB9_nXDACK0 (0x02 << 18) #define S3C2443_GPB9_XDACK0 (0x03 << 18) #define S3C2400_GPB9_DATA25 (0x02 << 18) #define S3C2400_GPB9_I2SSDI (0x03 << 18) +#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) +#define S3C2410_GPB10_INP (0x00 << 20) +#define S3C2410_GPB10_OUTP (0x01 << 20) #define S3C2410_GPB10_nXDRE0 (0x02 << 20) #define S3C2443_GPB10_XDREQ0 (0x03 << 20) #define S3C2400_GPB10_DATA26 (0x02 << 20) #define S3C2400_GPB10_nSS (0x03 << 20) +#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11) #define S3C2400_GPB11_INP (0x00 << 22) #define S3C2400_GPB11_OUTP (0x01 << 22) #define S3C2400_GPB11_DATA27 (0x02 << 22) +#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12) #define S3C2400_GPB12_INP (0x00 << 24) #define S3C2400_GPB12_OUTP (0x01 << 24) #define S3C2400_GPB12_DATA28 (0x02 << 24) +#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13) #define S3C2400_GPB13_INP (0x00 << 26) #define S3C2400_GPB13_OUTP (0x01 << 26) #define S3C2400_GPB13_DATA29 (0x02 << 26) +#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14) #define S3C2400_GPB14_INP (0x00 << 28) #define S3C2400_GPB14_OUTP (0x01 << 28) #define S3C2400_GPB14_DATA30 (0x02 << 28) +#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15) #define S3C2400_GPB15_INP (0x00 << 30) #define S3C2400_GPB15_OUTP (0x01 << 30) #define S3C2400_GPB15_DATA31 (0x02 << 30) @@ -231,51 +315,99 @@ #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) +#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) +#define S3C2410_GPC0_INP (0x00 << 0) +#define S3C2410_GPC0_OUTP (0x01 << 0) #define S3C2410_GPC0_LEND (0x02 << 0) #define S3C2400_GPC0_VD0 (0x02 << 0) +#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) +#define S3C2410_GPC1_INP (0x00 << 2) +#define S3C2410_GPC1_OUTP (0x01 << 2) #define S3C2410_GPC1_VCLK (0x02 << 2) #define S3C2400_GPC1_VD1 (0x02 << 2) +#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) +#define S3C2410_GPC2_INP (0x00 << 4) +#define S3C2410_GPC2_OUTP (0x01 << 4) #define S3C2410_GPC2_VLINE (0x02 << 4) #define S3C2400_GPC2_VD2 (0x02 << 4) +#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) +#define S3C2410_GPC3_INP (0x00 << 6) +#define S3C2410_GPC3_OUTP (0x01 << 6) #define S3C2410_GPC3_VFRAME (0x02 << 6) #define S3C2400_GPC3_VD3 (0x02 << 6) +#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) +#define S3C2410_GPC4_INP (0x00 << 8) +#define S3C2410_GPC4_OUTP (0x01 << 8) #define S3C2410_GPC4_VM (0x02 << 8) #define S3C2400_GPC4_VD4 (0x02 << 8) +#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) +#define S3C2410_GPC5_INP (0x00 << 10) +#define S3C2410_GPC5_OUTP (0x01 << 10) #define S3C2410_GPC5_LCDVF0 (0x02 << 10) #define S3C2400_GPC5_VD5 (0x02 << 10) +#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) +#define S3C2410_GPC6_INP (0x00 << 12) +#define S3C2410_GPC6_OUTP (0x01 << 12) #define S3C2410_GPC6_LCDVF1 (0x02 << 12) #define S3C2400_GPC6_VD6 (0x02 << 12) +#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) +#define S3C2410_GPC7_INP (0x00 << 14) +#define S3C2410_GPC7_OUTP (0x01 << 14) #define S3C2410_GPC7_LCDVF2 (0x02 << 14) #define S3C2400_GPC7_VD7 (0x02 << 14) +#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) +#define S3C2410_GPC8_INP (0x00 << 16) +#define S3C2410_GPC8_OUTP (0x01 << 16) #define S3C2410_GPC8_VD0 (0x02 << 16) #define S3C2400_GPC8_VD8 (0x02 << 16) +#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) +#define S3C2410_GPC9_INP (0x00 << 18) +#define S3C2410_GPC9_OUTP (0x01 << 18) #define S3C2410_GPC9_VD1 (0x02 << 18) #define S3C2400_GPC9_VD9 (0x02 << 18) +#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) +#define S3C2410_GPC10_INP (0x00 << 20) +#define S3C2410_GPC10_OUTP (0x01 << 20) #define S3C2410_GPC10_VD2 (0x02 << 20) #define S3C2400_GPC10_VD10 (0x02 << 20) +#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) +#define S3C2410_GPC11_INP (0x00 << 22) +#define S3C2410_GPC11_OUTP (0x01 << 22) #define S3C2410_GPC11_VD3 (0x02 << 22) #define S3C2400_GPC11_VD11 (0x02 << 22) +#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) +#define S3C2410_GPC12_INP (0x00 << 24) +#define S3C2410_GPC12_OUTP (0x01 << 24) #define S3C2410_GPC12_VD4 (0x02 << 24) #define S3C2400_GPC12_VD12 (0x02 << 24) +#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) +#define S3C2410_GPC13_INP (0x00 << 26) +#define S3C2410_GPC13_OUTP (0x01 << 26) #define S3C2410_GPC13_VD5 (0x02 << 26) #define S3C2400_GPC13_VD13 (0x02 << 26) +#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) +#define S3C2410_GPC14_INP (0x00 << 28) +#define S3C2410_GPC14_OUTP (0x01 << 28) #define S3C2410_GPC14_VD6 (0x02 << 28) #define S3C2400_GPC14_VD14 (0x02 << 28) +#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) +#define S3C2410_GPC15_INP (0x00 << 30) +#define S3C2410_GPC15_OUTP (0x01 << 30) #define S3C2410_GPC15_VD7 (0x02 << 30) #define S3C2400_GPC15_VD15 (0x02 << 30) @@ -300,51 +432,99 @@ #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) +#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) +#define S3C2410_GPD0_INP (0x00 << 0) +#define S3C2410_GPD0_OUTP (0x01 << 0) #define S3C2410_GPD0_VD8 (0x02 << 0) #define S3C2400_GPD0_VFRAME (0x02 << 0) #define S3C2442_GPD0_nSPICS1 (0x03 << 0) +#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) +#define S3C2410_GPD1_INP (0x00 << 2) +#define S3C2410_GPD1_OUTP (0x01 << 2) #define S3C2410_GPD1_VD9 (0x02 << 2) #define S3C2400_GPD1_VM (0x02 << 2) #define S3C2442_GPD1_SPICLK1 (0x03 << 2) +#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) +#define S3C2410_GPD2_INP (0x00 << 4) +#define S3C2410_GPD2_OUTP (0x01 << 4) #define S3C2410_GPD2_VD10 (0x02 << 4) #define S3C2400_GPD2_VLINE (0x02 << 4) +#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) +#define S3C2410_GPD3_INP (0x00 << 6) +#define S3C2410_GPD3_OUTP (0x01 << 6) #define S3C2410_GPD3_VD11 (0x02 << 6) #define S3C2400_GPD3_VCLK (0x02 << 6) +#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) +#define S3C2410_GPD4_INP (0x00 << 8) +#define S3C2410_GPD4_OUTP (0x01 << 8) #define S3C2410_GPD4_VD12 (0x02 << 8) #define S3C2400_GPD4_LEND (0x02 << 8) +#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) +#define S3C2410_GPD5_INP (0x00 << 10) +#define S3C2410_GPD5_OUTP (0x01 << 10) #define S3C2410_GPD5_VD13 (0x02 << 10) #define S3C2400_GPD5_TOUT0 (0x02 << 10) +#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) +#define S3C2410_GPD6_INP (0x00 << 12) +#define S3C2410_GPD6_OUTP (0x01 << 12) #define S3C2410_GPD6_VD14 (0x02 << 12) #define S3C2400_GPD6_TOUT1 (0x02 << 12) +#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) +#define S3C2410_GPD7_INP (0x00 << 14) +#define S3C2410_GPD7_OUTP (0x01 << 14) #define S3C2410_GPD7_VD15 (0x02 << 14) #define S3C2400_GPD7_TOUT2 (0x02 << 14) +#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) +#define S3C2410_GPD8_INP (0x00 << 16) +#define S3C2410_GPD8_OUTP (0x01 << 16) #define S3C2410_GPD8_VD16 (0x02 << 16) #define S3C2400_GPD8_TOUT3 (0x02 << 16) +#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) +#define S3C2410_GPD9_INP (0x00 << 18) +#define S3C2410_GPD9_OUTP (0x01 << 18) #define S3C2410_GPD9_VD17 (0x02 << 18) #define S3C2400_GPD9_TCLK0 (0x02 << 18) #define S3C2410_GPD9_MASK (0x03 << 18) +#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) +#define S3C2410_GPD10_INP (0x00 << 20) +#define S3C2410_GPD10_OUTP (0x01 << 20) #define S3C2410_GPD10_VD18 (0x02 << 20) #define S3C2400_GPD10_nWAIT (0x02 << 20) +#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) +#define S3C2410_GPD11_INP (0x00 << 22) +#define S3C2410_GPD11_OUTP (0x01 << 22) #define S3C2410_GPD11_VD19 (0x02 << 22) +#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12) +#define S3C2410_GPD12_INP (0x00 << 24) +#define S3C2410_GPD12_OUTP (0x01 << 24) #define S3C2410_GPD12_VD20 (0x02 << 24) +#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13) +#define S3C2410_GPD13_INP (0x00 << 26) +#define S3C2410_GPD13_OUTP (0x01 << 26) #define S3C2410_GPD13_VD21 (0x02 << 26) +#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14) +#define S3C2410_GPD14_INP (0x00 << 28) +#define S3C2410_GPD14_OUTP (0x01 << 28) #define S3C2410_GPD14_VD22 (0x02 << 28) #define S3C2410_GPD14_nSS1 (0x03 << 28) +#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) +#define S3C2410_GPD15_INP (0x00 << 30) +#define S3C2410_GPD15_OUTP (0x01 << 30) #define S3C2410_GPD15_VD23 (0x02 << 30) #define S3C2410_GPD15_nSS0 (0x03 << 30) @@ -370,22 +550,34 @@ #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) +#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) +#define S3C2410_GPE0_INP (0x00 << 0) +#define S3C2410_GPE0_OUTP (0x01 << 0) #define S3C2410_GPE0_I2SLRCK (0x02 << 0) #define S3C2443_GPE0_AC_nRESET (0x03 << 0) #define S3C2400_GPE0_EINT0 (0x02 << 0) #define S3C2410_GPE0_MASK (0x03 << 0) +#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) +#define S3C2410_GPE1_INP (0x00 << 2) +#define S3C2410_GPE1_OUTP (0x01 << 2) #define S3C2410_GPE1_I2SSCLK (0x02 << 2) #define S3C2443_GPE1_AC_SYNC (0x03 << 2) #define S3C2400_GPE1_EINT1 (0x02 << 2) #define S3C2400_GPE1_nSS (0x03 << 2) #define S3C2410_GPE1_MASK (0x03 << 2) +#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) +#define S3C2410_GPE2_INP (0x00 << 4) +#define S3C2410_GPE2_OUTP (0x01 << 4) #define S3C2410_GPE2_CDCLK (0x02 << 4) #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) #define S3C2400_GPE2_EINT2 (0x02 << 4) #define S3C2400_GPE2_I2SSDI (0x03 << 4) +#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) +#define S3C2410_GPE3_INP (0x00 << 6) +#define S3C2410_GPE3_OUTP (0x01 << 6) #define S3C2410_GPE3_I2SSDI (0x02 << 6) #define S3C2443_GPE3_AC_SDI (0x03 << 6) #define S3C2400_GPE3_EINT3 (0x02 << 6) @@ -393,6 +585,9 @@ #define S3C2410_GPE3_nSS0 (0x03 << 6) #define S3C2410_GPE3_MASK (0x03 << 6) +#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4) +#define S3C2410_GPE4_INP (0x00 << 8) +#define S3C2410_GPE4_OUTP (0x01 << 8) #define S3C2410_GPE4_I2SSDO (0x02 << 8) #define S3C2443_GPE4_AC_SDO (0x03 << 8) #define S3C2400_GPE4_EINT4 (0x02 << 8) @@ -400,48 +595,81 @@ #define S3C2410_GPE4_I2SSDI (0x03 << 8) #define S3C2410_GPE4_MASK (0x03 << 8) +#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5) +#define S3C2410_GPE5_INP (0x00 << 10) +#define S3C2410_GPE5_OUTP (0x01 << 10) #define S3C2410_GPE5_SDCLK (0x02 << 10) #define S3C2443_GPE5_SD1_CLK (0x02 << 10) #define S3C2400_GPE5_EINT5 (0x02 << 10) #define S3C2400_GPE5_TCLK1 (0x03 << 10) +#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) +#define S3C2410_GPE6_INP (0x00 << 12) +#define S3C2410_GPE6_OUTP (0x01 << 12) #define S3C2410_GPE6_SDCMD (0x02 << 12) #define S3C2443_GPE6_SD1_CMD (0x02 << 12) #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) #define S3C2400_GPE6_EINT6 (0x02 << 12) +#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) +#define S3C2410_GPE7_INP (0x00 << 14) +#define S3C2410_GPE7_OUTP (0x01 << 14) #define S3C2410_GPE7_SDDAT0 (0x02 << 14) #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) #define S3C2443_GPE7_AC_SDI (0x03 << 14) #define S3C2400_GPE7_EINT7 (0x02 << 14) +#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) +#define S3C2410_GPE8_INP (0x00 << 16) +#define S3C2410_GPE8_OUTP (0x01 << 16) #define S3C2410_GPE8_SDDAT1 (0x02 << 16) #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) #define S3C2443_GPE8_AC_SDO (0x03 << 16) #define S3C2400_GPE8_nXDACK0 (0x02 << 16) +#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) +#define S3C2410_GPE9_INP (0x00 << 18) +#define S3C2410_GPE9_OUTP (0x01 << 18) #define S3C2410_GPE9_SDDAT2 (0x02 << 18) #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) #define S3C2443_GPE9_AC_SYNC (0x03 << 18) #define S3C2400_GPE9_nXDACK1 (0x02 << 18) #define S3C2400_GPE9_nXBACK (0x03 << 18) +#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) +#define S3C2410_GPE10_INP (0x00 << 20) +#define S3C2410_GPE10_OUTP (0x01 << 20) #define S3C2410_GPE10_SDDAT3 (0x02 << 20) #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) #define S3C2443_GPE10_AC_nRESET (0x03 << 20) #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) +#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) +#define S3C2410_GPE11_INP (0x00 << 22) +#define S3C2410_GPE11_OUTP (0x01 << 22) #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) #define S3C2400_GPE11_nXBREQ (0x03 << 22) +#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) +#define S3C2410_GPE12_INP (0x00 << 24) +#define S3C2410_GPE12_OUTP (0x01 << 24) #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) +#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13) +#define S3C2410_GPE13_INP (0x00 << 26) +#define S3C2410_GPE13_OUTP (0x01 << 26) #define S3C2410_GPE13_SPICLK0 (0x02 << 26) +#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14) +#define S3C2410_GPE14_INP (0x00 << 28) +#define S3C2410_GPE14_OUTP (0x01 << 28) #define S3C2410_GPE14_IICSCL (0x02 << 28) #define S3C2410_GPE14_MASK (0x03 << 28) +#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15) +#define S3C2410_GPE15_INP (0x00 << 30) +#define S3C2410_GPE15_OUTP (0x01 << 30) #define S3C2410_GPE15_IICSDA (0x02 << 30) #define S3C2410_GPE15_MASK (0x03 << 30) @@ -477,31 +705,55 @@ #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) +#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) +#define S3C2410_GPF0_INP (0x00 << 0) +#define S3C2410_GPF0_OUTP (0x01 << 0) #define S3C2410_GPF0_EINT0 (0x02 << 0) #define S3C2400_GPF0_RXD0 (0x02 << 0) +#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) +#define S3C2410_GPF1_INP (0x00 << 2) +#define S3C2410_GPF1_OUTP (0x01 << 2) #define S3C2410_GPF1_EINT1 (0x02 << 2) #define S3C2400_GPF1_RXD1 (0x02 << 2) #define S3C2400_GPF1_IICSDA (0x03 << 2) +#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) +#define S3C2410_GPF2_INP (0x00 << 4) +#define S3C2410_GPF2_OUTP (0x01 << 4) #define S3C2410_GPF2_EINT2 (0x02 << 4) #define S3C2400_GPF2_TXD0 (0x02 << 4) +#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) +#define S3C2410_GPF3_INP (0x00 << 6) +#define S3C2410_GPF3_OUTP (0x01 << 6) #define S3C2410_GPF3_EINT3 (0x02 << 6) #define S3C2400_GPF3_TXD1 (0x02 << 6) #define S3C2400_GPF3_IICSCL (0x03 << 6) +#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) +#define S3C2410_GPF4_INP (0x00 << 8) +#define S3C2410_GPF4_OUTP (0x01 << 8) #define S3C2410_GPF4_EINT4 (0x02 << 8) #define S3C2400_GPF4_nRTS0 (0x02 << 8) #define S3C2400_GPF4_nXBACK (0x03 << 8) +#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) +#define S3C2410_GPF5_INP (0x00 << 10) +#define S3C2410_GPF5_OUTP (0x01 << 10) #define S3C2410_GPF5_EINT5 (0x02 << 10) #define S3C2400_GPF5_nCTS0 (0x02 << 10) #define S3C2400_GPF5_nXBREQ (0x03 << 10) +#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) +#define S3C2410_GPF6_INP (0x00 << 12) +#define S3C2410_GPF6_OUTP (0x01 << 12) #define S3C2410_GPF6_EINT6 (0x02 << 12) #define S3C2400_GPF6_CLKOUT (0x02 << 12) +#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) +#define S3C2410_GPF7_INP (0x00 << 14) +#define S3C2410_GPF7_OUTP (0x01 << 14) #define S3C2410_GPF7_EINT7 (0x02 << 14) #define S3C2410_GPF_PUPDIS(x) (1<<(x)) @@ -526,69 +778,117 @@ #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) +#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) +#define S3C2410_GPG0_INP (0x00 << 0) +#define S3C2410_GPG0_OUTP (0x01 << 0) #define S3C2410_GPG0_EINT8 (0x02 << 0) #define S3C2400_GPG0_I2SLRCK (0x02 << 0) +#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) +#define S3C2410_GPG1_INP (0x00 << 2) +#define S3C2410_GPG1_OUTP (0x01 << 2) #define S3C2410_GPG1_EINT9 (0x02 << 2) #define S3C2400_GPG1_I2SSCLK (0x02 << 2) +#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) +#define S3C2410_GPG2_INP (0x00 << 4) +#define S3C2410_GPG2_OUTP (0x01 << 4) #define S3C2410_GPG2_EINT10 (0x02 << 4) #define S3C2410_GPG2_nSS0 (0x03 << 4) #define S3C2400_GPG2_CDCLK (0x02 << 4) +#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) +#define S3C2410_GPG3_INP (0x00 << 6) +#define S3C2410_GPG3_OUTP (0x01 << 6) #define S3C2410_GPG3_EINT11 (0x02 << 6) #define S3C2410_GPG3_nSS1 (0x03 << 6) #define S3C2400_GPG3_I2SSDO (0x02 << 6) #define S3C2400_GPG3_I2SSDI (0x03 << 6) +#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) +#define S3C2410_GPG4_INP (0x00 << 8) +#define S3C2410_GPG4_OUTP (0x01 << 8) #define S3C2410_GPG4_EINT12 (0x02 << 8) #define S3C2400_GPG4_MMCCLK (0x02 << 8) #define S3C2400_GPG4_I2SSDI (0x03 << 8) #define S3C2410_GPG4_LCDPWREN (0x03 << 8) #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) +#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) +#define S3C2410_GPG5_INP (0x00 << 10) +#define S3C2410_GPG5_OUTP (0x01 << 10) #define S3C2410_GPG5_EINT13 (0x02 << 10) #define S3C2400_GPG5_MMCCMD (0x02 << 10) #define S3C2400_GPG5_IICSDA (0x03 << 10) #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ +#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) +#define S3C2410_GPG6_INP (0x00 << 12) +#define S3C2410_GPG6_OUTP (0x01 << 12) #define S3C2410_GPG6_EINT14 (0x02 << 12) #define S3C2400_GPG6_MMCDAT (0x02 << 12) #define S3C2400_GPG6_IICSCL (0x03 << 12) #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) +#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) +#define S3C2410_GPG7_INP (0x00 << 14) +#define S3C2410_GPG7_OUTP (0x01 << 14) #define S3C2410_GPG7_EINT15 (0x02 << 14) #define S3C2410_GPG7_SPICLK1 (0x03 << 14) #define S3C2400_GPG7_SPIMISO (0x02 << 14) #define S3C2400_GPG7_IICSDA (0x03 << 14) +#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) +#define S3C2410_GPG8_INP (0x00 << 16) +#define S3C2410_GPG8_OUTP (0x01 << 16) #define S3C2410_GPG8_EINT16 (0x02 << 16) #define S3C2400_GPG8_SPIMOSI (0x02 << 16) #define S3C2400_GPG8_IICSCL (0x03 << 16) +#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) +#define S3C2410_GPG9_INP (0x00 << 18) +#define S3C2410_GPG9_OUTP (0x01 << 18) #define S3C2410_GPG9_EINT17 (0x02 << 18) #define S3C2400_GPG9_SPICLK (0x02 << 18) #define S3C2400_GPG9_MMCCLK (0x03 << 18) +#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) +#define S3C2410_GPG10_INP (0x00 << 20) +#define S3C2410_GPG10_OUTP (0x01 << 20) #define S3C2410_GPG10_EINT18 (0x02 << 20) +#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11) +#define S3C2410_GPG11_INP (0x00 << 22) +#define S3C2410_GPG11_OUTP (0x01 << 22) #define S3C2410_GPG11_EINT19 (0x02 << 22) #define S3C2410_GPG11_TCLK1 (0x03 << 22) #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) +#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) +#define S3C2410_GPG12_INP (0x00 << 24) +#define S3C2410_GPG12_OUTP (0x01 << 24) #define S3C2410_GPG12_EINT20 (0x02 << 24) #define S3C2410_GPG12_XMON (0x03 << 24) #define S3C2442_GPG12_nSPICS0 (0x03 << 24) #define S3C2443_GPG12_nINPACK (0x03 << 24) +#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) +#define S3C2410_GPG13_INP (0x00 << 26) +#define S3C2410_GPG13_OUTP (0x01 << 26) #define S3C2410_GPG13_EINT21 (0x02 << 26) #define S3C2410_GPG13_nXPON (0x03 << 26) #define S3C2443_GPG13_CF_nREG (0x03 << 26) +#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) +#define S3C2410_GPG14_INP (0x00 << 28) +#define S3C2410_GPG14_OUTP (0x01 << 28) #define S3C2410_GPG14_EINT22 (0x02 << 28) #define S3C2410_GPG14_YMON (0x03 << 28) #define S3C2443_GPG14_CF_RESET (0x03 << 28) +#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) +#define S3C2410_GPG15_INP (0x00 << 30) +#define S3C2410_GPG15_OUTP (0x01 << 30) #define S3C2410_GPG15_EINT23 (0x02 << 30) #define S3C2410_GPG15_nYPON (0x03 << 30) #define S3C2443_GPG15_CF_PWR (0x03 << 30) @@ -607,29 +907,62 @@ #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) +#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0) +#define S3C2410_GPH0_INP (0x00 << 0) +#define S3C2410_GPH0_OUTP (0x01 << 0) #define S3C2410_GPH0_nCTS0 (0x02 << 0) +#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1) +#define S3C2410_GPH1_INP (0x00 << 2) +#define S3C2410_GPH1_OUTP (0x01 << 2) #define S3C2410_GPH1_nRTS0 (0x02 << 2) +#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2) +#define S3C2410_GPH2_INP (0x00 << 4) +#define S3C2410_GPH2_OUTP (0x01 << 4) #define S3C2410_GPH2_TXD0 (0x02 << 4) +#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3) +#define S3C2410_GPH3_INP (0x00 << 6) +#define S3C2410_GPH3_OUTP (0x01 << 6) #define S3C2410_GPH3_RXD0 (0x02 << 6) +#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4) +#define S3C2410_GPH4_INP (0x00 << 8) +#define S3C2410_GPH4_OUTP (0x01 << 8) #define S3C2410_GPH4_TXD1 (0x02 << 8) +#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5) +#define S3C2410_GPH5_INP (0x00 << 10) +#define S3C2410_GPH5_OUTP (0x01 << 10) #define S3C2410_GPH5_RXD1 (0x02 << 10) +#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6) +#define S3C2410_GPH6_INP (0x00 << 12) +#define S3C2410_GPH6_OUTP (0x01 << 12) #define S3C2410_GPH6_TXD2 (0x02 << 12) #define S3C2410_GPH6_nRTS1 (0x03 << 12) +#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7) +#define S3C2410_GPH7_INP (0x00 << 14) +#define S3C2410_GPH7_OUTP (0x01 << 14) #define S3C2410_GPH7_RXD2 (0x02 << 14) #define S3C2410_GPH7_nCTS1 (0x03 << 14) +#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8) +#define S3C2410_GPH8_INP (0x00 << 16) +#define S3C2410_GPH8_OUTP (0x01 << 16) #define S3C2410_GPH8_UCLK (0x02 << 16) +#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9) +#define S3C2410_GPH9_INP (0x00 << 18) +#define S3C2410_GPH9_OUTP (0x01 << 18) #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) #define S3C2442_GPH9_nSPICS0 (0x03 << 18) +#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) +#define S3C2410_GPH10_INP (0x00 << 20) +#define S3C2410_GPH10_OUTP (0x01 << 20) #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) /* The S3C2412 and S3C2413 move the GPJ register set to after diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/system-reset.h b/trunk/arch/arm/mach-s3c2410/include/mach/system-reset.h index 6faadcee7729..b8687f71c304 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/system-reset.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/system-reset.h @@ -11,13 +11,21 @@ */ #include -#include +#include + +#include +#include + +#include +#include extern void (*s3c24xx_reset_hook)(void); static void arch_reset(char mode, const char *cmd) { + struct clk *wdtclk; + if (mode == 's') { cpu_reset(0); } @@ -25,7 +33,31 @@ arch_reset(char mode, const char *cmd) if (s3c24xx_reset_hook) s3c24xx_reset_hook(); - arch_wdt_reset(); + printk("arch_reset: attempting watchdog reset\n"); + + __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ + + wdtclk = clk_get(NULL, "watchdog"); + if (!IS_ERR(wdtclk)) { + clk_enable(wdtclk); + } else + printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); + + /* put initial values into count and data */ + __raw_writel(0x80, S3C2410_WTCNT); + __raw_writel(0x80, S3C2410_WTDAT); + + /* set the watchdog to go and reset... */ + __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | + S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); + + /* wait for reset to assert... */ + mdelay(500); + + printk(KERN_ERR "Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); /* we'll take a jump through zero as a poor second */ cpu_reset(0); diff --git a/trunk/arch/arm/mach-s3c2410/mach-amlm5900.c b/trunk/arch/arm/mach-s3c2410/mach-amlm5900.c index 06a84adfb13f..6d6995afeb43 100644 --- a/trunk/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/trunk/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -225,8 +224,8 @@ static void amlm5900_init_pm(void) } else { enable_irq_wake(IRQ_EINT9); /* configure the suspend/resume status pin */ - s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_pullup(S3C2410_GPF(2), 0); + s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); + s3c2410_gpio_pullup(S3C2410_GPF2, 0); } } static void __init amlm5900_init(void) diff --git a/trunk/arch/arm/mach-s3c2410/mach-bast.c b/trunk/arch/arm/mach-s3c2410/mach-bast.c index ce3baba2cd7f..8637dea5e150 100644 --- a/trunk/arch/arm/mach-s3c2410/mach-bast.c +++ b/trunk/arch/arm/mach-s3c2410/mach-bast.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -213,15 +212,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) { /* ensure that an nRESET is not generated on resume. */ - s3c2410_gpio_setpin(S3C2410_GPA(21), 1); - s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPA21, 1); + s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); return 0; } static int bast_pm_resume(struct sys_device *sd) { - s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); + s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); return 0; } @@ -592,6 +591,8 @@ static void __init bast_map_io(void) s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); + + usb_simtec_init(); } static void __init bast_init(void) @@ -606,7 +607,6 @@ static void __init bast_init(void) i2c_register_board_info(0, bast_i2c_devs, ARRAY_SIZE(bast_i2c_devs)); - usb_simtec_init(); nor_simtec_init(); } diff --git a/trunk/arch/arm/mach-s3c2410/mach-h1940.c b/trunk/arch/arm/mach-s3c2410/mach-h1940.c index d9cd5ddecf4a..7a7c4da4c256 100644 --- a/trunk/arch/arm/mach-s3c2410/mach-h1940.c +++ b/trunk/arch/arm/mach-s3c2410/mach-h1940.c @@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd) static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = { .udc_command = h1940_udc_pullup, - .vbus_pin = S3C2410_GPG(5), + .vbus_pin = S3C2410_GPG5, .vbus_pin_inverted = 1, }; diff --git a/trunk/arch/arm/mach-s3c2410/mach-n30.c b/trunk/arch/arm/mach-s3c2410/mach-n30.c index 0f6ed61af415..2b83f8707710 100644 --- a/trunk/arch/arm/mach-s3c2410/mach-n30.c +++ b/trunk/arch/arm/mach-s3c2410/mach-n30.c @@ -19,7 +19,6 @@ #include #include -#include #include #include #include @@ -86,10 +85,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd) { switch (cmd) { case S3C2410_UDC_P_ENABLE : - s3c2410_gpio_setpin(S3C2410_GPB(3), 1); + s3c2410_gpio_setpin(S3C2410_GPB3, 1); break; case S3C2410_UDC_P_DISABLE : - s3c2410_gpio_setpin(S3C2410_GPB(3), 0); + s3c2410_gpio_setpin(S3C2410_GPB3, 0); break; case S3C2410_UDC_P_RESET : break; @@ -100,55 +99,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd) static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = { .udc_command = n30_udc_pullup, - .vbus_pin = S3C2410_GPG(1), + .vbus_pin = S3C2410_GPG1, .vbus_pin_inverted = 0, }; static struct gpio_keys_button n30_buttons[] = { { - .gpio = S3C2410_GPF(0), + .gpio = S3C2410_GPF0, .code = KEY_POWER, .desc = "Power", .active_low = 0, }, { - .gpio = S3C2410_GPG(9), + .gpio = S3C2410_GPG9, .code = KEY_UP, .desc = "Thumbwheel Up", .active_low = 0, }, { - .gpio = S3C2410_GPG(8), + .gpio = S3C2410_GPG8, .code = KEY_DOWN, .desc = "Thumbwheel Down", .active_low = 0, }, { - .gpio = S3C2410_GPG(7), + .gpio = S3C2410_GPG7, .code = KEY_ENTER, .desc = "Thumbwheel Press", .active_low = 0, }, { - .gpio = S3C2410_GPF(7), + .gpio = S3C2410_GPF7, .code = KEY_HOMEPAGE, .desc = "Home", .active_low = 0, }, { - .gpio = S3C2410_GPF(6), + .gpio = S3C2410_GPF6, .code = KEY_CALENDAR, .desc = "Calendar", .active_low = 0, }, { - .gpio = S3C2410_GPF(5), + .gpio = S3C2410_GPF5, .code = KEY_ADDRESSBOOK, .desc = "Contacts", .active_low = 0, }, { - .gpio = S3C2410_GPF(4), + .gpio = S3C2410_GPF4, .code = KEY_MAIL, .desc = "Mail", .active_low = 0, @@ -170,73 +169,73 @@ static struct platform_device n30_button_device = { static struct gpio_keys_button n35_buttons[] = { { - .gpio = S3C2410_GPF(0), + .gpio = S3C2410_GPF0, .code = KEY_POWER, .desc = "Power", .active_low = 0, }, { - .gpio = S3C2410_GPG(9), + .gpio = S3C2410_GPG9, .code = KEY_UP, .desc = "Joystick Up", .active_low = 0, }, { - .gpio = S3C2410_GPG(8), + .gpio = S3C2410_GPG8, .code = KEY_DOWN, .desc = "Joystick Down", .active_low = 0, }, { - .gpio = S3C2410_GPG(6), + .gpio = S3C2410_GPG6, .code = KEY_DOWN, .desc = "Joystick Left", .active_low = 0, }, { - .gpio = S3C2410_GPG(5), + .gpio = S3C2410_GPG5, .code = KEY_DOWN, .desc = "Joystick Right", .active_low = 0, }, { - .gpio = S3C2410_GPG(7), + .gpio = S3C2410_GPG7, .code = KEY_ENTER, .desc = "Joystick Press", .active_low = 0, }, { - .gpio = S3C2410_GPF(7), + .gpio = S3C2410_GPF7, .code = KEY_HOMEPAGE, .desc = "Home", .active_low = 0, }, { - .gpio = S3C2410_GPF(6), + .gpio = S3C2410_GPF6, .code = KEY_CALENDAR, .desc = "Calendar", .active_low = 0, }, { - .gpio = S3C2410_GPF(5), + .gpio = S3C2410_GPF5, .code = KEY_ADDRESSBOOK, .desc = "Contacts", .active_low = 0, }, { - .gpio = S3C2410_GPF(4), + .gpio = S3C2410_GPF4, .code = KEY_MAIL, .desc = "Mail", .active_low = 0, }, { - .gpio = S3C2410_GPF(3), + .gpio = S3C2410_GPF3, .code = SW_RADIO, .desc = "GPS Antenna", .active_low = 0, }, { - .gpio = S3C2410_GPG(2), + .gpio = S3C2410_GPG2, .code = SW_HEADPHONE_INSERT, .desc = "Headphone", .active_low = 0, @@ -260,7 +259,7 @@ static struct platform_device n35_button_device = { /* This is the bluetooth LED on the device. */ static struct s3c24xx_led_platdata n30_blue_led_pdata = { .name = "blue_led", - .gpio = S3C2410_GPG(6), + .gpio = S3C2410_GPG6, .def_trigger = "", }; @@ -271,7 +270,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = { static struct s3c24xx_led_platdata n30_warning_led_pdata = { .name = "warning_led", .flags = S3C24XX_LEDF_ACTLOW, - .gpio = S3C2410_GPD(9), + .gpio = S3C2410_GPD9, .def_trigger = "", }; diff --git a/trunk/arch/arm/mach-s3c2410/mach-qt2410.c b/trunk/arch/arm/mach-s3c2410/mach-qt2410.c index 2cc9849eb448..9f1ba9b63f70 100644 --- a/trunk/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/trunk/arch/arm/mach-s3c2410/mach-qt2410.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -199,7 +198,7 @@ static struct platform_device qt2410_cs89x0 = { /* LED */ static struct s3c24xx_led_platdata qt2410_pdata_led = { - .gpio = S3C2410_GPB(0), + .gpio = S3C2410_GPB0, .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .name = "led", .def_trigger = "timer", @@ -219,18 +218,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs) { switch (cs) { case BITBANG_CS_ACTIVE: - s3c2410_gpio_setpin(S3C2410_GPB(5), 0); + s3c2410_gpio_setpin(S3C2410_GPB5, 0); break; case BITBANG_CS_INACTIVE: - s3c2410_gpio_setpin(S3C2410_GPB(5), 1); + s3c2410_gpio_setpin(S3C2410_GPB5, 1); break; } } static struct s3c2410_spigpio_info spi_gpio_cfg = { - .pin_clk = S3C2410_GPG(7), - .pin_mosi = S3C2410_GPG(6), - .pin_miso = S3C2410_GPG(5), + .pin_clk = S3C2410_GPG7, + .pin_mosi = S3C2410_GPG6, + .pin_miso = S3C2410_GPG5, .chip_select = &spi_gpio_cs, }; @@ -347,13 +346,13 @@ static void __init qt2410_machine_init(void) } s3c24xx_fb_set_platdata(&qt2410_fb_info); - s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPB(0), 1); + s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPB0, 1); s3c24xx_udc_set_platdata(&qt2410_udc_cfg); s3c_i2c0_set_platdata(NULL); - s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); s3c_pm_init(); diff --git a/trunk/arch/arm/mach-s3c2410/mach-vr1000.c b/trunk/arch/arm/mach-s3c2410/mach-vr1000.c index 1628cc773a2c..61a1ea9c5c5c 100644 --- a/trunk/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/trunk/arch/arm/mach-s3c2410/mach-vr1000.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include @@ -278,19 +277,19 @@ static struct platform_device vr1000_dm9k1 = { static struct s3c24xx_led_platdata vr1000_led1_pdata = { .name = "led1", - .gpio = S3C2410_GPB(0), + .gpio = S3C2410_GPB0, .def_trigger = "", }; static struct s3c24xx_led_platdata vr1000_led2_pdata = { .name = "led2", - .gpio = S3C2410_GPB(1), + .gpio = S3C2410_GPB1, .def_trigger = "", }; static struct s3c24xx_led_platdata vr1000_led3_pdata = { .name = "led3", - .gpio = S3C2410_GPB(2), + .gpio = S3C2410_GPB2, .def_trigger = "", }; @@ -356,8 +355,8 @@ static struct clk *vr1000_clocks[] __initdata = { static void vr1000_power_off(void) { - s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPB(9), 1); + s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP); + s3c2410_gpio_setpin(S3C2410_GPB9, 1); } static void __init vr1000_map_io(void) diff --git a/trunk/arch/arm/mach-s3c2410/pm.c b/trunk/arch/arm/mach-s3c2410/pm.c index 143e08a599d4..87fc481d92d4 100644 --- a/trunk/arch/arm/mach-s3c2410/pm.c +++ b/trunk/arch/arm/mach-s3c2410/pm.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include @@ -77,7 +76,7 @@ static void s3c2410_pm_prepare(void) } if ( machine_is_aml_m5900() ) - s3c2410_gpio_setpin(S3C2410_GPF(2), 1); + s3c2410_gpio_setpin(S3C2410_GPF2, 1); } @@ -92,7 +91,7 @@ static int s3c2410_pm_resume(struct sys_device *dev) __raw_writel(tmp, S3C2410_GSTATUS2); if ( machine_is_aml_m5900() ) - s3c2410_gpio_setpin(S3C2410_GPF(2), 0); + s3c2410_gpio_setpin(S3C2410_GPF2, 0); return 0; } diff --git a/trunk/arch/arm/mach-s3c2410/usb-simtec.c b/trunk/arch/arm/mach-s3c2410/usb-simtec.c index 6cd9377ddb82..8331e8d97e20 100644 --- a/trunk/arch/arm/mach-s3c2410/usb-simtec.c +++ b/trunk/arch/arm/mach-s3c2410/usb-simtec.c @@ -18,11 +18,9 @@ #include #include #include -#include #include #include #include -#include #include #include @@ -31,6 +29,7 @@ #include #include +#include #include #include @@ -54,9 +53,9 @@ usb_simtec_powercontrol(int port, int to) power_state[port] = to; if (power_state[0] && power_state[1]) - gpio_set_value(S3C2410_GPB(4), 0); + s3c2410_gpio_setpin(S3C2410_GPB4, 0); else - gpio_set_value(S3C2410_GPB(4), 1); + s3c2410_gpio_setpin(S3C2410_GPB4, 1); } static irqreturn_t @@ -64,7 +63,7 @@ usb_simtec_ocirq(int irq, void *pw) { struct s3c2410_hcd_info *info = pw; - if (gpio_get_value(S3C2410_GPG(10)) == 0) { + if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) { pr_debug("usb_simtec: over-current irq (oc detected)\n"); s3c2410_usb_report_oc(info, 3); } else { @@ -107,27 +106,10 @@ static struct s3c2410_hcd_info usb_simtec_info = { int usb_simtec_init(void) { - int ret; - printk("USB Power Control, (c) 2004 Simtec Electronics\n"); - - ret = gpio_request(S3C2410_GPB(4), "USB power control"); - if (ret < 0) { - pr_err("%s: failed to get GPB4\n", __func__); - return ret; - } - - ret = gpio_request(S3C2410_GPG(10), "USB overcurrent"); - if (ret < 0) { - pr_err("%s: failed to get GPG10\n", __func__); - gpio_free(S3C2410_GPB(4)); - return ret; - } - - /* turn power on */ - gpio_direction_output(S3C2410_GPB(4), 1); - gpio_direction_input(S3C2410_GPG(10)); - s3c_device_usb.dev.platform_data = &usb_simtec_info; + + s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP); + s3c2410_gpio_setpin(S3C2410_GPB4, 1); return 0; } diff --git a/trunk/arch/arm/mach-s3c2412/Kconfig b/trunk/arch/arm/mach-s3c2412/Kconfig index 63586ffd0ae7..ca99564ae4b5 100644 --- a/trunk/arch/arm/mach-s3c2412/Kconfig +++ b/trunk/arch/arm/mach-s3c2412/Kconfig @@ -38,7 +38,6 @@ menu "S3C2412 Machines" config MACH_JIVE bool "Logitech Jive" select CPU_S3C2412 - select S3C_DEV_USB_HOST help Say Y here if you are using the Logitech Jive. @@ -51,7 +50,6 @@ config MACH_SMDK2413 select CPU_S3C2412 select MACH_S3C2413 select MACH_SMDK - select S3C_DEV_USB_HOST help Say Y here if you are using an SMDK2413 @@ -74,7 +72,6 @@ config MACH_SMDK2412 config MACH_VSTMS bool "VMSTMS" select CPU_S3C2412 - select S3C_DEV_USB_HOST help Say Y here if you are using an VSTMS board diff --git a/trunk/arch/arm/mach-s3c2412/dma.c b/trunk/arch/arm/mach-s3c2412/dma.c index f8d16fc10bc6..9e3478506c6f 100644 --- a/trunk/arch/arm/mach-s3c2412/dma.c +++ b/trunk/arch/arm/mach-s3c2412/dma.c @@ -20,13 +20,12 @@ #include -#include +#include #include #include #include #include -#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c2412/mach-jive.c b/trunk/arch/arm/mach-s3c2412/mach-jive.c index 8df506eac903..8f0d37d43b43 100644 --- a/trunk/arch/arm/mach-s3c2412/mach-jive.c +++ b/trunk/arch/arm/mach-s3c2412/mach-jive.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -357,8 +356,8 @@ static void jive_lcm_reset(unsigned int set) { printk(KERN_DEBUG "%s(%d)\n", __func__, set); - s3c2410_gpio_setpin(S3C2410_GPG(13), set); - s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPG13, set); + s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); } #undef LCD_UPPER_MARGIN @@ -391,13 +390,13 @@ static struct ili9320_platdata jive_lcm_config = { static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs) { - s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1); + s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1); } static struct s3c2410_spigpio_info jive_lcd_spi = { .bus_num = 1, - .pin_clk = S3C2410_GPG(8), - .pin_mosi = S3C2410_GPB(8), + .pin_clk = S3C2410_GPG8, + .pin_mosi = S3C2410_GPB8, .num_chipselect = 1, .chip_select = jive_lcd_spi_chipselect, }; @@ -413,13 +412,13 @@ static struct platform_device jive_device_lcdspi = { static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs) { - s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1); + s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1); } static struct s3c2410_spigpio_info jive_wm8750_spi = { .bus_num = 2, - .pin_clk = S3C2410_GPB(4), - .pin_mosi = S3C2410_GPB(9), + .pin_clk = S3C2410_GPB4, + .pin_mosi = S3C2410_GPB9, .num_chipselect = 1, .chip_select = jive_wm8750_chipselect, }; @@ -480,7 +479,7 @@ static struct platform_device *jive_devices[] __initdata = { }; static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = { - .vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */ + .vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */ }; /* Jive power management device */ @@ -530,8 +529,8 @@ static void jive_power_off(void) { printk(KERN_INFO "powering system down...\n"); - s3c2410_gpio_setpin(S3C2410_GPC(5), 1); - s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPC5, 1); + s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT); } static void __init jive_machine_init(void) @@ -635,22 +634,22 @@ static void __init jive_machine_init(void) /* initialise the spi */ - s3c2410_gpio_setpin(S3C2410_GPG(13), 0); - s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPG13, 0); + s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPB(7), 1); - s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPB7, 1); + s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPB(6), 0); - s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPB6, 0); + s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPG(8), 1); - s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPG8, 1); + s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT); /* initialise the WM8750 spi */ - s3c2410_gpio_setpin(S3C2410_GPH(10), 1); - s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPH10, 1); + s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT); /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ diff --git a/trunk/arch/arm/mach-s3c2412/mach-smdk2413.c b/trunk/arch/arm/mach-s3c2412/mach-smdk2413.c index 9a5e43419722..eba66aa6bd20 100644 --- a/trunk/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/trunk/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -85,10 +84,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd) switch (cmd) { case S3C2410_UDC_P_ENABLE : - s3c2410_gpio_setpin(S3C2410_GPF(2), 1); + s3c2410_gpio_setpin(S3C2410_GPF2, 1); break; case S3C2410_UDC_P_DISABLE : - s3c2410_gpio_setpin(S3C2410_GPF(2), 0); + s3c2410_gpio_setpin(S3C2410_GPF2, 0); break; case S3C2410_UDC_P_RESET : break; @@ -135,8 +134,8 @@ static void __init smdk2413_machine_init(void) { /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ - s3c2410_gpio_setpin(S3C2410_GPF(2), 0); - s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPF2, 0); + s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT); s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | S3C2410_MISCCR_USBSUSPND0 | diff --git a/trunk/arch/arm/mach-s3c2440/Kconfig b/trunk/arch/arm/mach-s3c2440/Kconfig index 5df73cbf2b40..cde5ae9a4340 100644 --- a/trunk/arch/arm/mach-s3c2440/Kconfig +++ b/trunk/arch/arm/mach-s3c2440/Kconfig @@ -33,7 +33,6 @@ config MACH_ANUBIS select PM_SIMTEC if PM select HAVE_PATA_PLATFORM select S3C24XX_GPIO_EXTRA64 - select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec Electronics ANUBIS development system @@ -44,7 +43,6 @@ config MACH_OSIRIS select S3C24XX_DCLK select PM_SIMTEC if PM select S3C24XX_GPIO_EXTRA128 - select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec IM2440D20 module, also known as the Osiris. @@ -60,14 +58,12 @@ config ARCH_S3C2440 bool "SMDK2440" select CPU_S3C2440 select MACH_SMDK - select S3C_DEV_USB_HOST help Say Y here if you are using the SMDK2440. config MACH_NEXCODER_2440 bool "NexVision NEXCODER 2440 Light Board" select CPU_S3C2440 - select S3C_DEV_USB_HOST help Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board @@ -80,7 +76,6 @@ config SMDK2440_CPU2440 config MACH_AT2440EVB bool "Avantech AT2440EVB development board" select CPU_S3C2440 - select S3C_DEV_USB_HOST help Say Y here if you are using the AT2440EVB development board diff --git a/trunk/arch/arm/mach-s3c2440/dma.c b/trunk/arch/arm/mach-s3c2440/dma.c index e08e081430f0..69b6cf34df47 100644 --- a/trunk/arch/arm/mach-s3c2440/dma.c +++ b/trunk/arch/arm/mach-s3c2440/dma.c @@ -17,16 +17,14 @@ #include #include -#include #include -#include +#include #include #include #include #include -#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c2440/mach-anubis.c b/trunk/arch/arm/mach-s3c2440/mach-anubis.c index 68f3870991bf..9c6abf9fb540 100644 --- a/trunk/arch/arm/mach-s3c2440/mach-anubis.c +++ b/trunk/arch/arm/mach-s3c2440/mach-anubis.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -469,7 +468,7 @@ static void __init anubis_map_io(void) anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large); } else { /* ensure that the GPIO is setup */ - s3c2410_gpio_setpin(S3C2410_GPA(0), 1); + s3c2410_gpio_setpin(S3C2410_GPA0, 1); } } diff --git a/trunk/arch/arm/mach-s3c2440/mach-at2440evb.c b/trunk/arch/arm/mach-s3c2440/mach-at2440evb.c index dfc7010935da..315c42e31278 100644 --- a/trunk/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/trunk/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -166,7 +166,7 @@ static struct platform_device at2440evb_device_eth = { }; static struct s3c24xx_mci_pdata at2440evb_mci_pdata = { - .gpio_detect = S3C2410_GPG(10), + .gpio_detect = S3C2410_GPG10, }; /* 7" LCD panel */ diff --git a/trunk/arch/arm/mach-s3c2440/mach-nexcoder.c b/trunk/arch/arm/mach-s3c2440/mach-nexcoder.c index d43edede590e..7aeaa972d7f5 100644 --- a/trunk/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/trunk/arch/arm/mach-s3c2440/mach-nexcoder.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -121,16 +120,16 @@ static struct platform_device *nexcoder_devices[] __initdata = { static void __init nexcoder_sensorboard_init(void) { // Initialize SCCB bus - s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL - s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA - s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL + s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP); + s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA + s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP); // Power up the sensor board - s3c2410_gpio_setpin(S3C2410_GPF(1), 1); - s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN - s3c2410_gpio_setpin(S3C2410_GPF(2), 0); - s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN + s3c2410_gpio_setpin(S3C2410_GPF1, 1); + s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN + s3c2410_gpio_setpin(S3C2410_GPF2, 0); + s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN } static void __init nexcoder_map_io(void) diff --git a/trunk/arch/arm/mach-s3c2440/mach-osiris.c b/trunk/arch/arm/mach-s3c2440/mach-osiris.c index cba064b49a64..c8a46685ce38 100644 --- a/trunk/arch/arm/mach-s3c2440/mach-osiris.c +++ b/trunk/arch/arm/mach-s3c2440/mach-osiris.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -292,8 +291,8 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state) __raw_writeb(tmp, OSIRIS_VA_CTRL0); /* ensure that an nRESET is not generated on resume. */ - s3c2410_gpio_setpin(S3C2410_GPA(21), 1); - s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPA21, 1); + s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); return 0; } @@ -305,7 +304,7 @@ static int osiris_pm_resume(struct sys_device *sd) __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0); - s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); + s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); return 0; } @@ -385,7 +384,7 @@ static void __init osiris_map_io(void) osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large); } else { /* write-protect line to the NAND */ - s3c2410_gpio_setpin(S3C2410_GPA(0), 1); + s3c2410_gpio_setpin(S3C2410_GPA0, 1); } /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ diff --git a/trunk/arch/arm/mach-s3c2443/dma.c b/trunk/arch/arm/mach-s3c2443/dma.c index 397f3b5c0b47..8430e5829186 100644 --- a/trunk/arch/arm/mach-s3c2443/dma.c +++ b/trunk/arch/arm/mach-s3c2443/dma.c @@ -20,13 +20,12 @@ #include -#include +#include #include #include #include #include -#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c6400/Kconfig b/trunk/arch/arm/mach-s3c6400/Kconfig index f5af212066c3..6da82b5c09ba 100644 --- a/trunk/arch/arm/mach-s3c6400/Kconfig +++ b/trunk/arch/arm/mach-s3c6400/Kconfig @@ -5,27 +5,4 @@ # # Licensed under GPLv2 -# Configuration options for the S3C6410 CPU - -config CPU_S3C6400 - bool - select CPU_S3C6400_INIT - select CPU_S3C6400_CLOCK - help - Enable S3C6400 CPU support - -config S3C6400_SETUP_SDHCI - bool - help - Internal configuration for default SDHCI - setup for S3C6400. - -# S36400 Macchine support - -config MACH_SMDK6400 - bool "SMDK6400" - select CPU_S3C6400 - select S3C_DEV_HSMMC - select S3C6400_SETUP_SDHCI - help - Machine support for the Samsung SMDK6400 +# Currently nothing here, this will be added later diff --git a/trunk/arch/arm/mach-s3c6400/Makefile b/trunk/arch/arm/mach-s3c6400/Makefile index df1ce4aa03e5..8f397db25b87 100644 --- a/trunk/arch/arm/mach-s3c6400/Makefile +++ b/trunk/arch/arm/mach-s3c6400/Makefile @@ -12,12 +12,4 @@ obj- := # Core support for S3C6400 system -obj-$(CONFIG_CPU_S3C6400) += s3c6400.o - -# setup support - -obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o - -# Machine support - -obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o +obj-n += blank.o diff --git a/trunk/arch/arm/mach-s3c6400/include/mach/dma.h b/trunk/arch/arm/mach-s3c6400/include/mach/dma.h index 1067619f0ba0..9771ac2cb07e 100644 --- a/trunk/arch/arm/mach-s3c6400/include/mach/dma.h +++ b/trunk/arch/arm/mach-s3c6400/include/mach/dma.h @@ -11,63 +11,6 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H __FILE__ -#define S3C_DMA_CHANNELS (16) - -/* see mach-s3c2410/dma.h for notes on dma channel numbers */ - -/* Note, for the S3C64XX architecture we keep the DMACH_ - * defines in the order they are allocated to [S]DMA0/[S]DMA1 - * so that is easy to do DHACH_ -> DMA controller conversion - */ -enum dma_ch { - /* DMA0/SDMA0 */ - DMACH_UART0 = 0, - DMACH_UART0_SRC2, - DMACH_UART1, - DMACH_UART1_SRC2, - DMACH_UART2, - DMACH_UART2_SRC2, - DMACH_UART3, - DMACH_UART3_SRC2, - DMACH_PCM0_TX, - DMACH_PCM0_RX, - DMACH_I2S0_OUT, - DMACH_I2S0_IN, - DMACH_SPI0_TX, - DMACH_SPI0_RX, - DMACH_HSI_I2SV40_TX, - DMACH_HSI_I2SV40_RX, - - /* DMA1/SDMA1 */ - DMACH_PCM1_TX = 16, - DMACH_PCM1_RX, - DMACH_I2S1_OUT, - DMACH_I2S1_IN, - DMACH_SPI1_TX, - DMACH_SPI1_RX, - DMACH_AC97_PCMOUT, - DMACH_AC97_PCMIN, - DMACH_AC97_MICIN, - DMACH_PWM, - DMACH_IRDA, - DMACH_EXTERNAL, - DMACH_RES1, - DMACH_RES2, - DMACH_SECURITY_RX, /* SDMA1 only */ - DMACH_SECURITY_TX, /* SDMA1 only */ - DMACH_MAX /* the end */ -}; - -static __inline__ int s3c_dma_has_circular(void) -{ - /* we will be supporting ciruclar buffers as soon as we have DMA - * engine support. - */ - return 1; -} - -#define S3C2410_DMAF_CIRCULAR (1 << 0) - -#include +/* currently nothing here, placeholder */ #endif /* __ASM_ARCH_IRQ_H */ diff --git a/trunk/arch/arm/mach-s3c6400/include/mach/map.h b/trunk/arch/arm/mach-s3c6400/include/mach/map.h index 5057d9948d35..8199972ed5bd 100644 --- a/trunk/arch/arm/mach-s3c6400/include/mach/map.h +++ b/trunk/arch/arm/mach-s3c6400/include/mach/map.h @@ -39,8 +39,6 @@ #define S3C_VA_UART3 S3C_VA_UARTx(3) #define S3C64XX_PA_FB (0x77100000) -#define S3C64XX_PA_USB_HSOTG (0x7C000000) -#define S3C64XX_PA_WATCHDOG (0x7E004000) #define S3C64XX_PA_SYSCON (0x7E00F000) #define S3C64XX_PA_IIS0 (0x7F002000) #define S3C64XX_PA_IIS1 (0x7F003000) @@ -59,8 +57,6 @@ #define S3C64XX_PA_MODEM (0x74108000) #define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) -#define S3C64XX_PA_USBHOST (0x74300000) - /* place VICs close together */ #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) @@ -73,7 +69,5 @@ #define S3C_PA_IIC S3C64XX_PA_IIC0 #define S3C_PA_IIC1 S3C64XX_PA_IIC1 #define S3C_PA_FB S3C64XX_PA_FB -#define S3C_PA_USBHOST S3C64XX_PA_USBHOST -#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG #endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/trunk/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/trunk/arch/arm/mach-s3c6400/include/mach/regs-clock.h deleted file mode 100644 index a6c7f4eb3a1b..000000000000 --- a/trunk/arch/arm/mach-s3c6400/include/mach/regs-clock.h +++ /dev/null @@ -1,16 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C64XX - clock register compatibility with s3c24xx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - diff --git a/trunk/arch/arm/mach-s3c6400/include/mach/system.h b/trunk/arch/arm/mach-s3c6400/include/mach/system.h index 2e58cb7a7147..090cfd969bc7 100644 --- a/trunk/arch/arm/mach-s3c6400/include/mach/system.h +++ b/trunk/arch/arm/mach-s3c6400/include/mach/system.h @@ -11,8 +11,6 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ -#include - static void arch_idle(void) { /* nothing here yet */ @@ -20,11 +18,7 @@ static void arch_idle(void) static void arch_reset(char mode, const char *cmd) { - if (mode != 's') - arch_wdt_reset(); - - /* if all else fails, or mode was for soft, jump to 0 */ - cpu_reset(0); + /* nothing here yet */ } #endif /* __ASM_ARCH_IRQ_H */ diff --git a/trunk/arch/arm/mach-s3c6400/mach-smdk6400.c b/trunk/arch/arm/mach-s3c6400/mach-smdk6400.c deleted file mode 100644 index ab19285389a7..000000000000 --- a/trunk/arch/arm/mach-s3c6400/mach-smdk6400.c +++ /dev/null @@ -1,96 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include -#include -#include - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, -}; - -static struct map_desc smdk6400_iodesc[] = {}; - -static void __init smdk6400_map_io(void) -{ - s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); -} - -static struct platform_device *smdk6400_devices[] __initdata = { - &s3c_device_hsmmc1, - &s3c_device_i2c0, -}; - -static struct i2c_board_info i2c_devs[] __initdata = { - { I2C_BOARD_INFO("wm8753", 0x1A), }, - { I2C_BOARD_INFO("24c08", 0x50), }, -}; - -static void __init smdk6400_machine_init(void) -{ - i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs)); - platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices)); -} - -MACHINE_START(SMDK6400, "SMDK6400") - /* Maintainer: Ben Dooks */ - .phys_io = S3C_PA_UART & 0xfff00000, - .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C64XX_PA_SDRAM + 0x100, - - .init_irq = s3c6400_init_irq, - .map_io = smdk6400_map_io, - .init_machine = smdk6400_machine_init, - .timer = &s3c24xx_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-s3c6400/s3c6400.c b/trunk/arch/arm/mach-s3c6400/s3c6400.c deleted file mode 100644 index 1ece887d90bb..000000000000 --- a/trunk/arch/arm/mach-s3c6400/s3c6400.c +++ /dev/null @@ -1,89 +0,0 @@ -/* linux/arch/arm/mach-s3c6410/cpu.c - * - * Copyright 2009 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -void __init s3c6400_map_io(void) -{ - /* setup SDHCI */ - - s3c6400_default_sdhci0(); - s3c6400_default_sdhci1(); - - /* the i2c devices are directly compatible with s3c2440 */ - s3c_i2c0_setname("s3c2440-i2c"); -} - -void __init s3c6400_init_clocks(int xtal) -{ - printk(KERN_DEBUG "%s: initialising clocks\n", __func__); - s3c24xx_register_baseclocks(xtal); - s3c64xx_register_clocks(); - s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK); - s3c6400_setup_clocks(); -} - -void __init s3c6400_init_irq(void) -{ - /* VIC0 does not have IRQS 5..7, - * VIC1 is fully populated. */ - s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); -} - -struct sysdev_class s3c6400_sysclass = { - .name = "s3c6400-core", -}; - -static struct sys_device s3c6400_sysdev = { - .cls = &s3c6400_sysclass, -}; - -static int __init s3c6400_core_init(void) -{ - return sysdev_class_register(&s3c6400_sysclass); -} - -core_initcall(s3c6400_core_init); - -int __init s3c6400_init(void) -{ - printk("S3C6400: Initialising architecture\n"); - - return sysdev_register(&s3c6400_sysdev); -} diff --git a/trunk/arch/arm/mach-s3c6400/setup-sdhci.c b/trunk/arch/arm/mach-s3c6400/setup-sdhci.c deleted file mode 100644 index b93dafbee1f4..000000000000 --- a/trunk/arch/arm/mach-s3c6400/setup-sdhci.c +++ /dev/null @@ -1,63 +0,0 @@ -/* linux/arch/arm/mach-s3c6410/setup-sdhci.c - * - * Copyright 2008 Simtec Electronics - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s3c6400_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - [2] = "mmc_bus", - /* [3] = "48m", - note not succesfully used yet */ -}; - -void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - ctrl2 = readl(r + S3C_SDHCI_CONTROL2); - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); - writel(ctrl2, r + S3C_SDHCI_CONTROL2); - writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} - diff --git a/trunk/arch/arm/mach-s3c6410/Kconfig b/trunk/arch/arm/mach-s3c6410/Kconfig index e63aac7f4e5a..1d5010070027 100644 --- a/trunk/arch/arm/mach-s3c6410/Kconfig +++ b/trunk/arch/arm/mach-s3c6410/Kconfig @@ -16,18 +16,9 @@ config CPU_S3C6410 config S3C6410_SETUP_SDHCI bool - select S3C64XX_SETUP_SDHCI_GPIO help Internal helper functions for S3C6410 based SDHCI systems -config MACH_ANW6410 - bool "A&W6410" - select CPU_S3C6410 - select S3C_DEV_FB - select S3C64XX_SETUP_FB_24BPP - help - Machine support for the A&W6410 - config MACH_SMDK6410 bool "SMDK6410" select CPU_S3C6410 @@ -35,8 +26,6 @@ config MACH_SMDK6410 select S3C_DEV_HSMMC1 select S3C_DEV_I2C1 select S3C_DEV_FB - select S3C_DEV_USB_HOST - select S3C_DEV_USB_HSOTG select S3C6410_SETUP_SDHCI select S3C64XX_SETUP_I2C1 select S3C64XX_SETUP_FB_24BPP @@ -71,29 +60,3 @@ config SMDK6410_SD_CH1 channels 0 and 1 are the same. endchoice - -config SMDK6410_WM1190_EV1 - bool "Support Wolfson Microelectronics 1190-EV1 PMIC card" - depends on MACH_SMDK6410 - select REGULATOR - select REGULATOR_WM8350 - select MFD_WM8350_I2C - select MFD_WM8350_CONFIG_MODE_0 - select MFD_WM8350_CONFIG_MODE_3 - select MFD_WM8352_CONFIG_MODE_0 - help - The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC - and audio daughtercard for the Samsung SMDK6410 reference - platform. Enabling this option will build support for this - module into the kernel. The presence of the module will be - detected at runtime so the the resulting kernel can be used - with or without the 1190-EV1 fitted. - -config MACH_NCP - bool "NCP" - select CPU_S3C6410 - select S3C_DEV_I2C1 - select S3C_DEV_HSMMC1 - select S3C64XX_SETUP_I2C1 - help - Machine support for the Samsung NCP diff --git a/trunk/arch/arm/mach-s3c6410/Makefile b/trunk/arch/arm/mach-s3c6410/Makefile index 6f9deac88612..2cd4f189036b 100644 --- a/trunk/arch/arm/mach-s3c6410/Makefile +++ b/trunk/arch/arm/mach-s3c6410/Makefile @@ -20,8 +20,4 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o # machine support -obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o -obj-$(CONFIG_MACH_NCP) += mach-ncp.o - - diff --git a/trunk/arch/arm/mach-s3c6410/cpu.c b/trunk/arch/arm/mach-s3c6410/cpu.c index ade904de8895..6a73ca6b7a3a 100644 --- a/trunk/arch/arm/mach-s3c6410/cpu.c +++ b/trunk/arch/arm/mach-s3c6410/cpu.c @@ -31,7 +31,6 @@ #include #include -#include #include #include @@ -69,7 +68,7 @@ void __init s3c6410_init_clocks(int xtal) printk(KERN_DEBUG "%s: initialising clocks\n", __func__); s3c24xx_register_baseclocks(xtal); s3c64xx_register_clocks(); - s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK); + s3c6400_register_clocks(); s3c6400_setup_clocks(); } diff --git a/trunk/arch/arm/mach-s3c6410/mach-anw6410.c b/trunk/arch/arm/mach-s3c6410/mach-anw6410.c deleted file mode 100644 index 661cca63de25..000000000000 --- a/trunk/arch/arm/mach-s3c6410/mach-anw6410.c +++ /dev/null @@ -1,245 +0,0 @@ -/* linux/arch/arm/mach-s3c6410/mach-anw6410.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * Copyright 2009 Kwangwoo Lee - * Kwangwoo Lee - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include