From 17463911bb71e1365a5e9421c906eb5015022fd0 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 17 Oct 2011 14:38:09 +1000 Subject: [PATCH] --- yaml --- r: 279729 b: refs/heads/master c: ae2eca724af2802739efe02b3fc56daa8b674eb9 h: refs/heads/master i: 279727: be5e7f757420e340316f0a882bc029ee696d0baa v: v3 --- [refs] | 2 +- trunk/arch/m68k/include/asm/cacheflush_mm.h | 88 +++++++++++++++++++-- trunk/arch/m68k/mm/cache.c | 24 +++++- 3 files changed, 105 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 147e51dff446..4a0e4a2c1434 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 78d705e3be4bfbd2e75157d284096d600ea6eda5 +refs/heads/master: ae2eca724af2802739efe02b3fc56daa8b674eb9 diff --git a/trunk/arch/m68k/include/asm/cacheflush_mm.h b/trunk/arch/m68k/include/asm/cacheflush_mm.h index 73de7c89d8e0..8104bd874649 100644 --- a/trunk/arch/m68k/include/asm/cacheflush_mm.h +++ b/trunk/arch/m68k/include/asm/cacheflush_mm.h @@ -2,23 +2,89 @@ #define _M68K_CACHEFLUSH_H #include +#ifdef CONFIG_COLDFIRE +#include +#endif /* cache code */ #define FLUSH_I_AND_D (0x00000808) #define FLUSH_I (0x00000008) +#ifndef ICACHE_MAX_ADDR +#define ICACHE_MAX_ADDR 0 +#define ICACHE_SET_MASK 0 +#define DCACHE_MAX_ADDR 0 +#define DCACHE_SETMASK 0 +#endif + +static inline void flush_cf_icache(unsigned long start, unsigned long end) +{ + unsigned long set; + + for (set = start; set <= end; set += (0x10 - 3)) { + __asm__ __volatile__ ( + "cpushl %%ic,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%ic,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%ic,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%ic,(%0)" + : "=a" (set) + : "a" (set)); + } +} + +static inline void flush_cf_dcache(unsigned long start, unsigned long end) +{ + unsigned long set; + + for (set = start; set <= end; set += (0x10 - 3)) { + __asm__ __volatile__ ( + "cpushl %%dc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%dc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%dc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%dc,(%0)" + : "=a" (set) + : "a" (set)); + } +} + +static inline void flush_cf_bcache(unsigned long start, unsigned long end) +{ + unsigned long set; + + for (set = start; set <= end; set += (0x10 - 3)) { + __asm__ __volatile__ ( + "cpushl %%bc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%bc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%bc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%bc,(%0)" + : "=a" (set) + : "a" (set)); + } +} + /* * Cache handling functions */ static inline void flush_icache(void) { - if (CPU_IS_040_OR_060) + if (CPU_IS_COLDFIRE) { + flush_cf_icache(0, ICACHE_MAX_ADDR); + } else if (CPU_IS_040_OR_060) { asm volatile ( "nop\n" " .chip 68040\n" " cpusha %bc\n" " .chip 68k"); - else { + } else { unsigned long tmp; asm volatile ( "movec %%cacr,%0\n" " or.w %1,%0\n" @@ -51,12 +117,14 @@ extern void cache_push_v(unsigned long vaddr, int len); process changes. */ #define __flush_cache_all() \ ({ \ - if (CPU_IS_040_OR_060) \ + if (CPU_IS_COLDFIRE) { \ + flush_cf_dcache(0, DCACHE_MAX_ADDR); \ + } else if (CPU_IS_040_OR_060) { \ __asm__ __volatile__("nop\n\t" \ ".chip 68040\n\t" \ "cpusha %dc\n\t" \ ".chip 68k"); \ - else { \ + } else { \ unsigned long _tmp; \ __asm__ __volatile__("movec %%cacr,%0\n\t" \ "orw %1,%0\n\t" \ @@ -112,7 +180,17 @@ static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vm /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ static inline void __flush_page_to_ram(void *vaddr) { - if (CPU_IS_040_OR_060) { + if (CPU_IS_COLDFIRE) { + unsigned long addr, start, end; + addr = ((unsigned long) vaddr) & ~(PAGE_SIZE - 1); + start = addr & ICACHE_SET_MASK; + end = (addr + PAGE_SIZE - 1) & ICACHE_SET_MASK; + if (start > end) { + flush_cf_bcache(0, end); + end = ICACHE_MAX_ADDR; + } + flush_cf_bcache(start, end); + } else if (CPU_IS_040_OR_060) { __asm__ __volatile__("nop\n\t" ".chip 68040\n\t" "cpushp %%bc,(%0)\n\t" diff --git a/trunk/arch/m68k/mm/cache.c b/trunk/arch/m68k/mm/cache.c index 5437fff5fe07..95d0bf66e2e2 100644 --- a/trunk/arch/m68k/mm/cache.c +++ b/trunk/arch/m68k/mm/cache.c @@ -74,8 +74,16 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr) /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ void flush_icache_range(unsigned long address, unsigned long endaddr) { - - if (CPU_IS_040_OR_060) { + if (CPU_IS_COLDFIRE) { + unsigned long start, end; + start = address & ICACHE_SET_MASK; + end = endaddr & ICACHE_SET_MASK; + if (start > end) { + flush_cf_icache(0, end); + end = ICACHE_MAX_ADDR; + } + flush_cf_icache(start, end); + } else if (CPU_IS_040_OR_060) { address &= PAGE_MASK; do { @@ -100,7 +108,17 @@ EXPORT_SYMBOL(flush_icache_range); void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, unsigned long addr, int len) { - if (CPU_IS_040_OR_060) { + if (CPU_IS_COLDFIRE) { + unsigned long start, end; + start = addr & ICACHE_SET_MASK; + end = (addr + len) & ICACHE_SET_MASK; + if (start > end) { + flush_cf_icache(0, end); + end = ICACHE_MAX_ADDR; + } + flush_cf_icache(start, end); + + } else if (CPU_IS_040_OR_060) { asm volatile ("nop\n\t" ".chip 68040\n\t" "cpushp %%bc,(%0)\n\t"