From 175bc42d6351e73fd2bd98b4b0adc24815f2876b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 16 Nov 2012 16:56:50 +0100 Subject: [PATCH] --- yaml --- r: 342269 b: refs/heads/master c: e6f097960621828bdce238aef7a7fc5404bfca71 h: refs/heads/master i: 342267: e21af9639ae7e8c49b2f75a4ba74df8f4d2a3c56 v: v3 --- [refs] | 2 +- trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi | 16 +++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 1524555e605f..f055be681e85 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: dced3e3ee5833109c04ecf8687ae44960c65ca73 +refs/heads/master: e6f097960621828bdce238aef7a7fc5404bfca71 diff --git a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi index 95df80e7cda7..a239ccdfaa52 100644 --- a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -8,6 +8,16 @@ reg = <0x00000000 0x20000000>; }; + host1x { + hdmi { + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -292,7 +302,7 @@ pinctrl-1 = <&state_i2cmux_pta>; pinctrl-2 = <&state_i2cmux_idle>; - i2c@0 { + hdmi_ddc: i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -407,13 +417,13 @@ regulator-max-microvolt = <2850000>; }; - ldo7 { + hdmi_vdd_reg: ldo7 { regulator-name = "vdd_ldo7,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo8 { + hdmi_pll_reg: ldo8 { regulator-name = "vdd_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>;