From 178b47fddedee672eac41e011d398632df97ae36 Mon Sep 17 00:00:00 2001
From: Will Deacon <will.deacon@arm.com>
Date: Tue, 9 Aug 2011 12:13:53 +0100
Subject: [PATCH] --- yaml --- r: 272884 b: refs/heads/master c:
 f80ca52cab8f999246ed2e4daa90eb40cb810822 h: refs/heads/master v: v3

---
 [refs]                                    | 2 +-
 trunk/arch/arm/mach-shmobile/smp-sh73a0.c | 6 +++++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 8d94fabb09e2..7676e766ec96 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1d3cfb34f9605578b4f733acba4affa751b2e4a2
+refs/heads/master: f80ca52cab8f999246ed2e4daa90eb40cb810822
diff --git a/trunk/arch/arm/mach-shmobile/smp-sh73a0.c b/trunk/arch/arm/mach-shmobile/smp-sh73a0.c
index 3ffdbc92ba82..be1ade76ccc8 100644
--- a/trunk/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/trunk/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -74,6 +74,8 @@ void __cpuinit sh73a0_secondary_init(unsigned int cpu)
 
 int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
 {
+	cpu = cpu_logical_map(cpu);
+
 	/* enable cache coherency */
 	modify_scu_cpu_psr(0, 3 << (cpu * 8));
 
@@ -87,6 +89,8 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
 
 void __init sh73a0_smp_prepare_cpus(void)
 {
+	int cpu = cpu_logical_map(0);
+
 	scu_enable(scu_base_addr());
 
 	/* Map the reset vector (in headsmp.S) */
@@ -94,5 +98,5 @@ void __init sh73a0_smp_prepare_cpus(void)
 	__raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
 
 	/* enable cache coherency on CPU0 */
-	modify_scu_cpu_psr(0, 3 << (0 * 8));
+	modify_scu_cpu_psr(0, 3 << (cpu * 8));
 }