From 1861c350e83d0fbb51c16468aec94b17946269ad Mon Sep 17 00:00:00 2001 From: Grant Grundler Date: Fri, 21 Oct 2005 22:55:51 -0400 Subject: [PATCH] --- yaml --- r: 10509 b: refs/heads/master c: 9b3b331d0322b60de1bde20528bf974f62804ffa h: refs/heads/master i: 10507: 61e6e69afc267cc301f491bb1830a7dbe5cbd4e1 v: v3 --- [refs] | 2 +- trunk/arch/parisc/kernel/pacache.S | 4 ++-- trunk/arch/parisc/kernel/signal.c | 11 +++++++---- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/[refs] b/[refs] index b679f4ec8800..8e7c4ee41ea5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 37318a3cb1028933417533084ddbf9d84be06878 +refs/heads/master: 9b3b331d0322b60de1bde20528bf974f62804ffa diff --git a/trunk/arch/parisc/kernel/pacache.S b/trunk/arch/parisc/kernel/pacache.S index e217ae369fbb..08cde5addfca 100644 --- a/trunk/arch/parisc/kernel/pacache.S +++ b/trunk/arch/parisc/kernel/pacache.S @@ -227,7 +227,7 @@ flush_instruction_cache_local: fimanyloop: /* Loop if LOOP >= 2 */ ADDIB> -1, %r31, fimanyloop /* Adjusted inner loop decr */ - fice 0(%sr1, %arg0) + fice %r0(%sr1, %arg0) fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */ movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */ ADDIB<=,n -1, %arg2, fisync /* Outer loop decr */ @@ -269,7 +269,7 @@ flush_data_cache_local: fdmanyloop: /* Loop if LOOP >= 2 */ ADDIB> -1, %r31, fdmanyloop /* Adjusted inner loop decr */ - fdce 0(%sr1, %arg0) + fdce %r0(%sr1, %arg0) fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */ movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */ ADDIB<=,n -1, %arg2, fdsync /* Outer loop decr */ diff --git a/trunk/arch/parisc/kernel/signal.c b/trunk/arch/parisc/kernel/signal.c index befdfe700616..82c24e62ab63 100644 --- a/trunk/arch/parisc/kernel/signal.c +++ b/trunk/arch/parisc/kernel/signal.c @@ -625,11 +625,14 @@ do_signal(sigset_t *oldset, struct pt_regs *regs, int in_syscall) put_user(0xe0008200, &usp[3]); put_user(0x34140000, &usp[4]); - /* Stack is 64-byte aligned, and we only - * need to flush 1 cache line */ - asm("fdc 0(%%sr3, %0)\n" + /* Stack is 64-byte aligned, and we only need + * to flush 1 cache line. + * Flushing one cacheline is cheap. + * "sync" on bigger (> 4 way) boxes is not. + */ + asm("fdc %%r0(%%sr3, %0)\n" "sync\n" - "fic 0(%%sr3, %0)\n" + "fic %%r0(%%sr3, %0)\n" "sync\n" : : "r"(regs->gr[30]));