From 18990ae7120758bbf4fa3ec2482340ea651ae46f Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 28 Feb 2012 19:24:44 -0500 Subject: [PATCH] --- yaml --- r: 309026 b: refs/heads/master c: cc06748cf00e6a4accb18c1b70079dccffc69c37 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mips/cavium-octeon/smp.c | 6 ++++++ trunk/arch/mips/include/asm/setup.h | 3 +-- trunk/arch/mips/include/asm/traps.h | 1 - trunk/arch/mips/kernel/setup.c | 2 -- trunk/arch/mips/kernel/smp.c | 2 +- trunk/arch/mips/kernel/traps.c | 16 ++++++---------- trunk/arch/mips/mm/c-octeon.c | 14 ++++++-------- trunk/arch/mips/mm/c-r4k.c | 14 ++++---------- trunk/drivers/tty/serial/zs.c | 1 + 10 files changed, 26 insertions(+), 35 deletions(-) diff --git a/[refs] b/[refs] index 754b1992bcc1..b31dc5cd5904 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a3c8b4faeeccb33dbad6969bc9e50bf409f167e7 +refs/heads/master: cc06748cf00e6a4accb18c1b70079dccffc69c37 diff --git a/trunk/arch/mips/cavium-octeon/smp.c b/trunk/arch/mips/cavium-octeon/smp.c index 4b93048044eb..97e7ce9b50ed 100644 --- a/trunk/arch/mips/cavium-octeon/smp.c +++ b/trunk/arch/mips/cavium-octeon/smp.c @@ -257,6 +257,8 @@ DEFINE_PER_CPU(int, cpu_state); extern void fixup_irqs(void); +static DEFINE_SPINLOCK(smp_reserve_lock); + static int octeon_cpu_disable(void) { unsigned int cpu = smp_processor_id(); @@ -264,6 +266,8 @@ static int octeon_cpu_disable(void) if (cpu == 0) return -EBUSY; + spin_lock(&smp_reserve_lock); + set_cpu_online(cpu, false); cpu_clear(cpu, cpu_callin_map); local_irq_disable(); @@ -273,6 +277,8 @@ static int octeon_cpu_disable(void) flush_cache_all(); local_flush_tlb_all(); + spin_unlock(&smp_reserve_lock); + return 0; } diff --git a/trunk/arch/mips/include/asm/setup.h b/trunk/arch/mips/include/asm/setup.h index 2560b6b6a7d8..6dce6d8d09ab 100644 --- a/trunk/arch/mips/include/asm/setup.h +++ b/trunk/arch/mips/include/asm/setup.h @@ -14,8 +14,7 @@ extern void *set_vi_handler(int n, vi_handler_t addr); extern void *set_except_vector(int n, void *addr); extern unsigned long ebase; -extern void per_cpu_trap_init(bool); -extern void cpu_cache_init(void); +extern void per_cpu_trap_init(void); #endif /* __KERNEL__ */ diff --git a/trunk/arch/mips/include/asm/traps.h b/trunk/arch/mips/include/asm/traps.h index 420ca06b2f42..ff74aec3561a 100644 --- a/trunk/arch/mips/include/asm/traps.h +++ b/trunk/arch/mips/include/asm/traps.h @@ -25,7 +25,6 @@ extern void (*board_nmi_handler_setup)(void); extern void (*board_ejtag_handler_setup)(void); extern void (*board_bind_eic_interrupt)(int irq, int regset); extern void (*board_ebase_setup)(void); -extern void (*board_cache_error_setup)(void); extern int register_nmi_notifier(struct notifier_block *nb); diff --git a/trunk/arch/mips/kernel/setup.c b/trunk/arch/mips/kernel/setup.c index a53f8ec37aac..c504b212f8f3 100644 --- a/trunk/arch/mips/kernel/setup.c +++ b/trunk/arch/mips/kernel/setup.c @@ -605,8 +605,6 @@ void __init setup_arch(char **cmdline_p) resource_init(); plat_smp_setup(); - - cpu_cache_init(); } unsigned long kernelsp[NR_CPUS]; diff --git a/trunk/arch/mips/kernel/smp.c b/trunk/arch/mips/kernel/smp.c index dc019a1f128d..ba9376bf52a1 100644 --- a/trunk/arch/mips/kernel/smp.c +++ b/trunk/arch/mips/kernel/smp.c @@ -106,7 +106,7 @@ asmlinkage __cpuinit void start_secondary(void) #endif /* CONFIG_MIPS_MT_SMTC */ cpu_probe(); cpu_report(); - per_cpu_trap_init(false); + per_cpu_trap_init(); mips_clockevent_init(); mp_ops->init_secondary(); diff --git a/trunk/arch/mips/kernel/traps.c b/trunk/arch/mips/kernel/traps.c index 8e3488afbcc1..cfdaaa4cffc0 100644 --- a/trunk/arch/mips/kernel/traps.c +++ b/trunk/arch/mips/kernel/traps.c @@ -91,7 +91,7 @@ void (*board_nmi_handler_setup)(void); void (*board_ejtag_handler_setup)(void); void (*board_bind_eic_interrupt)(int irq, int regset); void (*board_ebase_setup)(void); -void __cpuinitdata(*board_cache_error_setup)(void); + static void show_raw_backtrace(unsigned long reg29) { @@ -1490,6 +1490,7 @@ void *set_vi_handler(int n, vi_handler_t addr) return set_vi_srs_handler(n, addr, 0); } +extern void cpu_cache_init(void); extern void tlb_init(void); extern void flush_tlb_handlers(void); @@ -1516,7 +1517,7 @@ static int __init ulri_disable(char *s) } __setup("noulri", ulri_disable); -void __cpuinit per_cpu_trap_init(bool is_boot_cpu) +void __cpuinit per_cpu_trap_init(void) { unsigned int cpu = smp_processor_id(); unsigned int status_set = ST0_CU0; @@ -1615,9 +1616,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) #ifdef CONFIG_MIPS_MT_SMTC if (bootTC) { #endif /* CONFIG_MIPS_MT_SMTC */ - /* Boot CPU's cache setup in setup_arch(). */ - if (!is_boot_cpu) - cpu_cache_init(); + cpu_cache_init(); tlb_init(); #ifdef CONFIG_MIPS_MT_SMTC } else if (!secondaryTC) { @@ -1633,7 +1632,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) } /* Install CPU exception handler */ -void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) +void __init set_handler(unsigned long offset, void *addr, unsigned long size) { memcpy((void *)(ebase + offset), addr, size); local_flush_icache_range(ebase + offset, ebase + offset + size); @@ -1694,7 +1693,7 @@ void __init trap_init(void) if (board_ebase_setup) board_ebase_setup(); - per_cpu_trap_init(true); + per_cpu_trap_init(); /* * Copy the generic exception handlers to their final destination. @@ -1798,9 +1797,6 @@ void __init trap_init(void) set_except_vector(26, handle_dsp); - if (board_cache_error_setup) - board_cache_error_setup(); - if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); diff --git a/trunk/arch/mips/mm/c-octeon.c b/trunk/arch/mips/mm/c-octeon.c index 44e69e7a4519..47037ec5589b 100644 --- a/trunk/arch/mips/mm/c-octeon.c +++ b/trunk/arch/mips/mm/c-octeon.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include @@ -249,11 +248,6 @@ static void __cpuinit probe_octeon(void) } } -static void __cpuinit octeon_cache_error_setup(void) -{ - extern char except_vec2_octeon; - set_handler(0x100, &except_vec2_octeon, 0x80); -} /** * Setup the Octeon cache flush routines @@ -261,6 +255,12 @@ static void __cpuinit octeon_cache_error_setup(void) */ void __cpuinit octeon_cache_init(void) { + extern unsigned long ebase; + extern char except_vec2_octeon; + + memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80); + octeon_flush_cache_sigtramp(ebase + 0x100); + probe_octeon(); shm_align_mask = PAGE_SIZE - 1; @@ -280,8 +280,6 @@ void __cpuinit octeon_cache_init(void) build_clear_page(); build_copy_page(); - - board_cache_error_setup = octeon_cache_error_setup; } /** diff --git a/trunk/arch/mips/mm/c-r4k.c b/trunk/arch/mips/mm/c-r4k.c index 5109be96d98d..bda8eb26ece7 100644 --- a/trunk/arch/mips/mm/c-r4k.c +++ b/trunk/arch/mips/mm/c-r4k.c @@ -32,7 +32,7 @@ #include #include #include /* for run_uncached() */ -#include + /* * Special Variant of smp_call_function for use by cache functions: @@ -1385,8 +1385,10 @@ static int __init setcoherentio(char *str) __setup("coherentio", setcoherentio); #endif -static void __cpuinit r4k_cache_error_setup(void) +void __cpuinit r4k_cache_init(void) { + extern void build_clear_page(void); + extern void build_copy_page(void); extern char __weak except_vec2_generic; extern char __weak except_vec2_sb1; struct cpuinfo_mips *c = ¤t_cpu_data; @@ -1401,13 +1403,6 @@ static void __cpuinit r4k_cache_error_setup(void) set_uncached_handler(0x100, &except_vec2_generic, 0x80); break; } -} - -void __cpuinit r4k_cache_init(void) -{ - extern void build_clear_page(void); - extern void build_copy_page(void); - struct cpuinfo_mips *c = ¤t_cpu_data; probe_pcache(); setup_scache(); @@ -1470,5 +1465,4 @@ void __cpuinit r4k_cache_init(void) local_r4k___flush_cache_all(NULL); #endif coherency_setup(); - board_cache_error_setup = r4k_cache_error_setup; } diff --git a/trunk/drivers/tty/serial/zs.c b/trunk/drivers/tty/serial/zs.c index 4001eee6c08d..92c00b24d0df 100644 --- a/trunk/drivers/tty/serial/zs.c +++ b/trunk/drivers/tty/serial/zs.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include