From 19b2022f1ae4c5a09feec4eee5e1ffc3f44b8099 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Wed, 24 Oct 2012 16:48:07 +0100 Subject: [PATCH] --- yaml --- r: 337241 b: refs/heads/master c: 855d5fb469a7e9ac71358248e27d17422ad4c663 h: refs/heads/master i: 337239: bce142d9d70811e60052ac87142dc7c3230eb238 v: v3 --- [refs] | 2 +- trunk/drivers/staging/comedi/drivers/amplc_dio200.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 713112eee50d..07c4a1681adb 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c5f68d79259ee61b58197b0f751411e0196560f2 +refs/heads/master: 855d5fb469a7e9ac71358248e27d17422ad4c663 diff --git a/trunk/drivers/staging/comedi/drivers/amplc_dio200.c b/trunk/drivers/staging/comedi/drivers/amplc_dio200.c index cf53e84c3bc4..1fc6d63398eb 100644 --- a/trunk/drivers/staging/comedi/drivers/amplc_dio200.c +++ b/trunk/drivers/staging/comedi/drivers/amplc_dio200.c @@ -269,6 +269,9 @@ #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */ #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */ #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */ +/* Extra registers for new PCIe boards */ +#define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */ +#define DIO200_VERSION 0x24 /* Hardware version register */ /* * Macros for constructing value for DIO_200_?CLK_SCE and @@ -457,6 +460,7 @@ struct dio200_layout { unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */ char has_int_sce; /* has interrupt enable/status register */ char has_clk_gat_sce; /* has clock/gate selection registers */ + char has_enhancements; /* has enhanced features */ }; static const struct dio200_layout dio200_layouts[] = { @@ -519,6 +523,7 @@ static const struct dio200_layout dio200_layouts[] = { 0x10, 0x14, 0x00, 0x3F}, .has_int_sce = 1, .has_clk_gat_sce = 1, + .has_enhancements = 1, }, [pcie236_layout] = { .n_subdevs = 8, @@ -528,6 +533,7 @@ static const struct dio200_layout dio200_layouts[] = { 0x10, 0x14, 0x00, 0x3F}, .has_int_sce = 1, .has_clk_gat_sce = 1, + .has_enhancements = 1, }, [pcie296_layout] = { .n_subdevs = 8, @@ -537,6 +543,7 @@ static const struct dio200_layout dio200_layouts[] = { 0x10, 0x14, 0x00, 0x3F}, .has_int_sce = 1, .has_clk_gat_sce = 1, + .has_enhancements = 1, }, #endif }; @@ -1571,6 +1578,8 @@ static int dio200_pcie_board_setup(struct comedi_device *dev) } writel(0x80, brbase + 0x50); iounmap(brbase); + /* Enable "enhanced" features of board. */ + dio200_write8(dev, DIO200_ENHANCE, 1); return 0; }