From 19be53243c7fa7d4ac46122c1f0825b5a68ffed2 Mon Sep 17 00:00:00 2001 From: Mengdong Lin Date: Wed, 12 Dec 2012 09:16:15 -0500 Subject: [PATCH] --- yaml --- r: 342998 b: refs/heads/master c: fa348da53b6ffd3dcebae288d4072a4571755d35 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/sound/pci/hda/hda_intel.c | 20 +++++++++++--------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/[refs] b/[refs] index 30e300651896..45c78b43cb7b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6121b84af33fcec843a082cb6bc8d39f187faa20 +refs/heads/master: fa348da53b6ffd3dcebae288d4072a4571755d35 diff --git a/trunk/sound/pci/hda/hda_intel.c b/trunk/sound/pci/hda/hda_intel.c index a9cd18b3db7c..d00dea0eb7f9 100644 --- a/trunk/sound/pci/hda/hda_intel.c +++ b/trunk/sound/pci/hda/hda_intel.c @@ -1054,7 +1054,7 @@ static void azx_power_notify(struct hda_bus *bus, bool power_up); /* reset codec link */ static int azx_reset(struct azx *chip, int full_reset) { - int count; + unsigned long timeout; if (!full_reset) goto __skip; @@ -1065,24 +1065,26 @@ static int azx_reset(struct azx *chip, int full_reset) /* reset controller */ azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); - count = 50; - while (azx_readb(chip, GCTL) && --count) - msleep(1); + timeout = jiffies + msecs_to_jiffies(100); + while (azx_readb(chip, GCTL) && + time_before(jiffies, timeout)) + usleep_range(500, 1000); /* delay for >= 100us for codec PLL to settle per spec * Rev 0.9 section 5.5.1 */ - msleep(1); + usleep_range(500, 1000); /* Bring controller out of reset */ azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); - count = 50; - while (!azx_readb(chip, GCTL) && --count) - msleep(1); + timeout = jiffies + msecs_to_jiffies(100); + while (!azx_readb(chip, GCTL) && + time_before(jiffies, timeout)) + usleep_range(500, 1000); /* Brent Chartrand said to wait >= 540us for codecs to initialize */ - msleep(1); + usleep_range(1000, 1200); __skip: /* check to see if controller is ready */