From 1a8a2be753151c1ada3fc8e20aa3bf425df592ba Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 7 Oct 2010 16:01:25 -0700 Subject: [PATCH] --- yaml --- r: 218303 b: refs/heads/master c: 382b09362711d7d03272230a33767015a277926e h: refs/heads/master i: 218301: a3b94f79e4463c58973c36da0fb0244b02872c2c 218299: 3d42cac94eb969eaacd7f52c4e3d2abd0061995f 218295: 642e4becc2068f5d4a72ea9e15cc54bbd40a0fe7 218287: 56785c3deb9dcc1b3c7e623b1ba3052ac5a964db 218271: b12d92a3b82c0e95e0eda78a3b9420e3ef537a82 218239: c45a196f719555f1532026c2495dfb5bc84a1dbe v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 3 +++ trunk/drivers/gpu/drm/i915/intel_display.c | 7 +++++++ 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index ffb9772db903..f7351c4359b7 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 298b0b392c750137f148fda056a7d4c42019814c +refs/heads/master: 382b09362711d7d03272230a33767015a277926e diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index 5a22887a5381..88292893b255 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -2784,6 +2784,9 @@ #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN) +#define SOUTH_DSPCLK_GATE_D 0xc2020 +#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) + /* CPU: FDI_TX */ #define FDI_TXA_CTL 0x60100 #define FDI_TXB_CTL 0x61100 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 89cfe4684147..8e98d708f970 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -5745,6 +5745,13 @@ void intel_init_clock_gating(struct drm_device *dev) I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); + /* + * On Ibex Peak and Cougar Point, we need to disable clock + * gating for the panel power sequencer or it will fail to + * start up when no ports are active. + */ + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); + /* * According to the spec the following bits should be set in * order to enable memory self-refresh