From 1afaa37aa795546949bb8d625d2fb91462aaa972 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Sun, 31 Mar 2013 20:22:21 -0600 Subject: [PATCH] --- yaml --- r: 370165 b: refs/heads/master c: da91b89eb76d4ecddcfc7fca3b8422891eb5e62e h: refs/heads/master i: 370163: e2101c3b6a863702fd1e61cc228917d249d74589 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/cclock33xx_data.c | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 85ff9ce9d83e..99ac65431e19 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 05cf03b6eb7f791ad70b1540df2c39b54d428258 +refs/heads/master: da91b89eb76d4ecddcfc7fca3b8422891eb5e62e diff --git a/trunk/arch/arm/mach-omap2/cclock33xx_data.c b/trunk/arch/arm/mach-omap2/cclock33xx_data.c index 476b82066cb6..7f091c85384e 100644 --- a/trunk/arch/arm/mach-omap2/cclock33xx_data.c +++ b/trunk/arch/arm/mach-omap2/cclock33xx_data.c @@ -958,6 +958,14 @@ int __init am33xx_clk_init(void) clk_set_parent(&timer3_fck, &sys_clkin_ck); clk_set_parent(&timer6_fck, &sys_clkin_ck); + /* + * The On-Chip 32K RC Osc clock is not an accurate clock-source as per + * the design/spec, so as a result, for example, timer which supposed + * to get expired @60Sec, but will expire somewhere ~@40Sec, which is + * not expected by any use-case, so change WDT1 clock source to PRCM + * 32KHz clock. + */ + clk_set_parent(&wdt1_fck, &clkdiv32k_ick); return 0; }