From 1bc947fd422d30a9d0de44cde3c6f7bf38874f0a Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Tue, 15 Jul 2008 12:08:50 +0800 Subject: [PATCH] --- yaml --- r: 106282 b: refs/heads/master c: 1c0d20cd29aec11a3580cedf0bccec25052e8d4c h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/include/asm-blackfin/mach-bf527/anomaly.h | 2 ++ trunk/include/asm-blackfin/mach-bf527/defBF527.h | 1 + trunk/include/asm-blackfin/mach-bf537/defBF537.h | 1 + 4 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 3db080a89ebe..5bbf9a6b1163 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c71b47835188d0c2a1e1f9590564f1b71c651710 +refs/heads/master: 1c0d20cd29aec11a3580cedf0bccec25052e8d4c diff --git a/trunk/include/asm-blackfin/mach-bf527/anomaly.h b/trunk/include/asm-blackfin/mach-bf527/anomaly.h index 4725268a5ada..b7b166f4f064 100644 --- a/trunk/include/asm-blackfin/mach-bf527/anomaly.h +++ b/trunk/include/asm-blackfin/mach-bf527/anomaly.h @@ -23,6 +23,8 @@ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) +/* New Feature: EMAC TX DMA Word Alignment */ +#define ANOMALY_05000285 (1) /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ diff --git a/trunk/include/asm-blackfin/mach-bf527/defBF527.h b/trunk/include/asm-blackfin/mach-bf527/defBF527.h index 82134f578f32..f1a70db70cb8 100644 --- a/trunk/include/asm-blackfin/mach-bf527/defBF527.h +++ b/trunk/include/asm-blackfin/mach-bf527/defBF527.h @@ -302,6 +302,7 @@ #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ +#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ diff --git a/trunk/include/asm-blackfin/mach-bf537/defBF537.h b/trunk/include/asm-blackfin/mach-bf537/defBF537.h index 3f455909c418..abde24c6d3b1 100644 --- a/trunk/include/asm-blackfin/mach-bf537/defBF537.h +++ b/trunk/include/asm-blackfin/mach-bf537/defBF537.h @@ -290,6 +290,7 @@ #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ +#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */