From 1c3ab1258784b62f9b4f06d76007860fdcbb90f8 Mon Sep 17 00:00:00 2001 From: Thiemo Seufer Date: Wed, 5 Sep 2007 17:44:50 +0100 Subject: [PATCH] --- yaml --- r: 66154 b: refs/heads/master c: bcb0fd94633afde9c1f4f8aca43141ba2c78f04b h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/include/asm-mips/mach-excite/cpu-feature-overrides.h | 5 +++++ trunk/include/asm-mips/mach-sibyte/cpu-feature-overrides.h | 7 ++++++- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 22ddc050b6fd..f9ba0d9f208e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 7ca16d269a1a4b96d98968b48f137977bcab1522 +refs/heads/master: bcb0fd94633afde9c1f4f8aca43141ba2c78f04b diff --git a/trunk/include/asm-mips/mach-excite/cpu-feature-overrides.h b/trunk/include/asm-mips/mach-excite/cpu-feature-overrides.h index 07f4322c235d..107104c3cd12 100644 --- a/trunk/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ b/trunk/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -34,6 +34,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff --git a/trunk/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/trunk/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index 63d5bf649af1..1c1f92415b9a 100644 --- a/trunk/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/trunk/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -9,7 +9,7 @@ #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H /* - * Sibyte are MIPS64 processors weired to a specific configuration + * Sibyte are MIPS64 processors wired to a specific configuration */ #define cpu_has_watch 1 #define cpu_has_mips16 0 @@ -33,6 +33,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32