From 1c5b72f258e059b280f962ecc2f9705430d8e30a Mon Sep 17 00:00:00 2001 From: Eugeni Dodonov Date: Thu, 29 Mar 2012 12:32:29 -0300 Subject: [PATCH] --- yaml --- r: 307037 b: refs/heads/master c: 7501a4d846c9ca3d448f0eee102ebc409d9c1b19 h: refs/heads/master i: 307035: 23578c94a92dcb4fe7d82a4948bf07de62e9ebcc v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index b2697b19e4da..d925829ea4d7 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bb879a44ffd5f708be14b1578239e51b2a4555e8 +refs/heads/master: 7501a4d846c9ca3d448f0eee102ebc409d9c1b19 diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index a87f41c92243..542128c80546 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -4116,4 +4116,16 @@ DDI_BUF_TRANS_A, \ DDI_BUF_TRANS_B) +/* Sideband Interface (SBI) is programmed indirectly, via + * SBI_ADDR, which contains the register offset; and SBI_DATA, + * which contains the payload */ +#define SBI_ADDR 0xC6000 +#define SBI_DATA 0xC6004 +#define SBI_CTL_STAT 0xC6008 +#define SBI_CTL_OP_CRRD (0x6<<8) +#define SBI_CTL_OP_CRWR (0x7<<8) +#define SBI_RESPONSE_FAIL (0x1<<1) +#define SBI_RESPONSE_SUCCESS (0x0<<1) +#define SBI_BUSY (0x1<<0) +#define SBI_READY (0x0<<0) #endif /* _I915_REG_H_ */