From 1c71549b247bf7398390678b6c2a425884273557 Mon Sep 17 00:00:00 2001
From: Mark Rutland <mark.rutland@arm.com>
Date: Wed, 17 Aug 2011 18:03:17 +0100
Subject: [PATCH] --- yaml --- r: 264604 b: refs/heads/master c:
 8d4e652d1b2539196efaef051956fa29e22e9c10 h: refs/heads/master v: v3

---
 [refs]                                               | 2 +-
 trunk/Documentation/devicetree/bindings/arm/l2cc.txt | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 36117d124c06..2ae4637be20d 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 74d41f39a9c161cd0434bb13d929d75fc7be75bd
+refs/heads/master: 8d4e652d1b2539196efaef051956fa29e22e9c10
diff --git a/trunk/Documentation/devicetree/bindings/arm/l2cc.txt b/trunk/Documentation/devicetree/bindings/arm/l2cc.txt
index f50e021a0998..7ca52161e7ab 100644
--- a/trunk/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/trunk/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -28,6 +28,7 @@ Optional properties:
 - arm,filter-ranges : <start length> Starting address and length of window to
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
+- interrupts : 1 combined interrupt.
 
 Example:
 
@@ -39,4 +40,5 @@ L2: cache-controller {
         arm,filter-latency = <0x80000000 0x8000000>;
         cache-unified;
         cache-level = <2>;
+	interrupts = <45>;
 };