From 1cd0b61bd89acea6c368e4133f5b94e240796ed4 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Tue, 7 Sep 2010 14:48:06 -0700 Subject: [PATCH] --- yaml --- r: 217947 b: refs/heads/master c: 434ed097245423c5ea277d18121c0fad0df42abf h: refs/heads/master i: 217945: 021fa46cfc996763f72cb6a85d837dfa769a2e63 217943: 02a8047dc7ca3d6914ea0ba6999bdf4dbeb534ee v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 35 +++++++++++----------- 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/[refs] b/[refs] index 50f1ca7349c4..6f27ad3735ba 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4f0d1aff791db8935ee146fe7928b63bba0f1b59 +refs/heads/master: 434ed097245423c5ea277d18121c0fad0df42abf diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 948a3608d1bd..4b23646304df 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -3909,11 +3909,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, udelay(150); } - if (HAS_PCH_SPLIT(dev)) { - pipeconf &= ~PIPECONF_DITHER_EN; - pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; - } - /* The LVDS pin pair needs to be on before the DPLLs are enabled. * This is an exception to the general rule that mode_set doesn't turn * things on. @@ -3951,23 +3946,27 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, * appropriately here, but we need to look more thoroughly into how * panels behave in the two modes. */ - /* set the dithering flag */ - if (IS_I965G(dev)) { - if (dev_priv->lvds_dither) { - if (HAS_PCH_SPLIT(dev)) { - pipeconf |= PIPECONF_DITHER_EN; - pipeconf |= PIPECONF_DITHER_TYPE_ST1; - } else - lvds |= LVDS_ENABLE_DITHER; - } else { - if (!HAS_PCH_SPLIT(dev)) { - lvds &= ~LVDS_ENABLE_DITHER; - } - } + /* set the dithering flag on non-PCH LVDS as needed */ + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { + if (dev_priv->lvds_dither) + lvds |= LVDS_ENABLE_DITHER; + else + lvds &= ~LVDS_ENABLE_DITHER; } I915_WRITE(lvds_reg, lvds); I915_READ(lvds_reg); } + + /* set the dithering flag and clear for anything other than a panel. */ + if (HAS_PCH_SPLIT(dev)) { + pipeconf &= ~PIPECONF_DITHER_EN; + pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; + if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { + pipeconf |= PIPECONF_DITHER_EN; + pipeconf |= PIPECONF_DITHER_TYPE_ST1; + } + } + if (is_dp) intel_dp_set_m_n(crtc, mode, adjusted_mode); else if (HAS_PCH_SPLIT(dev)) {