From 1cebda4f16d5ddc5755c1b31daa13014bddb1afb Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 22 Apr 2007 10:56:40 +0100 Subject: [PATCH] --- yaml --- r: 54007 b: refs/heads/master c: 7531a1c2c4477f63688871c1648d828f55313d42 h: refs/heads/master i: 54005: 5f0c08829958b9f3a2018c8d174656cd6c723e23 54003: 8a19f8cbe821196b362fede75ce81cbd4a2dbd0a 53999: 25084d72bf7fdf13acf80b3f864bca84254fce93 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-iop13xx/Makefile | 1 - trunk/arch/arm/mach-iop13xx/iq81340mc.c | 5 +- trunk/arch/arm/mach-iop13xx/iq81340sc.c | 5 +- trunk/arch/arm/mach-iop13xx/pci.c | 8 +- trunk/arch/arm/mach-iop13xx/setup.c | 6 +- trunk/arch/arm/mach-iop13xx/tpmi.c | 234 ------------------- trunk/arch/arm/mach-iop32x/Kconfig | 8 - trunk/arch/arm/mach-iop32x/iq31244.c | 11 +- trunk/arch/arm/mach-iop32x/iq80321.c | 3 +- trunk/arch/arm/mach-iop33x/Kconfig | 8 - trunk/arch/arm/mach-iop33x/iq80331.c | 3 +- trunk/arch/arm/mach-iop33x/iq80332.c | 3 +- trunk/arch/arm/plat-iop/pci.c | 140 +---------- trunk/arch/arm/plat-iop/time.c | 8 +- trunk/arch/arm/vfp/vfpdouble.c | 1 - trunk/arch/arm/vfp/vfpsingle.c | 1 - trunk/include/asm-arm/arch-iop13xx/iop13xx.h | 24 +- trunk/include/asm-arm/arch-iop13xx/time.h | 56 ----- trunk/include/asm-arm/arch-iop32x/iop32x.h | 9 - trunk/include/asm-arm/arch-iop32x/memory.h | 4 +- trunk/include/asm-arm/arch-iop33x/iop33x.h | 10 - trunk/include/asm-arm/arch-iop33x/memory.h | 4 +- trunk/include/asm-arm/hardware/iop3xx.h | 24 +- 24 files changed, 42 insertions(+), 536 deletions(-) delete mode 100644 trunk/arch/arm/mach-iop13xx/tpmi.c diff --git a/[refs] b/[refs] index f93d6f35a7d8..431e5506ef09 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ad902cb9e29a4d6ff155f682ae79d8d8b2b73a9b +refs/heads/master: 7531a1c2c4477f63688871c1648d828f55313d42 diff --git a/trunk/arch/arm/mach-iop13xx/Makefile b/trunk/arch/arm/mach-iop13xx/Makefile index da1609dc0dee..4185e0586c33 100644 --- a/trunk/arch/arm/mach-iop13xx/Makefile +++ b/trunk/arch/arm/mach-iop13xx/Makefile @@ -7,6 +7,5 @@ obj-$(CONFIG_ARCH_IOP13XX) += setup.o obj-$(CONFIG_ARCH_IOP13XX) += irq.o obj-$(CONFIG_ARCH_IOP13XX) += pci.o obj-$(CONFIG_ARCH_IOP13XX) += io.o -obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o diff --git a/trunk/arch/arm/mach-iop13xx/iq81340mc.c b/trunk/arch/arm/mach-iop13xx/iq81340mc.c index 268a8d84999c..a519d707571c 100644 --- a/trunk/arch/arm/mach-iop13xx/iq81340mc.c +++ b/trunk/arch/arm/mach-iop13xx/iq81340mc.c @@ -75,14 +75,11 @@ static void __init iq81340mc_init(void) { iop13xx_platform_init(); iq81340mc_pci_init(); - iop13xx_add_tpmi_devices(); } static void __init iq81340mc_timer_init(void) { - unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); - printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq); - iop_init_time(bus_freq); + iop_init_time(400000000); } static struct sys_timer iq81340mc_timer = { diff --git a/trunk/arch/arm/mach-iop13xx/iq81340sc.c b/trunk/arch/arm/mach-iop13xx/iq81340sc.c index a51ffd2683e5..0e71fbcabe00 100644 --- a/trunk/arch/arm/mach-iop13xx/iq81340sc.c +++ b/trunk/arch/arm/mach-iop13xx/iq81340sc.c @@ -77,14 +77,11 @@ static void __init iq81340sc_init(void) { iop13xx_platform_init(); iq81340sc_pci_init(); - iop13xx_add_tpmi_devices(); } static void __init iq81340sc_timer_init(void) { - unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); - printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq); - iop_init_time(bus_freq); + iop_init_time(400000000); } static struct sys_timer iq81340sc_timer = { diff --git a/trunk/arch/arm/mach-iop13xx/pci.c b/trunk/arch/arm/mach-iop13xx/pci.c index d907a2aadfe6..89ec70ea3187 100644 --- a/trunk/arch/arm/mach-iop13xx/pci.c +++ b/trunk/arch/arm/mach-iop13xx/pci.c @@ -1023,7 +1023,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) << IOP13XX_ATUX_PCIXSR_FUNC_NUM; __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); - res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; + res[0].start = IOP13XX_PCIX_LOWER_IO_PA; res[0].end = IOP13XX_PCIX_UPPER_IO_PA; res[0].name = "IQ81340 ATUX PCI I/O Space"; res[0].flags = IORESOURCE_IO; @@ -1033,7 +1033,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) res[1].name = "IQ81340 ATUX PCI Memory Space"; res[1].flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; + sys->io_offset = IOP13XX_PCIX_IO_OFFSET; break; case IOP13XX_INIT_ATU_ATUE: /* Note: the function number field in the PCSR is ro */ @@ -1044,7 +1044,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) __raw_writel(pcsr, IOP13XX_ATUE_PCSR); - res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; + res[0].start = IOP13XX_PCIE_LOWER_IO_PA; res[0].end = IOP13XX_PCIE_UPPER_IO_PA; res[0].name = "IQ81340 ATUE PCI I/O Space"; res[0].flags = IORESOURCE_IO; @@ -1054,7 +1054,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) res[1].name = "IQ81340 ATUE PCI Memory Space"; res[1].flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; + sys->io_offset = IOP13XX_PCIE_IO_OFFSET; sys->map_irq = iop13xx_pcie_map_irq; break; default: diff --git a/trunk/arch/arm/mach-iop13xx/setup.c b/trunk/arch/arm/mach-iop13xx/setup.c index bc4871553f6a..9a46bcd5f18e 100644 --- a/trunk/arch/arm/mach-iop13xx/setup.c +++ b/trunk/arch/arm/mach-iop13xx/setup.c @@ -258,11 +258,15 @@ void __init iop13xx_platform_init(void) if (init_uart == IOP13XX_INIT_UART_DEFAULT) { switch (iop13xx_dev_id()) { - /* enable both uarts on iop341 */ + /* enable both uarts on iop341 and iop342 */ case 0x3380: case 0x3384: case 0x3388: case 0x338c: + case 0x3382: + case 0x3386: + case 0x338a: + case 0x338e: init_uart |= IOP13XX_INIT_UART_0; init_uart |= IOP13XX_INIT_UART_1; break; diff --git a/trunk/arch/arm/mach-iop13xx/tpmi.c b/trunk/arch/arm/mach-iop13xx/tpmi.c deleted file mode 100644 index d3dc278213da..000000000000 --- a/trunk/arch/arm/mach-iop13xx/tpmi.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * iop13xx tpmi device resources - * Copyright (c) 2005-2006, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place - Suite 330, Boston, MA 02111-1307 USA. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -/* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */ -#define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12)) -#define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13)) -#define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10)) -#define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1) -#define IOP13XX_TPMI_MEM_SIZE (255) -#define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1) -#define IOP13XX_TPMI_RESOURCE_MMR 0 -#define IOP13XX_TPMI_RESOURCE_MEM 1 -#define IOP13XX_TPMI_RESOURCE_CTRL 2 -#define IOP13XX_TPMI_RESOURCE_IRQ 3 - -static struct resource iop13xx_tpmi_0_resources[] = { - [IOP13XX_TPMI_RESOURCE_MMR] = { - .start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */ - .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_MEM] = { - .start = IOP13XX_TPMI_MEM(0), - .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_CTRL] = { - .start = IOP13XX_TPMI_CTRL(0), - .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IRQ] = { - .start = IRQ_IOP13XX_TPMI0_OUT, - .end = IRQ_IOP13XX_TPMI0_OUT, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_tpmi_1_resources[] = { - [IOP13XX_TPMI_RESOURCE_MMR] = { - .start = IOP13XX_TPMI_MMR(1), - .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_MEM] = { - .start = IOP13XX_TPMI_MEM(1), - .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_CTRL] = { - .start = IOP13XX_TPMI_CTRL(1), - .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IRQ] = { - .start = IRQ_IOP13XX_TPMI1_OUT, - .end = IRQ_IOP13XX_TPMI1_OUT, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_tpmi_2_resources[] = { - [IOP13XX_TPMI_RESOURCE_MMR] = { - .start = IOP13XX_TPMI_MMR(2), - .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_MEM] = { - .start = IOP13XX_TPMI_MEM(2), - .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_CTRL] = { - .start = IOP13XX_TPMI_CTRL(2), - .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IRQ] = { - .start = IRQ_IOP13XX_TPMI2_OUT, - .end = IRQ_IOP13XX_TPMI2_OUT, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop13xx_tpmi_3_resources[] = { - [IOP13XX_TPMI_RESOURCE_MMR] = { - .start = IOP13XX_TPMI_MMR(3), - .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_MEM] = { - .start = IOP13XX_TPMI_MEM(3), - .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_CTRL] = { - .start = IOP13XX_TPMI_CTRL(3), - .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL, - .flags = IORESOURCE_MEM, - }, - [IOP13XX_TPMI_RESOURCE_IRQ] = { - .start = IRQ_IOP13XX_TPMI3_OUT, - .end = IRQ_IOP13XX_TPMI3_OUT, - .flags = IORESOURCE_IRQ - } -}; - -u64 iop13xx_tpmi_mask = DMA_64BIT_MASK; -static struct platform_device iop13xx_tpmi_0_device = { - .name = "iop-tpmi", - .id = 0, - .num_resources = 4, - .resource = iop13xx_tpmi_0_resources, - .dev = { - .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_64BIT_MASK, - }, -}; - -static struct platform_device iop13xx_tpmi_1_device = { - .name = "iop-tpmi", - .id = 1, - .num_resources = 4, - .resource = iop13xx_tpmi_1_resources, - .dev = { - .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_64BIT_MASK, - }, -}; - -static struct platform_device iop13xx_tpmi_2_device = { - .name = "iop-tpmi", - .id = 2, - .num_resources = 4, - .resource = iop13xx_tpmi_2_resources, - .dev = { - .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_64BIT_MASK, - }, -}; - -static struct platform_device iop13xx_tpmi_3_device = { - .name = "iop-tpmi", - .id = 3, - .num_resources = 4, - .resource = iop13xx_tpmi_3_resources, - .dev = { - .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_64BIT_MASK, - }, -}; - -__init void iop13xx_add_tpmi_devices(void) -{ - unsigned short device_id; - - /* tpmi's not present on iop341 or iop342 */ - if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) - /* ATUE must be present */ - device_id = __raw_readw(IOP13XX_ATUE_DID); - else - /* ATUX must be present */ - device_id = __raw_readw(IOP13XX_ATUX_DID); - - switch (device_id) { - /* iop34[1|2] 0-tpmi */ - case 0x3380: - case 0x3384: - case 0x3388: - case 0x338c: - case 0x3382: - case 0x3386: - case 0x338a: - case 0x338e: - return; - /* iop348 1-tpmi */ - case 0x3310: - case 0x3312: - case 0x3314: - case 0x3318: - case 0x331a: - case 0x331c: - case 0x33c0: - case 0x33c2: - case 0x33c4: - case 0x33c8: - case 0x33ca: - case 0x33cc: - case 0x33b0: - case 0x33b2: - case 0x33b4: - case 0x33b8: - case 0x33ba: - case 0x33bc: - case 0x3320: - case 0x3322: - case 0x3324: - case 0x3328: - case 0x332a: - case 0x332c: - platform_device_register(&iop13xx_tpmi_0_device); - return; - default: - platform_device_register(&iop13xx_tpmi_0_device); - platform_device_register(&iop13xx_tpmi_1_device); - platform_device_register(&iop13xx_tpmi_2_device); - platform_device_register(&iop13xx_tpmi_3_device); - return; - } -} diff --git a/trunk/arch/arm/mach-iop32x/Kconfig b/trunk/arch/arm/mach-iop32x/Kconfig index 9bb02b6d7ae1..9dd49cff21ff 100644 --- a/trunk/arch/arm/mach-iop32x/Kconfig +++ b/trunk/arch/arm/mach-iop32x/Kconfig @@ -34,14 +34,6 @@ config MACH_N2100 Say Y here if you want to run your kernel on the Thecus n2100 NAS appliance. -config IOP3XX_ATU - bool "Enable the PCI Controller" - default y - help - Say Y here if you want the IOP to initialize its PCI Controller. - Say N if the IOP is an add in card, the host system owns the PCI - bus in this case. - endmenu endif diff --git a/trunk/arch/arm/mach-iop32x/iq31244.c b/trunk/arch/arm/mach-iop32x/iq31244.c index 7b21c6e13e59..60e74309a458 100644 --- a/trunk/arch/arm/mach-iop32x/iq31244.c +++ b/trunk/arch/arm/mach-iop32x/iq31244.c @@ -178,10 +178,9 @@ static struct hw_pci iq31244_pci __initdata = { static int __init iq31244_pci_init(void) { - if (is_ep80219()) { - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) - pci_common_init(&ep80219_pci); - } else if (machine_is_iq31244()) { + if (is_ep80219()) + pci_common_init(&ep80219_pci); + else if (machine_is_iq31244()) { if (is_80219()) { printk("note: iq31244 board type has been selected\n"); printk("note: to select ep80219 operation:\n"); @@ -190,9 +189,7 @@ static int __init iq31244_pci_init(void) printk("\t2/ update boot loader to pass" " the ep80219 id: %d\n", MACH_TYPE_EP80219); } - - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) - pci_common_init(&iq31244_pci); + pci_common_init(&iq31244_pci); } return 0; diff --git a/trunk/arch/arm/mach-iop32x/iq80321.c b/trunk/arch/arm/mach-iop32x/iq80321.c index bc25fb91e7b9..361c70c0f64c 100644 --- a/trunk/arch/arm/mach-iop32x/iq80321.c +++ b/trunk/arch/arm/mach-iop32x/iq80321.c @@ -113,8 +113,7 @@ static struct hw_pci iq80321_pci __initdata = { static int __init iq80321_pci_init(void) { - if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) && - machine_is_iq80321()) + if (machine_is_iq80321()) pci_common_init(&iq80321_pci); return 0; diff --git a/trunk/arch/arm/mach-iop33x/Kconfig b/trunk/arch/arm/mach-iop33x/Kconfig index 45598e096898..9aa016bb18f9 100644 --- a/trunk/arch/arm/mach-iop33x/Kconfig +++ b/trunk/arch/arm/mach-iop33x/Kconfig @@ -16,14 +16,6 @@ config MACH_IQ80332 Say Y here if you want to run your kernel on the Intel IQ80332 evaluation kit for the IOP332 chipset. -config IOP3XX_ATU - bool "Enable the PCI Controller" - default y - help - Say Y here if you want the IOP to initialize its PCI Controller. - Say N if the IOP is an add in card, the host system owns the PCI - bus in this case. - endmenu endif diff --git a/trunk/arch/arm/mach-iop33x/iq80331.c b/trunk/arch/arm/mach-iop33x/iq80331.c index 376c932830be..1a9e36138d80 100644 --- a/trunk/arch/arm/mach-iop33x/iq80331.c +++ b/trunk/arch/arm/mach-iop33x/iq80331.c @@ -96,8 +96,7 @@ static struct hw_pci iq80331_pci __initdata = { static int __init iq80331_pci_init(void) { - if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) && - machine_is_iq80331()) + if (machine_is_iq80331()) pci_common_init(&iq80331_pci); return 0; diff --git a/trunk/arch/arm/mach-iop33x/iq80332.c b/trunk/arch/arm/mach-iop33x/iq80332.c index 58c81496c6f6..96d6f0f3cd21 100644 --- a/trunk/arch/arm/mach-iop33x/iq80332.c +++ b/trunk/arch/arm/mach-iop33x/iq80332.c @@ -96,8 +96,7 @@ static struct hw_pci iq80332_pci __initdata = { static int __init iq80332_pci_init(void) { - if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) && - machine_is_iq80332()) + if (machine_is_iq80332()) pci_common_init(&iq80332_pci); return 0; diff --git a/trunk/arch/arm/plat-iop/pci.c b/trunk/arch/arm/plat-iop/pci.c index e2744b7227c5..b5f6ec35aafb 100644 --- a/trunk/arch/arm/plat-iop/pci.c +++ b/trunk/arch/arm/plat-iop/pci.c @@ -55,7 +55,7 @@ static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where) * This routine checks the status of the last configuration cycle. If an error * was detected it returns a 1, else it returns a 0. The errors being checked * are parity, master abort, target abort (master and target). These types of - * errors occur during a config cycle where there is no device, like during + * errors occure during a config cycle where there is no device, like during * the discovery stage. */ static int iop3xx_pci_status(void) @@ -223,111 +223,8 @@ struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) return pci_scan_bus(sys->busnr, &iop3xx_ops, sys); } -void __init iop3xx_atu_setup(void) -{ - /* BAR 0 ( Disabled ) */ - *IOP3XX_IAUBAR0 = 0x0; - *IOP3XX_IABAR0 = 0x0; - *IOP3XX_IATVR0 = 0x0; - *IOP3XX_IALR0 = 0x0; - - /* BAR 1 ( Disabled ) */ - *IOP3XX_IAUBAR1 = 0x0; - *IOP3XX_IABAR1 = 0x0; - *IOP3XX_IALR1 = 0x0; - - /* BAR 2 (1:1 mapping with Physical RAM) */ - /* Set limit and enable */ - *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1; - *IOP3XX_IAUBAR2 = 0x0; - - /* Align the inbound bar with the base of memory */ - *IOP3XX_IABAR2 = PHYS_OFFSET | - PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH; - - *IOP3XX_IATVR2 = PHYS_OFFSET; - - /* Outbound window 0 */ - *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA; - *IOP3XX_OUMWTVR0 = 0; - - /* Outbound window 1 */ - *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE; - *IOP3XX_OUMWTVR1 = 0; - - /* BAR 3 ( Disabled ) */ - *IOP3XX_IAUBAR3 = 0x0; - *IOP3XX_IABAR3 = 0x0; - *IOP3XX_IATVR3 = 0x0; - *IOP3XX_IALR3 = 0x0; - - /* Setup the I/O Bar - */ - *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;; - - /* Enable inbound and outbound cycles - */ - *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN; -} - -void __init iop3xx_atu_disable(void) -{ - *IOP3XX_ATUCMD = 0; - *IOP3XX_ATUCR = 0; - - /* wait for cycles to quiesce */ - while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY | - IOP3XX_PCSR_IN_Q_BUSY)) - cpu_relax(); - - /* BAR 0 ( Disabled ) */ - *IOP3XX_IAUBAR0 = 0x0; - *IOP3XX_IABAR0 = 0x0; - *IOP3XX_IATVR0 = 0x0; - *IOP3XX_IALR0 = 0x0; - - /* BAR 1 ( Disabled ) */ - *IOP3XX_IAUBAR1 = 0x0; - *IOP3XX_IABAR1 = 0x0; - *IOP3XX_IALR1 = 0x0; - - /* BAR 2 ( Disabled ) */ - *IOP3XX_IAUBAR2 = 0x0; - *IOP3XX_IABAR2 = 0x0; - *IOP3XX_IATVR2 = 0x0; - *IOP3XX_IALR2 = 0x0; - - /* BAR 3 ( Disabled ) */ - *IOP3XX_IAUBAR3 = 0x0; - *IOP3XX_IABAR3 = 0x0; - *IOP3XX_IATVR3 = 0x0; - *IOP3XX_IALR3 = 0x0; - - /* Clear the outbound windows */ - *IOP3XX_OIOWTVR = 0; - - /* Outbound window 0 */ - *IOP3XX_OMWTVR0 = 0; - *IOP3XX_OUMWTVR0 = 0; - - /* Outbound window 1 */ - *IOP3XX_OMWTVR1 = 0; - *IOP3XX_OUMWTVR1 = 0; -} - -/* Flag to determine whether the ATU is initialized and the PCI bus scanned */ -int init_atu; - void iop3xx_pci_preinit(void) { - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { - iop3xx_atu_disable(); - iop3xx_atu_setup(); - } - DBG("PCI: Intel 803xx PCI init code.\n"); DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n", @@ -348,38 +245,3 @@ void iop3xx_pci_preinit(void) hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); } - -/* allow init_atu to be user overridden */ -static int __init iop3xx_init_atu_setup(char *str) -{ - init_atu = IOP3XX_INIT_ATU_DEFAULT; - if (str) { - while (*str != '\0') { - switch (*str) { - case 'y': - case 'Y': - init_atu = IOP3XX_INIT_ATU_ENABLE; - break; - case 'n': - case 'N': - init_atu = IOP3XX_INIT_ATU_DISABLE; - break; - case ',': - case '=': - break; - default: - printk(KERN_DEBUG "\"%s\" malformed at " - "character: \'%c\'", - __FUNCTION__, - *str); - *(str + 1) = '\0'; - } - str++; - } - } - - return 1; -} - -__setup("iop3xx_init_atu", iop3xx_init_atu_setup); - diff --git a/trunk/arch/arm/plat-iop/time.c b/trunk/arch/arm/plat-iop/time.c index 0cc26da034a1..16300adfb4de 100644 --- a/trunk/arch/arm/plat-iop/time.c +++ b/trunk/arch/arm/plat-iop/time.c @@ -32,22 +32,22 @@ static unsigned long next_jiffy_time; unsigned long iop_gettimeoffset(void) { - unsigned long offset, temp; + unsigned long offset, temp1, temp2; /* enable cp6, if necessary, to avoid taking the overhead of an * undefined instruction trap */ asm volatile ( "mrc p15, 0, %0, c15, c1, 0\n\t" - "tst %0, #(1 << 6)\n\t" + "ands %1, %0, #(1 << 6)\n\t" "orreq %0, %0, #(1 << 6)\n\t" "mcreq p15, 0, %0, c15, c1, 0\n\t" -#ifdef CONFIG_CPU_XSCALE +#ifdef CONFIG_XSCALE "mrceq p15, 0, %0, c15, c1, 0\n\t" "moveq %0, %0\n\t" "subeq pc, pc, #4\n\t" #endif - : "=r"(temp) : : "cc"); + : "=r"(temp1), "=r"(temp2) : : "cc"); offset = next_jiffy_time - read_tcr1(); diff --git a/trunk/arch/arm/vfp/vfpdouble.c b/trunk/arch/arm/vfp/vfpdouble.c index e44b9ed0f81f..74e89f8fb3ab 100644 --- a/trunk/arch/arm/vfp/vfpdouble.c +++ b/trunk/arch/arm/vfp/vfpdouble.c @@ -34,7 +34,6 @@ #include #include -#include #include #include "vfpinstr.h" diff --git a/trunk/arch/arm/vfp/vfpsingle.c b/trunk/arch/arm/vfp/vfpsingle.c index 0221ba3bc799..b252631b406b 100644 --- a/trunk/arch/arm/vfp/vfpsingle.c +++ b/trunk/arch/arm/vfp/vfpsingle.c @@ -34,7 +34,6 @@ #include #include -#include #include #include "vfpinstr.h" diff --git a/trunk/include/asm-arm/arch-iop13xx/iop13xx.h b/trunk/include/asm-arm/arch-iop13xx/iop13xx.h index 85707e9c3325..d26b755a9879 100644 --- a/trunk/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/trunk/include/asm-arm/arch-iop13xx/iop13xx.h @@ -8,7 +8,6 @@ extern u32 iop13xx_atue_pmmr_offset; void iop13xx_init_irq(void); void iop13xx_map_io(void); void iop13xx_platform_init(void); -void iop13xx_add_tpmi_devices(void); void iop13xx_init_irq(void); /* CPUID CP6 R0 Page 0 */ @@ -28,24 +27,19 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE /* PCI MAP - * bus range cpu phys cpu virt note - * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM - * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window - * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window - * - * IO MAP - * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window - * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window - */ + * 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM + * 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB) +*/ #define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL #define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL -#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL +#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL #define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ IOP13XX_PCIX_IO_WINDOW_SIZE - 1) #define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ IOP13XX_PCIX_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\ + IOP13XX_PCIX_LOWER_IO_BA) #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ (IOP13XX_PCIX_LOWER_IO_PA\ - IOP13XX_PCIX_LOWER_IO_VA)) @@ -71,14 +65,15 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL #define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL -#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL +#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL #define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ IOP13XX_PCIE_IO_WINDOW_SIZE - 1) #define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ IOP13XX_PCIE_IO_WINDOW_SIZE - 1) #define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\ + IOP13XX_PCIE_LOWER_IO_BA) #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ (IOP13XX_PCIE_LOWER_IO_PA\ - IOP13XX_PCIE_LOWER_IO_VA)) @@ -456,5 +451,4 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) -#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) #endif /* _IOP13XX_HW_H_ */ diff --git a/trunk/include/asm-arm/arch-iop13xx/time.h b/trunk/include/asm-arm/arch-iop13xx/time.h index 49213d9d7cad..77a837a02dec 100644 --- a/trunk/include/asm-arm/arch-iop13xx/time.h +++ b/trunk/include/asm-arm/arch-iop13xx/time.h @@ -7,65 +7,9 @@ #define IOP_TMR_PRIVILEGED 0x08 #define IOP_TMR_RATIO_1_1 0x00 -#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19) -#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19) -#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19) -#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19) -#define IOP13XX_CORE_FREQ_MASK (7 << 16) -#define IOP13XX_CORE_FREQ_600 (0 << 16) -#define IOP13XX_CORE_FREQ_667 (1 << 16) -#define IOP13XX_CORE_FREQ_800 (2 << 16) -#define IOP13XX_CORE_FREQ_933 (3 << 16) -#define IOP13XX_CORE_FREQ_1000 (4 << 16) -#define IOP13XX_CORE_FREQ_1200 (5 << 16) - void iop_init_time(unsigned long tickrate); unsigned long iop_gettimeoffset(void); -static inline unsigned long iop13xx_core_freq(void) -{ - unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ); - freq &= IOP13XX_CORE_FREQ_MASK; - switch (freq) { - case IOP13XX_CORE_FREQ_600: - return 600000000; - case IOP13XX_CORE_FREQ_667: - return 667000000; - case IOP13XX_CORE_FREQ_800: - return 800000000; - case IOP13XX_CORE_FREQ_933: - return 933000000; - case IOP13XX_CORE_FREQ_1000: - return 1000000000; - case IOP13XX_CORE_FREQ_1200: - return 1200000000; - default: - printk("%s: warning unknown frequency, defaulting to 800Mhz\n", - __FUNCTION__); - } - - return 800000000; -} - -static inline unsigned long iop13xx_xsi_bus_ratio(void) -{ - unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ); - ratio &= IOP13XX_XSI_FREQ_RATIO_MASK; - switch (ratio) { - case IOP13XX_XSI_FREQ_RATIO_2: - return 2; - case IOP13XX_XSI_FREQ_RATIO_3: - return 3; - case IOP13XX_XSI_FREQ_RATIO_4: - return 4; - default: - printk("%s: warning unknown ratio, defaulting to 2\n", - __FUNCTION__); - } - - return 2; -} - static inline void write_tmr0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); diff --git a/trunk/include/asm-arm/arch-iop32x/iop32x.h b/trunk/include/asm-arm/arch-iop32x/iop32x.h index 0d8af57221a1..2e9469047eb1 100644 --- a/trunk/include/asm-arm/arch-iop32x/iop32x.h +++ b/trunk/include/asm-arm/arch-iop32x/iop32x.h @@ -24,14 +24,5 @@ #include -/* ATU Parameters - * set up a 1:1 bus to physical ram relationship - * w/ physical ram on top of pci in the memory map - */ -#define IOP32X_MAX_RAM_SIZE 0x40000000UL -#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE -#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000 -#define IOP32X_PCI_MEM_WINDOW_SIZE 0x04000000 -#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP32X_PCI_MEM_WINDOW_SIZE #endif diff --git a/trunk/include/asm-arm/arch-iop32x/memory.h b/trunk/include/asm-arm/arch-iop32x/memory.h index c51072af214e..764cd3f0d416 100644 --- a/trunk/include/asm-arm/arch-iop32x/memory.h +++ b/trunk/include/asm-arm/arch-iop32x/memory.h @@ -19,8 +19,8 @@ * bus_to_virt: Used to convert an address for DMA operations * to an address that the kernel can use. */ -#define __virt_to_bus(x) (__virt_to_phys(x)) -#define __bus_to_virt(x) (__phys_to_virt(x)) +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2))) #endif diff --git a/trunk/include/asm-arm/arch-iop33x/iop33x.h b/trunk/include/asm-arm/arch-iop33x/iop33x.h index 766985b9a723..7ac6e93db5ff 100644 --- a/trunk/include/asm-arm/arch-iop33x/iop33x.h +++ b/trunk/include/asm-arm/arch-iop33x/iop33x.h @@ -29,15 +29,5 @@ #define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740) #define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740) -/* ATU Parameters - * set up a 1:1 bus to physical ram relationship - * w/ pci on top of physical ram in memory map - */ -#define IOP33X_MAX_RAM_SIZE 0x80000000UL -#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE -#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE) -#define IOP33X_PCI_MEM_WINDOW_SIZE 0x08000000 -#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP33X_PCI_MEM_WINDOW_SIZE - #endif diff --git a/trunk/include/asm-arm/arch-iop33x/memory.h b/trunk/include/asm-arm/arch-iop33x/memory.h index c8749127d6ab..0d39139b241e 100644 --- a/trunk/include/asm-arm/arch-iop33x/memory.h +++ b/trunk/include/asm-arm/arch-iop33x/memory.h @@ -19,8 +19,8 @@ * bus_to_virt: Used to convert an address for DMA operations * to an address that the kernel can use. */ -#define __virt_to_bus(x) (__virt_to_phys(x)) -#define __bus_to_virt(x) (__phys_to_virt(x)) +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2))) #endif diff --git a/trunk/include/asm-arm/hardware/iop3xx.h b/trunk/include/asm-arm/hardware/iop3xx.h index 63feceb7ede5..15141a9caca8 100644 --- a/trunk/include/asm-arm/hardware/iop3xx.h +++ b/trunk/include/asm-arm/hardware/iop3xx.h @@ -28,7 +28,6 @@ extern void gpio_line_config(int line, int direction); extern int gpio_line_get(int line); extern void gpio_line_set(int line, int value); -extern int init_atu; #endif @@ -42,7 +41,7 @@ extern int init_atu; IOP3XX_PERIPHERAL_SIZE - 1) #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\ IOP3XX_PERIPHERAL_SIZE - 1) -#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\ +#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ (IOP3XX_PERIPHERAL_PHYS_BASE\ - IOP3XX_PERIPHERAL_VIRT_BASE)) #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) @@ -104,21 +103,6 @@ extern int init_atu; #define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2) #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) -#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15) -#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14) -#define IOP3XX_ATUCR_OUT_EN (1 << 1) - -#define IOP3XX_INIT_ATU_DEFAULT 0 -#define IOP3XX_INIT_ATU_DISABLE -1 -#define IOP3XX_INIT_ATU_ENABLE 1 - -#ifdef CONFIG_IOP3XX_ATU -#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ - IOP3XX_INIT_ATU_ENABLE : init_atu) -#else -#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ - IOP3XX_INIT_ATU_DISABLE : init_atu) -#endif /* Messaging Unit */ #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) @@ -269,12 +253,14 @@ extern int init_atu; /* * IOP3XX I/O and Mem space regions for PCI autoconfiguration */ -#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 +#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000 +#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 +#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0) #define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 #define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 -#define IOP3XX_PCI_LOWER_IO_BA 0x90000000 +#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR) #define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ IOP3XX_PCI_IO_WINDOW_SIZE - 1) #define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\