From 1d2ea28ccca3c8e4bcdd74af74e1265b94811610 Mon Sep 17 00:00:00 2001 From: Yi Li Date: Fri, 19 Jun 2009 08:51:11 +0000 Subject: [PATCH] --- yaml --- r: 153888 b: refs/heads/master c: 986d6c1e05642edac81cb8cc99f36a26d16ef220 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/blackfin/include/asm/traps.h | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index b6ce06af607a..2705bf6c7e65 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bd854c077e660b5f44b5049219645042bcba61ac +refs/heads/master: 986d6c1e05642edac81cb8cc99f36a26d16ef220 diff --git a/trunk/arch/blackfin/include/asm/traps.h b/trunk/arch/blackfin/include/asm/traps.h index 34f7295fb070..3cdc454cde23 100644 --- a/trunk/arch/blackfin/include/asm/traps.h +++ b/trunk/arch/blackfin/include/asm/traps.h @@ -111,9 +111,7 @@ level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" #define EXC_0x2A(level) \ "Instruction fetch misaligned address violation\n" \ - level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ - level " exception, the return address provided in RETX is the destination address which is\n" \ - level " misaligned, rather than the address of the offending instruction.\n" + level " - Attempted misaligned instruction cache fetch.\n" #define EXC_0x2B(level) \ "CPLB protection violation\n" \ level " - Illegal instruction fetch access (memory protection violation).\n"