diff --git a/[refs] b/[refs] index 037429daba12..c9343fb81501 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 228e3023eb0430b4b9ed0736f8f87c96a6cd9c7a +refs/heads/master: 99ffe6f4c2984959cd327bb4143eea9fec0052ef diff --git a/trunk/CREDITS b/trunk/CREDITS index afaa7cec6ea5..948e0fb9a70e 100644 --- a/trunk/CREDITS +++ b/trunk/CREDITS @@ -953,11 +953,11 @@ S: Blacksburg, Virginia 24061 S: USA N: Randy Dunlap -E: rdunlap@infradead.org -W: http://www.infradead.org/~rdunlap/ +E: rdunlap@xenotime.net +W: http://www.xenotime.net/linux/linux.html +W: http://www.linux-usb.org D: Linux-USB subsystem, USB core/UHCI/printer/storage drivers D: x86 SMP, ACPI, bootflag hacking -D: documentation, builds S: (ask for current address) S: USA @@ -1510,14 +1510,6 @@ D: Natsemi ethernet D: Cobalt Networks (x86) support D: This-and-That -N: Mark M. Hoffman -E: mhoffman@lightlink.com -D: asb100, lm93 and smsc47b397 hardware monitoring drivers -D: hwmon subsystem core -D: hwmon subsystem maintainer -D: i2c-sis96x and i2c-stub SMBus drivers -S: USA - N: Dirk Hohndel E: hohndel@suse.de D: The XFree86[tm] Project diff --git a/trunk/Documentation/SubmittingPatches b/trunk/Documentation/SubmittingPatches index aa0c1e63f050..c379a2a6949f 100644 --- a/trunk/Documentation/SubmittingPatches +++ b/trunk/Documentation/SubmittingPatches @@ -60,7 +60,8 @@ own source tree. For example: "dontdiff" is a list of files which are generated by the kernel during the build process, and should be ignored in any diff(1)-generated patch. The "dontdiff" file is included in the kernel tree in -2.6.12 and later. +2.6.12 and later. For earlier kernel versions, you can get it +from . Make sure your patch does not include any extra files which do not belong in a patch submission. Make sure to review your patch -after- diff --git a/trunk/Documentation/arm/sunxi/clocks.txt b/trunk/Documentation/arm/sunxi/clocks.txt deleted file mode 100644 index e09a88aa3136..000000000000 --- a/trunk/Documentation/arm/sunxi/clocks.txt +++ /dev/null @@ -1,56 +0,0 @@ -Frequently asked questions about the sunxi clock system -======================================================= - -This document contains useful bits of information that people tend to ask -about the sunxi clock system, as well as accompanying ASCII art when adequate. - -Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the - system? - -A: The 24MHz oscillator allows gating to save power. Indeed, if gated - carelessly the system would stop functioning, but with the right - steps, one can gate it and keep the system running. Consider this - simplified suspend example: - - While the system is operational, you would see something like - - 24MHz 32kHz - | - PLL1 - \ - \_ CPU Mux - | - [CPU] - - When you are about to suspend, you switch the CPU Mux to the 32kHz - oscillator: - - 24Mhz 32kHz - | | - PLL1 | - / - CPU Mux _/ - | - [CPU] - - Finally you can gate the main oscillator - - 32kHz - | - | - / - CPU Mux _/ - | - [CPU] - -Q: Were can I learn more about the sunxi clocks? - -A: The linux-sunxi wiki contains a page documenting the clock registers, - you can find it at - - http://linux-sunxi.org/A10/CCM - - The authoritative source for information at this time is the ccmu driver - released by Allwinner, you can find it at - - https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu diff --git a/trunk/Documentation/clk.txt b/trunk/Documentation/clk.txt index 4274a546eb57..1943fae014fd 100644 --- a/trunk/Documentation/clk.txt +++ b/trunk/Documentation/clk.txt @@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw) }; Below is a matrix detailing which clk_ops are mandatory based upon the -hardware capabilities of that clock. A cell marked as "y" means +hardware capbilities of that clock. A cell marked as "y" means mandatory, a cell marked as "n" implies that either including that -callback is invalid or otherwise unnecessary. Empty cells are either +callback is invalid or otherwise uneccesary. Empty cells are either optional or must be evaluated on a case-by-case basis. clock hardware characteristics diff --git a/trunk/Documentation/device-mapper/dm-raid.txt b/trunk/Documentation/device-mapper/dm-raid.txt index b428556197c9..56fb62b09fc5 100644 --- a/trunk/Documentation/device-mapper/dm-raid.txt +++ b/trunk/Documentation/device-mapper/dm-raid.txt @@ -30,7 +30,6 @@ The target is named "raid" and it accepts the following parameters: raid10 Various RAID10 inspired algorithms chosen by additional params - RAID10: Striped Mirrors (aka 'Striping on top of mirrors') - RAID1E: Integrated Adjacent Stripe Mirroring - - RAID1E: Integrated Offset Stripe Mirroring - and other similar RAID10 variants Reference: Chapter 4 of @@ -65,15 +64,15 @@ The target is named "raid" and it accepts the following parameters: synchronisation state for each region. [raid10_copies <# copies>] - [raid10_format ] + [raid10_format near] These two options are used to alter the default layout of a RAID10 configuration. The number of copies is can be - specified, but the default is 2. There are also three - variations to how the copies are laid down - the default - is "near". Near copies are what most people think of with - respect to mirroring. If these options are left unspecified, - or 'raid10_copies 2' and/or 'raid10_format near' are given, - then the layouts for 2, 3 and 4 devices are: + specified, but the default is 2. There are other variations + to how the copies are laid down - the default and only current + option is "near". Near copies are what most people think of + with respect to mirroring. If these options are left + unspecified, or 'raid10_copies 2' and/or 'raid10_format near' + are given, then the layouts for 2, 3 and 4 devices are: 2 drives 3 drives 4 drives -------- ---------- -------------- A1 A1 A1 A1 A2 A1 A1 A2 A2 @@ -86,33 +85,6 @@ The target is named "raid" and it accepts the following parameters: 3-device layout is what might be called a 'RAID1E - Integrated Adjacent Stripe Mirroring'. - If 'raid10_copies 2' and 'raid10_format far', then the layouts - for 2, 3 and 4 devices are: - 2 drives 3 drives 4 drives - -------- -------------- -------------------- - A1 A2 A1 A2 A3 A1 A2 A3 A4 - A3 A4 A4 A5 A6 A5 A6 A7 A8 - A5 A6 A7 A8 A9 A9 A10 A11 A12 - .. .. .. .. .. .. .. .. .. - A2 A1 A3 A1 A2 A2 A1 A4 A3 - A4 A3 A6 A4 A5 A6 A5 A8 A7 - A6 A5 A9 A7 A8 A10 A9 A12 A11 - .. .. .. .. .. .. .. .. .. - - If 'raid10_copies 2' and 'raid10_format offset', then the - layouts for 2, 3 and 4 devices are: - 2 drives 3 drives 4 drives - -------- ------------ ----------------- - A1 A2 A1 A2 A3 A1 A2 A3 A4 - A2 A1 A3 A1 A2 A2 A1 A4 A3 - A3 A4 A4 A5 A6 A5 A6 A7 A8 - A4 A3 A6 A4 A5 A6 A5 A8 A7 - A5 A6 A7 A8 A9 A9 A10 A11 A12 - A6 A5 A9 A7 A8 A10 A9 A12 A11 - .. .. .. .. .. .. .. .. .. - Here we see layouts closely akin to 'RAID1E - Integrated - Offset Stripe Mirroring'. - <#raid_devs>: The number of devices composing the array. Each device consists of two entries. The first is the device containing the metadata (if any); the second is the one containing the @@ -170,5 +142,3 @@ Version History 1.3.0 Added support for RAID 10 1.3.1 Allow device replacement/rebuild for RAID 10 1.3.2 Fix/improve redundancy checking for RAID10 -1.4.0 Non-functional change. Removes arg from mapping function. -1.4.1 Add RAID10 "far" and "offset" algorithm support. diff --git a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index 1608a54e90e1..b5846e21cc2e 100644 --- a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt @@ -1,84 +1,19 @@ NVIDIA Tegra Power Management Controller (PMC) -The PMC block interacts with an external Power Management Unit. The PMC -mostly controls the entry and exit of the system from different sleep -modes. It provides power-gating controllers for SoC and CPU power-islands. - -Required properties: +Properties: - name : Should be pmc - compatible : Should contain "nvidia,tegra-pmc". - reg : Offset and length of the register set for the device -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "pclk" (The Tegra clock of that name), - "clk32k_in" (The 32KHz clock input to Tegra). - -Optional properties: - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. The PMU is an external Power Management Unit, whose interrupt output signal is fed into the PMC. This signal is optionally inverted, and then fed into the ARM GIC. The PMC is not involved in the detection or handling of this interrupt signal, merely its inversion. -- nvidia,suspend-mode : The suspend mode that the platform should use. - Valid values are 0, 1 and 2: - 0 (LP0): CPU + Core voltage off and DRAM in self-refresh - 1 (LP1): CPU voltage off and DRAM in self-refresh - 2 (LP2): CPU voltage off -- nvidia,core-power-req-active-high : Boolean, core power request active-high -- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high -- nvidia,combined-power-req : Boolean, combined power request for CPU & Core -- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) - is enabled. - -Required properties when nvidia,suspend-mode is specified: -- nvidia,cpu-pwr-good-time : CPU power good time in uS. -- nvidia,cpu-pwr-off-time : CPU power off time in uS. -- nvidia,core-pwr-good-time : - Core power good time in uS. -- nvidia,core-pwr-off-time : Core power off time in uS. - -Required properties when nvidia,suspend-mode=<0>: -- nvidia,lp0-vec : Starting address and length of LP0 vector - The LP0 vector contains the warm boot code that is executed by AVP when - resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 - processor and always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed from the deep - sleep mode, the warm boot code will restore some PLLs, clocks and then - bring up CPU0 for resuming the system. Example: -/ SoC dts including file pmc@7000f400 { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 110>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,lp0-vec = <0xbdffd000 0x2000>; -}; - -/ Tegra board dts file -{ - ... - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - ... }; diff --git a/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt index 4b87ea1194e3..5ddb2e9efaaa 100644 --- a/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt +++ b/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt @@ -35,83 +35,36 @@ Required properties: Timing properties for child nodes. All are optional and default to 0. - - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds - - Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: - - gpmc,cs-on-ns: Assertion time - - gpmc,cs-rd-off-ns: Read deassertion time - - gpmc,cs-wr-off-ns: Write deassertion time - - ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: - - gpmc,adv-on-ns: Assertion time - - gpmc,adv-rd-off-ns: Read deassertion time - - gpmc,adv-wr-off-ns: Write deassertion time - - WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,we-on-ns Assertion time - - gpmc,we-off-ns: Deassertion time - - OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,oe-on-ns: Assertion time - - gpmc,oe-off-ns: Deassertion time - - Access time and cycle time timings (in nanoseconds) corresponding to - GPMC_CONFIG5: - - gpmc,page-burst-access-ns: Multiple access word delay - - gpmc,access-ns: Start-cycle to first data valid delay - - gpmc,rd-cycle-ns: Total read cycle time - - gpmc,wr-cycle-ns: Total write cycle time - - gpmc,bus-turnaround-ns: Turn-around time between successive accesses - - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses - - gpmc,clk-activation-ns: GPMC clock activation time - - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid - data - -Boolean timing parameters. If property is present parameter enabled and -disabled if omitted: - - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock - - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock - - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive - accesses to a different CS - - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive - accesses to the same CS - - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock - - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock - - gpmc,time-para-granularity: Multiply all access times by 2 + - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds + + Chip-select signal timings corresponding to GPMC_CONFIG2: + - gpmc,cs-on: Assertion time + - gpmc,cs-rd-off: Read deassertion time + - gpmc,cs-wr-off: Write deassertion time + + ADV signal timings corresponding to GPMC_CONFIG3: + - gpmc,adv-on: Assertion time + - gpmc,adv-rd-off: Read deassertion time + - gpmc,adv-wr-off: Write deassertion time + + WE signals timings corresponding to GPMC_CONFIG4: + - gpmc,we-on: Assertion time + - gpmc,we-off: Deassertion time + + OE signals timings corresponding to GPMC_CONFIG4: + - gpmc,oe-on: Assertion time + - gpmc,oe-off: Deassertion time + + Access time and cycle time timings corresponding to GPMC_CONFIG5: + - gpmc,page-burst-access: Multiple access word delay + - gpmc,access: Start-cycle to first data valid delay + - gpmc,rd-cycle: Total read cycle time + - gpmc,wr-cycle: Total write cycle time The following are only applicable to OMAP3+ and AM335x: - - gpmc,wr-access-ns: In synchronous write mode, for single or - burst accesses, defines the number of - GPMC_FCLK cycles from start access time - to the GPMC_CLK rising edge used by the - memory device for the first data capture. - - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies - the time when the first data is driven on - the address-data bus. - -GPMC chip-select settings properties for child nodes. All are optional. - -- gpmc,burst-length Page/burst length. Must be 4, 8 or 16. -- gpmc,burst-wrap Enables wrap bursting -- gpmc,burst-read Enables read page/burst mode -- gpmc,burst-write Enables write page/burst mode -- gpmc,device-nand Device is NAND -- gpmc,device-width Total width of device(s) connected to a GPMC - chip-select in bytes. The GPMC supports 8-bit - and 16-bit devices and so this property must be - 1 or 2. -- gpmc,mux-add-data Address and data multiplexing configuration. - Valid values are 1 for address-address-data - multiplexing mode and 2 for address-data - multiplexing mode. -- gpmc,sync-read Enables synchronous read. Defaults to asynchronous - is this is not set. -- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous - is this is not set. -- gpmc,wait-pin Wait-pin used by client. Must be less than - "gpmc,num-waitpins". -- gpmc,wait-on-read Enables wait monitoring on reads. -- gpmc,wait-on-write Enables wait monitoring on writes. + - gpmc,wr-access + - gpmc,wr-data-mux-bus + Example for an AM33xx board: diff --git a/trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt deleted file mode 100644 index 028b493e97ff..000000000000 --- a/trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt +++ /dev/null @@ -1,22 +0,0 @@ -Binding for the axi-clkgen clock generator - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "adi,axi-clkgen". -- #clock-cells : from common clock binding; Should always be set to 0. -- reg : Address and length of the axi-clkgen register set. -- clocks : Phandle and clock specifier for the parent clock. - -Optional properties: -- clock-output-names : From common clock binding. - -Example: - clock@0xff000000 { - compatible = "adi,axi-clkgen"; - #clock-cells = <0>; - reg = <0xff000000 0x1000>; - clocks = <&osc 1>; - }; diff --git a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt deleted file mode 100644 index d6cb083b90a2..000000000000 --- a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt +++ /dev/null @@ -1,303 +0,0 @@ -NVIDIA Tegra114 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra114-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the CAR. - - The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - registers. These IDs often match those in the CAR's RST_DEVICES registers, - but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - this case, those clocks are assigned IDs above 160 in order to highlight - this issue. Implementations that interpret these clock IDs as bit values - within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - explicitly handle these special cases. - - The balance of the clocks controlled by the CAR are assigned IDs of 160 and - above. - - 0 unassigned - 1 unassigned - 2 unassigned - 3 unassigned - 4 rtc - 5 timer - 6 uarta - 7 unassigned (register bit affects uartb and vfir) - 8 unassigned - 9 sdmmc2 - 10 unassigned (register bit affects spdif_in and spdif_out) - 11 i2s1 - 12 i2c1 - 13 ndflash - 14 sdmmc1 - 15 sdmmc4 - 16 unassigned - 17 pwm - 18 i2s2 - 19 epp - 20 unassigned (register bit affects vi and vi_sensor) - 21 2d - 22 usbd - 23 isp - 24 3d - 25 unassigned - 26 disp2 - 27 disp1 - 28 host1x - 29 vcp - 30 i2s0 - 31 unassigned - - 32 unassigned - 33 unassigned - 34 apbdma - 35 unassigned - 36 kbc - 37 unassigned - 38 unassigned - 39 unassigned (register bit affects fuse and fuse_burn) - 40 kfuse - 41 sbc1 - 42 nor - 43 unassigned - 44 sbc2 - 45 unassigned - 46 sbc3 - 47 i2c5 - 48 dsia - 49 unassigned - 50 mipi - 51 hdmi - 52 csi - 53 unassigned - 54 i2c2 - 55 uartc - 56 mipi-cal - 57 emc - 58 usb2 - 59 usb3 - 60 msenc - 61 vde - 62 bsea - 63 bsev - - 64 unassigned - 65 uartd - 66 unassigned - 67 i2c3 - 68 sbc4 - 69 sdmmc3 - 70 unassigned - 71 owr - 72 afi - 73 csite - 74 unassigned - 75 unassigned - 76 la - 77 trace - 78 soc_therm - 79 dtv - 80 ndspeed - 81 i2cslow - 82 dsib - 83 tsec - 84 unassigned - 85 unassigned - 86 unassigned - 87 unassigned - 88 unassigned - 89 xusb_host - 90 unassigned - 91 msenc - 92 csus - 93 unassigned - 94 unassigned - 95 unassigned (bit affects xusb_dev and xusb_dev_src) - - 96 unassigned - 97 unassigned - 98 unassigned - 99 mselect - 100 tsensor - 101 i2s3 - 102 i2s4 - 103 i2c4 - 104 sbc5 - 105 sbc6 - 106 d_audio - 107 apbif - 108 dam0 - 109 dam1 - 110 dam2 - 111 hda2codec_2x - 112 unassigned - 113 audio0_2x - 114 audio1_2x - 115 audio2_2x - 116 audio3_2x - 117 audio4_2x - 118 spdif_2x - 119 actmon - 120 extern1 - 121 extern2 - 122 extern3 - 123 unassigned - 124 unassigned - 125 hda - 126 unassigned - 127 se - - 128 hda2hdmi - 129 unassigned - 130 unassigned - 131 unassigned - 132 unassigned - 133 unassigned - 134 unassigned - 135 unassigned - 136 unassigned - 137 unassigned - 138 unassigned - 139 unassigned - 140 unassigned - 141 unassigned - 142 unassigned - 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src, - xusb_host_src and xusb_ss_src) - 144 cilab - 145 cilcd - 146 cile - 147 dsialp - 148 dsiblp - 149 unassigned - 150 dds - 151 unassigned - 152 dp2 - 153 amx - 154 adx - 155 unassigned (bit affects dfll_ref and dfll_soc) - 156 xusb_ss - - 192 uartb - 193 vfir - 194 spdif_in - 195 spdif_out - 196 vi - 197 vi_sensor - 198 fuse - 199 fuse_burn - 200 clk_32k - 201 clk_m - 202 clk_m_div2 - 203 clk_m_div4 - 204 pll_ref - 205 pll_c - 206 pll_c_out1 - 207 pll_c2 - 208 pll_c3 - 209 pll_m - 210 pll_m_out1 - 211 pll_p - 212 pll_p_out1 - 213 pll_p_out2 - 214 pll_p_out3 - 215 pll_p_out4 - 216 pll_a - 217 pll_a_out0 - 218 pll_d - 219 pll_d_out0 - 220 pll_d2 - 221 pll_d2_out0 - 222 pll_u - 223 pll_u_480M - 224 pll_u_60M - 225 pll_u_48M - 226 pll_u_12M - 227 pll_x - 228 pll_x_out0 - 229 pll_re_vco - 230 pll_re_out - 231 pll_e_out0 - 232 spdif_in_sync - 233 i2s0_sync - 234 i2s1_sync - 235 i2s2_sync - 236 i2s3_sync - 237 i2s4_sync - 238 vimclk_sync - 239 audio0 - 240 audio1 - 241 audio2 - 242 audio3 - 243 audio4 - 244 spdif - 245 clk_out_1 - 246 clk_out_2 - 247 clk_out_3 - 248 blink - 252 xusb_host_src - 253 xusb_falcon_src - 254 xusb_fs_src - 255 xusb_ss_src - 256 xusb_dev_src - 257 xusb_dev - 258 xusb_hs_src - 259 sclk - 260 hclk - 261 pclk - 262 cclk_g - 263 cclk_lp - 264 dfll_ref - 265 dfll_soc - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car 58>; /* usb2 */ - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt index e885680f6b45..0921fac73528 100644 --- a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt @@ -120,8 +120,8 @@ Required properties : 90 clk_d 91 unassigned 92 sus - 93 cdev2 - 94 cdev1 + 93 cdev1 + 94 cdev2 95 unassigned 96 uart2 diff --git a/trunk/Documentation/devicetree/bindings/clock/sunxi.txt b/trunk/Documentation/devicetree/bindings/clock/sunxi.txt deleted file mode 100644 index 20b8479c2760..000000000000 --- a/trunk/Documentation/devicetree/bindings/clock/sunxi.txt +++ /dev/null @@ -1,44 +0,0 @@ -Device Tree Clock bindings for arch-sunxi - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "allwinner,sun4i-osc-clk" - for a gatable oscillator - "allwinner,sun4i-pll1-clk" - for the main PLL clock - "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock - "allwinner,sun4i-axi-clk" - for the AXI clock - "allwinner,sun4i-ahb-clk" - for the AHB clock - "allwinner,sun4i-apb0-clk" - for the APB0 clock - "allwinner,sun4i-apb1-clk" - for the APB1 clock - "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing - -Required properties for all clocks: -- reg : shall be the control register address for the clock. -- clocks : shall be the input parent clock(s) phandle for the clock -- #clock-cells : from common clock binding; shall be set to 0. - -For example: - -osc24M: osc24M@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; - reg = <0x01c20050 0x4>; - clocks = <&osc24M_fixed>; -}; - -pll1: pll1@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; -}; - -cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>; -}; diff --git a/trunk/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt b/trunk/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt new file mode 100644 index 000000000000..f4dc5233167e --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt @@ -0,0 +1,24 @@ +VIA/Wondermedia VT8500 GPIO Controller +----------------------------------------------------- + +Required properties: +- compatible : "via,vt8500-gpio", "wm,wm8505-gpio" + or "wm,wm8650-gpio" depending on your SoC +- reg : Should contain 1 register range (address and length) +- #gpio-cells : should be <3>. + 1) bank + 2) pin number + 3) flags - should be 0 + +Example: + + gpio: gpio-controller@d8110000 { + compatible = "via,vt8500-gpio"; + gpio-controller; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; + }; + + vibrate { + gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */ + }; diff --git a/trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt deleted file mode 100644 index c54c5a9a2a90..000000000000 --- a/trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt +++ /dev/null @@ -1,53 +0,0 @@ -Samsung S3C24XX Interrupt Controllers - -The S3C24XX SoCs contain a custom set of interrupt controllers providing a -varying number of interrupt sources. The set consists of a main- and sub- -controller and on newer SoCs even a second main controller. - -Required properties: -- compatible: Compatible property value should be "samsung,s3c2410-irq" - for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later. - -- reg: Physical base address of the controller and length of memory mapped - region. - -- interrupt-controller : Identifies the node as an interrupt controller - -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 4 and interrupt descriptor shall - have the following format: - - - ctrl_num contains the controller to use: - - 0 ... main controller - - 1 ... sub controller - - 2 ... second main controller on s3c2416 and s3c2450 - parent_irq contains the parent bit in the main controller and will be - ignored in main controllers - ctrl_irq contains the interrupt bit of the controller - type contains the trigger type to use - -Example: - - interrupt-controller@4a000000 { - compatible = "samsung,s3c2410-irq"; - reg = <0x4a000000 0x100>; - interrupt-controller; - #interrupt-cells=<4>; - }; - - [...] - - serial@50000000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50000000 0x4000>; - interrupt-parent = <&subintc>; - interrupts = <1 28 0 4>, <1 28 1 4>; - }; - - rtc@57000000 { - compatible = "samsung,s3c2410-rtc"; - reg = <0x57000000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 30 0 3>, <0 8 0 3>; - }; diff --git a/trunk/Documentation/devicetree/bindings/mfd/ab8500.txt b/trunk/Documentation/devicetree/bindings/mfd/ab8500.txt index c3a14e0ad0ad..13b707b7355c 100644 --- a/trunk/Documentation/devicetree/bindings/mfd/ab8500.txt +++ b/trunk/Documentation/devicetree/bindings/mfd/ab8500.txt @@ -13,6 +13,9 @@ Required parent device properties: 4 = active high level-sensitive 8 = active low level-sensitive +Optional parent device properties: +- reg : contains the PRCMU mailbox address for the AB8500 i2c port + The AB8500 consists of a large and varied group of sub-devices: Device IRQ Names Supply Names Description @@ -83,8 +86,9 @@ Non-standard child device properties: - stericsson,amic2-bias-vamic1 : Analoge Mic wishes to use a non-standard Vamic - stericsson,earpeice-cmv : Earpeice voltage (only: 950 | 1100 | 1270 | 1580) -ab8500 { +ab8500@5 { compatible = "stericsson,ab8500"; + reg = <5>; /* mailbox 5 is i2c */ interrupts = <0 40 0x4>; interrupt-controller; #interrupt-cells = <2>; diff --git a/trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt deleted file mode 100644 index 420b3ab18890..000000000000 --- a/trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt +++ /dev/null @@ -1,98 +0,0 @@ -Device tree bindings for NOR flash connect to TI GPMC - -NOR flash connected to the TI GPMC (found on OMAP boards) are represented as -child nodes of the GPMC controller with a name of "nor". - -All timing relevant properties as well as generic GPMC child properties are -explained in a separate documents. Please refer to -Documentation/devicetree/bindings/bus/ti-gpmc.txt - -Required properties: -- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and - 16-bit devices and so must be either 1 or 2 bytes. -- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt -- gpmc,cs-on-ns: Chip-select assertion time -- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads -- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes -- gpmc,oe-on-ns: Output-enable assertion time -- gpmc,oe-off-ns: Output-enable de-assertion time -- gpmc,we-on-ns Write-enable assertion time -- gpmc,we-off-ns: Write-enable de-assertion time -- gpmc,access-ns: Start cycle to first data capture (read access) -- gpmc,rd-cycle-ns: Total read cycle time -- gpmc,wr-cycle-ns: Total write cycle time -- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt -- reg: Chip-select, base address (relative to chip-select) - and size of NOR flash. Note that base address will be - typically 0 as this is the start of the chip-select. - -Optional properties: -- gpmc,XXX Additional GPMC timings and settings parameters. See - Documentation/devicetree/bindings/bus/ti-gpmc.txt - -Optional properties for partiton table parsing: -- #address-cells: should be set to 1 -- #size-cells: should be set to 1 - -Example: - -gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc", "simple-bus"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x1000>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <0 0 0x10000000 0x08000000>; - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name= "intel,pf48f6000m0y1be"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x08000000>; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - partition@0 { - label = "bootloader-nor"; - reg = <0 0x40000>; - }; - partition@0x40000 { - label = "params-nor"; - reg = <0x40000 0x40000>; - }; - partition@0x80000 { - label = "kernel-nor"; - reg = <0x80000 0x200000>; - }; - partition@0x280000 { - label = "filesystem-nor"; - reg = <0x240000 0x7d80000>; - }; - }; -}; diff --git a/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt index b7529424ac88..deec9da224a2 100644 --- a/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt +++ b/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt @@ -10,8 +10,6 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt Required properties: - reg: The CS line the peripheral is connected to - - gpmc,device-width Width of the ONENAND device connected to the GPMC - in bytes. Must be 1 or 2. Optional properties: @@ -36,7 +34,6 @@ Example for an OMAP3430 board: onenand@0 { reg = <0 0 0>; /* CS0, offset 0 */ - gpmc,device-width = <2>; #address-cells = <1>; #size-cells = <1>; diff --git a/trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt b/trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt deleted file mode 100644 index 24cb4e46f675..000000000000 --- a/trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt +++ /dev/null @@ -1,97 +0,0 @@ -Device tree bindings for Ethernet chip connected to TI GPMC - -Besides being used to interface with external memory devices, the -General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices -such as ethernet controllers to processors using the TI GPMC as a data bus. - -Ethernet controllers connected to TI GPMC are represented as child nodes of -the GPMC controller with an "ethernet" name. - -All timing relevant properties as well as generic GPMC child properties are -explained in a separate documents. Please refer to -Documentation/devicetree/bindings/bus/ti-gpmc.txt - -For the properties relevant to the ethernet controller connected to the GPMC -refer to the binding documentation of the device. For example, the documentation -for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt - -Child nodes need to specify the GPMC bus address width using the "bank-width" -property but is possible that an ethernet controller also has a property to -specify the I/O registers address width. Even when the GPMC has a maximum 16-bit -address width, it supports devices with 32-bit word registers. -For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an -OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". - -Required properties: -- bank-width: Address width of the device in bytes. GPMC supports 8-bit - and 16-bit devices and so must be either 1 or 2 bytes. -- compatible: Compatible string property for the ethernet child device. -- gpmc,cs-on: Chip-select assertion time -- gpmc,cs-rd-off: Chip-select de-assertion time for reads -- gpmc,cs-wr-off: Chip-select de-assertion time for writes -- gpmc,oe-on: Output-enable assertion time -- gpmc,oe-off Output-enable de-assertion time -- gpmc,we-on: Write-enable assertion time -- gpmc,we-off: Write-enable de-assertion time -- gpmc,access: Start cycle to first data capture (read access) -- gpmc,rd-cycle: Total read cycle time -- gpmc,wr-cycle: Total write cycle time -- reg: Chip-select, base address (relative to chip-select) - and size of the memory mapped for the device. - Note that base address will be typically 0 as this - is the start of the chip-select. - -Optional properties: -- gpmc,XXX Additional GPMC timings and settings parameters. See - Documentation/devicetree/bindings/bus/ti-gpmc.txt - -Example: - -gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x1000>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <5 0 0x2c000000 0x1000000>; - - ethernet@5,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <5 0 0xff>; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on = <0>; - gpmc,cs-rd-off = <186>; - gpmc,cs-wr-off = <186>; - gpmc,adv-on = <12>; - gpmc,adv-rd-off = <48>; - gpmc,adv-wr-off = <48>; - gpmc,oe-on = <54>; - gpmc,oe-off = <168>; - gpmc,we-on = <54>; - gpmc,we-off = <168>; - gpmc,rd-cycle = <186>; - gpmc,wr-cycle = <186>; - gpmc,access = <114>; - gpmc,page-burst-access = <6>; - gpmc,bus-turnaround = <12>; - gpmc,cycle2cycle-delay = <18>; - gpmc,wr-data-mux-bus = <90>; - gpmc,wr-access = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - interrupt-parent = <&gpio6>; - interrupts = <16>; - vmmc-supply = <&vddvario>; - vmmc_aux-supply = <&vdd33a>; - reg-io-width = <4>; - - smsc,save-mac-address; - }; -}; diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt b/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt deleted file mode 100644 index b3aa90f0ce44..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt +++ /dev/null @@ -1,57 +0,0 @@ -VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller - -These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as -either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc). - -Required properties: -- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl", - "wm8750-pinctrl" or "wm,wm8850-pinctrl" -- reg: Should contain the physical address of the module's registers. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters. - bit 0 - active low - -Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Each pin configuration node lists the pin(s) to which it applies, and one or -more of the mux functions to select on those pin(s), and pull-up/down -configuration. Each subnode only affects those parameters that are explicitly -listed. In other words, a subnode that lists only a mux function implies no -information about any pull configuration. Similarly, a subnode that lists only -a pull parameter implies no information about the mux function. - -Required subnode-properties: -- wm,pins: An array of cells. Each cell contains the ID of a pin. - -Optional subnode-properties: -- wm,function: Integer, containing the function to mux to the pin(s): - 0: GPIO in - 1: GPIO out - 2: alternate - -- wm,pull: Integer, representing the pull-down/up to apply to the pin(s): - 0: none - 1: down - 2: up - -Each of wm,function and wm,pull may contain either a single value which -will be applied to all pins in wm,pins, or one value for each entry in -wm,pins. - -Example: - - pinctrl: pinctrl { - compatible = "wm,wm8505-pinctrl"; - reg = <0xD8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/trunk/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/trunk/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt deleted file mode 100644 index 993695c659e1..000000000000 --- a/trunk/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt +++ /dev/null @@ -1,17 +0,0 @@ -Cadence TTC - Triple Timer Counter - -Required properties: -- compatible : Should be "cdns,ttc". -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 3 interrupts; one per timer channel. -- clocks: phandle to the source clock - -Example: - -ttc0: ttc0@f8001000 { - interrupt-parent = <&intc>; - interrupts = < 0 10 4 0 11 4 0 12 4 >; - compatible = "cdns,ttc"; - reg = <0xF8001000 0x1000>; - clocks = <&cpu_clk 3>; -}; diff --git a/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt deleted file mode 100644 index cb47bfbcaeea..000000000000 --- a/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt +++ /dev/null @@ -1,68 +0,0 @@ -Samsung's Multi Core Timer (MCT) - -The Samsung's Multi Core Timer (MCT) module includes two main blocks, the -global timer and CPU local timers. The global timer is a 64-bit free running -up-counter and can generate 4 interrupts when the counter reaches one of the -four preset counter values. The CPU local timers are 32-bit free running -down-counters and generate an interrupt when the counter expires. There is -one CPU local timer instantiated in MCT for every CPU in the system. - -Required properties: - -- compatible: should be "samsung,exynos4210-mct". - (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct. - (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct. - -- reg: base address of the mct controller and length of the address space - it occupies. - -- interrupts: the list of interrupts generated by the controller. The following - should be the order of the interrupts specified. The local timer interrupts - should be specified after the four global timer interrupts have been - specified. - - 0: Global Timer Interrupt 0 - 1: Global Timer Interrupt 1 - 2: Global Timer Interrupt 2 - 3: Global Timer Interrupt 3 - 4: Local Timer Interrupt 0 - 5: Local Timer Interrupt 1 - 6: .. - 7: .. - i: Local Timer Interrupt n - -Example 1: In this example, the system uses only the first global timer - interrupt generated by MCT and the remaining three global timer - interrupts are unused. Two local timer interrupts have been - specified. - - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>, - <0 42 0>, <0 48 0>; - }; - -Example 2: In this example, the MCT global and local timer interrupts are - connected to two seperate interrupt controllers. Hence, an - interrupt-map is created to map the interrupts to the respective - interrupt controllers. - - mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &combiner 23 3>, - <0x4 0 &gic 0 120 0>, - <0x5 0 &gic 0 121 0>; - }; - }; diff --git a/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt index 8f01cb190f25..1e1145ca4f3c 100644 --- a/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt +++ b/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt @@ -11,9 +11,6 @@ Required properties: - "nvidia,tegra20-uart" - "nxp,lpc3220-uart" - "ibm,qpace-nwp-serial" - - "altr,16550-FIFO32" - - "altr,16550-FIFO64" - - "altr,16550-FIFO128" - "serial" if the port type is unknown. - reg : offset and length of the register set for the device. - interrupts : should contain uart interrupt. diff --git a/trunk/Documentation/hwmon/adm1275 b/trunk/Documentation/hwmon/adm1275 index 15b4a20d5062..2cfa25667123 100644 --- a/trunk/Documentation/hwmon/adm1275 +++ b/trunk/Documentation/hwmon/adm1275 @@ -15,7 +15,7 @@ Supported chips: Addresses scanned: - Datasheet: www.analog.com/static/imported-files/data_sheets/ADM1276.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/adt7410 b/trunk/Documentation/hwmon/adt7410 index 58150c480e56..96004000dc2a 100644 --- a/trunk/Documentation/hwmon/adt7410 +++ b/trunk/Documentation/hwmon/adt7410 @@ -4,14 +4,9 @@ Kernel driver adt7410 Supported chips: * Analog Devices ADT7410 Prefix: 'adt7410' - Addresses scanned: None + Addresses scanned: I2C 0x48 - 0x4B Datasheet: Publicly available at the Analog Devices website http://www.analog.com/static/imported-files/data_sheets/ADT7410.pdf - * Analog Devices ADT7420 - Prefix: 'adt7420' - Addresses scanned: None - Datasheet: Publicly available at the Analog Devices website - http://www.analog.com/static/imported-files/data_sheets/ADT7420.pdf Author: Hartmut Knaack @@ -32,10 +27,6 @@ value per second or even justget one sample on demand for power saving. Besides, it can completely power down its ADC, if power management is required. -The ADT7420 is register compatible, the only differences being the package, -a slightly narrower operating temperature range (-40°C to +150°C), and a -better accuracy (0.25°C instead of 0.50°C.) - Configuration Notes ------------------- diff --git a/trunk/Documentation/hwmon/jc42 b/trunk/Documentation/hwmon/jc42 index 868d74d6b773..165077121238 100644 --- a/trunk/Documentation/hwmon/jc42 +++ b/trunk/Documentation/hwmon/jc42 @@ -49,7 +49,7 @@ Supported chips: Addresses scanned: I2C 0x18 - 0x1f Author: - Guenter Roeck + Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/lineage-pem b/trunk/Documentation/hwmon/lineage-pem index 83b2ddc160c8..2ba5ed126858 100644 --- a/trunk/Documentation/hwmon/lineage-pem +++ b/trunk/Documentation/hwmon/lineage-pem @@ -8,7 +8,7 @@ Supported devices: Documentation: http://www.lineagepower.com/oem/pdf/CPLI2C.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/lm25066 b/trunk/Documentation/hwmon/lm25066 index 26025e419d35..a21db81c4591 100644 --- a/trunk/Documentation/hwmon/lm25066 +++ b/trunk/Documentation/hwmon/lm25066 @@ -19,7 +19,7 @@ Supported chips: Datasheet: http://www.national.com/pf/LM/LM5066.html -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/lm75 b/trunk/Documentation/hwmon/lm75 index 69af1c7db6b7..c91a1d15fa28 100644 --- a/trunk/Documentation/hwmon/lm75 +++ b/trunk/Documentation/hwmon/lm75 @@ -23,7 +23,7 @@ Supported chips: Datasheet: Publicly available at the Maxim website http://www.maxim-ic.com/ * Microchip (TelCom) TCN75 - Prefix: 'tcn75' + Prefix: 'lm75' Addresses scanned: none Datasheet: Publicly available at the Microchip website http://www.microchip.com/ diff --git a/trunk/Documentation/hwmon/ltc2978 b/trunk/Documentation/hwmon/ltc2978 index e4d75c606c97..c365f9beb5dd 100644 --- a/trunk/Documentation/hwmon/ltc2978 +++ b/trunk/Documentation/hwmon/ltc2978 @@ -5,13 +5,13 @@ Supported chips: * Linear Technology LTC2978 Prefix: 'ltc2978' Addresses scanned: - - Datasheet: http://www.linear.com/product/ltc2978 + Datasheet: http://cds.linear.com/docs/Datasheet/2978fa.pdf * Linear Technology LTC3880 Prefix: 'ltc3880' Addresses scanned: - - Datasheet: http://www.linear.com/product/ltc3880 + Datasheet: http://cds.linear.com/docs/Datasheet/3880f.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/ltc4261 b/trunk/Documentation/hwmon/ltc4261 index 9378a75c6134..eba2e2c4b94d 100644 --- a/trunk/Documentation/hwmon/ltc4261 +++ b/trunk/Documentation/hwmon/ltc4261 @@ -8,7 +8,7 @@ Supported chips: Datasheet: http://cds.linear.com/docs/Datasheet/42612fb.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/max16064 b/trunk/Documentation/hwmon/max16064 index d59cc7829bec..f8b478076f6d 100644 --- a/trunk/Documentation/hwmon/max16064 +++ b/trunk/Documentation/hwmon/max16064 @@ -7,7 +7,7 @@ Supported chips: Addresses scanned: - Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX16064.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/max16065 b/trunk/Documentation/hwmon/max16065 index 208a29e43010..c11f64a1f2ad 100644 --- a/trunk/Documentation/hwmon/max16065 +++ b/trunk/Documentation/hwmon/max16065 @@ -24,7 +24,7 @@ Supported chips: http://datasheets.maxim-ic.com/en/ds/MAX16070-MAX16071.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/max34440 b/trunk/Documentation/hwmon/max34440 index 37cbf472a19d..47651ff341ae 100644 --- a/trunk/Documentation/hwmon/max34440 +++ b/trunk/Documentation/hwmon/max34440 @@ -27,7 +27,7 @@ Supported chips: Addresses scanned: - Datasheet: http://datasheets.maximintegrated.com/en/ds/MAX34461.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/max8688 b/trunk/Documentation/hwmon/max8688 index e78078638b91..fe849871df32 100644 --- a/trunk/Documentation/hwmon/max8688 +++ b/trunk/Documentation/hwmon/max8688 @@ -7,7 +7,7 @@ Supported chips: Addresses scanned: - Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX8688.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/pmbus b/trunk/Documentation/hwmon/pmbus index cf756ed48ff9..3d3a0f97f966 100644 --- a/trunk/Documentation/hwmon/pmbus +++ b/trunk/Documentation/hwmon/pmbus @@ -34,7 +34,7 @@ Supported chips: Addresses scanned: - Datasheet: n.a. -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/smm665 b/trunk/Documentation/hwmon/smm665 index a341eeedab75..59e316140542 100644 --- a/trunk/Documentation/hwmon/smm665 +++ b/trunk/Documentation/hwmon/smm665 @@ -29,7 +29,7 @@ Supported chips: http://www.summitmicro.com/prod_select/summary/SMM766/SMM766_2086.pdf http://www.summitmicro.com/prod_select/summary/SMM766B/SMM766B_2122.pdf -Author: Guenter Roeck +Author: Guenter Roeck Module Parameters diff --git a/trunk/Documentation/hwmon/ucd9000 b/trunk/Documentation/hwmon/ucd9000 index 805e33edb978..0df5f276505b 100644 --- a/trunk/Documentation/hwmon/ucd9000 +++ b/trunk/Documentation/hwmon/ucd9000 @@ -11,7 +11,7 @@ Supported chips: http://focus.ti.com/lit/ds/symlink/ucd9090.pdf http://focus.ti.com/lit/ds/symlink/ucd90910.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/ucd9200 b/trunk/Documentation/hwmon/ucd9200 index 1e8060e631bd..fd7d07b1908a 100644 --- a/trunk/Documentation/hwmon/ucd9200 +++ b/trunk/Documentation/hwmon/ucd9200 @@ -15,7 +15,7 @@ Supported chips: http://focus.ti.com/lit/ds/symlink/ucd9246.pdf http://focus.ti.com/lit/ds/symlink/ucd9248.pdf -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/hwmon/zl6100 b/trunk/Documentation/hwmon/zl6100 index 756b57c6b73e..3d924b6b59e9 100644 --- a/trunk/Documentation/hwmon/zl6100 +++ b/trunk/Documentation/hwmon/zl6100 @@ -54,7 +54,7 @@ http://archive.ericsson.net/service/internet/picov/get?DocNo=28701-EN/LZT146401 http://archive.ericsson.net/service/internet/picov/get?DocNo=28701-EN/LZT146256 -Author: Guenter Roeck +Author: Guenter Roeck Description diff --git a/trunk/Documentation/i2c/busses/i2c-diolan-u2c b/trunk/Documentation/i2c/busses/i2c-diolan-u2c index 0d6018c316c7..30fe4bb9a069 100644 --- a/trunk/Documentation/i2c/busses/i2c-diolan-u2c +++ b/trunk/Documentation/i2c/busses/i2c-diolan-u2c @@ -5,7 +5,7 @@ Supported adapters: Documentation: http://www.diolan.com/i2c/u2c12.html -Author: Guenter Roeck +Author: Guenter Roeck Description ----------- diff --git a/trunk/Documentation/input/alps.txt b/trunk/Documentation/input/alps.txt index e544c7ff8cfa..3262b6e4d686 100644 --- a/trunk/Documentation/input/alps.txt +++ b/trunk/Documentation/input/alps.txt @@ -3,26 +3,10 @@ ALPS Touchpad Protocol Introduction ------------ -Currently the ALPS touchpad driver supports five protocol versions in use by -ALPS touchpads, called versions 1, 2, 3, 4 and 5. - -Since roughly mid-2010 several new ALPS touchpads have been released and -integrated into a variety of laptops and netbooks. These new touchpads -have enough behavior differences that the alps_model_data definition -table, describing the properties of the different versions, is no longer -adequate. The design choices were to re-define the alps_model_data -table, with the risk of regression testing existing devices, or isolate -the new devices outside of the alps_model_data table. The latter design -choice was made. The new touchpad signatures are named: "Rushmore", -"Pinnacle", and "Dolphin", which you will see in the alps.c code. -For the purposes of this document, this group of ALPS touchpads will -generically be called "new ALPS touchpads". - -We experimented with probing the ACPI interface _HID (Hardware ID)/_CID -(Compatibility ID) definition as a way to uniquely identify the -different ALPS variants but there did not appear to be a 1:1 mapping. -In fact, it appeared to be an m:n mapping between the _HID and actual -hardware type. + +Currently the ALPS touchpad driver supports four protocol versions in use by +ALPS touchpads, called versions 1, 2, 3, and 4. Information about the various +protocol versions is contained in the following sections. Detection --------- @@ -36,13 +20,9 @@ If the E6 report is successful, the touchpad model is identified using the "E7 report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is matched against known models in the alps_model_data_array. -For older touchpads supporting protocol versions 3 and 4, the E7 report -model signature is always 73-02-64. To differentiate between these -versions, the response from the "Enter Command Mode" sequence must be -inspected as described below. - -The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but -seem to be better differentiated by the EC Command Mode response. +With protocol versions 3 and 4, the E7 report model signature is always +73-02-64. To differentiate between these versions, the response from the +"Enter Command Mode" sequence must be inspected as described below. Command Mode ------------ @@ -67,14 +47,6 @@ address of the register being read, and the third contains the value of the register. Registers are written by writing the value one nibble at a time using the same encoding used for addresses. -For the new ALPS touchpads, the EC command is used to enter command -mode. The response in the new ALPS touchpads is significantly different, -and more important in determining the behavior. This code has been -separated from the original alps_model_data table and put in the -alps_identify function. For example, there seem to be two hardware init -sequences for the "Dolphin" touchpads as determined by the second byte -of the EC response. - Packet Format ------------- @@ -215,28 +187,3 @@ There are several things worth noting here. well. So far no v4 devices with tracksticks have been encountered. - -ALPS Absolute Mode - Protocol Version 5 ---------------------------------------- -This is basically Protocol Version 3 but with different logic for packet -decode. It uses the same alps_process_touchpad_packet_v3 call with a -specialized decode_fields function pointer to correctly interpret the -packets. This appears to only be used by the Dolphin devices. - -For single-touch, the 6-byte packet format is: - - byte 0: 1 1 0 0 1 0 0 0 - byte 1: 0 x6 x5 x4 x3 x2 x1 x0 - byte 2: 0 y6 y5 y4 y3 y2 y1 y0 - byte 3: 0 M R L 1 m r l - byte 4: y10 y9 y8 y7 x10 x9 x8 x7 - byte 5: 0 z6 z5 z4 z3 z2 z1 z0 - -For mt, the format is: - - byte 0: 1 1 1 n3 1 n2 n1 x24 - byte 1: 1 y7 y6 y5 y4 y3 y2 y1 - byte 2: ? x2 x1 y12 y11 y10 y9 y8 - byte 3: 0 x23 x22 x21 x20 x19 x18 x17 - byte 4: 0 x9 x8 x7 x6 x5 x4 x3 - byte 5: 0 x16 x15 x14 x13 x12 x11 x10 diff --git a/trunk/Documentation/networking/ipvs-sysctl.txt b/trunk/Documentation/networking/ipvs-sysctl.txt index 9573d0c48c6e..f2a2488f1bf3 100644 --- a/trunk/Documentation/networking/ipvs-sysctl.txt +++ b/trunk/Documentation/networking/ipvs-sysctl.txt @@ -15,13 +15,6 @@ amemthresh - INTEGER enabled and the variable is automatically set to 2, otherwise the strategy is disabled and the variable is set to 1. -backup_only - BOOLEAN - 0 - disabled (default) - not 0 - enabled - - If set, disable the director function while the server is - in backup mode to avoid packet loops for DR/TUN methods. - conntrack - BOOLEAN 0 - disabled (default) not 0 - enabled diff --git a/trunk/Documentation/networking/tuntap.txt b/trunk/Documentation/networking/tuntap.txt index 949d5dcdd9a3..c0aab985bad9 100644 --- a/trunk/Documentation/networking/tuntap.txt +++ b/trunk/Documentation/networking/tuntap.txt @@ -105,83 +105,6 @@ Copyright (C) 1999-2000 Maxim Krasnyansky Proto [2 bytes] Raw protocol(IP, IPv6, etc) frame. - 3.3 Multiqueue tuntap interface: - - From version 3.8, Linux supports multiqueue tuntap which can uses multiple - file descriptors (queues) to parallelize packets sending or receiving. The - device allocation is the same as before, and if user wants to create multiple - queues, TUNSETIFF with the same device name must be called many times with - IFF_MULTI_QUEUE flag. - - char *dev should be the name of the device, queues is the number of queues to - be created, fds is used to store and return the file descriptors (queues) - created to the caller. Each file descriptor were served as the interface of a - queue which could be accessed by userspace. - - #include - #include - - int tun_alloc_mq(char *dev, int queues, int *fds) - { - struct ifreq ifr; - int fd, err, i; - - if (!dev) - return -1; - - memset(&ifr, 0, sizeof(ifr)); - /* Flags: IFF_TUN - TUN device (no Ethernet headers) - * IFF_TAP - TAP device - * - * IFF_NO_PI - Do not provide packet information - * IFF_MULTI_QUEUE - Create a queue of multiqueue device - */ - ifr.ifr_flags = IFF_TAP | IFF_NO_PI | IFF_MULTI_QUEUE; - strcpy(ifr.ifr_name, dev); - - for (i = 0; i < queues; i++) { - if ((fd = open("/dev/net/tun", O_RDWR)) < 0) - goto err; - err = ioctl(fd, TUNSETIFF, (void *)&ifr); - if (err) { - close(fd); - goto err; - } - fds[i] = fd; - } - - return 0; - err: - for (--i; i >= 0; i--) - close(fds[i]); - return err; - } - - A new ioctl(TUNSETQUEUE) were introduced to enable or disable a queue. When - calling it with IFF_DETACH_QUEUE flag, the queue were disabled. And when - calling it with IFF_ATTACH_QUEUE flag, the queue were enabled. The queue were - enabled by default after it was created through TUNSETIFF. - - fd is the file descriptor (queue) that we want to enable or disable, when - enable is true we enable it, otherwise we disable it - - #include - #include - - int tun_set_queue(int fd, int enable) - { - struct ifreq ifr; - - memset(&ifr, 0, sizeof(ifr)); - - if (enable) - ifr.ifr_flags = IFF_ATTACH_QUEUE; - else - ifr.ifr_flags = IFF_DETACH_QUEUE; - - return ioctl(fd, TUNSETQUEUE, (void *)&ifr); - } - Universal TUN/TAP device driver Frequently Asked Question. 1. What platforms are supported by TUN/TAP driver ? diff --git a/trunk/Documentation/power/opp.txt b/trunk/Documentation/power/opp.txt index 425c51d56aef..3035d00757ad 100644 --- a/trunk/Documentation/power/opp.txt +++ b/trunk/Documentation/power/opp.txt @@ -1,5 +1,6 @@ -Operating Performance Points (OPP) Library -========================================== +*=============* +* OPP Library * +*=============* (C) 2009-2010 Nishanth Menon , Texas Instruments Incorporated @@ -15,31 +16,15 @@ Contents 1. Introduction =============== -1.1 What is an Operating Performance Point (OPP)? - Complex SoCs of today consists of a multiple sub-modules working in conjunction. In an operational system executing varied use cases, not all modules in the SoC need to function at their highest performing frequency all the time. To facilitate this, sub-modules in a SoC are grouped into domains, allowing some -domains to run at lower voltage and frequency while other domains run at -voltage/frequency pairs that are higher. - -The set of discrete tuples consisting of frequency and voltage pairs that +domains to run at lower voltage and frequency while other domains are loaded +more. The set of discrete tuples consisting of frequency and voltage pairs that the device will support per domain are called Operating Performance Points or OPPs. -As an example: -Let us consider an MPU device which supports the following: -{300MHz at minimum voltage of 1V}, {800MHz at minimum voltage of 1.2V}, -{1GHz at minimum voltage of 1.3V} - -We can represent these as three OPPs as the following {Hz, uV} tuples: -{300000000, 1000000} -{800000000, 1200000} -{1000000000, 1300000} - -1.2 Operating Performance Points Library - OPP library provides a set of helper functions to organize and query the OPP information. The library is located in drivers/base/power/opp.c and the header is located in include/linux/opp.h. OPP library can be enabled by enabling diff --git a/trunk/Documentation/printk-formats.txt b/trunk/Documentation/printk-formats.txt index 6e953564de03..e8a6aa473bab 100644 --- a/trunk/Documentation/printk-formats.txt +++ b/trunk/Documentation/printk-formats.txt @@ -170,5 +170,5 @@ Reminder: sizeof() result is of type size_t. Thank you for your cooperation and attention. -By Randy Dunlap and +By Randy Dunlap and Andrew Murray diff --git a/trunk/Documentation/sound/alsa/ALSA-Configuration.txt b/trunk/Documentation/sound/alsa/ALSA-Configuration.txt index 4499bd948860..ce6581c8ca26 100644 --- a/trunk/Documentation/sound/alsa/ALSA-Configuration.txt +++ b/trunk/Documentation/sound/alsa/ALSA-Configuration.txt @@ -912,7 +912,7 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed. models depending on the codec chip. The list of available models is found in HD-Audio-Models.txt - The model name "generic" is treated as a special case. When this + The model name "genric" is treated as a special case. When this model is given, the driver uses the generic codec parser without "codec-patch". It's sometimes good for testing and debugging. diff --git a/trunk/Documentation/sound/alsa/seq_oss.html b/trunk/Documentation/sound/alsa/seq_oss.html index 9663b45f6fde..d9776cf60c07 100644 --- a/trunk/Documentation/sound/alsa/seq_oss.html +++ b/trunk/Documentation/sound/alsa/seq_oss.html @@ -285,7 +285,7 @@

7.2.4 Close Callback

The close callback is called when this device is closed by the -application. If any private data was allocated in open callback, it must +applicaion. If any private data was allocated in open callback, it must be released in the close callback. The deletion of ALSA port should be done here, too. This callback must not be NULL.

diff --git a/trunk/Documentation/trace/ftrace.txt b/trunk/Documentation/trace/ftrace.txt index a372304aef10..53d6a3c51d87 100644 --- a/trunk/Documentation/trace/ftrace.txt +++ b/trunk/Documentation/trace/ftrace.txt @@ -1873,7 +1873,7 @@ feature: status\input | 0 | 1 | else | --------------+------------+------------+------------+ - not allocated |(do nothing)| alloc+swap |(do nothing)| + not allocated |(do nothing)| alloc+swap | EINVAL | --------------+------------+------------+------------+ allocated | free | swap | clear | --------------+------------+------------+------------+ diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 74e58a4d035b..e95b1e944eb7 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -114,6 +114,12 @@ Maintainers List (try to look for most precise areas first) ----------------------------------- +3C505 NETWORK DRIVER +M: Philip Blundell +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/i825xx/3c505* + 3C59X NETWORK DRIVER M: Steffen Klassert L: netdev@vger.kernel.org @@ -1338,6 +1344,12 @@ S: Maintained F: drivers/platform/x86/asus*.c F: drivers/platform/x86/eeepc*.c +ASUS ASB100 HARDWARE MONITOR DRIVER +M: "Mark M. Hoffman" +L: lm-sensors@lm-sensors.org +S: Maintained +F: drivers/hwmon/asb100.c + ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API M: Dan Williams W: http://sourceforge.net/projects/xscaleiop @@ -1461,12 +1473,6 @@ F: drivers/dma/at_hdmac.c F: drivers/dma/at_hdmac_regs.h F: include/linux/platform_data/dma-atmel.h -ATMEL I2C DRIVER -M: Ludovic Desroches -L: linux-i2c@vger.kernel.org -S: Supported -F: drivers/i2c/busses/i2c-at91.c - ATMEL ISI DRIVER M: Josh Wu L: linux-media@vger.kernel.org @@ -2355,6 +2361,12 @@ W: http://www.arm.linux.org.uk/ S: Maintained F: drivers/video/cyber2000fb.* +CYCLADES 2X SYNC CARD DRIVER +M: Arnaldo Carvalho de Melo +W: http://oops.ghostprotocols.net:81/blog +S: Maintained +F: drivers/net/wan/cycx* + CYCLADES ASYNC MUX DRIVER W: http://www.cyclades.com/ S: Orphan @@ -2629,7 +2641,7 @@ F: include/uapi/drm/ INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) M: Daniel Vetter -L: intel-gfx@lists.freedesktop.org +L: intel-gfx@lists.freedesktop.org (subscribers-only) L: dri-devel@lists.freedesktop.org T: git git://people.freedesktop.org/~danvet/drm-intel S: Supported @@ -3055,6 +3067,12 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/kristoffer/linux-hpc.git F: drivers/video/s1d13xxxfb.c F: include/video/s1d13xxxfb.h +ETHEREXPRESS-16 NETWORK DRIVER +M: Philip Blundell +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/i825xx/eexpress.* + ETHERNET BRIDGE M: Stephen Hemminger L: bridge@lists.linux-foundation.org @@ -3242,12 +3260,6 @@ F: Documentation/firmware_class/ F: drivers/base/firmware*.c F: include/linux/firmware.h -FLASHSYSTEM DRIVER (IBM FlashSystem 70/80 PCI SSD Flash Card) -M: Joshua Morris -M: Philip Kelleher -S: Maintained -F: drivers/block/rsxx/ - FLOPPY DRIVER M: Jiri Kosina T: git git://git.kernel.org/pub/scm/linux/kernel/git/jikos/floppy.git @@ -3857,7 +3869,7 @@ F: drivers/i2c/busses/i2c-ismt.c F: Documentation/i2c/busses/i2c-ismt I2C/SMBUS STUB DRIVER -M: Jean Delvare +M: "Mark M. Hoffman" L: linux-i2c@vger.kernel.org S: Maintained F: drivers/i2c/i2c-stub.c @@ -4011,22 +4023,6 @@ M: Stanislaw Gruszka S: Maintained F: drivers/usb/atm/ueagle-atm.c -INA209 HARDWARE MONITOR DRIVER -M: Guenter Roeck -L: lm-sensors@lm-sensors.org -S: Maintained -F: Documentation/hwmon/ina209 -F: Documentation/devicetree/bindings/i2c/ina209.txt -F: drivers/hwmon/ina209.c - -INA2XX HARDWARE MONITOR DRIVER -M: Guenter Roeck -L: lm-sensors@lm-sensors.org -S: Maintained -F: Documentation/hwmon/ina2xx -F: drivers/hwmon/ina2xx.c -F: include/linux/platform_data/ina2xx.h - INDUSTRY PACK SUBSYSTEM (IPACK) M: Samuel Iglesias Gonsalvez M: Jens Taprogge @@ -5120,15 +5116,6 @@ S: Maintained F: Documentation/hwmon/max6650 F: drivers/hwmon/max6650.c -MAX6697 HARDWARE MONITOR DRIVER -M: Guenter Roeck -L: lm-sensors@lm-sensors.org -S: Maintained -F: Documentation/hwmon/max6697 -F: Documentation/devicetree/bindings/i2c/max6697.txt -F: drivers/hwmon/max6697.c -F: include/linux/platform_data/max6697.h - MAXIRADIO FM RADIO RECEIVER DRIVER M: Hans Verkuil L: linux-media@vger.kernel.org @@ -5653,14 +5640,6 @@ S: Maintained F: drivers/video/riva/ F: drivers/video/nvidia/ -NVM EXPRESS DRIVER -M: Matthew Wilcox -L: linux-nvme@lists.infradead.org -T: git git://git.infradead.org/users/willy/linux-nvme.git -S: Supported -F: drivers/block/nvme.c -F: include/linux/nvme.h - OMAP SUPPORT M: Tony Lindgren L: linux-omap@vger.kernel.org @@ -5689,7 +5668,7 @@ S: Maintained F: arch/arm/*omap*/*clock* OMAP POWER MANAGEMENT SUPPORT -M: Kevin Hilman +M: Kevin Hilman L: linux-omap@vger.kernel.org S: Maintained F: arch/arm/*omap*/*pm* @@ -5783,7 +5762,7 @@ F: arch/arm/*omap*/usb* OMAP GPIO DRIVER M: Santosh Shilimkar -M: Kevin Hilman +M: Kevin Hilman L: linux-omap@vger.kernel.org S: Maintained F: drivers/gpio/gpio-omap.c @@ -6215,7 +6194,7 @@ F: include/linux/power_supply.h F: drivers/power/ PNP SUPPORT -M: Rafael J. Wysocki +M: Adam Belay M: Bjorn Helgaas S: Maintained F: drivers/pnp/ @@ -6451,8 +6430,6 @@ F: Documentation/networking/LICENSE.qla3xxx F: drivers/net/ethernet/qlogic/qla3xxx.* QLOGIC QLCNIC (1/10)Gb ETHERNET DRIVER -M: Rajesh Borundia -M: Shahed Shaikh M: Jitendra Kalsaria M: Sony Chacko M: linux-driver@qlogic.com @@ -6557,6 +6534,12 @@ S: Maintained F: Documentation/blockdev/ramdisk.txt F: drivers/block/brd.c +RAMSAM DRIVER (IBM RamSan 70/80 PCI SSD Flash Card) +M: Joshua Morris +M: Philip Kelleher +S: Maintained +F: drivers/block/rsxx/ + RANDOM NUMBER DRIVER M: Theodore Ts'o" S: Maintained @@ -7173,7 +7156,7 @@ F: arch/arm/mach-s3c2410/bast-irq.c TI DAVINCI MACHINE SUPPORT M: Sekhar Nori -M: Kevin Hilman +M: Kevin Hilman L: davinci-linux-open-source@linux.davincidsp.com (moderated for non-subscribers) T: git git://gitorious.org/linux-davinci/linux-davinci.git Q: http://patchwork.kernel.org/project/linux-davinci/list/ @@ -7206,6 +7189,13 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/sis/sis900.* +SIS 96X I2C/SMBUS DRIVER +M: "Mark M. Hoffman" +L: linux-i2c@vger.kernel.org +S: Maintained +F: Documentation/i2c/busses/i2c-sis96x +F: drivers/i2c/busses/i2c-sis96x.c + SIS FRAMEBUFFER DRIVER M: Thomas Winischhofer W: http://www.winischhofer.net/linuxsisvga.shtml @@ -7283,7 +7273,7 @@ F: Documentation/hwmon/sch5627 F: drivers/hwmon/sch5627.c SMSC47B397 HARDWARE MONITOR DRIVER -M: Jean Delvare +M: "Mark M. Hoffman" L: lm-sensors@lm-sensors.org S: Maintained F: Documentation/hwmon/smsc47b397 @@ -7706,10 +7696,9 @@ F: include/linux/swiotlb.h SYNOPSYS ARC ARCHITECTURE M: Vineet Gupta +L: linux-snps-arc@vger.kernel.org S: Supported F: arch/arc/ -F: Documentation/devicetree/bindings/arc/ -F: drivers/tty/serial/arc-uart.c SYSV FILESYSTEM M: Christoph Hellwig diff --git a/trunk/Makefile b/trunk/Makefile index 58a165b02af1..5bd9f7700eb9 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 9 SUBLEVEL = 0 -EXTRAVERSION = -rc5 +EXTRAVERSION = -rc1 NAME = Unicycling Gorilla # *DOCUMENTATION* diff --git a/trunk/arch/Kconfig b/trunk/arch/Kconfig index 1455579791ec..5a1779c93940 100644 --- a/trunk/arch/Kconfig +++ b/trunk/arch/Kconfig @@ -319,6 +319,13 @@ config ARCH_WANT_OLD_COMPAT_IPC select ARCH_WANT_COMPAT_IPC_PARSE_VERSION bool +config HAVE_VIRT_TO_BUS + bool + help + An architecture should select this if it implements the + deprecated interface virt_to_bus(). All new architectures + should probably not select this. + config HAVE_ARCH_SECCOMP_FILTER bool help diff --git a/trunk/arch/alpha/Kconfig b/trunk/arch/alpha/Kconfig index 8a33ba01301f..5833aa441481 100644 --- a/trunk/arch/alpha/Kconfig +++ b/trunk/arch/alpha/Kconfig @@ -9,7 +9,7 @@ config ALPHA select HAVE_PERF_EVENTS select HAVE_DMA_ATTRS select HAVE_GENERIC_HARDIRQS - select VIRT_TO_BUS + select HAVE_VIRT_TO_BUS select GENERIC_IRQ_PROBE select AUTO_IRQ_AFFINITY if SMP select GENERIC_IRQ_SHOW diff --git a/trunk/arch/alpha/boot/head.S b/trunk/arch/alpha/boot/head.S index 8efb26686d47..b06812bcac83 100644 --- a/trunk/arch/alpha/boot/head.S +++ b/trunk/arch/alpha/boot/head.S @@ -4,7 +4,6 @@ * initial bootloader stuff.. */ -#include .set noreorder .globl __start diff --git a/trunk/arch/arc/include/asm/dma-mapping.h b/trunk/arch/arc/include/asm/dma-mapping.h index 45b8e0cea176..31f77aec0823 100644 --- a/trunk/arch/arc/include/asm/dma-mapping.h +++ b/trunk/arch/arc/include/asm/dma-mapping.h @@ -126,7 +126,7 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int i; for_each_sg(sg, s, nents, i) - s->dma_address = dma_map_page(dev, sg_page(s), s->offset, + sg->dma_address = dma_map_page(dev, sg_page(s), s->offset, s->length, dir); return nents; diff --git a/trunk/arch/arc/include/asm/elf.h b/trunk/arch/arc/include/asm/elf.h index a26282857683..f4c8d36ebecb 100644 --- a/trunk/arch/arc/include/asm/elf.h +++ b/trunk/arch/arc/include/asm/elf.h @@ -72,4 +72,7 @@ extern int elf_check_arch(const struct elf32_hdr *); */ #define ELF_PLATFORM (NULL) +#define SET_PERSONALITY(ex) \ + set_personality(PER_LINUX | (current->personality & (~PER_MASK))) + #endif diff --git a/trunk/arch/arc/include/asm/entry.h b/trunk/arch/arc/include/asm/entry.h index eb2ae53187d9..23daa326fc9b 100644 --- a/trunk/arch/arc/include/asm/entry.h +++ b/trunk/arch/arc/include/asm/entry.h @@ -415,7 +415,7 @@ *-------------------------------------------------------------*/ .macro SAVE_ALL_EXCEPTION marker - st \marker, [sp, 8] /* orig_r8 */ + st \marker, [sp, 8] st r0, [sp, 4] /* orig_r0, needed only for sys calls */ /* Restore r9 used to code the early prologue */ diff --git a/trunk/arch/arc/include/asm/kgdb.h b/trunk/arch/arc/include/asm/kgdb.h index 4930957ca3d3..f3c4934f0ca9 100644 --- a/trunk/arch/arc/include/asm/kgdb.h +++ b/trunk/arch/arc/include/asm/kgdb.h @@ -13,7 +13,7 @@ #ifdef CONFIG_KGDB -#include +#include /* to ensure compatibility with Linux 2.6.35, we don't implement the get/set * register API yet */ @@ -53,7 +53,9 @@ enum arc700_linux_regnums { }; #else -#define kgdb_trap(regs, param) +static inline void kgdb_trap(struct pt_regs *regs, int param) +{ +} #endif #endif /* __ARC_KGDB_H__ */ diff --git a/trunk/arch/arc/include/asm/ptrace.h b/trunk/arch/arc/include/asm/ptrace.h index 6179de7e07c2..8ae783d20a81 100644 --- a/trunk/arch/arc/include/asm/ptrace.h +++ b/trunk/arch/arc/include/asm/ptrace.h @@ -123,7 +123,7 @@ static inline long regs_return_value(struct pt_regs *regs) #define orig_r8_IS_SCALL 0x0001 #define orig_r8_IS_SCALL_RESTARTED 0x0002 #define orig_r8_IS_BRKPT 0x0004 -#define orig_r8_IS_EXCPN 0x0008 +#define orig_r8_IS_EXCPN 0x0004 #define orig_r8_IS_IRQ1 0x0010 #define orig_r8_IS_IRQ2 0x0020 diff --git a/trunk/arch/arc/include/asm/syscalls.h b/trunk/arch/arc/include/asm/syscalls.h index dd785befe7fd..e53a5340ba4f 100644 --- a/trunk/arch/arc/include/asm/syscalls.h +++ b/trunk/arch/arc/include/asm/syscalls.h @@ -16,6 +16,8 @@ #include int sys_clone_wrapper(int, int, int, int, int); +int sys_fork_wrapper(void); +int sys_vfork_wrapper(void); int sys_cacheflush(uint32_t, uint32_t uint32_t); int sys_arc_settls(void *); int sys_arc_gettls(void); diff --git a/trunk/arch/arc/include/uapi/asm/ptrace.h b/trunk/arch/arc/include/uapi/asm/ptrace.h index 30333cec0fef..6afa4f702075 100644 --- a/trunk/arch/arc/include/uapi/asm/ptrace.h +++ b/trunk/arch/arc/include/uapi/asm/ptrace.h @@ -28,14 +28,14 @@ */ struct user_regs_struct { - struct { + struct scratch { long pad; long bta, lp_start, lp_end, lp_count; long status32, ret, blink, fp, gp; long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0; long sp; } scratch; - struct { + struct callee { long pad; long r25, r24, r23, r22, r21, r20; long r19, r18, r17, r16, r15, r14, r13; diff --git a/trunk/arch/arc/kernel/entry.S b/trunk/arch/arc/kernel/entry.S index 91eeab81f52d..ef6800ba2f03 100644 --- a/trunk/arch/arc/kernel/entry.S +++ b/trunk/arch/arc/kernel/entry.S @@ -452,7 +452,7 @@ tracesys: ; using ERET won't work since next-PC has already committed lr r12, [efa] GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11 - st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address + st r12, [r11, THREAD_FAULT_ADDR] ; PRE Sys Call Ptrace hook mov r0, sp ; pt_regs needed @@ -792,6 +792,31 @@ ARC_EXIT ret_from_fork ;################### Special Sys Call Wrappers ########################## +; TBD: call do_fork directly from here +ARC_ENTRY sys_fork_wrapper + SAVE_CALLEE_SAVED_USER + bl @sys_fork + DISCARD_CALLEE_SAVED_USER + + GET_CURR_THR_INFO_FLAGS r10 + btst r10, TIF_SYSCALL_TRACE + bnz tracesys_exit + + b ret_from_system_call +ARC_EXIT sys_fork_wrapper + +ARC_ENTRY sys_vfork_wrapper + SAVE_CALLEE_SAVED_USER + bl @sys_vfork + DISCARD_CALLEE_SAVED_USER + + GET_CURR_THR_INFO_FLAGS r10 + btst r10, TIF_SYSCALL_TRACE + bnz tracesys_exit + + b ret_from_system_call +ARC_EXIT sys_vfork_wrapper + ARC_ENTRY sys_clone_wrapper SAVE_CALLEE_SAVED_USER bl @sys_clone diff --git a/trunk/arch/arc/kernel/kgdb.c b/trunk/arch/arc/kernel/kgdb.c index 52bdc83c1495..2888ba5be47e 100644 --- a/trunk/arch/arc/kernel/kgdb.c +++ b/trunk/arch/arc/kernel/kgdb.c @@ -9,7 +9,6 @@ */ #include -#include #include #include diff --git a/trunk/arch/arc/kernel/setup.c b/trunk/arch/arc/kernel/setup.c index 2d95ac07df7b..dc0f968dae0a 100644 --- a/trunk/arch/arc/kernel/setup.c +++ b/trunk/arch/arc/kernel/setup.c @@ -232,8 +232,10 @@ char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) n += scnprintf(buf + n, len - n, "\n"); +#ifdef _ASM_GENERIC_UNISTD_H n += scnprintf(buf + n, len - n, - "OS ABI [v3]\t: no-legacy-syscalls\n"); + "OS ABI [v2]\t: asm-generic/{unistd,stat,fcntl}\n"); +#endif return buf; } diff --git a/trunk/arch/arc/kernel/sys.c b/trunk/arch/arc/kernel/sys.c index 9d6c1ca26af6..f6bdd07583f3 100644 --- a/trunk/arch/arc/kernel/sys.c +++ b/trunk/arch/arc/kernel/sys.c @@ -6,6 +6,8 @@ #include #define sys_clone sys_clone_wrapper +#define sys_fork sys_fork_wrapper +#define sys_vfork sys_vfork_wrapper #undef __SYSCALL #define __SYSCALL(nr, call) [nr] = (call), diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 03301cb114ac..5b714695b01b 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -49,6 +49,7 @@ config ARM select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 + select HAVE_VIRT_TO_BUS select KTIME_SCALAR select PERF_USE_VMALLOC select RTC_LIB @@ -555,6 +556,7 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" select ARCH_REQUIRE_GPIOLIB + select COMMON_CLK_DOVE select CPU_V7 select GENERIC_CLOCKEVENTS select MIGHT_HAVE_PCI @@ -673,7 +675,6 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select SOC_BUS select SPARSE_IRQ select USE_OF help @@ -743,7 +744,6 @@ config ARCH_RPC select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select NO_IOPORT - select VIRT_TO_BUS help On the Acorn Risc-PC, Linux can support the internal IDE disk and CD-ROM interface, serial and parallel port, and the floppy drive. @@ -770,15 +770,12 @@ config ARCH_SA1100 config ARCH_S3C24XX bool "Samsung S3C24XX SoCs" select ARCH_HAS_CPUFREQ + select ARCH_USES_GETTIMEOFFSET select CLKDEV_LOOKUP - select CLKSRC_MMIO - select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS - select MULTI_IRQ_HANDLER select NEED_MACH_GPIO_H select NEED_MACH_IO_H help @@ -791,11 +788,10 @@ config ARCH_S3C64XX bool "Samsung S3C64XX" select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB + select ARCH_USES_GETTIMEOFFSET select ARM_VIC select CLKDEV_LOOKUP - select CLKSRC_MMIO select CPU_V6 - select GENERIC_CLOCKEVENTS select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -829,11 +825,9 @@ config ARCH_S5P64X0 config ARCH_S5PC100 bool "Samsung S5PC100" + select ARCH_USES_GETTIMEOFFSET select CLKDEV_LOOKUP - select CLKSRC_MMIO select CPU_V7 - select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -885,7 +879,6 @@ config ARCH_SHARK select ISA_DMA select NEED_MACH_MEMORY_H select PCI - select VIRT_TO_BUS select ZONE_DMA help Support for the StrongARM based Digital DNARD machine, also known @@ -1013,12 +1006,12 @@ config ARCH_MULTI_V4_V5 bool config ARCH_MULTI_V6 - bool "ARMv6 based platforms (ARM11)" + bool "ARMv6 based platforms (ARM11, Scorpion, ...)" select ARCH_MULTI_V6_V7 select CPU_V6 config ARCH_MULTI_V7 - bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" + bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)" default y select ARCH_MULTI_V6_V7 select ARCH_VEXPRESS @@ -1469,6 +1462,10 @@ config ISA_DMA bool select ISA_DMA_API +config ARCH_NO_VIRT_TO_BUS + def_bool y + depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK + # Select ISA DMA interface config ISA_DMA_API bool @@ -1600,7 +1597,6 @@ config HAVE_ARM_ARCH_TIMER config HAVE_ARM_TWD bool depends on SMP - select CLKSRC_OF if OF help This options enables support for the ARM timer and watchdog unit @@ -1654,24 +1650,20 @@ config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP default y - select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT) + select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system accounting to be spread across the timer interval, preventing a "thundering herd" at every timer tick. -# The GPIO number here must be sorted by descending number. In case of -# a multiplatform kernel, we just want the highest value required by the -# selected platforms. config ARCH_NR_GPIO int default 1024 if ARCH_SHMOBILE || ARCH_TEGRA - default 512 if SOC_OMAP5 default 355 if ARCH_U8500 - default 352 if ARCH_VT8500 - default 288 if ARCH_SUNXI default 264 if MACH_H4700 + default 512 if SOC_OMAP5 + default 288 if ARCH_VT8500 || ARCH_SUNXI default 0 help Maximum number of GPIOs in the system. @@ -1895,9 +1887,8 @@ config XEN_DOM0 config XEN bool "Xen guest support on ARM (EXPERIMENTAL)" - depends on ARM && AEABI && OF + depends on ARM && OF depends on CPU_V7 && !CPU_V6 - depends on !GENERIC_ATOMIC64 help Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug index 9b31f4311ea2..acddddac7ee4 100644 --- a/trunk/arch/arm/Kconfig.debug +++ b/trunk/arch/arm/Kconfig.debug @@ -492,10 +492,9 @@ config DEBUG_IMX_UART_PORT DEBUG_IMX31_UART || \ DEBUG_IMX35_UART || \ DEBUG_IMX51_UART || \ - DEBUG_IMX53_UART || \ + DEBUG_IMX50_IMX53_UART || \ DEBUG_IMX6Q_UART default 1 - depends on ARCH_MXC help Choose UART port on which kernel low-level debug messages should be output. diff --git a/trunk/arch/arm/boot/Makefile b/trunk/arch/arm/boot/Makefile index 84aa2caf07ed..71768b8a1ab9 100644 --- a/trunk/arch/arm/boot/Makefile +++ b/trunk/arch/arm/boot/Makefile @@ -115,4 +115,4 @@ i: $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/Image System.map "$(INSTALL_PATH)" -subdir- := bootp compressed dts +subdir- := bootp compressed diff --git a/trunk/arch/arm/boot/compressed/Makefile b/trunk/arch/arm/boot/compressed/Makefile index afed28e37ea5..5cad8a6dadb0 100644 --- a/trunk/arch/arm/boot/compressed/Makefile +++ b/trunk/arch/arm/boot/compressed/Makefile @@ -120,7 +120,7 @@ ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif -ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) +ccflags-y := -fpic -fno-builtin -I$(obj) asflags-y := -Wa,-march=all -DZIMAGE # Supply kernel BSS size to the decompressor via a linker symbol. diff --git a/trunk/arch/arm/boot/dts/armada-370-rd.dts b/trunk/arch/arm/boot/dts/armada-370-rd.dts index 070bba4f2585..f8e4855bc9a5 100644 --- a/trunk/arch/arm/boot/dts/armada-370-rd.dts +++ b/trunk/arch/arm/boot/dts/armada-370-rd.dts @@ -64,13 +64,5 @@ status = "okay"; /* No CD or WP GPIOs */ }; - - usb@d0050000 { - status = "okay"; - }; - - usb@d0051000 { - status = "okay"; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-370-xp.dtsi b/trunk/arch/arm/boot/dts/armada-370-xp.dtsi index 5b708208b607..6f1acc75e155 100644 --- a/trunk/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/trunk/arch/arm/boot/dts/armada-370-xp.dtsi @@ -31,6 +31,7 @@ mpic: interrupt-controller@d0020000 { compatible = "marvell,mpic"; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <1>; interrupt-controller; }; @@ -53,7 +54,7 @@ reg = <0xd0012000 0x100>; reg-shift = <2>; interrupts = <41>; - reg-io-width = <1>; + reg-io-width = <4>; status = "disabled"; }; serial@d0012100 { @@ -61,7 +62,7 @@ reg = <0xd0012100 0x100>; reg-shift = <2>; interrupts = <42>; - reg-io-width = <1>; + reg-io-width = <4>; status = "disabled"; }; diff --git a/trunk/arch/arm/boot/dts/armada-xp.dtsi b/trunk/arch/arm/boot/dts/armada-xp.dtsi index ca00d8326c87..1443949c165e 100644 --- a/trunk/arch/arm/boot/dts/armada-xp.dtsi +++ b/trunk/arch/arm/boot/dts/armada-xp.dtsi @@ -46,7 +46,7 @@ reg = <0xd0012200 0x100>; reg-shift = <2>; interrupts = <43>; - reg-io-width = <1>; + reg-io-width = <4>; status = "disabled"; }; serial@d0012300 { @@ -54,7 +54,7 @@ reg = <0xd0012300 0x100>; reg-shift = <2>; interrupts = <44>; - reg-io-width = <1>; + reg-io-width = <4>; status = "disabled"; }; diff --git a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi index a98c0d50fbbe..aa98e641931f 100644 --- a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi @@ -238,32 +238,8 @@ nand { pinctrl_nand: nand-0 { atmel,pins = - <3 0 0x1 0x0 /* PD0 periph A Read Enable */ - 3 1 0x1 0x0 /* PD1 periph A Write Enable */ - 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */ - 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */ - 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */ - 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */ - 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */ - 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */ - 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */ - 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */ - 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */ - 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */ - 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */ - 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */ - }; - - pinctrl_nand_16bits: nand_16bits-0 { - atmel,pins = - <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */ - 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */ - 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */ - 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */ - 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */ - 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */ - 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */ - 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */ + <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */ + 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */ }; }; diff --git a/trunk/arch/arm/boot/dts/bcm2835.dtsi b/trunk/arch/arm/boot/dts/bcm2835.dtsi index 7e0481e2441a..4bf2a8774aa7 100644 --- a/trunk/arch/arm/boot/dts/bcm2835.dtsi +++ b/trunk/arch/arm/boot/dts/bcm2835.dtsi @@ -105,7 +105,7 @@ compatible = "fixed-clock"; reg = <1>; #clock-cells = <0>; - clock-frequency = <250000000>; + clock-frequency = <150000000>; }; }; }; diff --git a/trunk/arch/arm/boot/dts/dbx5x0.dtsi b/trunk/arch/arm/boot/dts/dbx5x0.dtsi index 9de93096601a..69140ba99f46 100644 --- a/trunk/arch/arm/boot/dts/dbx5x0.dtsi +++ b/trunk/arch/arm/boot/dts/dbx5x0.dtsi @@ -319,8 +319,9 @@ }; }; - ab8500 { + ab8500@5 { compatible = "stericsson,ab8500"; + reg = <5>; /* mailbox 5 is i2c */ interrupt-parent = <&intc>; interrupts = <0 40 0x4>; interrupt-controller; diff --git a/trunk/arch/arm/boot/dts/dove.dtsi b/trunk/arch/arm/boot/dts/dove.dtsi index f7509cafc377..67dbe20868a2 100644 --- a/trunk/arch/arm/boot/dts/dove.dtsi +++ b/trunk/arch/arm/boot/dts/dove.dtsi @@ -197,11 +197,6 @@ status = "disabled"; }; - rtc@d8500 { - compatible = "marvell,orion-rtc"; - reg = <0xd8500 0x20>; - }; - crypto: crypto@30000 { compatible = "marvell,orion-crypto"; reg = <0x30000 0x10000>, diff --git a/trunk/arch/arm/boot/dts/exynos4.dtsi b/trunk/arch/arm/boot/dts/exynos4.dtsi index 1a62bcf18aa3..e1347fceb5bc 100644 --- a/trunk/arch/arm/boot/dts/exynos4.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4.dtsi @@ -275,27 +275,18 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = <0 35 0>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = <0 36 0>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; mdma1: mdma@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = <0 34 0>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4210.dtsi b/trunk/arch/arm/boot/dts/exynos4210.dtsi index 49a2786e00b9..2feffc70814c 100644 --- a/trunk/arch/arm/boot/dts/exynos4210.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4210.dtsi @@ -47,28 +47,6 @@ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; }; - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &gic 0 69 0>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 0 42 0>, - <0x5 0 &gic 0 48 0>; - }; - }; - pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11400000 0x1000>; diff --git a/trunk/arch/arm/boot/dts/exynos4212.dtsi b/trunk/arch/arm/boot/dts/exynos4212.dtsi index 36d4299789ef..c6ae2005961f 100644 --- a/trunk/arch/arm/boot/dts/exynos4212.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4212.dtsi @@ -25,26 +25,4 @@ gic:interrupt-controller@10490000 { cpu-offset = <0x8000>; }; - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4412.dtsi b/trunk/arch/arm/boot/dts/exynos4412.dtsi index 821c9fdd1e3b..d7dfe312772a 100644 --- a/trunk/arch/arm/boot/dts/exynos4412.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4412.dtsi @@ -25,28 +25,4 @@ gic:interrupt-controller@10490000 { cpu-offset = <0x4000>; }; - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>, - <0x6 0 &gic 1 12 0>, - <0x7 0 &gic 1 12 0>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos5250.dtsi b/trunk/arch/arm/boot/dts/exynos5250.dtsi index c60108e0d27e..b1ac73e21c80 100644 --- a/trunk/arch/arm/boot/dts/exynos5250.dtsi +++ b/trunk/arch/arm/boot/dts/exynos5250.dtsi @@ -69,28 +69,6 @@ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; }; - mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &combiner 23 3>, - <0x1 0 &combiner 23 4>, - <0x2 0 &combiner 25 2>, - <0x3 0 &combiner 25 3>, - <0x4 0 &gic 0 120 0>, - <0x5 0 &gic 0 121 0>; - }; - }; - watchdog { compatible = "samsung,s3c2410-wdt"; reg = <0x101D0000 0x100>; diff --git a/trunk/arch/arm/boot/dts/exynos5440.dtsi b/trunk/arch/arm/boot/dts/exynos5440.dtsi index 9a99755920c0..0bde96d6570b 100644 --- a/trunk/arch/arm/boot/dts/exynos5440.dtsi +++ b/trunk/arch/arm/boot/dts/exynos5440.dtsi @@ -58,11 +58,6 @@ }; }; - common { - compatible = "samsung,exynos5440"; - - }; - serial@B0000 { compatible = "samsung,exynos4210-uart"; reg = <0xB0000 0x1000>; @@ -142,18 +137,12 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x120000 0x1000>; interrupts = <0 34 0>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: pdma@121B0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121000 0x1000>; interrupts = <0 35 0>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; }; diff --git a/trunk/arch/arm/boot/dts/href.dtsi b/trunk/arch/arm/boot/dts/href.dtsi index 379128eb9d98..592fb9dc35bd 100644 --- a/trunk/arch/arm/boot/dts/href.dtsi +++ b/trunk/arch/arm/boot/dts/href.dtsi @@ -221,7 +221,7 @@ }; }; - ab8500 { + ab8500@5 { ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; diff --git a/trunk/arch/arm/boot/dts/hrefv60plus.dts b/trunk/arch/arm/boot/dts/hrefv60plus.dts index 2b587a74b813..55f4191a626e 100644 --- a/trunk/arch/arm/boot/dts/hrefv60plus.dts +++ b/trunk/arch/arm/boot/dts/hrefv60plus.dts @@ -158,7 +158,7 @@ }; }; - ab8500 { + ab8500@5 { ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; diff --git a/trunk/arch/arm/boot/dts/imx53-mba53.dts b/trunk/arch/arm/boot/dts/imx53-mba53.dts index 468c0a1d48d9..e54fffd48369 100644 --- a/trunk/arch/arm/boot/dts/imx53-mba53.dts +++ b/trunk/arch/arm/boot/dts/imx53-mba53.dts @@ -42,9 +42,10 @@ fsl,pins = <689 0x10000 /* DISP1_DRDY */ 482 0x10000 /* DISP1_HSYNC */ 489 0x10000 /* DISP1_VSYNC */ + 684 0x10000 /* DISP1_DAT_0 */ 515 0x10000 /* DISP1_DAT_22 */ 523 0x10000 /* DISP1_DAT_23 */ - 545 0x10000 /* DISP1_DAT_21 */ + 543 0x10000 /* DISP1_DAT_21 */ 553 0x10000 /* DISP1_DAT_20 */ 558 0x10000 /* DISP1_DAT_19 */ 564 0x10000 /* DISP1_DAT_18 */ diff --git a/trunk/arch/arm/boot/dts/kirkwood-dns320.dts b/trunk/arch/arm/boot/dts/kirkwood-dns320.dts index c9c44b2f62d7..5bb0bf39d3b8 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-dns320.dts @@ -42,10 +42,12 @@ ocp@f1000000 { serial@12000 { + clock-frequency = <166666667>; status = "okay"; }; serial@12100 { + clock-frequency = <166666667>; status = "okay"; }; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-dns325.dts b/trunk/arch/arm/boot/dts/kirkwood-dns325.dts index e4e4930dc5cf..d430713ea9b9 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-dns325.dts @@ -50,6 +50,7 @@ }; }; serial@12000 { + clock-frequency = <200000000>; status = "okay"; }; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-dockstar.dts b/trunk/arch/arm/boot/dts/kirkwood-dockstar.dts index 0196cf6b0ef2..2e3dd34e21a5 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -37,6 +37,7 @@ }; }; serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-dreamplug.dts b/trunk/arch/arm/boot/dts/kirkwood-dreamplug.dts index 289e51d86372..ef2d8c705709 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -38,6 +38,7 @@ }; }; serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts b/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts index bd83b8fc7c83..1b133e0c566e 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -73,6 +73,7 @@ }; }; serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-ib62x0.dts b/trunk/arch/arm/boot/dts/kirkwood-ib62x0.dts index 5335b1aa8601..71902da33d63 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -51,6 +51,7 @@ }; }; serial@12000 { + clock-frequency = <200000000>; status = "okay"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts b/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts index 12ccf74ac3c4..504f16be8b54 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -78,6 +78,7 @@ }; }; serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/trunk/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 93c3afbef9ee..6cae4599c4b3 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -115,6 +115,7 @@ }; serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/trunk/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 5bbd0542cdd3..8db3123ac80f 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -34,6 +34,7 @@ }; serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-lschlv2.dts b/trunk/arch/arm/boot/dts/kirkwood-lschlv2.dts index 9f55d95f35f5..9510c9ea666c 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-lschlv2.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-lschlv2.dts @@ -13,6 +13,7 @@ ocp@f1000000 { serial@12000 { + clock-frequency = <166666667>; status = "okay"; }; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-lsxhl.dts b/trunk/arch/arm/boot/dts/kirkwood-lsxhl.dts index 5c84c118ed8d..739019c4cba9 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-lsxhl.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-lsxhl.dts @@ -13,6 +13,7 @@ ocp@f1000000 { serial@12000 { + clock-frequency = <200000000>; status = "okay"; }; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-mplcec4.dts b/trunk/arch/arm/boot/dts/kirkwood-mplcec4.dts index 758824118a9a..662dfd81b1ce 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -90,6 +90,7 @@ }; serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/trunk/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 6affd924fe11..e8e7ecef1650 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/trunk/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -23,6 +23,7 @@ }; serial@12000 { + clock-frequency = <166666667>; status = "okay"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-nsa310.dts b/trunk/arch/arm/boot/dts/kirkwood-nsa310.dts index a7412b937a8a..3a178cf708d7 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -117,6 +117,7 @@ }; serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/trunk/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index d27f7245f8e7..ede7fe0d7a87 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -18,10 +18,12 @@ ocp@f1000000 { serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; serial@12100 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-topkick.dts b/trunk/arch/arm/boot/dts/kirkwood-topkick.dts index 66eb45b00b25..842ff95d60df 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-topkick.dts @@ -108,6 +108,7 @@ }; serial@12000 { + clock-frequency = <200000000>; status = "ok"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood.dtsi b/trunk/arch/arm/boot/dts/kirkwood.dtsi index fada7e6d24d8..2c738d9dc82a 100644 --- a/trunk/arch/arm/boot/dts/kirkwood.dtsi +++ b/trunk/arch/arm/boot/dts/kirkwood.dtsi @@ -38,7 +38,6 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <35>, <36>, <37>, <38>; - clocks = <&gate_clk 7>; }; gpio1: gpio@10140 { @@ -50,7 +49,6 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <39>, <40>, <41>; - clocks = <&gate_clk 7>; }; serial@12000 { @@ -59,6 +57,7 @@ reg-shift = <2>; interrupts = <33>; clocks = <&gate_clk 7>; + /* set clock-frequency in board dts */ status = "disabled"; }; @@ -68,6 +67,7 @@ reg-shift = <2>; interrupts = <34>; clocks = <&gate_clk 7>; + /* set clock-frequency in board dts */ status = "disabled"; }; @@ -75,7 +75,6 @@ compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <53>; - clocks = <&gate_clk 7>; }; spi@10600 { diff --git a/trunk/arch/arm/boot/dts/omap3-beagle.dts b/trunk/arch/arm/boot/dts/omap3-beagle.dts index 02d23f15fd86..f624dc85d441 100644 --- a/trunk/arch/arm/boot/dts/omap3-beagle.dts +++ b/trunk/arch/arm/boot/dts/omap3-beagle.dts @@ -38,57 +38,6 @@ }; }; - /* HS USB Port 2 RESET */ - hsusb2_reset: hsusb2_reset_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_reset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 19 0>; /* gpio_147 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 0>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-supply = <&hsusb2_reset>; - vcc-supply = <&hsusb2_power>; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb2_pins - >; - - hsusbb2_pins: pinmux_hsusbb2_pins { - pinctrl-single,pins = < - 0x5c0 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */ - 0x5c2 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */ - 0x5c4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */ - 0x5c6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */ - 0x5c8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */ - 0x5cA 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */ - 0x1a4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */ - 0x1a6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */ - 0x1a8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */ - 0x1aa 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */ - 0x1ac 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */ - 0x1ae 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */ - >; - }; }; &i2c1 { @@ -116,23 +65,3 @@ &mmc3 { status = "disabled"; }; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; diff --git a/trunk/arch/arm/boot/dts/omap3.dtsi b/trunk/arch/arm/boot/dts/omap3.dtsi index a14f74bbce7c..1acc26148ffc 100644 --- a/trunk/arch/arm/boot/dts/omap3.dtsi +++ b/trunk/arch/arm/boot/dts/omap3.dtsi @@ -397,36 +397,5 @@ ti,timer-alwon; ti,timer-secure; }; - - usbhstll: usbhstll@48062000 { - compatible = "ti,usbhs-tll"; - reg = <0x48062000 0x1000>; - interrupts = <78>; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@48064000 { - compatible = "ti,usbhs-host"; - reg = <0x48064000 0x400>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbhsohci: ohci@48064400 { - compatible = "ti,ohci-omap3", "usb-ohci"; - reg = <0x48064400 0x400>; - interrupt-parent = <&intc>; - interrupts = <76>; - }; - - usbhsehci: ehci@48064800 { - compatible = "ti,ehci-omap", "usb-ehci"; - reg = <0x48064800 0x400>; - interrupt-parent = <&intc>; - interrupts = <77>; - }; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/omap4.dtsi b/trunk/arch/arm/boot/dts/omap4.dtsi index b7db1a2b6ca7..739bb79e410e 100644 --- a/trunk/arch/arm/boot/dts/omap4.dtsi +++ b/trunk/arch/arm/boot/dts/omap4.dtsi @@ -529,35 +529,5 @@ ti,hwmods = "timer11"; ti,timer-pwm; }; - - usbhstll: usbhstll@4a062000 { - compatible = "ti,usbhs-tll"; - reg = <0x4a062000 0x1000>; - interrupts = <0 78 0x4>; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@4a064000 { - compatible = "ti,usbhs-host"; - reg = <0x4a064000 0x800>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3", "usb-ohci"; - reg = <0x4a064800 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 76 0x4>; - }; - - usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap", "usb-ehci"; - reg = <0x4a064c00 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 77 0x4>; - }; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/trunk/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 0077fc8510b7..5a3a58b7e18f 100644 --- a/trunk/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/trunk/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -11,7 +11,7 @@ / { model = "LaCie Ethernet Disk mini V2"; - compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x"; + compatible = "lacie,ethernet-disk-mini-v2", "marvell-orion5x-88f5182", "marvell,orion5x"; memory { reg = <0x00000000 0x4000000>; /* 64 MB */ diff --git a/trunk/arch/arm/boot/dts/r8a7779.dtsi b/trunk/arch/arm/boot/dts/r8a7779.dtsi deleted file mode 100644 index fe5c6f213271..000000000000 --- a/trunk/arch/arm/boot/dts/r8a7779.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Device Tree Source for Renesas r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "renesas,r8a7779"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - }; - }; - - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; - - i2c0: i2c@0xffc70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0xffc70000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 79 0x4>; - }; - - i2c1: i2c@0xffc71000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0xffc71000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 82 0x4>; - }; - - i2c2: i2c@0xffc72000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0xffc72000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 80 0x4>; - }; - - i2c3: i2c@0xffc73000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0xffc73000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 81 0x4>; - }; - - thermal@ffc48000 { - compatible = "renesas,rcar-thermal"; - reg = <0xffc48000 0x38>; - }; - - sata: sata@fc600000 { - compatible = "renesas,rcar-sata"; - reg = <0xfc600000 0x2000>; - interrupt-parent = <&gic>; - interrupts = <0 100 0x4>; - }; -}; diff --git a/trunk/arch/arm/boot/dts/snowball.dts b/trunk/arch/arm/boot/dts/snowball.dts index d3ec32f6b790..27f31a5fa494 100644 --- a/trunk/arch/arm/boot/dts/snowball.dts +++ b/trunk/arch/arm/boot/dts/snowball.dts @@ -298,7 +298,7 @@ }; }; - ab8500 { + ab8500@5 { ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; diff --git a/trunk/arch/arm/boot/dts/socfpga.dtsi b/trunk/arch/arm/boot/dts/socfpga.dtsi index 7e8769bd5977..936d2306e7e1 100644 --- a/trunk/arch/arm/boot/dts/socfpga.dtsi +++ b/trunk/arch/arm/boot/dts/socfpga.dtsi @@ -75,9 +75,6 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0xffe01000 0x1000>; interrupts = <0 180 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra114-dalmore.dts b/trunk/arch/arm/boot/dts/tegra114-dalmore.dts index 616990dc92db..a30aca62658a 100644 --- a/trunk/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/trunk/arch/arm/boot/dts/tegra114-dalmore.dts @@ -12,22 +12,10 @@ serial@70006300 { status = "okay"; + clock-frequency = <408000000>; }; pmc { nvidia,invert-interrupt; }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/tegra114-pluto.dts b/trunk/arch/arm/boot/dts/tegra114-pluto.dts index 6bbc8efae9c0..9bea8f57aa47 100644 --- a/trunk/arch/arm/boot/dts/tegra114-pluto.dts +++ b/trunk/arch/arm/boot/dts/tegra114-pluto.dts @@ -12,22 +12,10 @@ serial@70006300 { status = "okay"; + clock-frequency = <408000000>; }; pmc { nvidia,invert-interrupt; }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/tegra114.dtsi b/trunk/arch/arm/boot/dts/tegra114.dtsi index c1110a9b2a91..1dfaf2874c57 100644 --- a/trunk/arch/arm/boot/dts/tegra114.dtsi +++ b/trunk/arch/arm/boot/dts/tegra114.dtsi @@ -24,11 +24,10 @@ 0 42 0x04 0 121 0x04 0 122 0x04>; - clocks = <&tegra_car 5>; }; tegra_car: clock { - compatible = "nvidia,tegra114-car"; + compatible = "nvidia,tegra114-car, nvidia,tegra30-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; }; @@ -67,7 +66,6 @@ reg-shift = <2>; interrupts = <0 36 0x04>; status = "disabled"; - clocks = <&tegra_car 6>; }; serial@70006040 { @@ -76,7 +74,6 @@ reg-shift = <2>; interrupts = <0 37 0x04>; status = "disabled"; - clocks = <&tegra_car 192>; }; serial@70006200 { @@ -85,7 +82,6 @@ reg-shift = <2>; interrupts = <0 46 0x04>; status = "disabled"; - clocks = <&tegra_car 55>; }; serial@70006300 { @@ -94,21 +90,17 @@ reg-shift = <2>; interrupts = <0 90 0x04>; status = "disabled"; - clocks = <&tegra_car 65>; }; rtc { compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; }; pmc { - compatible = "nvidia,tegra114-pmc"; + compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 261>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; }; iommu { diff --git a/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 4e3afdef28a8..444162090042 100644 --- a/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -444,20 +444,7 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 23 1>; /* gpio PC7 */ - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + cd-gpios = <&gpio 23 0>; /* gpio PC7 */ }; sound { diff --git a/trunk/arch/arm/boot/dts/tegra20-harmony.dts b/trunk/arch/arm/boot/dts/tegra20-harmony.dts index ae9d5a20834e..61d027f03617 100644 --- a/trunk/arch/arm/boot/dts/tegra20-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra20-harmony.dts @@ -437,7 +437,7 @@ sdhci@c8000200 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ bus-width = <4>; @@ -445,25 +445,12 @@ sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <8>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - kbc { status = "okay"; nvidia,debounce-delay-ms = <2>; diff --git a/trunk/arch/arm/boot/dts/tegra20-paz00.dts b/trunk/arch/arm/boot/dts/tegra20-paz00.dts index fd60940e4063..54d6fce00a59 100644 --- a/trunk/arch/arm/boot/dts/tegra20-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra20-paz00.dts @@ -436,7 +436,7 @@ sdhci@c8000000 { status = "okay"; - cd-gpios = <&gpio 173 1>; /* gpio PV5 */ + cd-gpios = <&gpio 173 0>; /* gpio PV5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 169 0>; /* gpio PV1 */ bus-width = <4>; @@ -447,19 +447,6 @@ bus-width = <8>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - gpio-keys { compatible = "gpio-keys"; diff --git a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts index 4ee700a33ca5..37b3a57ec0f1 100644 --- a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts @@ -584,7 +584,7 @@ sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <4>; @@ -595,19 +595,6 @@ bus-width = <8>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - gpio-keys { compatible = "gpio-keys"; diff --git a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi index c19025725918..4766abae7a72 100644 --- a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -465,25 +465,12 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ bus-width = <4>; status = "okay"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - regulators { compatible = "simple-bus"; diff --git a/trunk/arch/arm/boot/dts/tegra20-trimslice.dts b/trunk/arch/arm/boot/dts/tegra20-trimslice.dts index a9f3f06580f5..5d79e4fc49a6 100644 --- a/trunk/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/trunk/arch/arm/boot/dts/tegra20-trimslice.dts @@ -325,24 +325,11 @@ sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 121 1>; /* gpio PP1 */ + cd-gpios = <&gpio 121 0>; /* gpio PP1 */ wp-gpios = <&gpio 122 0>; /* gpio PP2 */ bus-width = <4>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - poweroff { compatible = "gpio-poweroff"; gpios = <&gpio 191 1>; /* gpio PX7, active low */ diff --git a/trunk/arch/arm/boot/dts/tegra20-ventana.dts b/trunk/arch/arm/boot/dts/tegra20-ventana.dts index f544806e9618..425c89000c20 100644 --- a/trunk/arch/arm/boot/dts/tegra20-ventana.dts +++ b/trunk/arch/arm/boot/dts/tegra20-ventana.dts @@ -520,7 +520,7 @@ sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <4>; @@ -531,19 +531,6 @@ bus-width = <8>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/tegra20-whistler.dts b/trunk/arch/arm/boot/dts/tegra20-whistler.dts index 258cf945f515..ea57c0f6dcce 100644 --- a/trunk/arch/arm/boot/dts/tegra20-whistler.dts +++ b/trunk/arch/arm/boot/dts/tegra20-whistler.dts @@ -510,7 +510,6 @@ sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 173 0>; /* gpio PV5 */ bus-width = <8>; }; @@ -520,19 +519,6 @@ bus-width = <8>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - kbc { status = "okay"; nvidia,debounce-delay-ms = <20>; diff --git a/trunk/arch/arm/boot/dts/tegra20.dtsi b/trunk/arch/arm/boot/dts/tegra20.dtsi index fc7febc2b386..9a428931d042 100644 --- a/trunk/arch/arm/boot/dts/tegra20.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20.dtsi @@ -118,7 +118,6 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0x50040600 0x20>; interrupts = <1 13 0x304>; - clocks = <&tegra_car 132>; }; intc: interrupt-controller { @@ -145,7 +144,6 @@ 0 1 0x04 0 41 0x04 0 42 0x04>; - clocks = <&tegra_car 5>; }; tegra_car: clock { @@ -305,7 +303,6 @@ compatible = "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; }; i2c@7000c000 { @@ -387,7 +384,7 @@ spi@7000d800 { compatible = "nvidia,tegra20-slink"; - reg = <0x7000d800 0x200>; + reg = <0x7000d480 0x200>; interrupts = <0 83 0x04>; nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; @@ -418,8 +415,6 @@ pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 110>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; }; memory-controller@7000f000 { diff --git a/trunk/arch/arm/boot/dts/tegra30-beaver.dts b/trunk/arch/arm/boot/dts/tegra30-beaver.dts index 6248b2445b32..8ff2ff20e4a3 100644 --- a/trunk/arch/arm/boot/dts/tegra30-beaver.dts +++ b/trunk/arch/arm/boot/dts/tegra30-beaver.dts @@ -257,7 +257,7 @@ sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 31 0>; /* gpio PD7 */ bus-width = <4>; @@ -268,19 +268,6 @@ bus-width = <8>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi index 65bf2b63174e..17499272a4ef 100644 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -311,7 +311,7 @@ sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 31 0>; /* gpio PD7 */ bus-width = <4>; @@ -322,19 +322,6 @@ bus-width = <8>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/tegra30.dtsi b/trunk/arch/arm/boot/dts/tegra30.dtsi index 9fe7a92b4c85..767803e1fd55 100644 --- a/trunk/arch/arm/boot/dts/tegra30.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30.dtsi @@ -119,7 +119,6 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0x50040600 0x20>; interrupts = <1 13 0xf04>; - clocks = <&tegra_car 214>; }; intc: interrupt-controller { @@ -148,7 +147,6 @@ 0 42 0x04 0 121 0x04 0 122 0x04>; - clocks = <&tegra_car 5>; }; tegra_car: clock { @@ -292,7 +290,6 @@ compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; }; i2c@7000c000 { @@ -374,7 +371,7 @@ spi@7000d800 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d800 0x200>; + reg = <0x7000d480 0x200>; interrupts = <0 83 0x04>; nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; @@ -425,10 +422,8 @@ }; pmc { - compatible = "nvidia,tegra30-pmc"; + compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 218>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; }; memory-controller { diff --git a/trunk/arch/arm/boot/dts/vt8500.dtsi b/trunk/arch/arm/boot/dts/vt8500.dtsi index e1c3926aca52..cf31ced46602 100644 --- a/trunk/arch/arm/boot/dts/vt8500.dtsi +++ b/trunk/arch/arm/boot/dts/vt8500.dtsi @@ -25,13 +25,11 @@ #interrupt-cells = <1>; }; - pinctrl: pinctrl@d8110000 { - compatible = "via,vt8500-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; + gpio: gpio-controller@d8110000 { + compatible = "via,vt8500-gpio"; gpio-controller; - #gpio-cells = <2>; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; }; pmc@d8130000 { diff --git a/trunk/arch/arm/boot/dts/wm8505.dtsi b/trunk/arch/arm/boot/dts/wm8505.dtsi index bb92ef8ce665..e74a1c0fb9a2 100644 --- a/trunk/arch/arm/boot/dts/wm8505.dtsi +++ b/trunk/arch/arm/boot/dts/wm8505.dtsi @@ -40,13 +40,11 @@ interrupts = <56 57 58 59 60 61 62 63>; }; - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8505-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; + gpio: gpio-controller@d8110000 { + compatible = "wm,wm8505-gpio"; gpio-controller; - #gpio-cells = <2>; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; }; pmc@d8130000 { diff --git a/trunk/arch/arm/boot/dts/wm8650.dtsi b/trunk/arch/arm/boot/dts/wm8650.dtsi index bb4af580f40b..db3c0a12e052 100644 --- a/trunk/arch/arm/boot/dts/wm8650.dtsi +++ b/trunk/arch/arm/boot/dts/wm8650.dtsi @@ -34,13 +34,11 @@ interrupts = <56 57 58 59 60 61 62 63>; }; - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8650-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; + gpio: gpio-controller@d8110000 { + compatible = "wm,wm8650-gpio"; gpio-controller; - #gpio-cells = <2>; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; }; pmc@d8130000 { diff --git a/trunk/arch/arm/boot/dts/wm8850.dtsi b/trunk/arch/arm/boot/dts/wm8850.dtsi index 11cd180c58d3..e8cbfdc87bba 100644 --- a/trunk/arch/arm/boot/dts/wm8850.dtsi +++ b/trunk/arch/arm/boot/dts/wm8850.dtsi @@ -41,13 +41,11 @@ interrupts = <56 57 58 59 60 61 62 63>; }; - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8850-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; + gpio: gpio-controller@d8110000 { + compatible = "wm,wm8650-gpio"; gpio-controller; - #gpio-cells = <2>; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; }; pmc@d8130000 { diff --git a/trunk/arch/arm/boot/dts/zynq-7000.dtsi b/trunk/arch/arm/boot/dts/zynq-7000.dtsi index 51243db2e9e4..5914b5654591 100644 --- a/trunk/arch/arm/boot/dts/zynq-7000.dtsi +++ b/trunk/arch/arm/boot/dts/zynq-7000.dtsi @@ -111,23 +111,56 @@ }; ttc0: ttc0@f8001000 { - interrupt-parent = <&intc>; - interrupts = < 0 10 4 0 11 4 0 12 4 >; - compatible = "cdns,ttc"; + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; reg = <0xF8001000 0x1000>; clocks = <&cpu_clk 3>; clock-names = "cpu_1x"; clock-ranges; + + ttc0_0: ttc0.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 10 4>; + }; + ttc0_1: ttc0.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 11 4>; + }; + ttc0_2: ttc0.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 12 4>; + }; }; ttc1: ttc1@f8002000 { - interrupt-parent = <&intc>; - interrupts = < 0 37 4 0 38 4 0 39 4 >; - compatible = "cdns,ttc"; + #interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; reg = <0xF8002000 0x1000>; clocks = <&cpu_clk 3>; clock-names = "cpu_1x"; clock-ranges; + + ttc1_0: ttc1.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 37 4>; + }; + ttc1_1: ttc1.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 38 4>; + }; + ttc1_2: ttc1.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 39 4>; + }; }; }; }; diff --git a/trunk/arch/arm/boot/dts/zynq-zc702.dts b/trunk/arch/arm/boot/dts/zynq-zc702.dts index 86f44d5b0265..c772942a399a 100644 --- a/trunk/arch/arm/boot/dts/zynq-zc702.dts +++ b/trunk/arch/arm/boot/dts/zynq-zc702.dts @@ -32,3 +32,13 @@ &ps_clk { clock-frequency = <33333330>; }; + +&ttc0_0 { + status = "ok"; + compatible = "xlnx,ttc-counter-clocksource"; +}; + +&ttc0_1 { + status = "ok"; + compatible = "xlnx,ttc-counter-clockevent"; +}; diff --git a/trunk/arch/arm/configs/mxs_defconfig b/trunk/arch/arm/configs/mxs_defconfig index 6a99e30f81d2..fbbc5bb022d5 100644 --- a/trunk/arch/arm/configs/mxs_defconfig +++ b/trunk/arch/arm/configs/mxs_defconfig @@ -116,7 +116,6 @@ CONFIG_SND_SOC=y CONFIG_SND_MXS_SOC=y CONFIG_SND_SOC_MXS_SGTL5000=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_STORAGE=y diff --git a/trunk/arch/arm/configs/omap2plus_defconfig b/trunk/arch/arm/configs/omap2plus_defconfig index bd07864f14a0..b16bae2c9a60 100644 --- a/trunk/arch/arm/configs/omap2plus_defconfig +++ b/trunk/arch/arm/configs/omap2plus_defconfig @@ -126,8 +126,6 @@ CONFIG_INPUT_MISC=y CONFIG_INPUT_TWL4030_PWRBUTTON=y CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=32 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y diff --git a/trunk/arch/arm/include/asm/mmu.h b/trunk/arch/arm/include/asm/mmu.h index e3d55547e755..9f77e7804f3b 100644 --- a/trunk/arch/arm/include/asm/mmu.h +++ b/trunk/arch/arm/include/asm/mmu.h @@ -5,15 +5,15 @@ typedef struct { #ifdef CONFIG_CPU_HAS_ASID - atomic64_t id; + u64 id; #endif - unsigned int vmalloc_seq; + unsigned int vmalloc_seq; } mm_context_t; #ifdef CONFIG_CPU_HAS_ASID #define ASID_BITS 8 #define ASID_MASK ((~0ULL) << ASID_BITS) -#define ASID(mm) ((mm)->context.id.counter & ~ASID_MASK) +#define ASID(mm) ((mm)->context.id & ~ASID_MASK) #else #define ASID(mm) (0) #endif @@ -26,7 +26,7 @@ typedef struct { * modified for 2.6 by Hyok S. Choi */ typedef struct { - unsigned long end_brk; + unsigned long end_brk; } mm_context_t; #endif diff --git a/trunk/arch/arm/include/asm/mmu_context.h b/trunk/arch/arm/include/asm/mmu_context.h index 863a6611323c..e1f644bc7cc5 100644 --- a/trunk/arch/arm/include/asm/mmu_context.h +++ b/trunk/arch/arm/include/asm/mmu_context.h @@ -25,7 +25,7 @@ void __check_vmalloc_seq(struct mm_struct *mm); #ifdef CONFIG_CPU_HAS_ASID void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); -#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) +#define init_new_context(tsk,mm) ({ mm->context.id = 0; }) #else /* !CONFIG_CPU_HAS_ASID */ diff --git a/trunk/arch/arm/include/asm/smp_twd.h b/trunk/arch/arm/include/asm/smp_twd.h index 7b2899c2f7fc..0f01f4677bd2 100644 --- a/trunk/arch/arm/include/asm/smp_twd.h +++ b/trunk/arch/arm/include/asm/smp_twd.h @@ -34,4 +34,12 @@ struct twd_local_timer name __initdata = { \ int twd_local_timer_register(struct twd_local_timer *); +#ifdef CONFIG_HAVE_ARM_TWD +void twd_local_timer_of_register(void); +#else +static inline void twd_local_timer_of_register(void) +{ +} +#endif + #endif diff --git a/trunk/arch/arm/include/asm/tlbflush.h b/trunk/arch/arm/include/asm/tlbflush.h index 4db8c8820f0d..6e924d3a77eb 100644 --- a/trunk/arch/arm/include/asm/tlbflush.h +++ b/trunk/arch/arm/include/asm/tlbflush.h @@ -34,13 +34,10 @@ #define TLB_V6_D_ASID (1 << 17) #define TLB_V6_I_ASID (1 << 18) -#define TLB_V6_BP (1 << 19) - /* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ -#define TLB_V7_UIS_PAGE (1 << 20) -#define TLB_V7_UIS_FULL (1 << 21) -#define TLB_V7_UIS_ASID (1 << 22) -#define TLB_V7_UIS_BP (1 << 23) +#define TLB_V7_UIS_PAGE (1 << 19) +#define TLB_V7_UIS_FULL (1 << 20) +#define TLB_V7_UIS_ASID (1 << 21) #define TLB_BARRIER (1 << 28) #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ @@ -153,8 +150,7 @@ #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ TLB_V6_I_FULL | TLB_V6_D_FULL | \ TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ - TLB_V6_I_ASID | TLB_V6_D_ASID | \ - TLB_V6_BP) + TLB_V6_I_ASID | TLB_V6_D_ASID) #ifdef CONFIG_CPU_TLB_V6 # define v6wbi_possible_flags v6wbi_tlb_flags @@ -170,11 +166,9 @@ #endif #define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ - TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \ - TLB_V7_UIS_ASID | TLB_V7_UIS_BP) + TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) #define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ - TLB_V6_U_FULL | TLB_V6_U_PAGE | \ - TLB_V6_U_ASID | TLB_V6_BP) + TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) #ifdef CONFIG_CPU_TLB_V7 @@ -436,20 +430,6 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) } } -static inline void local_flush_bp_all(void) -{ - const int zero = 0; - const unsigned int __tlb_flag = __cpu_tlb_flags; - - if (tlb_flag(TLB_V7_UIS_BP)) - asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); - else if (tlb_flag(TLB_V6_BP)) - asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); - - if (tlb_flag(TLB_BARRIER)) - isb(); -} - /* * flush_pmd_entry * @@ -500,7 +480,6 @@ static inline void clean_pmd_entry(void *pmd) #define flush_tlb_kernel_page local_flush_tlb_kernel_page #define flush_tlb_range local_flush_tlb_range #define flush_tlb_kernel_range local_flush_tlb_kernel_range -#define flush_bp_all local_flush_bp_all #else extern void flush_tlb_all(void); extern void flush_tlb_mm(struct mm_struct *mm); @@ -508,7 +487,6 @@ extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr); extern void flush_tlb_kernel_page(unsigned long kaddr); extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); -extern void flush_bp_all(void); #endif /* diff --git a/trunk/arch/arm/include/asm/xen/events.h b/trunk/arch/arm/include/asm/xen/events.h index 8b1f37bfeeec..5c27696de14f 100644 --- a/trunk/arch/arm/include/asm/xen/events.h +++ b/trunk/arch/arm/include/asm/xen/events.h @@ -2,7 +2,6 @@ #define _ASM_ARM_XEN_EVENTS_H #include -#include enum ipi_vector { XEN_PLACEHOLDER_VECTOR, @@ -16,8 +15,26 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) return raw_irqs_disabled_flags(regs->ARM_cpsr); } -#define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr), \ - atomic64_t, \ - counter), (val)) +/* + * We cannot use xchg because it does not support 8-byte + * values. However it is safe to use {ldr,dtd}exd directly because all + * platforms which Xen can run on support those instructions. + */ +static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val) +{ + xen_ulong_t oldval; + unsigned int tmp; + + wmb(); + asm volatile("@ xchg_xen_ulong\n" + "1: ldrexd %0, %H0, [%3]\n" + " strexd %1, %2, %H2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (oldval), "=&r" (tmp) + : "r" (val), "r" (ptr) + : "memory", "cc"); + return oldval; +} #endif /* _ASM_ARM_XEN_EVENTS_H */ diff --git a/trunk/arch/arm/include/uapi/asm/unistd.h b/trunk/arch/arm/include/uapi/asm/unistd.h index af33b44990ed..4da7cde70b5d 100644 --- a/trunk/arch/arm/include/uapi/asm/unistd.h +++ b/trunk/arch/arm/include/uapi/asm/unistd.h @@ -404,7 +404,7 @@ #define __NR_setns (__NR_SYSCALL_BASE+375) #define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) #define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) -#define __NR_kcmp (__NR_SYSCALL_BASE+378) + /* 378 for kcmp */ #define __NR_finit_module (__NR_SYSCALL_BASE+379) /* diff --git a/trunk/arch/arm/kernel/asm-offsets.c b/trunk/arch/arm/kernel/asm-offsets.c index 923eec7105cf..5ce738b43508 100644 --- a/trunk/arch/arm/kernel/asm-offsets.c +++ b/trunk/arch/arm/kernel/asm-offsets.c @@ -110,7 +110,7 @@ int main(void) BLANK(); #endif #ifdef CONFIG_CPU_HAS_ASID - DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter)); + DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); BLANK(); #endif DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm)); diff --git a/trunk/arch/arm/kernel/calls.S b/trunk/arch/arm/kernel/calls.S index c6ca7e376773..0cc57611fc4f 100644 --- a/trunk/arch/arm/kernel/calls.S +++ b/trunk/arch/arm/kernel/calls.S @@ -387,7 +387,7 @@ /* 375 */ CALL(sys_setns) CALL(sys_process_vm_readv) CALL(sys_process_vm_writev) - CALL(sys_kcmp) + CALL(sys_ni_syscall) /* reserved for sys_kcmp */ CALL(sys_finit_module) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls diff --git a/trunk/arch/arm/kernel/entry-armv.S b/trunk/arch/arm/kernel/entry-armv.S index cd22d821bf74..0f82098c9bfe 100644 --- a/trunk/arch/arm/kernel/entry-armv.S +++ b/trunk/arch/arm/kernel/entry-armv.S @@ -562,21 +562,21 @@ ENDPROC(__und_usr) @ Fall-through from Thumb-2 __und_usr @ #ifdef CONFIG_NEON - get_thread_info r10 @ get current thread adr r6, .LCneon_thumb_opcodes b 2f #endif call_fpe: - get_thread_info r10 @ get current thread #ifdef CONFIG_NEON adr r6, .LCneon_arm_opcodes -2: ldr r5, [r6], #4 @ mask value - ldr r7, [r6], #4 @ opcode bits matching in mask - cmp r5, #0 @ end mask? +2: + ldr r7, [r6], #4 @ mask value + cmp r7, #0 @ end mask? beq 1f - and r8, r0, r5 + and r8, r0, r7 + ldr r7, [r6], #4 @ opcode bits matching in mask cmp r8, r7 @ NEON instruction? bne 2b + get_thread_info r10 mov r7, #1 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used @@ -586,6 +586,7 @@ call_fpe: tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 moveq pc, lr + get_thread_info r10 @ get current thread and r8, r0, #0x00000f00 @ mask out CP number THUMB( lsr r8, r8, #8 ) mov r7, #1 diff --git a/trunk/arch/arm/kernel/head.S b/trunk/arch/arm/kernel/head.S index e0eb9a1cae77..486a15ae9011 100644 --- a/trunk/arch/arm/kernel/head.S +++ b/trunk/arch/arm/kernel/head.S @@ -184,22 +184,13 @@ __create_page_tables: orr r3, r3, #3 @ PGD block type mov r6, #4 @ PTRS_PER_PGD mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER -1: -#ifdef CONFIG_CPU_ENDIAN_BE8 +1: str r3, [r0], #4 @ set bottom PGD entry bits str r7, [r0], #4 @ set top PGD entry bits - str r3, [r0], #4 @ set bottom PGD entry bits -#else - str r3, [r0], #4 @ set bottom PGD entry bits - str r7, [r0], #4 @ set top PGD entry bits -#endif add r3, r3, #0x1000 @ next PMD table subs r6, r6, #1 bne 1b add r4, r4, #0x1000 @ point to the PMD tables -#ifdef CONFIG_CPU_ENDIAN_BE8 - add r4, r4, #4 @ we only write the bottom word -#endif #endif ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags @@ -267,11 +258,6 @@ __create_page_tables: addne r6, r6, #1 << SECTION_SHIFT strne r6, [r3] -#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) - sub r4, r4, #4 @ Fixup page table pointer - @ for 64-bit descriptors -#endif - #ifdef CONFIG_DEBUG_LL #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING) /* @@ -290,16 +276,12 @@ __create_page_tables: orr r3, r7, r3, lsl #SECTION_SHIFT #ifdef CONFIG_ARM_LPAE mov r7, #1 << (54 - 32) @ XN -#ifdef CONFIG_CPU_ENDIAN_BE8 - str r7, [r0], #4 - str r3, [r0], #4 -#else - str r3, [r0], #4 - str r7, [r0], #4 -#endif #else orr r3, r3, #PMD_SECT_XN +#endif str r3, [r0], #4 +#ifdef CONFIG_ARM_LPAE + str r7, [r0], #4 #endif #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ diff --git a/trunk/arch/arm/kernel/hw_breakpoint.c b/trunk/arch/arm/kernel/hw_breakpoint.c index 96093b75ab90..5eae53e7a2e1 100644 --- a/trunk/arch/arm/kernel/hw_breakpoint.c +++ b/trunk/arch/arm/kernel/hw_breakpoint.c @@ -1023,7 +1023,7 @@ static void reset_ctrl_regs(void *unused) static int __cpuinit dbg_reset_notify(struct notifier_block *self, unsigned long action, void *cpu) { - if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE) + if (action == CPU_ONLINE) smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); return NOTIFY_OK; diff --git a/trunk/arch/arm/kernel/perf_event.c b/trunk/arch/arm/kernel/perf_event.c index 146157dfe27c..31e0eb353cd8 100644 --- a/trunk/arch/arm/kernel/perf_event.c +++ b/trunk/arch/arm/kernel/perf_event.c @@ -400,7 +400,7 @@ __hw_perf_event_init(struct perf_event *event) } if (event->group_leader != event) { - if (validate_group(event) != 0) + if (validate_group(event) != 0); return -EINVAL; } @@ -484,7 +484,7 @@ const struct dev_pm_ops armpmu_dev_pm_ops = { SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) }; -static void armpmu_init(struct arm_pmu *armpmu) +static void __init armpmu_init(struct arm_pmu *armpmu) { atomic_set(&armpmu->active_events, 0); mutex_init(&armpmu->reserve_mutex); diff --git a/trunk/arch/arm/kernel/perf_event_v7.c b/trunk/arch/arm/kernel/perf_event_v7.c index 039cffb053a7..8c79a9e70b83 100644 --- a/trunk/arch/arm/kernel/perf_event_v7.c +++ b/trunk/arch/arm/kernel/perf_event_v7.c @@ -774,7 +774,7 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] /* * PMXEVTYPER: Event selection reg */ -#define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */ +#define ARMV7_EVTYPE_MASK 0xc00000ff /* Mask for writable bits */ #define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ /* diff --git a/trunk/arch/arm/kernel/process.c b/trunk/arch/arm/kernel/process.c index cbd0f51937cc..047d3e40e470 100644 --- a/trunk/arch/arm/kernel/process.c +++ b/trunk/arch/arm/kernel/process.c @@ -459,16 +459,15 @@ unsigned long arch_randomize_brk(struct mm_struct *mm) * atomic helpers and the signal restart code. Insert it into the * gate_vma so that it is visible through ptrace and /proc//mem. */ -static struct vm_area_struct gate_vma = { - .vm_start = 0xffff0000, - .vm_end = 0xffff0000 + PAGE_SIZE, - .vm_flags = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC, - .vm_mm = &init_mm, -}; +static struct vm_area_struct gate_vma; static int __init gate_vma_init(void) { - gate_vma.vm_page_prot = PAGE_READONLY_EXEC; + gate_vma.vm_start = 0xffff0000; + gate_vma.vm_end = 0xffff0000 + PAGE_SIZE; + gate_vma.vm_page_prot = PAGE_READONLY_EXEC; + gate_vma.vm_flags = VM_READ | VM_EXEC | + VM_MAYREAD | VM_MAYEXEC; return 0; } arch_initcall(gate_vma_init); diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c index 79078edbb9bc..1bdfd87c8e41 100644 --- a/trunk/arch/arm/kernel/smp.c +++ b/trunk/arch/arm/kernel/smp.c @@ -285,7 +285,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void) * switch away from it before attempting any exclusive accesses. */ cpu_switch_mm(mm->pgd, mm); - local_flush_bp_all(); enter_lazy_tlb(mm, current); local_flush_tlb_all(); @@ -480,7 +479,7 @@ static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt) evt->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_DUMMY; - evt->rating = 100; + evt->rating = 400; evt->mult = 1; evt->set_mode = broadcast_timer_set_mode; diff --git a/trunk/arch/arm/kernel/smp_tlb.c b/trunk/arch/arm/kernel/smp_tlb.c index bd0300531399..02c5d2ce23bf 100644 --- a/trunk/arch/arm/kernel/smp_tlb.c +++ b/trunk/arch/arm/kernel/smp_tlb.c @@ -64,11 +64,6 @@ static inline void ipi_flush_tlb_kernel_range(void *arg) local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end); } -static inline void ipi_flush_bp_all(void *ignored) -{ - local_flush_bp_all(); -} - void flush_tlb_all(void) { if (tlb_ops_need_broadcast()) @@ -132,10 +127,3 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end) local_flush_tlb_kernel_range(start, end); } -void flush_bp_all(void) -{ - if (tlb_ops_need_broadcast()) - on_each_cpu(ipi_flush_bp_all, NULL, 1); - else - local_flush_bp_all(); -} diff --git a/trunk/arch/arm/kernel/smp_twd.c b/trunk/arch/arm/kernel/smp_twd.c index 90525d9d290b..c092115d903a 100644 --- a/trunk/arch/arm/kernel/smp_twd.c +++ b/trunk/arch/arm/kernel/smp_twd.c @@ -22,7 +22,6 @@ #include #include -#include #include #include @@ -362,11 +361,20 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt) } #ifdef CONFIG_OF -static void __init twd_local_timer_of_register(struct device_node *np) +const static struct of_device_id twd_of_match[] __initconst = { + { .compatible = "arm,cortex-a9-twd-timer", }, + { .compatible = "arm,cortex-a5-twd-timer", }, + { .compatible = "arm,arm11mp-twd-timer", }, + { }, +}; + +void __init twd_local_timer_of_register(void) { + struct device_node *np; int err; - if (!is_smp() || !setup_max_cpus) + np = of_find_matching_node(NULL, twd_of_match); + if (!np) return; twd_ppi = irq_of_parse_and_map(np, 0); @@ -386,7 +394,4 @@ static void __init twd_local_timer_of_register(struct device_node *np) out: WARN(err, "twd_local_timer_of_register failed (%d)\n", err); } -CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); -CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); -CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); #endif diff --git a/trunk/arch/arm/kernel/suspend.c b/trunk/arch/arm/kernel/suspend.c index c59c97ea8268..358bca3a995e 100644 --- a/trunk/arch/arm/kernel/suspend.c +++ b/trunk/arch/arm/kernel/suspend.c @@ -68,7 +68,6 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) ret = __cpu_suspend(arg, fn); if (ret == 0) { cpu_switch_mm(mm->pgd, mm); - local_flush_bp_all(); local_flush_tlb_all(); } diff --git a/trunk/arch/arm/lib/memset.S b/trunk/arch/arm/lib/memset.S index 94b0650ea98f..650d5923ab83 100644 --- a/trunk/arch/arm/lib/memset.S +++ b/trunk/arch/arm/lib/memset.S @@ -14,15 +14,27 @@ .text .align 5 + .word 0 + +1: subs r2, r2, #4 @ 1 do we have enough + blt 5f @ 1 bytes to align with? + cmp r3, #2 @ 1 + strltb r1, [r0], #1 @ 1 + strleb r1, [r0], #1 @ 1 + strb r1, [r0], #1 @ 1 + add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) +/* + * The pointer is now aligned and the length is adjusted. Try doing the + * memset again. + */ ENTRY(memset) ands r3, r0, #3 @ 1 unaligned? - mov ip, r0 @ preserve r0 as return value - bne 6f @ 1 + bne 1b @ 1 /* - * we know that the pointer in ip is aligned to a word boundary. + * we know that the pointer in r0 is aligned to a word boundary. */ -1: orr r1, r1, r1, lsl #8 + orr r1, r1, r1, lsl #8 orr r1, r1, r1, lsl #16 mov r3, r1 cmp r2, #16 @@ -31,28 +43,29 @@ ENTRY(memset) #if ! CALGN(1)+0 /* - * We need 2 extra registers for this loop - use r8 and the LR + * We need an extra register for this loop - save the return address and + * use the LR */ - stmfd sp!, {r8, lr} - mov r8, r1 + str lr, [sp, #-4]! + mov ip, r1 mov lr, r1 2: subs r2, r2, #64 - stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time. - stmgeia ip!, {r1, r3, r8, lr} - stmgeia ip!, {r1, r3, r8, lr} - stmgeia ip!, {r1, r3, r8, lr} + stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time. + stmgeia r0!, {r1, r3, ip, lr} + stmgeia r0!, {r1, r3, ip, lr} + stmgeia r0!, {r1, r3, ip, lr} bgt 2b - ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go. + ldmeqfd sp!, {pc} @ Now <64 bytes to go. /* * No need to correct the count; we're only testing bits from now on */ tst r2, #32 - stmneia ip!, {r1, r3, r8, lr} - stmneia ip!, {r1, r3, r8, lr} + stmneia r0!, {r1, r3, ip, lr} + stmneia r0!, {r1, r3, ip, lr} tst r2, #16 - stmneia ip!, {r1, r3, r8, lr} - ldmfd sp!, {r8, lr} + stmneia r0!, {r1, r3, ip, lr} + ldr lr, [sp], #4 #else @@ -61,63 +74,54 @@ ENTRY(memset) * whole cache lines at once. */ - stmfd sp!, {r4-r8, lr} + stmfd sp!, {r4-r7, lr} mov r4, r1 mov r5, r1 mov r6, r1 mov r7, r1 - mov r8, r1 + mov ip, r1 mov lr, r1 cmp r2, #96 - tstgt ip, #31 + tstgt r0, #31 ble 3f - and r8, ip, #31 - rsb r8, r8, #32 - sub r2, r2, r8 - movs r8, r8, lsl #(32 - 4) - stmcsia ip!, {r4, r5, r6, r7} - stmmiia ip!, {r4, r5} - tst r8, #(1 << 30) - mov r8, r1 - strne r1, [ip], #4 + and ip, r0, #31 + rsb ip, ip, #32 + sub r2, r2, ip + movs ip, ip, lsl #(32 - 4) + stmcsia r0!, {r4, r5, r6, r7} + stmmiia r0!, {r4, r5} + tst ip, #(1 << 30) + mov ip, r1 + strne r1, [r0], #4 3: subs r2, r2, #64 - stmgeia ip!, {r1, r3-r8, lr} - stmgeia ip!, {r1, r3-r8, lr} + stmgeia r0!, {r1, r3-r7, ip, lr} + stmgeia r0!, {r1, r3-r7, ip, lr} bgt 3b - ldmeqfd sp!, {r4-r8, pc} + ldmeqfd sp!, {r4-r7, pc} tst r2, #32 - stmneia ip!, {r1, r3-r8, lr} + stmneia r0!, {r1, r3-r7, ip, lr} tst r2, #16 - stmneia ip!, {r4-r7} - ldmfd sp!, {r4-r8, lr} + stmneia r0!, {r4-r7} + ldmfd sp!, {r4-r7, lr} #endif 4: tst r2, #8 - stmneia ip!, {r1, r3} + stmneia r0!, {r1, r3} tst r2, #4 - strne r1, [ip], #4 + strne r1, [r0], #4 /* * When we get here, we've got less than 4 bytes to zero. We * may have an unaligned pointer as well. */ 5: tst r2, #2 - strneb r1, [ip], #1 - strneb r1, [ip], #1 + strneb r1, [r0], #1 + strneb r1, [r0], #1 tst r2, #1 - strneb r1, [ip], #1 + strneb r1, [r0], #1 mov pc, lr - -6: subs r2, r2, #4 @ 1 do we have enough - blt 5b @ 1 bytes to align with? - cmp r3, #2 @ 1 - strltb r1, [ip], #1 @ 1 - strleb r1, [ip], #1 @ 1 - strb r1, [ip], #1 @ 1 - add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) - b 1b ENDPROC(memset) diff --git a/trunk/arch/arm/mach-at91/at91sam9261.c b/trunk/arch/arm/mach-at91/at91sam9261.c index 0204f4cc9ebf..2998a08afc2d 100644 --- a/trunk/arch/arm/mach-at91/at91sam9261.c +++ b/trunk/arch/arm/mach-at91/at91sam9261.c @@ -169,8 +169,6 @@ static struct clk *periph_clocks[] __initdata = { }; static struct clk_lookup periph_clocks_lookups[] = { - CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1), - CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), diff --git a/trunk/arch/arm/mach-at91/at91sam9261_devices.c b/trunk/arch/arm/mach-at91/at91sam9261_devices.c index 629ea5fc95cf..92e0f861084a 100644 --- a/trunk/arch/arm/mach-at91/at91sam9261_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9261_devices.c @@ -488,6 +488,7 @@ static struct resource lcdc_resources[] = { }; static struct platform_device at91_lcdc_device = { + .name = "atmel_lcdfb", .id = 0, .dev = { .dma_mask = &lcdc_dmamask, @@ -504,11 +505,6 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) return; } - if (cpu_is_at91sam9g10()) - at91_lcdc_device.name = "at91sam9g10-lcdfb"; - else - at91_lcdc_device.name = "at91sam9261-lcdfb"; - #if defined(CONFIG_FB_ATMEL_STN) at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */ at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ diff --git a/trunk/arch/arm/mach-at91/at91sam9263.c b/trunk/arch/arm/mach-at91/at91sam9263.c index 2282fd7ad3e3..b9fc60d1b33a 100644 --- a/trunk/arch/arm/mach-at91/at91sam9263.c +++ b/trunk/arch/arm/mach-at91/at91sam9263.c @@ -190,7 +190,6 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk), - CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), diff --git a/trunk/arch/arm/mach-at91/at91sam9263_devices.c b/trunk/arch/arm/mach-at91/at91sam9263_devices.c index 858c8aac2daf..ed666f5cb01d 100644 --- a/trunk/arch/arm/mach-at91/at91sam9263_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9263_devices.c @@ -848,7 +848,7 @@ static struct resource lcdc_resources[] = { }; static struct platform_device at91_lcdc_device = { - .name = "at91sam9263-lcdfb", + .name = "atmel_lcdfb", .id = 0, .dev = { .dma_mask = &lcdc_dmamask, diff --git a/trunk/arch/arm/mach-at91/at91sam9g45.c b/trunk/arch/arm/mach-at91/at91sam9g45.c index c68960d82247..d3addee43d8d 100644 --- a/trunk/arch/arm/mach-at91/at91sam9g45.c +++ b/trunk/arch/arm/mach-at91/at91sam9g45.c @@ -228,8 +228,6 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_ID("hclk", &macb_clk), /* One additional fake clock for ohci */ CLKDEV_CON_ID("ohci_clk", &uhphs_clk), - CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk), - CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk), CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), diff --git a/trunk/arch/arm/mach-at91/at91sam9g45_devices.c b/trunk/arch/arm/mach-at91/at91sam9g45_devices.c index fe626d431b69..827c9f2a70fb 100644 --- a/trunk/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9g45_devices.c @@ -981,6 +981,7 @@ static struct resource lcdc_resources[] = { }; static struct platform_device at91_lcdc_device = { + .name = "atmel_lcdfb", .id = 0, .dev = { .dma_mask = &lcdc_dmamask, @@ -996,11 +997,6 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) if (!data) return; - if (cpu_is_at91sam9g45es()) - at91_lcdc_device.name = "at91sam9g45es-lcdfb"; - else - at91_lcdc_device.name = "at91sam9g45-lcdfb"; - at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ diff --git a/trunk/arch/arm/mach-at91/at91sam9rl.c b/trunk/arch/arm/mach-at91/at91sam9rl.c index 3de3e04d0f81..eb98704db2d9 100644 --- a/trunk/arch/arm/mach-at91/at91sam9rl.c +++ b/trunk/arch/arm/mach-at91/at91sam9rl.c @@ -179,7 +179,6 @@ static struct clk *periph_clocks[] __initdata = { }; static struct clk_lookup periph_clocks_lookups[] = { - CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk), CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), diff --git a/trunk/arch/arm/mach-at91/at91sam9rl_devices.c b/trunk/arch/arm/mach-at91/at91sam9rl_devices.c index 352468f265a9..ddf223ff35c4 100644 --- a/trunk/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9rl_devices.c @@ -514,7 +514,7 @@ static struct resource lcdc_resources[] = { }; static struct platform_device at91_lcdc_device = { - .name = "at91sam9rl-lcdfb", + .name = "atmel_lcdfb", .id = 0, .dev = { .dma_mask = &lcdc_dmamask, diff --git a/trunk/arch/arm/mach-at91/board-foxg20.c b/trunk/arch/arm/mach-at91/board-foxg20.c index c20a870ea9c9..2ea7059b840b 100644 --- a/trunk/arch/arm/mach-at91/board-foxg20.c +++ b/trunk/arch/arm/mach-at91/board-foxg20.c @@ -176,7 +176,6 @@ static struct w1_gpio_platform_data w1_gpio_pdata = { /* If you choose to use a pin other than PB16 it needs to be 3.3V */ .pin = AT91_PIN_PB16, .is_open_drain = 1, - .ext_pullup_enable_pin = -EINVAL, }; static struct platform_device w1_device = { diff --git a/trunk/arch/arm/mach-at91/board-stamp9g20.c b/trunk/arch/arm/mach-at91/board-stamp9g20.c index 869cbecf00b7..a033b8df9fb2 100644 --- a/trunk/arch/arm/mach-at91/board-stamp9g20.c +++ b/trunk/arch/arm/mach-at91/board-stamp9g20.c @@ -188,7 +188,6 @@ static struct spi_board_info portuxg20_spi_devices[] = { static struct w1_gpio_platform_data w1_gpio_pdata = { .pin = AT91_PIN_PA29, .is_open_drain = 1, - .ext_pullup_enable_pin = -EINVAL, }; static struct platform_device w1_device = { diff --git a/trunk/arch/arm/mach-at91/include/mach/gpio.h b/trunk/arch/arm/mach-at91/include/mach/gpio.h index 5fc23771c154..eed465ab0dd7 100644 --- a/trunk/arch/arm/mach-at91/include/mach/gpio.h +++ b/trunk/arch/arm/mach-at91/include/mach/gpio.h @@ -209,14 +209,6 @@ extern int at91_get_gpio_value(unsigned pin); extern void at91_gpio_suspend(void); extern void at91_gpio_resume(void); -#ifdef CONFIG_PINCTRL_AT91 -extern void at91_pinctrl_gpio_suspend(void); -extern void at91_pinctrl_gpio_resume(void); -#else -static inline void at91_pinctrl_gpio_suspend(void) {} -static inline void at91_pinctrl_gpio_resume(void) {} -#endif - #endif /* __ASSEMBLY__ */ #endif diff --git a/trunk/arch/arm/mach-at91/irq.c b/trunk/arch/arm/mach-at91/irq.c index e0ca59171022..8e210262aeee 100644 --- a/trunk/arch/arm/mach-at91/irq.c +++ b/trunk/arch/arm/mach-at91/irq.c @@ -92,21 +92,23 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value) void at91_irq_suspend(void) { - int bit = -1; + int i = 0, bit; if (has_aic5()) { /* disable enabled irqs */ - while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) { + while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { at91_aic_write(AT91_AIC5_SSR, bit & AT91_AIC5_INTSEL_MSK); at91_aic_write(AT91_AIC5_IDCR, 1); + i = bit; } /* enable wakeup irqs */ - bit = -1; - while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) { + i = 0; + while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { at91_aic_write(AT91_AIC5_SSR, bit & AT91_AIC5_INTSEL_MSK); at91_aic_write(AT91_AIC5_IECR, 1); + i = bit; } } else { at91_aic_write(AT91_AIC_IDCR, *backups); @@ -116,21 +118,23 @@ void at91_irq_suspend(void) void at91_irq_resume(void) { - int bit = -1; + int i = 0, bit; if (has_aic5()) { /* disable wakeup irqs */ - while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) { + while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { at91_aic_write(AT91_AIC5_SSR, bit & AT91_AIC5_INTSEL_MSK); at91_aic_write(AT91_AIC5_IDCR, 1); + i = bit; } /* enable irqs disabled for suspend */ - bit = -1; - while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) { + i = 0; + while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { at91_aic_write(AT91_AIC5_SSR, bit & AT91_AIC5_INTSEL_MSK); at91_aic_write(AT91_AIC5_IECR, 1); + i = bit; } } else { at91_aic_write(AT91_AIC_IDCR, *wakeups); diff --git a/trunk/arch/arm/mach-at91/pm.c b/trunk/arch/arm/mach-at91/pm.c index 73f1f250403a..adb6db888a1f 100644 --- a/trunk/arch/arm/mach-at91/pm.c +++ b/trunk/arch/arm/mach-at91/pm.c @@ -201,10 +201,7 @@ extern u32 at91_slow_clock_sz; static int at91_pm_enter(suspend_state_t state) { - if (of_have_populated_dt()) - at91_pinctrl_gpio_suspend(); - else - at91_gpio_suspend(); + at91_gpio_suspend(); at91_irq_suspend(); pr_debug("AT91: PM - wake mask %08x, pm state %d\n", @@ -289,10 +286,7 @@ static int at91_pm_enter(suspend_state_t state) error: target_state = PM_SUSPEND_ON; at91_irq_resume(); - if (of_have_populated_dt()) - at91_pinctrl_gpio_resume(); - else - at91_gpio_resume(); + at91_gpio_resume(); return 0; } diff --git a/trunk/arch/arm/mach-davinci/dma.c b/trunk/arch/arm/mach-davinci/dma.c index 45b7c71d9cc1..a685e9706b7b 100644 --- a/trunk/arch/arm/mach-davinci/dma.c +++ b/trunk/arch/arm/mach-davinci/dma.c @@ -743,9 +743,6 @@ EXPORT_SYMBOL(edma_free_channel); */ int edma_alloc_slot(unsigned ctlr, int slot) { - if (!edma_cc[ctlr]) - return -EINVAL; - if (slot >= 0) slot = EDMA_CHAN_SLOT(slot); diff --git a/trunk/arch/arm/mach-exynos/Kconfig b/trunk/arch/arm/mach-exynos/Kconfig index faca4326b46a..70f94c87479d 100644 --- a/trunk/arch/arm/mach-exynos/Kconfig +++ b/trunk/arch/arm/mach-exynos/Kconfig @@ -79,6 +79,12 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support +config EXYNOS4_MCT + bool + default y + help + Use MCT (Multi Core Timer) as kernel timers + config EXYNOS_DEV_DMA bool help @@ -270,8 +276,8 @@ config MACH_UNIVERSAL_C210 select S5P_DEV_ONENAND select S5P_DEV_TV select S5P_GPIO_INT + select S5P_HRT select S5P_SETUP_MIPIPHY - select SAMSUNG_HRT help Machine support for Samsung Mobile Universal S5PC210 Reference Board. @@ -400,7 +406,6 @@ config MACH_EXYNOS4_DT bool "Samsung Exynos4 Machine using device tree" depends on ARCH_EXYNOS4 select ARM_AMBA - select CLKSRC_OF select CPU_EXYNOS4210 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD select PINCTRL @@ -417,7 +422,6 @@ config MACH_EXYNOS5_DT default y depends on ARCH_EXYNOS5 select ARM_AMBA - select CLKSRC_OF select USE_OF help Machine support for Samsung EXYNOS5 machine with device tree enabled. diff --git a/trunk/arch/arm/mach-exynos/Makefile b/trunk/arch/arm/mach-exynos/Makefile index daf289b21486..435757e57bb4 100644 --- a/trunk/arch/arm/mach-exynos/Makefile +++ b/trunk/arch/arm/mach-exynos/Makefile @@ -26,6 +26,8 @@ obj-$(CONFIG_ARCH_EXYNOS) += pmu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_EXYNOS4_MCT) += mct.o + obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o # machine support diff --git a/trunk/arch/arm/mach-exynos/common.c b/trunk/arch/arm/mach-exynos/common.c index db7dbd0eb6b4..d63d399c7bae 100644 --- a/trunk/arch/arm/mach-exynos/common.c +++ b/trunk/arch/arm/mach-exynos/common.c @@ -256,6 +256,11 @@ static struct map_desc exynos5_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSTIMER, + .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER), + .length = SZ_4K, + .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_SYSRAM, .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), @@ -817,7 +822,6 @@ static int __init exynos_init_irq_eint(void) static const struct of_device_id exynos_pinctrl_ids[] = { { .compatible = "samsung,exynos4210-pinctrl", }, { .compatible = "samsung,exynos4x12-pinctrl", }, - { .compatible = "samsung,exynos5250-pinctrl", }, }; struct device_node *pctrl_np, *wkup_np; const char *wkup_compat = "samsung,exynos4210-wakeup-eint"; diff --git a/trunk/arch/arm/mach-exynos/common.h b/trunk/arch/arm/mach-exynos/common.h index 3b186eaaaa7b..9339bb8954be 100644 --- a/trunk/arch/arm/mach-exynos/common.h +++ b/trunk/arch/arm/mach-exynos/common.h @@ -12,7 +12,7 @@ #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H #define __ARCH_ARM_MACH_EXYNOS_COMMON_H -extern void mct_init(void); +extern void exynos4_timer_init(void); struct map_desc; void exynos_init_io(struct map_desc *mach_desc, int size); diff --git a/trunk/arch/arm/mach-exynos/include/mach/irqs.h b/trunk/arch/arm/mach-exynos/include/mach/irqs.h index c0e75d8dd737..1f4dc35cd4b9 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/irqs.h +++ b/trunk/arch/arm/mach-exynos/include/mach/irqs.h @@ -30,6 +30,8 @@ /* For EXYNOS4 and EXYNOS5 */ +#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12) + #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) /* For EXYNOS4 SoCs */ @@ -321,6 +323,8 @@ #define EXYNOS5_IRQ_CEC IRQ_SPI(114) #define EXYNOS5_IRQ_SATA IRQ_SPI(115) +#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120) +#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121) #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) @@ -415,6 +419,8 @@ #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) +#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) +#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) diff --git a/trunk/arch/arm/mach-exynos/include/mach/map.h b/trunk/arch/arm/mach-exynos/include/mach/map.h index 7f99b7b187d6..1df6abbf53b8 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/map.h +++ b/trunk/arch/arm/mach-exynos/include/mach/map.h @@ -65,6 +65,7 @@ #define EXYNOS5_PA_CMU 0x10010000 #define EXYNOS4_PA_SYSTIMER 0x10050000 +#define EXYNOS5_PA_SYSTIMER 0x101C0000 #define EXYNOS4_PA_WATCHDOG 0x10060000 #define EXYNOS5_PA_WATCHDOG 0x101D0000 diff --git a/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h b/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h new file mode 100644 index 000000000000..80dd02ad6d61 --- /dev/null +++ b/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h @@ -0,0 +1,53 @@ +/* arch/arm/mach-exynos4/include/mach/regs-mct.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 MCT configutation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_MCT_H +#define __ASM_ARCH_REGS_MCT_H __FILE__ + +#include + +#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x)) + +#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) +#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) +#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) + +#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) +#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) +#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) + +#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) + +#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) +#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) +#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) + +#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) +#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) +#define EXYNOS4_MCT_L_MASK (0xffffff00) + +#define MCT_L_TCNTB_OFFSET (0x00) +#define MCT_L_ICNTB_OFFSET (0x08) +#define MCT_L_TCON_OFFSET (0x20) +#define MCT_L_INT_CSTAT_OFFSET (0x30) +#define MCT_L_INT_ENB_OFFSET (0x34) +#define MCT_L_WSTAT_OFFSET (0x40) + +#define MCT_G_TCON_START (1 << 8) +#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) +#define MCT_G_TCON_COMP0_ENABLE (1 << 0) + +#define MCT_L_TCON_INTERVAL_MODE (1 << 2) +#define MCT_L_TCON_INT_START (1 << 1) +#define MCT_L_TCON_TIMER_START (1 << 0) + +#endif /* __ASM_ARCH_REGS_MCT_H */ diff --git a/trunk/arch/arm/mach-exynos/mach-armlex4210.c b/trunk/arch/arm/mach-exynos/mach-armlex4210.c index 3b1a34742679..685f29173afa 100644 --- a/trunk/arch/arm/mach-exynos/mach-armlex4210.c +++ b/trunk/arch/arm/mach-exynos/mach-armlex4210.c @@ -202,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210") .map_io = armlex4210_map_io, .init_machine = armlex4210_machine_init, .init_late = exynos_init_late, - .init_time = mct_init, + .init_time = exynos4_timer_init, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c index c4ae108e192d..3358088c822a 100644 --- a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -13,7 +13,6 @@ #include #include -#include #include #include @@ -143,7 +142,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") .map_io = exynos4_dt_map_io, .init_machine = exynos4_dt_machine_init, .init_late = exynos_init_late, - .init_time = clocksource_of_init, + .init_time = exynos4_timer_init, .dt_compat = exynos4_dt_compat, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c index 7da4791bfb8b..acaeb14db54b 100644 --- a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include @@ -217,7 +216,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") .map_io = exynos5_dt_map_io, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, - .init_time = clocksource_of_init, + .init_time = exynos4_timer_init, .dt_compat = exynos5_dt_compat, .restart = exynos5_restart, .reserve = exynos5_reserve, diff --git a/trunk/arch/arm/mach-exynos/mach-nuri.c b/trunk/arch/arm/mach-exynos/mach-nuri.c index da3605d15110..1ea79730187f 100644 --- a/trunk/arch/arm/mach-exynos/mach-nuri.c +++ b/trunk/arch/arm/mach-exynos/mach-nuri.c @@ -1380,7 +1380,7 @@ MACHINE_START(NURI, "NURI") .map_io = nuri_map_io, .init_machine = nuri_machine_init, .init_late = exynos_init_late, - .init_time = mct_init, + .init_time = exynos4_timer_init, .reserve = &nuri_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-origen.c b/trunk/arch/arm/mach-exynos/mach-origen.c index 1772cd284f4c..579d2d171daa 100644 --- a/trunk/arch/arm/mach-exynos/mach-origen.c +++ b/trunk/arch/arm/mach-exynos/mach-origen.c @@ -815,7 +815,7 @@ MACHINE_START(ORIGEN, "ORIGEN") .map_io = origen_map_io, .init_machine = origen_machine_init, .init_late = exynos_init_late, - .init_time = mct_init, + .init_time = exynos4_timer_init, .reserve = &origen_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c index 34a6356364eb..fe6149624b84 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c @@ -376,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212") .init_irq = exynos4_init_irq, .map_io = smdk4x12_map_io, .init_machine = smdk4x12_machine_init, - .init_time = mct_init, + .init_time = exynos4_timer_init, .restart = exynos4_restart, .reserve = &smdk4x12_reserve, MACHINE_END @@ -390,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412") .map_io = smdk4x12_map_io, .init_machine = smdk4x12_machine_init, .init_late = exynos_init_late, - .init_time = mct_init, + .init_time = exynos4_timer_init, .restart = exynos4_restart, .reserve = &smdk4x12_reserve, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-smdkv310.c b/trunk/arch/arm/mach-exynos/mach-smdkv310.c index 893b14e8c62a..d71672922b19 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdkv310.c +++ b/trunk/arch/arm/mach-exynos/mach-smdkv310.c @@ -423,7 +423,7 @@ MACHINE_START(SMDKV310, "SMDKV310") .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, - .init_time = mct_init, + .init_time = exynos4_timer_init, .reserve = &smdkv310_reserve, .restart = exynos4_restart, MACHINE_END @@ -436,7 +436,7 @@ MACHINE_START(SMDKC210, "SMDKC210") .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, .init_late = exynos_init_late, - .init_time = mct_init, + .init_time = exynos4_timer_init, .reserve = &smdkv310_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-universal_c210.c b/trunk/arch/arm/mach-exynos/mach-universal_c210.c index c870b0aaa5e0..497fcb793dc1 100644 --- a/trunk/arch/arm/mach-exynos/mach-universal_c210.c +++ b/trunk/arch/arm/mach-exynos/mach-universal_c210.c @@ -41,7 +41,7 @@ #include #include #include -#include +#include #include #include @@ -1094,7 +1094,7 @@ static void __init universal_map_io(void) exynos_init_io(NULL, 0); s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4); + s5p_set_timer_source(S5P_PWM2, S5P_PWM4); } static void s5p_tv_setup(void) @@ -1152,7 +1152,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") .map_io = universal_map_io, .init_machine = universal_machine_init, .init_late = exynos_init_late, - .init_time = samsung_timer_init, + .init_time = s5p_timer_init, .reserve = &universal_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/drivers/clocksource/exynos_mct.c b/trunk/arch/arm/mach-exynos/mct.c similarity index 67% rename from trunk/drivers/clocksource/exynos_mct.c rename to trunk/arch/arm/mach-exynos/mct.c index 957af8636c9d..c9d6650f9b5d 100644 --- a/trunk/drivers/clocksource/exynos_mct.c +++ b/trunk/arch/arm/mach-exynos/mct.c @@ -20,9 +20,6 @@ #include #include #include -#include -#include -#include #include #include @@ -31,36 +28,9 @@ #include #include +#include #include -#define EXYNOS4_MCTREG(x) (x) -#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) -#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) -#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) -#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) -#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) -#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) -#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) -#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) -#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) -#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) -#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) -#define EXYNOS4_MCT_L_MASK (0xffffff00) - -#define MCT_L_TCNTB_OFFSET (0x00) -#define MCT_L_ICNTB_OFFSET (0x08) -#define MCT_L_TCON_OFFSET (0x20) -#define MCT_L_INT_CSTAT_OFFSET (0x30) -#define MCT_L_INT_ENB_OFFSET (0x34) -#define MCT_L_WSTAT_OFFSET (0x40) -#define MCT_G_TCON_START (1 << 8) -#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) -#define MCT_G_TCON_COMP0_ENABLE (1 << 0) -#define MCT_L_TCON_INTERVAL_MODE (1 << 2) -#define MCT_L_TCON_INT_START (1 << 1) -#define MCT_L_TCON_TIMER_START (1 << 0) - #define TICK_BASE_CNT 1 enum { @@ -68,75 +38,64 @@ enum { MCT_INT_PPI }; -enum { - MCT_G0_IRQ, - MCT_G1_IRQ, - MCT_G2_IRQ, - MCT_G3_IRQ, - MCT_L0_IRQ, - MCT_L1_IRQ, - MCT_L2_IRQ, - MCT_L3_IRQ, - MCT_NR_IRQS, -}; - -static void __iomem *reg_base; static unsigned long clk_rate; static unsigned int mct_int_type; -static int mct_irqs[MCT_NR_IRQS]; struct mct_clock_event_device { struct clock_event_device *evt; - unsigned long base; + void __iomem *base; char name[10]; }; -static void exynos4_mct_write(unsigned int value, unsigned long offset) +static void exynos4_mct_write(unsigned int value, void *addr) { - unsigned long stat_addr; + void __iomem *stat_addr; u32 mask; u32 i; - __raw_writel(value, reg_base + offset); + __raw_writel(value, addr); - if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { - stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; - switch (offset & EXYNOS4_MCT_L_MASK) { - case MCT_L_TCON_OFFSET: + if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) { + u32 base = (u32) addr & EXYNOS4_MCT_L_MASK; + switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) { + case (u32) MCT_L_TCON_OFFSET: + stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; mask = 1 << 3; /* L_TCON write status */ break; - case MCT_L_ICNTB_OFFSET: + case (u32) MCT_L_ICNTB_OFFSET: + stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; mask = 1 << 1; /* L_ICNTB write status */ break; - case MCT_L_TCNTB_OFFSET: + case (u32) MCT_L_TCNTB_OFFSET: + stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; mask = 1 << 0; /* L_TCNTB write status */ break; default: return; } } else { - switch (offset) { - case EXYNOS4_MCT_G_TCON: + switch ((u32) addr) { + case (u32) EXYNOS4_MCT_G_TCON: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 16; /* G_TCON write status */ break; - case EXYNOS4_MCT_G_COMP0_L: + case (u32) EXYNOS4_MCT_G_COMP0_L: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 0; /* G_COMP0_L write status */ break; - case EXYNOS4_MCT_G_COMP0_U: + case (u32) EXYNOS4_MCT_G_COMP0_U: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 1; /* G_COMP0_U write status */ break; - case EXYNOS4_MCT_G_COMP0_ADD_INCR: + case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ break; - case EXYNOS4_MCT_G_CNT_L: + case (u32) EXYNOS4_MCT_G_CNT_L: stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; mask = 1 << 0; /* G_CNT_L write status */ break; - case EXYNOS4_MCT_G_CNT_U: + case (u32) EXYNOS4_MCT_G_CNT_U: stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; mask = 1 << 1; /* G_CNT_U write status */ break; @@ -147,12 +106,12 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset) /* Wait maximum 1 ms until written values are applied */ for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) - if (__raw_readl(reg_base + stat_addr) & mask) { - __raw_writel(mask, reg_base + stat_addr); + if (__raw_readl(stat_addr) & mask) { + __raw_writel(mask, stat_addr); return; } - panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); + panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr); } /* Clocksource handling */ @@ -163,7 +122,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo) exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); - reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); + reg = __raw_readl(EXYNOS4_MCT_G_TCON); reg |= MCT_G_TCON_START; exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); } @@ -171,12 +130,12 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo) static cycle_t exynos4_frc_read(struct clocksource *cs) { unsigned int lo, hi; - u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); + u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U); do { hi = hi2; - lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L); - hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); + lo = __raw_readl(EXYNOS4_MCT_G_CNT_L); + hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U); } while (hi != hi2); return ((cycle_t)hi << 32) | lo; @@ -208,7 +167,7 @@ static void exynos4_mct_comp0_stop(void) { unsigned int tcon; - tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); + tcon = __raw_readl(EXYNOS4_MCT_G_TCON); tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); @@ -221,7 +180,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode, unsigned int tcon; cycle_t comp_cycle; - tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); + tcon = __raw_readl(EXYNOS4_MCT_G_TCON); if (mode == CLOCK_EVT_MODE_PERIODIC) { tcon |= MCT_G_TCON_COMP0_AUTO_INC; @@ -298,7 +257,11 @@ static void exynos4_clockevent_init(void) mct_comp_device.cpumask = cpumask_of(0); clockevents_config_and_register(&mct_comp_device, clk_rate, 0xf, 0xffffffff); - setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); + + if (soc_is_exynos5250()) + setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq); + else + setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq); } #ifdef CONFIG_LOCAL_TIMERS @@ -310,12 +273,12 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) { unsigned long tmp; unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; - unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; + void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET; - tmp = __raw_readl(reg_base + offset); + tmp = __raw_readl(addr); if (tmp & mask) { tmp &= ~mask; - exynos4_mct_write(tmp, offset); + exynos4_mct_write(tmp, addr); } } @@ -334,7 +297,7 @@ static void exynos4_mct_tick_start(unsigned long cycles, /* enable MCT tick interrupt */ exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); - tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET); + tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET); tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | MCT_L_TCON_INTERVAL_MODE; exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); @@ -386,7 +349,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) exynos4_mct_tick_stop(mevt); /* Clear the MCT tick interrupt */ - if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { + if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); return 1; } else { @@ -422,6 +385,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) { struct mct_clock_event_device *mevt; unsigned int cpu = smp_processor_id(); + int mct_lx_irq; mevt = this_cpu_ptr(&percpu_mct_tick); mevt->evt = evt; @@ -442,17 +406,21 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) if (mct_int_type == MCT_INT_SPI) { if (cpu == 0) { + mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 : + EXYNOS5_IRQ_MCT_L0; mct_tick0_event_irq.dev_id = mevt; - evt->irq = mct_irqs[MCT_L0_IRQ]; - setup_irq(evt->irq, &mct_tick0_event_irq); + evt->irq = mct_lx_irq; + setup_irq(mct_lx_irq, &mct_tick0_event_irq); } else { + mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 : + EXYNOS5_IRQ_MCT_L1; mct_tick1_event_irq.dev_id = mevt; - evt->irq = mct_irqs[MCT_L1_IRQ]; - setup_irq(evt->irq, &mct_tick1_event_irq); - irq_set_affinity(evt->irq, cpumask_of(1)); + evt->irq = mct_lx_irq; + setup_irq(mct_lx_irq, &mct_tick1_event_irq); + irq_set_affinity(mct_lx_irq, cpumask_of(1)); } } else { - enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); + enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0); } return 0; @@ -468,7 +436,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt) else remove_irq(evt->irq, &mct_tick1_event_irq); else - disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); + disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER); } static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { @@ -477,80 +445,41 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { }; #endif /* CONFIG_LOCAL_TIMERS */ -static void __init exynos4_timer_resources(void __iomem *base) +static void __init exynos4_timer_resources(void) { struct clk *mct_clk; mct_clk = clk_get(NULL, "xtal"); clk_rate = clk_get_rate(mct_clk); - reg_base = base; - if (!reg_base) - panic("%s: unable to ioremap mct address space\n", __func__); - #ifdef CONFIG_LOCAL_TIMERS if (mct_int_type == MCT_INT_PPI) { int err; - err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], + err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, exynos4_mct_tick_isr, "MCT", &percpu_mct_tick); WARN(err, "MCT: can't request IRQ %d (%d)\n", - mct_irqs[MCT_L0_IRQ], err); + EXYNOS_IRQ_MCT_LOCALTIMER, err); } local_timer_register(&exynos4_mct_tick_ops); #endif /* CONFIG_LOCAL_TIMERS */ } -void __init mct_init(void) +void __init exynos4_timer_init(void) { - if (soc_is_exynos4210()) { - mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0; - mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0; - mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1; - mct_int_type = MCT_INT_SPI; - } else { - panic("unable to determine mct controller type\n"); + if (soc_is_exynos5440()) { + arch_timer_of_register(); + return; } - exynos4_timer_resources(S5P_VA_SYSTIMER); - exynos4_clocksource_init(); - exynos4_clockevent_init(); -} - -static void __init mct_init_dt(struct device_node *np, unsigned int int_type) -{ - u32 nr_irqs, i; - - mct_int_type = int_type; - - /* This driver uses only one global timer interrupt */ - mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); - - /* - * Find out the number of local irqs specified. The local - * timer irqs are specified after the four global timer - * irqs are specified. - */ - nr_irqs = of_irq_count(np); - for (i = MCT_L0_IRQ; i < nr_irqs; i++) - mct_irqs[i] = irq_of_parse_and_map(np, i); + if ((soc_is_exynos4210()) || (soc_is_exynos5250())) + mct_int_type = MCT_INT_SPI; + else + mct_int_type = MCT_INT_PPI; - exynos4_timer_resources(of_iomap(np, 0)); + exynos4_timer_resources(); exynos4_clocksource_init(); exynos4_clockevent_init(); } - - -static void __init mct_init_spi(struct device_node *np) -{ - return mct_init_dt(np, MCT_INT_SPI); -} - -static void __init mct_init_ppi(struct device_node *np) -{ - return mct_init_dt(np, MCT_INT_PPI); -} -CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); -CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); diff --git a/trunk/arch/arm/mach-footbridge/Kconfig b/trunk/arch/arm/mach-footbridge/Kconfig index 0f2111a11315..abda5a18a664 100644 --- a/trunk/arch/arm/mach-footbridge/Kconfig +++ b/trunk/arch/arm/mach-footbridge/Kconfig @@ -67,7 +67,6 @@ config ARCH_NETWINDER select ISA select ISA_DMA select PCI - select VIRT_TO_BUS help Say Y here if you intend to run this kernel on the Rebel.COM NetWinder. Information about this machine can be found at: diff --git a/trunk/arch/arm/mach-highbank/highbank.c b/trunk/arch/arm/mach-highbank/highbank.c index 76c1170b3528..a4f9f50247d4 100644 --- a/trunk/arch/arm/mach-highbank/highbank.c +++ b/trunk/arch/arm/mach-highbank/highbank.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -118,10 +119,10 @@ static void __init highbank_timer_init(void) sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); sp804_clockevents_init(timer_base, irq, "timer0"); + twd_local_timer_of_register(); + arch_timer_of_register(); arch_timer_sched_clock_init(); - - clocksource_of_init(); } static void highbank_power_off(void) diff --git a/trunk/arch/arm/mach-imx/clk-busy.c b/trunk/arch/arm/mach-imx/clk-busy.c index 85b728cc27ab..1ab91b5209e6 100644 --- a/trunk/arch/arm/mach-imx/clk-busy.c +++ b/trunk/arch/arm/mach-imx/clk-busy.c @@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, busy->mux.reg = reg; busy->mux.shift = shift; - busy->mux.mask = BIT(width) - 1; + busy->mux.width = width; busy->mux.lock = &imx_ccm_lock; busy->mux_ops = &clk_mux_ops; diff --git a/trunk/arch/arm/mach-imx/clk-imx35.c b/trunk/arch/arm/mach-imx/clk-imx35.c index e13a8fa5e62c..74e3a34d78b8 100644 --- a/trunk/arch/arm/mach-imx/clk-imx35.c +++ b/trunk/arch/arm/mach-imx/clk-imx35.c @@ -264,7 +264,6 @@ int __init mx35_clocks_init(void) clk_prepare_enable(clk[gpio3_gate]); clk_prepare_enable(clk[iim_gate]); clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[max_gate]); /* * SCC is needed to boot via mmc after a watchdog reset. The clock code diff --git a/trunk/arch/arm/mach-imx/clk-imx6q.c b/trunk/arch/arm/mach-imx/clk-imx6q.c index 2f9ff93a4e61..7b025ee528a5 100644 --- a/trunk/arch/arm/mach-imx/clk-imx6q.c +++ b/trunk/arch/arm/mach-imx/clk-imx6q.c @@ -172,7 +172,7 @@ static struct clk *clk[clk_max]; static struct clk_onecell_data clk_data; static enum mx6q_clks const clks_init_on[] __initconst = { - mmdc_ch0_axi, rom, pll1_sys, + mmdc_ch0_axi, rom, }; static struct clk_div_table clk_enet_ref_table[] = { diff --git a/trunk/arch/arm/mach-imx/headsmp.S b/trunk/arch/arm/mach-imx/headsmp.S index a58c8b0527cc..921fc1555854 100644 --- a/trunk/arch/arm/mach-imx/headsmp.S +++ b/trunk/arch/arm/mach-imx/headsmp.S @@ -26,16 +26,16 @@ ENDPROC(v7_secondary_startup) #ifdef CONFIG_PM /* - * The following code must assume it is running from physical address - * where absolute virtual addresses to the data section have to be - * turned into relative ones. + * The following code is located into the .data section. This is to + * allow phys_l2x0_saved_regs to be accessed with a relative load + * as we are running on physical address here. */ + .data + .align #ifdef CONFIG_CACHE_L2X0 .macro pl310_resume - adr r0, l2x0_saved_regs_offset - ldr r2, [r0] - add r2, r2, r0 + ldr r2, phys_l2x0_saved_regs ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl @@ -43,9 +43,9 @@ ENDPROC(v7_secondary_startup) str r1, [r0, #L2X0_CTRL] @ re-enable L2 .endm -l2x0_saved_regs_offset: - .word l2x0_saved_regs - . - + .globl phys_l2x0_saved_regs +phys_l2x0_saved_regs: + .long 0 #else .macro pl310_resume .endm diff --git a/trunk/arch/arm/mach-imx/imx25-dt.c b/trunk/arch/arm/mach-imx/imx25-dt.c index 82348391582a..03b65e5ea541 100644 --- a/trunk/arch/arm/mach-imx/imx25-dt.c +++ b/trunk/arch/arm/mach-imx/imx25-dt.c @@ -27,11 +27,6 @@ static const char * const imx25_dt_board_compat[] __initconst = { NULL }; -static void __init imx25_timer_init(void) -{ - mx25_clocks_init_dt(); -} - DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") .map_io = mx25_map_io, .init_early = imx25_init_early, diff --git a/trunk/arch/arm/mach-imx/mach-imx6q.c b/trunk/arch/arm/mach-imx/mach-imx6q.c index b59ddcb57c78..9ffd103b27e4 100644 --- a/trunk/arch/arm/mach-imx/mach-imx6q.c +++ b/trunk/arch/arm/mach-imx/mach-imx6q.c @@ -12,7 +12,6 @@ #include #include -#include #include #include #include @@ -29,9 +28,11 @@ #include #include #include +#include #include #include #include +#include #include #include "common.h" @@ -291,7 +292,7 @@ static void __init imx6q_init_irq(void) static void __init imx6q_timer_init(void) { mx6q_clocks_init(); - clocksource_of_init(); + twd_local_timer_of_register(); imx_print_silicon_rev("i.MX6Q", imx6q_revision()); } diff --git a/trunk/arch/arm/mach-imx/pm-imx6q.c b/trunk/arch/arm/mach-imx/pm-imx6q.c index 5faba7a3c95f..ee42d20cba19 100644 --- a/trunk/arch/arm/mach-imx/pm-imx6q.c +++ b/trunk/arch/arm/mach-imx/pm-imx6q.c @@ -22,6 +22,8 @@ #include "common.h" #include "hardware.h" +extern unsigned long phys_l2x0_saved_regs; + static int imx6q_suspend_finish(unsigned long val) { cpu_do_idle(); @@ -55,5 +57,18 @@ static const struct platform_suspend_ops imx6q_pm_ops = { void __init imx6q_pm_init(void) { + /* + * The l2x0 core code provides an infrastucture to save and restore + * l2x0 registers across suspend/resume cycle. But because imx6q + * retains L2 content during suspend and needs to resume L2 before + * MMU is enabled, it can only utilize register saving support and + * have to take care of restoring on its own. So we save physical + * address of the data structure used by l2x0 core to save registers, + * and later restore the necessary ones in imx6q resume entry. + */ +#ifdef CONFIG_CACHE_L2X0 + phys_l2x0_saved_regs = __pa(&l2x0_saved_regs); +#endif + suspend_set_ops(&imx6q_pm_ops); } diff --git a/trunk/arch/arm/mach-integrator/integrator_ap.c b/trunk/arch/arm/mach-integrator/integrator_ap.c index b23c8e4f28e8..ea961445e0e9 100644 --- a/trunk/arch/arm/mach-integrator/integrator_ap.c +++ b/trunk/arch/arm/mach-integrator/integrator_ap.c @@ -536,14 +536,16 @@ static void __init ap_init_of(void) 'A' + (ap_sc_id & 0x0f)); soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { + if (IS_ERR_OR_NULL(soc_dev)) { kfree(soc_dev_attr->revision); kfree(soc_dev_attr); return; } parent = soc_device_to_device(soc_dev); - integrator_init_sysfs(parent, ap_sc_id); + + if (!IS_ERR_OR_NULL(parent)) + integrator_init_sysfs(parent, ap_sc_id); of_platform_populate(root, of_default_bus_match_table, ap_auxdata_lookup, parent); diff --git a/trunk/arch/arm/mach-integrator/integrator_cp.c b/trunk/arch/arm/mach-integrator/integrator_cp.c index da1091be0887..2b0db82a5381 100644 --- a/trunk/arch/arm/mach-integrator/integrator_cp.c +++ b/trunk/arch/arm/mach-integrator/integrator_cp.c @@ -360,14 +360,17 @@ static void __init intcp_init_of(void) 'A' + (intcp_sc_id & 0x0f)); soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { + if (IS_ERR_OR_NULL(soc_dev)) { kfree(soc_dev_attr->revision); kfree(soc_dev_attr); return; } parent = soc_device_to_device(soc_dev); - integrator_init_sysfs(parent, intcp_sc_id); + + if (!IS_ERR_OR_NULL(parent)) + integrator_init_sysfs(parent, intcp_sc_id); + of_platform_populate(root, of_default_bus_match_table, intcp_auxdata_lookup, parent); } diff --git a/trunk/arch/arm/mach-ixp4xx/vulcan-setup.c b/trunk/arch/arm/mach-ixp4xx/vulcan-setup.c index d599e354ca57..d42730a1d4ab 100644 --- a/trunk/arch/arm/mach-ixp4xx/vulcan-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/vulcan-setup.c @@ -163,7 +163,6 @@ static struct platform_device vulcan_max6369 = { static struct w1_gpio_platform_data vulcan_w1_gpio_pdata = { .pin = 14, - .ext_pullup_enable_pin = -EINVAL, }; static struct platform_device vulcan_w1_gpio = { diff --git a/trunk/arch/arm/mach-kirkwood/board-dt.c b/trunk/arch/arm/mach-kirkwood/board-dt.c index d367aa6b47bb..2e73e9d53f70 100644 --- a/trunk/arch/arm/mach-kirkwood/board-dt.c +++ b/trunk/arch/arm/mach-kirkwood/board-dt.c @@ -41,12 +41,16 @@ static void __init kirkwood_legacy_clk_init(void) struct device_node *np = of_find_compatible_node( NULL, NULL, "marvell,kirkwood-gating-clock"); + struct of_phandle_args clkspec; - struct clk *clk; clkspec.np = np; clkspec.args_count = 1; + clkspec.args[0] = CGC_BIT_GE0; + orion_clkdev_add(NULL, "mv643xx_eth_port.0", + of_clk_get_from_provider(&clkspec)); + clkspec.args[0] = CGC_BIT_PEX0; orion_clkdev_add("0", "pcie", of_clk_get_from_provider(&clkspec)); @@ -55,24 +59,9 @@ static void __init kirkwood_legacy_clk_init(void) orion_clkdev_add("1", "pcie", of_clk_get_from_provider(&clkspec)); - clkspec.args[0] = CGC_BIT_SDIO; - orion_clkdev_add(NULL, "mvsdio", - of_clk_get_from_provider(&clkspec)); - - /* - * The ethernet interfaces forget the MAC address assigned by - * u-boot if the clocks are turned off. Until proper DT support - * is available we always enable them for now. - */ - clkspec.args[0] = CGC_BIT_GE0; - clk = of_clk_get_from_provider(&clkspec); - orion_clkdev_add(NULL, "mv643xx_eth_port.0", clk); - clk_prepare_enable(clk); - clkspec.args[0] = CGC_BIT_GE1; - clk = of_clk_get_from_provider(&clkspec); - orion_clkdev_add(NULL, "mv643xx_eth_port.1", clk); - clk_prepare_enable(clk); + orion_clkdev_add(NULL, "mv643xx_eth_port.1", + of_clk_get_from_provider(&clkspec)); } static void __init kirkwood_of_clk_init(void) diff --git a/trunk/arch/arm/mach-mmp/gplugd.c b/trunk/arch/arm/mach-mmp/gplugd.c index f62b68d926f4..d1e2d595e79c 100644 --- a/trunk/arch/arm/mach-mmp/gplugd.c +++ b/trunk/arch/arm/mach-mmp/gplugd.c @@ -9,7 +9,6 @@ */ #include -#include #include #include diff --git a/trunk/arch/arm/mach-mxs/icoll.c b/trunk/arch/arm/mach-mxs/icoll.c index e26eeba46598..8fb23af154b3 100644 --- a/trunk/arch/arm/mach-mxs/icoll.c +++ b/trunk/arch/arm/mach-mxs/icoll.c @@ -100,7 +100,7 @@ static struct irq_domain_ops icoll_irq_domain_ops = { .xlate = irq_domain_xlate_onecell, }; -static void __init icoll_of_init(struct device_node *np, +void __init icoll_of_init(struct device_node *np, struct device_node *interrupt_parent) { /* diff --git a/trunk/arch/arm/mach-mxs/mach-mxs.c b/trunk/arch/arm/mach-mxs/mach-mxs.c index e7b781d3788f..052186713347 100644 --- a/trunk/arch/arm/mach-mxs/mach-mxs.c +++ b/trunk/arch/arm/mach-mxs/mach-mxs.c @@ -41,6 +41,8 @@ static struct fb_videomode mx23evk_video_modes[] = { .lower_margin = 4, .hsync_len = 1, .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, }, }; @@ -57,6 +59,8 @@ static struct fb_videomode mx28evk_video_modes[] = { .lower_margin = 10, .hsync_len = 10, .vsync_len = 10, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, }, }; @@ -73,6 +77,7 @@ static struct fb_videomode m28evk_video_modes[] = { .lower_margin = 45, .hsync_len = 1, .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, }, }; @@ -89,7 +94,9 @@ static struct fb_videomode apx4devkit_video_modes[] = { .lower_margin = 13, .hsync_len = 48, .vsync_len = 3, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, }, }; @@ -106,7 +113,9 @@ static struct fb_videomode apf28dev_video_modes[] = { .lower_margin = 0x15, .hsync_len = 64, .vsync_len = 4, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, }, }; @@ -123,6 +132,7 @@ static struct fb_videomode cfa10049_video_modes[] = { .lower_margin = 2, .hsync_len = 15, .vsync_len = 15, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT }, }; @@ -249,8 +259,6 @@ static void __init imx23_evk_init(void) mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes); mxsfb_pdata.default_bpp = 32; mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; - mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | - MXSFB_SYNC_DOTCLK_FAILING_ACT; } static inline void enable_clk_enet_out(void) @@ -270,8 +278,6 @@ static void __init imx28_evk_init(void) mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); mxsfb_pdata.default_bpp = 32; mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; - mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | - MXSFB_SYNC_DOTCLK_FAILING_ACT; mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); } @@ -291,7 +297,6 @@ static void __init m28evk_init(void) mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); mxsfb_pdata.default_bpp = 16; mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; - mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT; } static void __init sc_sps1_init(void) @@ -317,8 +322,6 @@ static void __init apx4devkit_init(void) mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes); mxsfb_pdata.default_bpp = 32; mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; - mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | - MXSFB_SYNC_DOTCLK_FAILING_ACT; } #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) @@ -399,18 +402,17 @@ static void __init cfa10049_init(void) { enable_clk_enet_out(); update_fec_mac_prop(OUI_CRYSTALFONTZ); - - mxsfb_pdata.mode_list = cfa10049_video_modes; - mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes); - mxsfb_pdata.default_bpp = 32; - mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; - mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT; } static void __init cfa10037_init(void) { enable_clk_enet_out(); update_fec_mac_prop(OUI_CRYSTALFONTZ); + + mxsfb_pdata.mode_list = cfa10049_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; } static void __init apf28_init(void) @@ -421,8 +423,6 @@ static void __init apf28_init(void) mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes); mxsfb_pdata.default_bpp = 16; mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT; - mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | - MXSFB_SYNC_DOTCLK_FAILING_ACT; } static void __init mxs_machine_init(void) diff --git a/trunk/arch/arm/mach-mxs/mm.c b/trunk/arch/arm/mach-mxs/mm.c index e63b7d87acbd..a4294aa9f301 100644 --- a/trunk/arch/arm/mach-mxs/mm.c +++ b/trunk/arch/arm/mach-mxs/mm.c @@ -18,7 +18,6 @@ #include #include -#include /* * Define the MX23 memory map. diff --git a/trunk/arch/arm/mach-mxs/ocotp.c b/trunk/arch/arm/mach-mxs/ocotp.c index 1dff46703753..54add60f94c9 100644 --- a/trunk/arch/arm/mach-mxs/ocotp.c +++ b/trunk/arch/arm/mach-mxs/ocotp.c @@ -19,7 +19,6 @@ #include /* for cpu_relax() */ #include -#include #define OCOTP_WORD_OFFSET 0x20 #define OCOTP_WORD_COUNT 0x20 diff --git a/trunk/arch/arm/mach-netx/generic.c b/trunk/arch/arm/mach-netx/generic.c index 1504b68f4c66..27c2cb7ab813 100644 --- a/trunk/arch/arm/mach-netx/generic.c +++ b/trunk/arch/arm/mach-netx/generic.c @@ -168,7 +168,7 @@ void __init netx_init_irq(void) { int irq; - vic_init(io_p2v(NETX_PA_VIC), NETX_IRQ_VIC_START, ~0, 0); + vic_init(io_p2v(NETX_PA_VIC), 0, ~0, 0); for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { irq_set_chip_and_handler(irq, &netx_hif_chip, diff --git a/trunk/arch/arm/mach-netx/include/mach/irqs.h b/trunk/arch/arm/mach-netx/include/mach/irqs.h index 8f74a844a775..6ce914d54a30 100644 --- a/trunk/arch/arm/mach-netx/include/mach/irqs.h +++ b/trunk/arch/arm/mach-netx/include/mach/irqs.h @@ -17,42 +17,42 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define NETX_IRQ_VIC_START 64 -#define NETX_IRQ_SOFTINT (NETX_IRQ_VIC_START + 0) -#define NETX_IRQ_TIMER0 (NETX_IRQ_VIC_START + 1) -#define NETX_IRQ_TIMER1 (NETX_IRQ_VIC_START + 2) -#define NETX_IRQ_TIMER2 (NETX_IRQ_VIC_START + 3) -#define NETX_IRQ_SYSTIME_NS (NETX_IRQ_VIC_START + 4) -#define NETX_IRQ_SYSTIME_S (NETX_IRQ_VIC_START + 5) -#define NETX_IRQ_GPIO_15 (NETX_IRQ_VIC_START + 6) -#define NETX_IRQ_WATCHDOG (NETX_IRQ_VIC_START + 7) -#define NETX_IRQ_UART0 (NETX_IRQ_VIC_START + 8) -#define NETX_IRQ_UART1 (NETX_IRQ_VIC_START + 9) -#define NETX_IRQ_UART2 (NETX_IRQ_VIC_START + 10) -#define NETX_IRQ_USB (NETX_IRQ_VIC_START + 11) -#define NETX_IRQ_SPI (NETX_IRQ_VIC_START + 12) -#define NETX_IRQ_I2C (NETX_IRQ_VIC_START + 13) -#define NETX_IRQ_LCD (NETX_IRQ_VIC_START + 14) -#define NETX_IRQ_HIF (NETX_IRQ_VIC_START + 15) -#define NETX_IRQ_GPIO_0_14 (NETX_IRQ_VIC_START + 16) -#define NETX_IRQ_XPEC0 (NETX_IRQ_VIC_START + 17) -#define NETX_IRQ_XPEC1 (NETX_IRQ_VIC_START + 18) -#define NETX_IRQ_XPEC2 (NETX_IRQ_VIC_START + 19) -#define NETX_IRQ_XPEC3 (NETX_IRQ_VIC_START + 20) -#define NETX_IRQ_XPEC(no) (NETX_IRQ_VIC_START + 17 + (no)) -#define NETX_IRQ_MSYNC0 (NETX_IRQ_VIC_START + 21) -#define NETX_IRQ_MSYNC1 (NETX_IRQ_VIC_START + 22) -#define NETX_IRQ_MSYNC2 (NETX_IRQ_VIC_START + 23) -#define NETX_IRQ_MSYNC3 (NETX_IRQ_VIC_START + 24) -#define NETX_IRQ_IRQ_PHY (NETX_IRQ_VIC_START + 25) -#define NETX_IRQ_ISO_AREA (NETX_IRQ_VIC_START + 26) +#define NETX_IRQ_VIC_START 0 +#define NETX_IRQ_SOFTINT 0 +#define NETX_IRQ_TIMER0 1 +#define NETX_IRQ_TIMER1 2 +#define NETX_IRQ_TIMER2 3 +#define NETX_IRQ_SYSTIME_NS 4 +#define NETX_IRQ_SYSTIME_S 5 +#define NETX_IRQ_GPIO_15 6 +#define NETX_IRQ_WATCHDOG 7 +#define NETX_IRQ_UART0 8 +#define NETX_IRQ_UART1 9 +#define NETX_IRQ_UART2 10 +#define NETX_IRQ_USB 11 +#define NETX_IRQ_SPI 12 +#define NETX_IRQ_I2C 13 +#define NETX_IRQ_LCD 14 +#define NETX_IRQ_HIF 15 +#define NETX_IRQ_GPIO_0_14 16 +#define NETX_IRQ_XPEC0 17 +#define NETX_IRQ_XPEC1 18 +#define NETX_IRQ_XPEC2 19 +#define NETX_IRQ_XPEC3 20 +#define NETX_IRQ_XPEC(no) (17 + (no)) +#define NETX_IRQ_MSYNC0 21 +#define NETX_IRQ_MSYNC1 22 +#define NETX_IRQ_MSYNC2 23 +#define NETX_IRQ_MSYNC3 24 +#define NETX_IRQ_IRQ_PHY 25 +#define NETX_IRQ_ISO_AREA 26 /* int 27 is reserved */ /* int 28 is reserved */ -#define NETX_IRQ_TIMER3 (NETX_IRQ_VIC_START + 29) -#define NETX_IRQ_TIMER4 (NETX_IRQ_VIC_START + 30) +#define NETX_IRQ_TIMER3 29 +#define NETX_IRQ_TIMER4 30 /* int 31 is reserved */ -#define NETX_IRQS (NETX_IRQ_VIC_START + 32) +#define NETX_IRQS 32 /* for multiplexed irqs on gpio 0..14 */ #define NETX_IRQ_GPIO(x) (NETX_IRQS + (x)) diff --git a/trunk/arch/arm/mach-omap1/Kconfig b/trunk/arch/arm/mach-omap1/Kconfig index cdd05f2e67ee..903da8eb886c 100644 --- a/trunk/arch/arm/mach-omap1/Kconfig +++ b/trunk/arch/arm/mach-omap1/Kconfig @@ -55,6 +55,12 @@ config MACH_OMAP_H3 TI OMAP 1710 H3 board support. Say Y here if you have such a board. +config MACH_OMAP_HTCWIZARD + bool "HTC Wizard" + depends on ARCH_OMAP850 + help + HTC Wizard smartphone support (AKA QTEK 9100, ...) + config MACH_HERALD bool "HTC Herald" depends on ARCH_OMAP850 diff --git a/trunk/arch/arm/mach-omap1/common.h b/trunk/arch/arm/mach-omap1/common.h index 14f7e9920479..fb18831e88aa 100644 --- a/trunk/arch/arm/mach-omap1/common.h +++ b/trunk/arch/arm/mach-omap1/common.h @@ -31,8 +31,6 @@ #include -#include - #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) void omap7xx_map_io(void); #else diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index b9c0ed3f648c..49ac3dfebef9 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -311,6 +311,9 @@ config MACH_OMAP_ZOOM2 default y select OMAP_PACKAGE_CBB select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SERIAL_8250 + select SERIAL_8250_CONSOLE + select SERIAL_CORE_CONSOLE config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" @@ -318,6 +321,9 @@ config MACH_OMAP_ZOOM3 default y select OMAP_PACKAGE_CBP select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SERIAL_8250 + select SERIAL_8250_CONSOLE + select SERIAL_CORE_CONSOLE config MACH_CM_T35 bool "CompuLab CM-T35/CM-T3730 modules" @@ -408,7 +414,7 @@ config OMAP3_SDRC_AC_TIMING config OMAP4_ERRATA_I688 bool "OMAP4 errata: Async Bridge Corruption" - depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM + depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM select ARCH_HAS_BARRIERS help If a data is stalled inside asynchronous bridge because of back diff --git a/trunk/arch/arm/mach-omap2/board-2430sdp.c b/trunk/arch/arm/mach-omap2/board-2430sdp.c index cb0596b631cf..a3e0aaa4886b 100644 --- a/trunk/arch/arm/mach-omap2/board-2430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-2430sdp.c @@ -166,7 +166,7 @@ static void __init sdp2430_display_init(void) omap_display_init(&sdp2430_dss_data); } -#if IS_ENABLED(CONFIG_SMC91X) +#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) static struct omap_smc91x_platform_data board_smc91x_data = { .cs = 5, diff --git a/trunk/arch/arm/mach-omap2/board-3430sdp.c b/trunk/arch/arm/mach-omap2/board-3430sdp.c index 7eb9651dd0f7..ce812decfaca 100644 --- a/trunk/arch/arm/mach-omap2/board-3430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3430sdp.c @@ -445,23 +445,16 @@ static void enable_board_wakeup_source(void) OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = 57, - .vcc_gpio = -EINVAL, - }, - { - .port = 2, - .reset_gpio = 61, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = 57, + .reset_gpio_port[1] = 61, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -613,8 +606,6 @@ static void __init omap_3430sdp_init(void) board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); sdp3430_display_init(); enable_board_wakeup_source(); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); } diff --git a/trunk/arch/arm/mach-omap2/board-3630sdp.c b/trunk/arch/arm/mach-omap2/board-3630sdp.c index 20d6d8189240..67447bd4564f 100644 --- a/trunk/arch/arm/mach-omap2/board-3630sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3630sdp.c @@ -53,23 +53,16 @@ static void enable_board_wakeup_source(void) OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = 126, - .vcc_gpio = -EINVAL, - }, - { - .port = 2, - .reset_gpio = 61, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = 126, + .reset_gpio_port[1] = 61, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -206,8 +199,6 @@ static void __init omap_sdp_init(void) board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16); enable_board_wakeup_source(); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); } diff --git a/trunk/arch/arm/mach-omap2/board-am3517crane.c b/trunk/arch/arm/mach-omap2/board-am3517crane.c index fc53911d0d13..7d3358b2e593 100644 --- a/trunk/arch/arm/mach-omap2/board-am3517crane.c +++ b/trunk/arch/arm/mach-omap2/board-am3517crane.c @@ -47,17 +47,15 @@ static struct omap_board_mux board_mux[] __initdata = { }; #endif -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = GPIO_USB_NRESET, - .vcc_gpio = GPIO_USB_POWER, - .vcc_polarity = 1, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = GPIO_USB_NRESET, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL }; static struct mtd_partition crane_nand_partitions[] = { @@ -133,7 +131,13 @@ static void __init am3517_crane_init(void) return; } - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); + ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH, + "usb_ehci_enable"); + if (ret < 0) { + pr_err("Can not request GPIO %d\n", GPIO_USB_POWER); + return; + } + usbhs_init(&usbhs_bdata); am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1); } diff --git a/trunk/arch/arm/mach-omap2/board-am3517evm.c b/trunk/arch/arm/mach-omap2/board-am3517evm.c index 191f9762ba63..9fb85908a61e 100644 --- a/trunk/arch/arm/mach-omap2/board-am3517evm.c +++ b/trunk/arch/arm/mach-omap2/board-am3517evm.c @@ -274,14 +274,6 @@ static __init void am3517_evm_mcbsp1_init(void) omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0); } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = 57, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ @@ -290,6 +282,12 @@ static struct usbhs_omap_platform_data usbhs_bdata __initdata = { #else .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, #endif + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = 57, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -351,6 +349,7 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; + static void __init am3517_evm_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); @@ -362,8 +361,6 @@ static void __init am3517_evm_init(void) /* Configure GPIO for EHCI port */ omap_mux_init_gpio(57, OMAP_PIN_OUTPUT); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); am3517_evm_hecc_init(&am3517_evm_hecc_pdata); /* DSS */ diff --git a/trunk/arch/arm/mach-omap2/board-cm-t35.c b/trunk/arch/arm/mach-omap2/board-cm-t35.c index 7fda3f5f8a7f..af2bb219e214 100644 --- a/trunk/arch/arm/mach-omap2/board-cm-t35.c +++ b/trunk/arch/arm/mach-omap2/board-cm-t35.c @@ -419,22 +419,15 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = OMAP_MAX_GPIO_LINES + 6, - .vcc_gpio = -EINVAL, - }, - { - .port = 2, - .reset_gpio = OMAP_MAX_GPIO_LINES + 7, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6, + .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7, + .reset_gpio_port[2] = -EINVAL }; static void __init cm_t35_init_usbh(void) @@ -451,7 +444,6 @@ static void __init cm_t35_init_usbh(void) msleep(1); } - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); } diff --git a/trunk/arch/arm/mach-omap2/board-cm-t3517.c b/trunk/arch/arm/mach-omap2/board-cm-t3517.c index 4eb5e6f2f7f5..a66da808cc4a 100644 --- a/trunk/arch/arm/mach-omap2/board-cm-t3517.c +++ b/trunk/arch/arm/mach-omap2/board-cm-t3517.c @@ -188,22 +188,15 @@ static inline void cm_t3517_init_rtc(void) {} #define HSUSB2_RESET_GPIO (147) #define USB_HUB_RESET_GPIO (152) -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = HSUSB1_RESET_GPIO, - .vcc_gpio = -EINVAL, - }, - { - .port = 2, - .reset_gpio = HSUSB2_RESET_GPIO, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = HSUSB1_RESET_GPIO, + .reset_gpio_port[1] = HSUSB2_RESET_GPIO, + .reset_gpio_port[2] = -EINVAL, }; static int __init cm_t3517_init_usbh(void) @@ -220,7 +213,6 @@ static int __init cm_t3517_init_usbh(void) msleep(1); } - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&cm_t3517_ehci_pdata); return 0; @@ -332,6 +324,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517") .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t3517_init, .init_late = am35xx_init_late, - .init_time = omap3_gptimer_timer_init, + .init_time = omap3_gp_gptimer_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-devkit8000.c b/trunk/arch/arm/mach-omap2/board-devkit8000.c index 42fbf1ef12a9..53056c3b0836 100644 --- a/trunk/arch/arm/mach-omap2/board-devkit8000.c +++ b/trunk/arch/arm/mach-omap2/board-devkit8000.c @@ -437,7 +437,15 @@ static struct platform_device *devkit8000_devices[] __initdata = { }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX diff --git a/trunk/arch/arm/mach-omap2/board-generic.c b/trunk/arch/arm/mach-omap2/board-generic.c index 78813b397209..0274ff7a2a2b 100644 --- a/trunk/arch/arm/mach-omap2/board-generic.c +++ b/trunk/arch/arm/mach-omap2/board-generic.c @@ -102,7 +102,6 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, - .init_late = omap3_init_late, .init_time = omap3_sync32k_timer_init, .dt_compat = omap3_boards_compat, .restart = omap3xxx_restart, @@ -120,7 +119,6 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, - .init_late = omap3_init_late, .init_time = omap3_secure_sync32k_timer_init, .dt_compat = omap3_gp_boards_compat, .restart = omap3xxx_restart, @@ -140,7 +138,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, - .init_time = omap3_gptimer_timer_init, + .init_time = omap3_am33xx_gptimer_timer_init, .dt_compat = am33xx_boards_compat, .restart = am33xx_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-h4.c b/trunk/arch/arm/mach-omap2/board-h4.c index 5b4ec51c385f..812c829fa46f 100644 --- a/trunk/arch/arm/mach-omap2/board-h4.c +++ b/trunk/arch/arm/mach-omap2/board-h4.c @@ -246,7 +246,7 @@ static u32 is_gpmc_muxed(void) return 0; } -#if IS_ENABLED(CONFIG_SMC91X) +#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) static struct omap_smc91x_platform_data board_smc91x_data = { .cs = 1, diff --git a/trunk/arch/arm/mach-omap2/board-igep0020.c b/trunk/arch/arm/mach-omap2/board-igep0020.c index 95ccec0eeab9..bf92678a01d0 100644 --- a/trunk/arch/arm/mach-omap2/board-igep0020.c +++ b/trunk/arch/arm/mach-omap2/board-igep0020.c @@ -527,28 +527,26 @@ static void __init igep_i2c_init(void) omap3_pmic_init("twl4030", &igep_twldata); } -static struct usbhs_phy_data igep2_phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = IGEP2_GPIO_USBH_NRESET, - .vcc_gpio = -EINVAL, - }, -}; - -static struct usbhs_phy_data igep3_phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = IGEP3_GPIO_USBH_NRESET, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL, }; static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET, + .reset_gpio_port[2] = -EINVAL, }; #ifdef CONFIG_OMAP_MUX @@ -644,10 +642,8 @@ static void __init igep_init(void) if (machine_is_igep0020()) { omap_display_init(&igep2_dss_data); igep2_init_smsc911x(); - usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data)); usbhs_init(&igep2_usbhs_bdata); } else { - usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data)); usbhs_init(&igep3_usbhs_bdata); } } diff --git a/trunk/arch/arm/mach-omap2/board-omap3beagle.c b/trunk/arch/arm/mach-omap2/board-omap3beagle.c index 6955a428f534..c3558f93d42c 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3beagle.c +++ b/trunk/arch/arm/mach-omap2/board-omap3beagle.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include @@ -278,21 +277,6 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = { static struct gpio_led gpio_leds[]; -/* PHY's VCC regulator might be added later, so flag that we need it */ -static struct nop_usb_xceiv_platform_data hsusb2_phy_data = { - .needs_vcc = true, -}; - -static struct usbhs_phy_data phy_data[] = { - { - .port = 2, - .reset_gpio = 147, - .vcc_gpio = -1, /* updated in beagle_twl_gpio_setup */ - .vcc_polarity = 1, /* updated in beagle_twl_gpio_setup */ - .platform_data = &hsusb2_phy_data, - }, -}; - static int beagle_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -334,11 +318,9 @@ static int beagle_twl_gpio_setup(struct device *dev, } dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio; - /* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */ - phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX; - phy_data[0].vcc_polarity = beagle_config.usb_pwr_level; + gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level, + "nEN_USB_PWR"); - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); return 0; } @@ -471,7 +453,15 @@ static struct platform_device *omap3_beagle_devices[] __initdata = { }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 147, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -489,7 +479,7 @@ static int __init beagle_opp_init(void) /* Initialize the omap3 opp table if not already created. */ r = omap3_opp_init(); - if (r < 0 && (r != -EEXIST)) { + if (IS_ERR_VALUE(r) && (r != -EEXIST)) { pr_err("%s: opp default init failed\n", __func__); return r; } @@ -553,9 +543,7 @@ static void __init omap3_beagle_init(void) usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); - usbhs_init(&usbhs_bdata); - board_nand_init(omap3beagle_nand_partitions, ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS, NAND_BUSWIDTH_16, NULL); diff --git a/trunk/arch/arm/mach-omap2/board-omap3evm.c b/trunk/arch/arm/mach-omap2/board-omap3evm.c index 2de92facc8a3..48789e0bb915 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3evm.c +++ b/trunk/arch/arm/mach-omap2/board-omap3evm.c @@ -496,7 +496,7 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = { static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = { REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */ REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */ - REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */ + REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"), REGULATOR_SUPPLY("vaux2", NULL), }; @@ -539,16 +539,17 @@ static int __init omap3_evm_i2c_init(void) return 0; } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = -1, /* set at runtime */ - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + /* PHY reset GPIO will be runtime programmed based on EVM version */ + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -724,7 +725,7 @@ static void __init omap3_evm_init(void) /* setup EHCI phy reset config */ omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP); - phy_data[0].reset_gpio = 21; + usbhs_bdata.reset_gpio_port[1] = 21; /* EVM REV >= E can supply 500mA with EXTVBUS programming */ musb_board_data.power = 500; @@ -732,12 +733,10 @@ static void __init omap3_evm_init(void) } else { /* setup EHCI phy reset on MDC */ omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); - phy_data[0].reset_gpio = 135; + usbhs_bdata.reset_gpio_port[1] = 135; } usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(&musb_board_data); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); board_nand_init(omap3evm_nand_partitions, ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS, diff --git a/trunk/arch/arm/mach-omap2/board-omap3pandora.c b/trunk/arch/arm/mach-omap2/board-omap3pandora.c index 1004d2aaa68f..2bba362148a0 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3pandora.c +++ b/trunk/arch/arm/mach-omap2/board-omap3pandora.c @@ -346,7 +346,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = { }; static struct regulator_consumer_supply pandora_usb_phy_supply[] = { - REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */ + REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"), }; /* ads7846 on SPI and 2 nub controllers on I2C */ @@ -561,14 +561,6 @@ static void __init pandora_wl1251_init(void) printk(KERN_ERR "wl1251 board initialisation failed\n"); } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = 16, - .vcc_gpio = -EINVAL, - }, -}; - static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_leds_gpio, &pandora_keys_gpio, @@ -577,7 +569,15 @@ static struct platform_device *omap3pandora_devices[] __initdata = { }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 16, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -601,10 +601,7 @@ static void __init omap3pandora_init(void) spi_register_board_info(omap3pandora_spi_board_info, ARRAY_SIZE(omap3pandora_spi_board_info)); omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); gpmc_nand_init(&pandora_nand_data, NULL); diff --git a/trunk/arch/arm/mach-omap2/board-omap3stalker.c b/trunk/arch/arm/mach-omap2/board-omap3stalker.c index bf0956489899..95c10b3aa678 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3stalker.c +++ b/trunk/arch/arm/mach-omap2/board-omap3stalker.c @@ -358,20 +358,19 @@ static int __init omap3_stalker_i2c_init(void) #define OMAP3_STALKER_TS_GPIO 175 -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = 21, - .vcc_gpio = -EINVAL, - }, -}; - static struct platform_device *omap3_stalker_devices[] __initdata = { &keys_gpio, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 21, + .reset_gpio_port[2] = -EINVAL, }; #ifdef CONFIG_OMAP_MUX @@ -408,8 +407,6 @@ static void __init omap3_stalker_init(void) omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL); usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL); diff --git a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c b/trunk/arch/arm/mach-omap2/board-omap3touchbook.c index 7da48bc42bbf..bcd44fbcd877 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/trunk/arch/arm/mach-omap2/board-omap3touchbook.c @@ -305,22 +305,21 @@ static struct omap_board_mux board_mux[] __initdata = { }; #endif -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = 147, - .vcc_gpio = -EINVAL, - }, -}; - static struct platform_device *omap3_touchbook_devices[] __initdata = { &leds_gpio, &keys_gpio, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 147, + .reset_gpio_port[2] = -EINVAL }; static void omap3_touchbook_poweroff(void) @@ -369,8 +368,6 @@ static void __init omap3_touchbook_init(void) omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata); usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); board_nand_init(omap3touchbook_nand_partitions, ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS, diff --git a/trunk/arch/arm/mach-omap2/board-omap4panda.c b/trunk/arch/arm/mach-omap2/board-omap4panda.c index a71ad345f20d..b02c2f00609b 100644 --- a/trunk/arch/arm/mach-omap2/board-omap4panda.c +++ b/trunk/arch/arm/mach-omap2/board-omap4panda.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -133,22 +132,6 @@ static struct platform_device btwilink_device = { .id = -1, }; -/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */ -static struct nop_usb_xceiv_platform_data hsusb1_phy_data = { - /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ - .clk_rate = 19200000, -}; - -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = GPIO_HUB_NRESET, - .vcc_gpio = GPIO_HUB_POWER, - .vcc_polarity = 1, - .platform_data = &hsusb1_phy_data, - }, -}; - static struct platform_device *panda_devices[] __initdata = { &leds_gpio, &wl1271_device, @@ -159,19 +142,49 @@ static struct platform_device *panda_devices[] __initdata = { static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + .phy_reset = false, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL +}; + +static struct gpio panda_ehci_gpios[] __initdata = { + { GPIO_HUB_POWER, GPIOF_OUT_INIT_LOW, "hub_power" }, + { GPIO_HUB_NRESET, GPIOF_OUT_INIT_LOW, "hub_nreset" }, }; static void __init omap4_ehci_init(void) { int ret; + struct clk *phy_ref_clk; /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ - ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL); - if (ret) - pr_err("Failed to add main_clk alias to auxclk3_ck\n"); + phy_ref_clk = clk_get(NULL, "auxclk3_ck"); + if (IS_ERR(phy_ref_clk)) { + pr_err("Cannot request auxclk3\n"); + return; + } + clk_set_rate(phy_ref_clk, 19200000); + clk_prepare_enable(phy_ref_clk); + + /* disable the power to the usb hub prior to init and reset phy+hub */ + ret = gpio_request_array(panda_ehci_gpios, + ARRAY_SIZE(panda_ehci_gpios)); + if (ret) { + pr_err("Unable to initialize EHCI power/reset\n"); + return; + } + + gpio_export(GPIO_HUB_POWER, 0); + gpio_export(GPIO_HUB_NRESET, 0); + gpio_set_value(GPIO_HUB_NRESET, 1); - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); + + /* enable power to hub */ + gpio_set_value(GPIO_HUB_POWER, 1); } static struct omap_musb_board_data musb_board_data = { diff --git a/trunk/arch/arm/mach-omap2/board-overo.c b/trunk/arch/arm/mach-omap2/board-overo.c index ab79a4422bcc..86bab51154ee 100644 --- a/trunk/arch/arm/mach-omap2/board-overo.c +++ b/trunk/arch/arm/mach-omap2/board-overo.c @@ -458,16 +458,14 @@ static int __init overo_spi_init(void) return 0; } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = OVERO_GPIO_USBH_NRESET, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = OVERO_GPIO_USBH_NRESET, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -504,8 +502,6 @@ static void __init overo_init(void) ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL); usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); overo_spi_init(); overo_init_smsc911x(); diff --git a/trunk/arch/arm/mach-omap2/board-rx51.c b/trunk/arch/arm/mach-omap2/board-rx51.c index d2ea68ea678a..f7c4616cbb60 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51.c +++ b/trunk/arch/arm/mach-omap2/board-rx51.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -99,7 +98,6 @@ static void __init rx51_init(void) sdrc_params = nokia_get_sdram_timings(); omap_sdrc_init(sdrc_params, sdrc_params); - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(&musb_board_data); rx51_peripherals_init(); diff --git a/trunk/arch/arm/mach-omap2/board-zoom.c b/trunk/arch/arm/mach-omap2/board-zoom.c index 1a3dd865d8eb..5e4d4c9fe61a 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom.c +++ b/trunk/arch/arm/mach-omap2/board-zoom.c @@ -92,16 +92,14 @@ static struct mtd_partition zoom_nand_partitions[] = { }, }; -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = ZOOM3_EHCI_RESET_GPIO, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO, + .reset_gpio_port[2] = -EINVAL, }; static void __init omap_zoom_init(void) @@ -111,8 +109,6 @@ static void __init omap_zoom_init(void) } else if (machine_is_omap_zoom3()) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); } diff --git a/trunk/arch/arm/mach-omap2/cclock33xx_data.c b/trunk/arch/arm/mach-omap2/cclock33xx_data.c index 7f091c85384e..476b82066cb6 100644 --- a/trunk/arch/arm/mach-omap2/cclock33xx_data.c +++ b/trunk/arch/arm/mach-omap2/cclock33xx_data.c @@ -958,14 +958,6 @@ int __init am33xx_clk_init(void) clk_set_parent(&timer3_fck, &sys_clkin_ck); clk_set_parent(&timer6_fck, &sys_clkin_ck); - /* - * The On-Chip 32K RC Osc clock is not an accurate clock-source as per - * the design/spec, so as a result, for example, timer which supposed - * to get expired @60Sec, but will expire somewhere ~@40Sec, which is - * not expected by any use-case, so change WDT1 clock source to PRCM - * 32KHz clock. - */ - clk_set_parent(&wdt1_fck, &clkdiv32k_ick); return 0; } diff --git a/trunk/arch/arm/mach-omap2/clock.c b/trunk/arch/arm/mach-omap2/clock.c index 2191f25ad21b..e4ec3a69ee2e 100644 --- a/trunk/arch/arm/mach-omap2/clock.c +++ b/trunk/arch/arm/mach-omap2/clock.c @@ -596,7 +596,7 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) return -ENOENT; r = clk_set_rate(mpurate_ck, mpurate); - if (r < 0) { + if (IS_ERR_VALUE(r)) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", mpurate_ck_name, mpurate, r); clk_put(mpurate_ck); diff --git a/trunk/arch/arm/mach-omap2/common.h b/trunk/arch/arm/mach-omap2/common.h index bf70e2b57ff8..0a6b9c7a63da 100644 --- a/trunk/arch/arm/mach-omap2/common.h +++ b/trunk/arch/arm/mach-omap2/common.h @@ -82,7 +82,8 @@ extern void omap2_init_common_infrastructure(void); extern void omap2_sync32k_timer_init(void); extern void omap3_sync32k_timer_init(void); extern void omap3_secure_sync32k_timer_init(void); -extern void omap3_gptimer_timer_init(void); +extern void omap3_gp_gptimer_timer_init(void); +extern void omap3_am33xx_gptimer_timer_init(void); extern void omap4_local_timer_init(void); extern void omap5_realtime_timer_init(void); @@ -107,6 +108,7 @@ void omap35xx_init_late(void); void omap3630_init_late(void); void am35xx_init_late(void); void ti81xx_init_late(void); +void omap4430_init_late(void); int omap2_common_pm_late_init(void); #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) diff --git a/trunk/arch/arm/mach-omap2/dpll3xxx.c b/trunk/arch/arm/mach-omap2/dpll3xxx.c index 3a0296cfcace..3aed4b0b9563 100644 --- a/trunk/arch/arm/mach-omap2/dpll3xxx.c +++ b/trunk/arch/arm/mach-omap2/dpll3xxx.c @@ -307,10 +307,10 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) _omap3_noncore_dpll_bypass(clk); /* - * Set jitter correction. Jitter correction applicable for OMAP343X - * only since freqsel field is no longer present on other devices. + * Set jitter correction. No jitter correction for OMAP4 and 3630 + * since freqsel field is no longer present */ - if (cpu_is_omap343x()) { + if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { v = __raw_readl(dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -480,30 +480,29 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, if (!dd) return -EINVAL; + __clk_prepare(dd->clk_bypass); + clk_enable(dd->clk_bypass); + __clk_prepare(dd->clk_ref); + clk_enable(dd->clk_ref); + if (__clk_get_rate(dd->clk_bypass) == rate && (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { pr_debug("%s: %s: set rate: entering bypass.\n", __func__, __clk_get_name(hw->clk)); - __clk_prepare(dd->clk_bypass); - clk_enable(dd->clk_bypass); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; - clk_disable(dd->clk_bypass); - __clk_unprepare(dd->clk_bypass); } else { - __clk_prepare(dd->clk_ref); - clk_enable(dd->clk_ref); - if (dd->last_rounded_rate != rate) rate = __clk_round_rate(hw->clk, rate); if (dd->last_rounded_rate == 0) return -EINVAL; - /* Freqsel is available only on OMAP343X devices */ - if (cpu_is_omap343x()) { + /* No freqsel on AM335x, OMAP4 and OMAP3630 */ + if (!soc_is_am33xx() && !cpu_is_omap44xx() && + !cpu_is_omap3630()) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); WARN_ON(!freqsel); @@ -515,8 +514,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, ret = omap3_noncore_dpll_program(clk, freqsel); if (!ret) new_parent = dd->clk_ref; - clk_disable(dd->clk_ref); - __clk_unprepare(dd->clk_ref); } /* * FIXME - this is all wrong. common code handles reparenting and @@ -528,6 +525,11 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, if (!ret) __clk_reparent(hw->clk, new_parent); + clk_disable(dd->clk_ref); + __clk_unprepare(dd->clk_ref); + clk_disable(dd->clk_bypass); + __clk_unprepare(dd->clk_bypass); + return 0; } diff --git a/trunk/arch/arm/mach-omap2/dsp.c b/trunk/arch/arm/mach-omap2/dsp.c index b8208b4b1bd9..b155500e84a8 100644 --- a/trunk/arch/arm/mach-omap2/dsp.c +++ b/trunk/arch/arm/mach-omap2/dsp.c @@ -26,7 +26,7 @@ #include "control.h" #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" -#ifdef CONFIG_TIDSPBRIDGE_DVFS +#ifdef CONFIG_BRIDGE_DVFS #include "omap-pm.h" #endif @@ -35,7 +35,7 @@ static struct platform_device *omap_dsp_pdev; static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { -#ifdef CONFIG_TIDSPBRIDGE_DVFS +#ifdef CONFIG_BRIDGE_DVFS .dsp_set_min_opp = omap_pm_dsp_set_min_opp, .dsp_get_opp = omap_pm_dsp_get_opp, .cpu_set_freq = omap_pm_cpu_set_freq, diff --git a/trunk/arch/arm/mach-omap2/gpmc-nand.c b/trunk/arch/arm/mach-omap2/gpmc-nand.c index d9c27195caf0..afc1e8c32d6c 100644 --- a/trunk/arch/arm/mach-omap2/gpmc-nand.c +++ b/trunk/arch/arm/mach-omap2/gpmc-nand.c @@ -74,6 +74,14 @@ static int omap2_nand_gpmc_retime( t.cs_wr_off = gpmc_t->cs_wr_off; t.wr_cycle = gpmc_t->wr_cycle; + /* Configure GPMC */ + if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1); + else + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); + gpmc_cs_configure(gpmc_nand_data->cs, + GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0); err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); if (err) return err; @@ -107,18 +115,14 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, struct gpmc_timings *gpmc_t) { int err = 0; - struct gpmc_settings s; struct device *dev = &gpmc_nand_device.dev; - memset(&s, 0, sizeof(struct gpmc_settings)); - gpmc_nand_device.dev.platform_data = gpmc_nand_data; err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, (unsigned long *)&gpmc_nand_resource[0].start); if (err < 0) { - dev_err(dev, "Cannot request GPMC CS %d, error %d\n", - gpmc_nand_data->cs, err); + dev_err(dev, "Cannot request GPMC CS\n"); return err; } @@ -136,31 +140,11 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; } + } - if (gpmc_nand_data->of_node) { - gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); - } else { - s.device_nand = true; - - /* Enable RD PIN Monitoring Reg */ - if (gpmc_nand_data->dev_ready) { - s.wait_on_read = true; - s.wait_on_write = true; - } - } - - if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) - s.device_width = GPMC_DEVWIDTH_16BIT; - else - s.device_width = GPMC_DEVWIDTH_8BIT; - - err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); - if (err < 0) - goto out_free_cs; - - err = gpmc_configure(GPMC_CONFIG_WP, 0); - if (err < 0) - goto out_free_cs; + /* Enable RD PIN Monitoring Reg */ + if (gpmc_nand_data->dev_ready) { + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); } gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); diff --git a/trunk/arch/arm/mach-omap2/gpmc-onenand.c b/trunk/arch/arm/mach-omap2/gpmc-onenand.c index 64b5a8346982..fadd87435cd0 100644 --- a/trunk/arch/arm/mach-omap2/gpmc-onenand.c +++ b/trunk/arch/arm/mach-omap2/gpmc-onenand.c @@ -47,23 +47,11 @@ static struct platform_device gpmc_onenand_device = { .resource = &gpmc_onenand_resource, }; -static struct gpmc_settings onenand_async = { - .device_width = GPMC_DEVWIDTH_16BIT, - .mux_add_data = GPMC_MUX_AD, -}; - -static struct gpmc_settings onenand_sync = { - .burst_read = true, - .burst_wrap = true, - .burst_len = GPMC_BURST_16, - .device_width = GPMC_DEVWIDTH_16BIT, - .mux_add_data = GPMC_MUX_AD, - .wait_pin = 0, -}; - -static void omap2_onenand_calc_async_timings(struct gpmc_timings *t) +static struct gpmc_timings omap2_onenand_calc_async_timings(void) { struct gpmc_device_timings dev_t; + struct gpmc_timings t; + const int t_cer = 15; const int t_avdp = 12; const int t_aavdh = 7; @@ -76,6 +64,7 @@ static void omap2_onenand_calc_async_timings(struct gpmc_timings *t) memset(&dev_t, 0, sizeof(dev_t)); + dev_t.mux = true; dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000; dev_t.t_avdp_w = dev_t.t_avdp_r; dev_t.t_aavdh = t_aavdh * 1000; @@ -87,7 +76,19 @@ static void omap2_onenand_calc_async_timings(struct gpmc_timings *t) dev_t.t_wpl = t_wpl * 1000; dev_t.t_wph = t_wph * 1000; - gpmc_calc_timings(t, &onenand_async, &dev_t); + gpmc_calc_timings(&t, &dev_t); + + return t; +} + +static int gpmc_set_async_mode(int cs, struct gpmc_timings *t) +{ + /* Configure GPMC for asynchronous read */ + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, + GPMC_CONFIG1_DEVICESIZE_16 | + GPMC_CONFIG1_MUXADDDATA); + + return gpmc_cs_set_timings(cs, t); } static void omap2_onenand_set_async_mode(void __iomem *onenand_base) @@ -157,11 +158,12 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, return freq; } -static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t, - unsigned int flags, - int freq) +static struct gpmc_timings +omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, + int freq) { struct gpmc_device_timings dev_t; + struct gpmc_timings t; const int t_cer = 15; const int t_avdp = 12; const int t_cez = 20; /* max of t_cez, t_oez */ @@ -170,9 +172,9 @@ static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t, int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; int div, gpmc_clk_ns; - if (flags & ONENAND_SYNC_READ) + if (cfg->flags & ONENAND_SYNC_READ) onenand_flags = ONENAND_FLAG_SYNCREAD; - else if (flags & ONENAND_SYNC_READWRITE) + else if (cfg->flags & ONENAND_SYNC_READWRITE) onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE; switch (freq) { @@ -237,11 +239,10 @@ static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t, /* Set synchronous read timings */ memset(&dev_t, 0, sizeof(dev_t)); - if (onenand_flags & ONENAND_FLAG_SYNCREAD) - onenand_sync.sync_read = true; + dev_t.mux = true; + dev_t.sync_read = true; if (onenand_flags & ONENAND_FLAG_SYNCWRITE) { - onenand_sync.sync_write = true; - onenand_sync.burst_write = true; + dev_t.sync_write = true; } else { dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; dev_t.t_wpl = t_wpl * 1000; @@ -264,7 +265,32 @@ static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t, dev_t.cyc_aavdh_oe = 1; dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; - gpmc_calc_timings(t, &onenand_sync, &dev_t); + gpmc_calc_timings(&t, &dev_t); + + return t; +} + +static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t) +{ + unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD; + unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE; + + /* Configure GPMC for synchronous read */ + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, + GPMC_CONFIG1_WRAPBURST_SUPP | + GPMC_CONFIG1_READMULTIPLE_SUPP | + (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) | + (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) | + (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) | + GPMC_CONFIG1_PAGE_LEN(2) | + (cpu_is_omap34xx() ? 0 : + (GPMC_CONFIG1_WAIT_READ_MON | + GPMC_CONFIG1_WAIT_PIN_SEL(0))) | + GPMC_CONFIG1_DEVICESIZE_16 | + GPMC_CONFIG1_DEVICETYPE_NOR | + GPMC_CONFIG1_MUXADDDATA); + + return gpmc_cs_set_timings(cs, t); } static int omap2_onenand_setup_async(void __iomem *onenand_base) @@ -272,20 +298,12 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base) struct gpmc_timings t; int ret; - if (gpmc_onenand_data->of_node) - gpmc_read_settings_dt(gpmc_onenand_data->of_node, - &onenand_async); - omap2_onenand_set_async_mode(onenand_base); - omap2_onenand_calc_async_timings(&t); - - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async); - if (ret < 0) - return ret; + t = omap2_onenand_calc_async_timings(); - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t); - if (ret < 0) + ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t); + if (IS_ERR_VALUE(ret)) return ret; omap2_onenand_set_async_mode(onenand_base); @@ -304,26 +322,10 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) set_onenand_cfg(onenand_base); } - if (gpmc_onenand_data->of_node) { - gpmc_read_settings_dt(gpmc_onenand_data->of_node, - &onenand_sync); - } else { - /* - * FIXME: Appears to be legacy code from initial ONENAND commit. - * Unclear what boards this is for and if this can be removed. - */ - if (!cpu_is_omap34xx()) - onenand_sync.wait_on_read = true; - } - - omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq); + t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq); - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync); - if (ret < 0) - return ret; - - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t); - if (ret < 0) + ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t); + if (IS_ERR_VALUE(ret)) return ret; set_onenand_cfg(onenand_base); @@ -357,7 +359,6 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) { int err; - struct device *dev = &gpmc_onenand_device.dev; gpmc_onenand_data = _onenand_data; gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; @@ -365,7 +366,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) if (cpu_is_omap24xx() && (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) { - dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n"); + printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n"); gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE; gpmc_onenand_data->flags |= ONENAND_SYNC_READ; } @@ -378,8 +379,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, (unsigned long *)&gpmc_onenand_resource.start); if (err < 0) { - dev_err(dev, "Cannot request GPMC CS %d, error %d\n", - gpmc_onenand_data->cs, err); + pr_err("%s: Cannot request GPMC CS\n", __func__); return; } @@ -387,7 +387,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) ONENAND_IO_SIZE - 1; if (platform_device_register(&gpmc_onenand_device) < 0) { - dev_err(dev, "Unable to register OneNAND device\n"); + pr_err("%s: Unable to register OneNAND device\n", __func__); gpmc_cs_free(gpmc_onenand_data->cs); return; } diff --git a/trunk/arch/arm/mach-omap2/gpmc-smc91x.c b/trunk/arch/arm/mach-omap2/gpmc-smc91x.c index 61a063595e66..11d0b756f098 100644 --- a/trunk/arch/arm/mach-omap2/gpmc-smc91x.c +++ b/trunk/arch/arm/mach-omap2/gpmc-smc91x.c @@ -49,10 +49,6 @@ static struct platform_device gpmc_smc91x_device = { .resource = gpmc_smc91x_resources, }; -static struct gpmc_settings smc91x_settings = { - .device_width = GPMC_DEVWIDTH_16BIT, -}; - /* * Set the gpmc timings for smc91c96. The timings are taken * from the data sheet available at: @@ -71,6 +67,18 @@ static int smc91c96_gpmc_retime(void) const int t7 = 5; /* Figure 12.4 write */ const int t8 = 5; /* Figure 12.4 write */ const int t20 = 185; /* Figure 12.2 read and 12.4 write */ + u32 l; + + l = GPMC_CONFIG1_DEVICESIZE_16; + if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA) + l |= GPMC_CONFIG1_MUXADDDATA; + if (gpmc_cfg->flags & GPMC_READ_MON) + l |= GPMC_CONFIG1_WAIT_READ_MON; + if (gpmc_cfg->flags & GPMC_WRITE_MON) + l |= GPMC_CONFIG1_WAIT_WRITE_MON; + if (gpmc_cfg->wait_pin) + l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin); + gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l); /* * FIXME: Calculate the address and data bus muxed timings. @@ -96,7 +104,7 @@ static int smc91c96_gpmc_retime(void) dev_t.t_cez_w = t4_w * 1000; dev_t.t_wr_cycle = (t20 - t3) * 1000; - gpmc_calc_timings(&t, &smc91x_settings, &dev_t); + gpmc_calc_timings(&t, &dev_t); return gpmc_cs_set_timings(gpmc_cfg->cs, &t); } @@ -125,18 +133,6 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data) gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f; gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK); - if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA) - smc91x_settings.mux_add_data = GPMC_MUX_AD; - if (gpmc_cfg->flags & GPMC_READ_MON) - smc91x_settings.wait_on_read = true; - if (gpmc_cfg->flags & GPMC_WRITE_MON) - smc91x_settings.wait_on_write = true; - if (gpmc_cfg->wait_pin) - smc91x_settings.wait_pin = gpmc_cfg->wait_pin; - ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings); - if (ret < 0) - goto free1; - if (gpmc_cfg->retime) { ret = gpmc_cfg->retime(); if (ret != 0) diff --git a/trunk/arch/arm/mach-omap2/gpmc.c b/trunk/arch/arm/mach-omap2/gpmc.c index ed946df5ad8a..e4b16c8efe8b 100644 --- a/trunk/arch/arm/mach-omap2/gpmc.c +++ b/trunk/arch/arm/mach-omap2/gpmc.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -92,7 +91,9 @@ #define GPMC_CS_SIZE 0x30 #define GPMC_BCH_SIZE 0x10 +#define GPMC_MEM_START 0x00000000 #define GPMC_MEM_END 0x3FFFFFFF +#define BOOT_ROM_SPACE 0x100000 /* 1MB */ #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ #define GPMC_SECTION_SHIFT 28 /* 128 MB */ @@ -106,9 +107,6 @@ #define GPMC_HAS_WR_ACCESS 0x1 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 -#define GPMC_HAS_MUX_AAD 0x4 - -#define GPMC_NR_WAITPINS 4 /* XXX: Only NAND irq has been considered,currently these are the only ones used */ @@ -155,7 +153,6 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); /* Define chip-selects as reserved by default until probe completes */ static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); -static unsigned int gpmc_nr_waitpins; static struct device *gpmc_dev; static int gpmc_irq; static resource_size_t phys_base, mem_size; @@ -184,7 +181,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val) __raw_writel(val, reg_addr); } -static u32 gpmc_cs_read_reg(int cs, int idx) +u32 gpmc_cs_read_reg(int cs, int idx) { void __iomem *reg_addr; @@ -193,7 +190,7 @@ static u32 gpmc_cs_read_reg(int cs, int idx) } /* TODO: Add support for gpmc_fck to clock framework and use it */ -static unsigned long gpmc_get_fclk_period(void) +unsigned long gpmc_get_fclk_period(void) { unsigned long rate = clk_get_rate(gpmc_l3_clk); @@ -208,7 +205,7 @@ static unsigned long gpmc_get_fclk_period(void) return rate; } -static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) +unsigned int gpmc_ns_to_ticks(unsigned int time_ns) { unsigned long tick_ps; @@ -218,7 +215,7 @@ static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) return (time_ns * 1000 + tick_ps - 1) / tick_ps; } -static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) +unsigned int gpmc_ps_to_ticks(unsigned int time_ps) { unsigned long tick_ps; @@ -233,6 +230,13 @@ unsigned int gpmc_ticks_to_ns(unsigned int ticks) return ticks * gpmc_get_fclk_period() / 1000; } +unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) +{ + unsigned long ticks = gpmc_ns_to_ticks(time_ns); + + return ticks * gpmc_get_fclk_period() / 1000; +} + static unsigned int gpmc_ticks_to_ps(unsigned int ticks) { return ticks * gpmc_get_fclk_period(); @@ -401,18 +405,11 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) return 0; } -static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) +static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) { u32 l; u32 mask; - /* - * Ensure that base address is aligned on a - * boundary equal to or greater than size. - */ - if (base & (size - 1)) - return -EINVAL; - mask = (1 << GPMC_SECTION_SHIFT) - size; l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); l &= ~0x3f; @@ -421,8 +418,6 @@ static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; l |= GPMC_CONFIG7_CSVALID; gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); - - return 0; } static void gpmc_cs_disable_mem(int cs) @@ -453,14 +448,22 @@ static int gpmc_cs_mem_enabled(int cs) return l & GPMC_CONFIG7_CSVALID; } -static void gpmc_cs_set_reserved(int cs, int reserved) +int gpmc_cs_set_reserved(int cs, int reserved) { + if (cs > GPMC_CS_NUM) + return -ENODEV; + gpmc_cs_map &= ~(1 << cs); gpmc_cs_map |= (reserved ? 1 : 0) << cs; + + return 0; } -static bool gpmc_cs_reserved(int cs) +int gpmc_cs_reserved(int cs) { + if (cs > GPMC_CS_NUM) + return -ENODEV; + return gpmc_cs_map & (1 << cs); } @@ -507,39 +510,6 @@ static int gpmc_cs_delete_mem(int cs) return r; } -/** - * gpmc_cs_remap - remaps a chip-select physical base address - * @cs: chip-select to remap - * @base: physical base address to re-map chip-select to - * - * Re-maps a chip-select to a new physical base address specified by - * "base". Returns 0 on success and appropriate negative error code - * on failure. - */ -static int gpmc_cs_remap(int cs, u32 base) -{ - int ret; - u32 old_base, size; - - if (cs > GPMC_CS_NUM) - return -ENODEV; - gpmc_cs_get_memconf(cs, &old_base, &size); - if (base == old_base) - return 0; - gpmc_cs_disable_mem(cs); - ret = gpmc_cs_delete_mem(cs); - if (ret < 0) - return ret; - ret = gpmc_cs_insert_mem(cs, base, size); - if (ret < 0) - return ret; - ret = gpmc_cs_enable_mem(cs, base, size); - if (ret < 0) - return ret; - - return 0; -} - int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) { struct resource *res = &gpmc_cs_mem[cs]; @@ -565,12 +535,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) if (r < 0) goto out; - r = gpmc_cs_enable_mem(cs, res->start, resource_size(res)); - if (r < 0) { - release_resource(res); - goto out; - } - + gpmc_cs_enable_mem(cs, res->start, resource_size(res)); *base = res->start; gpmc_cs_set_reserved(cs, 1); out: @@ -596,14 +561,16 @@ void gpmc_cs_free(int cs) EXPORT_SYMBOL(gpmc_cs_free); /** - * gpmc_configure - write request to configure gpmc + * gpmc_cs_configure - write request to configure gpmc + * @cs: chip select number * @cmd: command type * @wval: value to write * @return status of the operation */ -int gpmc_configure(int cmd, int wval) +int gpmc_cs_configure(int cs, int cmd, int wval) { - u32 regval; + int err = 0; + u32 regval = 0; switch (cmd) { case GPMC_ENABLE_IRQ: @@ -623,14 +590,43 @@ int gpmc_configure(int cmd, int wval) gpmc_write_reg(GPMC_CONFIG, regval); break; + case GPMC_CONFIG_RDY_BSY: + regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + if (wval) + regval |= WR_RD_PIN_MONITORING; + else + regval &= ~WR_RD_PIN_MONITORING; + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); + break; + + case GPMC_CONFIG_DEV_SIZE: + regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + + /* clear 2 target bits */ + regval &= ~GPMC_CONFIG1_DEVICESIZE(3); + + /* set the proper value */ + regval |= GPMC_CONFIG1_DEVICESIZE(wval); + + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); + break; + + case GPMC_CONFIG_DEV_TYPE: + regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + regval |= GPMC_CONFIG1_DEVICETYPE(wval); + if (wval == GPMC_DEVICETYPE_NOR) + regval |= GPMC_CONFIG1_MUXADDDATA; + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); + break; + default: - pr_err("%s: command not supported\n", __func__); - return -EINVAL; + printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); + err = -EINVAL; } - return 0; + return err; } -EXPORT_SYMBOL(gpmc_configure); +EXPORT_SYMBOL(gpmc_cs_configure); void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) { @@ -720,7 +716,7 @@ static int gpmc_setup_irq(void) return -EINVAL; gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); - if (gpmc_irq_start < 0) { + if (IS_ERR_VALUE(gpmc_irq_start)) { pr_err("irq_alloc_descs failed\n"); return gpmc_irq_start; } @@ -785,16 +781,16 @@ static void gpmc_mem_exit(void) } -static void gpmc_mem_init(void) +static int gpmc_mem_init(void) { - int cs; + int cs, rc; + unsigned long boot_rom_space = 0; - /* - * The first 1MB of GPMC address space is typically mapped to - * the internal ROM. Never allocate the first page, to - * facilitate bug detection; even if we didn't boot from ROM. + /* never allocate the first page, to facilitate bug detection; + * even if we didn't boot from ROM. */ - gpmc_mem_root.start = SZ_1M; + boot_rom_space = BOOT_ROM_SPACE; + gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; gpmc_mem_root.end = GPMC_MEM_END; /* Reserve all regions that has been set up by bootloader */ @@ -804,12 +800,16 @@ static void gpmc_mem_init(void) if (!gpmc_cs_mem_enabled(cs)) continue; gpmc_cs_get_memconf(cs, &base, &size); - if (gpmc_cs_insert_mem(cs, base, size)) { - pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", - __func__, cs, base, base + size); - gpmc_cs_disable_mem(cs); + rc = gpmc_cs_insert_mem(cs, base, size); + if (IS_ERR_VALUE(rc)) { + while (--cs >= 0) + if (gpmc_cs_mem_enabled(cs)) + gpmc_cs_delete_mem(cs); + return rc; } } + + return 0; } static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) @@ -825,9 +825,9 @@ static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) /* XXX: can the cycles be avoided ? */ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, - struct gpmc_device_timings *dev_t, - bool mux) + struct gpmc_device_timings *dev_t) { + bool mux = dev_t->mux; u32 temp; /* adv_rd_off */ @@ -880,9 +880,9 @@ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, } static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, - struct gpmc_device_timings *dev_t, - bool mux) + struct gpmc_device_timings *dev_t) { + bool mux = dev_t->mux; u32 temp; /* adv_wr_off */ @@ -942,9 +942,9 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, } static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, - struct gpmc_device_timings *dev_t, - bool mux) + struct gpmc_device_timings *dev_t) { + bool mux = dev_t->mux; u32 temp; /* adv_rd_off */ @@ -982,9 +982,9 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, } static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, - struct gpmc_device_timings *dev_t, - bool mux) + struct gpmc_device_timings *dev_t) { + bool mux = dev_t->mux; u32 temp; /* adv_wr_off */ @@ -1054,8 +1054,7 @@ static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, } static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, - struct gpmc_device_timings *dev_t, - bool sync) + struct gpmc_device_timings *dev_t) { u32 temp; @@ -1069,7 +1068,7 @@ static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, gpmc_t->cs_on + dev_t->t_ce_avd); gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); - if (sync) + if (dev_t->sync_write || dev_t->sync_read) gpmc_calc_sync_common_timings(gpmc_t, dev_t); return 0; @@ -1104,116 +1103,27 @@ static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) } int gpmc_calc_timings(struct gpmc_timings *gpmc_t, - struct gpmc_settings *gpmc_s, - struct gpmc_device_timings *dev_t) + struct gpmc_device_timings *dev_t) { - bool mux = false, sync = false; - - if (gpmc_s) { - mux = gpmc_s->mux_add_data ? true : false; - sync = (gpmc_s->sync_read || gpmc_s->sync_write); - } - memset(gpmc_t, 0, sizeof(*gpmc_t)); - gpmc_calc_common_timings(gpmc_t, dev_t, sync); + gpmc_calc_common_timings(gpmc_t, dev_t); - if (gpmc_s && gpmc_s->sync_read) - gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); + if (dev_t->sync_read) + gpmc_calc_sync_read_timings(gpmc_t, dev_t); else - gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); + gpmc_calc_async_read_timings(gpmc_t, dev_t); - if (gpmc_s && gpmc_s->sync_write) - gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); + if (dev_t->sync_write) + gpmc_calc_sync_write_timings(gpmc_t, dev_t); else - gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); + gpmc_calc_async_write_timings(gpmc_t, dev_t); /* TODO: remove, see function definition */ gpmc_convert_ps_to_ns(gpmc_t); - return 0; -} - -/** - * gpmc_cs_program_settings - programs non-timing related settings - * @cs: GPMC chip-select to program - * @p: pointer to GPMC settings structure - * - * Programs non-timing related settings for a GPMC chip-select, such as - * bus-width, burst configuration, etc. Function should be called once - * for each chip-select that is being used and must be called before - * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 - * register will be initialised to zero by this function. Returns 0 on - * success and appropriate negative error code on failure. - */ -int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) -{ - u32 config1; - - if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { - pr_err("%s: invalid width %d!", __func__, p->device_width); - return -EINVAL; - } - - /* Address-data multiplexing not supported for NAND devices */ - if (p->device_nand && p->mux_add_data) { - pr_err("%s: invalid configuration!\n", __func__); - return -EINVAL; - } - - if ((p->mux_add_data > GPMC_MUX_AD) || - ((p->mux_add_data == GPMC_MUX_AAD) && - !(gpmc_capability & GPMC_HAS_MUX_AAD))) { - pr_err("%s: invalid multiplex configuration!\n", __func__); - return -EINVAL; - } - - /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ - if (p->burst_read || p->burst_write) { - switch (p->burst_len) { - case GPMC_BURST_4: - case GPMC_BURST_8: - case GPMC_BURST_16: - break; - default: - pr_err("%s: invalid page/burst-length (%d)\n", - __func__, p->burst_len); - return -EINVAL; - } - } - - if ((p->wait_on_read || p->wait_on_write) && - (p->wait_pin > gpmc_nr_waitpins)) { - pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); - return -EINVAL; - } - - config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); - - if (p->sync_read) - config1 |= GPMC_CONFIG1_READTYPE_SYNC; - if (p->sync_write) - config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; - if (p->wait_on_read) - config1 |= GPMC_CONFIG1_WAIT_READ_MON; - if (p->wait_on_write) - config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; - if (p->wait_on_read || p->wait_on_write) - config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); - if (p->device_nand) - config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); - if (p->mux_add_data) - config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); - if (p->burst_read) - config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; - if (p->burst_write) - config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; - if (p->burst_read || p->burst_write) { - config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); - config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; - } - - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); + /* Now the GPMC is initialised, unreserve the chip-selects */ + gpmc_cs_map = 0; return 0; } @@ -1229,110 +1139,70 @@ static struct of_device_id gpmc_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, gpmc_dt_ids); -/** - * gpmc_read_settings_dt - read gpmc settings from device-tree - * @np: pointer to device-tree node for a gpmc child device - * @p: pointer to gpmc settings structure - * - * Reads the GPMC settings for a GPMC child device from device-tree and - * stores them in the GPMC settings structure passed. The GPMC settings - * structure is initialised to zero by this function and so any - * previously stored settings will be cleared. - */ -void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) -{ - memset(p, 0, sizeof(struct gpmc_settings)); - - p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); - p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); - p->device_nand = of_property_read_bool(np, "gpmc,device-nand"); - of_property_read_u32(np, "gpmc,device-width", &p->device_width); - of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); - - if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { - p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); - p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); - p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); - if (!p->burst_read && !p->burst_write) - pr_warn("%s: page/burst-length set but not used!\n", - __func__); - } - - if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { - p->wait_on_read = of_property_read_bool(np, - "gpmc,wait-on-read"); - p->wait_on_write = of_property_read_bool(np, - "gpmc,wait-on-write"); - if (!p->wait_on_read && !p->wait_on_write) - pr_warn("%s: read/write wait monitoring not enabled!\n", - __func__); - } -} - static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, struct gpmc_timings *gpmc_t) { - struct gpmc_bool_timings *p; - - if (!np || !gpmc_t) - return; + u32 val; memset(gpmc_t, 0, sizeof(*gpmc_t)); /* minimum clock period for syncronous mode */ - of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); + if (!of_property_read_u32(np, "gpmc,sync-clk", &val)) + gpmc_t->sync_clk = val; /* chip select timtings */ - of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); - of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); - of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); + if (!of_property_read_u32(np, "gpmc,cs-on", &val)) + gpmc_t->cs_on = val; + + if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val)) + gpmc_t->cs_rd_off = val; + + if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val)) + gpmc_t->cs_wr_off = val; /* ADV signal timings */ - of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); - of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); - of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); + if (!of_property_read_u32(np, "gpmc,adv-on", &val)) + gpmc_t->adv_on = val; + + if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val)) + gpmc_t->adv_rd_off = val; + + if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val)) + gpmc_t->adv_wr_off = val; /* WE signal timings */ - of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); - of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); + if (!of_property_read_u32(np, "gpmc,we-on", &val)) + gpmc_t->we_on = val; + + if (!of_property_read_u32(np, "gpmc,we-off", &val)) + gpmc_t->we_off = val; /* OE signal timings */ - of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); - of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); + if (!of_property_read_u32(np, "gpmc,oe-on", &val)) + gpmc_t->oe_on = val; + + if (!of_property_read_u32(np, "gpmc,oe-off", &val)) + gpmc_t->oe_off = val; /* access and cycle timings */ - of_property_read_u32(np, "gpmc,page-burst-access-ns", - &gpmc_t->page_burst_access); - of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); - of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); - of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); - of_property_read_u32(np, "gpmc,bus-turnaround-ns", - &gpmc_t->bus_turnaround); - of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", - &gpmc_t->cycle2cycle_delay); - of_property_read_u32(np, "gpmc,wait-monitoring-ns", - &gpmc_t->wait_monitoring); - of_property_read_u32(np, "gpmc,clk-activation-ns", - &gpmc_t->clk_activation); - - /* only applicable to OMAP3+ */ - of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); - of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", - &gpmc_t->wr_data_mux_bus); - - /* bool timing parameters */ - p = &gpmc_t->bool_timings; - - p->cycle2cyclediffcsen = - of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); - p->cycle2cyclesamecsen = - of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); - p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); - p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); - p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); - p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); - p->time_para_granularity = - of_property_read_bool(np, "gpmc,time-para-granularity"); + if (!of_property_read_u32(np, "gpmc,page-burst-access", &val)) + gpmc_t->page_burst_access = val; + + if (!of_property_read_u32(np, "gpmc,access", &val)) + gpmc_t->access = val; + + if (!of_property_read_u32(np, "gpmc,rd-cycle", &val)) + gpmc_t->rd_cycle = val; + + if (!of_property_read_u32(np, "gpmc,wr-cycle", &val)) + gpmc_t->wr_cycle = val; + + /* only for OMAP3430 */ + if (!of_property_read_u32(np, "gpmc,wr-access", &val)) + gpmc_t->wr_access = val; + + if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val)) + gpmc_t->wr_data_mux_bus = val; } #ifdef CONFIG_MTD_NAND @@ -1428,81 +1298,6 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev, } #endif -/** - * gpmc_probe_generic_child - configures the gpmc for a child device - * @pdev: pointer to gpmc platform device - * @child: pointer to device-tree node for child device - * - * Allocates and configures a GPMC chip-select for a child device. - * Returns 0 on success and appropriate negative error code on failure. - */ -static int gpmc_probe_generic_child(struct platform_device *pdev, - struct device_node *child) -{ - struct gpmc_settings gpmc_s; - struct gpmc_timings gpmc_t; - struct resource res; - unsigned long base; - int ret, cs; - - if (of_property_read_u32(child, "reg", &cs) < 0) { - dev_err(&pdev->dev, "%s has no 'reg' property\n", - child->full_name); - return -ENODEV; - } - - if (of_address_to_resource(child, 0, &res) < 0) { - dev_err(&pdev->dev, "%s has malformed 'reg' property\n", - child->full_name); - return -ENODEV; - } - - ret = gpmc_cs_request(cs, resource_size(&res), &base); - if (ret < 0) { - dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); - return ret; - } - - /* - * FIXME: gpmc_cs_request() will map the CS to an arbitary - * location in the gpmc address space. When booting with - * device-tree we want the NOR flash to be mapped to the - * location specified in the device-tree blob. So remap the - * CS to this location. Once DT migration is complete should - * just make gpmc_cs_request() map a specific address. - */ - ret = gpmc_cs_remap(cs, res.start); - if (ret < 0) { - dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n", - cs, res.start); - goto err; - } - - gpmc_read_settings_dt(child, &gpmc_s); - - ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width); - if (ret < 0) - goto err; - - ret = gpmc_cs_program_settings(cs, &gpmc_s); - if (ret < 0) - goto err; - - gpmc_read_timings_dt(child, &gpmc_t); - gpmc_cs_set_timings(cs, &gpmc_t); - - if (of_platform_device_create(child, NULL, &pdev->dev)) - return 0; - - dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name); - ret = -ENODEV; - -err: - gpmc_cs_free(cs); - - return ret; -} - static int gpmc_probe_dt(struct platform_device *pdev) { int ret; @@ -1513,13 +1308,6 @@ static int gpmc_probe_dt(struct platform_device *pdev) if (!of_id) return 0; - ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", - &gpmc_nr_waitpins); - if (ret < 0) { - pr_err("%s: number of wait pins not found!\n", __func__); - return ret; - } - for_each_node_by_name(child, "nand") { ret = gpmc_probe_nand_child(pdev, child); if (ret < 0) { @@ -1535,23 +1323,6 @@ static int gpmc_probe_dt(struct platform_device *pdev) return ret; } } - - for_each_node_by_name(child, "nor") { - ret = gpmc_probe_generic_child(pdev, child); - if (ret < 0) { - of_node_put(child); - return ret; - } - } - - for_each_node_by_name(child, "ethernet") { - ret = gpmc_probe_generic_child(pdev, child); - if (ret < 0) { - of_node_put(child); - return ret; - } - } - return 0; } #else @@ -1596,37 +1367,22 @@ static int gpmc_probe(struct platform_device *pdev) gpmc_dev = &pdev->dev; l = gpmc_read_reg(GPMC_REVISION); - - /* - * FIXME: Once device-tree migration is complete the below flags - * should be populated based upon the device-tree compatible - * string. For now just use the IP revision. OMAP3+ devices have - * the wr_access and wr_data_mux_bus register fields. OMAP4+ - * devices support the addr-addr-data multiplex protocol. - * - * GPMC IP revisions: - * - OMAP24xx = 2.0 - * - OMAP3xxx = 5.0 - * - OMAP44xx/54xx/AM335x = 6.0 - */ if (GPMC_REVISION_MAJOR(l) > 0x4) gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; - if (GPMC_REVISION_MAJOR(l) > 0x5) - gpmc_capability |= GPMC_HAS_MUX_AAD; dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), GPMC_REVISION_MINOR(l)); - gpmc_mem_init(); + rc = gpmc_mem_init(); + if (IS_ERR_VALUE(rc)) { + clk_disable_unprepare(gpmc_l3_clk); + clk_put(gpmc_l3_clk); + dev_err(gpmc_dev, "failed to reserve memory\n"); + return rc; + } - if (gpmc_setup_irq() < 0) + if (IS_ERR_VALUE(gpmc_setup_irq())) dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); - /* Now the GPMC is initialised, unreserve the chip-selects */ - gpmc_cs_map = 0; - - if (!pdev->dev.of_node) - gpmc_nr_waitpins = GPMC_NR_WAITPINS; - rc = gpmc_probe_dt(pdev); if (rc < 0) { clk_disable_unprepare(gpmc_l3_clk); diff --git a/trunk/arch/arm/mach-omap2/gpmc.h b/trunk/arch/arm/mach-omap2/gpmc.h index 707f6d58edd5..fe0a844d5007 100644 --- a/trunk/arch/arm/mach-omap2/gpmc.h +++ b/trunk/arch/arm/mach-omap2/gpmc.h @@ -58,7 +58,7 @@ #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) -#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) +#define GPMC_CONFIG1_MUXADDDATA (1 << 9) #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) @@ -73,13 +73,6 @@ #define GPMC_IRQ_FIFOEVENTENABLE 0x01 #define GPMC_IRQ_COUNT_EVENT 0x02 -#define GPMC_BURST_4 4 /* 4 word burst */ -#define GPMC_BURST_8 8 /* 8 word burst */ -#define GPMC_BURST_16 16 /* 16 word burst */ -#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */ -#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */ -#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */ -#define GPMC_MUX_AD 2 /* Addr-Data multiplex */ /* bool type time settings */ struct gpmc_bool_timings { @@ -185,6 +178,10 @@ struct gpmc_device_timings { u8 cyc_wpl; /* write deassertion time in cycles */ u32 cyc_iaa; /* initial access time in cycles */ + bool mux; /* address & data muxed */ + bool sync_write;/* synchronous write */ + bool sync_read; /* synchronous read */ + /* extra delays */ bool ce_xdelay; bool avd_xdelay; @@ -192,40 +189,28 @@ struct gpmc_device_timings { bool we_xdelay; }; -struct gpmc_settings { - bool burst_wrap; /* enables wrap bursting */ - bool burst_read; /* enables read page/burst mode */ - bool burst_write; /* enables write page/burst mode */ - bool device_nand; /* device is NAND */ - bool sync_read; /* enables synchronous reads */ - bool sync_write; /* enables synchronous writes */ - bool wait_on_read; /* monitor wait on reads */ - bool wait_on_write; /* monitor wait on writes */ - u32 burst_len; /* page/burst length */ - u32 device_width; /* device bus width (8 or 16 bit) */ - u32 mux_add_data; /* multiplex address & data */ - u32 wait_pin; /* wait-pin to be used */ -}; - extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t, - struct gpmc_settings *gpmc_s, - struct gpmc_device_timings *dev_t); + struct gpmc_device_timings *dev_t); extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); extern int gpmc_get_client_irq(unsigned irq_config); +extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); +extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); +extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); +extern unsigned long gpmc_get_fclk_period(void); extern void gpmc_cs_write_reg(int cs, int idx, u32 val); +extern u32 gpmc_cs_read_reg(int cs, int idx); extern int gpmc_calc_divider(unsigned int sync_clk); extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); -extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p); extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); extern void gpmc_cs_free(int cs); +extern int gpmc_cs_set_reserved(int cs, int reserved); +extern int gpmc_cs_reserved(int cs); extern void omap3_gpmc_save_context(void); extern void omap3_gpmc_restore_context(void); -extern int gpmc_configure(int cmd, int wval); -extern void gpmc_read_settings_dt(struct device_node *np, - struct gpmc_settings *p); +extern int gpmc_cs_configure(int cs, int cmd, int wval); #endif diff --git a/trunk/arch/arm/mach-omap2/id.c b/trunk/arch/arm/mach-omap2/id.c index ff0bc9e51aa7..8a68f1ec66b9 100644 --- a/trunk/arch/arm/mach-omap2/id.c +++ b/trunk/arch/arm/mach-omap2/id.c @@ -529,28 +529,22 @@ void __init omap5xxx_check_revision(void) case 0xb942: switch (rev) { case 0: - omap_revision = OMAP5430_REV_ES1_0; - break; - case 1: default: - omap_revision = OMAP5430_REV_ES2_0; + omap_revision = OMAP5430_REV_ES1_0; } break; case 0xb998: switch (rev) { case 0: - omap_revision = OMAP5432_REV_ES1_0; - break; - case 1: default: - omap_revision = OMAP5432_REV_ES2_0; + omap_revision = OMAP5432_REV_ES1_0; } break; default: /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP5430_REV_ES2_0; + omap_revision = OMAP5430_REV_ES1_0; } pr_info("OMAP%04x ES%d.0\n", diff --git a/trunk/arch/arm/mach-omap2/io.c b/trunk/arch/arm/mach-omap2/io.c index 2bef5a7e6af8..2c3fdd65387b 100644 --- a/trunk/arch/arm/mach-omap2/io.c +++ b/trunk/arch/arm/mach-omap2/io.c @@ -271,14 +271,6 @@ static struct map_desc omap54xx_io_desc[] __initdata = { .length = L4_PER_54XX_SIZE, .type = MT_DEVICE, }, -#ifdef CONFIG_OMAP4_ERRATA_I688 - { - .virtual = OMAP4_SRAM_VA, - .pfn = __phys_to_pfn(OMAP4_SRAM_PA), - .length = PAGE_SIZE, - .type = MT_MEMORY_SO, - }, -#endif }; #endif @@ -331,7 +323,6 @@ void __init omap4_map_io(void) void __init omap5_map_io(void) { iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); - omap_barriers_init(); } #endif /* diff --git a/trunk/arch/arm/mach-omap2/mux.c b/trunk/arch/arm/mach-omap2/mux.c index f82cf878d6af..6a217c98db54 100644 --- a/trunk/arch/arm/mach-omap2/mux.c +++ b/trunk/arch/arm/mach-omap2/mux.c @@ -211,6 +211,8 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition, return -EINVAL; } + pr_err("%s: Could not find signal %s\n", __func__, muxname); + return -ENODEV; } @@ -232,8 +234,6 @@ int __init omap_mux_get_by_name(const char *muxname, return mux_mode; } - pr_err("%s: Could not find signal %s\n", __func__, muxname); - return -ENODEV; } @@ -739,9 +739,8 @@ static void __init omap_mux_dbg_create_entry( list_for_each_entry(e, &partition->muxmodes, node) { struct omap_mux *m = &e->mux; - (void)debugfs_create_file(m->muxnames[0], S_IWUSR | S_IRUGO, - mux_dbg_dir, m, - &omap_mux_dbg_signal_fops); + (void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir, + m, &omap_mux_dbg_signal_fops); } } diff --git a/trunk/arch/arm/mach-omap2/omap4-common.c b/trunk/arch/arm/mach-omap2/omap4-common.c index 2aeb928efdfd..708bb115a27f 100644 --- a/trunk/arch/arm/mach-omap2/omap4-common.c +++ b/trunk/arch/arm/mach-omap2/omap4-common.c @@ -240,21 +240,15 @@ void __iomem *omap4_get_sar_ram_base(void) */ static int __init omap4_sar_ram_init(void) { - unsigned long sar_base; - /* * To avoid code running on other OMAPs in * multi-omap builds */ - if (cpu_is_omap44xx()) - sar_base = OMAP44XX_SAR_RAM_BASE; - else if (soc_is_omap54xx()) - sar_base = OMAP54XX_SAR_RAM_BASE; - else + if (!cpu_is_omap44xx()) return -ENOMEM; /* Static mapping, never released */ - sar_ram_base = ioremap(sar_base, SZ_16K); + sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); if (WARN_ON(!sar_ram_base)) return -ENOMEM; diff --git a/trunk/arch/arm/mach-omap2/omap4-sar-layout.h b/trunk/arch/arm/mach-omap2/omap4-sar-layout.h index 937417523b8e..e170fe803b04 100644 --- a/trunk/arch/arm/mach-omap2/omap4-sar-layout.h +++ b/trunk/arch/arm/mach-omap2/omap4-sar-layout.h @@ -48,13 +48,13 @@ #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ -#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) -#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) -#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) -#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) -#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) -#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) -#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) +#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4) +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8) +#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc) +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910) +#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924) +#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928) +#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c) #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) #endif diff --git a/trunk/arch/arm/mach-omap2/omap54xx.h b/trunk/arch/arm/mach-omap2/omap54xx.h index a086ba15868b..a2582bb3cab3 100644 --- a/trunk/arch/arm/mach-omap2/omap54xx.h +++ b/trunk/arch/arm/mach-omap2/omap54xx.h @@ -28,6 +28,5 @@ #define OMAP54XX_PRCM_MPU_BASE 0x48243000 #define OMAP54XX_SCM_BASE 0x4a002000 #define OMAP54XX_CTRL_BASE 0x4a002800 -#define OMAP54XX_SAR_RAM_BASE 0x4ae26000 #endif /* __ASM_SOC_OMAP555554XX_H */ diff --git a/trunk/arch/arm/mach-omap2/omap_device.c b/trunk/arch/arm/mach-omap2/omap_device.c index eeea4fa28fbc..381be7ac0c17 100644 --- a/trunk/arch/arm/mach-omap2/omap_device.c +++ b/trunk/arch/arm/mach-omap2/omap_device.c @@ -131,7 +131,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev) int oh_cnt, i, ret = 0; oh_cnt = of_property_count_strings(node, "ti,hwmods"); - if (oh_cnt <= 0) { + if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) { dev_dbg(&pdev->dev, "No 'hwmods' to build omap_device\n"); return -ENODEV; } @@ -815,17 +815,20 @@ struct device *omap_device_get_by_hwmod_name(const char *oh_name) } oh = omap_hwmod_lookup(oh_name); - if (!oh) { + if (IS_ERR_OR_NULL(oh)) { WARN(1, "%s: no hwmod for %s\n", __func__, oh_name); - return ERR_PTR(-ENODEV); + return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV); } - if (!oh->od) { + if (IS_ERR_OR_NULL(oh->od)) { WARN(1, "%s: no omap_device for %s\n", __func__, oh_name); - return ERR_PTR(-ENODEV); + return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV); } + if (IS_ERR_OR_NULL(oh->od->pdev)) + return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV); + return &oh->od->pdev->dev; } diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.c b/trunk/arch/arm/mach-omap2/omap_hwmod.c index 2520d46c8508..c2c798c08c2b 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.c @@ -610,6 +610,8 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) /* XXX test pwrdm_get_wken for this hwmod's subsystem */ + oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; + return 0; } @@ -643,6 +645,8 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) /* XXX test pwrdm_get_wken for this hwmod's subsystem */ + oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; + return 0; } @@ -1659,7 +1663,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) return -ENOSYS; ret = _lookup_hardreset(oh, name, &ohri); - if (ret < 0) + if (IS_ERR_VALUE(ret)) return ret; if (oh->clkdm) { @@ -2409,7 +2413,7 @@ static int __init _init(struct omap_hwmod *oh, void *data) _init_mpu_rt_base(oh, NULL); r = _init_clocks(oh, NULL); - if (r < 0) { + if (IS_ERR_VALUE(r)) { WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); return -EINVAL; } diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.h b/trunk/arch/arm/mach-omap2/omap_hwmod.h index 28f4dea0512e..d43d9b608eda 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.h +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.h @@ -477,13 +477,15 @@ struct omap_hwmod_omap4_prcm { * These are for internal use only and are managed by the omap_hwmod code. * * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module + * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - * causes the first call to _enable() to only update the pinmux */ #define _HWMOD_NO_MPU_PORT (1 << 0) -#define _HWMOD_SYSCONFIG_LOADED (1 << 1) -#define _HWMOD_SKIP_ENABLE (1 << 2) +#define _HWMOD_WAKEUP_ENABLED (1 << 1) +#define _HWMOD_SYSCONFIG_LOADED (1 << 2) +#define _HWMOD_SKIP_ENABLE (1 << 3) /* * omap_hwmod._state definitions diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 31bea1ce3de1..26eee4a556ad 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -28,7 +28,6 @@ #include "prm-regbits-33xx.h" #include "i2c.h" #include "mmc.h" -#include "wd_timer.h" /* * IP blocks @@ -2088,21 +2087,8 @@ static struct omap_hwmod am33xx_uart6_hwmod = { }; /* 'wd_timer' class */ -static struct omap_hwmod_class_sysconfig wdt_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x10, - .syss_offs = 0x14, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { .name = "wd_timer", - .sysc = &wdt_sysc, - .pre_shutdown = &omap2_wd_timer_disable, }; /* @@ -2113,7 +2099,6 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = { .name = "wd_timer2", .class = &am33xx_wd_timer_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_SWSUP_SIDLE, .main_clk = "wdt1_fck", .prcm = { .omap4 = { diff --git a/trunk/arch/arm/mach-omap2/pm-debug.c b/trunk/arch/arm/mach-omap2/pm-debug.c index 0b339861d751..1edd000a8143 100644 --- a/trunk/arch/arm/mach-omap2/pm-debug.c +++ b/trunk/arch/arm/mach-omap2/pm-debug.c @@ -217,7 +217,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir) return 0; d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir); - if (d) + if (!(IS_ERR_OR_NULL(d))) (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d, (void *)pwrdm, &pwrdm_suspend_fops); @@ -261,8 +261,8 @@ static int __init pm_dbg_init(void) return 0; d = debugfs_create_dir("pm_debug", NULL); - if (!d) - return -EINVAL; + if (IS_ERR_OR_NULL(d)) + return PTR_ERR(d); (void) debugfs_create_file("count", S_IRUGO, d, (void *)DEBUG_FILE_COUNTERS, &debug_fops); diff --git a/trunk/arch/arm/mach-omap2/powerdomain.c b/trunk/arch/arm/mach-omap2/powerdomain.c index 86babd740d41..8e61d80bf6b3 100644 --- a/trunk/arch/arm/mach-omap2/powerdomain.c +++ b/trunk/arch/arm/mach-omap2/powerdomain.c @@ -52,6 +52,7 @@ enum { #define ALREADYACTIVE_SWITCH 0 #define FORCEWAKEUP_SWITCH 1 #define LOWPOWERSTATE_SWITCH 2 +#define ERROR_SWITCH 3 /* pwrdm_list contains all registered struct powerdomains */ static LIST_HEAD(pwrdm_list); @@ -232,7 +233,10 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm, { u8 sleep_switch; - if (curr_pwrst < PWRDM_POWER_ON) { + if (curr_pwrst < 0) { + WARN_ON(1); + sleep_switch = ERROR_SWITCH; + } else if (curr_pwrst < PWRDM_POWER_ON) { if (curr_pwrst > pwrst && pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE && arch_pwrdm->pwrdm_set_lowpwrstchange) { @@ -1087,8 +1091,7 @@ int pwrdm_post_transition(struct powerdomain *pwrdm) */ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) { - u8 next_pwrst, sleep_switch; - int curr_pwrst; + u8 curr_pwrst, next_pwrst, sleep_switch; int ret = 0; bool hwsup = false; @@ -1104,17 +1107,16 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) pwrdm_lock(pwrdm); curr_pwrst = pwrdm_read_pwrst(pwrdm); - if (curr_pwrst < 0) { - ret = -EINVAL; - goto osps_out; - } - next_pwrst = pwrdm_read_next_pwrst(pwrdm); if (curr_pwrst == pwrst && next_pwrst == pwrst) goto osps_out; sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst, pwrst, &hwsup); + if (sleep_switch == ERROR_SWITCH) { + ret = -EINVAL; + goto osps_out; + } ret = pwrdm_set_next_pwrst(pwrdm, pwrst); if (ret) @@ -1180,7 +1182,7 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm) { int i; - if (!pwrdm) { + if (IS_ERR_OR_NULL(pwrdm)) { pr_debug("powerdomain: %s: invalid powerdomain pointer\n", __func__); return 1; diff --git a/trunk/arch/arm/mach-omap2/prm44xx.c b/trunk/arch/arm/mach-omap2/prm44xx.c index 415c7e0c9393..d35f98aabf7a 100644 --- a/trunk/arch/arm/mach-omap2/prm44xx.c +++ b/trunk/arch/arm/mach-omap2/prm44xx.c @@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { /* Read a register in a CM/PRM instance in the PRM module */ u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) { - return __raw_readl(prm_base + inst + reg); + return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); } /* Write into a register in a CM/PRM instance in the PRM module */ void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) { - __raw_writel(val, prm_base + inst + reg); + __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); } /* Read-modify-write a register in a PRM module. Caller must lock */ @@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = { int __init omap44xx_prm_init(void) { - if (!cpu_is_omap44xx() && !soc_is_omap54xx()) + if (!cpu_is_omap44xx()) return 0; return prm_register(&omap44xx_prm_ll_data); diff --git a/trunk/arch/arm/mach-omap2/soc.h b/trunk/arch/arm/mach-omap2/soc.h index 18fdeeb3a44a..c62116bbc760 100644 --- a/trunk/arch/arm/mach-omap2/soc.h +++ b/trunk/arch/arm/mach-omap2/soc.h @@ -413,9 +413,7 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP54XX_CLASS 0x54000054 #define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) -#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) #define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) -#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) void omap2xxx_check_revision(void); void omap3xxx_check_revision(void); diff --git a/trunk/arch/arm/mach-omap2/timer.c b/trunk/arch/arm/mach-omap2/timer.c index f12aa6c15da4..2bdd4cf17a8f 100644 --- a/trunk/arch/arm/mach-omap2/timer.c +++ b/trunk/arch/arm/mach-omap2/timer.c @@ -57,6 +57,15 @@ #include "common.h" #include "powerdomain.h" +/* Parent clocks, eventually these will come from the clock framework */ + +#define OMAP2_MPU_SOURCE "sys_ck" +#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE +#define OMAP4_MPU_SOURCE "sys_clkin_ck" +#define OMAP2_32K_SOURCE "func_32k_ck" +#define OMAP3_32K_SOURCE "omap_32k_fck" +#define OMAP4_32K_SOURCE "sys_32k_ck" + #define REALTIME_COUNTER_BASE 0x48243200 #define INCREMENTER_NUMERATOR_OFFSET 0x10 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 @@ -120,6 +129,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, } static struct clock_event_device clockevent_gpt = { + .name = "gp_timer", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .rating = 300, .set_next_event = omap2_gp_timer_set_next_event, @@ -160,12 +170,6 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, if (property && !of_get_property(np, property, NULL)) continue; - if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || - of_get_property(np, "ti,timer-dsp", NULL) || - of_get_property(np, "ti,timer-pwm", NULL) || - of_get_property(np, "ti,timer-secure", NULL))) - continue; - of_add_property(np, &device_disabled); return np; } @@ -210,17 +214,16 @@ static u32 __init omap_dm_timer_get_errata(void) } static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, - const char *fck_source, - const char *property, - const char **timer_name, - int posted) + int gptimer_id, + const char *fck_source, + const char *property, + int posted) { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ const char *oh_name; struct device_node *np; struct omap_hwmod *oh; struct resource irq, mem; - struct clk *src; int r = 0; if (of_have_populated_dt()) { @@ -240,10 +243,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, of_node_put(np); } else { - if (omap_dm_timer_reserve_systimer(timer->id)) + if (omap_dm_timer_reserve_systimer(gptimer_id)) return -ENODEV; - sprintf(name, "timer%d", timer->id); + sprintf(name, "timer%d", gptimer_id); oh_name = name; } @@ -251,8 +254,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, if (!oh) return -ENODEV; - *timer_name = oh->name; - if (!of_have_populated_dt()) { r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq); @@ -275,24 +276,24 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, /* After the dmtimer is using hwmod these clocks won't be needed */ timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); if (IS_ERR(timer->fclk)) - return PTR_ERR(timer->fclk); - - src = clk_get(NULL, fck_source); - if (IS_ERR(src)) - return PTR_ERR(src); + return -ENODEV; - if (clk_get_parent(timer->fclk) != src) { - r = clk_set_parent(timer->fclk, src); - if (r < 0) { - pr_warn("%s: %s cannot set source\n", __func__, - oh->name); + /* FIXME: Need to remove hard-coded test on timer ID */ + if (gptimer_id != 12) { + struct clk *src; + + src = clk_get(NULL, fck_source); + if (IS_ERR(src)) { + r = -EINVAL; + } else { + r = clk_set_parent(timer->fclk, src); + if (IS_ERR_VALUE(r)) + pr_warn("%s: %s cannot set source\n", + __func__, oh->name); clk_put(src); - return r; } } - clk_put(src); - omap_hwmod_setup_one(oh_name); omap_hwmod_enable(oh); __omap_dm_timer_init_regs(timer); @@ -316,7 +317,6 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, { int res; - clkev.id = gptimer_id; clkev.errata = omap_dm_timer_get_errata(); /* @@ -326,8 +326,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, */ __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); - res = omap_dm_timer_init_one(&clkev, fck_source, property, - &clockevent_gpt.name, OMAP_TIMER_POSTED); + res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, + OMAP_TIMER_POSTED); BUG_ON(res); omap2_gp_timer_irq.dev_id = &clkev; @@ -341,8 +341,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, 3, /* Timer internal resynch latency */ 0xffffffff); - pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, - clkev.rate); + pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", + gptimer_id, clkev.rate); } /* Clocksource code */ @@ -359,6 +359,7 @@ static cycle_t clocksource_read_cycles(struct clocksource *cs) } static struct clocksource clocksource_gpt = { + .name = "gp_timer", .rating = 300, .read = clocksource_read_cycles, .mask = CLOCKSOURCE_MASK(32), @@ -441,16 +442,13 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void) } static void __init omap2_gptimer_clocksource_init(int gptimer_id, - const char *fck_source, - const char *property) + const char *fck_source) { int res; - clksrc.id = gptimer_id; clksrc.errata = omap_dm_timer_get_errata(); - res = omap_dm_timer_init_one(&clksrc, fck_source, property, - &clocksource_gpt.name, + res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL, OMAP_TIMER_NONPOSTED); BUG_ON(res); @@ -463,8 +461,8 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id, pr_err("Could not register clocksource %s\n", clocksource_gpt.name); else - pr_info("OMAP clocksource: %s at %lu Hz\n", - clocksource_gpt.name, clksrc.rate); + pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", + gptimer_id, clksrc.rate); } #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER @@ -489,7 +487,7 @@ static void __init realtime_counter_init(void) pr_err("%s: ioremap failed\n", __func__); return; } - sys_clk = clk_get(NULL, "sys_clkin"); + sys_clk = clk_get(NULL, "sys_clkin_ck"); if (IS_ERR(sys_clk)) { pr_err("%s: failed to get system clock handle\n", __func__); iounmap(base); @@ -546,52 +544,49 @@ static inline void __init realtime_counter_init(void) #endif #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ - clksrc_nr, clksrc_src, clksrc_prop) \ + clksrc_nr, clksrc_src) \ void __init omap##name##_gptimer_timer_init(void) \ { \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ - omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ - clksrc_prop); \ + omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \ } #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ - clksrc_nr, clksrc_src, clksrc_prop) \ + clksrc_nr, clksrc_src) \ void __init omap##name##_sync32k_timer_init(void) \ { \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ /* Enable the use of clocksource="gp_timer" kernel parameter */ \ if (use_gptimer_clksrc) \ - omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ - clksrc_prop); \ + omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\ else \ omap2_sync32k_clocksource_init(); \ } #ifdef CONFIG_ARCH_OMAP2 -OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", - 2, "timer_sys_ck", NULL); +OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon", + 2, OMAP2_MPU_SOURCE); #endif /* CONFIG_ARCH_OMAP2 */ #ifdef CONFIG_ARCH_OMAP3 -OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", - 2, "timer_sys_ck", NULL); -OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", - 2, "timer_sys_ck", NULL); +OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon", + 2, OMAP3_MPU_SOURCE); +OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure", + 2, OMAP3_MPU_SOURCE); +OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon", + 2, OMAP3_MPU_SOURCE); #endif /* CONFIG_ARCH_OMAP3 */ -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) -OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, - 1, "timer_sys_ck", "ti,timer-alwon"); -#endif - -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) -static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", - 2, "sys_clkin_ck", NULL); -#endif +#ifdef CONFIG_SOC_AM33XX +OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", + 2, OMAP4_MPU_SOURCE); +#endif /* CONFIG_SOC_AM33XX */ #ifdef CONFIG_ARCH_OMAP4 +OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", + 2, OMAP4_MPU_SOURCE); #ifdef CONFIG_LOCAL_TIMERS static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); void __init omap4_local_timer_init(void) @@ -602,7 +597,7 @@ void __init omap4_local_timer_init(void) int err; if (of_have_populated_dt()) { - clocksource_of_init(); + twd_local_timer_of_register(); return; } @@ -620,11 +615,13 @@ void __init omap4_local_timer_init(void) #endif /* CONFIG_ARCH_OMAP4 */ #ifdef CONFIG_SOC_OMAP5 +OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", + 2, OMAP4_MPU_SOURCE); void __init omap5_realtime_timer_init(void) { int err; - omap4_sync32k_timer_init(); + omap5_sync32k_timer_init(); realtime_counter_init(); err = arch_timer_of_register(); diff --git a/trunk/arch/arm/mach-omap2/usb-host.c b/trunk/arch/arm/mach-omap2/usb-host.c index aa27d7f5cbb7..5706bdccf45e 100644 --- a/trunk/arch/arm/mach-omap2/usb-host.c +++ b/trunk/arch/arm/mach-omap2/usb-host.c @@ -22,12 +22,8 @@ #include #include #include -#include -#include -#include -#include -#include -#include + +#include #include "soc.h" #include "omap_device.h" @@ -530,155 +526,3 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata) } #endif - -/* Template for PHY regulators */ -static struct fixed_voltage_config hsusb_reg_config = { - /* .supply_name filled later */ - .microvolts = 3300000, - .gpio = -1, /* updated later */ - .startup_delay = 70000, /* 70msec */ - .enable_high = 1, /* updated later */ - .enabled_at_boot = 0, /* keep in RESET */ - /* .init_data filled later */ -}; - -static const char *nop_name = "nop_usb_xceiv"; /* NOP PHY driver */ -static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */ - -/** - * usbhs_add_regulator - Add a gpio based fixed voltage regulator device - * @name: name for the regulator - * @dev_id: device id of the device this regulator supplies power to - * @dev_supply: supply name that the device expects - * @gpio: GPIO number - * @polarity: 1 - Active high, 0 - Active low - */ -static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply, - int gpio, int polarity) -{ - struct regulator_consumer_supply *supplies; - struct regulator_init_data *reg_data; - struct fixed_voltage_config *config; - struct platform_device *pdev; - int ret; - - supplies = kzalloc(sizeof(*supplies), GFP_KERNEL); - if (!supplies) - return -ENOMEM; - - supplies->supply = dev_supply; - supplies->dev_name = dev_id; - - reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL); - if (!reg_data) - return -ENOMEM; - - reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS; - reg_data->consumer_supplies = supplies; - reg_data->num_consumer_supplies = 1; - - config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config), - GFP_KERNEL); - if (!config) - return -ENOMEM; - - config->supply_name = name; - config->gpio = gpio; - config->enable_high = polarity; - config->init_data = reg_data; - - /* create a regulator device */ - pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); - if (!pdev) - return -ENOMEM; - - pdev->id = PLATFORM_DEVID_AUTO; - pdev->name = reg_name; - pdev->dev.platform_data = config; - - ret = platform_device_register(pdev); - if (ret) - pr_err("%s: Failed registering regulator %s for %s\n", - __func__, name, dev_id); - - return ret; -} - -int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) -{ - char *rail_name; - int i, len; - struct platform_device *pdev; - char *phy_id; - - /* the phy_id will be something like "nop_usb_xceiv.1" */ - len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */ - - for (i = 0; i < num_phys; i++) { - - if (!phy->port) { - pr_err("%s: Invalid port 0. Must start from 1\n", - __func__); - continue; - } - - /* do we need a NOP PHY device ? */ - if (!gpio_is_valid(phy->reset_gpio) && - !gpio_is_valid(phy->vcc_gpio)) - continue; - - /* create a NOP PHY device */ - pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); - if (!pdev) - return -ENOMEM; - - pdev->id = phy->port; - pdev->name = nop_name; - pdev->dev.platform_data = phy->platform_data; - - phy_id = kmalloc(len, GFP_KERNEL); - if (!phy_id) - return -ENOMEM; - - scnprintf(phy_id, len, "nop_usb_xceiv.%d\n", - pdev->id); - - if (platform_device_register(pdev)) { - pr_err("%s: Failed to register device %s\n", - __func__, phy_id); - continue; - } - - usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id); - - /* Do we need RESET regulator ? */ - if (gpio_is_valid(phy->reset_gpio)) { - - rail_name = kmalloc(13, GFP_KERNEL); - if (!rail_name) - return -ENOMEM; - - scnprintf(rail_name, 13, "hsusb%d_reset", phy->port); - - usbhs_add_regulator(rail_name, phy_id, "reset", - phy->reset_gpio, 1); - } - - /* Do we need VCC regulator ? */ - if (gpio_is_valid(phy->vcc_gpio)) { - - rail_name = kmalloc(13, GFP_KERNEL); - if (!rail_name) - return -ENOMEM; - - scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port); - - usbhs_add_regulator(rail_name, phy_id, "vcc", - phy->vcc_gpio, phy->vcc_polarity); - } - - phy++; - } - - return 0; -} diff --git a/trunk/arch/arm/mach-omap2/usb-tusb6010.c b/trunk/arch/arm/mach-omap2/usb-tusb6010.c index e832bc7b8e2d..c5a3c6f9504e 100644 --- a/trunk/arch/arm/mach-omap2/usb-tusb6010.c +++ b/trunk/arch/arm/mach-omap2/usb-tusb6010.c @@ -8,7 +8,6 @@ * published by the Free Software Foundation. */ -#include #include #include #include @@ -27,24 +26,6 @@ static u8 async_cs, sync_cs; static unsigned refclk_psec; -static struct gpmc_settings tusb_async = { - .wait_on_read = true, - .wait_on_write = true, - .device_width = GPMC_DEVWIDTH_16BIT, - .mux_add_data = GPMC_MUX_AD, -}; - -static struct gpmc_settings tusb_sync = { - .burst_read = true, - .burst_write = true, - .sync_read = true, - .sync_write = true, - .wait_on_read = true, - .wait_on_write = true, - .burst_len = GPMC_BURST_16, - .device_width = GPMC_DEVWIDTH_16BIT, - .mux_add_data = GPMC_MUX_AD, -}; /* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */ @@ -56,6 +37,8 @@ static int tusb_set_async_mode(unsigned sysclk_ps) memset(&dev_t, 0, sizeof(dev_t)); + dev_t.mux = true; + dev_t.t_ceasu = 8 * 1000; dev_t.t_avdasu = t_acsnh_advnh - 7000; dev_t.t_ce_avd = 1000; @@ -69,7 +52,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps) dev_t.t_wpl = 300; dev_t.cyc_aavdh_we = 1; - gpmc_calc_timings(&t, &tusb_async, &dev_t); + gpmc_calc_timings(&t, &dev_t); return gpmc_cs_set_timings(async_cs, &t); } @@ -82,6 +65,10 @@ static int tusb_set_sync_mode(unsigned sysclk_ps) memset(&dev_t, 0, sizeof(dev_t)); + dev_t.mux = true; + dev_t.sync_read = true; + dev_t.sync_write = true; + dev_t.clk = 11100; dev_t.t_bacc = 1000; dev_t.t_ces = 1000; @@ -97,7 +84,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps) dev_t.cyc_wpl = 6; dev_t.t_ce_rdyz = 7000; - gpmc_calc_timings(&t, &tusb_sync, &dev_t); + gpmc_calc_timings(&t, &dev_t); return gpmc_cs_set_timings(sync_cs, &t); } @@ -178,12 +165,18 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data, return status; } tusb_resources[0].end = tusb_resources[0].start + 0x9ff; - tusb_async.wait_pin = waitpin; async_cs = async; + gpmc_cs_write_reg(async, GPMC_CS_CONFIG1, + GPMC_CONFIG1_PAGE_LEN(2) + | GPMC_CONFIG1_WAIT_READ_MON + | GPMC_CONFIG1_WAIT_WRITE_MON + | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin) + | GPMC_CONFIG1_READTYPE_ASYNC + | GPMC_CONFIG1_WRITETYPE_ASYNC + | GPMC_CONFIG1_DEVICESIZE_16 + | GPMC_CONFIG1_DEVICETYPE_NOR + | GPMC_CONFIG1_MUXADDDATA); - status = gpmc_cs_program_settings(async_cs, &tusb_async); - if (status < 0) - return status; /* SYNC region, primarily for DMA */ status = gpmc_cs_request(sync, SZ_16M, (unsigned long *) @@ -193,12 +186,21 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data, return status; } tusb_resources[1].end = tusb_resources[1].start + 0x9ff; - tusb_sync.wait_pin = waitpin; sync_cs = sync; - - status = gpmc_cs_program_settings(sync_cs, &tusb_sync); - if (status < 0) - return status; + gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1, + GPMC_CONFIG1_READMULTIPLE_SUPP + | GPMC_CONFIG1_READTYPE_SYNC + | GPMC_CONFIG1_WRITEMULTIPLE_SUPP + | GPMC_CONFIG1_WRITETYPE_SYNC + | GPMC_CONFIG1_PAGE_LEN(2) + | GPMC_CONFIG1_WAIT_READ_MON + | GPMC_CONFIG1_WAIT_WRITE_MON + | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin) + | GPMC_CONFIG1_DEVICESIZE_16 + | GPMC_CONFIG1_DEVICETYPE_NOR + | GPMC_CONFIG1_MUXADDDATA + /* fclk divider gets set later */ + ); /* IRQ */ status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq"); diff --git a/trunk/arch/arm/mach-omap2/usb.h b/trunk/arch/arm/mach-omap2/usb.h index e7261ebcf7b0..3319f5cf47a3 100644 --- a/trunk/arch/arm/mach-omap2/usb.h +++ b/trunk/arch/arm/mach-omap2/usb.h @@ -53,17 +53,8 @@ #define USBPHY_OTGSESSEND_EN (1 << 20) #define USBPHY_DATA_POLARITY (1 << 23) -struct usbhs_phy_data { - int port; /* 1 indexed port number */ - int reset_gpio; - int vcc_gpio; - bool vcc_polarity; /* 1 active high, 0 active low */ - void *platform_data; -}; - extern void usb_musb_init(struct omap_musb_board_data *board_data); extern void usbhs_init(struct usbhs_omap_platform_data *pdata); -extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys); extern void am35x_musb_reset(void); extern void am35x_musb_phy_power(u8 on); diff --git a/trunk/arch/arm/mach-pxa/raumfeld.c b/trunk/arch/arm/mach-pxa/raumfeld.c index 969b0ba7fa70..af41888acbd6 100644 --- a/trunk/arch/arm/mach-pxa/raumfeld.c +++ b/trunk/arch/arm/mach-pxa/raumfeld.c @@ -505,7 +505,6 @@ static struct w1_gpio_platform_data w1_gpio_platform_data = { .pin = GPIO_ONE_WIRE, .is_open_drain = 0, .enable_external_pullup = w1_enable_external_pullup, - .ext_pullup_enable_pin = -EINVAL, }; struct platform_device raumfeld_w1_gpio_device = { diff --git a/trunk/arch/arm/mach-s3c24xx/Kconfig b/trunk/arch/arm/mach-s3c24xx/Kconfig index 0a8663c5f2ba..37f513d1588e 100644 --- a/trunk/arch/arm/mach-s3c24xx/Kconfig +++ b/trunk/arch/arm/mach-s3c24xx/Kconfig @@ -30,7 +30,6 @@ config CPU_S3C2410 select S3C2410_CLOCK select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX select S3C2410_PM if PM - select SAMSUNG_HRT help Support for S3C2410 and S3C2410A family from the S3C24XX line of Samsung Mobile CPUs. @@ -42,7 +41,6 @@ config CPU_S3C2412 select CPU_LLSERIAL_S3C2440 select S3C2412_DMA if S3C24XX_DMA select S3C2412_PM if PM - select SAMSUNG_HRT help Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line @@ -55,7 +53,6 @@ config CPU_S3C2416 select S3C2443_COMMON select S3C2443_DMA if S3C24XX_DMA select SAMSUNG_CLKSRC - select SAMSUNG_HRT help Support for the S3C2416 SoC from the S3C24XX line @@ -66,7 +63,6 @@ config CPU_S3C2440 select S3C2410_CLOCK select S3C2410_PM if PM select S3C2440_DMA if S3C24XX_DMA - select SAMSUNG_HRT help Support for S3C2440 Samsung Mobile CPU based systems. @@ -76,7 +72,6 @@ config CPU_S3C2442 select CPU_LLSERIAL_S3C2440 select S3C2410_CLOCK select S3C2410_PM if PM - select SAMSUNG_HRT help Support for S3C2442 Samsung Mobile CPU based systems. @@ -92,7 +87,6 @@ config CPU_S3C2443 select S3C2443_COMMON select S3C2443_DMA if S3C24XX_DMA select SAMSUNG_CLKSRC - select SAMSUNG_HRT help Support for the S3C2443 SoC from the S3C24XX line @@ -407,7 +401,6 @@ config S3C2412_DMA config S3C2412_PM bool select S3C2412_PM_SLEEP - select SAMSUNG_WAKEMASK help Internal config node to apply S3C2412 power management diff --git a/trunk/arch/arm/mach-s3c24xx/Makefile b/trunk/arch/arm/mach-s3c24xx/Makefile index 6f46ecfc8396..af53d27d5c36 100644 --- a/trunk/arch/arm/mach-s3c24xx/Makefile +++ b/trunk/arch/arm/mach-s3c24xx/Makefile @@ -14,7 +14,7 @@ obj- := # core -obj-y += common.o +obj-y += common.o irq.o obj-$(CONFIG_CPU_S3C2410) += s3c2410.o obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o @@ -22,7 +22,7 @@ obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o -obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o +obj-$(CONFIG_CPU_S3C2412) += s3c2412.o irq-s3c2412.o clock-s3c2412.o obj-$(CONFIG_S3C2412_CPUFREQ) += cpufreq-s3c2412.o obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o @@ -31,9 +31,9 @@ obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock-s3c2416.o obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o -obj-$(CONFIG_CPU_S3C2440) += s3c2440.o clock-s3c2440.o +obj-$(CONFIG_CPU_S3C2440) += s3c2440.o irq-s3c2440.o clock-s3c2440.o obj-$(CONFIG_CPU_S3C2442) += s3c2442.o -obj-$(CONFIG_CPU_S3C244X) += s3c244x.o clock-s3c244x.o +obj-$(CONFIG_CPU_S3C244X) += s3c244x.o irq-s3c244x.o clock-s3c244x.o obj-$(CONFIG_S3C2440_CPUFREQ) += cpufreq-s3c2440.o obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o diff --git a/trunk/arch/arm/mach-s3c24xx/bast-irq.c b/trunk/arch/arm/mach-s3c24xx/bast-irq.c index cb1b791954de..c0daa9590b4c 100644 --- a/trunk/arch/arm/mach-s3c24xx/bast-irq.c +++ b/trunk/arch/arm/mach-s3c24xx/bast-irq.c @@ -34,6 +34,8 @@ #include #include +#include + #include "bast.h" #define irqdbf(x...) diff --git a/trunk/arch/arm/mach-s3c24xx/clock-s3c2410.c b/trunk/arch/arm/mach-s3c24xx/clock-s3c2410.c index 34fffdf6fc1d..641266f3d152 100644 --- a/trunk/arch/arm/mach-s3c24xx/clock-s3c2410.c +++ b/trunk/arch/arm/mach-s3c24xx/clock-s3c2410.c @@ -40,6 +40,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/clock-s3c2412.c b/trunk/arch/arm/mach-s3c24xx/clock-s3c2412.c index 2cc017da88fe..d10b695a9066 100644 --- a/trunk/arch/arm/mach-s3c24xx/clock-s3c2412.c +++ b/trunk/arch/arm/mach-s3c24xx/clock-s3c2412.c @@ -41,6 +41,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/clock-s3c2416.c b/trunk/arch/arm/mach-s3c24xx/clock-s3c2416.c index 036056cea57c..14a81c2317a4 100644 --- a/trunk/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ b/trunk/arch/arm/mach-s3c24xx/clock-s3c2416.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/clock-s3c2443.c b/trunk/arch/arm/mach-s3c24xx/clock-s3c2443.c index 0a53051b0787..bdaba59b42dc 100644 --- a/trunk/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ b/trunk/arch/arm/mach-s3c24xx/clock-s3c2443.c @@ -41,6 +41,7 @@ #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/common-smdk.c b/trunk/arch/arm/mach-s3c24xx/common-smdk.c index 404444dd3840..3b2cf6db3634 100644 --- a/trunk/arch/arm/mach-s3c24xx/common-smdk.c +++ b/trunk/arch/arm/mach-s3c24xx/common-smdk.c @@ -41,12 +41,11 @@ #include +#include #include #include #include -#include "common-smdk.h" - /* LED devices */ static struct s3c24xx_led_platdata smdk_pdata_led4 = { diff --git a/trunk/arch/arm/mach-s3c24xx/common.c b/trunk/arch/arm/mach-s3c24xx/common.c index d97533d21ac4..6bcf87f65f9e 100644 --- a/trunk/arch/arm/mach-s3c24xx/common.c +++ b/trunk/arch/arm/mach-s3c24xx/common.c @@ -47,11 +47,14 @@ #include #include #include +#include +#include +#include +#include +#include #include #include -#include "common.h" - /* table of supported CPUs */ static const char name_s3c2410[] = "S3C2410"; diff --git a/trunk/arch/arm/mach-s3c24xx/common.h b/trunk/arch/arm/mach-s3c24xx/common.h index 307c3714be55..ed6276fcaa3b 100644 --- a/trunk/arch/arm/mach-s3c24xx/common.h +++ b/trunk/arch/arm/mach-s3c24xx/common.h @@ -12,98 +12,8 @@ #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__ -struct s3c2410_uartcfg; - -#ifdef CONFIG_CPU_S3C2410 -extern int s3c2410_init(void); -extern int s3c2410a_init(void); -extern void s3c2410_map_io(void); -extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2410_init_clocks(int xtal); -extern void s3c2410_restart(char mode, const char *cmd); -extern void s3c2410_init_irq(void); -#else -#define s3c2410_init_clocks NULL -#define s3c2410_init_uarts NULL -#define s3c2410_map_io NULL -#define s3c2410_init NULL -#define s3c2410a_init NULL -#endif - -#ifdef CONFIG_CPU_S3C2412 -extern int s3c2412_init(void); -extern void s3c2412_map_io(void); -extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2412_init_clocks(int xtal); -extern int s3c2412_baseclk_add(void); -extern void s3c2412_restart(char mode, const char *cmd); -extern void s3c2412_init_irq(void); -#else -#define s3c2412_init_clocks NULL -#define s3c2412_init_uarts NULL -#define s3c2412_map_io NULL -#define s3c2412_init NULL -#endif - -#ifdef CONFIG_CPU_S3C2416 -extern int s3c2416_init(void); -extern void s3c2416_map_io(void); -extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2416_init_clocks(int xtal); -extern int s3c2416_baseclk_add(void); -extern void s3c2416_restart(char mode, const char *cmd); -extern void s3c2416_init_irq(void); - -extern struct syscore_ops s3c2416_irq_syscore_ops; -#else -#define s3c2416_init_clocks NULL -#define s3c2416_init_uarts NULL -#define s3c2416_map_io NULL -#define s3c2416_init NULL -#endif - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) -extern void s3c244x_map_io(void); -extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c244x_init_clocks(int xtal); -extern void s3c244x_restart(char mode, const char *cmd); -#else -#define s3c244x_init_clocks NULL -#define s3c244x_init_uarts NULL -#endif - -#ifdef CONFIG_CPU_S3C2440 -extern int s3c2440_init(void); -extern void s3c2440_map_io(void); -extern void s3c2440_init_irq(void); -#else -#define s3c2440_init NULL -#define s3c2440_map_io NULL -#endif - -#ifdef CONFIG_CPU_S3C2442 -extern int s3c2442_init(void); -extern void s3c2442_map_io(void); -extern void s3c2442_init_irq(void); -#else -#define s3c2442_init NULL -#define s3c2442_map_io NULL -#endif - -#ifdef CONFIG_CPU_S3C2443 -extern int s3c2443_init(void); -extern void s3c2443_map_io(void); -extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2443_init_clocks(int xtal); -extern int s3c2443_baseclk_add(void); -extern void s3c2443_restart(char mode, const char *cmd); -extern void s3c2443_init_irq(void); -#else -#define s3c2443_init_clocks NULL -#define s3c2443_init_uarts NULL -#define s3c2443_map_io NULL -#define s3c2443_init NULL -#endif +void s3c2410_restart(char mode, const char *cmd); +void s3c244x_restart(char mode, const char *cmd); extern struct syscore_ops s3c24xx_irq_syscore_ops; diff --git a/trunk/arch/arm/mach-s3c24xx/dma-s3c2410.c b/trunk/arch/arm/mach-s3c24xx/dma-s3c2410.c index a6c94b820954..25d085adc93c 100644 --- a/trunk/arch/arm/mach-s3c24xx/dma-s3c2410.c +++ b/trunk/arch/arm/mach-s3c24xx/dma-s3c2410.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/dma-s3c2412.c b/trunk/arch/arm/mach-s3c24xx/dma-s3c2412.c index c0e8c3f5057e..d2408ba372cb 100644 --- a/trunk/arch/arm/mach-s3c24xx/dma-s3c2412.c +++ b/trunk/arch/arm/mach-s3c24xx/dma-s3c2412.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/dma-s3c2440.c b/trunk/arch/arm/mach-s3c24xx/dma-s3c2440.c index 1c08eccd9425..0b86e74d104f 100644 --- a/trunk/arch/arm/mach-s3c24xx/dma-s3c2440.c +++ b/trunk/arch/arm/mach-s3c24xx/dma-s3c2440.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/dma-s3c2443.c b/trunk/arch/arm/mach-s3c24xx/dma-s3c2443.c index 000e4c69fce9..05536254a3f8 100644 --- a/trunk/arch/arm/mach-s3c24xx/dma-s3c2443.c +++ b/trunk/arch/arm/mach-s3c24xx/dma-s3c2443.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/trunk/arch/arm/mach-s3c24xx/include/mach/entry-macro.S new file mode 100644 index 000000000000..6a21beeba1da --- /dev/null +++ b/trunk/arch/arm/mach-s3c24xx/include/mach/entry-macro.S @@ -0,0 +1,70 @@ +/* + * arch/arm/mach-s3c2410/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for S3C2410-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/* We have a problem that the INTOFFSET register does not always + * show one interrupt. Occasionally we get two interrupts through + * the prioritiser, and this causes the INTOFFSET register to show + * what looks like the logical-or of the two interrupt numbers. + * + * Thanks to Klaus, Shannon, et al for helping to debug this problem +*/ + +#define INTPND (0x10) +#define INTOFFSET (0x14) + +#include +#include + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + mov \base, #S3C24XX_VA_IRQ + + @@ try the interrupt offset register, since it is there + + ldr \irqstat, [\base, #INTPND ] + teq \irqstat, #0 + beq 1002f + ldr \irqnr, [\base, #INTOFFSET ] + mov \tmp, #1 + tst \irqstat, \tmp, lsl \irqnr + bne 1001f + + @@ the number specified is not a valid irq, so try + @@ and work it out for ourselves + + mov \irqnr, #0 @@ start here + + @@ work out which irq (if any) we got + + movs \tmp, \irqstat, lsl#16 + addeq \irqnr, \irqnr, #16 + moveq \irqstat, \irqstat, lsr#16 + tst \irqstat, #0xff + addeq \irqnr, \irqnr, #8 + moveq \irqstat, \irqstat, lsr#8 + tst \irqstat, #0xf + addeq \irqnr, \irqnr, #4 + moveq \irqstat, \irqstat, lsr#4 + tst \irqstat, #0x3 + addeq \irqnr, \irqnr, #2 + moveq \irqstat, \irqstat, lsr#2 + tst \irqstat, #0x1 + addeq \irqnr, \irqnr, #1 + + @@ we have the value +1001: + adds \irqnr, \irqnr, #IRQ_EINT0 +1002: + @@ exit here, Z flag unset if IRQ + + .endm diff --git a/trunk/arch/arm/mach-s3c24xx/include/mach/irqs.h b/trunk/arch/arm/mach-s3c24xx/include/mach/irqs.h index 43cada8019b4..b7a9f4d469e8 100644 --- a/trunk/arch/arm/mach-s3c24xx/include/mach/irqs.h +++ b/trunk/arch/arm/mach-s3c24xx/include/mach/irqs.h @@ -59,53 +59,49 @@ #define IRQ_ADCPARENT S3C2410_IRQ(31) /* interrupts generated from the external interrupts sources */ -#define IRQ_EINT0_2412 S3C2410_IRQ(32) -#define IRQ_EINT1_2412 S3C2410_IRQ(33) -#define IRQ_EINT2_2412 S3C2410_IRQ(34) -#define IRQ_EINT3_2412 S3C2410_IRQ(35) -#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */ -#define IRQ_EINT5 S3C2410_IRQ(37) -#define IRQ_EINT6 S3C2410_IRQ(38) -#define IRQ_EINT7 S3C2410_IRQ(39) -#define IRQ_EINT8 S3C2410_IRQ(40) -#define IRQ_EINT9 S3C2410_IRQ(41) -#define IRQ_EINT10 S3C2410_IRQ(42) -#define IRQ_EINT11 S3C2410_IRQ(43) -#define IRQ_EINT12 S3C2410_IRQ(44) -#define IRQ_EINT13 S3C2410_IRQ(45) -#define IRQ_EINT14 S3C2410_IRQ(46) -#define IRQ_EINT15 S3C2410_IRQ(47) -#define IRQ_EINT16 S3C2410_IRQ(48) -#define IRQ_EINT17 S3C2410_IRQ(49) -#define IRQ_EINT18 S3C2410_IRQ(50) -#define IRQ_EINT19 S3C2410_IRQ(51) -#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */ -#define IRQ_EINT21 S3C2410_IRQ(53) -#define IRQ_EINT22 S3C2410_IRQ(54) -#define IRQ_EINT23 S3C2410_IRQ(55) +#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ +#define IRQ_EINT5 S3C2410_IRQ(33) +#define IRQ_EINT6 S3C2410_IRQ(34) +#define IRQ_EINT7 S3C2410_IRQ(35) +#define IRQ_EINT8 S3C2410_IRQ(36) +#define IRQ_EINT9 S3C2410_IRQ(37) +#define IRQ_EINT10 S3C2410_IRQ(38) +#define IRQ_EINT11 S3C2410_IRQ(39) +#define IRQ_EINT12 S3C2410_IRQ(40) +#define IRQ_EINT13 S3C2410_IRQ(41) +#define IRQ_EINT14 S3C2410_IRQ(42) +#define IRQ_EINT15 S3C2410_IRQ(43) +#define IRQ_EINT16 S3C2410_IRQ(44) +#define IRQ_EINT17 S3C2410_IRQ(45) +#define IRQ_EINT18 S3C2410_IRQ(46) +#define IRQ_EINT19 S3C2410_IRQ(47) +#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ +#define IRQ_EINT21 S3C2410_IRQ(49) +#define IRQ_EINT22 S3C2410_IRQ(50) +#define IRQ_EINT23 S3C2410_IRQ(51) #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) -#define IRQ_LCD_FIFO S3C2410_IRQ(56) -#define IRQ_LCD_FRAME S3C2410_IRQ(57) +#define IRQ_LCD_FIFO S3C2410_IRQ(52) +#define IRQ_LCD_FRAME S3C2410_IRQ(53) /* IRQs for the interal UARTs, and ADC * these need to be ordered in number of appearance in the * SUBSRC mask register */ -#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58) +#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) -#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */ +#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ #define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) #define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) -#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */ +#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ #define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) #define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) -#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */ +#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ #define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) #define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) @@ -140,7 +136,7 @@ /* second interrupt-register of s3c2416/s3c2450 */ -#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29) +#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 54 + 29) #define IRQ_S3C2416_2D S3C2416_IRQ(0) #define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) #define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) diff --git a/trunk/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h b/trunk/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h new file mode 100644 index 000000000000..cbf2d8884e30 --- /dev/null +++ b/trunk/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h @@ -0,0 +1,127 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h + * + * Copyright (c) 2004 Simtec Electronics + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 MMC/SDIO register definitions +*/ + +#ifndef __ASM_ARM_REGS_SDI +#define __ASM_ARM_REGS_SDI "regs-sdi.h" + +#define S3C2410_SDICON (0x00) +#define S3C2410_SDIPRE (0x04) +#define S3C2410_SDICMDARG (0x08) +#define S3C2410_SDICMDCON (0x0C) +#define S3C2410_SDICMDSTAT (0x10) +#define S3C2410_SDIRSP0 (0x14) +#define S3C2410_SDIRSP1 (0x18) +#define S3C2410_SDIRSP2 (0x1C) +#define S3C2410_SDIRSP3 (0x20) +#define S3C2410_SDITIMER (0x24) +#define S3C2410_SDIBSIZE (0x28) +#define S3C2410_SDIDCON (0x2C) +#define S3C2410_SDIDCNT (0x30) +#define S3C2410_SDIDSTA (0x34) +#define S3C2410_SDIFSTA (0x38) + +#define S3C2410_SDIDATA (0x3C) +#define S3C2410_SDIIMSK (0x40) + +#define S3C2440_SDIDATA (0x40) +#define S3C2440_SDIIMSK (0x3C) + +#define S3C2440_SDICON_SDRESET (1<<8) +#define S3C2440_SDICON_MMCCLOCK (1<<5) +#define S3C2410_SDICON_BYTEORDER (1<<4) +#define S3C2410_SDICON_SDIOIRQ (1<<3) +#define S3C2410_SDICON_RWAITEN (1<<2) +#define S3C2410_SDICON_FIFORESET (1<<1) +#define S3C2410_SDICON_CLOCKTYPE (1<<0) + +#define S3C2410_SDICMDCON_ABORT (1<<12) +#define S3C2410_SDICMDCON_WITHDATA (1<<11) +#define S3C2410_SDICMDCON_LONGRSP (1<<10) +#define S3C2410_SDICMDCON_WAITRSP (1<<9) +#define S3C2410_SDICMDCON_CMDSTART (1<<8) +#define S3C2410_SDICMDCON_SENDERHOST (1<<6) +#define S3C2410_SDICMDCON_INDEX (0x3f) + +#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) +#define S3C2410_SDICMDSTAT_CMDSENT (1<<11) +#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) +#define S3C2410_SDICMDSTAT_RSPFIN (1<<9) +#define S3C2410_SDICMDSTAT_XFERING (1<<8) +#define S3C2410_SDICMDSTAT_INDEX (0xff) + +#define S3C2440_SDIDCON_DS_BYTE (0<<22) +#define S3C2440_SDIDCON_DS_HALFWORD (1<<22) +#define S3C2440_SDIDCON_DS_WORD (2<<22) +#define S3C2410_SDIDCON_IRQPERIOD (1<<21) +#define S3C2410_SDIDCON_TXAFTERRESP (1<<20) +#define S3C2410_SDIDCON_RXAFTERCMD (1<<19) +#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) +#define S3C2410_SDIDCON_BLOCKMODE (1<<17) +#define S3C2410_SDIDCON_WIDEBUS (1<<16) +#define S3C2410_SDIDCON_DMAEN (1<<15) +#define S3C2410_SDIDCON_STOP (1<<14) +#define S3C2440_SDIDCON_DATSTART (1<<14) +#define S3C2410_SDIDCON_DATMODE (3<<12) +#define S3C2410_SDIDCON_BLKNUM (0x7ff) + +/* constants for S3C2410_SDIDCON_DATMODE */ +#define S3C2410_SDIDCON_XFER_READY (0<<12) +#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) +#define S3C2410_SDIDCON_XFER_RXSTART (2<<12) +#define S3C2410_SDIDCON_XFER_TXSTART (3<<12) + +#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) +#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) + +#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) +#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) +#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ +#define S3C2410_SDIDSTA_CRCFAIL (1<<7) +#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) +#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) +#define S3C2410_SDIDSTA_XFERFINISH (1<<4) +#define S3C2410_SDIDSTA_BUSYFINISH (1<<3) +#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ +#define S3C2410_SDIDSTA_TXDATAON (1<<1) +#define S3C2410_SDIDSTA_RXDATAON (1<<0) + +#define S3C2440_SDIFSTA_FIFORESET (1<<16) +#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ +#define S3C2410_SDIFSTA_TFDET (1<<13) +#define S3C2410_SDIFSTA_RFDET (1<<12) +#define S3C2410_SDIFSTA_TFHALF (1<<11) +#define S3C2410_SDIFSTA_TFEMPTY (1<<10) +#define S3C2410_SDIFSTA_RFLAST (1<<9) +#define S3C2410_SDIFSTA_RFFULL (1<<8) +#define S3C2410_SDIFSTA_RFHALF (1<<7) +#define S3C2410_SDIFSTA_COUNTMASK (0x7f) + +#define S3C2410_SDIIMSK_RESPONSECRC (1<<17) +#define S3C2410_SDIIMSK_CMDSENT (1<<16) +#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) +#define S3C2410_SDIIMSK_RESPONSEND (1<<14) +#define S3C2410_SDIIMSK_READWAIT (1<<13) +#define S3C2410_SDIIMSK_SDIOIRQ (1<<12) +#define S3C2410_SDIIMSK_FIFOFAIL (1<<11) +#define S3C2410_SDIIMSK_CRCSTATUS (1<<10) +#define S3C2410_SDIIMSK_DATACRC (1<<9) +#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) +#define S3C2410_SDIIMSK_DATAFINISH (1<<7) +#define S3C2410_SDIIMSK_BUSYFINISH (1<<6) +#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ +#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) +#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) +#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) +#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) +#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) + +#endif /* __ASM_ARM_REGS_SDI */ diff --git a/trunk/arch/arm/mach-s3c24xx/irq-pm.c b/trunk/arch/arm/mach-s3c24xx/irq-pm.c index b91341ef2b2e..e1199599873e 100644 --- a/trunk/arch/arm/mach-s3c24xx/irq-pm.c +++ b/trunk/arch/arm/mach-s3c24xx/irq-pm.c @@ -16,15 +16,10 @@ #include #include #include -#include #include #include -#include -#include - -#include -#include +#include #include diff --git a/trunk/arch/arm/mach-s3c24xx/irq-s3c2412.c b/trunk/arch/arm/mach-s3c24xx/irq-s3c2412.c new file mode 100644 index 000000000000..67d763178d3f --- /dev/null +++ b/trunk/arch/arm/mach-s3c24xx/irq-s3c2412.c @@ -0,0 +1,215 @@ +/* linux/arch/arm/mach-s3c2412/irq.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include "s3c2412-power.h" + +#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) +#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0)))) + +/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by + * having them turn up in both the INT* and the EINT* registers. Whilst + * both show the status, they both now need to be acked when the IRQs + * go off. +*/ + +static void +s3c2412_irq_mask(struct irq_data *data) +{ + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask | bitval, S3C2410_INTMSK); + + mask = __raw_readl(S3C2412_EINTMASK); + __raw_writel(mask | bitval, S3C2412_EINTMASK); +} + +static inline void +s3c2412_irq_ack(struct irq_data *data) +{ + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); + + __raw_writel(bitval, S3C2412_EINTPEND); + __raw_writel(bitval, S3C2410_SRCPND); + __raw_writel(bitval, S3C2410_INTPND); +} + +static inline void +s3c2412_irq_maskack(struct irq_data *data) +{ + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask|bitval, S3C2410_INTMSK); + + mask = __raw_readl(S3C2412_EINTMASK); + __raw_writel(mask | bitval, S3C2412_EINTMASK); + + __raw_writel(bitval, S3C2412_EINTPEND); + __raw_writel(bitval, S3C2410_SRCPND); + __raw_writel(bitval, S3C2410_INTPND); +} + +static void +s3c2412_irq_unmask(struct irq_data *data) +{ + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2412_EINTMASK); + __raw_writel(mask & ~bitval, S3C2412_EINTMASK); + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask & ~bitval, S3C2410_INTMSK); +} + +static struct irq_chip s3c2412_irq_eint0t4 = { + .irq_ack = s3c2412_irq_ack, + .irq_mask = s3c2412_irq_mask, + .irq_unmask = s3c2412_irq_unmask, + .irq_set_wake = s3c_irq_wake, + .irq_set_type = s3c_irqext_type, +}; + +#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0))) + +/* CF and SDI sub interrupts */ + +static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + + if (subsrc & INTBIT(IRQ_S3C2412_SDI)) + generic_handle_irq(IRQ_S3C2412_SDI); + + if (subsrc & INTBIT(IRQ_S3C2412_CF)) + generic_handle_irq(IRQ_S3C2412_CF); +} + +#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0)) +#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF) + +static void s3c2412_irq_cfsdi_mask(struct irq_data *data) +{ + s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); +} + +static void s3c2412_irq_cfsdi_unmask(struct irq_data *data) +{ + s3c_irqsub_unmask(data->irq, INTMSK_CFSDI); +} + +static void s3c2412_irq_cfsdi_ack(struct irq_data *data) +{ + s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); +} + +static struct irq_chip s3c2412_irq_cfsdi = { + .name = "s3c2412-cfsdi", + .irq_ack = s3c2412_irq_cfsdi_ack, + .irq_mask = s3c2412_irq_cfsdi_mask, + .irq_unmask = s3c2412_irq_cfsdi_unmask, +}; + +static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state) +{ + unsigned long pwrcfg; + + pwrcfg = __raw_readl(S3C2412_PWRCFG); + if (state) + pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ; + else + pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ; + __raw_writel(pwrcfg, S3C2412_PWRCFG); + + return s3c_irq_chip.irq_set_wake(data, state); +} + +static struct irq_chip s3c2412_irq_rtc_chip; + +static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif) +{ + unsigned int irqno; + + for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { + irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4, + handle_edge_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + /* add demux support for CF/SDI */ + + irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); + + for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { + irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi, + handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + /* change RTC IRQ's set wake method */ + + s3c2412_irq_rtc_chip = s3c_irq_chip; + s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; + + irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); + + return 0; +} + +static struct subsys_interface s3c2412_irq_interface = { + .name = "s3c2412_irq", + .subsys = &s3c2412_subsys, + .add_dev = s3c2412_irq_add, +}; + +static int s3c2412_irq_init(void) +{ + return subsys_interface_register(&s3c2412_irq_interface); +} + +arch_initcall(s3c2412_irq_init); diff --git a/trunk/arch/arm/mach-s3c24xx/irq-s3c2440.c b/trunk/arch/arm/mach-s3c24xx/irq-s3c2440.c new file mode 100644 index 000000000000..4a18cde439cc --- /dev/null +++ b/trunk/arch/arm/mach-s3c24xx/irq-s3c2440.c @@ -0,0 +1,128 @@ +/* linux/arch/arm/mach-s3c2440/irq.c + * + * Copyright (c) 2003-2004 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include +#include +#include + +/* WDT/AC97 */ + +static void s3c_irq_demux_wdtac97(unsigned int irq, + struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + + /* read the current pending interrupts, and the mask + * for what it is available */ + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + subsrc >>= 13; + subsrc &= 3; + + if (subsrc != 0) { + if (subsrc & 1) { + generic_handle_irq(IRQ_S3C2440_WDT); + } + if (subsrc & 2) { + generic_handle_irq(IRQ_S3C2440_AC97); + } + } +} + + +#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0)) + +static void +s3c_irq_wdtac97_mask(struct irq_data *data) +{ + s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13); +} + +static void +s3c_irq_wdtac97_unmask(struct irq_data *data) +{ + s3c_irqsub_unmask(data->irq, INTMSK_WDT); +} + +static void +s3c_irq_wdtac97_ack(struct irq_data *data) +{ + s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13); +} + +static struct irq_chip s3c_irq_wdtac97 = { + .irq_mask = s3c_irq_wdtac97_mask, + .irq_unmask = s3c_irq_wdtac97_unmask, + .irq_ack = s3c_irq_wdtac97_ack, +}; + +static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif) +{ + unsigned int irqno; + + printk("S3C2440: IRQ Support\n"); + + /* add new chained handler for wdt, ac7 */ + + irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip, + handle_level_irq); + irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); + + for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { + irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97, + handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + return 0; +} + +static struct subsys_interface s3c2440_irq_interface = { + .name = "s3c2440_irq", + .subsys = &s3c2440_subsys, + .add_dev = s3c2440_irq_add, +}; + +static int s3c2440_irq_init(void) +{ + return subsys_interface_register(&s3c2440_irq_interface); +} + +arch_initcall(s3c2440_irq_init); + diff --git a/trunk/arch/arm/mach-s3c24xx/irq-s3c244x.c b/trunk/arch/arm/mach-s3c24xx/irq-s3c244x.c new file mode 100644 index 000000000000..5fe8e58d3afd --- /dev/null +++ b/trunk/arch/arm/mach-s3c24xx/irq-s3c244x.c @@ -0,0 +1,142 @@ +/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c + * + * Copyright (c) 2003-2004 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include +#include +#include + +/* camera irq */ + +static void s3c_irq_demux_cam(unsigned int irq, + struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + + /* read the current pending interrupts, and the mask + * for what it is available */ + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + subsrc >>= 11; + subsrc &= 3; + + if (subsrc != 0) { + if (subsrc & 1) { + generic_handle_irq(IRQ_S3C2440_CAM_C); + } + if (subsrc & 2) { + generic_handle_irq(IRQ_S3C2440_CAM_P); + } + } +} + +#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) + +static void +s3c_irq_cam_mask(struct irq_data *data) +{ + s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11); +} + +static void +s3c_irq_cam_unmask(struct irq_data *data) +{ + s3c_irqsub_unmask(data->irq, INTMSK_CAM); +} + +static void +s3c_irq_cam_ack(struct irq_data *data) +{ + s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11); +} + +static struct irq_chip s3c_irq_cam = { + .irq_mask = s3c_irq_cam_mask, + .irq_unmask = s3c_irq_cam_unmask, + .irq_ack = s3c_irq_cam_ack, +}; + +static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif) +{ + unsigned int irqno; + + irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip, + handle_level_irq); + set_irq_flags(IRQ_NFCON, IRQF_VALID); + + /* add chained handler for camera */ + + irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip, + handle_level_irq); + irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); + + for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { + irq_set_chip_and_handler(irqno, &s3c_irq_cam, + handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + return 0; +} + +static struct subsys_interface s3c2440_irq_interface = { + .name = "s3c2440_irq", + .subsys = &s3c2440_subsys, + .add_dev = s3c244x_irq_add, +}; + +static int s3c2440_irq_init(void) +{ + return subsys_interface_register(&s3c2440_irq_interface); +} + +arch_initcall(s3c2440_irq_init); + +static struct subsys_interface s3c2442_irq_interface = { + .name = "s3c2442_irq", + .subsys = &s3c2442_subsys, + .add_dev = s3c244x_irq_add, +}; + + +static int s3c2442_irq_init(void) +{ + return subsys_interface_register(&s3c2442_irq_interface); +} + +arch_initcall(s3c2442_irq_init); diff --git a/trunk/drivers/irqchip/irq-s3c24xx.c b/trunk/arch/arm/mach-s3c24xx/irq.c similarity index 52% rename from trunk/drivers/irqchip/irq-s3c24xx.c rename to trunk/arch/arm/mach-s3c24xx/irq.c index 5e40b3424df8..cb9f5e011e73 100644 --- a/trunk/drivers/irqchip/irq-s3c24xx.c +++ b/trunk/arch/arm/mach-s3c24xx/irq.c @@ -25,11 +25,7 @@ #include #include #include -#include -#include -#include -#include #include #include @@ -38,8 +34,7 @@ #include #include #include - -#include "irqchip.h" +#include #define S3C_IRQTYPE_NONE 0 #define S3C_IRQTYPE_EINT 1 @@ -48,7 +43,6 @@ struct s3c_irq_data { unsigned int type; - unsigned long offset; unsigned long parent_irq; /* data gets filled during init */ @@ -75,34 +69,23 @@ struct s3c_irq_intc { struct s3c_irq_data *irqs; }; -/* - * Array holding pointers to the global controller structs - * [0] ... main_intc - * [1] ... sub_intc - * [2] ... main_intc2 on s3c2416 - */ -static struct s3c_irq_intc *s3c_intc[3]; - static void s3c_irq_mask(struct irq_data *data) { - struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); - struct s3c_irq_intc *intc = irq_data->intc; + struct s3c_irq_intc *intc = data->domain->host_data; struct s3c_irq_intc *parent_intc = intc->parent; + struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; struct s3c_irq_data *parent_data; unsigned long mask; unsigned int irqno; mask = __raw_readl(intc->reg_mask); - mask |= (1UL << irq_data->offset); + mask |= (1UL << data->hwirq); __raw_writel(mask, intc->reg_mask); - if (parent_intc) { + if (parent_intc && irq_data->parent_irq) { parent_data = &parent_intc->irqs[irq_data->parent_irq]; - /* check to see if we need to mask the parent IRQ - * The parent_irq is always in main_intc, so the hwirq - * for find_mapping does not need an offset in any case. - */ + /* check to see if we need to mask the parent IRQ */ if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { irqno = irq_find_mapping(parent_intc->domain, irq_data->parent_irq); @@ -113,17 +96,17 @@ static void s3c_irq_mask(struct irq_data *data) static void s3c_irq_unmask(struct irq_data *data) { - struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); - struct s3c_irq_intc *intc = irq_data->intc; + struct s3c_irq_intc *intc = data->domain->host_data; struct s3c_irq_intc *parent_intc = intc->parent; + struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; unsigned long mask; unsigned int irqno; mask = __raw_readl(intc->reg_mask); - mask &= ~(1UL << irq_data->offset); + mask &= ~(1UL << data->hwirq); __raw_writel(mask, intc->reg_mask); - if (parent_intc) { + if (parent_intc && irq_data->parent_irq) { irqno = irq_find_mapping(parent_intc->domain, irq_data->parent_irq); s3c_irq_unmask(irq_get_irq_data(irqno)); @@ -132,37 +115,14 @@ static void s3c_irq_unmask(struct irq_data *data) static inline void s3c_irq_ack(struct irq_data *data) { - struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); - struct s3c_irq_intc *intc = irq_data->intc; - unsigned long bitval = 1UL << irq_data->offset; + struct s3c_irq_intc *intc = data->domain->host_data; + unsigned long bitval = 1UL << data->hwirq; __raw_writel(bitval, intc->reg_pending); if (intc->reg_intpnd) __raw_writel(bitval, intc->reg_intpnd); } -static int s3c_irq_type(struct irq_data *data, unsigned int type) -{ - switch (type) { - case IRQ_TYPE_NONE: - break; - case IRQ_TYPE_EDGE_RISING: - case IRQ_TYPE_EDGE_FALLING: - case IRQ_TYPE_EDGE_BOTH: - irq_set_handler(data->irq, handle_edge_irq); - break; - case IRQ_TYPE_LEVEL_LOW: - case IRQ_TYPE_LEVEL_HIGH: - irq_set_handler(data->irq, handle_level_irq); - break; - default: - pr_err("No such irq type %d", type); - return -EINVAL; - } - - return 0; -} - static int s3c_irqext_type_set(void __iomem *gpcon_reg, void __iomem *extint_reg, unsigned long gpcon_offset, @@ -215,7 +175,8 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg, return 0; } -static int s3c_irqext_type(struct irq_data *data, unsigned int type) +/* FIXME: make static when it's out of plat-samsung/irq.h */ +int s3c_irqext_type(struct irq_data *data, unsigned int type) { void __iomem *extint_reg; void __iomem *gpcon_reg; @@ -263,21 +224,19 @@ static int s3c_irqext0_type(struct irq_data *data, unsigned int type) extint_offset, type); } -static struct irq_chip s3c_irq_chip = { +struct irq_chip s3c_irq_chip = { .name = "s3c", .irq_ack = s3c_irq_ack, .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, - .irq_set_type = s3c_irq_type, .irq_set_wake = s3c_irq_wake }; -static struct irq_chip s3c_irq_level_chip = { +struct irq_chip s3c_irq_level_chip = { .name = "s3c-level", .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, .irq_ack = s3c_irq_ack, - .irq_set_type = s3c_irq_type, }; static struct irq_chip s3c_irqext_chip = { @@ -301,19 +260,12 @@ static struct irq_chip s3c_irq_eint0t4 = { static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); - struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc); - struct s3c_irq_intc *intc = irq_data->intc; + struct s3c_irq_intc *intc = desc->irq_data.domain->host_data; + struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq]; struct s3c_irq_intc *sub_intc = irq_data->sub_intc; unsigned long src; unsigned long msk; unsigned int n; - unsigned int offset; - - /* we're using individual domains for the non-dt case - * and one big domain for the dt case where the subintc - * starts at hwirq number 32. - */ - offset = (intc->domain->of_node) ? 32 : 0; chained_irq_enter(chip, desc); @@ -326,64 +278,12 @@ static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc) while (src) { n = __ffs(src); src &= ~(1 << n); - irq = irq_find_mapping(sub_intc->domain, offset + n); - generic_handle_irq(irq); + generic_handle_irq(irq_find_mapping(sub_intc->domain, n)); } chained_irq_exit(chip, desc); } -static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, - struct pt_regs *regs, int intc_offset) -{ - int pnd; - int offset; - int irq; - - pnd = __raw_readl(intc->reg_intpnd); - if (!pnd) - return false; - - /* non-dt machines use individual domains */ - if (!intc->domain->of_node) - intc_offset = 0; - - /* We have a problem that the INTOFFSET register does not always - * show one interrupt. Occasionally we get two interrupts through - * the prioritiser, and this causes the INTOFFSET register to show - * what looks like the logical-or of the two interrupt numbers. - * - * Thanks to Klaus, Shannon, et al for helping to debug this problem - */ - offset = __raw_readl(intc->reg_intpnd + 4); - - /* Find the bit manually, when the offset is wrong. - * The pending register only ever contains the one bit of the next - * interrupt to handle. - */ - if (!(pnd & (1 << offset))) - offset = __ffs(pnd); - - irq = irq_find_mapping(intc->domain, intc_offset + offset); - handle_IRQ(irq, regs); - return true; -} - -asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) -{ - do { - if (likely(s3c_intc[0])) - if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) - continue; - - if (s3c_intc[2]) - if (s3c24xx_handle_intc(s3c_intc[2], regs, 64)) - continue; - - break; - } while (1); -} - #ifdef CONFIG_FIQ /** * s3c24xx_set_fiq - set the FIQ routing @@ -426,21 +326,25 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, struct s3c_irq_data *parent_irq_data; unsigned int irqno; + if (!intc) { + pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw); + return -EINVAL; + } + + if (!irq_data) { + pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw); + return -EINVAL; + } + /* attach controller pointer to irq_data */ irq_data->intc = intc; - irq_data->offset = hw; - - parent_intc = intc->parent; /* set handler and flags */ switch (irq_data->type) { case S3C_IRQTYPE_NONE: return 0; case S3C_IRQTYPE_EINT: - /* On the S3C2412, the EINT0to3 have a parent irq - * but need the s3c_irq_eint0t4 chip - */ - if (parent_intc && (!soc_is_s3c2412() || hw >= 4)) + if (irq_data->parent_irq) irq_set_chip_and_handler(virq, &s3c_irqext_chip, handle_edge_irq); else @@ -448,7 +352,8 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, handle_edge_irq); break; case S3C_IRQTYPE_EDGE: - if (parent_intc || intc->reg_pending == S3C2416_SRCPND2) + if (irq_data->parent_irq || + intc->reg_pending == S3C2416_SRCPND2) irq_set_chip_and_handler(virq, &s3c_irq_level_chip, handle_edge_irq); else @@ -456,7 +361,7 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, handle_edge_irq); break; case S3C_IRQTYPE_LEVEL: - if (parent_intc) + if (irq_data->parent_irq) irq_set_chip_and_handler(virq, &s3c_irq_level_chip, handle_level_irq); else @@ -467,19 +372,23 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); return -EINVAL; } - - irq_set_chip_data(virq, irq_data); - set_irq_flags(virq, IRQF_VALID); - if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) { - if (irq_data->parent_irq > 31) { - pr_err("irq-s3c24xx: parent irq %lu is out of range\n", - irq_data->parent_irq); + if (irq_data->parent_irq) { + parent_intc = intc->parent; + if (!parent_intc) { + pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n", + hw); goto err; } parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; + if (!irq_data) { + pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", + hw); + goto err; + } + parent_irq_data->sub_intc = intc; parent_irq_data->sub_bits |= (1UL << hw); @@ -534,7 +443,7 @@ static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) } } -static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, +struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, struct s3c_irq_data *irq_data, struct s3c_irq_intc *parent, unsigned long address) @@ -543,6 +452,7 @@ static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, void __iomem *base = (void *)0xf6000000; /* static mapping */ int irq_num; int irq_start; + int irq_offset; int ret; intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); @@ -566,6 +476,7 @@ static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, intc->reg_intpnd = base + 0x10; irq_num = 32; irq_start = S3C2410_IRQ(0); + irq_offset = 0; break; case 0x4a000018: pr_debug("irq: found subintc\n"); @@ -573,6 +484,7 @@ static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, intc->reg_mask = base + 0x1c; irq_num = 29; irq_start = S3C2410_IRQSUB(0); + irq_offset = 0; break; case 0x4a000040: pr_debug("irq: found intc2\n"); @@ -581,6 +493,7 @@ static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, intc->reg_intpnd = base + 0x50; irq_num = 8; irq_start = S3C2416_IRQ(0); + irq_offset = 0; break; case 0x560000a4: pr_debug("irq: found eintc\n"); @@ -588,8 +501,9 @@ static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, intc->reg_mask = base + 0xa4; intc->reg_pending = base + 0x08; - irq_num = 24; + irq_num = 20; irq_start = S3C2410_IRQ(32); + irq_offset = 4; break; default: pr_err("irq: unsupported controller address\n"); @@ -600,7 +514,7 @@ static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, /* now that all the data is complete, init the irq-domain */ s3c24xx_clear_intc(intc); intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, - 0, &s3c24xx_irq_ops, + irq_offset, &s3c24xx_irq_ops, intc); if (!intc->domain) { pr_err("irq: could not create irq-domain\n"); @@ -608,8 +522,6 @@ static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, goto err; } - set_handle_irq(s3c24xx_handle_irq); - return intc; err: @@ -617,35 +529,12 @@ static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, return ERR_PTR(ret); } -static struct s3c_irq_data init_eint[32] = { - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ -}; +/* s3c24xx_init_irq + * + * Initialise S3C2410 IRQ system +*/ -#ifdef CONFIG_CPU_S3C2410 -static struct s3c_irq_data init_s3c2410base[32] = { +static struct s3c_irq_data init_base[32] = { { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ @@ -680,80 +569,11 @@ static struct s3c_irq_data init_s3c2410base[32] = { { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ }; -static struct s3c_irq_data init_s3c2410subint[32] = { - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ -}; - -void __init s3c2410_init_irq(void) -{ -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { - pr_err("irq: could not create main interrupt controller\n"); - return; - } - - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0], - s3c_intc[0], 0x4a000018); - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); -} -#endif - -#ifdef CONFIG_CPU_S3C2412 -static struct s3c_irq_data init_s3c2412base[32] = { - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ +static struct s3c_irq_data init_eint[32] = { + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ - { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ { .type = S3C_IRQTYPE_NONE, }, /* reserved */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ - { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ -}; - -static struct s3c_irq_data init_s3c2412eint[32] = { - { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */ - { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ @@ -776,7 +596,7 @@ static struct s3c_irq_data init_s3c2412eint[32] = { { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ }; -static struct s3c_irq_data init_s3c2412subint[32] = { +static struct s3c_irq_data init_subint[32] = { { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ @@ -788,32 +608,25 @@ static struct s3c_irq_data init_s3c2412subint[32] = { { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ - { .type = S3C_IRQTYPE_NONE, }, - { .type = S3C_IRQTYPE_NONE, }, - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */ }; -void s3c2412_init_irq(void) +void __init s3c24xx_init_irq(void) { - pr_info("S3C2412: IRQ Support\n"); + struct s3c_irq_intc *main_intc; #ifdef CONFIG_FIQ init_FIQ(FIQ_START); #endif - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { + main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000); + if (IS_ERR(main_intc)) { pr_err("irq: could not create main interrupt controller\n"); return; } - s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0], - s3c_intc[0], 0x4a000018); + s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018); + s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); } -#endif #ifdef CONFIG_CPU_S3C2416 static struct s3c_irq_data init_s3c2416base[32] = { @@ -885,185 +698,37 @@ static struct s3c_irq_data init_s3c2416subint[32] = { static struct s3c_irq_data init_s3c2416_second[32] = { { .type = S3C_IRQTYPE_EDGE }, /* 2D */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */ { .type = S3C_IRQTYPE_NONE }, /* reserved */ { .type = S3C_IRQTYPE_NONE }, /* reserved */ { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */ - { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */ { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */ + { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */ }; void __init s3c2416_init_irq(void) { + struct s3c_irq_intc *main_intc; + pr_info("S3C2416: IRQ Support\n"); #ifdef CONFIG_FIQ init_FIQ(FIQ_START); #endif - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { + main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000); + if (IS_ERR(main_intc)) { pr_err("irq: could not create main interrupt controller\n"); return; } - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0], - s3c_intc[0], 0x4a000018); - - s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0], - NULL, 0x4a000040); -} - -#endif - -#ifdef CONFIG_CPU_S3C2440 -static struct s3c_irq_data init_s3c2440base[32] = { - { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ - { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ - { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ - { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ -}; - -static struct s3c_irq_data init_s3c2440subint[32] = { - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ -}; - -void __init s3c2440_init_irq(void) -{ - pr_info("S3C2440: IRQ Support\n"); + s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); + s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018); -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { - pr_err("irq: could not create main interrupt controller\n"); - return; - } - - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0], - s3c_intc[0], 0x4a000018); + s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040); } -#endif -#ifdef CONFIG_CPU_S3C2442 -static struct s3c_irq_data init_s3c2442base[32] = { - { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ - { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ - { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ - { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ - { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ - { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ - { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ - { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ - { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ - { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ - { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ -}; - -static struct s3c_irq_data init_s3c2442subint[32] = { - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ - { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ - { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ -}; - -void __init s3c2442_init_irq(void) -{ - pr_info("S3C2442: IRQ Support\n"); - -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { - pr_err("irq: could not create main interrupt controller\n"); - return; - } - - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0], - s3c_intc[0], 0x4a000018); -} #endif #ifdef CONFIG_CPU_S3C2443 @@ -1137,219 +802,21 @@ static struct s3c_irq_data init_s3c2443subint[32] = { void __init s3c2443_init_irq(void) { + struct s3c_irq_intc *main_intc; + pr_info("S3C2443: IRQ Support\n"); #ifdef CONFIG_FIQ init_FIQ(FIQ_START); #endif - s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, - 0x4a000000); - if (IS_ERR(s3c_intc[0])) { + main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000); + if (IS_ERR(main_intc)) { pr_err("irq: could not create main interrupt controller\n"); return; } - s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); - s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0], - s3c_intc[0], 0x4a000018); -} -#endif - -#ifdef CONFIG_OF -static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - unsigned int ctrl_num = hw / 32; - unsigned int intc_hw = hw % 32; - struct s3c_irq_intc *intc = s3c_intc[ctrl_num]; - struct s3c_irq_intc *parent_intc = intc->parent; - struct s3c_irq_data *irq_data = &intc->irqs[intc_hw]; - - /* attach controller pointer to irq_data */ - irq_data->intc = intc; - irq_data->offset = intc_hw; - - if (!parent_intc) - irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq); - else - irq_set_chip_and_handler(virq, &s3c_irq_level_chip, - handle_edge_irq); - - irq_set_chip_data(virq, irq_data); - - set_irq_flags(virq, IRQF_VALID); - - return 0; -} - -/* Translate our of irq notation - * format: - */ -static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n, - const u32 *intspec, unsigned int intsize, - irq_hw_number_t *out_hwirq, unsigned int *out_type) -{ - struct s3c_irq_intc *intc; - struct s3c_irq_intc *parent_intc; - struct s3c_irq_data *irq_data; - struct s3c_irq_data *parent_irq_data; - int irqno; - - if (WARN_ON(intsize < 4)) - return -EINVAL; - - if (intspec[0] > 2 || !s3c_intc[intspec[0]]) { - pr_err("controller number %d invalid\n", intspec[0]); - return -EINVAL; - } - intc = s3c_intc[intspec[0]]; - - *out_hwirq = intspec[0] * 32 + intspec[2]; - *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; - - parent_intc = intc->parent; - if (parent_intc) { - irq_data = &intc->irqs[intspec[2]]; - irq_data->parent_irq = intspec[1]; - parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; - parent_irq_data->sub_intc = intc; - parent_irq_data->sub_bits |= (1UL << intspec[2]); - - /* parent_intc is always s3c_intc[0], so no offset */ - irqno = irq_create_mapping(parent_intc->domain, intspec[1]); - if (irqno < 0) { - pr_err("irq: could not map parent interrupt\n"); - return irqno; - } - - irq_set_chained_handler(irqno, s3c_irq_demux); - } - - return 0; -} - -static struct irq_domain_ops s3c24xx_irq_ops_of = { - .map = s3c24xx_irq_map_of, - .xlate = s3c24xx_irq_xlate_of, -}; - -struct s3c24xx_irq_of_ctrl { - char *name; - unsigned long offset; - struct s3c_irq_intc **handle; - struct s3c_irq_intc **parent; - struct irq_domain_ops *ops; -}; - -static int __init s3c_init_intc_of(struct device_node *np, - struct device_node *interrupt_parent, - struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl) -{ - struct s3c_irq_intc *intc; - struct s3c24xx_irq_of_ctrl *ctrl; - struct irq_domain *domain; - void __iomem *reg_base; - int i; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("irq-s3c24xx: could not map irq registers\n"); - return -EINVAL; - } - - domain = irq_domain_add_linear(np, num_ctrl * 32, - &s3c24xx_irq_ops_of, NULL); - if (!domain) { - pr_err("irq: could not create irq-domain\n"); - return -EINVAL; - } - - for (i = 0; i < num_ctrl; i++) { - ctrl = &s3c_ctrl[i]; - - pr_debug("irq: found controller %s\n", ctrl->name); - - intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); - if (!intc) - return -ENOMEM; - - intc->domain = domain; - intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32, - GFP_KERNEL); - if (!intc->irqs) { - kfree(intc); - return -ENOMEM; - } - - if (ctrl->parent) { - intc->reg_pending = reg_base + ctrl->offset; - intc->reg_mask = reg_base + ctrl->offset + 0x4; - - if (*(ctrl->parent)) { - intc->parent = *(ctrl->parent); - } else { - pr_warn("irq: parent of %s missing\n", - ctrl->name); - kfree(intc->irqs); - kfree(intc); - continue; - } - } else { - intc->reg_pending = reg_base + ctrl->offset; - intc->reg_mask = reg_base + ctrl->offset + 0x08; - intc->reg_intpnd = reg_base + ctrl->offset + 0x10; - } - - s3c24xx_clear_intc(intc); - s3c_intc[i] = intc; - } - - set_handle_irq(s3c24xx_handle_irq); - - return 0; -} - -static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = { - { - .name = "intc", - .offset = 0, - }, { - .name = "subintc", - .offset = 0x18, - .parent = &s3c_intc[0], - } -}; - -int __init s3c2410_init_intc_of(struct device_node *np, - struct device_node *interrupt_parent, - struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl) -{ - return s3c_init_intc_of(np, interrupt_parent, - s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl)); -} -IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of); - -static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = { - { - .name = "intc", - .offset = 0, - }, { - .name = "subintc", - .offset = 0x18, - .parent = &s3c_intc[0], - }, { - .name = "intc2", - .offset = 0x40, - } -}; - -int __init s3c2416_init_intc_of(struct device_node *np, - struct device_node *interrupt_parent, - struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl) -{ - return s3c_init_intc_of(np, interrupt_parent, - s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl)); + s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); + s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018); } -IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of); #endif diff --git a/trunk/arch/arm/mach-s3c24xx/mach-amlm5900.c b/trunk/arch/arm/mach-s3c24xx/mach-amlm5900.c index e27b5c91b3db..0e0279e79150 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-amlm5900.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-amlm5900.c @@ -63,8 +63,6 @@ #include #include -#include - #include "common.h" static struct resource amlm5900_nor_resource = @@ -162,7 +160,6 @@ static void __init amlm5900_map_io(void) s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } #ifdef CONFIG_FB_S3C2410 @@ -238,8 +235,8 @@ static void __init amlm5900_init(void) MACHINE_START(AML_M5900, "AML_M5900") .atag_offset = 0x100, .map_io = amlm5900_map_io, - .init_irq = s3c2410_init_irq, + .init_irq = s3c24xx_init_irq, .init_machine = amlm5900_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-anubis.c b/trunk/arch/arm/mach-s3c24xx/mach-anubis.c index c1fb6c37867f..bb595f15ce36 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-anubis.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-anubis.c @@ -49,7 +49,6 @@ #include #include #include -#include #include "anubis.h" #include "common.h" @@ -411,7 +410,6 @@ static void __init anubis_map_io(void) s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* check for the newer revision boards with large page nand */ @@ -445,7 +443,7 @@ MACHINE_START(ANUBIS, "Simtec-Anubis") .atag_offset = 0x100, .map_io = anubis_map_io, .init_machine = anubis_init, - .init_irq = s3c2440_init_irq, - .init_time = samsung_timer_init, + .init_irq = s3c24xx_init_irq, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-at2440evb.c b/trunk/arch/arm/mach-s3c24xx/mach-at2440evb.c index 6dfeeb7ef469..b4bc60c78ebb 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-at2440evb.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-at2440evb.c @@ -48,7 +48,6 @@ #include #include #include -#include #include "common.h" @@ -193,7 +192,6 @@ static void __init at2440evb_map_io(void) s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); s3c24xx_init_clocks(16934400); s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init at2440evb_init(void) @@ -211,7 +209,7 @@ MACHINE_START(AT2440EVB, "AT2440EVB") .atag_offset = 0x100, .map_io = at2440evb_map_io, .init_machine = at2440evb_init, - .init_irq = s3c2440_init_irq, - .init_time = samsung_timer_init, + .init_irq = s3c24xx_init_irq, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-bast.c b/trunk/arch/arm/mach-s3c24xx/mach-bast.c index 22d6ae926d91..ca6618081041 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-bast.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-bast.c @@ -55,7 +55,6 @@ #include #include #include -#include #include "bast.h" #include "common.h" @@ -577,7 +576,6 @@ static void __init bast_map_io(void) s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init bast_init(void) @@ -605,8 +603,8 @@ MACHINE_START(BAST, "Simtec-BAST") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, .map_io = bast_map_io, - .init_irq = s3c2410_init_irq, + .init_irq = s3c24xx_init_irq, .init_machine = bast_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-gta02.c b/trunk/arch/arm/mach-s3c24xx/mach-gta02.c index 13d8d073675a..a25e8c5a7b4c 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-gta02.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-gta02.c @@ -81,7 +81,6 @@ #include #include #include -#include #include "common.h" #include "gta02.h" @@ -502,7 +501,6 @@ static void __init gta02_map_io(void) s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } @@ -589,8 +587,8 @@ MACHINE_START(NEO1973_GTA02, "GTA02") /* Maintainer: Nelson Castillo */ .atag_offset = 0x100, .map_io = gta02_map_io, - .init_irq = s3c2442_init_irq, + .init_irq = s3c24xx_init_irq, .init_machine = gta02_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-h1940.c b/trunk/arch/arm/mach-s3c24xx/mach-h1940.c index af4334d6b4d5..79bc0830d740 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-h1940.c @@ -62,7 +62,7 @@ #include #include #include -#include + #include "common.h" #include "h1940.h" @@ -646,7 +646,6 @@ static void __init h1940_map_io(void) s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* setup PM */ @@ -667,6 +666,11 @@ static void __init h1940_reserve(void) memblock_reserve(0x30081000, 0x1000); } +static void __init h1940_init_irq(void) +{ + s3c24xx_init_irq(); +} + static void __init h1940_init(void) { u32 tmp; @@ -735,8 +739,8 @@ MACHINE_START(H1940, "IPAQ-H1940") .atag_offset = 0x100, .map_io = h1940_map_io, .reserve = h1940_reserve, - .init_irq = s3c2410_init_irq, + .init_irq = h1940_init_irq, .init_machine = h1940_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-jive.c b/trunk/arch/arm/mach-s3c24xx/mach-jive.c index a45fcd8ccf79..54e83c1f780c 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-jive.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-jive.c @@ -46,15 +46,14 @@ #include #include +#include #include #include #include #include #include #include -#include -#include "common.h" #include "s3c2412-power.h" static struct map_desc jive_iodesc[] __initdata = { @@ -507,7 +506,6 @@ static void __init jive_map_io(void) s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void jive_power_off(void) @@ -660,9 +658,9 @@ MACHINE_START(JIVE, "JIVE") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, - .init_irq = s3c2412_init_irq, + .init_irq = s3c24xx_init_irq, .map_io = jive_map_io, .init_machine = jive_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-mini2440.c b/trunk/arch/arm/mach-s3c24xx/mach-mini2440.c index a83db46320bc..2865e5919f2c 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-mini2440.c @@ -56,7 +56,6 @@ #include #include #include -#include #include @@ -526,7 +525,6 @@ static void __init mini2440_map_io(void) s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } /* @@ -688,7 +686,7 @@ MACHINE_START(MINI2440, "MINI2440") .atag_offset = 0x100, .map_io = mini2440_map_io, .init_machine = mini2440_init, - .init_irq = s3c2440_init_irq, - .init_time = samsung_timer_init, + .init_irq = s3c24xx_init_irq, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-n30.c b/trunk/arch/arm/mach-s3c24xx/mach-n30.c index 2cb46c37c920..d9d04b240295 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-n30.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-n30.c @@ -48,8 +48,8 @@ #include #include #include +#include #include -#include #include "common.h" @@ -536,7 +536,6 @@ static void __init n30_map_io(void) n30_hwinit(); s3c24xx_init_clocks(0); s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } /* GPB3 is the line that controls the pull-up for the USB D+ line */ @@ -590,9 +589,9 @@ MACHINE_START(N30, "Acer-N30") Ben Dooks */ .atag_offset = 0x100, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .init_machine = n30_init, - .init_irq = s3c2410_init_irq, + .init_irq = s3c24xx_init_irq, .map_io = n30_map_io, .restart = s3c2410_restart, MACHINE_END @@ -601,9 +600,9 @@ MACHINE_START(N35, "Acer-N35") /* Maintainer: Christer Weinigel */ .atag_offset = 0x100, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .init_machine = n30_init, - .init_irq = s3c2410_init_irq, + .init_irq = s3c24xx_init_irq, .map_io = n30_map_io, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-nexcoder.c b/trunk/arch/arm/mach-s3c24xx/mach-nexcoder.c index 01f4354206f9..a454e2461860 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-nexcoder.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-nexcoder.c @@ -41,10 +41,11 @@ #include #include +#include +#include #include #include #include -#include #include "common.h" @@ -136,7 +137,6 @@ static void __init nexcoder_map_io(void) s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); nexcoder_sensorboard_init(); } @@ -152,7 +152,7 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440") .atag_offset = 0x100, .map_io = nexcoder_map_io, .init_machine = nexcoder_init, - .init_irq = s3c2440_init_irq, - .init_time = samsung_timer_init, + .init_irq = s3c24xx_init_irq, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-osiris.c b/trunk/arch/arm/mach-s3c24xx/mach-osiris.c index 58d6fbe5bf1f..ae2cbdf3e3ca 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-osiris.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-osiris.c @@ -45,7 +45,6 @@ #include #include #include -#include #include #include @@ -385,7 +384,6 @@ static void __init osiris_map_io(void) s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* check for the newer revision boards with large page nand */ @@ -426,8 +424,8 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, .map_io = osiris_map_io, - .init_irq = s3c2440_init_irq, + .init_irq = s3c24xx_init_irq, .init_machine = osiris_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-otom.c b/trunk/arch/arm/mach-s3c24xx/mach-otom.c index 7e16b0740ec1..40a47d6c6a85 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-otom.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-otom.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include "common.h" #include "otom.h" @@ -102,7 +102,6 @@ static void __init otom11_map_io(void) s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init otom11_init(void) @@ -116,7 +115,7 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1") .atag_offset = 0x100, .map_io = otom11_map_io, .init_machine = otom11_init, - .init_irq = s3c2410_init_irq, - .init_time = samsung_timer_init, + .init_irq = s3c24xx_init_irq, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-qt2410.c b/trunk/arch/arm/mach-s3c24xx/mach-qt2410.c index f8feaeadb55a..56175f0941b1 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-qt2410.c @@ -55,14 +55,13 @@ #include #include +#include #include #include #include #include -#include #include "common.h" -#include "common-smdk.h" static struct map_desc qt2410_iodesc[] __initdata = { { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE } @@ -305,7 +304,6 @@ static void __init qt2410_map_io(void) s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc)); s3c24xx_init_clocks(12*1000*1000); s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init qt2410_machine_init(void) @@ -343,8 +341,8 @@ static void __init qt2410_machine_init(void) MACHINE_START(QT2410, "QT2410") .atag_offset = 0x100, .map_io = qt2410_map_io, - .init_irq = s3c2410_init_irq, + .init_irq = s3c24xx_init_irq, .init_machine = qt2410_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-rx1950.c b/trunk/arch/arm/mach-s3c24xx/mach-rx1950.c index e4d67a33ebee..1f9ba2ae5288 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-rx1950.c @@ -58,7 +58,6 @@ #include #include #include -#include #include "common.h" #include "h1940.h" @@ -742,7 +741,6 @@ static void __init rx1950_map_io(void) s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc)); s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* setup PM */ @@ -813,8 +811,8 @@ MACHINE_START(RX1950, "HP iPAQ RX1950") .atag_offset = 0x100, .map_io = rx1950_map_io, .reserve = rx1950_reserve, - .init_irq = s3c2442_init_irq, + .init_irq = s3c24xx_init_irq, .init_machine = rx1950_init_machine, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-rx3715.c b/trunk/arch/arm/mach-s3c24xx/mach-rx3715.c index 3bc6231d0a1f..f20418a2fb1b 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-rx3715.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-rx3715.c @@ -49,7 +49,6 @@ #include #include #include -#include #include "common.h" #include "h1940.h" @@ -180,7 +179,6 @@ static void __init rx3715_map_io(void) s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } /* H1940 and RX3715 need to reserve this for suspend */ @@ -190,6 +188,11 @@ static void __init rx3715_reserve(void) memblock_reserve(0x30081000, 0x1000); } +static void __init rx3715_init_irq(void) +{ + s3c24xx_init_irq(); +} + static void __init rx3715_init_machine(void) { #ifdef CONFIG_PM_H1940 @@ -207,8 +210,8 @@ MACHINE_START(RX3715, "IPAQ-RX3715") .atag_offset = 0x100, .map_io = rx3715_map_io, .reserve = rx3715_reserve, - .init_irq = s3c2440_init_irq, + .init_irq = rx3715_init_irq, .init_machine = rx3715_init_machine, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2410.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2410.c index a773789e4f38..e184bfa9613a 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2410.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2410.c @@ -51,10 +51,10 @@ #include #include -#include + +#include #include "common.h" -#include "common-smdk.h" static struct map_desc smdk2410_iodesc[] __initdata = { /* nothing here yet */ @@ -101,7 +101,6 @@ static void __init smdk2410_map_io(void) s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2410_init(void) @@ -116,8 +115,8 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc /* Maintainer: Jonas Dietsche */ .atag_offset = 0x100, .map_io = smdk2410_map_io, - .init_irq = s3c2410_init_irq, + .init_irq = s3c24xx_init_irq, .init_machine = smdk2410_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2413.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2413.c index 8146e920f10d..86d7847c9d45 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2413.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2413.c @@ -41,13 +41,13 @@ #include #include +#include +#include #include #include #include -#include -#include "common.h" -#include "common-smdk.h" +#include static struct map_desc smdk2413_iodesc[] __initdata = { }; @@ -106,7 +106,6 @@ static void __init smdk2413_map_io(void) s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2413_machine_init(void) @@ -130,10 +129,10 @@ MACHINE_START(S3C2413, "S3C2413") .atag_offset = 0x100, .fixup = smdk2413_fixup, - .init_irq = s3c2412_init_irq, + .init_irq = s3c24xx_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END @@ -142,10 +141,10 @@ MACHINE_START(SMDK2412, "SMDK2412") .atag_offset = 0x100, .fixup = smdk2413_fixup, - .init_irq = s3c2412_init_irq, + .init_irq = s3c24xx_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END @@ -154,9 +153,9 @@ MACHINE_START(SMDK2413, "SMDK2413") .atag_offset = 0x100, .fixup = smdk2413_fixup, - .init_irq = s3c2412_init_irq, + .init_irq = s3c24xx_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2416.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2416.c index cb46847c66b4..ebb2e61f3d07 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2416.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2416.c @@ -42,6 +42,7 @@ #include #include +#include #include #include #include @@ -50,12 +51,10 @@ #include #include #include -#include #include -#include "common.h" -#include "common-smdk.h" +#include static struct map_desc smdk2416_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -222,7 +221,6 @@ static void __init smdk2416_map_io(void) s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2416_machine_init(void) @@ -255,6 +253,6 @@ MACHINE_START(SMDK2416, "SMDK2416") .init_irq = s3c2416_init_irq, .map_io = smdk2416_map_io, .init_machine = smdk2416_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2416_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2440.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2440.c index de2e5d39a847..08cc38c8a4ae 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2440.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2440.c @@ -38,13 +38,15 @@ #include #include +#include +#include #include #include #include -#include + +#include #include "common.h" -#include "common-smdk.h" static struct map_desc smdk2440_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -161,7 +163,6 @@ static void __init smdk2440_map_io(void) s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc)); s3c24xx_init_clocks(16934400); s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2440_machine_init(void) @@ -177,9 +178,9 @@ MACHINE_START(S3C2440, "SMDK2440") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, - .init_irq = s3c2440_init_irq, + .init_irq = s3c24xx_init_irq, .map_io = smdk2440_map_io, .init_machine = smdk2440_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2443.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2443.c index 9435c3bef18a..fc65d74d3c73 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2443.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2443.c @@ -38,13 +38,13 @@ #include #include +#include +#include #include #include #include -#include -#include "common.h" -#include "common-smdk.h" +#include static struct map_desc smdk2443_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -122,7 +122,6 @@ static void __init smdk2443_map_io(void) s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2443_machine_init(void) @@ -144,6 +143,6 @@ MACHINE_START(SMDK2443, "SMDK2443") .init_irq = s3c2443_init_irq, .map_io = smdk2443_map_io, .init_machine = smdk2443_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2443_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/trunk/arch/arm/mach-s3c24xx/mach-tct_hammer.c index 7fad8f055cab..24b3d79e7b2c 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-tct_hammer.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-tct_hammer.c @@ -53,7 +53,6 @@ #include #include #include -#include #include "common.h" @@ -137,7 +136,6 @@ static void __init tct_hammer_map_io(void) s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init tct_hammer_init(void) @@ -149,8 +147,8 @@ static void __init tct_hammer_init(void) MACHINE_START(TCT_HAMMER, "TCT_HAMMER") .atag_offset = 0x100, .map_io = tct_hammer_map_io, - .init_irq = s3c2410_init_irq, + .init_irq = s3c24xx_init_irq, .init_machine = tct_hammer_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-vr1000.c b/trunk/arch/arm/mach-s3c24xx/mach-vr1000.c index 42e7187fed60..ec42d1e4e465 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-vr1000.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-vr1000.c @@ -45,7 +45,6 @@ #include #include #include -#include #include "bast.h" #include "common.h" @@ -333,7 +332,6 @@ static void __init vr1000_map_io(void) s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init vr1000_init(void) @@ -355,7 +353,7 @@ MACHINE_START(VR1000, "Thorcom-VR1000") .atag_offset = 0x100, .map_io = vr1000_map_io, .init_machine = vr1000_init, - .init_irq = s3c2410_init_irq, - .init_time = samsung_timer_init, + .init_irq = s3c24xx_init_irq, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-vstms.c b/trunk/arch/arm/mach-s3c24xx/mach-vstms.c index b66588428ec9..3e2bfddc9df1 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-vstms.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-vstms.c @@ -41,12 +41,12 @@ #include #include +#include +#include #include #include #include -#include -#include "common.h" static struct map_desc vstms_iodesc[] __initdata = { }; @@ -143,7 +143,6 @@ static void __init vstms_map_io(void) s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init vstms_init(void) @@ -158,9 +157,9 @@ MACHINE_START(VSTMS, "VSTMS") .atag_offset = 0x100, .fixup = vstms_fixup, - .init_irq = s3c2412_init_irq, + .init_irq = s3c24xx_init_irq, .init_machine = vstms_init, .map_io = vstms_map_io, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/pm-s3c2412.c b/trunk/arch/arm/mach-s3c24xx/pm-s3c2412.c index d75f95e487ee..668a78a8b195 100644 --- a/trunk/arch/arm/mach-s3c24xx/pm-s3c2412.c +++ b/trunk/arch/arm/mach-s3c24xx/pm-s3c2412.c @@ -29,7 +29,7 @@ #include #include -#include +#include #include "regs-dsc.h" #include "s3c2412-power.h" @@ -52,15 +52,8 @@ static int s3c2412_cpu_suspend(unsigned long arg) return 1; /* Aborting suspend */ } -/* mapping of interrupts to parts of the wakeup mask */ -static struct samsung_wakeup_mask wake_irqs[] = { - { .irq = IRQ_RTC, .bit = S3C2412_PWRCFG_RTC_MASKIRQ, }, -}; - static void s3c2412_pm_prepare(void) { - samsung_sync_wakemask(S3C2412_PWRCFG, - wake_irqs, ARRAY_SIZE(wake_irqs)); } static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif) diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2410.c b/trunk/arch/arm/mach-s3c24xx/s3c2410.c index d850ea5adac2..9ebef95da721 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2410.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2410.c @@ -37,6 +37,7 @@ #include #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2412.c b/trunk/arch/arm/mach-s3c24xx/s3c2412.c index 0f864d4c97de..0d592159a5c3 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2412.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2412.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "common.h" #include "regs-dsc.h" diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2416.c b/trunk/arch/arm/mach-s3c24xx/s3c2416.c index b9c5d382dafb..e30476db0295 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2416.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2416.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2440.c b/trunk/arch/arm/mach-s3c24xx/s3c2440.c index 5f9d6569475d..559e394e8989 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2440.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2440.c @@ -33,6 +33,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2442.c b/trunk/arch/arm/mach-s3c24xx/s3c2442.c index 6819961f6b19..f732826c2359 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2442.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2442.c @@ -44,6 +44,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2443.c b/trunk/arch/arm/mach-s3c24xx/s3c2443.c index 8328cd65bf3d..165b6a6b3daa 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2443.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2443.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c244x.c b/trunk/arch/arm/mach-s3c24xx/s3c244x.c index 2a35edb67354..ad2671baa910 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c244x.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c244x.c @@ -37,6 +37,8 @@ #include #include +#include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c64xx/Kconfig b/trunk/arch/arm/mach-s3c64xx/Kconfig index 283cb77d4721..131c86284711 100644 --- a/trunk/arch/arm/mach-s3c64xx/Kconfig +++ b/trunk/arch/arm/mach-s3c64xx/Kconfig @@ -17,13 +17,11 @@ config PLAT_S3C64XX # Configuration options for the S3C6410 CPU config CPU_S3C6400 - select SAMSUNG_HRT bool help Enable S3C6400 CPU support config CPU_S3C6410 - select SAMSUNG_HRT bool help Enable S3C6410 CPU support diff --git a/trunk/arch/arm/mach-s3c64xx/mach-anw6410.c b/trunk/arch/arm/mach-s3c64xx/mach-anw6410.c index 35e3f54574ef..728eef3296b2 100644 --- a/trunk/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/trunk/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -49,7 +49,6 @@ #include #include #include -#include #include "common.h" #include "regs-modem.h" @@ -209,7 +208,6 @@ static void __init anw6410_map_io(void) s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); anw6410_lcd_mode_set(); } @@ -234,6 +232,6 @@ MACHINE_START(ANW6410, "A&W6410") .map_io = anw6410_map_io, .init_machine = anw6410_machine_init, .init_late = s3c64xx_init_late, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c64xx/mach-crag6410.c b/trunk/arch/arm/mach-s3c64xx/mach-crag6410.c index 8ad88ace795a..1acf02bace57 100644 --- a/trunk/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/trunk/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -64,7 +64,6 @@ #include #include #include -#include #include "common.h" #include "crag6410.h" @@ -745,7 +744,6 @@ static void __init crag6410_map_io(void) s3c64xx_init_io(NULL, 0); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* LCD type and Bypass set by bootloader */ } @@ -870,6 +868,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") .map_io = crag6410_map_io, .init_machine = crag6410_machine_init, .init_late = s3c64xx_init_late, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c64xx/mach-hmt.c b/trunk/arch/arm/mach-s3c64xx/mach-hmt.c index 5b7f357d8c22..7212eb9cfeb9 100644 --- a/trunk/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/trunk/arch/arm/mach-s3c64xx/mach-hmt.c @@ -41,7 +41,6 @@ #include #include #include -#include #include "common.h" @@ -249,7 +248,6 @@ static void __init hmt_map_io(void) s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init hmt_machine_init(void) @@ -277,6 +275,6 @@ MACHINE_START(HMT, "Airgoo-HMT") .map_io = hmt_map_io, .init_machine = hmt_machine_init, .init_late = s3c64xx_init_late, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c64xx/mach-mini6410.c b/trunk/arch/arm/mach-s3c64xx/mach-mini6410.c index fc043e3ecdf8..4b41fcdaa7b6 100644 --- a/trunk/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/trunk/arch/arm/mach-s3c64xx/mach-mini6410.c @@ -41,7 +41,6 @@ #include