From 1d9030aa3e32c48033b511f631c8ba266502b224 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Tue, 8 May 2012 16:19:34 -0700 Subject: [PATCH] --- yaml --- r: 304594 b: refs/heads/master c: 2b7a521b121ebc16b9137f07ded7874105c9486a h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/staging/comedi/drivers/mite.h | 4 ++-- trunk/drivers/staging/comedi/drivers/ni_660x.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 2c607e3d8c08..d5edf07d9826 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a19fb006c4d37b321712268b3937079973c730d6 +refs/heads/master: 2b7a521b121ebc16b9137f07ded7874105c9486a diff --git a/trunk/drivers/staging/comedi/drivers/mite.h b/trunk/drivers/staging/comedi/drivers/mite.h index 999551f54c2a..83f1b27a4720 100644 --- a/trunk/drivers/staging/comedi/drivers/mite.h +++ b/trunk/drivers/staging/comedi/drivers/mite.h @@ -66,9 +66,9 @@ struct mite_struct { struct pci_dev *pcidev; resource_size_t mite_phys_addr; - void *mite_io_addr; + void __iomem *mite_io_addr; resource_size_t daq_phys_addr; - void *daq_io_addr; + void __iomem *daq_io_addr; struct mite_channel channels[MAX_MITE_DMA_CHANNELS]; short channel_allocated[MAX_MITE_DMA_CHANNELS]; diff --git a/trunk/drivers/staging/comedi/drivers/ni_660x.c b/trunk/drivers/staging/comedi/drivers/ni_660x.c index eea7047f6eac..21eb7fb5c42c 100644 --- a/trunk/drivers/staging/comedi/drivers/ni_660x.c +++ b/trunk/drivers/staging/comedi/drivers/ni_660x.c @@ -761,7 +761,7 @@ static inline void ni_660x_write_register(struct comedi_device *dev, unsigned chip_index, unsigned bits, enum NI_660x_Register reg) { - void *const write_address = + void __iomem *write_address = private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] + registerData[reg].offset; @@ -784,7 +784,7 @@ static inline unsigned ni_660x_read_register(struct comedi_device *dev, unsigned chip_index, enum NI_660x_Register reg) { - void *const read_address = + void __iomem *read_address = private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] + registerData[reg].offset;