From 1e07faeb0992e738210c250aeed478996356f739 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 31 Oct 2012 18:12:52 -0200 Subject: [PATCH] --- yaml --- r: 345254 b: refs/heads/master c: 223a6fdfbf7e26d9ad5ee54e258eb164412fcbc0 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index aad13c4f3e9c..c05cbb4c8ec0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8a52fd9f240a6e2b73361fb825145f9951fc552d +refs/heads/master: 223a6fdfbf7e26d9ad5ee54e258eb164412fcbc0 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 1b57fbc5eb5b..7509e7903c22 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -1729,6 +1729,11 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, assert_fdi_tx_enabled(dev_priv, cpu_transcoder); assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); + /* Workaround: set timing override bit. */ + val = I915_READ(_TRANSA_CHICKEN2); + val |= TRANS_AUTOTRAIN_GEN_STALL_DIS; + I915_WRITE(_TRANSA_CHICKEN2, val); + val = TRANS_ENABLE; pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); @@ -1780,6 +1785,11 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv, /* wait for PCH transcoder off, transcoder state */ if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) DRM_ERROR("Failed to disable PCH transcoder\n"); + + /* Workaround: clear timing override bit. */ + val = I915_READ(_TRANSA_CHICKEN2); + val &= ~TRANS_AUTOTRAIN_GEN_STALL_DIS; + I915_WRITE(_TRANSA_CHICKEN2, val); } /**