From 1e590b5501f625fdb4a7d2408fc333023283429c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 26 Sep 2012 15:01:39 +1000 Subject: [PATCH] --- yaml --- r: 329688 b: refs/heads/master c: 8a57d279d6e1bf19d2d2e54f51d4f40c46c7d1a8 h: refs/heads/master v: v3 --- [refs] | 2 +- .../gpu/drm/nouveau/core/engine/dmaobj/nv04.c | 17 ++++++++++------- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/[refs] b/[refs] index 062276421e29..734528f617d1 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: dc73b45ad456b173610a211c588d003f7ea77957 +refs/heads/master: 8a57d279d6e1bf19d2d2e54f51d4f40c46c7d1a8 diff --git a/trunk/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/trunk/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c index 5ad76f74416f..9f4cc2f31994 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c +++ b/trunk/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c @@ -44,21 +44,24 @@ nv04_dmaobj_bind(struct nouveau_dmaeng *dmaeng, struct nouveau_dmaobj *dmaobj, struct nouveau_gpuobj **pgpuobj) { + struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaeng); struct nouveau_gpuobj *gpuobj; u32 flags0 = nv_mclass(dmaobj); u32 flags2 = 0x00000000; - u32 offset = (dmaobj->start & 0xfffff000); - u32 adjust = (dmaobj->start & 0x00000fff); + u64 offset = dmaobj->start & 0xfffff000; + u64 adjust = dmaobj->start & 0x00000fff; u32 length = dmaobj->limit - dmaobj->start; int ret; if (dmaobj->target == NV_MEM_TARGET_VM) { - gpuobj = nv04_vmmgr(dmaeng)->vm->pgt[0].obj[0]; - if (dmaobj->start == 0) - return nouveau_gpuobj_dup(parent, gpuobj, pgpuobj); + if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) { + struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0]; + if (!dmaobj->start) + return nouveau_gpuobj_dup(parent, pgt, pgpuobj); + offset = nv_ro32(pgt, 8 + (offset >> 10)); + offset &= 0xfffff000; + } - offset = nv_ro32(gpuobj, 8 + (offset >> 10)); - offset &= 0xfffff000; dmaobj->target = NV_MEM_TARGET_PCI; dmaobj->access = NV_MEM_ACCESS_RW; }