From 1f3c5af6175cb25300918258dd9acef74ea822b5 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@freescale.com>
Date: Sat, 28 May 2005 15:52:15 -0700
Subject: [PATCH] --- yaml --- r: 1655 b: refs/heads/master c:
 f9e4a005827ec0b33f0c61fec1634a5a3421decd h: refs/heads/master i:   1653:
 ee26483ba0bc6add861cd71028d993235b349aae   1651:
 d885a4c21b62997d18cfbc8bc87a27ae6438c50a   1647:
 1550b49c9cb6ed22e96405b3bf9385f4139552c7 v: v3

---
 [refs]                                      |  2 +-
 trunk/arch/ppc/platforms/83xx/mpc834x_sys.h |  6 +++++
 trunk/arch/ppc/syslib/ppc83xx_setup.c       | 28 +++++++++++++++++++++
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 76551bcec933..fd0a5fc16c8f 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ff945023c6a455679165b14d298316e262ceeb1f
+refs/heads/master: f9e4a005827ec0b33f0c61fec1634a5a3421decd
diff --git a/trunk/arch/ppc/platforms/83xx/mpc834x_sys.h b/trunk/arch/ppc/platforms/83xx/mpc834x_sys.h
index 49db0f4c847e..a2f6e49d7151 100644
--- a/trunk/arch/ppc/platforms/83xx/mpc834x_sys.h
+++ b/trunk/arch/ppc/platforms/83xx/mpc834x_sys.h
@@ -28,6 +28,12 @@
 #define BCSR_PHYS_ADDR		((uint)0xf8000000)
 #define BCSR_SIZE		((uint)(32 * 1024))
 
+#define BCSR_MISC_REG2_OFF	0x07
+#define BCSR_MISC_REG2_PORESET	0x01
+
+#define BCSR_MISC_REG3_OFF	0x08
+#define BCSR_MISC_REG3_CNFLOCK	0x80
+
 #ifdef CONFIG_PCI
 /* PCI interrupt controller */
 #define PIRQA        MPC83xx_IRQ_IRQ4
diff --git a/trunk/arch/ppc/syslib/ppc83xx_setup.c b/trunk/arch/ppc/syslib/ppc83xx_setup.c
index c28f9d679484..843cf8873e60 100644
--- a/trunk/arch/ppc/syslib/ppc83xx_setup.c
+++ b/trunk/arch/ppc/syslib/ppc83xx_setup.c
@@ -29,6 +29,7 @@
 #include <asm/mmu.h>
 #include <asm/ppc_sys.h>
 #include <asm/kgdb.h>
+#include <asm/delay.h>
 
 #include <syslib/ppc83xx_setup.h>
 
@@ -117,7 +118,34 @@ mpc83xx_early_serial_map(void)
 void
 mpc83xx_restart(char *cmd)
 {
+	volatile unsigned char __iomem *reg;
+	unsigned char tmp;
+
+	reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
+
 	local_irq_disable();
+
+	/*
+	 * Unlock the BCSR bits so a PRST will update the contents.
+	 * Otherwise the reset asserts but doesn't clear.
+	 */
+	tmp = in_8(reg + BCSR_MISC_REG3_OFF);
+	tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
+	out_8(reg + BCSR_MISC_REG3_OFF, tmp);
+
+	/*
+	 * Trigger a reset via a low->high transition of the
+	 * PORESET bit.
+	 */
+	tmp = in_8(reg + BCSR_MISC_REG2_OFF);
+	tmp &= ~BCSR_MISC_REG2_PORESET;
+	out_8(reg + BCSR_MISC_REG2_OFF, tmp);
+
+	udelay(1);
+
+	tmp |= BCSR_MISC_REG2_PORESET;
+	out_8(reg + BCSR_MISC_REG2_OFF, tmp);
+
 	for(;;);
 }