From 1f9c480430263cef412422954b998da6b0b62d8e Mon Sep 17 00:00:00 2001
From: Mark Langsdorf <mark.langsdorf@calxeda.com>
Date: Mon, 28 Jan 2013 16:13:13 +0000
Subject: [PATCH] --- yaml --- r: 351021 b: refs/heads/master c:
 b5964708532f4713e9cfb1b8b1a6ac8544fc66af h: refs/heads/master i:   351019:
 bebadec114aab949ebdfe736d30c52c529150bf9 v: v3

---
 [refs]                           | 2 +-
 trunk/drivers/clk/clk-highbank.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index ec7347d37dc9..79bd6b7b9f67 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: bd603455f366bd66a5e1870bc285c05c9cb6a72d
+refs/heads/master: b5964708532f4713e9cfb1b8b1a6ac8544fc66af
diff --git a/trunk/drivers/clk/clk-highbank.c b/trunk/drivers/clk/clk-highbank.c
index 52fecadf004a..3a0b723da2bc 100644
--- a/trunk/drivers/clk/clk-highbank.c
+++ b/trunk/drivers/clk/clk-highbank.c
@@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
 		reg |= HB_PLL_EXT_ENA;
 		reg &= ~HB_PLL_EXT_BYPASS;
 	} else {
+		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
 		reg &= ~HB_PLL_DIVQ_MASK;
 		reg |= divq << HB_PLL_DIVQ_SHIFT;
+		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
 	}
 	writel(reg, hbclk->reg);