diff --git a/[refs] b/[refs]
index 3993e4dd179f..a0f66fe77e03 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: de9c27bf70964a8b257eaeb8f71f1898e9f4ac7d
+refs/heads/master: c64e311e650921fb014af2b3c500180fc65802b9
diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c
index 358c30127f1a..c31a64daf479 100644
--- a/trunk/drivers/gpu/drm/i915/intel_display.c
+++ b/trunk/drivers/gpu/drm/i915/intel_display.c
@@ -1857,12 +1857,18 @@ static void ironlake_fdi_enable(struct drm_crtc *crtc)
 	int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 	int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
 	int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
+	int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
 	u32 temp;
 	u32 pipe_bpc;
+	u32 tx_size;
 
 	temp = I915_READ(pipeconf_reg);
 	pipe_bpc = temp & PIPE_BPC_MASK;
 
+	/* Write the TU size bits so error detection works */
+	tx_size = I915_READ(data_m1_reg) & TU_SIZE_MASK;
+	I915_WRITE(FDI_RXA_TUSIZE1, tx_size);
+
 	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
 	temp = I915_READ(fdi_rx_reg);
 	/*