From 1fdf8d1ca6745b7eac0385fe8df4f5a80478dc78 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 30 Jan 2008 13:33:36 +0100 Subject: [PATCH] --- yaml --- r: 80400 b: refs/heads/master c: ff472a114ca11f5354912745fbb94bb66ec10916 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/x86/kernel/reboot_fixups_32.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index ded791befca9..336d47407acb 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5e3a77e9a9b7bfc1f69f51fe6d34aa649887980c +refs/heads/master: ff472a114ca11f5354912745fbb94bb66ec10916 diff --git a/trunk/arch/x86/kernel/reboot_fixups_32.c b/trunk/arch/x86/kernel/reboot_fixups_32.c index f452726c0fe2..dec0b5ec25c2 100644 --- a/trunk/arch/x86/kernel/reboot_fixups_32.c +++ b/trunk/arch/x86/kernel/reboot_fixups_32.c @@ -30,6 +30,19 @@ static void cs5536_warm_reset(struct pci_dev *dev) udelay(50); /* shouldn't get here but be safe and spin a while */ } +static void rdc321x_reset(struct pci_dev *dev) +{ + unsigned i; + /* Voluntary reset the watchdog timer */ + outl(0x80003840, 0xCF8); + /* Generate a CPU reset on next tick */ + i = inl(0xCFC); + /* Use the minimum timer resolution */ + i |= 0x1600; + outl(i, 0xCFC); + outb(1, 0x92); +} + struct device_fixup { unsigned int vendor; unsigned int device; @@ -40,6 +53,7 @@ static struct device_fixup fixups_table[] = { { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, cs5530a_warm_reset }, { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, cs5536_warm_reset }, { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE, cs5530a_warm_reset }, +{ PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6030, rdc321x_reset }, }; /*