diff --git a/[refs] b/[refs] index a70760b11017..27f09e8a61de 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 1a961ce09fe39df9a1b796df98794fd32c76c413 +refs/heads/master: ba59953d281747b1f7518a60f0ba8ff671cd0d65 diff --git a/trunk/drivers/gpu/drm/drm_crtc_helper.c b/trunk/drivers/gpu/drm/drm_crtc_helper.c index 7d0f00a935fa..aba79c494587 100644 --- a/trunk/drivers/gpu/drm/drm_crtc_helper.c +++ b/trunk/drivers/gpu/drm/drm_crtc_helper.c @@ -702,7 +702,7 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, if (encoder->crtc != crtc) continue; - DRM_DEBUG("%s: set mode %s %x\n", drm_get_encoder_name(encoder), + DRM_INFO("%s: set mode %s %x\n", drm_get_encoder_name(encoder), mode->name, mode->base.id); encoder_funcs = encoder->helper_private; encoder_funcs->mode_set(encoder, mode, adjusted_mode); @@ -1032,8 +1032,7 @@ bool drm_helper_initial_config(struct drm_device *dev) /* * we shouldn't end up with no modes here. */ - if (count == 0) - printk(KERN_INFO "No connectors reported connected with modes\n"); + WARN(!count, "No connectors reported connected with modes\n"); drm_setup_crtcs(dev); diff --git a/trunk/drivers/gpu/drm/drm_edid.c b/trunk/drivers/gpu/drm/drm_edid.c index f665b05592f3..defcaf108460 100644 --- a/trunk/drivers/gpu/drm/drm_edid.c +++ b/trunk/drivers/gpu/drm/drm_edid.c @@ -633,7 +633,8 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, return NULL; } if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { - printk(KERN_WARNING "composite sync not supported\n"); + printk(KERN_WARNING "integrated sync not supported\n"); + return NULL; } /* it is incorrect if hsync/vsync width is zero */ diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_dma.c b/trunk/drivers/gpu/drm/nouveau/nouveau_dma.c index 7afbe8b40d51..50d9e67745af 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_dma.c @@ -126,47 +126,52 @@ OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords) chan->dma.cur += nr_dwords; } -static inline bool -READ_GET(struct nouveau_channel *chan, uint32_t *get) +/* Fetch and adjust GPU GET pointer + * + * Returns: + * value >= 0, the adjusted GET pointer + * -EINVAL if GET pointer currently outside main push buffer + * -EBUSY if timeout exceeded + */ +static inline int +READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout) { uint32_t val; val = nvchan_rd32(chan, chan->user_get); - if (val < chan->pushbuf_base || - val > chan->pushbuf_base + (chan->dma.max << 2)) { - /* meaningless to dma_wait() except to know whether the - * GPU has stalled or not - */ - *get = val; - return false; + + /* reset counter as long as GET is still advancing, this is + * to avoid misdetecting a GPU lockup if the GPU happens to + * just be processing an operation that takes a long time + */ + if (val != *prev_get) { + *prev_get = val; + *timeout = 0; + } + + if ((++*timeout & 0xff) == 0) { + DRM_UDELAY(1); + if (*timeout > 100000) + return -EBUSY; } - *get = (val - chan->pushbuf_base) >> 2; - return true; + if (val < chan->pushbuf_base || + val > chan->pushbuf_base + (chan->dma.max << 2)) + return -EINVAL; + + return (val - chan->pushbuf_base) >> 2; } int nouveau_dma_wait(struct nouveau_channel *chan, int size) { - uint32_t get, prev_get = 0, cnt = 0; - bool get_valid; + uint32_t prev_get = 0, cnt = 0; + int get; while (chan->dma.free < size) { - /* reset counter as long as GET is still advancing, this is - * to avoid misdetecting a GPU lockup if the GPU happens to - * just be processing an operation that takes a long time - */ - get_valid = READ_GET(chan, &get); - if (get != prev_get) { - prev_get = get; - cnt = 0; - } - - if ((++cnt & 0xff) == 0) { - DRM_UDELAY(1); - if (cnt > 100000) - return -EBUSY; - } + get = READ_GET(chan, &prev_get, &cnt); + if (unlikely(get == -EBUSY)) + return -EBUSY; /* loop until we have a usable GET pointer. the value * we read from the GPU may be outside the main ring if @@ -177,7 +182,7 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size) * from the SKIPS area, so the code below doesn't have to deal * with some fun corner cases. */ - if (!get_valid || get < NOUVEAU_DMA_SKIPS) + if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS) continue; if (get <= chan->dma.cur) { @@ -203,6 +208,19 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size) * after processing the currently pending commands. */ OUT_RING(chan, chan->pushbuf_base | 0x20000000); + + /* wait for GET to depart from the skips area. + * prevents writing GET==PUT and causing a race + * condition that causes us to think the GPU is + * idle when it's not. + */ + do { + get = READ_GET(chan, &prev_get, &cnt); + if (unlikely(get == -EBUSY)) + return -EBUSY; + if (unlikely(get == -EINVAL)) + continue; + } while (get <= NOUVEAU_DMA_SKIPS); WRITE_PUT(NOUVEAU_DMA_SKIPS); /* we're now submitting commands at the start of diff --git a/trunk/drivers/gpu/drm/radeon/Makefile b/trunk/drivers/gpu/drm/radeon/Makefile index 1cc7b937b1ea..b5f5fe75e6af 100644 --- a/trunk/drivers/gpu/drm/radeon/Makefile +++ b/trunk/drivers/gpu/drm/radeon/Makefile @@ -24,9 +24,6 @@ $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable $(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable $(call if_changed,mkregtable) -$(obj)/r420_reg_safe.h: $(src)/reg_srcs/r420 $(obj)/mkregtable - $(call if_changed,mkregtable) - $(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable $(call if_changed,mkregtable) @@ -38,8 +35,6 @@ $(obj)/rv515.o: $(obj)/rv515_reg_safe.h $(obj)/r300.o: $(obj)/r300_reg_safe.h -$(obj)/r420.o: $(obj)/r420_reg_safe.h - $(obj)/rs600.o: $(obj)/rs600_reg_safe.h radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ diff --git a/trunk/drivers/gpu/drm/radeon/r100.c b/trunk/drivers/gpu/drm/radeon/r100.c index 62b27bede651..8760d66e058a 100644 --- a/trunk/drivers/gpu/drm/radeon/r100.c +++ b/trunk/drivers/gpu/drm/radeon/r100.c @@ -3399,7 +3399,9 @@ int r100_mc_init(struct radeon_device *rdev) if (rdev->flags & RADEON_IS_AGP) { r = radeon_agp_init(rdev); if (r) { - radeon_agp_disable(rdev); + printk(KERN_WARNING "[drm] Disabling AGP\n"); + rdev->flags &= ~RADEON_IS_AGP; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; } else { rdev->mc.gtt_location = rdev->mc.agp_base; } diff --git a/trunk/drivers/gpu/drm/radeon/r420.c b/trunk/drivers/gpu/drm/radeon/r420.c index 4526faaacca8..1d4d16ed7db1 100644 --- a/trunk/drivers/gpu/drm/radeon/r420.c +++ b/trunk/drivers/gpu/drm/radeon/r420.c @@ -32,13 +32,6 @@ #include "atom.h" #include "r100d.h" #include "r420d.h" -#include "r420_reg_safe.h" - -static void r420_set_reg_safe(struct radeon_device *rdev) -{ - rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; - rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); -} int r420_mc_init(struct radeon_device *rdev) { @@ -50,7 +43,9 @@ int r420_mc_init(struct radeon_device *rdev) if (rdev->flags & RADEON_IS_AGP) { r = radeon_agp_init(rdev); if (r) { - radeon_agp_disable(rdev); + printk(KERN_WARNING "[drm] Disabling AGP\n"); + rdev->flags &= ~RADEON_IS_AGP; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; } else { rdev->mc.gtt_location = rdev->mc.agp_base; } @@ -383,7 +378,7 @@ int r420_init(struct radeon_device *rdev) if (r) return r; } - r420_set_reg_safe(rdev); + r300_set_reg_safe(rdev); rdev->accel_working = true; r = r420_startup(rdev); if (r) { diff --git a/trunk/drivers/gpu/drm/radeon/r600.c b/trunk/drivers/gpu/drm/radeon/r600.c index b3713f61964c..1f4f83d6fbe6 100644 --- a/trunk/drivers/gpu/drm/radeon/r600.c +++ b/trunk/drivers/gpu/drm/radeon/r600.c @@ -624,6 +624,7 @@ int r600_mc_init(struct radeon_device *rdev) fixed20_12 a; u32 tmp; int chansize, numchan; + int r; /* Get VRAM informations */ rdev->mc.vram_is_ddr = true; @@ -666,6 +667,9 @@ int r600_mc_init(struct radeon_device *rdev) rdev->mc.real_vram_size = rdev->mc.aper_size; if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) + return r; /* gtt_size is setup by radeon_agp_init */ rdev->mc.gtt_location = rdev->mc.agp_base; tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; @@ -1957,13 +1961,11 @@ int r600_suspend(struct radeon_device *rdev) r600_wb_disable(rdev); r600_pcie_gart_disable(rdev); /* unpin shaders bo */ - if (rdev->r600_blit.shader_obj) { - r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); - if (!r) { - radeon_bo_unpin(rdev->r600_blit.shader_obj); - radeon_bo_unreserve(rdev->r600_blit.shader_obj); - } - } + r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); + if (unlikely(r != 0)) + return r; + radeon_bo_unpin(rdev->r600_blit.shader_obj); + radeon_bo_unreserve(rdev->r600_blit.shader_obj); return 0; } @@ -2024,11 +2026,6 @@ int r600_init(struct radeon_device *rdev) r = radeon_fence_driver_init(rdev); if (r) return r; - if (rdev->flags & RADEON_IS_AGP) { - r = radeon_agp_init(rdev); - if (r) - radeon_agp_disable(rdev); - } r = r600_mc_init(rdev); if (r) return r; @@ -2732,7 +2729,7 @@ int r600_irq_process(struct radeon_device *rdev) } break; default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); + DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); break; } break; @@ -2752,7 +2749,7 @@ int r600_irq_process(struct radeon_device *rdev) } break; default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); + DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); break; } break; @@ -2801,7 +2798,7 @@ int r600_irq_process(struct radeon_device *rdev) } break; default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); + DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); break; } break; @@ -2815,7 +2812,7 @@ int r600_irq_process(struct radeon_device *rdev) DRM_DEBUG("IH: CP EOP\n"); break; default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); + DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); break; } diff --git a/trunk/drivers/gpu/drm/radeon/r600_blit_kms.c b/trunk/drivers/gpu/drm/radeon/r600_blit_kms.c index 2bedce477a97..8787ea89dc6e 100644 --- a/trunk/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/trunk/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -512,16 +512,14 @@ void r600_blit_fini(struct radeon_device *rdev) { int r; - if (rdev->r600_blit.shader_obj == NULL) - return; - /* If we can't reserve the bo, unref should be enough to destroy - * it when it becomes idle. - */ r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); - if (!r) { - radeon_bo_unpin(rdev->r600_blit.shader_obj); - radeon_bo_unreserve(rdev->r600_blit.shader_obj); + if (unlikely(r != 0)) { + dev_err(rdev->dev, "(%d) can't finish r600 blit\n", r); + goto out_unref; } + radeon_bo_unpin(rdev->r600_blit.shader_obj); + radeon_bo_unreserve(rdev->r600_blit.shader_obj); +out_unref: radeon_bo_unref(&rdev->r600_blit.shader_obj); } diff --git a/trunk/drivers/gpu/drm/radeon/radeon.h b/trunk/drivers/gpu/drm/radeon/radeon.h index ab37dd0f2e71..eb5f99b9469d 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon.h +++ b/trunk/drivers/gpu/drm/radeon/radeon.h @@ -1017,8 +1017,6 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) /* Common functions */ -/* AGP */ -extern void radeon_agp_disable(struct radeon_device *rdev); extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); extern int radeon_modeset_init(struct radeon_device *rdev); extern void radeon_modeset_fini(struct radeon_device *rdev); diff --git a/trunk/drivers/gpu/drm/radeon/radeon_agp.c b/trunk/drivers/gpu/drm/radeon/radeon_agp.c index c9ad7f5cc1ac..220f454ea9fa 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_agp.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_agp.c @@ -133,13 +133,6 @@ int radeon_agp_init(struct radeon_device *rdev) bool is_v3; int ret; - if (rdev->ddev->agp->agp_info.aper_size < 32) { - dev_warn(rdev->dev, "AGP aperture to small (%dM) " - "need at least 32M, disabling AGP\n", - rdev->ddev->agp->agp_info.aper_size); - return -EINVAL; - } - /* Acquire AGP. */ if (!rdev->ddev->agp->acquired) { ret = drm_agp_acquire(rdev->ddev); diff --git a/trunk/drivers/gpu/drm/radeon/radeon_combios.c b/trunk/drivers/gpu/drm/radeon/radeon_combios.c index 579c8920e081..7914455c96ca 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_combios.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_combios.c @@ -687,9 +687,6 @@ radeon_combios_get_tv_info(struct radeon_device *rdev) uint16_t tv_info; enum radeon_tv_std tv_std = TV_STD_NTSC; - if (rdev->bios == NULL) - return tv_std; - tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); if (tv_info) { if (RBIOS8(tv_info + 6) == 'T') { diff --git a/trunk/drivers/gpu/drm/radeon/radeon_connectors.c b/trunk/drivers/gpu/drm/radeon/radeon_connectors.c index 55266416fa47..9da10dd5df80 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_connectors.c @@ -900,18 +900,10 @@ static void radeon_dvi_force(struct drm_connector *connector) static int radeon_dvi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { - struct drm_device *dev = connector->dev; - struct radeon_device *rdev = dev->dev_private; struct radeon_connector *radeon_connector = to_radeon_connector(connector); /* XXX check mode bandwidth */ - /* clocks over 135 MHz have heat issues with DVI on RV100 */ - if (radeon_connector->use_digital && - (rdev->family == CHIP_RV100) && - (mode->clock > 135000)) - return MODE_CLOCK_HIGH; - if (radeon_connector->use_digital && (mode->clock > 165000)) { if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || diff --git a/trunk/drivers/gpu/drm/radeon/radeon_device.c b/trunk/drivers/gpu/drm/radeon/radeon_device.c index 768b1509fa03..0c51f8e46613 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_device.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_device.c @@ -544,7 +544,6 @@ void radeon_agp_disable(struct radeon_device *rdev) rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; rdev->asic->gart_set_page = &r100_pci_gart_set_page; } - rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; } void radeon_check_arguments(struct radeon_device *rdev) diff --git a/trunk/drivers/gpu/drm/radeon/radeon_display.c b/trunk/drivers/gpu/drm/radeon/radeon_display.c index 49f3c69cf240..0ec491ead2ff 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_display.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_display.c @@ -357,8 +357,7 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; - if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || - dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) + if (dig->dp_i2c_bus) radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); } if (!radeon_connector->ddc_bus) @@ -668,6 +667,7 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) radeonfb_remove(dev, fb); if (radeon_fb->obj) { + radeon_gem_object_unpin(radeon_fb->obj); mutex_lock(&dev->struct_mutex); drm_gem_object_unreference(radeon_fb->obj); mutex_unlock(&dev->struct_mutex); diff --git a/trunk/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/trunk/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 38e45e231ef5..981508ff7037 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -46,7 +46,6 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; int panel_pwr_delay = 2000; - bool is_mac = false; DRM_DEBUG("\n"); if (radeon_encoder->enc_priv) { @@ -59,15 +58,6 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) } } - /* macs (and possibly some x86 oem systems?) wire up LVDS strangely - * Taken from radeonfb. - */ - if ((rdev->mode_info.connector_table == CT_IBOOK) || - (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || - (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || - (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) - is_mac = true; - switch (mode) { case DRM_MODE_DPMS_ON: disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); @@ -84,8 +74,6 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON); - if (is_mac) - lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); udelay(panel_pwr_delay * 1000); WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); @@ -97,14 +85,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; - if (is_mac) { - lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; - WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); - lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); - } else { - WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); - lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); - } + lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); udelay(panel_pwr_delay * 1000); WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); diff --git a/trunk/drivers/gpu/drm/radeon/radeon_ttm.c b/trunk/drivers/gpu/drm/radeon/radeon_ttm.c index db820ae9a034..a00450743d60 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_ttm.c @@ -215,10 +215,7 @@ static void radeon_evict_flags(struct ttm_buffer_object *bo, rbo = container_of(bo, struct radeon_bo, tbo); switch (bo->mem.mem_type) { case TTM_PL_VRAM: - if (rbo->rdev->cp.ready == false) - radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); - else - radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); + radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); break; case TTM_PL_TT: default: diff --git a/trunk/drivers/gpu/drm/radeon/reg_srcs/r420 b/trunk/drivers/gpu/drm/radeon/reg_srcs/r420 deleted file mode 100644 index 989f7a020832..000000000000 --- a/trunk/drivers/gpu/drm/radeon/reg_srcs/r420 +++ /dev/null @@ -1,795 +0,0 @@ -r420 0x4f60 -0x1434 SRC_Y_X -0x1438 DST_Y_X -0x143C DST_HEIGHT_WIDTH -0x146C DP_GUI_MASTER_CNTL -0x1474 BRUSH_Y_X -0x1478 DP_BRUSH_BKGD_CLR -0x147C DP_BRUSH_FRGD_CLR -0x1480 BRUSH_DATA0 -0x1484 BRUSH_DATA1 -0x1598 DST_WIDTH_HEIGHT -0x15C0 CLR_CMP_CNTL -0x15C4 CLR_CMP_CLR_SRC -0x15C8 CLR_CMP_CLR_DST -0x15CC CLR_CMP_MSK -0x15D8 DP_SRC_FRGD_CLR -0x15DC DP_SRC_BKGD_CLR -0x1600 DST_LINE_START -0x1604 DST_LINE_END -0x1608 DST_LINE_PATCOUNT -0x16C0 DP_CNTL -0x16CC DP_WRITE_MSK -0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR -0x16E8 DEFAULT_SC_BOTTOM_RIGHT -0x16EC SC_TOP_LEFT -0x16F0 SC_BOTTOM_RIGHT -0x16F4 SRC_SC_BOTTOM_RIGHT -0x1714 DSTCACHE_CTLSTAT -0x1720 WAIT_UNTIL -0x172C RBBM_GUICNTL -0x1D98 VAP_VPORT_XSCALE -0x1D9C VAP_VPORT_XOFFSET -0x1DA0 VAP_VPORT_YSCALE -0x1DA4 VAP_VPORT_YOFFSET -0x1DA8 VAP_VPORT_ZSCALE -0x1DAC VAP_VPORT_ZOFFSET -0x2080 VAP_CNTL -0x2090 VAP_OUT_VTX_FMT_0 -0x2094 VAP_OUT_VTX_FMT_1 -0x20B0 VAP_VTE_CNTL -0x2138 VAP_VF_MIN_VTX_INDX -0x2140 VAP_CNTL_STATUS -0x2150 VAP_PROG_STREAM_CNTL_0 -0x2154 VAP_PROG_STREAM_CNTL_1 -0x2158 VAP_PROG_STREAM_CNTL_2 -0x215C VAP_PROG_STREAM_CNTL_3 -0x2160 VAP_PROG_STREAM_CNTL_4 -0x2164 VAP_PROG_STREAM_CNTL_5 -0x2168 VAP_PROG_STREAM_CNTL_6 -0x216C VAP_PROG_STREAM_CNTL_7 -0x2180 VAP_VTX_STATE_CNTL -0x2184 VAP_VSM_VTX_ASSM -0x2188 VAP_VTX_STATE_IND_REG_0 -0x218C VAP_VTX_STATE_IND_REG_1 -0x2190 VAP_VTX_STATE_IND_REG_2 -0x2194 VAP_VTX_STATE_IND_REG_3 -0x2198 VAP_VTX_STATE_IND_REG_4 -0x219C VAP_VTX_STATE_IND_REG_5 -0x21A0 VAP_VTX_STATE_IND_REG_6 -0x21A4 VAP_VTX_STATE_IND_REG_7 -0x21A8 VAP_VTX_STATE_IND_REG_8 -0x21AC VAP_VTX_STATE_IND_REG_9 -0x21B0 VAP_VTX_STATE_IND_REG_10 -0x21B4 VAP_VTX_STATE_IND_REG_11 -0x21B8 VAP_VTX_STATE_IND_REG_12 -0x21BC VAP_VTX_STATE_IND_REG_13 -0x21C0 VAP_VTX_STATE_IND_REG_14 -0x21C4 VAP_VTX_STATE_IND_REG_15 -0x21DC VAP_PSC_SGN_NORM_CNTL -0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 -0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 -0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 -0x21EC VAP_PROG_STREAM_CNTL_EXT_3 -0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 -0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 -0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 -0x21FC VAP_PROG_STREAM_CNTL_EXT_7 -0x2200 VAP_PVS_VECTOR_INDX_REG -0x2204 VAP_PVS_VECTOR_DATA_REG -0x2208 VAP_PVS_VECTOR_DATA_REG_128 -0x221C VAP_CLIP_CNTL -0x2220 VAP_GB_VERT_CLIP_ADJ -0x2224 VAP_GB_VERT_DISC_ADJ -0x2228 VAP_GB_HORZ_CLIP_ADJ -0x222C VAP_GB_HORZ_DISC_ADJ -0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 -0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 -0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 -0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 -0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 -0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 -0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 -0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 -0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 -0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 -0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 -0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 -0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 -0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 -0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 -0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 -0x2284 VAP_PVS_STATE_FLUSH_REG -0x2288 VAP_PVS_VTX_TIMEOUT_REG -0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 -0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 -0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 -0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 -0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 -0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 -0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 -0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 -0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 -0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 -0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 -0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 -0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 -0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 -0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 -0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 -0x22D0 VAP_PVS_CODE_CNTL_0 -0x22D4 VAP_PVS_CONST_CNTL -0x22D8 VAP_PVS_CODE_CNTL_1 -0x22DC VAP_PVS_FLOW_CNTL_OPC -0x342C RB2D_DSTCACHE_CTLSTAT -0x4000 GB_VAP_RASTER_VTX_FMT_0 -0x4004 GB_VAP_RASTER_VTX_FMT_1 -0x4008 GB_ENABLE -0x401C GB_SELECT -0x4020 GB_AA_CONFIG -0x4024 GB_FIFO_SIZE -0x4100 TX_INVALTAGS -0x4200 GA_POINT_S0 -0x4204 GA_POINT_T0 -0x4208 GA_POINT_S1 -0x420C GA_POINT_T1 -0x4214 GA_TRIANGLE_STIPPLE -0x421C GA_POINT_SIZE -0x4230 GA_POINT_MINMAX -0x4234 GA_LINE_CNTL -0x4238 GA_LINE_STIPPLE_CONFIG -0x4260 GA_LINE_STIPPLE_VALUE -0x4264 GA_LINE_S0 -0x4268 GA_LINE_S1 -0x4278 GA_COLOR_CONTROL -0x427C GA_SOLID_RG -0x4280 GA_SOLID_BA -0x4288 GA_POLY_MODE -0x428C GA_ROUND_MODE -0x4290 GA_OFFSET -0x4294 GA_FOG_SCALE -0x4298 GA_FOG_OFFSET -0x42A0 SU_TEX_WRAP -0x42A4 SU_POLY_OFFSET_FRONT_SCALE -0x42A8 SU_POLY_OFFSET_FRONT_OFFSET -0x42AC SU_POLY_OFFSET_BACK_SCALE -0x42B0 SU_POLY_OFFSET_BACK_OFFSET -0x42B4 SU_POLY_OFFSET_ENABLE -0x42B8 SU_CULL_MODE -0x42C0 SU_DEPTH_SCALE -0x42C4 SU_DEPTH_OFFSET -0x42C8 SU_REG_DEST -0x4300 RS_COUNT -0x4304 RS_INST_COUNT -0x4310 RS_IP_0 -0x4314 RS_IP_1 -0x4318 RS_IP_2 -0x431C RS_IP_3 -0x4320 RS_IP_4 -0x4324 RS_IP_5 -0x4328 RS_IP_6 -0x432C RS_IP_7 -0x4330 RS_INST_0 -0x4334 RS_INST_1 -0x4338 RS_INST_2 -0x433C RS_INST_3 -0x4340 RS_INST_4 -0x4344 RS_INST_5 -0x4348 RS_INST_6 -0x434C RS_INST_7 -0x4350 RS_INST_8 -0x4354 RS_INST_9 -0x4358 RS_INST_10 -0x435C RS_INST_11 -0x4360 RS_INST_12 -0x4364 RS_INST_13 -0x4368 RS_INST_14 -0x436C RS_INST_15 -0x43A4 SC_HYPERZ_EN -0x43A8 SC_EDGERULE -0x43B0 SC_CLIP_0_A -0x43B4 SC_CLIP_0_B -0x43B8 SC_CLIP_1_A -0x43BC SC_CLIP_1_B -0x43C0 SC_CLIP_2_A -0x43C4 SC_CLIP_2_B -0x43C8 SC_CLIP_3_A -0x43CC SC_CLIP_3_B -0x43D0 SC_CLIP_RULE -0x43E0 SC_SCISSOR0 -0x43E8 SC_SCREENDOOR -0x4440 TX_FILTER1_0 -0x4444 TX_FILTER1_1 -0x4448 TX_FILTER1_2 -0x444C TX_FILTER1_3 -0x4450 TX_FILTER1_4 -0x4454 TX_FILTER1_5 -0x4458 TX_FILTER1_6 -0x445C TX_FILTER1_7 -0x4460 TX_FILTER1_8 -0x4464 TX_FILTER1_9 -0x4468 TX_FILTER1_10 -0x446C TX_FILTER1_11 -0x4470 TX_FILTER1_12 -0x4474 TX_FILTER1_13 -0x4478 TX_FILTER1_14 -0x447C TX_FILTER1_15 -0x4580 TX_CHROMA_KEY_0 -0x4584 TX_CHROMA_KEY_1 -0x4588 TX_CHROMA_KEY_2 -0x458C TX_CHROMA_KEY_3 -0x4590 TX_CHROMA_KEY_4 -0x4594 TX_CHROMA_KEY_5 -0x4598 TX_CHROMA_KEY_6 -0x459C TX_CHROMA_KEY_7 -0x45A0 TX_CHROMA_KEY_8 -0x45A4 TX_CHROMA_KEY_9 -0x45A8 TX_CHROMA_KEY_10 -0x45AC TX_CHROMA_KEY_11 -0x45B0 TX_CHROMA_KEY_12 -0x45B4 TX_CHROMA_KEY_13 -0x45B8 TX_CHROMA_KEY_14 -0x45BC TX_CHROMA_KEY_15 -0x45C0 TX_BORDER_COLOR_0 -0x45C4 TX_BORDER_COLOR_1 -0x45C8 TX_BORDER_COLOR_2 -0x45CC TX_BORDER_COLOR_3 -0x45D0 TX_BORDER_COLOR_4 -0x45D4 TX_BORDER_COLOR_5 -0x45D8 TX_BORDER_COLOR_6 -0x45DC TX_BORDER_COLOR_7 -0x45E0 TX_BORDER_COLOR_8 -0x45E4 TX_BORDER_COLOR_9 -0x45E8 TX_BORDER_COLOR_10 -0x45EC TX_BORDER_COLOR_11 -0x45F0 TX_BORDER_COLOR_12 -0x45F4 TX_BORDER_COLOR_13 -0x45F8 TX_BORDER_COLOR_14 -0x45FC TX_BORDER_COLOR_15 -0x4600 US_CONFIG -0x4604 US_PIXSIZE -0x4608 US_CODE_OFFSET -0x460C US_RESET -0x4610 US_CODE_ADDR_0 -0x4614 US_CODE_ADDR_1 -0x4618 US_CODE_ADDR_2 -0x461C US_CODE_ADDR_3 -0x4620 US_TEX_INST_0 -0x4624 US_TEX_INST_1 -0x4628 US_TEX_INST_2 -0x462C US_TEX_INST_3 -0x4630 US_TEX_INST_4 -0x4634 US_TEX_INST_5 -0x4638 US_TEX_INST_6 -0x463C US_TEX_INST_7 -0x4640 US_TEX_INST_8 -0x4644 US_TEX_INST_9 -0x4648 US_TEX_INST_10 -0x464C US_TEX_INST_11 -0x4650 US_TEX_INST_12 -0x4654 US_TEX_INST_13 -0x4658 US_TEX_INST_14 -0x465C US_TEX_INST_15 -0x4660 US_TEX_INST_16 -0x4664 US_TEX_INST_17 -0x4668 US_TEX_INST_18 -0x466C US_TEX_INST_19 -0x4670 US_TEX_INST_20 -0x4674 US_TEX_INST_21 -0x4678 US_TEX_INST_22 -0x467C US_TEX_INST_23 -0x4680 US_TEX_INST_24 -0x4684 US_TEX_INST_25 -0x4688 US_TEX_INST_26 -0x468C US_TEX_INST_27 -0x4690 US_TEX_INST_28 -0x4694 US_TEX_INST_29 -0x4698 US_TEX_INST_30 -0x469C US_TEX_INST_31 -0x46A4 US_OUT_FMT_0 -0x46A8 US_OUT_FMT_1 -0x46AC US_OUT_FMT_2 -0x46B0 US_OUT_FMT_3 -0x46B4 US_W_FMT -0x46B8 US_CODE_BANK -0x46BC US_CODE_EXT -0x46C0 US_ALU_RGB_ADDR_0 -0x46C4 US_ALU_RGB_ADDR_1 -0x46C8 US_ALU_RGB_ADDR_2 -0x46CC US_ALU_RGB_ADDR_3 -0x46D0 US_ALU_RGB_ADDR_4 -0x46D4 US_ALU_RGB_ADDR_5 -0x46D8 US_ALU_RGB_ADDR_6 -0x46DC US_ALU_RGB_ADDR_7 -0x46E0 US_ALU_RGB_ADDR_8 -0x46E4 US_ALU_RGB_ADDR_9 -0x46E8 US_ALU_RGB_ADDR_10 -0x46EC US_ALU_RGB_ADDR_11 -0x46F0 US_ALU_RGB_ADDR_12 -0x46F4 US_ALU_RGB_ADDR_13 -0x46F8 US_ALU_RGB_ADDR_14 -0x46FC US_ALU_RGB_ADDR_15 -0x4700 US_ALU_RGB_ADDR_16 -0x4704 US_ALU_RGB_ADDR_17 -0x4708 US_ALU_RGB_ADDR_18 -0x470C US_ALU_RGB_ADDR_19 -0x4710 US_ALU_RGB_ADDR_20 -0x4714 US_ALU_RGB_ADDR_21 -0x4718 US_ALU_RGB_ADDR_22 -0x471C US_ALU_RGB_ADDR_23 -0x4720 US_ALU_RGB_ADDR_24 -0x4724 US_ALU_RGB_ADDR_25 -0x4728 US_ALU_RGB_ADDR_26 -0x472C US_ALU_RGB_ADDR_27 -0x4730 US_ALU_RGB_ADDR_28 -0x4734 US_ALU_RGB_ADDR_29 -0x4738 US_ALU_RGB_ADDR_30 -0x473C US_ALU_RGB_ADDR_31 -0x4740 US_ALU_RGB_ADDR_32 -0x4744 US_ALU_RGB_ADDR_33 -0x4748 US_ALU_RGB_ADDR_34 -0x474C US_ALU_RGB_ADDR_35 -0x4750 US_ALU_RGB_ADDR_36 -0x4754 US_ALU_RGB_ADDR_37 -0x4758 US_ALU_RGB_ADDR_38 -0x475C US_ALU_RGB_ADDR_39 -0x4760 US_ALU_RGB_ADDR_40 -0x4764 US_ALU_RGB_ADDR_41 -0x4768 US_ALU_RGB_ADDR_42 -0x476C US_ALU_RGB_ADDR_43 -0x4770 US_ALU_RGB_ADDR_44 -0x4774 US_ALU_RGB_ADDR_45 -0x4778 US_ALU_RGB_ADDR_46 -0x477C US_ALU_RGB_ADDR_47 -0x4780 US_ALU_RGB_ADDR_48 -0x4784 US_ALU_RGB_ADDR_49 -0x4788 US_ALU_RGB_ADDR_50 -0x478C US_ALU_RGB_ADDR_51 -0x4790 US_ALU_RGB_ADDR_52 -0x4794 US_ALU_RGB_ADDR_53 -0x4798 US_ALU_RGB_ADDR_54 -0x479C US_ALU_RGB_ADDR_55 -0x47A0 US_ALU_RGB_ADDR_56 -0x47A4 US_ALU_RGB_ADDR_57 -0x47A8 US_ALU_RGB_ADDR_58 -0x47AC US_ALU_RGB_ADDR_59 -0x47B0 US_ALU_RGB_ADDR_60 -0x47B4 US_ALU_RGB_ADDR_61 -0x47B8 US_ALU_RGB_ADDR_62 -0x47BC US_ALU_RGB_ADDR_63 -0x47C0 US_ALU_ALPHA_ADDR_0 -0x47C4 US_ALU_ALPHA_ADDR_1 -0x47C8 US_ALU_ALPHA_ADDR_2 -0x47CC US_ALU_ALPHA_ADDR_3 -0x47D0 US_ALU_ALPHA_ADDR_4 -0x47D4 US_ALU_ALPHA_ADDR_5 -0x47D8 US_ALU_ALPHA_ADDR_6 -0x47DC US_ALU_ALPHA_ADDR_7 -0x47E0 US_ALU_ALPHA_ADDR_8 -0x47E4 US_ALU_ALPHA_ADDR_9 -0x47E8 US_ALU_ALPHA_ADDR_10 -0x47EC US_ALU_ALPHA_ADDR_11 -0x47F0 US_ALU_ALPHA_ADDR_12 -0x47F4 US_ALU_ALPHA_ADDR_13 -0x47F8 US_ALU_ALPHA_ADDR_14 -0x47FC US_ALU_ALPHA_ADDR_15 -0x4800 US_ALU_ALPHA_ADDR_16 -0x4804 US_ALU_ALPHA_ADDR_17 -0x4808 US_ALU_ALPHA_ADDR_18 -0x480C US_ALU_ALPHA_ADDR_19 -0x4810 US_ALU_ALPHA_ADDR_20 -0x4814 US_ALU_ALPHA_ADDR_21 -0x4818 US_ALU_ALPHA_ADDR_22 -0x481C US_ALU_ALPHA_ADDR_23 -0x4820 US_ALU_ALPHA_ADDR_24 -0x4824 US_ALU_ALPHA_ADDR_25 -0x4828 US_ALU_ALPHA_ADDR_26 -0x482C US_ALU_ALPHA_ADDR_27 -0x4830 US_ALU_ALPHA_ADDR_28 -0x4834 US_ALU_ALPHA_ADDR_29 -0x4838 US_ALU_ALPHA_ADDR_30 -0x483C US_ALU_ALPHA_ADDR_31 -0x4840 US_ALU_ALPHA_ADDR_32 -0x4844 US_ALU_ALPHA_ADDR_33 -0x4848 US_ALU_ALPHA_ADDR_34 -0x484C US_ALU_ALPHA_ADDR_35 -0x4850 US_ALU_ALPHA_ADDR_36 -0x4854 US_ALU_ALPHA_ADDR_37 -0x4858 US_ALU_ALPHA_ADDR_38 -0x485C US_ALU_ALPHA_ADDR_39 -0x4860 US_ALU_ALPHA_ADDR_40 -0x4864 US_ALU_ALPHA_ADDR_41 -0x4868 US_ALU_ALPHA_ADDR_42 -0x486C US_ALU_ALPHA_ADDR_43 -0x4870 US_ALU_ALPHA_ADDR_44 -0x4874 US_ALU_ALPHA_ADDR_45 -0x4878 US_ALU_ALPHA_ADDR_46 -0x487C US_ALU_ALPHA_ADDR_47 -0x4880 US_ALU_ALPHA_ADDR_48 -0x4884 US_ALU_ALPHA_ADDR_49 -0x4888 US_ALU_ALPHA_ADDR_50 -0x488C US_ALU_ALPHA_ADDR_51 -0x4890 US_ALU_ALPHA_ADDR_52 -0x4894 US_ALU_ALPHA_ADDR_53 -0x4898 US_ALU_ALPHA_ADDR_54 -0x489C US_ALU_ALPHA_ADDR_55 -0x48A0 US_ALU_ALPHA_ADDR_56 -0x48A4 US_ALU_ALPHA_ADDR_57 -0x48A8 US_ALU_ALPHA_ADDR_58 -0x48AC US_ALU_ALPHA_ADDR_59 -0x48B0 US_ALU_ALPHA_ADDR_60 -0x48B4 US_ALU_ALPHA_ADDR_61 -0x48B8 US_ALU_ALPHA_ADDR_62 -0x48BC US_ALU_ALPHA_ADDR_63 -0x48C0 US_ALU_RGB_INST_0 -0x48C4 US_ALU_RGB_INST_1 -0x48C8 US_ALU_RGB_INST_2 -0x48CC US_ALU_RGB_INST_3 -0x48D0 US_ALU_RGB_INST_4 -0x48D4 US_ALU_RGB_INST_5 -0x48D8 US_ALU_RGB_INST_6 -0x48DC US_ALU_RGB_INST_7 -0x48E0 US_ALU_RGB_INST_8 -0x48E4 US_ALU_RGB_INST_9 -0x48E8 US_ALU_RGB_INST_10 -0x48EC US_ALU_RGB_INST_11 -0x48F0 US_ALU_RGB_INST_12 -0x48F4 US_ALU_RGB_INST_13 -0x48F8 US_ALU_RGB_INST_14 -0x48FC US_ALU_RGB_INST_15 -0x4900 US_ALU_RGB_INST_16 -0x4904 US_ALU_RGB_INST_17 -0x4908 US_ALU_RGB_INST_18 -0x490C US_ALU_RGB_INST_19 -0x4910 US_ALU_RGB_INST_20 -0x4914 US_ALU_RGB_INST_21 -0x4918 US_ALU_RGB_INST_22 -0x491C US_ALU_RGB_INST_23 -0x4920 US_ALU_RGB_INST_24 -0x4924 US_ALU_RGB_INST_25 -0x4928 US_ALU_RGB_INST_26 -0x492C US_ALU_RGB_INST_27 -0x4930 US_ALU_RGB_INST_28 -0x4934 US_ALU_RGB_INST_29 -0x4938 US_ALU_RGB_INST_30 -0x493C US_ALU_RGB_INST_31 -0x4940 US_ALU_RGB_INST_32 -0x4944 US_ALU_RGB_INST_33 -0x4948 US_ALU_RGB_INST_34 -0x494C US_ALU_RGB_INST_35 -0x4950 US_ALU_RGB_INST_36 -0x4954 US_ALU_RGB_INST_37 -0x4958 US_ALU_RGB_INST_38 -0x495C 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US_ALU_CONST_A_5 -0x4C60 US_ALU_CONST_R_6 -0x4C64 US_ALU_CONST_G_6 -0x4C68 US_ALU_CONST_B_6 -0x4C6C US_ALU_CONST_A_6 -0x4C70 US_ALU_CONST_R_7 -0x4C74 US_ALU_CONST_G_7 -0x4C78 US_ALU_CONST_B_7 -0x4C7C US_ALU_CONST_A_7 -0x4C80 US_ALU_CONST_R_8 -0x4C84 US_ALU_CONST_G_8 -0x4C88 US_ALU_CONST_B_8 -0x4C8C US_ALU_CONST_A_8 -0x4C90 US_ALU_CONST_R_9 -0x4C94 US_ALU_CONST_G_9 -0x4C98 US_ALU_CONST_B_9 -0x4C9C US_ALU_CONST_A_9 -0x4CA0 US_ALU_CONST_R_10 -0x4CA4 US_ALU_CONST_G_10 -0x4CA8 US_ALU_CONST_B_10 -0x4CAC US_ALU_CONST_A_10 -0x4CB0 US_ALU_CONST_R_11 -0x4CB4 US_ALU_CONST_G_11 -0x4CB8 US_ALU_CONST_B_11 -0x4CBC US_ALU_CONST_A_11 -0x4CC0 US_ALU_CONST_R_12 -0x4CC4 US_ALU_CONST_G_12 -0x4CC8 US_ALU_CONST_B_12 -0x4CCC US_ALU_CONST_A_12 -0x4CD0 US_ALU_CONST_R_13 -0x4CD4 US_ALU_CONST_G_13 -0x4CD8 US_ALU_CONST_B_13 -0x4CDC US_ALU_CONST_A_13 -0x4CE0 US_ALU_CONST_R_14 -0x4CE4 US_ALU_CONST_G_14 -0x4CE8 US_ALU_CONST_B_14 -0x4CEC US_ALU_CONST_A_14 -0x4CF0 US_ALU_CONST_R_15 -0x4CF4 US_ALU_CONST_G_15 -0x4CF8 US_ALU_CONST_B_15 -0x4CFC US_ALU_CONST_A_15 -0x4D00 US_ALU_CONST_R_16 -0x4D04 US_ALU_CONST_G_16 -0x4D08 US_ALU_CONST_B_16 -0x4D0C US_ALU_CONST_A_16 -0x4D10 US_ALU_CONST_R_17 -0x4D14 US_ALU_CONST_G_17 -0x4D18 US_ALU_CONST_B_17 -0x4D1C US_ALU_CONST_A_17 -0x4D20 US_ALU_CONST_R_18 -0x4D24 US_ALU_CONST_G_18 -0x4D28 US_ALU_CONST_B_18 -0x4D2C US_ALU_CONST_A_18 -0x4D30 US_ALU_CONST_R_19 -0x4D34 US_ALU_CONST_G_19 -0x4D38 US_ALU_CONST_B_19 -0x4D3C US_ALU_CONST_A_19 -0x4D40 US_ALU_CONST_R_20 -0x4D44 US_ALU_CONST_G_20 -0x4D48 US_ALU_CONST_B_20 -0x4D4C US_ALU_CONST_A_20 -0x4D50 US_ALU_CONST_R_21 -0x4D54 US_ALU_CONST_G_21 -0x4D58 US_ALU_CONST_B_21 -0x4D5C US_ALU_CONST_A_21 -0x4D60 US_ALU_CONST_R_22 -0x4D64 US_ALU_CONST_G_22 -0x4D68 US_ALU_CONST_B_22 -0x4D6C US_ALU_CONST_A_22 -0x4D70 US_ALU_CONST_R_23 -0x4D74 US_ALU_CONST_G_23 -0x4D78 US_ALU_CONST_B_23 -0x4D7C US_ALU_CONST_A_23 -0x4D80 US_ALU_CONST_R_24 -0x4D84 US_ALU_CONST_G_24 -0x4D88 US_ALU_CONST_B_24 -0x4D8C US_ALU_CONST_A_24 -0x4D90 US_ALU_CONST_R_25 -0x4D94 US_ALU_CONST_G_25 -0x4D98 US_ALU_CONST_B_25 -0x4D9C US_ALU_CONST_A_25 -0x4DA0 US_ALU_CONST_R_26 -0x4DA4 US_ALU_CONST_G_26 -0x4DA8 US_ALU_CONST_B_26 -0x4DAC US_ALU_CONST_A_26 -0x4DB0 US_ALU_CONST_R_27 -0x4DB4 US_ALU_CONST_G_27 -0x4DB8 US_ALU_CONST_B_27 -0x4DBC US_ALU_CONST_A_27 -0x4DC0 US_ALU_CONST_R_28 -0x4DC4 US_ALU_CONST_G_28 -0x4DC8 US_ALU_CONST_B_28 -0x4DCC US_ALU_CONST_A_28 -0x4DD0 US_ALU_CONST_R_29 -0x4DD4 US_ALU_CONST_G_29 -0x4DD8 US_ALU_CONST_B_29 -0x4DDC US_ALU_CONST_A_29 -0x4DE0 US_ALU_CONST_R_30 -0x4DE4 US_ALU_CONST_G_30 -0x4DE8 US_ALU_CONST_B_30 -0x4DEC US_ALU_CONST_A_30 -0x4DF0 US_ALU_CONST_R_31 -0x4DF4 US_ALU_CONST_G_31 -0x4DF8 US_ALU_CONST_B_31 -0x4DFC US_ALU_CONST_A_31 -0x4E04 RB3D_BLENDCNTL_R3 -0x4E08 RB3D_ABLENDCNTL_R3 -0x4E0C RB3D_COLOR_CHANNEL_MASK -0x4E10 RB3D_CONSTANT_COLOR -0x4E14 RB3D_COLOR_CLEAR_VALUE -0x4E18 RB3D_ROPCNTL_R3 -0x4E1C RB3D_CLRCMP_FLIPE_R3 -0x4E20 RB3D_CLRCMP_CLR_R3 -0x4E24 RB3D_CLRCMP_MSK_R3 -0x4E48 RB3D_DEBUG_CTL -0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 -0x4E50 RB3D_DITHER_CTL -0x4E54 RB3D_CMASK_OFFSET0 -0x4E58 RB3D_CMASK_OFFSET1 -0x4E5C RB3D_CMASK_OFFSET2 -0x4E60 RB3D_CMASK_OFFSET3 -0x4E64 RB3D_CMASK_PITCH0 -0x4E68 RB3D_CMASK_PITCH1 -0x4E6C RB3D_CMASK_PITCH2 -0x4E70 RB3D_CMASK_PITCH3 -0x4E74 RB3D_CMASK_WRINDEX -0x4E78 RB3D_CMASK_DWORD -0x4E7C RB3D_CMASK_RDINDEX -0x4E80 RB3D_AARESOLVE_OFFSET -0x4E84 RB3D_AARESOLVE_PITCH -0x4E88 RB3D_AARESOLVE_CTL -0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD -0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD -0x4F04 ZB_ZSTENCILCNTL -0x4F08 ZB_STENCILREFMASK -0x4F14 ZB_ZTOP -0x4F18 ZB_ZCACHE_CTLSTAT -0x4F1C ZB_BW_CNTL -0x4F28 ZB_DEPTHCLEARVALUE -0x4F30 ZB_ZMASK_OFFSET -0x4F34 ZB_ZMASK_PITCH -0x4F38 ZB_ZMASK_WRINDEX -0x4F3C ZB_ZMASK_DWORD -0x4F40 ZB_ZMASK_RDINDEX -0x4F44 ZB_HIZ_OFFSET -0x4F48 ZB_HIZ_WRINDEX -0x4F4C ZB_HIZ_DWORD -0x4F50 ZB_HIZ_RDINDEX -0x4F54 ZB_HIZ_PITCH -0x4F58 ZB_ZPASS_DATA diff --git a/trunk/drivers/gpu/drm/radeon/reg_srcs/rs600 b/trunk/drivers/gpu/drm/radeon/reg_srcs/rs600 index 6801b865d1c4..8e3c0b807add 100644 --- a/trunk/drivers/gpu/drm/radeon/reg_srcs/rs600 +++ b/trunk/drivers/gpu/drm/radeon/reg_srcs/rs600 @@ -153,7 +153,7 @@ rs600 0x6d40 0x42A4 SU_POLY_OFFSET_FRONT_SCALE 0x42A8 SU_POLY_OFFSET_FRONT_OFFSET 0x42AC SU_POLY_OFFSET_BACK_SCALE -0x42B0 SU_POLY_OFFSET_BACK_OFFSET +0x42B0 SU_POLY_OFFSET_BACK_OFFSET 0x42B4 SU_POLY_OFFSET_ENABLE 0x42B8 SU_CULL_MODE 0x42C0 SU_DEPTH_SCALE @@ -291,8 +291,6 @@ rs600 0x6d40 0x46AC US_OUT_FMT_2 0x46B0 US_OUT_FMT_3 0x46B4 US_W_FMT -0x46B8 US_CODE_BANK -0x46BC US_CODE_EXT 0x46C0 US_ALU_RGB_ADDR_0 0x46C4 US_ALU_RGB_ADDR_1 0x46C8 US_ALU_RGB_ADDR_2 @@ -549,70 +547,6 @@ rs600 0x6d40 0x4AB4 US_ALU_ALPHA_INST_61 0x4AB8 US_ALU_ALPHA_INST_62 0x4ABC US_ALU_ALPHA_INST_63 -0x4AC0 US_ALU_EXT_ADDR_0 -0x4AC4 US_ALU_EXT_ADDR_1 -0x4AC8 US_ALU_EXT_ADDR_2 -0x4ACC US_ALU_EXT_ADDR_3 -0x4AD0 US_ALU_EXT_ADDR_4 -0x4AD4 US_ALU_EXT_ADDR_5 -0x4AD8 US_ALU_EXT_ADDR_6 -0x4ADC US_ALU_EXT_ADDR_7 -0x4AE0 US_ALU_EXT_ADDR_8 -0x4AE4 US_ALU_EXT_ADDR_9 -0x4AE8 US_ALU_EXT_ADDR_10 -0x4AEC US_ALU_EXT_ADDR_11 -0x4AF0 US_ALU_EXT_ADDR_12 -0x4AF4 US_ALU_EXT_ADDR_13 -0x4AF8 US_ALU_EXT_ADDR_14 -0x4AFC US_ALU_EXT_ADDR_15 -0x4B00 US_ALU_EXT_ADDR_16 -0x4B04 US_ALU_EXT_ADDR_17 -0x4B08 US_ALU_EXT_ADDR_18 -0x4B0C US_ALU_EXT_ADDR_19 -0x4B10 US_ALU_EXT_ADDR_20 -0x4B14 US_ALU_EXT_ADDR_21 -0x4B18 US_ALU_EXT_ADDR_22 -0x4B1C US_ALU_EXT_ADDR_23 -0x4B20 US_ALU_EXT_ADDR_24 -0x4B24 US_ALU_EXT_ADDR_25 -0x4B28 US_ALU_EXT_ADDR_26 -0x4B2C US_ALU_EXT_ADDR_27 -0x4B30 US_ALU_EXT_ADDR_28 -0x4B34 US_ALU_EXT_ADDR_29 -0x4B38 US_ALU_EXT_ADDR_30 -0x4B3C US_ALU_EXT_ADDR_31 -0x4B40 US_ALU_EXT_ADDR_32 -0x4B44 US_ALU_EXT_ADDR_33 -0x4B48 US_ALU_EXT_ADDR_34 -0x4B4C US_ALU_EXT_ADDR_35 -0x4B50 US_ALU_EXT_ADDR_36 -0x4B54 US_ALU_EXT_ADDR_37 -0x4B58 US_ALU_EXT_ADDR_38 -0x4B5C US_ALU_EXT_ADDR_39 -0x4B60 US_ALU_EXT_ADDR_40 -0x4B64 US_ALU_EXT_ADDR_41 -0x4B68 US_ALU_EXT_ADDR_42 -0x4B6C US_ALU_EXT_ADDR_43 -0x4B70 US_ALU_EXT_ADDR_44 -0x4B74 US_ALU_EXT_ADDR_45 -0x4B78 US_ALU_EXT_ADDR_46 -0x4B7C US_ALU_EXT_ADDR_47 -0x4B80 US_ALU_EXT_ADDR_48 -0x4B84 US_ALU_EXT_ADDR_49 -0x4B88 US_ALU_EXT_ADDR_50 -0x4B8C US_ALU_EXT_ADDR_51 -0x4B90 US_ALU_EXT_ADDR_52 -0x4B94 US_ALU_EXT_ADDR_53 -0x4B98 US_ALU_EXT_ADDR_54 -0x4B9C US_ALU_EXT_ADDR_55 -0x4BA0 US_ALU_EXT_ADDR_56 -0x4BA4 US_ALU_EXT_ADDR_57 -0x4BA8 US_ALU_EXT_ADDR_58 -0x4BAC US_ALU_EXT_ADDR_59 -0x4BB0 US_ALU_EXT_ADDR_60 -0x4BB4 US_ALU_EXT_ADDR_61 -0x4BB8 US_ALU_EXT_ADDR_62 -0x4BBC US_ALU_EXT_ADDR_63 0x4BC0 FG_FOG_BLEND 0x4BC4 FG_FOG_FACTOR 0x4BC8 FG_FOG_COLOR_R diff --git a/trunk/drivers/gpu/drm/radeon/reg_srcs/rv515 b/trunk/drivers/gpu/drm/radeon/reg_srcs/rv515 index 38abf63bf2cd..0102a0d5735c 100644 --- a/trunk/drivers/gpu/drm/radeon/reg_srcs/rv515 +++ b/trunk/drivers/gpu/drm/radeon/reg_srcs/rv515 @@ -161,12 +161,7 @@ rv515 0x6d40 0x401C GB_SELECT 0x4020 GB_AA_CONFIG 0x4024 GB_FIFO_SIZE -0x4028 GB_Z_PEQ_CONFIG 0x4100 TX_INVALTAGS -0x4114 SU_TEX_WRAP_PS3 -0x4118 PS3_ENABLE -0x411c PS3_VTX_FMT -0x4120 PS3_TEX_SOURCE 0x4200 GA_POINT_S0 0x4204 GA_POINT_T0 0x4208 GA_POINT_S1 @@ -176,7 +171,6 @@ rv515 0x6d40 0x4230 GA_POINT_MINMAX 0x4234 GA_LINE_CNTL 0x4238 GA_LINE_STIPPLE_CONFIG -0x4258 GA_COLOR_CONTROL_PS3 0x4260 GA_LINE_STIPPLE_VALUE 0x4264 GA_LINE_S0 0x4268 GA_LINE_S1 diff --git a/trunk/drivers/gpu/drm/radeon/rv770.c b/trunk/drivers/gpu/drm/radeon/rv770.c index eb065bbe1eeb..16f7317fa1af 100644 --- a/trunk/drivers/gpu/drm/radeon/rv770.c +++ b/trunk/drivers/gpu/drm/radeon/rv770.c @@ -779,6 +779,7 @@ int rv770_mc_init(struct radeon_device *rdev) fixed20_12 a; u32 tmp; int chansize, numchan; + int r; /* Get VRAM informations */ rdev->mc.vram_is_ddr = true; @@ -821,6 +822,9 @@ int rv770_mc_init(struct radeon_device *rdev) rdev->mc.real_vram_size = rdev->mc.aper_size; if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) + return r; /* gtt_size is setup by radeon_agp_init */ rdev->mc.gtt_location = rdev->mc.agp_base; tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; @@ -971,12 +975,10 @@ int rv770_suspend(struct radeon_device *rdev) r600_wb_disable(rdev); rv770_pcie_gart_disable(rdev); /* unpin shaders bo */ - if (rdev->r600_blit.shader_obj) { - r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); - if (likely(r == 0)) { - radeon_bo_unpin(rdev->r600_blit.shader_obj); - radeon_bo_unreserve(rdev->r600_blit.shader_obj); - } + r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); + if (likely(r == 0)) { + radeon_bo_unpin(rdev->r600_blit.shader_obj); + radeon_bo_unreserve(rdev->r600_blit.shader_obj); } return 0; } @@ -1035,11 +1037,6 @@ int rv770_init(struct radeon_device *rdev) r = radeon_fence_driver_init(rdev); if (r) return r; - if (rdev->flags & RADEON_IS_AGP) { - r = radeon_agp_init(rdev); - if (r) - radeon_agp_disable(rdev); - } r = rv770_mc_init(rdev); if (r) return r; diff --git a/trunk/drivers/gpu/drm/ttm/ttm_bo.c b/trunk/drivers/gpu/drm/ttm/ttm_bo.c index 8036b6e189ee..2920f9a279e1 100644 --- a/trunk/drivers/gpu/drm/ttm/ttm_bo.c +++ b/trunk/drivers/gpu/drm/ttm/ttm_bo.c @@ -426,8 +426,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, bdev->man[bo->mem.mem_type].gpu_offset; bo->cur_placement = bo->mem.placement; spin_unlock(&bo->lock); - } else - bo->offset = 0; + } return 0; @@ -524,44 +523,52 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) { struct ttm_bo_global *glob = bdev->glob; - struct ttm_buffer_object *entry = NULL; - int ret = 0; + struct ttm_buffer_object *entry, *nentry; + struct list_head *list, *next; + int ret; spin_lock(&glob->lru_lock); - if (list_empty(&bdev->ddestroy)) - goto out_unlock; + list_for_each_safe(list, next, &bdev->ddestroy) { + entry = list_entry(list, struct ttm_buffer_object, ddestroy); + nentry = NULL; - entry = list_first_entry(&bdev->ddestroy, - struct ttm_buffer_object, ddestroy); - kref_get(&entry->list_kref); - - for (;;) { - struct ttm_buffer_object *nentry = NULL; + /* + * Protect the next list entry from destruction while we + * unlock the lru_lock. + */ - if (entry->ddestroy.next != &bdev->ddestroy) { - nentry = list_first_entry(&entry->ddestroy, - struct ttm_buffer_object, ddestroy); + if (next != &bdev->ddestroy) { + nentry = list_entry(next, struct ttm_buffer_object, + ddestroy); kref_get(&nentry->list_kref); } + kref_get(&entry->list_kref); spin_unlock(&glob->lru_lock); ret = ttm_bo_cleanup_refs(entry, remove_all); kref_put(&entry->list_kref, ttm_bo_release_list); - entry = nentry; - - if (ret || !entry) - goto out; spin_lock(&glob->lru_lock); - if (list_empty(&entry->ddestroy)) + if (nentry) { + bool next_onlist = !list_empty(next); + spin_unlock(&glob->lru_lock); + kref_put(&nentry->list_kref, ttm_bo_release_list); + spin_lock(&glob->lru_lock); + /* + * Someone might have raced us and removed the + * next entry from the list. We don't bother restarting + * list traversal. + */ + + if (!next_onlist) + break; + } + if (ret) break; } - -out_unlock: + ret = !list_empty(&bdev->ddestroy); spin_unlock(&glob->lru_lock); -out: - if (entry) - kref_put(&entry->list_kref, ttm_bo_release_list); + return ret; } @@ -1837,9 +1844,6 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) * anyone tries to access a ttm page. */ - if (bo->bdev->driver->swap_notify) - bo->bdev->driver->swap_notify(bo); - ret = ttm_tt_swapout(bo->ttm, bo->persistant_swap_storage); out: @@ -1860,4 +1864,3 @@ void ttm_bo_swapout_all(struct ttm_bo_device *bdev) while (ttm_bo_swapout(&bdev->glob->shrink) == 0) ; } -EXPORT_SYMBOL(ttm_bo_swapout_all); diff --git a/trunk/drivers/gpu/drm/ttm/ttm_lock.c b/trunk/drivers/gpu/drm/ttm/ttm_lock.c index 3d172ef04ee1..f619ebcaa4ec 100644 --- a/trunk/drivers/gpu/drm/ttm/ttm_lock.c +++ b/trunk/drivers/gpu/drm/ttm/ttm_lock.c @@ -288,7 +288,6 @@ void ttm_suspend_unlock(struct ttm_lock *lock) wake_up_all(&lock->queue); spin_unlock(&lock->lock); } -EXPORT_SYMBOL(ttm_suspend_unlock); static bool __ttm_suspend_lock(struct ttm_lock *lock) { @@ -310,4 +309,3 @@ void ttm_suspend_lock(struct ttm_lock *lock) { wait_event(lock->queue, __ttm_suspend_lock(lock)); } -EXPORT_SYMBOL(ttm_suspend_lock); diff --git a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c index 37a81925b158..d6f2d2b882e9 100644 --- a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c +++ b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c @@ -172,18 +172,6 @@ static int vmw_verify_access(struct ttm_buffer_object *bo, struct file *filp) return 0; } -static void vmw_move_notify(struct ttm_buffer_object *bo, - struct ttm_mem_reg *new_mem) -{ - if (new_mem->mem_type != TTM_PL_SYSTEM) - vmw_dmabuf_gmr_unbind(bo); -} - -static void vmw_swap_notify(struct ttm_buffer_object *bo) -{ - vmw_dmabuf_gmr_unbind(bo); -} - /** * FIXME: We're using the old vmware polling method to sync. * Do this with fences instead. @@ -237,7 +225,5 @@ struct ttm_bo_driver vmw_bo_driver = { .sync_obj_wait = vmw_sync_obj_wait, .sync_obj_flush = vmw_sync_obj_flush, .sync_obj_unref = vmw_sync_obj_unref, - .sync_obj_ref = vmw_sync_obj_ref, - .move_notify = vmw_move_notify, - .swap_notify = vmw_swap_notify + .sync_obj_ref = vmw_sync_obj_ref }; diff --git a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c index dedd121d8fe7..1db1ef30be2b 100644 --- a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +++ b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c @@ -147,8 +147,6 @@ static char *vmw_devname = "vmwgfx"; static int vmw_probe(struct pci_dev *, const struct pci_device_id *); static void vmw_master_init(struct vmw_master *); -static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, - void *ptr); static void vmw_print_capabilities(uint32_t capabilities) { @@ -219,7 +217,6 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) dev_priv->dev = dev; dev_priv->vmw_chipset = chipset; - dev_priv->last_read_sequence = (uint32_t) -100; mutex_init(&dev_priv->hw_mutex); mutex_init(&dev_priv->cmdbuf_mutex); rwlock_init(&dev_priv->resource_lock); @@ -354,9 +351,6 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) vmw_fb_init(dev_priv); } - dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; - register_pm_notifier(&dev_priv->pm_nb); - return 0; out_no_device: @@ -391,8 +385,6 @@ static int vmw_driver_unload(struct drm_device *dev) DRM_INFO(VMWGFX_DRIVER_NAME " unload.\n"); - unregister_pm_notifier(&dev_priv->pm_nb); - if (!dev_priv->stealth) { vmw_fb_close(dev_priv); vmw_kms_close(dev_priv); @@ -658,57 +650,6 @@ static void vmw_remove(struct pci_dev *pdev) drm_put_dev(dev); } -static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, - void *ptr) -{ - struct vmw_private *dev_priv = - container_of(nb, struct vmw_private, pm_nb); - struct vmw_master *vmaster = dev_priv->active_master; - - switch (val) { - case PM_HIBERNATION_PREPARE: - case PM_SUSPEND_PREPARE: - ttm_suspend_lock(&vmaster->lock); - - /** - * This empties VRAM and unbinds all GMR bindings. - * Buffer contents is moved to swappable memory. - */ - ttm_bo_swapout_all(&dev_priv->bdev); - break; - case PM_POST_HIBERNATION: - case PM_POST_SUSPEND: - ttm_suspend_unlock(&vmaster->lock); - break; - case PM_RESTORE_PREPARE: - break; - case PM_POST_RESTORE: - break; - default: - break; - } - return 0; -} - -/** - * These might not be needed with the virtual SVGA device. - */ - -int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) -{ - pci_save_state(pdev); - pci_disable_device(pdev); - pci_set_power_state(pdev, PCI_D3hot); - return 0; -} - -int vmw_pci_resume(struct pci_dev *pdev) -{ - pci_set_power_state(pdev, PCI_D0); - pci_restore_state(pdev); - return pci_enable_device(pdev); -} - static struct drm_driver driver = { .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_MODESET, @@ -748,9 +689,7 @@ static struct drm_driver driver = { .name = VMWGFX_DRIVER_NAME, .id_table = vmw_pci_id_list, .probe = vmw_probe, - .remove = vmw_remove, - .suspend = vmw_pci_suspend, - .resume = vmw_pci_resume + .remove = vmw_remove }, .name = VMWGFX_DRIVER_NAME, .desc = VMWGFX_DRIVER_DESC, diff --git a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h index 7532b9b47eec..e61bd85b6975 100644 --- a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +++ b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h @@ -32,7 +32,6 @@ #include "drmP.h" #include "vmwgfx_drm.h" #include "drm_hashtab.h" -#include "linux/suspend.h" #include "ttm/ttm_bo_driver.h" #include "ttm/ttm_object.h" #include "ttm/ttm_lock.h" @@ -259,7 +258,6 @@ struct vmw_private { struct vmw_master *active_master; struct vmw_master fbdev_master; - struct notifier_block pm_nb; }; static inline struct vmw_private *vmw_priv(struct drm_device *dev) @@ -355,7 +353,6 @@ extern int vmw_dmabuf_to_start_of_vram(struct vmw_private *vmw_priv, struct vmw_dma_buffer *bo); extern int vmw_dmabuf_from_vram(struct vmw_private *vmw_priv, struct vmw_dma_buffer *bo); -extern void vmw_dmabuf_gmr_unbind(struct ttm_buffer_object *bo); extern int vmw_stream_claim_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int vmw_stream_unref_ioctl(struct drm_device *dev, void *data, diff --git a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c index 4f4f6432be8b..641dde76ada1 100644 --- a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c +++ b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c @@ -649,6 +649,14 @@ int vmw_dmabuf_to_start_of_vram(struct vmw_private *vmw_priv, if (unlikely(ret != 0)) goto err_unlock; + if (vmw_bo->gmr_bound) { + vmw_gmr_unbind(vmw_priv, vmw_bo->gmr_id); + spin_lock(&bo->glob->lru_lock); + ida_remove(&vmw_priv->gmr_ida, vmw_bo->gmr_id); + spin_unlock(&bo->glob->lru_lock); + vmw_bo->gmr_bound = NULL; + } + ret = ttm_bo_validate(bo, &ne_placement, false, false); ttm_bo_unreserve(bo); err_unlock: diff --git a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c index f7d5f70b52dd..01feb48af333 100644 --- a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c +++ b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c @@ -98,7 +98,8 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) (unsigned int) min, (unsigned int) fifo->capabilities); - dev_priv->fence_seq = dev_priv->last_read_sequence; + dev_priv->fence_seq = (uint32_t) -100; + dev_priv->last_read_sequence = (uint32_t) -100; iowrite32(dev_priv->last_read_sequence, fifo_mem + SVGA_FIFO_FENCE); return vmw_fifo_send_fence(dev_priv, &dummy); diff --git a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 686692de209a..b1af76e371c3 100644 --- a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -553,7 +553,9 @@ int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer, } *cmd; int i, increment = 1; - if (!num_clips) { + if (!num_clips || + !(dev_priv->fifo.capabilities & + SVGA_FIFO_CAP_SCREEN_OBJECT)) { num_clips = 1; clips = &norect; norect.x1 = norect.y1 = 0; @@ -572,10 +574,10 @@ int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer, for (i = 0; i < num_clips; i++, clips += increment) { cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE); - cmd[i].body.x = cpu_to_le32(clips->x1); - cmd[i].body.y = cpu_to_le32(clips->y1); - cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1); - cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1); + cmd[i].body.x = cpu_to_le32(clips[i].x1); + cmd[i].body.y = cpu_to_le32(clips[i].y1); + cmd[i].body.width = cpu_to_le32(clips[i].x2 - clips[i].x1); + cmd[i].body.height = cpu_to_le32(clips[i].y2 - clips[i].y1); } vmw_fifo_commit(dev_priv, sizeof(*cmd) * num_clips); diff --git a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c index 5b6eabeb7f51..bb6e6a096d25 100644 --- a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c +++ b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c @@ -104,6 +104,7 @@ static int vmw_dmabuf_pin_in_vram(struct vmw_private *dev_priv, bool pin, bool interruptible) { struct ttm_buffer_object *bo = &buf->base; + struct ttm_bo_global *glob = bo->glob; struct ttm_placement *overlay_placement = &vmw_vram_placement; int ret; @@ -115,6 +116,14 @@ static int vmw_dmabuf_pin_in_vram(struct vmw_private *dev_priv, if (unlikely(ret != 0)) goto err; + if (buf->gmr_bound) { + vmw_gmr_unbind(dev_priv, buf->gmr_id); + spin_lock(&glob->lru_lock); + ida_remove(&dev_priv->gmr_ida, buf->gmr_id); + spin_unlock(&glob->lru_lock); + buf->gmr_bound = NULL; + } + if (pin) overlay_placement = &vmw_vram_ne_placement; diff --git a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c index e0878077e8aa..c012d5927f65 100644 --- a/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c +++ b/trunk/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c @@ -599,27 +599,6 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data, if (unlikely(ret != 0)) goto out_err1; - - if (srf->flags & (1 << 9) && - srf->num_sizes == 1 && - srf->sizes[0].width == 64 && - srf->sizes[0].height == 64 && - srf->format == SVGA3D_A8R8G8B8) { - - srf->snooper.image = kmalloc(64 * 64 * 4, GFP_KERNEL); - /* clear the image */ - if (srf->snooper.image) { - memset(srf->snooper.image, 0x00, 64 * 64 * 4); - } else { - DRM_ERROR("Failed to allocate cursor_image\n"); - ret = -ENOMEM; - goto out_err1; - } - } else { - srf->snooper.image = NULL; - } - srf->snooper.crtc = NULL; - user_srf->base.shareable = false; user_srf->base.tfile = NULL; @@ -643,6 +622,24 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data, return ret; } + if (srf->flags & (1 << 9) && + srf->num_sizes == 1 && + srf->sizes[0].width == 64 && + srf->sizes[0].height == 64 && + srf->format == SVGA3D_A8R8G8B8) { + + srf->snooper.image = kmalloc(64 * 64 * 4, GFP_KERNEL); + /* clear the image */ + if (srf->snooper.image) + memset(srf->snooper.image, 0x00, 64 * 64 * 4); + else + DRM_ERROR("Failed to allocate cursor_image\n"); + + } else { + srf->snooper.image = NULL; + } + srf->snooper.crtc = NULL; + rep->sid = user_srf->base.hash.key; if (rep->sid == SVGA3D_INVALID_ID) DRM_ERROR("Created bad Surface ID.\n"); @@ -757,29 +754,20 @@ static size_t vmw_dmabuf_acc_size(struct ttm_bo_global *glob, return bo_user_size + page_array_size; } -void vmw_dmabuf_gmr_unbind(struct ttm_buffer_object *bo) +void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo) { struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo); struct ttm_bo_global *glob = bo->glob; struct vmw_private *dev_priv = container_of(bo->bdev, struct vmw_private, bdev); + ttm_mem_global_free(glob->mem_glob, bo->acc_size); if (vmw_bo->gmr_bound) { vmw_gmr_unbind(dev_priv, vmw_bo->gmr_id); spin_lock(&glob->lru_lock); ida_remove(&dev_priv->gmr_ida, vmw_bo->gmr_id); spin_unlock(&glob->lru_lock); - vmw_bo->gmr_bound = false; } -} - -void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo) -{ - struct vmw_dma_buffer *vmw_bo = vmw_dma_buffer(bo); - struct ttm_bo_global *glob = bo->glob; - - vmw_dmabuf_gmr_unbind(bo); - ttm_mem_global_free(glob->mem_glob, bo->acc_size); kfree(vmw_bo); } @@ -825,10 +813,18 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv, static void vmw_user_dmabuf_destroy(struct ttm_buffer_object *bo) { struct vmw_user_dma_buffer *vmw_user_bo = vmw_user_dma_buffer(bo); + struct vmw_dma_buffer *vmw_bo = &vmw_user_bo->dma; struct ttm_bo_global *glob = bo->glob; + struct vmw_private *dev_priv = + container_of(bo->bdev, struct vmw_private, bdev); - vmw_dmabuf_gmr_unbind(bo); ttm_mem_global_free(glob->mem_glob, bo->acc_size); + if (vmw_bo->gmr_bound) { + vmw_gmr_unbind(dev_priv, vmw_bo->gmr_id); + spin_lock(&glob->lru_lock); + ida_remove(&dev_priv->gmr_ida, vmw_bo->gmr_id); + spin_unlock(&glob->lru_lock); + } kfree(vmw_user_bo); } diff --git a/trunk/include/drm/ttm/ttm_bo_driver.h b/trunk/include/drm/ttm/ttm_bo_driver.h index 4c4e0f8375b3..ff7664e0c3cd 100644 --- a/trunk/include/drm/ttm/ttm_bo_driver.h +++ b/trunk/include/drm/ttm/ttm_bo_driver.h @@ -353,11 +353,6 @@ struct ttm_bo_driver { /* notify the driver we are taking a fault on this BO * and have reserved it */ void (*fault_reserve_notify)(struct ttm_buffer_object *bo); - - /** - * notify the driver that we're about to swap out this bo - */ - void (*swap_notify) (struct ttm_buffer_object *bo); }; /**