From 2080c9177da5c1c17c714f85ac0f79c617eacc92 Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Tue, 29 May 2007 20:01:55 +0100 Subject: [PATCH] --- yaml --- r: 57584 b: refs/heads/master c: cf7578995398e20d3ab0748e6d5f83ea6c7a0035 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mips/mips-boards/generic/time.c | 16 ++-------------- 2 files changed, 3 insertions(+), 15 deletions(-) diff --git a/[refs] b/[refs] index 4677756eea3e..b078c984c93f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6a05888d713dd915d3268000a479e38646aa423f +refs/heads/master: cf7578995398e20d3ab0748e6d5f83ea6c7a0035 diff --git a/trunk/arch/mips/mips-boards/generic/time.c b/trunk/arch/mips/mips-boards/generic/time.c index 37735bfc3afd..b41db9e7ab1f 100644 --- a/trunk/arch/mips/mips-boards/generic/time.c +++ b/trunk/arch/mips/mips-boards/generic/time.c @@ -88,8 +88,6 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) * the general MIPS timer_interrupt routine. */ - int vpflags; - /* * We could be here due to timer interrupt, * perf counter overflow, or both. @@ -98,15 +96,6 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) perf_irq(); if (read_c0_cause() & (1 << 30)) { - /* If timer interrupt, make it de-assert */ - write_c0_compare (read_c0_count() - 1); - /* - * DVPE is necessary so long as cross-VPE interrupts - * are done via read-modify-write of Cause register. - */ - vpflags = dvpe(); - clear_c0_cause(CPUCTR_IMASKBIT); - evpe(vpflags); /* * There are things we only want to do once per tick * in an "MP" system. One TC of each VPE will take @@ -115,14 +104,13 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) * the tick on VPE 0 to run the full timer_interrupt(). */ if (cpu_data[cpu].vpe_id == 0) { - timer_interrupt(irq, NULL); - smtc_timer_broadcast(cpu_data[cpu].vpe_id); + timer_interrupt(irq, NULL); } else { write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); local_timer_interrupt(irq, dev_id); - smtc_timer_broadcast(cpu_data[cpu].vpe_id); } + smtc_timer_broadcast(cpu_data[cpu].vpe_id); } #else /* CONFIG_MIPS_MT_SMTC */ int r2 = cpu_has_mips_r2;