From 2135a89fd3d9e1517cc8f5dcd5adcfb363ab2973 Mon Sep 17 00:00:00 2001 From: Andy Green Date: Mon, 30 May 2011 07:43:06 -0700 Subject: [PATCH] --- yaml --- r: 272423 b: refs/heads/master c: d177e5ddb83a4bc518270e705e60ccc5a5aa6410 h: refs/heads/master i: 272421: 5d353edecb41184202a5d046c022b196a84d0aef 272419: 2c4b0126776799c23ff53982b0aaafbf98dda391 272415: 4be67889d0e86f8e333d45566b4dd24477baa4dd v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-omap/i2c.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 8c9588db4f1c..78a7ec66255a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 67b90c67205149173dc0cfdc46039be92fa390b6 +refs/heads/master: d177e5ddb83a4bc518270e705e60ccc5a5aa6410 diff --git a/trunk/arch/arm/plat-omap/i2c.c b/trunk/arch/arm/plat-omap/i2c.c index a938df0908a2..0d3eda77e7ce 100644 --- a/trunk/arch/arm/plat-omap/i2c.c +++ b/trunk/arch/arm/plat-omap/i2c.c @@ -154,6 +154,12 @@ static inline int omap2_i2c_add_bus(int bus_id) } pdata = &i2c_pdata[bus_id - 1]; + /* + * pass the hwmod class's CPU-specific knowledge of I2C IP revision in + * use up to the OMAP I2C driver via platform data + */ + pdata->rev = oh->class->rev; + /* * When waiting for completion of a i2c transfer, we need to * set a wake up latency constraint for the MPU. This is to