From 22024e09efe446abb91f41c51fffab0eb8dc3926 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 26 May 2011 18:05:15 -0400 Subject: [PATCH] --- yaml --- r: 252745 b: refs/heads/master c: fcb243918f9e8414bf5ad6fb0361447ac3d3fddb h: refs/heads/master i: 252743: ee83f283c8faadc753841b32d7e0e3fed777551c v: v3 --- [refs] | 2 +- .../blackfin/mach-bf518/include/mach/defBF514.h | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 14358da3eb0c..4b639528fda0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 61aa818f7bfdb5dd0aef4687513566c75c0e4c21 +refs/heads/master: fcb243918f9e8414bf5ad6fb0361447ac3d3fddb diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h b/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h index 98a51c479290..cfab428e577c 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h @@ -36,13 +36,13 @@ #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ -#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ -#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ -#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ -#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ -#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ -#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ -#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ -#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ +#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ +#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ +#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ +#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ +#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */ +#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */ +#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */ +#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */ #endif /* _DEF_BF514_H */