diff --git a/[refs] b/[refs] index cea18783a87e..6bf52384c32a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 0c6d4b4e22a513f8563a2e00c5ab08e9f8796272 +refs/heads/master: 5d5a8d2d9d6cca979efe4fe1552d787fdc542603 diff --git a/trunk/Documentation/ABI/testing/sysfs-bus-pci-devices-cciss b/trunk/Documentation/ABI/testing/sysfs-bus-pci-devices-cciss index f5bb0a3bb8c0..53d99edd1d75 100644 --- a/trunk/Documentation/ABI/testing/sysfs-bus-pci-devices-cciss +++ b/trunk/Documentation/ABI/testing/sysfs-bus-pci-devices-cciss @@ -71,3 +71,10 @@ Description: Value of 1 indicates the controller can honor the reset_devices a dump device, as kdump requires resetting the device in order to work reliably. +Where: /sys/bus/pci/devices//ccissX/transport_mode +Date: July 2011 +Kernel Version: 3.0 +Contact: iss_storagedev@hp.com +Description: Value of "simple" indicates that the controller has been placed + in "simple mode". Value of "performant" indicates that the + controller has been placed in "performant mode". diff --git a/trunk/Documentation/CodingStyle b/trunk/Documentation/CodingStyle index c940239d9678..2b90d328b3ba 100644 --- a/trunk/Documentation/CodingStyle +++ b/trunk/Documentation/CodingStyle @@ -166,8 +166,8 @@ if (condition) else do_that(); -This does not apply if one branch of a conditional statement is a single -statement. Use braces in both branches. +This does not apply if only one branch of a conditional statement is a single +statement; in the latter case use braces in both branches: if (condition) { do_this(); diff --git a/trunk/Documentation/DocBook/media/v4l/compat.xml b/trunk/Documentation/DocBook/media/v4l/compat.xml index 91410b6e7e08..b68698f96e7f 100644 --- a/trunk/Documentation/DocBook/media/v4l/compat.xml +++ b/trunk/Documentation/DocBook/media/v4l/compat.xml @@ -2486,6 +2486,9 @@ ioctls. Flash API. + + &VIDIOC-CREATE-BUFS; and &VIDIOC-PREPARE-BUF; ioctls. + diff --git a/trunk/Documentation/DocBook/media/v4l/controls.xml b/trunk/Documentation/DocBook/media/v4l/controls.xml index 23fdf79f8cf3..3bc5ee8b2c74 100644 --- a/trunk/Documentation/DocBook/media/v4l/controls.xml +++ b/trunk/Documentation/DocBook/media/v4l/controls.xml @@ -232,8 +232,9 @@ control is deprecated. New drivers and applications should use the Enables a power line frequency filter to avoid flicker. Possible values for enum v4l2_power_line_frequency are: V4L2_CID_POWER_LINE_FREQUENCY_DISABLED (0), -V4L2_CID_POWER_LINE_FREQUENCY_50HZ (1) and -V4L2_CID_POWER_LINE_FREQUENCY_60HZ (2). +V4L2_CID_POWER_LINE_FREQUENCY_50HZ (1), +V4L2_CID_POWER_LINE_FREQUENCY_60HZ (2) and +V4L2_CID_POWER_LINE_FREQUENCY_AUTO (3). V4L2_CID_HUE_AUTO diff --git a/trunk/Documentation/DocBook/media/v4l/io.xml b/trunk/Documentation/DocBook/media/v4l/io.xml index c57d1ec6291c..3f47df1aa54a 100644 --- a/trunk/Documentation/DocBook/media/v4l/io.xml +++ b/trunk/Documentation/DocBook/media/v4l/io.xml @@ -927,6 +927,33 @@ ioctl is called. Applications set or clear this flag before calling the VIDIOC_QBUF ioctl. + + V4L2_BUF_FLAG_PREPARED + 0x0400 + The buffer has been prepared for I/O and can be queued by the +application. Drivers set or clear this flag when the +VIDIOC_QUERYBUF, VIDIOC_PREPARE_BUF, VIDIOC_QBUF or VIDIOC_DQBUF ioctl is called. + + + V4L2_BUF_FLAG_NO_CACHE_INVALIDATE + 0x0400 + Caches do not have to be invalidated for this buffer. +Typically applications shall use this flag if the data captured in the buffer +is not going to be touched by the CPU, instead the buffer will, probably, be +passed on to a DMA-capable hardware unit for further processing or output. + + + + V4L2_BUF_FLAG_NO_CACHE_CLEAN + 0x0800 + Caches do not have to be cleaned for this buffer. +Typically applications shall use this flag for output buffers if the data +in this buffer has not been created by the CPU but by some DMA-capable unit, +in which case caches have not been used. + diff --git a/trunk/Documentation/DocBook/media/v4l/v4l2.xml b/trunk/Documentation/DocBook/media/v4l/v4l2.xml index 40132c277647..2ab365c10fb9 100644 --- a/trunk/Documentation/DocBook/media/v4l/v4l2.xml +++ b/trunk/Documentation/DocBook/media/v4l/v4l2.xml @@ -469,6 +469,7 @@ and discussions on the V4L mailing list. &sub-close; &sub-ioctl; + &sub-create-bufs; &sub-cropcap; &sub-dbg-g-chip-ident; &sub-dbg-g-register; @@ -511,6 +512,7 @@ and discussions on the V4L mailing list. &sub-queryctrl; &sub-query-dv-preset; &sub-querystd; + &sub-prepare-buf; &sub-reqbufs; &sub-s-hw-freq-seek; &sub-streamon; diff --git a/trunk/Documentation/DocBook/media/v4l/vidioc-create-bufs.xml b/trunk/Documentation/DocBook/media/v4l/vidioc-create-bufs.xml new file mode 100644 index 000000000000..73ae8a6cd004 --- /dev/null +++ b/trunk/Documentation/DocBook/media/v4l/vidioc-create-bufs.xml @@ -0,0 +1,139 @@ + + + ioctl VIDIOC_CREATE_BUFS + &manvol; + + + + VIDIOC_CREATE_BUFS + Create buffers for Memory Mapped or User Pointer I/O + + + + + + int ioctl + int fd + int request + struct v4l2_create_buffers *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_CREATE_BUFS + + + + argp + + + + + + + + + Description + + This ioctl is used to create buffers for memory +mapped or user pointer +I/O. It can be used as an alternative or in addition to the +VIDIOC_REQBUFS ioctl, when a tighter control over buffers +is required. This ioctl can be called multiple times to create buffers of +different sizes. + + To allocate device buffers applications initialize relevant fields of +the v4l2_create_buffers structure. They set the +type field in the +v4l2_format structure, embedded in this +structure, to the respective stream or buffer type. +count must be set to the number of required buffers. +memory specifies the required I/O method. The +format field shall typically be filled in using +either the VIDIOC_TRY_FMT or +VIDIOC_G_FMT ioctl(). Additionally, applications can adjust +sizeimage fields to fit their specific needs. The +reserved array must be zeroed. + + When the ioctl is called with a pointer to this structure the driver +will attempt to allocate up to the requested number of buffers and store the +actual number allocated and the starting index in the +count and the index fields +respectively. On return count can be smaller than +the number requested. The driver may also increase buffer sizes if required, +however, it will not update sizeimage field values. +The user has to use VIDIOC_QUERYBUF to retrieve that +information. + + + struct <structname>v4l2_create_buffers</structname> + + &cs-str; + + + __u32 + index + The starting buffer index, returned by the driver. + + + __u32 + count + The number of buffers requested or granted. + + + &v4l2-memory; + memory + Applications set this field to +V4L2_MEMORY_MMAP or +V4L2_MEMORY_USERPTR. + + + &v4l2-format; + format + Filled in by the application, preserved by the driver. + + + __u32 + reserved[8] + A place holder for future extensions. + + + +
+ + + + &return-value; + + + + ENOMEM + + No memory to allocate buffers for memory +mapped I/O. + + + + EINVAL + + The buffer type (type field) or the +requested I/O method (memory) is not +supported. + + + + + diff --git a/trunk/Documentation/DocBook/media/v4l/vidioc-prepare-buf.xml b/trunk/Documentation/DocBook/media/v4l/vidioc-prepare-buf.xml new file mode 100644 index 000000000000..7bde698760e4 --- /dev/null +++ b/trunk/Documentation/DocBook/media/v4l/vidioc-prepare-buf.xml @@ -0,0 +1,88 @@ + + + ioctl VIDIOC_PREPARE_BUF + &manvol; + + + + VIDIOC_PREPARE_BUF + Prepare a buffer for I/O + + + + + + int ioctl + int fd + int request + struct v4l2_buffer *argp + + + + + + Arguments + + + + fd + + &fd; + + + + request + + VIDIOC_PREPARE_BUF + + + + argp + + + + + + + + + Description + + Applications can optionally call the +VIDIOC_PREPARE_BUF ioctl to pass ownership of the buffer +to the driver before actually enqueuing it, using the +VIDIOC_QBUF ioctl, and to prepare it for future I/O. +Such preparations may include cache invalidation or cleaning. Performing them +in advance saves time during the actual I/O. In case such cache operations are +not required, the application can use one of +V4L2_BUF_FLAG_NO_CACHE_INVALIDATE and +V4L2_BUF_FLAG_NO_CACHE_CLEAN flags to skip the respective +step. + + The v4l2_buffer structure is +specified in . + + + + &return-value; + + + + EBUSY + + File I/O is in progress. + + + + EINVAL + + The buffer type is not +supported, or the index is out of bounds, +or no buffers have been allocated yet, or the +userptr or +length are invalid. + + + + + diff --git a/trunk/Documentation/block/switching-sched.txt b/trunk/Documentation/block/switching-sched.txt index 71cfbdc0f74d..3b2612e342f1 100644 --- a/trunk/Documentation/block/switching-sched.txt +++ b/trunk/Documentation/block/switching-sched.txt @@ -1,6 +1,6 @@ To choose IO schedulers at boot time, use the argument 'elevator=deadline'. -'noop', 'as' and 'cfq' (the default) are also available. IO schedulers are -assigned globally at boot time only presently. +'noop' and 'cfq' (the default) are also available. IO schedulers are assigned +globally at boot time only presently. Each io queue has a set of io scheduler tunables associated with it. These tunables control how the io scheduler works. You can find these entries diff --git a/trunk/Documentation/blockdev/cciss.txt b/trunk/Documentation/blockdev/cciss.txt index c00c6a5ab21f..71464e09ec18 100644 --- a/trunk/Documentation/blockdev/cciss.txt +++ b/trunk/Documentation/blockdev/cciss.txt @@ -78,6 +78,16 @@ The device naming scheme is: /dev/cciss/c1d1p2 Controller 1, disk 1, partition 2 /dev/cciss/c1d1p3 Controller 1, disk 1, partition 3 +CCISS simple mode support +------------------------- + +The "cciss_simple_mode=1" boot parameter may be used to prevent the driver +from putting the controller into "performant" mode. The difference is that +with simple mode, each command completion requires an interrupt, while with +"performant mode" (the default, and ordinarily better performing) it is +possible to have multiple command completions indicated by a single +interrupt. + SCSI tape drive and medium changer support ------------------------------------------ diff --git a/trunk/Documentation/cgroups/cgroups.txt b/trunk/Documentation/cgroups/cgroups.txt index cd67e90003c0..9c452ef2328c 100644 --- a/trunk/Documentation/cgroups/cgroups.txt +++ b/trunk/Documentation/cgroups/cgroups.txt @@ -454,8 +454,8 @@ mounted hierarchy, to remove a task from its current cgroup you must move it into a new cgroup (possibly the root cgroup) by writing to the new cgroup's tasks file. -Note: If the ns cgroup is active, moving a process to another cgroup can -fail. +Note: Due to some restrictions enforced by some cgroup subsystems, moving +a process to another cgroup can fail. 2.3 Mounting hierarchies by name -------------------------------- diff --git a/trunk/Documentation/devicetree/bindings/ata/calxeda-sata.txt b/trunk/Documentation/devicetree/bindings/ata/calxeda-sata.txt new file mode 100644 index 000000000000..79caa5651f53 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/ata/calxeda-sata.txt @@ -0,0 +1,17 @@ +* Calxeda SATA Controller + +SATA nodes are defined to describe on-chip Serial ATA controllers. +Each SATA controller should have its own node. + +Required properties: +- compatible : compatible list, contains "calxeda,hb-ahci" +- interrupts : +- reg : + +Example: + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x1000>; + interrupts = <115>; + }; + diff --git a/trunk/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/trunk/Documentation/devicetree/bindings/powerpc/fsl/board.txt index 39e941515a36..380914e965e0 100644 --- a/trunk/Documentation/devicetree/bindings/powerpc/fsl/board.txt +++ b/trunk/Documentation/devicetree/bindings/powerpc/fsl/board.txt @@ -1,3 +1,8 @@ +Freescale Reference Board Bindings + +This document describes device tree bindings for various devices that +exist on some Freescale reference boards. + * Board Control and Status (BCSR) Required properties: @@ -12,25 +17,26 @@ Example: reg = ; }; -* Freescale on board FPGA +* Freescale on-board FPGA This is the memory-mapped registers for on board FPGA. Required properities: -- compatible : should be "fsl,fpga-pixis". -- reg : should contain the address and the length of the FPPGA register - set. +- compatible: should be a board-specific string followed by a string + indicating the type of FPGA. Example: + "fsl,-fpga", "fsl,fpga-pixis" +- reg: should contain the address and the length of the FPGA register set. - interrupt-parent: should specify phandle for the interrupt controller. -- interrupts : should specify event (wakeup) IRQ. +- interrupts: should specify event (wakeup) IRQ. -Example (MPC8610HPCD): +Example (P1022DS): - board-control@e8000000 { - compatible = "fsl,fpga-pixis"; - reg = <0xe8000000 32>; - interrupt-parent = <&mpic>; - interrupts = <8 8>; - }; + board-control@3,0 { + compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis"; + reg = <3 0 0x30>; + interrupt-parent = <&mpic>; + interrupts = <8 8 0 0>; + }; * Freescale BCSR GPIO banks diff --git a/trunk/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt b/trunk/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt new file mode 100644 index 000000000000..9d54eb5a295f --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt @@ -0,0 +1,395 @@ +=================================================================== +Debug Control and Status Register (DCSR) Binding +Copyright 2011 Freescale Semiconductor Inc. + +NOTE: The bindings described in this document are preliminary and subject +to change. Some of the compatible strings that contain only generic names +may turn out to be inappropriate, or need additional properties to describe +the integration of the block with the rest of the chip. + +===================================================================== +Debug Control and Status Register Memory Map + +Description + +This node defines the base address and range for the +defined DCSR Memory Map. Child nodes will describe the individual +debug blocks defined within this memory space. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,dcsr" and "simple-bus". + The DCSR space exists in the memory-mapped bus. + + - #address-cells + Usage: required + Value type: + Definition: A standard property. Defines the number of cells + or representing physical addresses in child nodes. + + - #size-cells + Usage: required + Value type: + Definition: A standard property. Defines the number of cells + or representing the size of physical addresses in + child nodes. + + - ranges + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + range of the DCSR space. + +EXAMPLE + dcsr: dcsr@f00000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,dcsr", "simple-bus"; + ranges = <0x00000000 0xf 0x00000000 0x01008000>; + }; + +===================================================================== +Event Processing Unit + +This node represents the region of DCSR space allocated to the EPU + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,dcsr-epu" + + - interrupts + Usage: required + Value type: + Definition: Specifies the interrupts generated by the EPU. + The value of the interrupts property consists of three + interrupt specifiers. The format of the specifier is defined + by the binding document describing the node's interrupt parent. + + The EPU counters can be configured to assert the performance + monitor interrupt signal based on either counter overflow or value + match. Which counter asserted the interrupt is captured in an EPU + Counter Interrupt Status Register (EPCPUISR). + + The EPU unit can also be configured to assert either or both of + two interrupt signals based on debug event sources within the SoC. + The interrupt signals are epu_xt_int0 and epu_xt_int1. + Which event source asserted the interrupt is captured in an EPU + Interrupt Status Register (EPISR0,EPISR1). + + Interrupt numbers are lised in order (perfmon, event0, event1). + + - interrupt-parent + Usage: required + Value type: + Definition: A single value that points + to the interrupt parent to which the child domain + is being mapped. Value must be "&mpic" + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + +EXAMPLE + dcsr-epu@0 { + compatible = "fsl,dcsr-epu"; + interrupts = <52 2 0 0 + 84 2 0 0 + 85 2 0 0>; + interrupt-parent = <&mpic>; + reg = <0x0 0x1000>; + }; + +======================================================================= +Nexus Port Controller + +This node represents the region of DCSR space allocated to the NPC + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,dcsr-npc" + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + The Nexus Port controller occupies two regions in the DCSR space + with distinct functionality. + + The first register range describes the Nexus Port Controller + control and status registers. + + The second register range describes the Nexus Port Controller + internal trace buffer. The NPC trace buffer is a small memory buffer + which stages the nexus trace data for transmission via the Aurora port + or to a DDR based trace buffer. In some configurations the NPC trace + buffer can be the only trace buffer used. + + +EXAMPLE + dcsr-npc { + compatible = "fsl,dcsr-npc"; + reg = <0x1000 0x1000 0x1000000 0x8000>; + }; + +======================================================================= +Nexus Concentrator + +This node represents the region of DCSR space allocated to the NXC + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,dcsr-nxc" + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + +EXAMPLE + dcsr-nxc@2000 { + compatible = "fsl,dcsr-nxc"; + reg = <0x2000 0x1000>; + }; +======================================================================= +CoreNet Debug Controller + +This node represents the region of DCSR space allocated to +the CoreNet Debug controller. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,dcsr-corenet" + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + The CoreNet Debug controller occupies two regions in the DCSR space + with distinct functionality. + + The first register range describes the CoreNet Debug Controller + functionalty to perform transaction and transaction attribute matches. + + The second register range describes the CoreNet Debug Controller + functionalty to trigger event notifications and debug traces. + +EXAMPLE + dcsr-corenet { + compatible = "fsl,dcsr-corenet"; + reg = <0x8000 0x1000 0xB0000 0x1000>; + }; + +======================================================================= +Data Path Debug controller + +This node represents the region of DCSR space allocated to +the DPAA Debug Controller. This controller controls debug configuration +for the QMAN and FMAN blocks. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include both an identifier specific to the SoC + or Debug IP of the form "fsl,-dcsr-dpaa" in addition to the + generic compatible string "fsl,dcsr-dpaa". + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + +EXAMPLE + dcsr-dpaa@9000 { + compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa"; + reg = <0x9000 0x1000>; + }; + +======================================================================= +OCeaN Debug controller + +This node represents the region of DCSR space allocated to +the OCN Debug Controller. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include both an identifier specific to the SoC + or Debug IP of the form "fsl,-dcsr-ocn" in addition to the + generic compatible string "fsl,dcsr-ocn". + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + +EXAMPLE + dcsr-ocn@11000 { + compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn"; + reg = <0x11000 0x1000>; + }; + +======================================================================= +DDR Controller Debug controller + +This node represents the region of DCSR space allocated to +the OCN Debug Controller. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,dcsr-ddr" + + - dev-handle + Usage: required + Definition: A phandle to associate this debug node with its + component controller. + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + +EXAMPLE + dcsr-ddr@12000 { + compatible = "fsl,dcsr-ddr"; + dev-handle = <&ddr1>; + reg = <0x12000 0x1000>; + }; + +======================================================================= +Nexus Aurora Link Controller + +This node represents the region of DCSR space allocated to +the NAL Controller. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include both an identifier specific to the SoC + or Debug IP of the form "fsl,-dcsr-nal" in addition to the + generic compatible string "fsl,dcsr-nal". + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + +EXAMPLE + dcsr-nal@18000 { + compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal"; + reg = <0x18000 0x1000>; + }; + + +======================================================================= +Run Control and Power Management + +This node represents the region of DCSR space allocated to +the RCPM Debug Controller. This functionlity is limited to the +control the debug operations of the SoC and cores. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include both an identifier specific to the SoC + or Debug IP of the form "fsl,-dcsr-rcpm" in addition to the + generic compatible string "fsl,dcsr-rcpm". + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + +EXAMPLE + dcsr-rcpm@22000 { + compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm"; + reg = <0x22000 0x1000>; + }; + +======================================================================= +Core Service Bridge Proxy + +This node represents the region of DCSR space allocated to +the Core Service Bridge Proxies. +There is one Core Service Bridge Proxy device for each CPU in the system. +This functionlity provides access to the debug operations of the CPU. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include both an identifier specific to the cpu + of the form "fsl,dcsr--sb-proxy" in addition to the + generic compatible string "fsl,dcsr-cpu-sb-proxy". + + - cpu-handle + Usage: required + Definition: A phandle to associate this debug node with its cpu. + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical address + offset and length of the DCSR space registers of the device + configuration block. + +EXAMPLE + dcsr-cpu-sb-proxy@40000 { + compatible = "fsl,dcsr-e500mc-sb-proxy", + "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu0>; + reg = <0x40000 0x1000>; + }; + dcsr-cpu-sb-proxy@41000 { + compatible = "fsl,dcsr-e500mc-sb-proxy", + "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu1>; + reg = <0x41000 0x1000>; + }; + +======================================================================= diff --git a/trunk/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/trunk/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt index 70558c3f3682..5d586e1ccaf5 100644 --- a/trunk/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt +++ b/trunk/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt @@ -25,6 +25,16 @@ Required properties: are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed to MPIC. +Optional properties: +- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register + is used for MSI messaging. The address of MSIIR in PCI address space is + the MSI message address. + + This property may be used in virtualized environments where the hypervisor + has created an alternate mapping for the MSIR block. See below for an + explanation. + + Example: msi@41600 { compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; @@ -41,3 +51,35 @@ Example: 0xe7 0>; interrupt-parent = <&mpic>; }; + +The Freescale hypervisor and msi-address-64 +------------------------------------------- +Normally, PCI devices have access to all of CCSR via an ATMU mapping. The +Freescale MSI driver calculates the address of MSIIR (in the MSI register +block) and sets that address as the MSI message address. + +In a virtualized environment, the hypervisor may need to create an IOMMU +mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement +because of hardware limitations of the Peripheral Access Management Unit +(PAMU), which is currently the only IOMMU that the hypervisor supports. +The ATMU is programmed with the guest physical address, and the PAMU +intercepts transactions and reroutes them to the true physical address. + +In the PAMU, each PCI controller is given only one primary window. The +PAMU restricts DMA operations so that they can only occur within a window. +Because PCI devices must be able to DMA to memory, the primary window must +be used to cover all of the guest's memory space. + +PAMU primary windows can be divided into 256 subwindows, and each +subwindow can have its own address mapping ("guest physical" to "true +physical"). However, each subwindow has to have the same alignment, which +means they cannot be located at just any address. Because of these +restrictions, it is usually impossible to create a 4KB subwindow that +covers MSIIR where it's normally located. + +Therefore, the hypervisor has to create a subwindow inside the same +primary window used for memory, but mapped to the MSIR block (where MSIIR +lives). The first subwindow after the end of guest memory is used for +this. The address specified in the msi-address-64 property is the PCI +address of MSIIR. The hypervisor configures the PAMU to map that address to +the true physical address of MSIIR. diff --git a/trunk/Documentation/filesystems/hfs.txt b/trunk/Documentation/filesystems/hfs.txt index bd0fa7704035..d096df6db07a 100644 --- a/trunk/Documentation/filesystems/hfs.txt +++ b/trunk/Documentation/filesystems/hfs.txt @@ -1,3 +1,4 @@ +Note: This filesystem doesn't have a maintainer. Macintosh HFS Filesystem for Linux ================================== @@ -76,8 +77,6 @@ hformat that can be used to create HFS filesystem. See Credits ======= -The HFS drivers was written by Paul H. Hargrovea (hargrove@sccm.Stanford.EDU) -and is now maintained by Roman Zippel (roman@ardistech.com) at Ardis -Technologies. -Roman rewrote large parts of the code and brought in btree routines derived -from Brad Boyer's hfsplus driver (also maintained by Roman now). +The HFS drivers was written by Paul H. Hargrovea (hargrove@sccm.Stanford.EDU). +Roman Zippel (roman@ardistech.com) rewrote large parts of the code and brought +in btree routines derived from Brad Boyer's hfsplus driver. diff --git a/trunk/Documentation/filesystems/inotify.txt b/trunk/Documentation/filesystems/inotify.txt index 59a919f16144..cfd02712b83e 100644 --- a/trunk/Documentation/filesystems/inotify.txt +++ b/trunk/Documentation/filesystems/inotify.txt @@ -194,7 +194,8 @@ associated with the inotify_handle, and on which events are queued. Each watch is associated with an inotify_watch structure. Watches are chained off of each associated inotify_handle and each associated inode. -See fs/inotify.c and fs/inotify_user.c for the locking and lifetime rules. +See fs/notify/inotify/inotify_fsnotify.c and fs/notify/inotify/inotify_user.c +for the locking and lifetime rules. (vi) Rationale diff --git a/trunk/Documentation/hwmon/w83627ehf b/trunk/Documentation/hwmon/w83627ehf index 76ffef94ed75..3f44dbdfda70 100644 --- a/trunk/Documentation/hwmon/w83627ehf +++ b/trunk/Documentation/hwmon/w83627ehf @@ -14,6 +14,10 @@ Supported chips: Prefix: 'w83627dhg' Addresses scanned: ISA address retrieved from Super I/O registers Datasheet: not available + * Winbond W83627UHG + Prefix: 'w83627uhg' + Addresses scanned: ISA address retrieved from Super I/O registers + Datasheet: available from www.nuvoton.com * Winbond W83667HG Prefix: 'w83667hg' Addresses scanned: ISA address retrieved from Super I/O registers @@ -42,14 +46,13 @@ Description ----------- This driver implements support for the Winbond W83627EHF, W83627EHG, -W83627DHG, W83627DHG-P, W83667HG, W83667HG-B, W83667HG-I (NCT6775F), -and NCT6776F super I/O chips. We will refer to them collectively as -Winbond chips. - -The chips implement three temperature sensors (up to four for 667HG-B, and nine -for NCT6775F and NCT6776F), five fan rotation speed sensors, ten analog voltage -sensors (only nine for the 627DHG), one VID (6 pins for the 627EHF/EHG, 8 pins -for the 627DHG and 667HG), alarms with beep warnings (control unimplemented), +W83627DHG, W83627DHG-P, W83627UHG, W83667HG, W83667HG-B, W83667HG-I +(NCT6775F), and NCT6776F super I/O chips. We will refer to them collectively +as Winbond chips. + +The chips implement 2 to 4 temperature sensors (9 for NCT6775F and NCT6776F), +2 to 5 fan rotation speed sensors, 8 to 10 analog voltage sensors, one VID +(except for 627UHG), alarms with beep warnings (control unimplemented), and some automatic fan regulation strategies (plus manual fan control mode). The temperature sensor sources on W82677HG-B, NCT6775F, and NCT6776F are @@ -86,17 +89,16 @@ follows: temp1 -> pwm1 temp2 -> pwm2 -temp3 -> pwm3 +temp3 -> pwm3 (not on 627UHG) prog -> pwm4 (not on 667HG and 667HG-B; the programmable setting is not supported by the driver) /sys files ---------- -name - this is a standard hwmon device entry. For the W83627EHF and W83627EHG, - it is set to "w83627ehf", for the W83627DHG it is set to "w83627dhg", - for the W83667HG and W83667HG-B it is set to "w83667hg", for NCT6775F it - is set to "nct6775", and for NCT6776F it is set to "nct6776". +name - this is a standard hwmon device entry, it contains the name of + the device (see the prefix in the list of supported devices at + the top of this file) pwm[1-4] - this file stores PWM duty cycle or DC value (fan speed) in range: 0 (stop) to 255 (full) diff --git a/trunk/Documentation/laptops/thinkpad-acpi.txt b/trunk/Documentation/laptops/thinkpad-acpi.txt index 3ff0dad62d36..9d666828915a 100644 --- a/trunk/Documentation/laptops/thinkpad-acpi.txt +++ b/trunk/Documentation/laptops/thinkpad-acpi.txt @@ -411,9 +411,9 @@ event code Key Notes 0x1004 0x03 FN+F4 Sleep button (ACPI sleep button semantics, i.e. sleep-to-RAM). - It is always generate some kind + It always generates some kind of event, either the hot key - event or a ACPI sleep button + event or an ACPI sleep button event. The firmware may refuse to generate further FN+F4 key presses until a S3 or S4 ACPI diff --git a/trunk/Documentation/leds/leds-class.txt b/trunk/Documentation/leds/leds-class.txt index 4996586e27e8..79699c200766 100644 --- a/trunk/Documentation/leds/leds-class.txt +++ b/trunk/Documentation/leds/leds-class.txt @@ -61,8 +61,8 @@ Hardware accelerated blink of LEDs Some LEDs can be programmed to blink without any CPU interaction. To support this feature, a LED driver can optionally implement the blink_set() function (see ). To set an LED to blinking, -however, it is better to use use the API function led_blink_set(), -as it will check and implement software fallback if necessary. +however, it is better to use the API function led_blink_set(), as it +will check and implement software fallback if necessary. To turn off blinking again, use the API function led_brightness_set() as that will not just set the LED brightness but also stop any software diff --git a/trunk/Documentation/networking/ipvs-sysctl.txt b/trunk/Documentation/networking/ipvs-sysctl.txt index 4ccdbca03811..f2a2488f1bf3 100644 --- a/trunk/Documentation/networking/ipvs-sysctl.txt +++ b/trunk/Documentation/networking/ipvs-sysctl.txt @@ -15,6 +15,23 @@ amemthresh - INTEGER enabled and the variable is automatically set to 2, otherwise the strategy is disabled and the variable is set to 1. +conntrack - BOOLEAN + 0 - disabled (default) + not 0 - enabled + + If set, maintain connection tracking entries for + connections handled by IPVS. + + This should be enabled if connections handled by IPVS are to be + also handled by stateful firewall rules. That is, iptables rules + that make use of connection tracking. It is a performance + optimisation to disable this setting otherwise. + + Connections handled by the IPVS FTP application module + will have connection tracking entries regardless of this setting. + + Only available when IPVS is compiled with CONFIG_IP_VS_NFCT enabled. + cache_bypass - BOOLEAN 0 - disabled (default) not 0 - enabled @@ -39,7 +56,7 @@ debug_level - INTEGER 11 - IPVS packet handling (ip_vs_in/ip_vs_out) 12 or more - packet traversal - Only available when IPVS is compiled with the CONFIG_IPVS_DEBUG + Only available when IPVS is compiled with CONFIG_IP_VS_DEBUG enabled. Higher debugging levels include the messages for lower debugging levels, so setting debug level 2, includes level 0, 1 and 2 @@ -123,13 +140,11 @@ nat_icmp_send - BOOLEAN secure_tcp - INTEGER 0 - disabled (default) - The secure_tcp defense is to use a more complicated state - transition table and some possible short timeouts of each - state. In the VS/NAT, it delays the entering the ESTABLISHED - until the real server starts to send data and ACK packet - (after 3-way handshake). + The secure_tcp defense is to use a more complicated TCP state + transition table. For VS/NAT, it also delays entering the + TCP ESTABLISHED state until the three way handshake is completed. - The value definition is the same as that of drop_entry or + The value definition is the same as that of drop_entry and drop_packet. sync_threshold - INTEGER @@ -141,3 +156,36 @@ sync_threshold - INTEGER synchronized, every time the number of its incoming packets modulus 50 equals the threshold. The range of the threshold is from 0 to 49. + +snat_reroute - BOOLEAN + 0 - disabled + not 0 - enabled (default) + + If enabled, recalculate the route of SNATed packets from + realservers so that they are routed as if they originate from the + director. Otherwise they are routed as if they are forwarded by the + director. + + If policy routing is in effect then it is possible that the route + of a packet originating from a director is routed differently to a + packet being forwarded by the director. + + If policy routing is not in effect then the recalculated route will + always be the same as the original route so it is an optimisation + to disable snat_reroute and avoid the recalculation. + +sync_version - INTEGER + default 1 + + The version of the synchronisation protocol used when sending + synchronisation messages. + + 0 selects the original synchronisation protocol (version 0). This + should be used when sending synchronisation messages to a legacy + system that only understands the original synchronisation protocol. + + 1 selects the current synchronisation protocol (version 1). This + should be used where possible. + + Kernels with this sync_version entry are able to receive messages + of both version 1 and version 2 of the synchronisation protocol. diff --git a/trunk/Documentation/oops-tracing.txt b/trunk/Documentation/oops-tracing.txt index 6fe9001b9263..13032c0140d4 100644 --- a/trunk/Documentation/oops-tracing.txt +++ b/trunk/Documentation/oops-tracing.txt @@ -263,6 +263,8 @@ characters, each representing a particular tainted value. 12: 'I' if the kernel is working around a severe bug in the platform firmware (BIOS or similar). + 13: 'O' if an externally-built ("out-of-tree") module has been loaded. + The primary reason for the 'Tainted: ' string is to tell kernel debuggers if this is a clean kernel or if anything unusual has occurred. Tainting is permanent: even if an offending module is diff --git a/trunk/Documentation/power/freezing-of-tasks.txt b/trunk/Documentation/power/freezing-of-tasks.txt index 38b57248fd61..316c2ba187f4 100644 --- a/trunk/Documentation/power/freezing-of-tasks.txt +++ b/trunk/Documentation/power/freezing-of-tasks.txt @@ -22,12 +22,12 @@ try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and either wakes them up, if they are kernel threads, or sends fake signals to them, if they are user space processes. A task that has TIF_FREEZE set, should react to it by calling the function called refrigerator() (defined in -kernel/power/process.c), which sets the task's PF_FROZEN flag, changes its state +kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it. Then, we say that the task is 'frozen' and therefore the set of functions handling this mechanism is referred to as 'the freezer' (these functions are -defined in kernel/power/process.c and include/linux/freezer.h). User space -processes are generally frozen before kernel threads. +defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h). +User space processes are generally frozen before kernel threads. It is not recommended to call refrigerator() directly. Instead, it is recommended to use the try_to_freeze() function (defined in @@ -95,7 +95,7 @@ after the memory for the image has been freed, we don't want tasks to allocate additional memory and we prevent them from doing that by freezing them earlier. [Of course, this also means that device drivers should not allocate substantial amounts of memory from their .suspend() callbacks before hibernation, but this -is e separate issue.] +is a separate issue.] 3. The third reason is to prevent user space processes and some kernel threads from interfering with the suspending and resuming of devices. A user space diff --git a/trunk/Documentation/power/runtime_pm.txt b/trunk/Documentation/power/runtime_pm.txt index 0e856088db7c..5336149f831b 100644 --- a/trunk/Documentation/power/runtime_pm.txt +++ b/trunk/Documentation/power/runtime_pm.txt @@ -789,6 +789,16 @@ will behave normally, not taking the autosuspend delay into account. Similarly, if the power.use_autosuspend field isn't set then the autosuspend helper functions will behave just like the non-autosuspend counterparts. +Under some circumstances a driver or subsystem may want to prevent a device +from autosuspending immediately, even though the usage counter is zero and the +autosuspend delay time has expired. If the ->runtime_suspend() callback +returns -EAGAIN or -EBUSY, and if the next autosuspend delay expiration time is +in the future (as it normally would be if the callback invoked +pm_runtime_mark_last_busy()), the PM core will automatically reschedule the +autosuspend. The ->runtime_suspend() callback can't do this rescheduling +itself because no suspend requests of any kind are accepted while the device is +suspending (i.e., while the callback is running). + The implementation is well suited for asynchronous use in interrupt contexts. However such use inevitably involves races, because the PM core can't synchronize ->runtime_suspend() callbacks with the arrival of I/O requests. diff --git a/trunk/Documentation/serial/computone.txt b/trunk/Documentation/serial/computone.txt index 60a6f657c37d..39ddcdbeeb85 100644 --- a/trunk/Documentation/serial/computone.txt +++ b/trunk/Documentation/serial/computone.txt @@ -20,8 +20,6 @@ Version: 1.2.14 Date: 11/01/2001 Historical Author: Andrew Manison Primary Author: Doug McNash -Support: support@computone.com -Fixes and Updates: Mike Warfield This file assumes that you are using the Computone drivers which are integrated into the kernel sources. For updating the drivers or installing diff --git a/trunk/Documentation/watchdog/convert_drivers_to_kernel_api.txt b/trunk/Documentation/watchdog/convert_drivers_to_kernel_api.txt new file mode 100644 index 000000000000..ae1e90036d06 --- /dev/null +++ b/trunk/Documentation/watchdog/convert_drivers_to_kernel_api.txt @@ -0,0 +1,195 @@ +Converting old watchdog drivers to the watchdog framework +by Wolfram Sang +========================================================= + +Before the watchdog framework came into the kernel, every driver had to +implement the API on its own. Now, as the framework factored out the common +components, those drivers can be lightened making it a user of the framework. +This document shall guide you for this task. The necessary steps are described +as well as things to look out for. + + +Remove the file_operations struct +--------------------------------- + +Old drivers define their own file_operations for actions like open(), write(), +etc... These are now handled by the framework and just call the driver when +needed. So, in general, the 'file_operations' struct and assorted functions can +go. Only very few driver-specific details have to be moved to other functions. +Here is a overview of the functions and probably needed actions: + +- open: Everything dealing with resource management (file-open checks, magic + close preparations) can simply go. Device specific stuff needs to go to the + driver specific start-function. Note that for some drivers, the start-function + also serves as the ping-function. If that is the case and you need start/stop + to be balanced (clocks!), you are better off refactoring a separate start-function. + +- close: Same hints as for open apply. + +- write: Can simply go, all defined behaviour is taken care of by the framework, + i.e. ping on write and magic char ('V') handling. + +- ioctl: While the driver is allowed to have extensions to the IOCTL interface, + the most common ones are handled by the framework, supported by some assistance + from the driver: + + WDIOC_GETSUPPORT: + Returns the mandatory watchdog_info struct from the driver + + WDIOC_GETSTATUS: + Needs the status-callback defined, otherwise returns 0 + + WDIOC_GETBOOTSTATUS: + Needs the bootstatus member properly set. Make sure it is 0 if you + don't have further support! + + WDIOC_SETOPTIONS: + No preparations needed + + WDIOC_KEEPALIVE: + If wanted, options in watchdog_info need to have WDIOF_KEEPALIVEPING + set + + WDIOC_SETTIMEOUT: + Options in watchdog_info need to have WDIOF_SETTIMEOUT set + and a set_timeout-callback has to be defined. The core will also + do limit-checking, if min_timeout and max_timeout in the watchdog + device are set. All is optional. + + WDIOC_GETTIMEOUT: + No preparations needed + + Other IOCTLs can be served using the ioctl-callback. Note that this is mainly + intended for porting old drivers; new drivers should not invent private IOCTLs. + Private IOCTLs are processed first. When the callback returns with + -ENOIOCTLCMD, the IOCTLs of the framework will be tried, too. Any other error + is directly given to the user. + +Example conversion: + +-static const struct file_operations s3c2410wdt_fops = { +- .owner = THIS_MODULE, +- .llseek = no_llseek, +- .write = s3c2410wdt_write, +- .unlocked_ioctl = s3c2410wdt_ioctl, +- .open = s3c2410wdt_open, +- .release = s3c2410wdt_release, +-}; + +Check the functions for device-specific stuff and keep it for later +refactoring. The rest can go. + + +Remove the miscdevice +--------------------- + +Since the file_operations are gone now, you can also remove the 'struct +miscdevice'. The framework will create it on watchdog_dev_register() called by +watchdog_register_device(). + +-static struct miscdevice s3c2410wdt_miscdev = { +- .minor = WATCHDOG_MINOR, +- .name = "watchdog", +- .fops = &s3c2410wdt_fops, +-}; + + +Remove obsolete includes and defines +------------------------------------ + +Because of the simplifications, a few defines are probably unused now. Remove +them. Includes can be removed, too. For example: + +- #include +- #include (if MODULE_ALIAS_MISCDEV is not used) +- #include (if no custom IOCTLs are used) + + +Add the watchdog operations +--------------------------- + +All possible callbacks are defined in 'struct watchdog_ops'. You can find it +explained in 'watchdog-kernel-api.txt' in this directory. start(), stop() and +owner must be set, the rest are optional. You will easily find corresponding +functions in the old driver. Note that you will now get a pointer to the +watchdog_device as a parameter to these functions, so you probably have to +change the function header. Other changes are most likely not needed, because +here simply happens the direct hardware access. If you have device-specific +code left from the above steps, it should be refactored into these callbacks. + +Here is a simple example: + ++static struct watchdog_ops s3c2410wdt_ops = { ++ .owner = THIS_MODULE, ++ .start = s3c2410wdt_start, ++ .stop = s3c2410wdt_stop, ++ .ping = s3c2410wdt_keepalive, ++ .set_timeout = s3c2410wdt_set_heartbeat, ++}; + +A typical function-header change looks like: + +-static void s3c2410wdt_keepalive(void) ++static int s3c2410wdt_keepalive(struct watchdog_device *wdd) + { +... ++ ++ return 0; + } + +... + +- s3c2410wdt_keepalive(); ++ s3c2410wdt_keepalive(&s3c2410_wdd); + + +Add the watchdog device +----------------------- + +Now we need to create a 'struct watchdog_device' and populate it with the +necessary information for the framework. The struct is also explained in detail +in 'watchdog-kernel-api.txt' in this directory. We pass it the mandatory +watchdog_info struct and the newly created watchdog_ops. Often, old drivers +have their own record-keeping for things like bootstatus and timeout using +static variables. Those have to be converted to use the members in +watchdog_device. Note that the timeout values are unsigned int. Some drivers +use signed int, so this has to be converted, too. + +Here is a simple example for a watchdog device: + ++static struct watchdog_device s3c2410_wdd = { ++ .info = &s3c2410_wdt_ident, ++ .ops = &s3c2410wdt_ops, ++}; + + +Register the watchdog device +---------------------------- + +Replace misc_register(&miscdev) with watchdog_register_device(&watchdog_dev). +Make sure the return value gets checked and the error message, if present, +still fits. Also convert the unregister case. + +- ret = misc_register(&s3c2410wdt_miscdev); ++ ret = watchdog_register_device(&s3c2410_wdd); + +... + +- misc_deregister(&s3c2410wdt_miscdev); ++ watchdog_unregister_device(&s3c2410_wdd); + + +Update the Kconfig-entry +------------------------ + +The entry for the driver now needs to select WATCHDOG_CORE: + ++ select WATCHDOG_CORE + + +Create a patch and send it to upstream +-------------------------------------- + +Make sure you understood Documentation/SubmittingPatches and send your patch to +linux-watchdog@vger.kernel.org. We are looking forward to it :) + diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index ab7767001286..6388a96dc1c4 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -1716,6 +1716,7 @@ F: include/linux/can.h F: include/linux/can/core.h F: include/linux/can/bcm.h F: include/linux/can/raw.h +F: include/linux/can/gw.h CAN NETWORK DRIVERS M: Wolfgang Grandegger @@ -2386,7 +2387,7 @@ F: include/linux/netfilter_bridge/ebt_*.h F: net/bridge/netfilter/ebt*.c ECRYPT FILE SYSTEM -M: Tyler Hicks +M: Tyler Hicks M: Dustin Kirkland L: ecryptfs@vger.kernel.org W: https://launchpad.net/ecryptfs @@ -4476,11 +4477,9 @@ F: Documentation/networking/vxge.txt F: drivers/net/ethernet/neterion/ NETFILTER/IPTABLES/IPCHAINS -P: Rusty Russell -P: Marc Boucher -P: James Morris P: Harald Welte P: Jozsef Kadlecsik +M: Pablo Neira Ayuso M: Patrick McHardy L: netfilter-devel@vger.kernel.org L: netfilter@vger.kernel.org diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index fe6b0526b3a6..44789eff983f 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -595,6 +595,7 @@ config ARCH_MMP select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ + select GENERIC_ALLOCATOR help Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. @@ -769,6 +770,7 @@ config ARCH_S3C64XX select CPU_V6 select ARM_VIC select HAVE_CLK + select HAVE_TCM select CLKDEV_LOOKUP select NO_IOPORT select ARCH_USES_GETTIMEOFFSET @@ -777,9 +779,6 @@ config ARCH_S3C64XX select SAMSUNG_CLKSRC select SAMSUNG_IRQ_VIC_TIMER select S3C_GPIO_TRACK - select S3C_GPIO_PULL_UPDOWN - select S3C_GPIO_CFG_S3C24XX - select S3C_GPIO_CFG_S3C64XX select S3C_DEV_NAND select USB_ARCH_HAS_OHCI select SAMSUNG_GPIOLIB_4BIT @@ -838,8 +837,8 @@ config ARCH_S5PV210 help Samsung S5PV210/S5PC110 series based systems -config ARCH_EXYNOS4 - bool "Samsung EXYNOS4" +config ARCH_EXYNOS + bool "SAMSUNG EXYNOS" select CPU_V7 select ARCH_SPARSEMEM_ENABLE select ARCH_HAS_HOLES_MEMORYMODEL @@ -853,7 +852,7 @@ config ARCH_EXYNOS4 select HAVE_S3C2410_WATCHDOG if WATCHDOG select NEED_MACH_MEMORY_H help - Samsung EXYNOS4 series based systems + Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) config ARCH_SHARK bool "Shark" @@ -1080,7 +1079,7 @@ source "arch/arm/mach-s5pc100/Kconfig" source "arch/arm/mach-s5pv210/Kconfig" -source "arch/arm/mach-exynos4/Kconfig" +source "arch/arm/mach-exynos/Kconfig" source "arch/arm/mach-shmobile/Kconfig" @@ -2212,7 +2211,7 @@ menu "Power management options" source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE - depends on !ARCH_S5P64X0 && !ARCH_S5PC100 + depends on !ARCH_S5PC100 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE def_bool y diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index b7c2d377a6c2..dfcf3b033e10 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -180,7 +180,7 @@ machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0 machine-$(CONFIG_ARCH_S5PC100) := s5pc100 machine-$(CONFIG_ARCH_S5PV210) := s5pv210 -machine-$(CONFIG_ARCH_EXYNOS4) := exynos4 +machine-$(CONFIG_ARCH_EXYNOS4) := exynos machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHMOBILE) := shmobile diff --git a/trunk/arch/arm/configs/exynos4_defconfig b/trunk/arch/arm/configs/exynos4_defconfig index cd40bb56e568..bffe68e190a3 100644 --- a/trunk/arch/arm/configs/exynos4_defconfig +++ b/trunk/arch/arm/configs/exynos4_defconfig @@ -4,19 +4,18 @@ CONFIG_KALLSYMS_ALL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_EXYNOS4=y +CONFIG_ARCH_EXYNOS=y CONFIG_S3C_LOWLEVEL_UART_PORT=1 CONFIG_MACH_SMDKC210=y -CONFIG_MACH_SMDKV310=y CONFIG_MACH_ARMLEX4210=y CONFIG_MACH_UNIVERSAL_C210=y CONFIG_MACH_NURI=y CONFIG_MACH_ORIGEN=y +CONFIG_MACH_SMDK4412=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_SMP=y CONFIG_NR_CPUS=2 -CONFIG_HOTPLUG_CPU=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" @@ -61,13 +60,9 @@ CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y -CONFIG_DEBUG_S3C_UART=1 CONFIG_CRC_CCITT=y diff --git a/trunk/arch/arm/include/asm/hardware/pl080.h b/trunk/arch/arm/include/asm/hardware/pl080.h index e4a04e4e5627..33c78d7af2e1 100644 --- a/trunk/arch/arm/include/asm/hardware/pl080.h +++ b/trunk/arch/arm/include/asm/hardware/pl080.h @@ -21,6 +21,9 @@ * OneNAND features. */ +#ifndef ASM_PL080_H +#define ASM_PL080_H + #define PL080_INT_STATUS (0x00) #define PL080_TC_STATUS (0x04) #define PL080_TC_CLEAR (0x08) @@ -138,3 +141,4 @@ struct pl080s_lli { u32 control1; }; +#endif /* ASM_PL080_H */ diff --git a/trunk/arch/arm/mach-davinci/include/mach/gpio.h b/trunk/arch/arm/mach-davinci/include/mach/gpio.h index fbaae4772b91..960e9de47e1e 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/gpio.h +++ b/trunk/arch/arm/mach-davinci/include/mach/gpio.h @@ -15,6 +15,8 @@ #include +#define __ARM_GPIOLIB_COMPLEX + /* The inline versions use the static inlines in the driver header */ #include "gpio-davinci.h" diff --git a/trunk/arch/arm/mach-exynos4/Kconfig b/trunk/arch/arm/mach-exynos/Kconfig similarity index 75% rename from trunk/arch/arm/mach-exynos4/Kconfig rename to trunk/arch/arm/mach-exynos/Kconfig index a65273598036..724ec0f3560d 100644 --- a/trunk/arch/arm/mach-exynos4/Kconfig +++ b/trunk/arch/arm/mach-exynos/Kconfig @@ -1,4 +1,4 @@ -# arch/arm/mach-exynos4/Kconfig +# arch/arm/mach-exynos/Kconfig # # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. # http://www.samsung.com/ @@ -7,22 +7,47 @@ # Configuration options for the EXYNOS4 -if ARCH_EXYNOS4 +if ARCH_EXYNOS + +menu "SAMSUNG EXYNOS SoCs Support" + +choice + prompt "EXYNOS System Type" + default ARCH_EXYNOS4 + +config ARCH_EXYNOS4 + bool "SAMSUNG EXYNOS4" + help + Samsung EXYNOS4 SoCs based systems + +endchoice + +comment "EXYNOS SoCs" config CPU_EXYNOS4210 - bool - select S3C_PL330_DMA + bool "SAMSUNG EXYNOS4210" + default y + depends on ARCH_EXYNOS4 + select SAMSUNG_DMADEV select ARM_CPU_SUSPEND if PM + select S5P_PM if PM + select S5P_SLEEP if PM help Enable EXYNOS4210 CPU support config SOC_EXYNOS4212 - bool + bool "SAMSUNG EXYNOS4212" + default y + depends on ARCH_EXYNOS4 + select S5P_PM if PM + select S5P_SLEEP if PM help Enable EXYNOS4212 SoC support config SOC_EXYNOS4412 - bool + bool "SAMSUNG EXYNOS4412" + default y + depends on ARCH_EXYNOS4 help Enable EXYNOS4412 SoC support @@ -120,7 +145,7 @@ config EXYNOS4_SETUP_USB_PHY # machine support -menu "EXYNOS4 Machines" +if ARCH_EXYNOS4 comment "EXYNOS4210 Boards" @@ -137,6 +162,14 @@ config MACH_SMDKV310 select S3C_DEV_RTC select S3C_DEV_WDT select S3C_DEV_I2C1 + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_FIMC3 + select S5P_DEV_I2C_HDMIPHY + select S5P_DEV_MFC + select S5P_DEV_TV + select S5P_DEV_USB_EHCI select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 @@ -151,6 +184,7 @@ config MACH_SMDKV310 select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_KEYPAD select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY help Machine support for Samsung SMDKV310 @@ -176,19 +210,26 @@ config MACH_UNIVERSAL_C210 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 select S5P_DEV_FIMC3 + select S5P_DEV_CSIS0 + select S5P_DEV_FIMD0 select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 select S3C_DEV_I2C1 select S3C_DEV_I2C3 select S3C_DEV_I2C5 + select S5P_DEV_I2C_HDMIPHY select S5P_DEV_MFC select S5P_DEV_ONENAND + select S5P_DEV_TV select EXYNOS4_DEV_PD + select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C3 select EXYNOS4_SETUP_I2C5 select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_FIMC + select S5P_SETUP_MIPIPHY help Machine support for Samsung Mobile Universal S5PC210 Reference Board. @@ -196,21 +237,33 @@ config MACH_UNIVERSAL_C210 config MACH_NURI bool "Mobile NURI Board" select CPU_EXYNOS4210 + select S5P_GPIO_INT select S3C_DEV_WDT + select S3C_DEV_RTC + select S5P_DEV_FIMD0 select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 select S3C_DEV_I2C1 select S3C_DEV_I2C3 select S3C_DEV_I2C5 + select S5P_DEV_CSIS0 + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_FIMC3 select S5P_DEV_MFC select S5P_DEV_USB_EHCI + select S5P_SETUP_MIPIPHY select EXYNOS4_DEV_PD + select EXYNOS4_SETUP_FIMC + select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C3 select EXYNOS4_SETUP_I2C5 select EXYNOS4_SETUP_SDHCI select EXYNOS4_SETUP_USB_PHY + select S5P_SETUP_MIPIPHY select SAMSUNG_DEV_PWM select SAMSUNG_DEV_ADC help @@ -221,8 +274,23 @@ config MACH_ORIGEN select CPU_EXYNOS4210 select S3C_DEV_RTC select S3C_DEV_WDT + select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_FIMC3 + select S5P_DEV_FIMD0 + select S5P_DEV_I2C_HDMIPHY + select S5P_DEV_MFC + select S5P_DEV_TV + select S5P_DEV_USB_EHCI + select SAMSUNG_DEV_BACKLIGHT + select SAMSUNG_DEV_PWM + select EXYNOS4_DEV_PD + select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY help Machine support for ORIGEN based on Samsung EXYNOS4210 @@ -257,12 +325,11 @@ config MACH_SMDK4412 select MACH_SMDK4212 help Machine support for Samsung SMDK4412 +endif -endmenu - -comment "Configuration for HSMMC bus width" +if ARCH_EXYNOS4 -menu "Use 8-bit bus width" +comment "Configuration for HSMMC 8-bit bus width" config EXYNOS4_SDHCI_CH0_8BIT bool "Channel 0 with 8-bit bus" @@ -275,6 +342,7 @@ config EXYNOS4_SDHCI_CH2_8BIT help Support HSMMC Channel 2 8-bit bus. If selected, Channel 3 is disabled. +endif endmenu diff --git a/trunk/arch/arm/mach-exynos4/Makefile b/trunk/arch/arm/mach-exynos/Makefile similarity index 88% rename from trunk/arch/arm/mach-exynos4/Makefile rename to trunk/arch/arm/mach-exynos/Makefile index c9b2e1f97e44..59069a35e40b 100644 --- a/trunk/arch/arm/mach-exynos4/Makefile +++ b/trunk/arch/arm/mach-exynos/Makefile @@ -1,4 +1,4 @@ -# arch/arm/mach-exynos4/Makefile +# arch/arm/mach-exynos/Makefile # # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. # http://www.samsung.com/ @@ -12,11 +12,11 @@ obj- := # Core support for EXYNOS4 system -obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o -obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o +obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o +obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o dma.o pmu.o obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o -obj-$(CONFIG_PM) += pm.o sleep.o +obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o @@ -39,11 +39,11 @@ obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o # device support -obj-y += dev-audio.o +obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o -obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o +obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o @@ -57,5 +57,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o - obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o diff --git a/trunk/arch/arm/mach-exynos4/Makefile.boot b/trunk/arch/arm/mach-exynos/Makefile.boot similarity index 100% rename from trunk/arch/arm/mach-exynos4/Makefile.boot rename to trunk/arch/arm/mach-exynos/Makefile.boot diff --git a/trunk/arch/arm/mach-exynos4/clock-exynos4210.c b/trunk/arch/arm/mach-exynos/clock-exynos4210.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/clock-exynos4210.c rename to trunk/arch/arm/mach-exynos/clock-exynos4210.c diff --git a/trunk/arch/arm/mach-exynos4/clock-exynos4212.c b/trunk/arch/arm/mach-exynos/clock-exynos4212.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/clock-exynos4212.c rename to trunk/arch/arm/mach-exynos/clock-exynos4212.c diff --git a/trunk/arch/arm/mach-exynos4/clock.c b/trunk/arch/arm/mach-exynos/clock.c similarity index 86% rename from trunk/arch/arm/mach-exynos4/clock.c rename to trunk/arch/arm/mach-exynos/clock.c index 0d59be3fa1fe..2894f0adef5c 100644 --- a/trunk/arch/arm/mach-exynos4/clock.c +++ b/trunk/arch/arm/mach-exynos/clock.c @@ -111,6 +111,11 @@ struct clk clk_sclk_usbphy1 = { .name = "sclk_usbphy1", }; +static struct clk dummy_apb_pclk = { + .name = "apb_pclk", + .id = -1, +}; + static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); @@ -146,6 +151,11 @@ static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable); } +static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable); +} + static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); @@ -186,6 +196,16 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); } +static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); +} + +static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); +} + /* Core list of CMU_CPU side */ static struct clksrc_clk clk_mout_apll = { @@ -503,13 +523,43 @@ static struct clk init_clocks_off[] = { .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 9), }, { - .name = "pdma", - .devname = "s3c-pl330.0", + .name = "dac", + .devname = "s5p-sdo", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "mixer", + .devname = "s5p-mixer", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "vp", + .devname = "s5p-mixer", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "hdmi", + .devname = "exynos4-hdmi", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "hdmiphy", + .devname = "exynos4-hdmi", + .enable = exynos4_clk_hdmiphy_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "dacphy", + .devname = "s5p-sdo", + .enable = exynos4_clk_dac_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "dma", + .devname = "dma-pl330.0", .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 0), }, { - .name = "pdma", - .devname = "s3c-pl330.1", + .name = "dma", + .devname = "dma-pl330.1", .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 1), }, { @@ -629,6 +679,12 @@ static struct clk init_clocks_off[] = { .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 13), + }, { + .name = "i2c", + .devname = "s3c2440-hdmiphy-i2c", + .parent = &clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 14), }, { .name = "SYSMMU_MDMA", .enable = exynos4_clk_ip_image_ctrl, @@ -831,6 +887,81 @@ static struct clksrc_sources clkset_mout_mfc = { .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list), }; +static struct clk *clkset_sclk_dac_list[] = { + [0] = &clk_sclk_vpll.clk, + [1] = &clk_sclk_hdmiphy, +}; + +static struct clksrc_sources clkset_sclk_dac = { + .sources = clkset_sclk_dac_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), +}; + +static struct clksrc_clk clk_sclk_dac = { + .clk = { + .name = "sclk_dac", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_sclk_dac, + .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 }, +}; + +static struct clksrc_clk clk_sclk_pixel = { + .clk = { + .name = "sclk_pixel", + .parent = &clk_sclk_vpll.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 }, +}; + +static struct clk *clkset_sclk_hdmi_list[] = { + [0] = &clk_sclk_pixel.clk, + [1] = &clk_sclk_hdmiphy, +}; + +static struct clksrc_sources clkset_sclk_hdmi = { + .sources = clkset_sclk_hdmi_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), +}; + +static struct clksrc_clk clk_sclk_hdmi = { + .clk = { + .name = "sclk_hdmi", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_sclk_hdmi, + .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 }, +}; + +static struct clk *clkset_sclk_mixer_list[] = { + [0] = &clk_sclk_dac.clk, + [1] = &clk_sclk_hdmi.clk, +}; + +static struct clksrc_sources clkset_sclk_mixer = { + .sources = clkset_sclk_mixer_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), +}; + +static struct clksrc_clk clk_sclk_mixer = { + .clk = { + .name = "sclk_mixer", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &clkset_sclk_mixer, + .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk *sclk_tv[] = { + &clk_sclk_dac, + &clk_sclk_pixel, + &clk_sclk_hdmi, + &clk_sclk_mixer, +}; + static struct clksrc_clk clk_dout_mmc0 = { .clk = { .name = "dout_mmc0", @@ -1157,6 +1288,71 @@ static struct clk_ops exynos4_fout_apll_ops = { .get_rate = exynos4_fout_apll_get_rate, }; +static u32 vpll_div[][8] = { + { 54000000, 3, 53, 3, 1024, 0, 17, 0 }, + { 108000000, 3, 53, 2, 1024, 0, 17, 0 }, +}; + +static unsigned long exynos4_vpll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int vpll_con0, vpll_con1 = 0; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + vpll_con0 = __raw_readl(S5P_VPLL_CON0); + vpll_con0 &= ~(0x1 << 27 | \ + PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ + PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ + PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + + vpll_con1 = __raw_readl(S5P_VPLL_CON1); + vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \ + PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \ + PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(vpll_div); i++) { + if (vpll_div[i][0] == rate) { + vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT; + vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT; + vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT; + vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT; + vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT; + vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT; + vpll_con0 |= vpll_div[i][7] << 27; + break; + } + } + + if (i == ARRAY_SIZE(vpll_div)) { + printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(vpll_con0, S5P_VPLL_CON0); + __raw_writel(vpll_con1, S5P_VPLL_CON1); + + /* Wait for VPLL lock */ + while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) + continue; + + clk->rate = rate; + return 0; +} + +static struct clk_ops exynos4_vpll_ops = { + .get_rate = exynos4_vpll_get_rate, + .set_rate = exynos4_vpll_set_rate, +}; + void __init_or_cpufreq exynos4_setup_clocks(void) { struct clk *xtal_clk; @@ -1214,6 +1410,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; + clk_fout_vpll.ops = &exynos4_vpll_ops; clk_fout_vpll.rate = vpll; printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", @@ -1241,7 +1438,10 @@ void __init_or_cpufreq exynos4_setup_clocks(void) } static struct clk *clks[] __initdata = { - /* Nothing here yet */ + &clk_sclk_hdmi27m, + &clk_sclk_hdmiphy, + &clk_sclk_usbphy0, + &clk_sclk_usbphy1, }; #ifdef CONFIG_PM_SLEEP @@ -1275,6 +1475,9 @@ void __init exynos4_register_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) s3c_register_clksrc(sysclks[ptr], 1); + for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) + s3c_register_clksrc(sclk_tv[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); @@ -1282,5 +1485,7 @@ void __init exynos4_register_clocks(void) s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); register_syscore_ops(&exynos4_clock_syscore_ops); + s3c24xx_register_clock(&dummy_apb_pclk); + s3c_pwmclk_init(); } diff --git a/trunk/arch/arm/mach-exynos4/cpu.c b/trunk/arch/arm/mach-exynos/cpu.c similarity index 90% rename from trunk/arch/arm/mach-exynos4/cpu.c rename to trunk/arch/arm/mach-exynos/cpu.c index a348434f17b5..90ec247f3b37 100644 --- a/trunk/arch/arm/mach-exynos4/cpu.c +++ b/trunk/arch/arm/mach-exynos/cpu.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-exynos4/cpu.c +/* linux/arch/arm/mach-exynos/cpu.c * * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -39,27 +40,46 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base, extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); /* Initial IO mappings */ -static struct map_desc exynos4_iodesc[] __initdata = { +static struct map_desc exynos_iodesc[] __initdata = { { .virtual = (unsigned long)S5P_VA_SYSTIMER, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER), + .pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER), .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_CMU, - .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), - .length = SZ_128K, .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_PMU, - .pfn = __phys_to_pfn(EXYNOS4_PA_PMU), + .pfn = __phys_to_pfn(EXYNOS_PA_PMU), .length = SZ_64K, .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_COMBINER_BASE, - .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), + .pfn = __phys_to_pfn(EXYNOS_PA_COMBINER), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GIC_CPU, + .pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GIC_DIST, + .pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_UART, + .pfn = __phys_to_pfn(S3C_PA_UART), + .length = SZ_512K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc exynos4_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_CMU, + .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), + .length = SZ_128K, + .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_COREPERI_BASE, .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI), @@ -90,11 +110,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), .length = SZ_4K, .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_UART, - .pfn = __phys_to_pfn(S3C_PA_UART), - .length = SZ_512K, - .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_SROMC, .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), @@ -105,16 +120,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), .length = SZ_4K, .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GIC_CPU, - .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GIC_DIST, - .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), - .length = SZ_64K, - .type = MT_DEVICE, }, }; @@ -136,7 +141,7 @@ static struct map_desc exynos4_iodesc1[] __initdata = { }, }; -static void exynos4_idle(void) +static void exynos_idle(void) { if (!need_resched()) cpu_do_idle(); @@ -150,12 +155,13 @@ static void exynos4_sw_reset(void) } /* - * exynos4_map_io + * exynos_map_io * * register the standard cpu IO areas */ void __init exynos4_map_io(void) { + iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc)); iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) @@ -182,6 +188,7 @@ void __init exynos4_map_io(void) s3c_i2c2_setname("s3c2440-i2c"); s5p_fb_setname(0, "exynos4-fb"); + s5p_hdmi_setname("exynos4-hdmi"); } void __init exynos4_init_clocks(int xtal) @@ -248,7 +255,6 @@ static int __init exynos4_core_init(void) { return sysdev_class_register(&exynos4_sysclass); } - core_initcall(exynos4_core_init); #ifdef CONFIG_CACHE_L2X0 @@ -277,15 +283,16 @@ static int __init exynos4_l2x0_cache_init(void) early_initcall(exynos4_l2x0_cache_init); #endif -int __init exynos4_init(void) +int __init exynos_init(void) { - printk(KERN_INFO "EXYNOS4: Initializing architecture\n"); + printk(KERN_INFO "EXYNOS: Initializing architecture\n"); /* set idle function */ - pm_idle = exynos4_idle; + pm_idle = exynos_idle; /* set sw_reset function */ - s5p_reset_hook = exynos4_sw_reset; + if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412()) + s5p_reset_hook = exynos4_sw_reset; return sysdev_register(&exynos4_sysdev); } diff --git a/trunk/arch/arm/mach-exynos4/cpuidle.c b/trunk/arch/arm/mach-exynos/cpuidle.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/cpuidle.c rename to trunk/arch/arm/mach-exynos/cpuidle.c diff --git a/trunk/arch/arm/mach-exynos4/dev-ahci.c b/trunk/arch/arm/mach-exynos/dev-ahci.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/dev-ahci.c rename to trunk/arch/arm/mach-exynos/dev-ahci.c diff --git a/trunk/arch/arm/mach-exynos4/dev-audio.c b/trunk/arch/arm/mach-exynos/dev-audio.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/dev-audio.c rename to trunk/arch/arm/mach-exynos/dev-audio.c diff --git a/trunk/arch/arm/mach-exynos4/dev-dwmci.c b/trunk/arch/arm/mach-exynos/dev-dwmci.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/dev-dwmci.c rename to trunk/arch/arm/mach-exynos/dev-dwmci.c diff --git a/trunk/arch/arm/mach-exynos4/dev-pd.c b/trunk/arch/arm/mach-exynos/dev-pd.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/dev-pd.c rename to trunk/arch/arm/mach-exynos/dev-pd.c diff --git a/trunk/arch/arm/mach-exynos4/dev-sysmmu.c b/trunk/arch/arm/mach-exynos/dev-sysmmu.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/dev-sysmmu.c rename to trunk/arch/arm/mach-exynos/dev-sysmmu.c diff --git a/trunk/arch/arm/mach-exynos/dma.c b/trunk/arch/arm/mach-exynos/dma.c new file mode 100644 index 000000000000..9667c61e64fb --- /dev/null +++ b/trunk/arch/arm/mach-exynos/dma.c @@ -0,0 +1,250 @@ +/* linux/arch/arm/mach-exynos4/dma.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +static u64 dma_dmamask = DMA_BIT_MASK(32); + +struct dma_pl330_peri pdma0_peri[28] = { + { + .peri_id = (u8)DMACH_PCM0_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_PCM0_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_PCM2_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_PCM2_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_MSM_REQ0, + }, { + .peri_id = (u8)DMACH_MSM_REQ2, + }, { + .peri_id = (u8)DMACH_SPI0_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_SPI0_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_SPI2_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_SPI2_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_I2S0S_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_I2S0_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_I2S0_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_UART0_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_UART0_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_UART2_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_UART2_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_UART4_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_UART4_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_SLIMBUS0_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_SLIMBUS0_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_SLIMBUS2_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_SLIMBUS2_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_SLIMBUS4_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_SLIMBUS4_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_AC97_MICIN, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_AC97_PCMIN, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_AC97_PCMOUT, + .rqtype = MEMTODEV, + }, +}; + +struct dma_pl330_platdata exynos4_pdma0_pdata = { + .nr_valid_peri = ARRAY_SIZE(pdma0_peri), + .peri = pdma0_peri, +}; + +struct amba_device exynos4_device_pdma0 = { + .dev = { + .init_name = "dma-pl330.0", + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &exynos4_pdma0_pdata, + }, + .res = { + .start = EXYNOS4_PA_PDMA0, + .end = EXYNOS4_PA_PDMA0 + SZ_4K, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_PDMA0, NO_IRQ}, + .periphid = 0x00041330, +}; + +struct dma_pl330_peri pdma1_peri[25] = { + { + .peri_id = (u8)DMACH_PCM0_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_PCM0_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_PCM1_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_PCM1_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_MSM_REQ1, + }, { + .peri_id = (u8)DMACH_MSM_REQ3, + }, { + .peri_id = (u8)DMACH_SPI1_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_SPI1_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_I2S0S_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_I2S0_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_I2S0_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_I2S1_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_I2S1_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_UART0_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_UART0_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_UART1_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_UART1_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_UART3_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_UART3_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_SLIMBUS1_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_SLIMBUS1_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_SLIMBUS3_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_SLIMBUS3_TX, + .rqtype = MEMTODEV, + }, { + .peri_id = (u8)DMACH_SLIMBUS5_RX, + .rqtype = DEVTOMEM, + }, { + .peri_id = (u8)DMACH_SLIMBUS5_TX, + .rqtype = MEMTODEV, + }, +}; + +struct dma_pl330_platdata exynos4_pdma1_pdata = { + .nr_valid_peri = ARRAY_SIZE(pdma1_peri), + .peri = pdma1_peri, +}; + +struct amba_device exynos4_device_pdma1 = { + .dev = { + .init_name = "dma-pl330.1", + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &exynos4_pdma1_pdata, + }, + .res = { + .start = EXYNOS4_PA_PDMA1, + .end = EXYNOS4_PA_PDMA1 + SZ_4K, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_PDMA1, NO_IRQ}, + .periphid = 0x00041330, +}; + +static int __init exynos4_dma_init(void) +{ + amba_device_register(&exynos4_device_pdma0, &iomem_resource); + amba_device_register(&exynos4_device_pdma1, &iomem_resource); + + return 0; +} +arch_initcall(exynos4_dma_init); diff --git a/trunk/arch/arm/mach-exynos4/headsmp.S b/trunk/arch/arm/mach-exynos/headsmp.S similarity index 100% rename from trunk/arch/arm/mach-exynos4/headsmp.S rename to trunk/arch/arm/mach-exynos/headsmp.S diff --git a/trunk/arch/arm/mach-exynos4/hotplug.c b/trunk/arch/arm/mach-exynos/hotplug.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/hotplug.c rename to trunk/arch/arm/mach-exynos/hotplug.c diff --git a/trunk/arch/arm/mach-exynos4/include/mach/debug-macro.S b/trunk/arch/arm/mach-exynos/include/mach/debug-macro.S similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/debug-macro.S rename to trunk/arch/arm/mach-exynos/include/mach/debug-macro.S diff --git a/trunk/arch/arm/mach-exynos4/include/mach/dma.h b/trunk/arch/arm/mach-exynos/include/mach/dma.h similarity index 90% rename from trunk/arch/arm/mach-exynos4/include/mach/dma.h rename to trunk/arch/arm/mach-exynos/include/mach/dma.h index 81209eb1409b..201842a3769e 100644 --- a/trunk/arch/arm/mach-exynos4/include/mach/dma.h +++ b/trunk/arch/arm/mach-exynos/include/mach/dma.h @@ -20,7 +20,7 @@ #ifndef __MACH_DMA_H #define __MACH_DMA_H -/* This platform uses the common S3C DMA API driver for PL330 */ -#include +/* This platform uses the common DMA API driver for PL330 */ +#include #endif /* __MACH_DMA_H */ diff --git a/trunk/arch/arm/mach-exynos4/include/mach/dwmci.h b/trunk/arch/arm/mach-exynos/include/mach/dwmci.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/dwmci.h rename to trunk/arch/arm/mach-exynos/include/mach/dwmci.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/entry-macro.S b/trunk/arch/arm/mach-exynos/include/mach/entry-macro.S similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/entry-macro.S rename to trunk/arch/arm/mach-exynos/include/mach/entry-macro.S diff --git a/trunk/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/trunk/arch/arm/mach-exynos/include/mach/exynos4-clock.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/exynos4-clock.h rename to trunk/arch/arm/mach-exynos/include/mach/exynos4-clock.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/gpio.h b/trunk/arch/arm/mach-exynos/include/mach/gpio.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/gpio.h rename to trunk/arch/arm/mach-exynos/include/mach/gpio.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/hardware.h b/trunk/arch/arm/mach-exynos/include/mach/hardware.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/hardware.h rename to trunk/arch/arm/mach-exynos/include/mach/hardware.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/io.h b/trunk/arch/arm/mach-exynos/include/mach/io.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/io.h rename to trunk/arch/arm/mach-exynos/include/mach/io.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/irqs.h b/trunk/arch/arm/mach-exynos/include/mach/irqs.h similarity index 97% rename from trunk/arch/arm/mach-exynos4/include/mach/irqs.h rename to trunk/arch/arm/mach-exynos/include/mach/irqs.h index 2d3f6bcd9bc0..dfd4b7eecb90 100644 --- a/trunk/arch/arm/mach-exynos4/include/mach/irqs.h +++ b/trunk/arch/arm/mach-exynos/include/mach/irqs.h @@ -95,7 +95,11 @@ #define IRQ_2D IRQ_SPI(89) #define IRQ_PCIE IRQ_SPI(90) +#define IRQ_MIXER IRQ_SPI(91) +#define IRQ_HDMI IRQ_SPI(92) +#define IRQ_IIC_HDMIPHY IRQ_SPI(93) #define IRQ_MFC IRQ_SPI(94) +#define IRQ_SDO IRQ_SPI(95) #define IRQ_AUDIO_SS IRQ_SPI(96) #define IRQ_I2S0 IRQ_SPI(97) diff --git a/trunk/arch/arm/mach-exynos4/include/mach/map.h b/trunk/arch/arm/mach-exynos/include/mach/map.h similarity index 87% rename from trunk/arch/arm/mach-exynos4/include/mach/map.h rename to trunk/arch/arm/mach-exynos/include/mach/map.h index 9f97eb8499ee..058541d45af0 100644 --- a/trunk/arch/arm/mach-exynos4/include/mach/map.h +++ b/trunk/arch/arm/mach-exynos/include/mach/map.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-exynos4/include/mach/map.h +/* linux/arch/arm/mach-exynos/include/mach/map.h * * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -112,6 +112,12 @@ #define EXYNOS4_PA_UART 0x13800000 +#define EXYNOS4_PA_VP 0x12C00000 +#define EXYNOS4_PA_MIXER 0x12C10000 +#define EXYNOS4_PA_SDO 0x12C20000 +#define EXYNOS4_PA_HDMI 0x12D00000 +#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 + #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) #define EXYNOS4_PA_ADC 0x13910000 @@ -139,33 +145,45 @@ #define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) #define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) -#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC -#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 #define S3C_PA_RTC EXYNOS4_PA_RTC #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG +#define S3C_PA_UART EXYNOS4_PA_UART #define S5P_PA_CHIPID EXYNOS4_PA_CHIPID +#define S5P_PA_EHCI EXYNOS4_PA_EHCI #define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 #define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 #define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2 #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 +#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 +#define S5P_PA_HDMI EXYNOS4_PA_HDMI +#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY +#define S5P_PA_MFC EXYNOS4_PA_MFC #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 -#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 +#define S5P_PA_MIXER EXYNOS4_PA_MIXER #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA +#define S5P_PA_SDO EXYNOS4_PA_SDO #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM #define S5P_PA_SROMC EXYNOS4_PA_SROMC -#define S5P_PA_MFC EXYNOS4_PA_MFC #define S5P_PA_SYSCON EXYNOS4_PA_SYSCON #define S5P_PA_TIMER EXYNOS4_PA_TIMER -#define S5P_PA_EHCI EXYNOS4_PA_EHCI +#define S5P_PA_VP EXYNOS4_PA_VP +#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC +#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 #define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD -/* UART */ +#define EXYNOS_PA_COMBINER EXYNOS4_PA_COMBINER +#define EXYNOS_PA_GIC_CPU EXYNOS4_PA_GIC_CPU +#define EXYNOS_PA_GIC_DIST EXYNOS4_PA_GIC_DIST +#define EXYNOS_PA_PMU EXYNOS4_PA_PMU +#define EXYNOS_PA_SYSTIMER EXYNOS4_PA_SYSTIMER -#define S3C_PA_UART EXYNOS4_PA_UART +/* Compatibility UART */ + +#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) #define S5P_PA_UART0 S5P_PA_UART(0) diff --git a/trunk/arch/arm/mach-exynos4/include/mach/memory.h b/trunk/arch/arm/mach-exynos/include/mach/memory.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/memory.h rename to trunk/arch/arm/mach-exynos/include/mach/memory.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/pm-core.h b/trunk/arch/arm/mach-exynos/include/mach/pm-core.h similarity index 89% rename from trunk/arch/arm/mach-exynos4/include/mach/pm-core.h rename to trunk/arch/arm/mach-exynos/include/mach/pm-core.h index 1df3b81f96e8..9d8da51e35ca 100644 --- a/trunk/arch/arm/mach-exynos4/include/mach/pm-core.h +++ b/trunk/arch/arm/mach-exynos/include/mach/pm-core.h @@ -14,6 +14,10 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ + +#ifndef __ASM_ARCH_PM_CORE_H +#define __ASM_ARCH_PM_CORE_H __FILE__ + #include static inline void s3c_pm_debug_init_uart(void) @@ -53,7 +57,9 @@ static inline void s3c_pm_restored_gpios(void) /* nothing here yet */ } -static inline void s3c_pm_saved_gpios(void) +static inline void samsung_pm_saved_gpios(void) { /* nothing here yet */ } + +#endif /* __ASM_ARCH_PM_CORE_H */ diff --git a/trunk/arch/arm/mach-exynos4/include/mach/pmu.h b/trunk/arch/arm/mach-exynos/include/mach/pmu.h similarity index 84% rename from trunk/arch/arm/mach-exynos4/include/mach/pmu.h rename to trunk/arch/arm/mach-exynos/include/mach/pmu.h index a952904b010e..632dd5630138 100644 --- a/trunk/arch/arm/mach-exynos4/include/mach/pmu.h +++ b/trunk/arch/arm/mach-exynos/include/mach/pmu.h @@ -13,6 +13,8 @@ #ifndef __ASM_ARCH_PMU_H #define __ASM_ARCH_PMU_H __FILE__ +#define PMU_TABLE_END NULL + enum sys_powerdown { SYS_AFTR, SYS_LPA, @@ -20,6 +22,11 @@ enum sys_powerdown { NUM_SYS_POWERDOWN, }; +struct exynos4_pmu_conf { + void __iomem *reg; + unsigned int val[NUM_SYS_POWERDOWN]; +}; + extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode); #endif /* __ASM_ARCH_PMU_H */ diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-audss.h b/trunk/arch/arm/mach-exynos/include/mach/regs-audss.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/regs-audss.h rename to trunk/arch/arm/mach-exynos/include/mach/regs-audss.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-clock.h b/trunk/arch/arm/mach-exynos/include/mach/regs-clock.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/regs-clock.h rename to trunk/arch/arm/mach-exynos/include/mach/regs-clock.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-gpio.h b/trunk/arch/arm/mach-exynos/include/mach/regs-gpio.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/regs-gpio.h rename to trunk/arch/arm/mach-exynos/include/mach/regs-gpio.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-irq.h b/trunk/arch/arm/mach-exynos/include/mach/regs-irq.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/regs-irq.h rename to trunk/arch/arm/mach-exynos/include/mach/regs-irq.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-mct.h b/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/regs-mct.h rename to trunk/arch/arm/mach-exynos/include/mach/regs-mct.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-mem.h b/trunk/arch/arm/mach-exynos/include/mach/regs-mem.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/regs-mem.h rename to trunk/arch/arm/mach-exynos/include/mach/regs-mem.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/trunk/arch/arm/mach-exynos/include/mach/regs-pmu.h similarity index 69% rename from trunk/arch/arm/mach-exynos4/include/mach/regs-pmu.h rename to trunk/arch/arm/mach-exynos/include/mach/regs-pmu.h index cdf9b47c303c..4fff8e938fec 100644 --- a/trunk/arch/arm/mach-exynos4/include/mach/regs-pmu.h +++ b/trunk/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -25,9 +25,10 @@ #define S5P_USE_STANDBY_WFI0 (1 << 16) #define S5P_USE_STANDBY_WFI1 (1 << 17) +#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18) #define S5P_USE_STANDBY_WFE0 (1 << 24) #define S5P_USE_STANDBY_WFE1 (1 << 25) -#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24)) +#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) #define S5P_SWRESET S5P_PMUREG(0x0400) @@ -35,15 +36,17 @@ #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) -#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) -#define S5P_USBHOST_PHY_ENABLE (1 << 0) +#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700) +#define S5P_HDMI_PHY_ENABLE (1 << 0) + +#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C) +#define S5P_DAC_PHY_ENABLE (1 << 0) #define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) #define S5P_MIPI_DPHY_ENABLE (1 << 0) #define S5P_MIPI_DPHY_SRESETN (1 << 1) #define S5P_MIPI_DPHY_MRESETN (1 << 2) -#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) #define S5P_INFORM0 S5P_PMUREG(0x0800) #define S5P_INFORM1 S5P_PMUREG(0x0804) #define S5P_INFORM2 S5P_PMUREG(0x0808) @@ -76,7 +79,6 @@ #define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) #define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) #define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) -#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) #define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) #define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) @@ -84,7 +86,6 @@ #define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) #define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) #define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) -#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) #define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) #define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) #define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) @@ -92,14 +93,11 @@ #define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) #define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) #define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) -#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) #define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) #define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) #define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) #define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) #define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) -#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) -#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) #define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) #define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) #define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) @@ -120,7 +118,6 @@ #define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) #define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) #define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) -#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) #define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) @@ -156,7 +153,6 @@ #define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) #define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) #define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) -#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) #define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 @@ -165,4 +161,60 @@ #define S5P_CHECK_SLEEP 0x00000BAD +/* Only for EXYNOS4210 */ +#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) +#define S5P_USBHOST_PHY_ENABLE (1 << 0) + +#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) + +#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) +#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) +#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) +#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) +#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) +#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) + +#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) + +/* Only for EXYNOS4212 */ +#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) +#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) +#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) +#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110) +#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114) +#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C) +#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130) +#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154) +#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174) +#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190) +#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194) +#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198) +#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4) +#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0) +#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4) +#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4) +#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC) +#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C) +#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250) +#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320) +#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344) +#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348) +#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394) +#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0) +#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4) +#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8) +#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC) +#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0) + +#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608) +#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628) +#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08) +#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28) +#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48) +#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68) +#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88) +#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8) +#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) +#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) + #endif /* __ASM_ARCH_REGS_PMU_H */ diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h b/trunk/arch/arm/mach-exynos/include/mach/regs-sysmmu.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h rename to trunk/arch/arm/mach-exynos/include/mach/regs-sysmmu.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h b/trunk/arch/arm/mach-exynos/include/mach/regs-usb-phy.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h rename to trunk/arch/arm/mach-exynos/include/mach/regs-usb-phy.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/sysmmu.h b/trunk/arch/arm/mach-exynos/include/mach/sysmmu.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/sysmmu.h rename to trunk/arch/arm/mach-exynos/include/mach/sysmmu.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/system.h b/trunk/arch/arm/mach-exynos/include/mach/system.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/system.h rename to trunk/arch/arm/mach-exynos/include/mach/system.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/timex.h b/trunk/arch/arm/mach-exynos/include/mach/timex.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/timex.h rename to trunk/arch/arm/mach-exynos/include/mach/timex.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/uncompress.h b/trunk/arch/arm/mach-exynos/include/mach/uncompress.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/uncompress.h rename to trunk/arch/arm/mach-exynos/include/mach/uncompress.h diff --git a/trunk/arch/arm/mach-exynos4/include/mach/vmalloc.h b/trunk/arch/arm/mach-exynos/include/mach/vmalloc.h similarity index 100% rename from trunk/arch/arm/mach-exynos4/include/mach/vmalloc.h rename to trunk/arch/arm/mach-exynos/include/mach/vmalloc.h diff --git a/trunk/arch/arm/mach-exynos4/init.c b/trunk/arch/arm/mach-exynos/init.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/init.c rename to trunk/arch/arm/mach-exynos/init.c diff --git a/trunk/arch/arm/mach-exynos4/irq-combiner.c b/trunk/arch/arm/mach-exynos/irq-combiner.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/irq-combiner.c rename to trunk/arch/arm/mach-exynos/irq-combiner.c diff --git a/trunk/arch/arm/mach-exynos4/irq-eint.c b/trunk/arch/arm/mach-exynos/irq-eint.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/irq-eint.c rename to trunk/arch/arm/mach-exynos/irq-eint.c diff --git a/trunk/arch/arm/mach-exynos4/mach-armlex4210.c b/trunk/arch/arm/mach-exynos/mach-armlex4210.c similarity index 100% rename from trunk/arch/arm/mach-exynos4/mach-armlex4210.c rename to trunk/arch/arm/mach-exynos/mach-armlex4210.c diff --git a/trunk/arch/arm/mach-exynos4/mach-nuri.c b/trunk/arch/arm/mach-exynos/mach-nuri.c similarity index 85% rename from trunk/arch/arm/mach-exynos4/mach-nuri.c rename to trunk/arch/arm/mach-exynos/mach-nuri.c index 6e0536818bf5..236bbe187163 100644 --- a/trunk/arch/arm/mach-exynos4/mach-nuri.c +++ b/trunk/arch/arm/mach-exynos/mach-nuri.c @@ -27,15 +27,20 @@ #include #include