From 22d33fc8bbf9e791988df008450bdd361a43edda Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu, 28 Oct 2010 23:43:30 +0100
Subject: [PATCH] --- yaml --- r: 228667 b: refs/heads/master c:
 872d860c85e30cdc97e7c91723257f4fcf04d5e9 h: refs/heads/master i:   228665:
 941c3417b36792eb7bf1443a5cdb12d0bd870903   228663:
 5f05c36c165cf21dc404eeba0da448ea29324316 v: v3

---
 [refs]                                | 2 +-
 trunk/drivers/gpu/drm/i915/i915_gem.c | 6 ------
 2 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/[refs] b/[refs]
index 472f314d4ae4..77a4171b53e6 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a00b10c360b35d6431a94cbf130a4e162870d661
+refs/heads/master: 872d860c85e30cdc97e7c91723257f4fcf04d5e9
diff --git a/trunk/drivers/gpu/drm/i915/i915_gem.c b/trunk/drivers/gpu/drm/i915/i915_gem.c
index 07ad1e354084..936ddd83f8a2 100644
--- a/trunk/drivers/gpu/drm/i915/i915_gem.c
+++ b/trunk/drivers/gpu/drm/i915/i915_gem.c
@@ -2847,22 +2847,16 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
 				       bool pipelined)
 {
 	struct drm_device *dev = obj->dev;
-	uint32_t old_write_domain;
 
 	if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
 		return 0;
 
 	/* Queue the GPU write cache flushing we need. */
-	old_write_domain = obj->write_domain;
 	i915_gem_flush_ring(dev, NULL,
 			    to_intel_bo(obj)->ring,
 			    0, obj->write_domain);
 	BUG_ON(obj->write_domain);
 
-	trace_i915_gem_object_change_domain(obj,
-					    obj->read_domains,
-					    old_write_domain);
-
 	if (pipelined)
 		return 0;