From 231a63262ea4a21bf3ddc73e3bb37fa94ed353bc Mon Sep 17 00:00:00 2001 From: Hartley Sweeten Date: Tue, 23 Feb 2010 21:20:31 +0100 Subject: [PATCH] --- yaml --- r: 182965 b: refs/heads/master c: ba7c6a3bccd25abd3c19d3655ecb1cc4d258271b h: refs/heads/master i: 182963: 17c20c31ff22f7b9af756ef1d1562bfeed6844f3 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-ep93xx/clock.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 9b184aae4aac..ab39e9798c7e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6bd4b382664d188daed8a48f7df88d188dcd95fa +refs/heads/master: ba7c6a3bccd25abd3c19d3655ecb1cc4d258271b diff --git a/trunk/arch/arm/mach-ep93xx/clock.c b/trunk/arch/arm/mach-ep93xx/clock.c index 27e335131799..49fa9f8fef4a 100644 --- a/trunk/arch/arm/mach-ep93xx/clock.c +++ b/trunk/arch/arm/mach-ep93xx/clock.c @@ -463,7 +463,7 @@ static int __init ep93xx_clock_init(void) ep93xx_dma_clock_init(); /* Determine the bootloader configured pll2 rate */ - value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); + value = __raw_readl(EP93XX_SYSCON_CLKSET2); if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) clk_pll2.rate = clk_xtali.rate; else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)