From 238515a65003fccab04bfa8f6a55a13bb79a5cdc Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 26 Mar 2008 22:42:55 +1100
Subject: [PATCH] --- yaml --- r: 91475 b: refs/heads/master c:
 99d8be052e248e09abf51d4a656717259bf9b930 h: refs/heads/master i:   91473:
 e00dc4b2d12bc99a484b1bd548b5447ea664e8d3   91471:
 b787a61fe02e16e4034863f0a62329597115d41a v: v3

---
 [refs]                                  |  2 +-
 trunk/arch/powerpc/boot/dts/taishan.dts | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 0c99381fb8e1..b4d6f584cb21 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 2a7069190e7a7f19bd37e8c08e2bf02c8d6330f7
+refs/heads/master: 99d8be052e248e09abf51d4a656717259bf9b930
diff --git a/trunk/arch/powerpc/boot/dts/taishan.dts b/trunk/arch/powerpc/boot/dts/taishan.dts
index 3d0334cec55c..96d033d6c05e 100644
--- a/trunk/arch/powerpc/boot/dts/taishan.dts
+++ b/trunk/arch/powerpc/boot/dts/taishan.dts
@@ -104,6 +104,16 @@
 		// FIXME: anything else?
 	};
 
+	L2C0: l2c {
+		compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
+		dcr-reg = <20 8			/* Internal SRAM DCR's */
+			   30 8>;		/* L2 cache DCR's */
+		cache-line-size = <20>;		/* 32 bytes */
+		cache-size = <40000>;		/* L2, 256K */
+		interrupt-parent = <&UIC2>;
+		interrupts = <17 1>;
+	};
+
 	plb {
 		compatible = "ibm,plb-440gx", "ibm,plb4";
 		#address-cells = <2>;