From 23b63c1c5aae62454a13b5b518ab2d91a42a8ac8 Mon Sep 17 00:00:00 2001 From: Avi Kivity Date: Thu, 14 Jun 2007 16:27:40 +0300 Subject: [PATCH] --- yaml --- r: 57785 b: refs/heads/master c: 7702fd1f6fea57921f2e643d27a23a2d0394499c h: refs/heads/master i: 57783: 45445402c4a887f67d06f244e0e9f142199e3d4c v: v3 --- [refs] | 2 +- trunk/arch/avr32/boards/atstk1000/atstk1002.c | 1 - trunk/arch/avr32/mm/fault.c | 2 +- trunk/arch/mips/kernel/smp-mt.c | 12 +- trunk/arch/mips/kernel/time.c | 44 ++----- trunk/arch/mips/mips-boards/generic/init.c | 62 +++------- trunk/arch/mips/mips-boards/generic/pci.c | 20 +-- trunk/arch/mips/mips-boards/generic/time.c | 115 ++++-------------- trunk/arch/mips/mips-boards/malta/malta_int.c | 42 ++++--- .../arch/mips/mips-boards/malta/malta_setup.c | 4 +- trunk/arch/mips/oprofile/op_model_mipsxx.c | 7 +- trunk/arch/powerpc/kernel/udbg.c | 8 +- trunk/arch/powerpc/platforms/powermac/setup.c | 13 +- trunk/arch/powerpc/platforms/powermac/smp.c | 1 + trunk/block/ll_rw_blk.c | 9 -- trunk/drivers/kvm/kvm.h | 3 + trunk/drivers/kvm/kvm_main.c | 22 ++++ trunk/drivers/kvm/vmx.c | 12 +- trunk/include/asm-avr32/arch-at32ap/gpio.h | 2 - trunk/include/asm-avr32/cache.h | 9 -- trunk/include/asm-mips/mips-boards/generic.h | 22 +--- .../include/asm-mips/mips-boards/msc01_pci.h | 1 - 22 files changed, 140 insertions(+), 273 deletions(-) diff --git a/[refs] b/[refs] index 60e91d917032..082958970a6f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4ff4275b24fdcca189b33f9a73fe7abef1dc84bc +refs/heads/master: 7702fd1f6fea57921f2e643d27a23a2d0394499c diff --git a/trunk/arch/avr32/boards/atstk1000/atstk1002.c b/trunk/arch/avr32/boards/atstk1000/atstk1002.c index e253e86a1a39..fe1dbe2e28f4 100644 --- a/trunk/arch/avr32/boards/atstk1000/atstk1002.c +++ b/trunk/arch/avr32/boards/atstk1000/atstk1002.c @@ -42,7 +42,6 @@ static struct spi_board_info spi0_board_info[] __initdata = { .modalias = "ltv350qv", .max_speed_hz = 16000000, .chip_select = 1, - .mode = SPI_MODE_3, }, }; diff --git a/trunk/arch/avr32/mm/fault.c b/trunk/arch/avr32/mm/fault.c index 4b2495285d94..e011f1ce1875 100644 --- a/trunk/arch/avr32/mm/fault.c +++ b/trunk/arch/avr32/mm/fault.c @@ -158,7 +158,7 @@ asmlinkage void do_page_fault(unsigned long ecr, struct pt_regs *regs) up_read(&mm->mmap_sem); if (user_mode(regs)) { - if (exception_trace && printk_ratelimit()) + if (exception_trace) printk("%s%s[%d]: segfault at %08lx pc %08lx " "sp %08lx ecr %lu\n", is_init(tsk) ? KERN_EMERG : KERN_INFO, diff --git a/trunk/arch/mips/kernel/smp-mt.c b/trunk/arch/mips/kernel/smp-mt.c index b8fa7ddd78f6..64b62bdfb4f6 100644 --- a/trunk/arch/mips/kernel/smp-mt.c +++ b/trunk/arch/mips/kernel/smp-mt.c @@ -129,13 +129,13 @@ static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) static struct irqaction irq_resched = { .handler = ipi_resched_interrupt, - .flags = IRQF_DISABLED|IRQF_PERCPU, + .flags = IRQF_DISABLED, .name = "IPI_resched" }; static struct irqaction irq_call = { .handler = ipi_call_interrupt, - .flags = IRQF_DISABLED|IRQF_PERCPU, + .flags = IRQF_DISABLED, .name = "IPI_call" }; @@ -275,7 +275,10 @@ void __init plat_prepare_cpus(unsigned int max_cpus) setup_irq(cpu_ipi_resched_irq, &irq_resched); setup_irq(cpu_ipi_call_irq, &irq_call); + /* need to mark IPI's as IRQ_PER_CPU */ + irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); + irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); } @@ -323,11 +326,8 @@ void prom_boot_secondary(int cpu, struct task_struct *idle) void prom_init_secondary(void) { - /* Enable per-cpu interrupts */ - - /* This is Malta specific: IPI,performance and timer inetrrupts */ write_c0_status((read_c0_status() & ~ST0_IM ) | - (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7)); + (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7)); } void prom_smp_finish(void) diff --git a/trunk/arch/mips/kernel/time.c b/trunk/arch/mips/kernel/time.c index 7def1ff3da94..751b4a18b133 100644 --- a/trunk/arch/mips/kernel/time.c +++ b/trunk/arch/mips/kernel/time.c @@ -199,30 +199,6 @@ int (*perf_irq)(void) = null_perf_irq; EXPORT_SYMBOL(null_perf_irq); EXPORT_SYMBOL(perf_irq); -/* - * Performance counter IRQ or -1 if shared with timer - */ -int mipsxx_perfcount_irq; -EXPORT_SYMBOL(mipsxx_perfcount_irq); - -/* - * Possibly handle a performance counter interrupt. - * Return true if the timer interrupt should not be checked - */ -static inline int handle_perf_irq (int r2) -{ - /* - * The performance counter overflow interrupt may be shared with the - * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a - * performance counter has overflowed (perf_irq() == IRQ_HANDLED) - * and we can't reliably determine if a counter interrupt has also - * happened (!r2) then don't check for a timer interrupt. - */ - return (mipsxx_perfcount_irq < 0) && - perf_irq() == IRQ_HANDLED && - !r2; -} - asmlinkage void ll_timer_interrupt(int irq) { int r2 = cpu_has_mips_r2; @@ -230,13 +206,19 @@ asmlinkage void ll_timer_interrupt(int irq) irq_enter(); kstat_this_cpu.irqs[irq]++; - if (handle_perf_irq(r2)) - goto out; - - if (r2 && ((read_c0_cause() & (1 << 30)) == 0)) - goto out; + /* + * Suckage alert: + * Before R2 of the architecture there was no way to see if a + * performance counter interrupt was pending, so we have to run the + * performance counter interrupt handler anyway. + */ + if (!r2 || (read_c0_cause() & (1 << 26))) + if (perf_irq()) + goto out; - timer_interrupt(irq, NULL); + /* we keep interrupt disabled all the time */ + if (!r2 || (read_c0_cause() & (1 << 30))) + timer_interrupt(irq, NULL); out: irq_exit(); @@ -276,7 +258,7 @@ unsigned int mips_hpt_frequency; static struct irqaction timer_irqaction = { .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_DISABLED, .name = "timer", }; diff --git a/trunk/arch/mips/mips-boards/generic/init.c b/trunk/arch/mips/mips-boards/generic/init.c index 4eabc1eadd23..88e9c2a7a2f9 100644 --- a/trunk/arch/mips/mips-boards/generic/init.c +++ b/trunk/arch/mips/mips-boards/generic/init.c @@ -57,8 +57,7 @@ int *_prom_argv, *_prom_envp; int init_debug = 0; -int mips_revision_corid; -int mips_revision_sconid; +unsigned int mips_revision_corid; /* Bonito64 system controller register base. */ unsigned long _pcictrl_bonito; @@ -276,38 +275,13 @@ void __init prom_init(void) else mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; } - - mips_revision_sconid = MIPS_REVISION_SCONID; - if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { - switch (mips_revision_corid) { - case MIPS_REVISION_CORID_QED_RM5261: - case MIPS_REVISION_CORID_CORE_LV: - case MIPS_REVISION_CORID_CORE_FPGA: - case MIPS_REVISION_CORID_CORE_FPGAR2: - mips_revision_sconid = MIPS_REVISION_SCON_GT64120; - break; - case MIPS_REVISION_CORID_CORE_EMUL_BON: - case MIPS_REVISION_CORID_BONITO64: - case MIPS_REVISION_CORID_CORE_20K: - mips_revision_sconid = MIPS_REVISION_SCON_BONITO; - break; - case MIPS_REVISION_CORID_CORE_MSC: - case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_FPGA3: - case MIPS_REVISION_CORID_CORE_24K: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: - mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; - break; - default: - mips_display_message("CC Error"); - while (1); /* We die here... */ - } - } - - switch (mips_revision_sconid) { + switch(mips_revision_corid) { u32 start, map, mask, data; - case MIPS_REVISION_SCON_GT64120: + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_FPGAR2: /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. @@ -331,7 +305,9 @@ void __init prom_init(void) set_io_port_base(MALTA_GT_PORT_BASE); break; - case MIPS_REVISION_SCON_BONITO: + case MIPS_REVISION_CORID_CORE_EMUL_BON: + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); /* @@ -358,10 +334,13 @@ void __init prom_init(void) set_io_port_base(MALTA_BONITO_PORT_BASE); break; - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); - mips_pci_controller: + mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); @@ -395,15 +374,10 @@ void __init prom_init(void) set_io_port_base(MALTA_MSC_PORT_BASE); break; - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); - goto mips_pci_controller; - default: - /* Unknown system controller */ - mips_display_message("SC Error"); - while (1); /* We die here... */ + /* Unknown Core card */ + mips_display_message("CC Error"); + while(1); /* We die here... */ } #endif board_nmi_handler_setup = mips_nmi_setup; diff --git a/trunk/arch/mips/mips-boards/generic/pci.c b/trunk/arch/mips/mips-boards/generic/pci.c index c9852206890a..f98d60f78658 100644 --- a/trunk/arch/mips/mips-boards/generic/pci.c +++ b/trunk/arch/mips/mips-boards/generic/pci.c @@ -92,8 +92,11 @@ void __init mips_pcibios_init(void) struct pci_controller *controller; resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_GT64120: + switch (mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_FPGAR2: /* * Due to a bug in the Galileo system controller, we need * to setup the PCI BAR for the Galileo internal registers. @@ -158,7 +161,9 @@ void __init mips_pcibios_init(void) controller = >64120_controller; break; - case MIPS_REVISION_SCON_BONITO: + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + case MIPS_REVISION_CORID_CORE_EMUL_BON: /* Set up resource ranges from the controller's registers. */ map = BONITO_PCIMAP; map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> @@ -190,10 +195,11 @@ void __init mips_pcibios_init(void) controller = &bonito64_controller; break; - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: /* Set up resource ranges from the controller's registers. */ MSC_READ(MSC01_PCI_SC2PMBASL, start); MSC_READ(MSC01_PCI_SC2PMMSKL, mask); diff --git a/trunk/arch/mips/mips-boards/generic/time.c b/trunk/arch/mips/mips-boards/generic/time.c index 8f1000f51b3d..b41db9e7ab1f 100644 --- a/trunk/arch/mips/mips-boards/generic/time.c +++ b/trunk/arch/mips/mips-boards/generic/time.c @@ -53,8 +53,9 @@ unsigned long cpu_khz; +#define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR) + static int mips_cpu_timer_irq; -extern int mipsxx_perfcount_irq; extern void smtc_timer_broadcast(int); static void mips_timer_dispatch(void) @@ -62,11 +63,6 @@ static void mips_timer_dispatch(void) do_IRQ(mips_cpu_timer_irq); } -static void mips_perf_dispatch(void) -{ - do_IRQ(mipsxx_perfcount_irq); -} - /* * Redeclare until I get around mopping the timer code insanity on MIPS. */ @@ -74,24 +70,6 @@ extern int null_perf_irq(void); extern int (*perf_irq)(void); -/* - * Possibly handle a performance counter interrupt. - * Return true if the timer interrupt should not be checked - */ -static inline int handle_perf_irq (int r2) -{ - /* - * The performance counter overflow interrupt may be shared with the - * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a - * performance counter has overflowed (perf_irq() == IRQ_HANDLED) - * and we can't reliably determine if a counter interrupt has also - * happened (!r2) then don't check for a timer interrupt. - */ - return (mipsxx_perfcount_irq < 0) && - perf_irq() == IRQ_HANDLED && - !r2; -} - irqreturn_t mips_timer_interrupt(int irq, void *dev_id) { int cpu = smp_processor_id(); @@ -114,7 +92,8 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) * We could be here due to timer interrupt, * perf counter overflow, or both. */ - (void) handle_perf_irq(1); + if (read_c0_cause() & (1 << 26)) + perf_irq(); if (read_c0_cause() & (1 << 30)) { /* @@ -136,19 +115,19 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) #else /* CONFIG_MIPS_MT_SMTC */ int r2 = cpu_has_mips_r2; - if (handle_perf_irq(r2)) - goto out; - - if (r2 && ((read_c0_cause() & (1 << 30)) == 0)) - goto out; - if (cpu == 0) { /* * CPU 0 handles the global timer interrupt job and process * accounting resets count/compare registers to trigger next * timer int. */ - timer_interrupt(irq, NULL); + if (!r2 || (read_c0_cause() & (1 << 26))) + if (perf_irq()) + goto out; + + /* we keep interrupt disabled all the time */ + if (!r2 || (read_c0_cause() & (1 << 30))) + timer_interrupt(irq, NULL); } else { /* Everyone else needs to reset the timer int here as ll_local_timer_interrupt doesn't */ @@ -246,85 +225,35 @@ void __init mips_time_init(void) mips_scroll_message(); } -irqreturn_t mips_perf_interrupt(int irq, void *dev_id) -{ - return perf_irq(); -} - -static struct irqaction perf_irqaction = { - .handler = mips_perf_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, - .name = "performance", -}; - -void __init plat_perf_setup(struct irqaction *irq) -{ - int hwint = 0; - mipsxx_perfcount_irq = -1; - -#ifdef MSC01E_INT_BASE - if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); - mipsxx_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; - } else -#endif - if (cpu_has_mips_r2) { - /* - * Read IntCtl.IPPCI to determine the performance - * counter interrupt - */ - hwint = (read_c0_intctl () >> 26) & 7; - if (hwint != MIPSCPU_INT_CPUCTR) { - if (cpu_has_vint) - set_vi_handler (hwint, mips_perf_dispatch); - mipsxx_perfcount_irq = MIPSCPU_INT_BASE + hwint; - } - } - if (mipsxx_perfcount_irq >= 0) { -#ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(mipsxx_perfcount_irq, irq, 0x100 << hwint); -#else - setup_irq(mipsxx_perfcount_irq, irq); -#endif /* CONFIG_MIPS_MT_SMTC */ -#ifdef CONFIG_SMP - set_irq_handler(mipsxx_perfcount_irq, handle_percpu_irq); -#endif - } -} - void __init plat_timer_setup(struct irqaction *irq) { - int hwint = 0; #ifdef MSC01E_INT_BASE if (cpu_has_veic) { set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; - } - else + } else #endif { - if (cpu_has_mips_r2) - /* - * Read IntCtl.IPTI to determine the timer interrupt - */ - hwint = (read_c0_intctl () >> 29) & 7; - else - hwint = MIPSCPU_INT_CPUCTR; if (cpu_has_vint) - set_vi_handler (hwint, mips_timer_dispatch); - mips_cpu_timer_irq = MIPSCPU_INT_BASE + hwint; + set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; } + /* we are using the cpu counter for timer interrupts */ irq->handler = mips_timer_interrupt; /* we use our own handler */ #ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << hwint); + setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT); #else setup_irq(mips_cpu_timer_irq, irq); #endif /* CONFIG_MIPS_MT_SMTC */ + #ifdef CONFIG_SMP + /* irq_desc(riptor) is a global resource, when the interrupt overlaps + on seperate cpu's the first one tries to handle the second interrupt. + The effect is that the int remains disabled on the second cpu. + Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ + irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif - - plat_perf_setup(&perf_irqaction); } diff --git a/trunk/arch/mips/mips-boards/malta/malta_int.c b/trunk/arch/mips/mips-boards/malta/malta_int.c index 1668cc21d5b5..1cd830e3d933 100644 --- a/trunk/arch/mips/mips-boards/malta/malta_int.c +++ b/trunk/arch/mips/mips-boards/malta/malta_int.c @@ -53,19 +53,25 @@ static inline int mips_pcibios_iack(void) * Determine highest priority pending interrupt by performing * a PCI Interrupt Acknowledge cycle. */ - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: + switch(mips_revision_corid) { + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: MSC_READ(MSC01_PCI_IACK, irq); irq &= 0xff; break; - case MIPS_REVISION_SCON_GT64120: + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_FPGAR2: irq = GT_READ(GT_PCI0_IACK_OFS); irq &= 0xff; break; - case MIPS_REVISION_SCON_BONITO: + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + case MIPS_REVISION_CORID_CORE_EMUL_BON: /* The following will generate a PCI IACK cycle on the * Bonito controller. It's a little bit kludgy, but it * was the easiest way to implement it in hardware at @@ -83,7 +89,7 @@ static inline int mips_pcibios_iack(void) BONITO_PCIMAP_CFG = 0; break; default: - printk("Unknown system controller.\n"); + printk("Unknown Core card, don't know the system controller.\n"); return -1; } return irq; @@ -138,21 +144,27 @@ static void corehi_irqdispatch(void) Do it for the others too. */ - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: + switch(mips_revision_corid) { + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: ll_msc_irq(); break; - case MIPS_REVISION_SCON_GT64120: + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_FPGAR2: intrcause = GT_READ(GT_INTRCAUSE_OFS); datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); printk("GT_INTRCAUSE = %08x\n", intrcause); printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo); break; - case MIPS_REVISION_SCON_BONITO: + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + case MIPS_REVISION_CORID_CORE_EMUL_BON: pcibadaddr = BONITO_PCIBADADDR; pcimstat = BONITO_PCIMSTAT; intisr = BONITO_INTISR; diff --git a/trunk/arch/mips/mips-boards/malta/malta_setup.c b/trunk/arch/mips/mips-boards/malta/malta_setup.c index 8f1b78dfd89f..c14b7bf89950 100644 --- a/trunk/arch/mips/mips-boards/malta/malta_setup.c +++ b/trunk/arch/mips/mips-boards/malta/malta_setup.c @@ -103,7 +103,9 @@ void __init plat_mem_setup(void) kgdb_config (); #endif - if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) || + (mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) || + (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) { char *argptr; argptr = prom_getcmdline(); diff --git a/trunk/arch/mips/oprofile/op_model_mipsxx.c b/trunk/arch/mips/oprofile/op_model_mipsxx.c index 1ea5c9c1010b..4f94fa261aae 100644 --- a/trunk/arch/mips/oprofile/op_model_mipsxx.c +++ b/trunk/arch/mips/oprofile/op_model_mipsxx.c @@ -177,10 +177,7 @@ static int mipsxx_perfcount_handler(void) unsigned int counters = op_model_mipsxx_ops.num_counters; unsigned int control; unsigned int counter; - int handled = IRQ_NONE; - - if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) - return handled; + int handled = 0; switch (counters) { #define HANDLE_COUNTER(n) \ @@ -191,7 +188,7 @@ static int mipsxx_perfcount_handler(void) (counter & M_COUNTER_OVERFLOW)) { \ oprofile_add_sample(get_irq_regs(), n); \ w_c0_perfcntr ## n(reg.counter[n]); \ - handled = IRQ_HANDLED; \ + handled = 1; \ } HANDLE_COUNTER(3) HANDLE_COUNTER(2) diff --git a/trunk/arch/powerpc/kernel/udbg.c b/trunk/arch/powerpc/kernel/udbg.c index cbca1df8bc60..87703df87509 100644 --- a/trunk/arch/powerpc/kernel/udbg.c +++ b/trunk/arch/powerpc/kernel/udbg.c @@ -151,18 +151,12 @@ static struct console udbg_console = { static int early_console_initialized; -/* - * Called by setup_system after ppc_md->probe and ppc_md->early_init. - * Call it again after setting udbg_putc in ppc_md->setup_arch. - */ +/* called by setup_system */ void register_early_udbg_console(void) { if (early_console_initialized) return; - if (!udbg_putc) - return; - if (strstr(boot_command_line, "udbg-immortal")) { printk(KERN_INFO "early console immortal !\n"); udbg_console.flags &= ~CON_BOOT; diff --git a/trunk/arch/powerpc/platforms/powermac/setup.c b/trunk/arch/powerpc/platforms/powermac/setup.c index 956571526a57..07b1c4ec428d 100644 --- a/trunk/arch/powerpc/platforms/powermac/setup.c +++ b/trunk/arch/powerpc/platforms/powermac/setup.c @@ -363,19 +363,8 @@ static void __init pmac_setup_arch(void) smp_ops = &core99_smp_ops; } #ifdef CONFIG_PPC32 - else { - /* - * We have to set bits in cpu_possible_map here since the - * secondary CPU(s) aren't in the device tree, and - * setup_per_cpu_areas only allocates per-cpu data for - * CPUs in the cpu_possible_map. - */ - int cpu; - - for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) - cpu_set(cpu, cpu_possible_map); + else smp_ops = &psurge_smp_ops; - } #endif #endif /* CONFIG_SMP */ diff --git a/trunk/arch/powerpc/platforms/powermac/smp.c b/trunk/arch/powerpc/platforms/powermac/smp.c index cb2d894541c6..686ed82bde79 100644 --- a/trunk/arch/powerpc/platforms/powermac/smp.c +++ b/trunk/arch/powerpc/platforms/powermac/smp.c @@ -317,6 +317,7 @@ static int __init smp_psurge_probe(void) ncpus = NR_CPUS; for (i = 1; i < ncpus ; ++i) { cpu_set(i, cpu_present_map); + cpu_set(i, cpu_possible_map); set_hard_smp_processor_id(i, i); } diff --git a/trunk/block/ll_rw_blk.c b/trunk/block/ll_rw_blk.c index c99b46354859..6b5173ac8131 100644 --- a/trunk/block/ll_rw_blk.c +++ b/trunk/block/ll_rw_blk.c @@ -340,15 +340,6 @@ unsigned blk_ordered_req_seq(struct request *rq) if (rq == &q->post_flush_rq) return QUEUE_ORDSEQ_POSTFLUSH; - /* - * !fs requests don't need to follow barrier ordering. Always - * put them at the front. This fixes the following deadlock. - * - * http://thread.gmane.org/gmane.linux.kernel/537473 - */ - if (!blk_fs_request(rq)) - return QUEUE_ORDSEQ_DRAIN; - if ((rq->cmd_flags & REQ_ORDERED_COLOR) == (q->orig_bar_rq->cmd_flags & REQ_ORDERED_COLOR)) return QUEUE_ORDSEQ_DRAIN; diff --git a/trunk/drivers/kvm/kvm.h b/trunk/drivers/kvm/kvm.h index 1c040d80c641..152312c1fafa 100644 --- a/trunk/drivers/kvm/kvm.h +++ b/trunk/drivers/kvm/kvm.h @@ -304,6 +304,7 @@ struct kvm_vcpu { char *host_fx_image; char *guest_fx_image; int fpu_active; + int guest_fpu_loaded; int mmio_needed; int mmio_read_completed; @@ -508,6 +509,8 @@ void fx_init(struct kvm_vcpu *vcpu); void load_msrs(struct vmx_msr_entry *e, int n); void save_msrs(struct vmx_msr_entry *e, int n); void kvm_resched(struct kvm_vcpu *vcpu); +void kvm_load_guest_fpu(struct kvm_vcpu *vcpu); +void kvm_put_guest_fpu(struct kvm_vcpu *vcpu); int kvm_read_guest(struct kvm_vcpu *vcpu, gva_t addr, diff --git a/trunk/drivers/kvm/kvm_main.c b/trunk/drivers/kvm/kvm_main.c index da985b31b17e..8f1f07adb04e 100644 --- a/trunk/drivers/kvm/kvm_main.c +++ b/trunk/drivers/kvm/kvm_main.c @@ -253,6 +253,28 @@ int kvm_write_guest(struct kvm_vcpu *vcpu, gva_t addr, unsigned long size, } EXPORT_SYMBOL_GPL(kvm_write_guest); +void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) +{ + if (!vcpu->fpu_active || vcpu->guest_fpu_loaded) + return; + + vcpu->guest_fpu_loaded = 1; + fx_save(vcpu->host_fx_image); + fx_restore(vcpu->guest_fx_image); +} +EXPORT_SYMBOL_GPL(kvm_load_guest_fpu); + +void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) +{ + if (!vcpu->guest_fpu_loaded) + return; + + vcpu->guest_fpu_loaded = 0; + fx_save(vcpu->guest_fx_image); + fx_restore(vcpu->host_fx_image); +} +EXPORT_SYMBOL_GPL(kvm_put_guest_fpu); + /* * Switches to specified vcpu, until a matching vcpu_put() */ diff --git a/trunk/drivers/kvm/vmx.c b/trunk/drivers/kvm/vmx.c index 184238e2ece4..c1ac106ace8c 100644 --- a/trunk/drivers/kvm/vmx.c +++ b/trunk/drivers/kvm/vmx.c @@ -280,6 +280,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu) static void vmx_vcpu_put(struct kvm_vcpu *vcpu) { + kvm_put_guest_fpu(vcpu); put_cpu(); } @@ -1847,10 +1848,8 @@ static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) if (vcpu->guest_debug.enabled) kvm_guest_debug_pre(vcpu); - if (vcpu->fpu_active) { - fx_save(vcpu->host_fx_image); - fx_restore(vcpu->guest_fx_image); - } + kvm_load_guest_fpu(vcpu); + /* * Loading guest fpu may have cleared host cr0.ts */ @@ -2012,11 +2011,6 @@ static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) } #endif - if (vcpu->fpu_active) { - fx_save(vcpu->guest_fx_image); - fx_restore(vcpu->host_fx_image); - } - vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0; asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); diff --git a/trunk/include/asm-avr32/arch-at32ap/gpio.h b/trunk/include/asm-avr32/arch-at32ap/gpio.h index af7f9535bab3..80a21aa9ae77 100644 --- a/trunk/include/asm-avr32/arch-at32ap/gpio.h +++ b/trunk/include/asm-avr32/arch-at32ap/gpio.h @@ -14,8 +14,6 @@ int gpio_direction_output(unsigned int gpio, int value); int gpio_get_value(unsigned int gpio); void gpio_set_value(unsigned int gpio, int value); -#include /* cansleep wrappers */ - static inline int gpio_to_irq(unsigned int gpio) { return gpio + GPIO_IRQ_BASE; diff --git a/trunk/include/asm-avr32/cache.h b/trunk/include/asm-avr32/cache.h index d3cf35ab11ab..dabb955f3c00 100644 --- a/trunk/include/asm-avr32/cache.h +++ b/trunk/include/asm-avr32/cache.h @@ -4,15 +4,6 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -/* - * Memory returned by kmalloc() may be used for DMA, so we must make - * sure that all such allocations are cache aligned. Otherwise, - * unrelated code may cause parts of the buffer to be read into the - * cache before the transfer is done, causing old data to be seen by - * the CPU. - */ -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES - #ifndef __ASSEMBLER__ struct cache_info { unsigned int ways; diff --git a/trunk/include/asm-mips/mips-boards/generic.h b/trunk/include/asm-mips/mips-boards/generic.h index c8ebcc3e1267..b98f1658cfd0 100644 --- a/trunk/include/asm-mips/mips-boards/generic.h +++ b/trunk/include/asm-mips/mips-boards/generic.h @@ -73,28 +73,12 @@ * CoreEMUL with Bonito System Controller is treated like a Core20K * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC */ -#define MIPS_REVISION_CORID_CORE_EMUL_BON -1 -#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 +#define MIPS_REVISION_CORID_CORE_EMUL_BON 0x63 +#define MIPS_REVISION_CORID_CORE_EMUL_MSC 0x65 #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) -extern int mips_revision_corid; - -#define MIPS_REVISION_SCON_OTHER 0 -#define MIPS_REVISION_SCON_SOCITSC 1 -#define MIPS_REVISION_SCON_SOCITSCP 2 - -/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ -#define MIPS_REVISION_SCON_UNKNOWN -1 -#define MIPS_REVISION_SCON_GT64120 -2 -#define MIPS_REVISION_SCON_BONITO -3 -#define MIPS_REVISION_SCON_BRTL -4 -#define MIPS_REVISION_SCON_SOCIT -5 -#define MIPS_REVISION_SCON_ROCIT -6 - -#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) - -extern int mips_revision_sconid; +extern unsigned int mips_revision_corid; #ifdef CONFIG_PCI extern void mips_pcibios_init(void); diff --git a/trunk/include/asm-mips/mips-boards/msc01_pci.h b/trunk/include/asm-mips/mips-boards/msc01_pci.h index e036b7dd6deb..8eaefb837b9d 100644 --- a/trunk/include/asm-mips/mips-boards/msc01_pci.h +++ b/trunk/include/asm-mips/mips-boards/msc01_pci.h @@ -208,7 +208,6 @@ * latter, they should be moved elsewhere. */ #define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 -#define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000 extern unsigned long _pcictrl_msc;